Tianocore/edk2-platforms.git, branch master

Silicon/QualcommSiliconPkg: Add Qualcomm SMEM Library

2026-09-02T23:48:11+00:00

Add Qualcomm SMEM lib implementation. Signed-off-by: gparikh

Platform/RaspberryPi: Fix mailbox tag struct alignment for GET_MAC_ADDRESS

2026-08-31T16:09:59+00:00

The mailbox property interface expects every tag's value buffer to be padded to a 32-bit boundary so the following tags and the end tag stay aligned. Commit 61708392042b ("RPiFirmwareDxe: Fix and consolidate incorrect pragma pack blocks") wrapped every mailbox tag struct in a module-wide #pragma pack(1). RPI_FW_MAC_ADDR_TAG then no longer rounds up to a multiple of 4: the packed tag is 10 bytes (6-byte MAC address + 4-byte "UINT32 Padding"), which leaves the trailing end tag misaligned. Recent VideoCore firmware rejects such a request with a 0x80000001 partial response, so RpiFirmwareGetMacAddress () fails and callers fall back to an all-zero MAC address. None of these tag structs actually need packing - they are all built from UINT32 fields and are laid out identically packed or not. The sole exception was RPI_FW_SERIAL_TAG's UINT64, which would otherwise be padded to an 8-byte boundary inside the tag body. Drop the #pragma pack block entirely, express the serial as UINT32[2] (read back with CopyMem) and remove the now-unneeded RPI_FW_MAC_ADDR_TAG padding member; the enclosing command struct's natural alignment keeps the end tag aligned. Signed-off-by: valtzu

SimicsOpenBoardPkg/BoardBdsHookLib: Add BDS enhancements for QSP

2026-08-26T06:42:20+00:00

Refactor BoardBdsHookLib to use SimicsUefiDeviceLib and add: - Video mode selection from simics-uefi device before boot handoff - Boot device priority from simics-uefi device config string - Boot option sorting (USB=4, DVD=5, HDD=6, PXE=7, HTTP=8, Shell=150) - USB HID keyboard device path registration in ConIn/ConInDev - "Press ESC to enter BIOS menu" on serial and graphics consoles Update BoardBootManager progress bar text to match. Signed-off-by: Robert Guenzel

SimicsOpenBoardPkg/MinPlatformAcpiTables: Add ACPI table override

2026-08-26T06:42:20+00:00

Simics scenarios may need to inject custom DSDT/SSDT tables without rebuilding the entire BIOS image. No mechanism exists to replace individual ACPI tables at boot time. Add ACPI table override support to AcpiPlatform that uses the SimicsUefiDeviceLib to collect ACPI Tables to add or override. Signed-off-by: Robert Guenzel

SimicsOpenBoardPkg/SimicsVideoDxe: Report video modes to simics-uefi device

2026-08-26T06:42:20+00:00

Use SimicsUefiDeviceLib to detect the Simics UEFI PCI config device during Bochs video mode setup. When present, write each supported video mode (index, width, height, depth) to the device capabilities register so the simulator can offer mode selection to the user. Add a presence guard to prevent MMIO faults when the device is absent. Signed-off-by: Robert Guenzel

SimicsOpenBoardPkg: Add SimicsUefiDeviceLib

2026-08-26T06:42:20+00:00

The Simics QSP platform uses a hidden PCI config space device (simics-uefi device, VID/DID=0xFFFF, SubsysVID/ID=0x8086/0x8086) to exchange configuration data between the simulator and BIOS. The device detection logic was duplicated across multiple consumers. Add SimicsUefiDeviceLib, a shared DXE library that provides: - SimicsUefiDeviceCheck: probe device presence via PCI config reads - SimicsUefiDeviceRead: read from device register offset - SimicsUefiDeviceWrite: write to device register offset Declare PCI BDF and capabilities register base PCDs in OpenBoardPkg.dec and add the library class mapping in OpenBoardPkg.dsc. Signed-off-by: Robert Guenzel

SimicsOpenBoardPkg/Logo: Replace boot logo with Simics branding

2026-08-26T06:42:20+00:00

Replace the generic boot logo bitmap with Simics-branded artwork for visual identification of the QSP BIOS during boot. Co-authored-by: Claes Lillieskold Signed-off-by: Robert Guenzel

SimicsOpenBoardPkg: Add 64-bit PCI MMIO window and enable SR-IOV

2026-08-26T06:42:20+00:00

The Simics QSP platform requires 64-bit PCI MMIO resources for SR-IOV virtual function BARs. The existing DSDT lacks a resource descriptor above 4 GiB, MemDetect.c uses a legacy SeaBIOS heuristic for aperture sizing, and PciLib uses CF8-based I/O that cannot reach extended config space (offset >= 0x100) needed for SR-IOV capability structures. Add a QWORDMEMORY resource descriptor in Dsdt.asl covering 0x800000000 - 0x107FFFFFFFF (1 TiB) for PCI bridge resources above 4 GiB. Replace the 1 GiB alignment heuristic in MemDetect.c with CPUID-based physical address width detection. Fix the 64-bit aperture base at 0x800000000 and cap the size by the CPU's physical address limit. Switch PciLib from BasePciLibCf8 to BasePciLibPciExpress so config registers beyond offset 0x100 are reachable. Enable PcdSrIovSupport and disable PcdPciDegradeResourceForOptionRom to preserve 64-bit MMIO space for SR-IOV BARs. Signed-off-by: Robert Guenzel

SimicsOpenBoardPkg/SimicsPei: Probe for SATA controller before access

2026-08-26T06:42:20+00:00

On QSP configurations without a SATA controller, the unconditional PCI register access reads undefined values and may configure incorrect I/O and memory resources. Add an explicit PCI vendor/device ID check before accessing SATA controller registers during PEI platform initialization. Skip SATA resource configuration when the controller is not present. Signed-off-by: Robert Guenzel

SimicsOpenBoardPkg/PeiReportFvLib: Guard against unset FV PCDs

2026-08-26T06:42:20+00:00

SimicsOpenBoardPkg does not set several MinPlatformPkg FV PCDs (PcdFlashFvSecurityBase/Size, PcdFlashFvAdvancedBase/Size, and others), leaving them at their default value of 0. ReportPreMemFv() and ReportPostMemFv() unconditionally install FV Info PPIs for all of these, which triggers notify callbacks (e.g., Tcg2Pei) that attempt to process a bogus FV at address 0 with size 0, leading to undefined behavior. Add null guards to skip FV Info PPI installation when both the base address and size PCDs are zero. Signed-off-by: Robert Guenzel