Tianocore/edk2-platforms.git, branch McfgTableEDK II sample platform branches and tags (mirror)https://git.radix-linux.su/Tianocore/edk2-platforms.git/atom?h=McfgTable2024-07-18T08:11:17+00:00AmdPlatformPkg/DynamicTables: Creates ACPI MCFG table2024-07-18T08:11:17+00:00Abdul Lateef Attarabdattar@amd.com2024-07-15T03:39:00+00:00urn:sha1:8679b81990d289e456be70c58bff60eb9fc5183d
Creates ACPI MCFG table during boot time.
Adds a library to generate and install MCFG table.
Cc: Abner Chang <abner.chang@amd.com>
Cc: Paul Grimes <paul.grimes@amd.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
AmdPlatformPkg/DynamicTables: Create ACPI MADT/APIC table2024-07-18T08:06:57+00:00Abdul Lateef Attarabdattar@amd.com2024-07-12T03:50:34+00:00urn:sha1:b2a5655d7aee128786ab072a1e390ee90801db02
Creates MADT/APIC table during boot time.
Cc: Abner Chang <abner.chang@amd.com>
Cc: Paul Grimes <paul.grimes@amd.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
AmdPlatformPkg: Creates ACPI SSDT PCI toplogy2024-07-18T08:04:59+00:00Abdul Lateef Attarabdattar@amd.com2024-07-09T06:23:21+00:00urn:sha1:6544ae0d200a8ae8ea10e6a88d06620f86e3775e
Generates ACPI SSDT PCI topology.
Append the PCI SSDT tolology to the DSDT table.
Cc: Abner Chang <abner.chang@amd.com>
Cc: Paul Grimes <paul.grimes@amd.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
AmdPlatformPkg/DynamicTables: Creates ACPI SSDT CPU topology2024-07-18T08:04:59+00:00Abdul Lateef Attarabdattar@amd.com2024-07-09T06:19:13+00:00urn:sha1:ec26b5751fbbe365bfecb0e7f7631a0f8ba7a3bb
Create ACPI SSDT CPU toplogy.
Append the CPU SSDT topology to the DSDT table.
Cc: Abner Chang <abner.chang@amd.com>
Cc: Paul Grimes <paul.grimes@amd.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
Platform/Intel: Set PcdAcpiBaseAddress for PEI MM Communication2024-07-07T07:41:18+00:00Jiaxin Wujiaxin.wu@intel.com2024-06-22T06:06:17+00:00urn:sha1:ad553efc01125cad4ebdbe694b82cf6a59ce6a03
Set PcdAcpiBaseAddress to 0x400 for PEI MM communication.
Signed-off-by: Wei6 Xu <wei6.xu@intel.com>
Co-authored-by: Jiaxin Wu <jiaxin.wu@intel.com>
Platform/Intel: Install an SMM Control PPI2024-07-07T07:41:18+00:00Jiaxin Wujiaxin.wu@intel.com2024-07-05T04:41:36+00:00urn:sha1:1fe5d09d5d03571a071222bc7a9433743533d21c
Install an instance of EFI_PEI_MM_CONTROL_PPI.
This PPI provides a standard way for other modules to
trigger software SMIs.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Co-authored-by: Jiaxin Wu <jiaxin.wu@intel.com>
Platform/Intel: Add SmmControlLib lib2024-07-07T07:41:18+00:00Jiaxin Wujiaxin.wu@intel.com2024-07-05T04:40:29+00:00urn:sha1:f27e442852e594b23e5c058069b6d6f5d6d0bcd9
This patch is to add SmmControlLib.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Co-authored-by: Jiaxin Wu <jiaxin.wu@intel.com>
Platform/Intel: Consume SmmRelocationInit interface2024-07-05T14:28:32+00:00Jiaxin Wujiaxin.wu@intel.com2024-07-05T03:42:04+00:00urn:sha1:12f68d29abdc9d703f67bd743fdec23ebb1e966e
Do the smm relocation during platform init.
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Platform/Intel: Add SmmRelocationLib lib2024-07-05T14:28:32+00:00Jiaxin Wujiaxin.wu@intel.com2024-06-06T06:30:40+00:00urn:sha1:adfa5674b335dd4366b4d396b385caf3804c5eac
This patch is to add SmmRelocationLib for SMM CPU driver usage.
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
SbsaQemu: use FEAT_RNG for EFI_RNG_PROTOCOL2024-07-04T11:40:02+00:00Marcin Juszkiewiczmarcin.juszkiewicz@linaro.org2024-06-27T11:55:57+00:00urn:sha1:25d66c5b9e5cd672b6e2723d4308cd815639f880
By default we have Neoverse-N2 cpu which supports FEAT_RNG feature. This
allows us to add RngDxe to have EFI_RNG_PROTOCOL available on
Neoverse-N2 and 'max' cpu cores.
Commit 5de5e230a80bed083360da95ba16a2c4a001620d (in EDK2) enabled that for
ArmVirt platform.
RNDR is implemented by both Neoverse-N2 and 'max' cpu implemented by QEMU.
Other cpu models lack it which prevents the RngDxe driver from running,
resulting in the same situation as before.
TRNG is not implemented in TCG mode but is required by RngDxe to run.
On older cpu cores nothing changes.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>