MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: 1 Introduction

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
1 Introduction

1.1 Purpose

The purpose of this document is to describe the steps required to integrate the Intel® Firmware Support Package (FSP) into a boot loader solution. It supports MeteorLake platforms with MeteorLake processor and MeteorLake Platform Controller Hub (PCH).

1.2 Intended Audience

This document is targeted at all platform and system developers who need to consume FSP binaries in their boot loader solutions. This includes, but is not limited to: system BIOS developers, boot loader developers, system integrators, as well as end users.

1.3 Related Documents

  • Platform Initialization (PI) Specification v1.7 located at http://www.uefi.org/specifications
  • Intel® Firmware Support Package: External Architecture Specification (EAS) v2.1 located at https://cdrdv2.intel.com/v1/dl/getContent/611786
  • Boot Setting File Specification (BSF) v1.0 https://firmware.intel.com/sites/default/files/BSF_1_0.pdf
  • Binary Configuration Tool for Intel® Firmware Support Package available at http://www.intel.com/fsp

1.4 Acronyms and Terminology

Acronym | Definition
BCT | Binary Configuration Tool
BDSM | Base Data Of Stolen Memory
BSF | Boot Setting File
BSP | Boot Strap Processor
BWG | BIOS Writer's Guide
CAR | Cache As Ram
CRB | Customer Reference Board
DPR | DMA Protected Range
FIT | Firmware Interface Table
FSP | Firmware Support Package
FSP API | Firmware Support Package Interface
FW | Firmware
GTT | Graphics Translation Table
IED | Intel Enhanced Debug
IFWI | Integrated Firmware Image
IOT | Internal Observation Trace
MRC | Memory Reference Code (Memory Init code encapsulated by FSP-M)
MOT | Memory Observation Trace
PCH | Platform Controller Hub
PMC | Power Management Controller
PMRR | Protected Memory Range Reporting
REMAP | Remapped Memory Area
RVP | Reference and Validation Platform
SBSP | System BSP
SMI | System Management Interrupt
SMM | System Management Mode
SMRAM | System Management Mode RAM
SPI | Serial Peripheral Interface
TOLUD | Top of Low Usable Memory
TOUUD | Top of Upper Usable Memory
TSEG | Memory Reserved at the Top of Memory to be used as SMRAM
UPD | Updatable Product Data
Generated on Mon Dec 29 2025 02:15:52 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: 2 Overview

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
2 Overview

2.1 Technical Overview

The Intel® Firmware Support Package (FSP) provides chipset and processor initialization in a format that can easily be incorporated into many existing boot loaders.

The FSP will perform the necessary initialization steps as documented in the BWG including initialization of the CPU, memory controller, chipset and certain bus interfaces, if necessary.

FSP is not a stand-alone boot loader; therefore it needs to be integrated into a host boot loader to carry out other boot loader functions, such as: initializing non-Intel components, conducting bus enumeration, and discovering devices in the system and all industry standard initialization.

The FSP binary can be integrated easily into many different boot loaders, such as Coreboot, EDKII MinPlatform, Intel® Slim Bootloader, etc. and also into the embedded OS directly.

Below are some required steps for the integration:

  • Customizing The static FSP configuration parameters are part of the FSP binary and can be customized by tools provided by Intel. This step is optional as configuration data may also be provided at runtime.
  • Rebasing The FSP is not Position Independent Code (PIC) and the whole FSP has to be rebased if it is placed at a location which is different from the preferred address during build process.
  • Placing Once the FSP binary is ready for integration, the boot loader build process needs to be modified to place this FSP binary at the specific rebasing location identified above.
  • Interfacing The boot loader needs to add code to setup the operating environment for the FSP, call the FSP with correct parameters and parse the FSP output to retrieve the necessary information returned by the FSP.

2.2 FSP Distribution Package

  • The FSP distribution package contains the following:
    • FSP Binary
    • FSP Integration Guide
    • BSF Configuration File
    • Data Structure Header Files
  • The FSP configuration utility called BCT is available as a separate package. It can be downloaded from link mentioned in Section 1.3.

2.2.1 Package Layout

  • Docs (Auto generated)
    • FSP_Integration_Guide.pdf
    • FSP_Integration_Guide.chm
  • Include
    • FsptUpd.h, FspmUpd.h and FspsUpd.h (FSP UPD structure and related definitions)
    • GpioSampleDef.h (Sample enum definitions for GPIO table)
  • FspBinPkg.dec (EDKII declaration file for package)
  • Fsp.bsf (BSF file for configuring the data using BCT tool)
  • Fsp.fd (FSP Binary)
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: 3 FSP Integration

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
3 FSP Integration

3.1 Assumptions Used in this Document

The FSP for this platform is built with a preferred base address given by PcdFspAreaBaseAddress and so the reference code provided in the document assumes that the FSP is placed at this base address during the final boot loader build. Users may rebase the FSP binary at a different location with Intel's Binary Configuration Tool (BCT) or SplitFspBin.py before integrating to the boot loader.

For other assumptions and conventions, please refer to Chapter 8 and 9 of the FSP External Architecture Specification version 2.2.

3.2 Boot Flow

Please refer Chapter 7 in the FSP External Architecture Specification version 2.2 for Boot flow chart. The FSP for this platform supports dispatch mode, see Chapter 7 and 9 of the FSP External Architecture Specification version 2.2 for a description of dispatch mode.

3.3 FSP INFO Header

The FSP has an Information Header that provides critical information that is required by the bootloader to successfully interface with the FSP. The structure of the FSP Information Header is documented in the FSP External Architecture Specification version 2.2 with a HeaderRevision of 5.

3.4 FSP Image ID and Revision

FSP information header contains an Image ID field and an Image Revision field that provide the identification and revision information of the FSP binary. It is important to verify these fields while integrating the FSP as API parameters could change over different FSP IDs and revisions. All the FSP FV segments(FSP-T, FSP-M and FSP-S) must have same FSP Image ID and revision number, using FV segments with different revision numbers in a single FSP image is not valid. The FSP API parameters documented in this integration guide are applicable for the Image ID and Revision specified as below.

The FSP ImageId string in the FSP information header is given by PcdFspImageIdString and the ImageRevision field is given by SiliconInitVersionMajor|Minor|FspVersionRevision|FspVersionBuild (Ex:0x0A001460).

3.5 FSP Global Data

FSP uses some amount of TempRam area to store FSP global data which contains some critical data like pointers to FSP information headers and UPD configuration regions, FSP/Bootloader stack pointers required for stack switching etc. HPET Timer register(2) PcdGlobalDataPointerAddress is reserved to store address of this global data, and hence boot loader should not use this register for any other purpose. If TempRAM initialization is done by boot loader, then HPET has to be initialized to the base so that access to the register will work fine.

3.6 Memory Map

Below diagram represents the memory map allocated by FSP including the FSP specific regions.

System Memory Map

3.7 Optional modules

For products using FSP in API mode, having SPI size constraints, the following modules can be safely removed to help save additional space. These modules are included in FSP binary primarily when FSP is used in dispatch mode:

  • PchInitDxeFsp
  • HeciInitDxeFsp
  • SiInitDxeFsp
  • MtlPchInitDxeFsp
  • CpuMpPei
  • FspS3Notify
  • FspEndOfPei2Peim
  • GpioV2PpiInitPei
  • PchInitFsp
  • HeciInitFsp
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: 4 FSP Dispatch Mode

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
4 FSP Dispatch Mode

Overview

The FSP for this platform supports dispatch mode. Support for dispatch mode can be detected by checking if FSP_INFO_HEADER->ImageAttribute[BIT1] == 1. Dispatch mode is intended to enable FSP to integrate well in to UEFI bootloader implementations. Dispatch mode implements a boot flow that is as close to a standard UEFI boot flow as possible. In dispatch mode, the FSP is exposed as standard Firmware Volumes (FVs) directly to the bootloader. The PEIMs in these FVs are executed in the same PEI environment as the boot loader. In dispatch mode, the PPI database, PCD database, and HOB list are shared between the boot loader and the FSP.

Blue blocks are from the FSP binary and green blocks are from the bootloader. Blocks with mixed colors indicate that both bootloader and FSP modules are dispatched during that phase of the boot flow. In dispatch mode, the NotifyPhase() API is not used. Instead, FSP-S contains DXE drivers that implement the native callbacks on equivalent events for each of the NotifyPhase() invocations.

In dispatch mode, the the PPI database and PCD database are used for providing policy data from the bootloader to FSP. Because these mechanisms provide a great deal of flexibility, dispatch mode does not constrain the method for passing policy data as strongly as API mode. The following sections describe the dispatch mode policy initialization flow used specifically for this platform.

CONFIG_BLOCK_HEADER
struct _CONFIG_BLOCK_HEADER CONFIG_BLOCK_HEADER
Config Block Header.
_CONFIG_BLOCK_HEADER::Reserved
UINT8 Reserved[2]
Offset 26-27 Reserved for future use.
Definition: ConfigBlock.h:34
_CONFIG_BLOCK_TABLE_STRUCT::NumberOfBlocks
UINT16 NumberOfBlocks
Offset 30-31 Number of config blocks (N)
Definition: ConfigBlock.h:53
_CONFIG_BLOCK_HEADER::Revision
UINT8 Revision
Offset 24 Revision of this config block.
Definition: ConfigBlock.h:32
_CONFIG_BLOCK_TABLE_STRUCT::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 GUID number for main entry of config block.
Definition: ConfigBlock.h:51
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CONFIG_BLOCK_TABLE_HEADER
struct _CONFIG_BLOCK_TABLE_STRUCT CONFIG_BLOCK_TABLE_HEADER
Config Block Table Header.
EFI_STATUS
RETURN_STATUS EFI_STATUS
Function return status for EFI API.
Definition: UefiBaseType.h:29
_CONFIG_BLOCK_HEADER::Attributes
UINT8 Attributes
Offset 25 The main revision for config block.
Definition: ConfigBlock.h:33
_CONFIG_BLOCK_TABLE_STRUCT::Rsvd0
UINT8 Rsvd0[2]
Offset 28-29 Reserved for future use.
Definition: ConfigBlock.h:52
EFI_HOB_GUID_TYPE
Allows writers of executable content in the HOB producer phase to maintain and manage HOBs with speci...
Definition: PiHob.h:345
NULL
#define NULL
NULL pointer (VOID *)
Definition: Base.h:319
_CONFIG_BLOCK_TABLE_STRUCT
Config Block Table Header.
Definition: ConfigBlock.h:50
_CONFIG_BLOCK_TABLE_STRUCT::AvailableSize
UINT32 AvailableSize
Offset 32-35 Current config block table size.
Definition: ConfigBlock.h:54
_CONFIG_BLOCK_HEADER::GuidHob
EFI_HOB_GUID_TYPE GuidHob
Offset 0-23 GUID extension HOB header.
Definition: ConfigBlock.h:31
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:49 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: 4.1 Dispatch Mode Policy Init

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • 4 FSP Dispatch Mode
4.1 Dispatch Mode Policy Init

For the plurality of platform designs, most of the policy options provided by FSP do not need to be modified by the bootloader.

To ease this common case, policy initialization has been broken in to two phases: 1. Policy Init and 2. Policy Update.

Policy Init creates the policy data structures with all default policy values pre-populated. Policy Init is implemented using the factory method pattern. The FSP provides an API to the bootloader for constructing the policy data structures. Because the factory method is provided by the FSP, backwards compatibility is made substantially easier. The FSP can be assured that the policy data structures match the definitions used at the time the FSP was compiled. As long as new fields are added to the bottom of policy structures, the bootloader may continue to use an older version of the policy data structures at compile time and retain compatibility with both new and old FSP binaries.

There are two factory methods, one for FSP-M and one for FSP-S. PeiPreMemPolicyInit() is provided by FSP-M, PeiPolicyInit() is provided by FSP-S. These methods are exposed to the bootloader using PPIs, PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI for FSP-M and PEI_SI_DEFAULT_POLICY_INIT_PPI for FSP-S. The usage of PPIs ensures ABI stability between the FSP and the bootloader.

While Policy Init is implemented by the FSP, Policy Update is implemented by the bootloader. Policy Update uses a read-modify-write operation to apply any motherboard specific settings to the policy data while leaving the default values intact when appropriate. After Policy Update is done, FSP may run its SOC initialization code.

4.1.1 FSP-M Policy Initialization Flow

The follow graph shows the policy initialization flow for FSP-M.

Note
The hollow arrow heads in the flow diagram below indicate that action by the PEI Foundation is required for the flow to proceed.
Note
The function names and PEIMs used by the UEFI PI boot loader are implementation dependent and may vary from those shown here. The function names and PEIMs used by MinPlatform are provided as an example.

Execution of FSP-M begins after FspmWrapperInit() in IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c installs a EFI_PEI_FIRMWARE_VOLUME_INFO_PPI instance for FSP-M. This causes the PEI foundation to become aware of the FV(s) in FSP-M, which schedules all PEIMs in FSP-M for dispatch by PEI. This results in the SiInitPreMem PEIM in FSP-M being executed.

One of the actions performed by the SiInitPreMem entry-point is calling the SiInitPrePolicy() function, which installs the PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI. The DEPEX for MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf requires PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI to exist in the PPI database before SiliconPolicyPeiPreMem can run. While SiliconPolicyPeiPreMem.inf does not directly add PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI to the DEPEX, SiliconPolicyPeiPreMem.inf does statically link against MeteorlakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPreMemSiliconPolicyInitLib.inf, which adds PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI to the DEPEX. After the SiInitPreMem entry-point completes the dependency will be satisfied, making SiliconPolicyPeiPreMem eligible for dispatch.

Next SiliconPolicyPeiPreMem PEIM will run. SiliconPolicyPeiPreMemEntryPoint() in MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.c will call SiliconPolicyInitPreMem() in MeteorlakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c. This function will locate the instance of PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI previously created by SiInitPreMem and use it to call PeiPreMemSiDefaultPolicyInit() in SiInitPreMem. PeiPreMemSiDefaultPolicyInit() will construct SI_PREMEM_POLICY_PPI, which contains all the policy data needed by FSP-M. SiliconPolicyInitPreMem() will then locate SI_PREMEM_POLICY_PPI and return it to SiliconPolicyPeiPreMemEntryPoint().

Next, SiliconPolicyPeiPreMemEntryPoint() takes the pointer to the policy data returned by SiliconPolicyInitPreMem() and passes it to SiliconPolicyUpdatePreMem(). SiliconPolicyUpdatePreMem() is part of SiliconPolicyUpdateLib, which is statically linked to SiliconPolicyPeiPreMem. SiliconPolicyUpdateLib is special since it is only piece of motherboard specific code in this flow. An example of SiliconPolicyUpdatePreMem() is seen in MeteorlakeOpenBoardPkg/MeteorlakeMRvp/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c. SiliconPolicyUpdatePreMem() uses a read-modify-write operation to apply any motherboard specific settings to the policy data while leaving the default values intact when appropriate.

After SiliconPolicyUpdatePreMem() applies any motherboard specific updates, SiliconPolicyPeiPreMemEntryPoint() calls SiliconPolicyDonePreMem() in MeteorlakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c. SiliconPolicyDonePreMem() dumps the policy data to the debug log (on a DEBUG build of MinPlatform only) and installs the SI_PREMEM_POLICY_READY_PPI. SI_PREMEM_POLICY_READY_PPI tells FSP-M that everything is ready and that it can run the SOC init code now. Installing SI_PREMEM_POLICY_READY_PPI causes the PEI Foundation to signal a PeiServices->NotifyPpi() callback previously set up by SiInitPreMem. This callback invokes SiInitPreMemOnPolicyReady() in SiInitPreMem, which runs MRC and all the other SOC init code in FSP-M.

4.1.1 FSP-S Policy Initialization Flow

Policy Initialization for FSP-S follows essentially the same flow as FSP-M. The primary difference is function and PPI names do not include the "PreMem" qualifier.

Generated on Mon Dec 29 2025 02:15:50 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: 4.2 Config Blocks

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • 4 FSP Dispatch Mode
4.2 Config Blocks

Overview

Config Blocks are a binary data serialization format with several unique properties that are useful for firmware implementations.

The serialization format is simple to implement in the C language, minimizing the code needed to implement it; this minimizes the size of the FSP binary. Second, the format is binary backwards compatible; enabling the bootloader to use an older version of the data structure at compile time and retain compatibility with both new and old FSP binaries. Third, the format is mutable in memory without requiring the data to be re-serialized. Finally, the format is position independent with no need for a base address or a rebase operation. This allows the data structure to be moved from pre-memory to post-memory without applying any fixups.

Data in SI_PREMEM_POLICY_PPI and SI_POLICY_PPI are stored using the Config Block format.

4.2.1 Config Block Data Format

In essence, Config Blocks are multiple C structures that are stored in a single continuous memory range using run length encoding.

The overall structure is termed a Config Block Table. The Config Block Table starts with a CONFIG_BLOCK_TABLE_HEADER structure. This header indicates the number of Config Blocks in the Config Block Table, the total size of the table, and the amount of free space remaining in the table. The table may be over-provisioned, which allows additional Config Blocks to be added after the table's initial creation.

The size of all Config Blocks must be an even multiple of 32-bits as all Config Blocks are DWORD aligned. When enumerating a Config Block Table one may assume that all Config Blocks are packed back-to-back, hence the enumeration algorithm can use the length of each config block to find the next config block in the table.

Each Config Block has a GUID that identifies which C structure the Config Block contains. All Config Blocks start with a standardized CONFIG_BLOCK_HEADER, which allows all the structures in the table to be enumerated even if the format of the data payload inside each Config Block is unknown.

typedef struct _CONFIG_BLOCK_HEADER {
EFI_HOB_GUID_TYPE GuidHob; ///< Offset 0-23 GUID extension HOB header
UINT8 Revision; ///< Offset 24 Revision of this config block
UINT8 Attributes; ///< Offset 25 The main revision for config block
UINT8 Reserved[2]; ///< Offset 26-27 Reserved for future use
} CONFIG_BLOCK_HEADER;

The CONFIG_BLOCK_HEADER uses the header of a GUID HOB to store its length and GUID. This makes it easy to copy Config Blocks to the HOB list. Copying Config Blocks to the HOB list is a common use case. Often the ACPI code uses policies that were initially supplied by a Config Block. Copying the Config Block to the HOB list makes it easy for DXE phase to copy any needed policies to the ACPI global NVS memory later.

The Revision field assists with binary backward compatibility. Whenever a new field is added to a Config Block, the new field is added to the bottom of the Config Block and the Revision is incremented by 1. Thus if a bootloader wishes to retain compatibility with new and old versions of the FSP binary, it may do so by either by only using fields that are present in Revision 1 of the Config Block or by checking the Revision number before modifying fields added since Revision 1.

The CONFIG_BLOCK_TABLE_HEADER builds upon the CONFIG_BLOCK_HEADER:

typedef struct _CONFIG_BLOCK_TABLE_STRUCT {
CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 GUID number for main entry of config block
UINT8 Rsvd0[2]; ///< Offset 28-29 Reserved for future use
UINT16 NumberOfBlocks; ///< Offset 30-31 Number of config blocks (N)
UINT32 AvailableSize; ///< Offset 32-35 Current config block table size
///
/// Individual Config Block Structures are added starting here
///
} CONFIG_BLOCK_TABLE_HEADER;

4.2.2 Config Block Library APIs

To assist in the creation and parsing of Config Blocks, Intel has provided an open source Config Block library in IntelSiliconPkg/Library/BaseConfigBlockLib. This library provides the following functions:

  • GetConfigBlock()
  • AddConfigBlock()
  • CreateConfigBlockTable()

In most cases, bootloaders will only need to call GetConfigBlock().

4.2.3 Config Blocks used by FSP-M

On MeteorLake platforms SI_PREMEM_POLICY_PPI contains a Config Block Table. PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI will construct this Config Block Table with all the below Config Blocks pre-populated. Additionally, all the Config Blocks will be initialized with default policy values as described in section 4.1.

SI_PREMEM_POLICY_PPI contains the following Config Blocks:

Todo:
This list is from TigerLake, needs to be updated for MeteorLake
  • SI_PREMEM_CONFIG
  • HOST_BRIDGE_PREMEM_CONFIG
  • CPU_INIT_PREMEM_CONFIG
  • CPU_DMI_PREMEM_CONFIG
  • CPU_PCIE_RP_PREMEM_CONFIG
  • CPU_SECURITY_PREMEM_CONFIG
  • CPU_TRACE_HUB_PREMEM_CONFIG
  • CPU_TXT_PREMEM_CONFIG
  • GRAPHICS_PEI_PREMEM_CONFIG
  • HDAUDIO_PREMEM_CONFIG
  • HYBRID_GRAPHICS_CONFIG
  • IPU_PREMEM_CONFIG
  • ISH_PREMEM_CONFIG
  • ME_PEI_PREMEM_CONFIG
  • MEMORY_CONFIG_NO_CRC
  • MEMORY_CONFIGURATION
  • OVERCLOCKING_PREMEM_CONFIG
  • PCH_DCI_PREMEM_CONFIG
  • PCH_GENERAL_PREMEM_CONFIG
  • PCH_HSIO_PCIE_PREMEM_CONFIG
  • PCH_HSIO_SATA_PREMEM_CONFIG
  • PCH_LPC_PREMEM_CONFIG
  • PCH_PCIE_RP_PREMEM_CONFIG
  • PCH_SMBUS_PREMEM_CONFIG
  • PCH_WDT_PREMEM_CONFIG
  • PCIE_PEI_PREMEM_CONFIG
  • PCIE_PREMEM_CONFIG
  • PRAM_PREMEM_CONFIG
  • SA_MISC_PEI_PREMEM_CONFIG
  • TCSS_PEI_PREMEM_CONFIG
  • TELEMETRY_PEI_PREMEM_CONFIG
  • TWOLM_PREMEM_CONFIG
  • VTD_CONFIG

4.2.4 Config Blocks used by FSP-S

On MeteorLake platforms SI_POLICY_PPI contains a Config Block Table. PEI_SI_DEFAULT_POLICY_INIT_PPI will construct this Config Block Table with all the below Config Blocks pre-populated. Additionally, all the Config Blocks will be initialized with default policy values as described in section 4.1.

SI_POLICY_PPI contains the following Config Blocks:

Todo:
This list is from TigerLake, needs to be updated for MeteorLake
  • SI_CONFIG
  • HOST_BRIDGE_PEI_CONFIG
  • ADR_CONFIG
  • AMT_PEI_CONFIG
  • BIOS_GUARD_CONFIG
  • CNVI_CONFIG
  • CPU_INIT_CONFIG
  • CPU_PCIE_CONFIG
  • CPU_PID_TEST_CONFIG
  • CPU_POWER_MGMT_BASIC_CONFIG
  • CPU_POWER_MGMT_CUSTOM_CONFIG
  • CPU_POWER_DELIVERY_CONFIG
  • CPU_POWER_MGMT_TEST_CONFIG
  • CPU_POWER_MGMT_VR_CONFIG
  • CPU_TEST_CONFIG
  • GBE_CONFIG
  • GNA_CONFIG
  • GRAPHICS_PEI_CONFIG
  • HDAUDIO_CONFIG
  • HYBRID_STORAGE_CONFIG
  • IEH_CONFIG
  • ISH_CONFIG
  • ME_PEI_CONFIG
  • PCH_DMI_CONFIG
  • PCH_ESPI_CONFIG
  • PCH_FIVR_CONFIG
  • PCH_FLASH_PROTECTION_CONFIG
  • PCH_GENERAL_CONFIG
  • PCH_HSIO_CONFIG
  • PCH_INTERRUPT_CONFIG
  • PCH_IOAPIC_CONFIG
  • PCH_LOCK_DOWN_CONFIG
  • PCH_P2SB_CONFIG
  • PCH_PCIE_CONFIG
  • PCH_PM_CONFIG
  • PEI_ITBT_CONFIG
  • PSF_CONFIG
  • RST_CONFIG
  • RTC_CONFIG
  • SA_MISC_PEI_CONFIG
  • SATA_CONFIG
  • SERIAL_IO_CONFIG
  • TCSS_PEI_CONFIG
  • TELEMETRY_PEI_CONFIG
  • THC_CONFIG
  • THERMAL_CONFIG
  • TSN_CONFIG
  • USB_CONFIG
  • USB2_PHY_CONFIG
  • USB3_HSIO_CONFIG
  • VMD_PEI_CONFIG
CONFIG_BLOCK_HEADER
struct _CONFIG_BLOCK_HEADER CONFIG_BLOCK_HEADER
Config Block Header.
_CONFIG_BLOCK_HEADER::Reserved
UINT8 Reserved[2]
Offset 26-27 Reserved for future use.
Definition: ConfigBlock.h:34
_CONFIG_BLOCK_TABLE_STRUCT::NumberOfBlocks
UINT16 NumberOfBlocks
Offset 30-31 Number of config blocks (N)
Definition: ConfigBlock.h:53
_CONFIG_BLOCK_HEADER::Revision
UINT8 Revision
Offset 24 Revision of this config block.
Definition: ConfigBlock.h:32
_CONFIG_BLOCK_TABLE_STRUCT::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 GUID number for main entry of config block.
Definition: ConfigBlock.h:51
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CONFIG_BLOCK_TABLE_HEADER
struct _CONFIG_BLOCK_TABLE_STRUCT CONFIG_BLOCK_TABLE_HEADER
Config Block Table Header.
_CONFIG_BLOCK_HEADER::Attributes
UINT8 Attributes
Offset 25 The main revision for config block.
Definition: ConfigBlock.h:33
_CONFIG_BLOCK_TABLE_STRUCT::Rsvd0
UINT8 Rsvd0[2]
Offset 28-29 Reserved for future use.
Definition: ConfigBlock.h:52
EFI_HOB_GUID_TYPE
Allows writers of executable content in the HOB producer phase to maintain and manage HOBs with speci...
Definition: PiHob.h:345
_CONFIG_BLOCK_TABLE_STRUCT
Config Block Table Header.
Definition: ConfigBlock.h:50
_CONFIG_BLOCK_TABLE_STRUCT::AvailableSize
UINT32 AvailableSize
Offset 32-35 Current config block table size.
Definition: ConfigBlock.h:54
_CONFIG_BLOCK_HEADER::GuidHob
EFI_HOB_GUID_TYPE GuidHob
Offset 0-23 GUID extension HOB header.
Definition: ConfigBlock.h:31
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: 4.3 FSP Error Information

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • 4 FSP Dispatch Mode
4.3 FSP Error Information

In the case of a fatal error occurring during the execution of the FSP, it may not be possible for the FSP to continue.

If a fatal error that prevents the successful completion of the FSP occurs, the FSP may use FSP_ERROR_INFO to report this error to the bootloader. During PEI phase, (*PeiServices)->ReportStatusCode() shall be used to transmit this error notification to the bootloader. During DXE phase, EFI_STATUS_CODE_PROTOCOL.ReportStatusCode() shall be used to transmit this error notification to the bootloader. The bootloader must ensure that ReportStatusCode() services are available before FSP-M begins execution.

typedef struct {
EFI_STATUS_CODE_DATA DataHeader;
EFI_GUID ErrorType;
EFI_STATUS Status;
} FSP_ERROR_INFO;

FSP_ERROR_INFO is provided as the optional EFI_STATUS_CODE_DATA parameter to ReportStatusCode(). EFI_STATUS_CODE_DATA provides a CallerId GUID, this CallerId combined with the ErrorType GUID describes the error to the bootloader. The FSP for this platform implements the following CallerId GUIDs:

CallerId | Description
{0x1f4dc7e9, 0x26ca, 0x4336, {0x8c, 0xe3, 0x39, 0x31, 0x03, 0xb5, 0xf3, 0xd7}} | ME
{0x98230916, 0xe632, 0x49ff, {0x81, 0x81, 0x55, 0xce, 0xe5, 0x10, 0x36, 0x89}} | System Agent
{0x5a47c211, 0x642f, 0x4f92, {0x9c, 0xb3, 0x7f, 0xeb, 0x93, 0xda, 0xdd, 0xba}} | MRC

If the CallerId parameter is not a GUID in the table above, then it should be the GUID that identifies the PEIM or DXE driver which was executing at the time of the error.

The following ErrorType GUIDs are implemented:

ErrorType | Description
{0x948585c4, 0x76a4, 0x45bb, {0xbe, 0x6c, 0x39, 0x61, 0xc3, 0xab, 0xde, 0x15}} | ME EOP failure
{0x8106a5cc, 0x30ba, 0x41cf, {0xa1, 0x78, 0x63, 0x38, 0x91, 0x11, 0xae, 0xb2}} | SA PEI GOP Init failure
{0x348cc7fe, 0x1e9a, 0x4c7a, {0x86, 0x28, 0xae, 0x48, 0x5b, 0x42, 0x10, 0xf0}} | SA PEI GOP GetMode failure
{0x5de1c071, 0x2c9c, 0x4a53, {0x80, 0x21, 0x4e, 0x80, 0xd2, 0x5d, 0x44, 0xa8}} | MRC training failure

When the FSP calls ReportStatusCode(), the Type parameter's EFI_STATUS_CODE_TYPE_MASK must be EFI_ERROR_CODE with the EFI_STATUS_CODE_SEVERITY_MASK >= EFI_ERROR_UNRECOVERED. The Value and Instance parameters must be 0.

The bootloader must register a listener for this status code. This listener should check if DataHeader.Type == STATUS_CODE_DATA_TYPE_FSP_ERROR_GUID to detect an FSP_ERROR_INFO notification. If an FSP_ERROR_INFO notification is encountered, the bootloader should assume that normal operation is no longer possible. In debug scenarios, this notification should be considered an ASSERT.

EFI_STATUS
RETURN_STATUS EFI_STATUS
Function return status for EFI API.
Definition: UefiBaseType.h:29
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: 4.4 Dispatch Mode Integration

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • 4 FSP Dispatch Mode
4.4 Dispatch Mode Integration

Dispatch Mode Integration Notes:

  1. The FSP for this platform contains PEIMs compiled for the IA32 architecture. The boot loader therefore must utilize a PEI Foundation compiled for the IA32 architecture.
  2. Since the FSP binary can be integrated into flash at any address, the boot loader has to report FSP FVs to the PEI and DXE dispatcher using PI specification defined mechanisms so PEIMs and DXE drivers inside the FSP Binary can be dispatched. FspmWrapperPeim and FspsWrapperPeim from IntelFsp2WrapperPkg can aid in implementing this.
  3. For this platform, FSP-T, FSP-M, and FSP-S contain 1 FV each.
  4. The FSP distribution package will include a DSC file which contains all DynamicEx PCDs consumed by the FSP binary. The boot loader should include the DSC during its build process so that any PCDs defined by this DSC file are included in the boot loader's PCD database. This enables the boot loader and FSP to share a single PCD database.
    • A NULL library (FspPcdListLibNull.inf) is included in the FSP distribution package. This library should be included in one of the boot loader's PEIMs. This ensures all DynamicEx PCDs used by the FSP are included in the boot loader's PCD database. One can fulfill this requirement by including the following code snippet in *BoardPkg.dsc:
      IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf {
      <LibraryClasses>
      !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 0
      #
      # In FSP Dispatch mode below dummy library should be linked to bootloader PEIM
      # to build all DynamicEx PCDs that FSP consumes into bootloader PCD database.
      #
      NULL|$(PLATFORM_FSP_BIN_PACKAGE)/Library/FspPcdListLib/FspPcdListLibNull.inf
      !endif
      }
  5. The boot loader must provide at minimum 256KB of stack and 128KB of HOB heap to execute FSP on this platform.
  6. In dispatch mode, the boot loader should not use FSP API calls described in chapter 5 of this document or chapter 8 of the FSP External Architecture Specification version 2.2. The TempRamInit API is the only exception, it is supported in both API mode and dispatch mode. All other APIs (MemoryInit, SiliconInit, etc.) should not be invoked.
  7. For dispatch mode, FSP contains x64 DXE drivers to replace the NotifyPhase API. This eliminates thunking from 64bit to 32bit when using FSP dispatch mode. The boot loader should remove S3EndOfPeiNotify and FspWrapperNotifyDxe since they are no longer used in dispatch mode.
  8. EFI_PEI_CORE_FV_LOCATION_PPI should be installed by the boot loader's SEC phase. EFI_PEI_CORE_FV_LOCATION_PPI.PeiCoreFvLocation should point to the first Firmware Volume (FV) in FSP-M so the PeiCore inside FSP will be invoked. If EFI_PEI_CORE_FV_LOCATION_PPI is not installed or PeiCore cannot be found at the address specified by EFI_PEI_CORE_FV_LOCATION_PPI.PeiCoreFvLocation, the PeiCore from the Boot Firmware Volume (BFV) will be invoked instead.
  9. FSP-S requires multi-threaded code to complete silicon initialization on this platform. FSP-S includes the UefiCpuPkg/CpuMpPei/CpuMpPei.inf PEIM to provide multiprocessing. The bootloader can choose to either use the MP_SERVICES provided by the FSP for all PEIMs or the bootloader may provide an alternative implementation. In either case, only one MP_SERVICES implementation can be active at once. If the bootloader wishes to not use the FSP provided MP_SERVICES, then the bootloader must install the MP_SERVICES_PPI before installing the FV_INFO_PPI for FSP-S. If MP_SERVICES_PPI already exists, then FSP-S will use it and not execute its own implementation.
  10. If you are using the Intel Reference BIOS, some EDK2 overrides may be required for Dispatch Mode, please refer to override folders in reference code or the override EDK2 repo for more details. For open source MinPlatform based firmware, no EDK2 overrides are required.
  11. FSPM_ARCH_CONFIG_PPI->NvsBufferPtr is now a universal policy option (FSP Dispatch Mode and EDK2 native.) To enable the fast MRC training flow, the boot loader or platform code must to install this PPI to restore the previous MRC training data (SA_MISC_PEI_PREMEM_CONFIG->S3DataPtr is obsolete).
  12. Policy initialization Flow Changes:
    • PEIMs from FSP-M/FSP-S should be dispatched early in PEI to produce the DefaultPolicyInit PPIs. -> Bootloader consumes the DefaultPolicyInit PPIs produced by the FSP binary to create the policy PPIs with default settings. -> Bootloader then locates and updates the policy PPIs as needed. -> Bootloader installs the PolicyReadyPpi after policy updates are completed. This signals to the FSP that silicon initialization may proceed.
    • Bootloader shall consume two PPIs produced by FSP binary to create policy PPIs with default settings. These PPIs are:
      • PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI
      • PEI_SI_DEFAULT_POLICY_INIT_PPI
    • The bootloader shall call the two functions below after the bootloader has completed any needed policy updates:
      • SiPreMemInstallPolicyReadyPpi()
      • SiInstallPolicyReadyPpi()
  13. Debug message handling in dispatch mode:
    • Before the ReportStatusCode service is ready, a debug built FSP will send debug messages using the FSP-T UPD configuration (passed as FSP-T API input parameter). FSP-T is recommended to be used regardless FSP API mode or Dispatch mode.
    • Once the ReportStatusCode service is ready, a debug built FSP will send debug messages using the ReportStatusCode service.
    • It is recommended that bootloader register a StatusCode listener immediately after the ReportStatusCode service is ready. It is important to register this listener as soon as possible so that all debug messages sent by the FSP are captured.
    • Please refer to section 9.4.7 in the Intel(R) Firmware Support Package External Architecture Specification v2.2 for details about the ReportStatusCode debug message format.
  14. Enable or Disable FSP S3BootScript functionality: Since edk2-stable201911 release the PiDxeS3BootScriptLib supports enabling or disabling S3BootScript functionality by PCD, and FSP consumes this PCD as DynamicEx type to enable or disable internal S3BootScript functionality. Bootloader must configure below PCD before entering DXE phase or before executing FSP DXE drivers.
    • gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable = TRUE if S3BootScript should be enabled.
    • gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable = FALSE if S3BootScript should be disabled.
NULL
#define NULL
NULL pointer (VOID *)
Definition: Base.h:319
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: 5 FSP API Mode

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
5 FSP API Mode

Overview

This release of the FSP supports the all APIs required by the FSP External Architecture Specification version 2.2. These APIs are only used when running the FSP in API mode. In Dispatch mode, these APIs are not used (with the exception of TempRamInit.) The FSP information header contains the address offset for these APIs. Register usage is described in the FSP External Architecture Specification version 2.2. Any usage not described by the specification is described in the individual sections below.

The sections below will highlight any changes that are specific to this FSP release.

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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: 5.1 FSP APIs

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • 5 FSP API Mode
5.1 FSP APIs

5.1.1 TempRamInit API

Please refer Chapter 8.6 in the FSP External Architecture Specification version 2.2 for complete details including the prototype, parameters and return value details for this API.

TempRamInit does basic early initialization primarily setting up temporary RAM using cache. It returns ECX pointing to beginning of temporary memory and EDX pointing to end of temporary memory + 1. The total temporary ram currently available is given by PcdTemporaryRamSize starting from the base address of PcdTemporaryRamBase. Out of the total temporary memory available, the last PcdFspReservedBufferSize bytes of space are reserved by the FSP for TempRamInit if temporary RAM initialization is done by the FSP. Any remaining space from TemporaryRamBase(ECX) to TemporaryRamBase+TemporaryRamSize-FspReservedBufferSize (EDX) is available for both bootloader and FSP use.

TempRamInit** also sets up the code caching of the region passed in through CodeCacheBase and CodeCacheLength, which are input parameters to TempRamInitApi. if 0 is passed in for CodeCacheBase, the base used will be (4 GB - 1 - CodeCacheLength).

Note
: When programming MTRRs CodeCacheLength will be reduced, if the LLC size on the current processor is smaller than the requested size.

It is a requirement for Firmware to have a Firmware Interface Table (FIT). The FIT contains pointers to each microcode update. The microcode update is loaded for all logical processors before executing the reset vector. If more than one microcode update for the CPU is present, the microcode update with the latest revision is loaded.

FSPT_UPD.MicrocodeRegionBase** and FSPT_UPD.MicrocodeRegionLength are input parameters to TempRamInit API. If these values are 0, FSP will not attempt to update microcode. If MicrocodeRegionBase != 0 and MicrocodeRegionLength != 0, then FSP will search that region for microcode updates. If a newer microcode update revision is found in the region, FSP will load it.

TempRamInit** will program MTRRs values to provide the following memory map:

Memory range | Cache Attribute
0xFEF00000 - 0x00040000 | Write back
CodeCacheBase - CodeCacheLength | Write protect

5.1.2 FspMemoryInit API

Please refer to Chapter 8.7 in the FSP External Architecture Specification version 2.2 for the prototype, parameters and return value details for this API.

The variable FspmUpdPtr is a pointer to the FSPM_UPD structure which is described in the header file FspmUpd.h.

The bootloader must pass valid a CAR region for FSP through FSPM_UPD.FspmArchUpd.StackBase and FSPM_UPD.FspmArchUpd.StackSize UPDs.

The FSP for this platform will run FspMemoryInit top of the stack provided by the bootloader instead of establishing a separate stack as described by the FSP External Architecture Specification version 2.1/2.2. The memory region provided by the FSPM_UPD.FspmArchUpd.StackBase and FSPM_UPD.FspmArchUpd.StackSize UPDs is used to establish a HOB heap. The names StackBase and StackSize can be confusing since they are NOT used for stack. These names were retained for backwards compatibility with FSP v2.0.

Below are the heap and stack requirements for FSP on this platform:

HOB Heap requirement:

HOB Heap | UPD | Setting
Base | FSPM_UPD.FspmArchUpd.StackBase | Any non-conflict CAR region (0xFEF17F00 as default)
Size | FSPM_UPD.FspmArchUpd.StackSize | at least 128KB

Stack requirement: FSP's stack usage starts from the current stack pointer. The minimum stack size requirement for FSP-M is 256KB.

The bootloader must ensure that sufficient stack space is available to fulfill the FSP-M minimum stack size requirement at the point in execution where FspMemoryInit() is called. The stack allocated by the bootloader must be large enough for both FSP-M as well as any other parent function calls that are still on the stack at the point when FspMemoryInit() is called.

After FspMemoryInit() is completed, permanent memory is available. After this point, the memory pressure experienced early in boot is eliminated. Accordingly, right before FspMemoryInit() exits, any data that needs to be retained for later use by FspSiliconInit() will be copied to permanent memory. FspSiliconInit() will then execute on a second stack.

The base address of HECI device (Bus 0, Device 22, Function 0) is required to be initialized prior to calling FspMemoryInit(). The default address is programmed to 0xFED1A000.

FspMemoryInit() will calculate the memory map by taking into account the size of several memory regions: TSEG, IED, GTT, BDSM, ME stolen, Uncore PMRR, IOT, MOT, DPR, REMAP, TOLUD, TOUUD. These memory regions may not be initialized by FspMemoryInit(), but space will be reserved for them.

5.1.3 TempRamExit API

Please refer to Chapter 8.8 in the FSP external Architecture Specification version 2.2 for the prototype, parameters and return value details for this API.

If Boot Loader initializes the Temporary RAM (CAR) and skip calling TempRamInit API, it is expected that bootloader must skip calling this API and bootloader will tear down the temporary memory area setup in the cache and bring the cache to normal mode of operation.

The FSP for this platform doesn't have any input parameters for this API. The value of TempRamExitParamPtr should be NULL.

At the end of TempRamExit the original code and data cache are disabled. FSP will reconfigure all MTRRs as described in the table below. These MTRR values optimize performance in most scenarios. If the boot loader wishes to configure the MTRRs differently, they can be reprogrammed immediately after this API call.

Memory range | Cache Attribute
0xFF000000 - 0xFFFFFFFF (Flash region) | Write protect
0x00000000 - 0x0009FFFF | Write back
0x000C0000 - Top of Low Memory | Write back
xxxx - xxxx | x *Note1
0x100000000 - Top of High Memory | Write back *Note2

Stack requirement: 4KB of free stack space should be provided to execute TempRamExit.

Note1: Certain silicon features require specific cache types for specific memory ranges. These ranges will be configured by FSP when such features are enabled.

Note2: In some cases MTRRs might not be enough to cover all desired regions, in this case memory regions need to be adjusted for better alignment (e.g., adjust MmioSize or MmioSizeAdjustment UPD) Covering flash region and above 4GB memory is another case which may consume more MTRRs, when there is not enough MTRR available FSP will only cover above 4GB memory partially. In this case the boot loader can optimize MTRRs to remove flash from the cached regions after all needed data is loaded from flash and before booting the OS.

5.1.4 FspSiliconInit API

Please refer to Chapter 8.9 in the FSP external Architecture Specification version 2.2 for the prototype, parameters and return value details for this API.

The variable FspsUpdPtr is a pointer to the FSPS_UPD structure which is described in the header file FspsUpd.h.

It is expected that the boot loader will adjust MTRRs for SBSP if needed after TempRamExit but before entering FspSiliconInit. If the MTRRs are not programmed properly, boot performance can be impacted.

The region of 0x5_8000 - 0x5_8FFF is used by FspSiliconInit for starting APs. If this data is important to bootloader, then bootloader needs to preserve it before calling FspSiliconInit.

FspSiliconInit requires multi-threaded code to complete silicon initialization on this platform. FSP includes the UefiCpuPkg/CpuMpPei/CpuMpPei.inf PEIM to provide multiprocessing. Accordingly, the boot loader must expect FSP to perform an INIT-SIPI-SIPI during FspSiliconInit and NotifyPhase which will take control of all APs in the system and restart them. This will kill any background threads that were running on the APs. In some cases, this may not be desirable. As an alternative, the boot loader may provide an instance of the EFI_PEI_MP_SERVICES_PPI through the FspsUpd->FspsConfig.CpuMpPpi UPD for the FSP to use instead of the built-in implementation. This is entirely optional, if callbacks from FSP to the boot loader are not desired, one may set FspsUpd->FspsConfig.CpuMpPpi == NULL.

In summary, there are two methods that FSP can use for performing multiprocessing:

  1. Using the multiprocessing services built-in to the FSP.
  2. Using the boot loader's multiprocessing services.

Using method #1, the boot loader will set FspsUpd->FspsConfig.CpuMpPpi == NULL. If this UPD is NULL, then FSP will use its built-in MP services implementation for multiprocessing. Accordingly, the boot loader must expect FSP to perform an INIT-SIPI-SIPI during FspSiliconInit and NotifyPhase which will take control of all APs in the system and restart them. This will kill any background threads that were running on the APs.

Note: If bootloader needs to take control of APs back, a full AP re-initialization is required after FSP-S completed and control has been transferred back to bootloader.

Using method #2, the boot loader will set FspsUpd->FspsConfig.CpuMpPpi != NULL. If this UPD is not NULL, it must point to an instance of EFI_PEI_MP_SERVICES_PPI. When the FSP needs to perform multiprocessing, it will use the EFI_PEI_MP_SERVICES_PPI instance provided by the boot loader to do so. Accordingly, the boot loader must expect the function pointers in EFI_PEI_MP_SERVICES_PPI to be invoked in the middle of the execution of FspSiliconInit and NotifyPhase.

It is a requirement for the bootloader to have a Firmware Interface Table (FIT), which contains pointers to each microcode. The microcode is loaded for all cores before reset vector. If more than one microcode update for the CPU is present, the latest revision is loaded.

MicrocodeRegionBase and MicrocodeRegionLength are both input parameters to TempRamInit and UPD for SiliconInit API. UPD has priority and will be searched for a later revision than TempRamInit. If MicrocodeRegionBase and MicrocodeRegionLength values are 0, FSP will not attempt to update the microcode. If a microcode region is passed, FSP will search that region for microcode updates. If a newer microcode update revision is found in the region, FSP will load it.

FspSiliconInit initializes PCH audio. This includes selecting the HD Audio verb table and initializing the audio CODEC.

FspSiliconInit initializes the following PCH features: HECI, USB, HSIO, Integrated Sensor Hub, Camera, PCI Express, DMI, Vt-d.

FspSiliconInit initializes the following CPU features: XD, VMX, AES, IED, HDC, x(2)APIC, Intel® Processor Trace, Three Strike Counter, Machine Check, Cache Pre-fetchers, Core PMRR, and Power Management.

FspSiliconInit initializes Internal Graphics. During this initialization, FSP publishes the EFI_PEI_GRAPHICS_INFO_HOB and the EFI_PEI_GRAPHICS_DEVICE_INFO_HOB. These HOBs will not be published during S3 resume as FSP will not initialize the internal graphics frame buffer during S3 resume.

FspSiliconInit programs SA BARs: MchBar, DmiBar, EpBar, GdxcBar, EDRAM (if supported). Please refer to section 2.8 (MemoryMap) for the corresponding Bar values. GttMmadr (0xDF000000) and GmAdr(0xC0000000) are temporarily programmed and cleared after use in FSP.

Stack requirement: 4KB of free stack space should be provided to execute FspSiliconInit.

5.1.5 FspMultiPhaseSiInit API

Please refer Chapter 8.10 in the FSP External Architecture Specification version 2.2 for the prototype, parameters and return value details for this API.

If the FspMultiPhaseSiInit API is enabled (by setting FSPS_ARCH_UPD->EnableMultiPhaseSiliconInit UPD to 1 before the FspSiliconInit API is invoked), the bootloader should call this API with the MultiPhaseAction parameter set to 0 to get the NumberOfPhases supported by this platform. FSP will return control back to the bootloader NumberOfPhases times and then the bootloader should call FspMultiPhaseSiInit API with the MultiPhaseAction parameter set to 1 by NumberOfPhases times.

Note
: Disable FSPS_ARCH_UPD->EnableMultiPhaseSiliconInit when we disable FSP_M_CONFIG->TcssXhciEn.

This platform supports the following MultiPhaseSiInit phase(s):

Phase | FSP return point | Purpose
1 | After TCSS initialization completed | for TCSS board specific initialization from bootloader side

5.1.6 NotifyPhase API

Please refer Chapter 8.11 in the FSP External Architecture Specification version 2.2 for the prototype, parameters and return value details for this API.

Stack requirement: 4KB of free stack space should be provided to execute NotifyPhase.

5.1.6.1 PostPciEnumeration Notification

This phase EnumInitPhaseAfterPciEnumeration is to be called after PCI enumeration but before execution of third party code such as option ROMs. It includes powering down unused PCH SATA ports, locking registers in PMC, DMI, TCO, and SPI Flash (DLOCK + WRSDIS + FLOCKDN). It also includes enabling bus hosting for eSPI connected devices.

5.1.6.2 ReadyToBoot Notification

This phase EnumInitPhaseReadyToBoot is to be called before giving control to the operating system. It includes some final initialization steps recommended by the BWG, including power management settings, and sending ME Message EOP (End of Post).

5.1.6.3 EndOfFirmware Notification

This phase EnumInitEndOfFirmware is to be called before the firmware/preboot environment transfers management of all system resources to the OS or next level execution environment. It includes final locking of chipset registers.

5.1.7 FSP Events API

Please refer Chapter 8.5 in the FSP External Architecture Specification version 2.2 for the prototype, parameters and return value details for these APIs.

This platform supports FSP Events which re-direct debug messages to event handlers provided by bootloader. To enable this function the bootloader must provide event handler function pointers via UPDs.

FSP phase | UPD for bootloader to pass handler function pointer
FSP-T | FSPT_ARCH_UPD -> FspDebugHandler
FSP-M | FSPM_ARCH_UPD -> FspEventHandler
FSP-S | FSPS_ARCH_UPD -> FspEventHandler
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: 5.2 Reset Return Codes

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • 5 FSP API Mode
5.2 Reset Return Codes

As per FSP External Architecture Specification version 2.0/2.1/2.2, any reset required in the FSP flow will be reported by returning one of the FSP_STATUS_RESET_REQUIRED* return codes.

It is the boot loader's responsibility to reset the system according to the reset type requested.

Below table specifies the return status returned by FSP API and the requested reset type.

FSP_STATUS_RESET_REQUIRED Code | Reset Type requested
0x40000001 | Cold Reset
0x40000002 | Warm Reset
0x40000003 | Global Reset - Puts the system through a Global Reset through HECI or a Full Reset through PCH
0x40000004 | Reserved
0x40000005 | Reserved
0x40000006 | Reserved
0x40000007 | Reserved
0x40000008 | Reserved
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: 5.3 UPD Porting Guide

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • 5 FSP API Mode
5.3 UPD Porting Guide

Recommended values for UPDs:

UPD | Dependency | Description | Value
CstateLatencyControl1Irtl | Server platform | Server platform should has different setting | 0x6B
PchPcieHsioRxSetCtleEnable | Board design | Different board requires different value | tune
PchPcieHsioRxSetCtle | Board design | Different board requires different value | tune
PchSataHsioRxGen3EqBoostMagEnable | Board design | Different board requires different value | tune
PchSataHsioRxGen3EqBoostMag | Board design | Different board requires different value | tune
PchSataHsioTxGen1DownscaleAmpEnable | Board design | Different board requires different value | tune
PchSataHsioTxGen1DownscaleAmp | Board design | Different board requires different value | tune
PchSataHsioTxGen2DownscaleAmpEnable | Board design | Different board requires different value | tune
PchSataHsioTxGen2DownscaleAmp | Board design | Different board requires different value | tune
PchNumRsvdSmbusAddresses | Board design | Different board requires different value | tune
RsvdSmbusAddressTablePtr | Board design | Different board requires different value | tune
BiosSize | Board design | Different board requires different value | tune
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: 6 Porting Recommendations

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
6 Porting Recommendations

Here are some notes and recommendations for adapting an existing boot loader to FSP.

6.1 Locking PAM register

FSP 2.0 introduced the EndOfFirmware Notify phase callback which is the recommended place for locking PAM registers. Accordingly, by default FSP locks the PAM registers during the EndOfFirmware Notify phase. If the EndOfFirmware Notify phase is too early to lock PAM registers, then the PAM locking code inside the FSP can be disabled by setting the UPD -> FSP_S_TEST_CONFIG -> SkipPamLock or SA policy -> _SI_PREMEM_POLICY_STRUCT -> SA_MISC_PEI_CONFIG -> SkipPamLock. If the PAM locking code inside the FSP is skipped, then the boot loader must lock the PAM registers before booting the OS. by programming one PCI config space register as below.

The PAM registers must be locked in all boot paths including S3 resume. To lock the PAM registers, program the following lock bit:

MmioOr32 (B0: D0: F0: Register 0x80, BIT0)

6.2 Locking SMRAM register

It is recommended that SMRAM be locked before any third party code (e.g. OpROM) execution. The point in execution where third party OpROMs begin executing can vary depending on the boot loader implementation. To provide flexibility, the FSP by default will not lock it. The boot loader should lock SMRAM by programming the following lock bit before any third party OpROM execution. Additionally, SMRAM should be locked before the EnumInitPhaseReadyToBoot notify phase is called. During S3 resume, the lock bit should be set right before the OS wake vector.

PciOr8 (B0: D0: F0: Register 0x88, BIT4);
Note: This register must be programmed using the legacy CF8/CFC PCI access mechanism. (MMIO access will not work)

6.3 Locking SMI register

It is recommended that the global SMI bit is locked before any third party code (e.g. OpROM) execution. SMM initialization flows may vary depending on boot loader implementation details. Accordingly, FSP will not lock it by default. The boot loader is responsible for locking the following registers after SMM configuration is complete. Set AcpiBase + 0x30[0] to 1b to enable global SMI. Set PMC PCI offset A0h[4] = 1b to lock SMI.

6.4 Verify below settings are correct for your platforms

PMC PCI configuration space is not PCI specification compliant. The FSP will hide the PMC controller to avoid external software or OS from corrupting the BAR addresses. FSP will program the PMC controller IO and MMIO BAR's with below addresses. Please use these addresses in the boot loader code instead of reading BAR addresses from the PMC controller.

Register | Values
ABASE | 0x1800
PWRMBASE | 0xFE000000
PCIEXBAR_BASE_ADDRESS | 0xE0000000
Note
:
  • Boot Loader can use a different value for PCIEXBAR_BASE_ADDRESS either by modifying the UPD (under FSP-T) or by overriding the PCIEXBAR (B0:D0:F0:R60h) before calling FspMemoryInit.
  • Boot Loader should avoid using conflicting address when reprogramming PCIEXBAR_BASE_ADDRESS than the recommended one.
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: 7 FSP Output

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
7 FSP Output

The FSP builds a series of data structures called Hand-Off-Blocks (HOBs) as it progresses through initializing the silicon.

Please refer to the Platform Initialization (PI) Specification - Volume 3: Shared Architectural Elements specification for PI Architectural HOBs. Please refer Chapter 10 in the FSP External Architecture Specification version 2.2 for details about FSP Architectural HOBs.

The sections below describe the HOBs not covered in the above two specifications.

7.1 Resource Descriptor HOB

Below resource HOBs with specific owner GUID are publicized to specify memory ranges used by FSP. Bootloader shall check and not consume these ranges to avoid memory collision.

7.1.1 SMRAM Resource Descriptor HOB

The FSP will report the system SMRAM T-SEG range through a generic resource HOB if T-SEG is enabled. The owner field of the HOB identifies the owner as T-SEG.

#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \
{ 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } }

7.1.2 TraceHub Resource Descriptor HOB

TraceHub Resource HOB is reported when TraceHub is enabled or PlatformDebugConsent UPD is 2 (Enabled) to reserve memory above 4G for TraceHub use.

#define FSP_HOB_RESOURCE_OWNER_TRACEHUB_GUID \
{ 0x5fb35909, 0x5a1c, 0x4a31, { 0xad, 0xaf, 0x57, 0x7b, 0x54, 0x68, 0x26, 0x3f } }

7.2 SMBIOS INFO HOB

The FSP will report the SMBIOS through a HOB with below GUID. This information can be consumed by the bootloader to produce the SMBIOS tables. These structures are included as part of MemInfoHob.h, SmbiosCacheInfoHob.h, SmbiosProcessorInfoHob.h, & FirmwareVersionInfoHob.h

#define SI_MEMORY_INFO_DATA_HOB_GUID \
{ 0x9b2071d4, 0xb054, 0x4e0c, { 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 } };
typedef struct {
MrcDimmStatus Status; ///< See MrcDimmStatus for the definition of this field.
UINT8 DimmId;
UINT32 DimmCapacity; ///< DIMM size in MBytes.
UINT16 MfgId;
UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
UINT8 RankInDimm; ///< The number of ranks in this DIMM.
UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
UINT8 SpdSave[MAX_SPD_SAVE_DATA]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
} DIMM_INFO;
typedef struct {
UINT8 Status; ///< Indicates whether this channel should be used.
UINT8 ChannelId;
UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
MRC_CH_TIMING Timing[MAX_PROFILE]; ///< The channel timing values.
DIMM_INFO Dimm[MAX_DIMM]; ///< Save the DIMM output characteristics.
} CHANNEL_INFO;
typedef struct {
UINT8 Status; ///< Indicates whether this controller should be used.
UINT16 DeviceId; ///< The PCI device id of this memory controller.
UINT8 RevisionId; ///< The PCI revision id of this memory controller.
UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
CHANNEL_INFO Channel[MAX_CH]; ///< The following are channel level definitions.
} CONTROLLER_INFO;
typedef struct {
EFI_HOB_GUID_TYPE EfiHobGuidType;
UINT8 Revision;
UINT16 DataWidth;
/// As defined in SMBIOS 3.0 spec
/// Section 7.18.2 and Table 75
UINT8 DdrType; ///< DDR type: DDR3, DDR4, or LPDDR3
UINT32 Frequency; ///< The system's common memory controller frequency in MT/s.
/// As defined in SMBIOS 3.0 spec
/// Section 7.17.3 and Table 72
UINT8 ErrorCorrectionType;
SiMrcVersion Version;
UINT32 FreqMax;
BOOLEAN EccSupport;
UINT8 MemoryProfile;
UINT32 TotalPhysicalMemorySize;
BOOLEAN XmpProfileEnable;
UINT8 Ratio;
UINT8 RefClk;
UINT32 VddVoltage[MAX_PROFILE];
CONTROLLER_INFO Controller[MAX_NODE];
} MEMORY_INFO_DATA_HOB;
#define SI_MEMORY_PLATFORM_DATA_HOB \
{ 0x6210d62f, 0x418d, 0x4999, { 0xa2, 0x45, 0x22, 0x10, 0x0a, 0x5d, 0xea, 0x44 } }
typedef struct {
UINT8 Revision;
UINT8 Reserved[3];
UINT32 BootMode;
UINT32 TsegSize;
UINT32 TsegBase;
UINT32 PrmrrSize;
UINT32 PrmrrBase;
UINT32 GttBase;
UINT32 MmioSize;
UINT32 PciEBaseAddress;
} MEMORY_PLATFORM_DATA;
typedef struct {
EFI_HOB_GUID_TYPE EfiHobGuidType;
MEMORY_PLATFORM_DATA Data;
UINT8 *Buffer;
} MEMORY_PLATFORM_DATA_HOB;
#define SMBIOS_CACHE_INFO_HOB_GUID \
{ 0xd805b74e, 0x1460, 0x4755, {0xbb, 0x36, 0x1e, 0x8c, 0x8a, 0xd6, 0x78, 0xd7} }
///
/// SMBIOS Cache Info HOB Structure
///
typedef struct {
UINT16 ProcessorSocketNumber;
UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3
UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE"
UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.0 Section7.8 Table36
UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.0 Section7.8.1
UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.0 Section7.8.1
UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.0 Section7.8.2
UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.0 Section7.8.2
UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown.
UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.3
UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.4
UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.5
///String Buffer - each string terminated by NULL "0x00"
///String buffer terminated by double NULL "0x0000"
} SMBIOS_CACHE_INFO;
#define SMBIOS_PROCESSOR_INFO_HOB_GUID \
{ 0xe6d73d92, 0xff56, 0x4146, {0xaf, 0xac, 0x1c, 0x18, 0x81, 0x7d, 0x68, 0x71} }
///
/// SMBIOS Processor Info HOB Structure
///
typedef struct {
UINT16 TotalNumberOfSockets;
UINT16 CurrentSocketNumber;
UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.1
///This info is used for both ProcessorFamily and ProcessorFamily2 fields
///See ENUM defined in SMBIOS Spec v3.0 Section 7.5.2
UINT16 ProcessorFamily;
UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer
UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.3
UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer
UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.0 Section 7.5.4
UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown.
UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot
UINT8 Status; ///< Format defined in the SMBIOS Spec v3.0 Table 21
UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.5
///This info is used for both CoreCount & CoreCount2 fields
/// See detailed description in SMBIOS Spec v3.0 Section 7.5.6
UINT16 CoreCount;
///This info is used for both CoreEnabled & CoreEnabled2 fields
///See detailed description in SMBIOS Spec v3.0 Section 7.5.7
UINT16 EnabledCoreCount;
///This info is used for both ThreadCount & ThreadCount2 fields
/// See detailed description in SMBIOS Spec v3.0 Section 7.5.8
UINT16 ThreadCount;
UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.0 Section 7.5.9
/// String Buffer - each string terminated by NULL "0x00"
/// String buffer terminated by double NULL "0x0000"
} SMBIOS_PROCESSOR_INFO;
#define SMBIOS_FIRMWARE_VERSION_INFO_HOB_GUID \
{ 0x798e722e, 0x15b2, 0x4e13, { 0x8a, 0xe9, 0x6b, 0xa3, 0x0f, 0xf7, 0xf1, 0x67 }}
///
/// Firmware Version Structure
///
typedef struct {
UINT8 MajorVersion;
UINT8 MinorVersion;
UINT8 Revision;
UINT16 BuildNumber;
} FIRMWARE_VERSION;
///
/// Firmware Version Information Structure
///
typedef struct {
UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
} FIRMWARE_VERSION_INFO;
///
/// The Smbios structure header.
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Handle;
} SMBIOS_STRUCTURE;
///
/// Firmware Version Information HOB Structure
///
typedef struct {
SMBIOS_STRUCTURE Header; ///< SMBIOS structure header
UINT8 Count; ///< Number of FVI entries in this structure
INTEL_FIRMWARE_VERSION_INFO Fvi[1]; ///< FVI structure(s)
///
/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
///
} FIRMWARE_VERSION_INFO_HOB;

7.3 CHIPSETINIT INFO HOB

The FSP will report the ChipsetInit CRC through a HOB with below GUID. This information can be consumed by the bootloader to check if ChipsetInit CRC is matched between BIOS and ME. These structures are included as part of FspsUpd.h

#define CHIPSETINIT_INFO_HOB_GUID \
{ 0xc1392859, 0x1f65, 0x446e, { 0xb3, 0xf5, 0x84, 0x35, 0xfc, 0xc7, 0xd1, 0xc4 }}
///
/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
///
typedef struct {
UINT8 Revision;
UINT8 Rsvd[3];
UINT16 MeChipInitCrc;
UINT16 BiosChipInitCrc;
} CHIPSET_INIT_INFO;

7.4 HOB USAGE INFO HOB

The FSP will report the Hob memory usage through a HOB with below GUID. This information can be consumed by the bootloader to check how much temporary RAM is left.

#define HOB_USAGE_DATA_HOB_GUID \
{0xc764a821, 0xec41, 0x450d, { 0x9c, 0x99, 0x27, 0x20, 0xfc, 0x7c, 0xe1, 0xf6 }}
typedef struct {
EFI_PHYSICAL_ADDRESS EfiMemoryTop;
EFI_PHYSICAL_ADDRESS EfiMemoryBottom;
EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop;
EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom;
UINTN FreeMemory;
} HOB_USAGE_DATA_HOB;

7.5 FSP_ERROR_INFO_HOB

In the case of an error occurring during the execution of the FSP, the FSP may produce this HOB which describes the error in more detail. FSP_ERROR_INFO_HOB is only used in FSP API Mode. In FSP Dispatch Mode, FSP may call ReportStatusCode() and provide a FSP_ERROR_INFO structure using the PI status code services.

#define FSP_ERROR_INFO_HOB_GUID \
{0x611e6a88, 0xadb7, 0x4301, { 0x93, 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6 }}
typedef struct {
EFI_HOB_GUID_TYPE GuidHob;
EFI_STATUS_CODE_TYPE Type;
EFI_STATUS_CODE_VALUE Value;
UINT32 Instance;
EFI_GUID CallerId;
EFI_GUID ErrorType;
UINT32 Status;
} FSP_ERROR_INFO_HOB;

The FSP for this platform implements the following CallerId GUIDs:

CallerId | Description
{0x1f4dc7e9, 0x26ca, 0x4336, {0x8c, 0xe3, 0x39, 0x31, 0x03, 0xb5, 0xf3, 0xd7}} | ME
{0x98230916, 0xe632, 0x49ff, {0x81, 0x81, 0x55, 0xce, 0xe5, 0x10, 0x36, 0x89}} | System Agent
{0x5a47c211, 0x642f, 0x4f92, {0x9c, 0xb3, 0x7f, 0xeb, 0x93, 0xda, 0xdd, 0xba}} | MRC

The following ErrorType GUIDs are implemented:

ErrorType | Description
{0x948585c4, 0x76a4, 0x45bb, {0xbe, 0x6c, 0x39, 0x61, 0xc3, 0xab, 0xde, 0x15}} | ME EOP failure
{0x8106a5cc, 0x30ba, 0x41cf, {0xa1, 0x78, 0x63, 0x38, 0x91, 0x11, 0xae, 0xb2}} | SA PEI GOP Init failure
{0x348cc7fe, 0x1e9a, 0x4c7a, {0x86, 0x28, 0xae, 0x48, 0x5b, 0x42, 0x10, 0xf0}} | SA PEI GOP GetMode failure
{0x5de1c071, 0x2c9c, 0x4a53, {0x80, 0x21, 0x4e, 0x80, 0xd2, 0x5d, 0x44, 0xa8}} | MRC training failure
EFI_PHYSICAL_ADDRESS
UINT64 EFI_PHYSICAL_ADDRESS
64-bit physical memory address.
Definition: UefiBaseType.h:50
FSP_ERROR_INFO_HOB
FSP Error Information Block.
Definition: FspErrorInfo.h:60
EFI_HOB_GUID_TYPE
Allows writers of executable content in the HOB producer phase to maintain and manage HOBs with speci...
Definition: PiHob.h:345
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: 8 POST Codes

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
8 POST Codes

The FSP outputs 16-bit POST codes to indicate which API and which module is currently executing.

Bit Range | Description
Bit15 - Bit12 (X) | used to indicate the phase/api under which the code is executing
Bit11 - Bit8 (Y) | used to indicate the module
Bit7 (ZZ bit 7) | reserved for error
Bit6 - Bit0 (ZZ) | individual codes

8.1 POST Code Info

The diagram below illustrates how sub-fields are encoded in the POST codes produced by the FSP.

8.1.1 TempRamInit API Status Codes (0xFxxx)

PostCode | Module | Description
0x0000 | FSP | TempRamInit API Entry (The change in upper byte is due to not enabling of the Port81 early in the boot)
0x007F | FSP | TempRamInit API Exit

8.1.2 FspMemoryInit API Status Codes (0xDxxx)

PostCode | Module | Description
0xD800 | FSP | FspMemoryInit API Entry
0xD87F | FSP | FSpMemoryInit API Exit
0xDA00 | SA | Pre-Mem SaInit Entry
0xDA02 | SA | OverrideDev0Did Start
0xDA04 | SA | OverrideDev2Did Start
0xDA06 | SA | Programming SA Bars
0xDA08 | SA | Install SA HOBs
0xDA0A | SA | Reporting SA PCIe code version
0xDA0C | SA | SaSvInit Start
0xDA10 | SA | Initializing DMI
0xDA15 | SA | Initialize TCSS PreMem
0xDA1F | SA | Initializing DMI/OPI Max PayLoad Size
0xDA20 | SA | Initializing SwitchableGraphics
0xDA30 | SA | Initializing SA PCIe
0xDA3F | SA | Programming PEG credit values Start
0xDA40 | SA | Initializing DMI Tc/Vc mapping
0xDA42 | SA | CheckOffboardPcieVga
0xDA44 | SA | CheckAndInitializePegVga
0xDA50 | SA | Initializing Graphics
0xDA52 | SA | Initializing System Agent Overclocking
0xDA7F | SA | Pre-Mem SaInit Exit
0xDB00 | PCH | Pre-Mem PchInit Entry
0xDB02 | PCH | Pre-Mem Disable PCH fused controllers
0xDB15 | PCH | Pre-Mem SMBUS configuration
0xDB48 | PCH | Pre-Mem PchOnPolicyInstalled Entry
0xDB49 | PCH | Pre-Mem Program HSIO
0xDB4A | PCH | Pre-Mem DCI configuration
0xDB4C | PCH | Pre-Mem Host DCI enabled
0xDB4D | PCH | Pre-Mem Trace Hub - Early configuration
0xDB4E | PCH | Pre-Mem Trace Hub - Device disabled
0xDB4F | PCH | Pre-Mem TraceHub - Programming MSR
0xDB50 | PCH | Pre-Mem Trace Hub - Power gating configuration
0xDB51 | PCH | Pre-Mem Trace Hub - Power gating Trace Hub device and locking HSWPGCR1 register
0xDB52 | PCH | Pre-Mem Initialize HPET timer
0xDB55 | PCH | Pre-Mem PchOnPolicyInstalled Exit
0xDB7F | PCH | Pre-Mem PchInit Exit
0xDC00 | CPU | CPU Pre-Mem Entry
0xDC0F | CPU | CpuAddPreMemConfigBlocks Done
0xDC20 | CPU | CpuOnPolicyInstalled Start
0xDC2F | CPU | XmmInit Start
0xDC3F | CPU | TxtInit Start
0xDC4F | CPU | Init CPU Straps
0xDC5F | CPU | Init Overclocking
0xDC6F | CPU | CPU Pre-Mem Exit
0x**55 | SA | MRC_MEM_INIT_DONE
0x**D5 | SA | MRC_MEM_INIT_DONE_WITH_ERRORS
0xDD00 | SA | MRC_INITIALIZATION_START
0xDD10 | SA | MRC_CMD_PLOT_2D
0xDD1B | SA | MRC_FAST_BOOT_PERMITTED
0xDD1C | SA | MRC_RESTORE_NON_TRAINING
0xDD1D | SA | MRC_PRINT_INPUT_PARAMS
0xDD1E | SA | MRC_SET_OVERRIDES_PSPD
0xDD20 | SA | MRC_SPD_PROCESSING
0xDD21 | SA | MRC_SET_OVERRIDES
0xDD22 | SA | MRC_MC_CAPABILITY
0xDD23 | SA | MRC_MC_CONFIG
0xDD24 | SA | MRC_MC_MEMORY_MAP
0xDD25 | SA | MRC_JEDEC_INIT_LPDDR3
0xDD26 | SA | MRC_RESET_SEQUENCE
0xDD27 | SA | MRC_PRE_TRAINING
0xDD28 | SA | MRC_EARLY_COMMAND
0xDD29 | SA | MRC_SENSE_AMP_OFFSET
0xDD2A | SA | MRC_READ_MPR
0xDD2B | SA | MRC_RECEIVE_ENABLE
0xDD2C | SA | MRC_JEDEC_WRITE_LEVELING
0xDD2D | SA | MRC_LPDDR_LATENCY_SET_B
0xDD2E | SA | MRC_WRITE_TIMING_1D
0xDD2F | SA | MRC_READ_TIMING_1D
0xDD30 | SA | MRC_DIMM_ODT
0xDD31 | SA | MRC_EARLY_WRITE_TIMING_2D
0xDD32 | SA | MRC_WRITE_DS
0xDD33 | SA | MRC_WRITE_EQ
0xDD34 | SA | MRC_EARLY_READ_TIMING_2D
0xDD35 | SA | MRC_READ_ODT
0xDD36 | SA | MRC_READ_EQ
0xDD37 | SA | MRC_READ_AMP_POWER
0xDD38 | SA | MRC_WRITE_TIMING_2D
0xDD39 | SA | MRC_READ_TIMING_2D
0xDD3A | SA | MRC_CMD_VREF
0xDD3B | SA | MRC_WRITE_VREF_2D
0xDD3C | SA | MRC_READ_VREF_2D
0xDD3D | SA | MRC_POST_TRAINING
0xDD3E | SA | MRC_LATE_COMMAND
0xDD3F | SA | MRC_ROUND_TRIP_LAT
0xDD40 | SA | MRC_TURN_AROUND
0xDD41 | SA | MRC_CMP_OPT
0xDD42 | SA | MRC_SAVE_MC_VALUES
0xDD43 | SA | MRC_RESTORE_TRAINING
0xDD44 | SA | MRC_RMT_TOOL
0xDD45 | SA | MRC_WRITE_SR
0xDD46 | SA | MRC_DIMM_RON
0xDD47 | SA | MRC_RCVEN_TIMING_1D
0xDD48 | SA | MRC_MR_FILL
0xDD49 | SA | MRC_PWR_MTR
0xDD4A | SA | MRC_DDR4_MAPPING
0xDD4B | SA | MRC_WRITE_VOLTAGE_1D
0xDD4C | SA | MRC_EARLY_RDMPR_TIMING_2D
0xDD4D | SA | MRC_FORCE_OLTM
0xDD50 | SA | MRC_MC_ACTIVATE
0xDD51 | SA | MRC_RH_PREVENTION
0xDD52 | SA | MRC_GET_MRC_DATA
0xDD53 | SA | Reserved
0xDD58 | SA | MRC_RETRAIN_CHECK
0xDD5A | SA | MRC_SA_GV_SWITCH
0xDD5B | SA | MRC_ALIAS_CHECK
0xDD5C | SA | MRC_ECC_CLEAN_START
0xDD5D | SA | MRC_DONE
0xDD5F | SA | MRC_CPGC_MEMORY_TEST
0xDD60 | SA | MRC_TXT_ALIAS_CHECK
0xDD61 | SA | MRC_ENG_PERF_GAIN
0xDD68 | SA | MRC_MEMORY_TEST
0xDD69 | SA | MRC_FILL_RMT_STRUCTURE
0xDD70 | SA | MRC_SELF_REFRESH_EXIT
0xDD71 | SA | MRC_NORMAL_MODE
0xDD7D | SA | MRC_SSA_PRE_STOP_POINT
0xDD7F | SA | MRC_SSA_STOP_POINT, MRC_INITIALIZATION_END
0xDD90 | SA | MRC_CMD_PLOT_2D_ERROR
0xDD9B | SA | MRC_FAST_BOOT_PERMITTED_ERROR
0xDD9C | SA | MRC_RESTORE_NON_TRAINING_ERROR
0xDD9D | SA | MRC_PRINT_INPUT_PARAMS_ERROR
0xDD9E | SA | MRC_SET_OVERRIDES_PSPD_ERROR
0xDDA0 | SA | MRC_SPD_PROCESSING_ERROR
0xDDA1 | SA | MRC_SET_OVERRIDES_ERROR
0xDDA2 | SA | MRC_MC_CAPABILITY_ERROR
0xDDA3 | SA | MRC_MC_CONFIG_ERROR
0xDDA4 | SA | MRC_MC_MEMORY_MAP_ERROR
0xDDA5 | SA | MRC_JEDEC_INIT_LPDDR3_ERROR
0xDDA6 | SA | MRC_RESET_ERROR
0xDDA7 | SA | MRC_PRE_TRAINING_ERROR
0xDDA8 | SA | MRC_EARLY_COMMAND_ERROR
0xDDA9 | SA | MRC_SENSE_AMP_OFFSET_ERROR
0xDDAA | SA | MRC_READ_MPR_ERROR
0xDDAB | SA | MRC_RECEIVE_ENABLE_ERROR
0xDDAC | SA | MRC_JEDEC_WRITE_LEVELING_ERROR
0xDDAD | SA | MRC_LPDDR_LATENCY_SET_B_ERROR
0xDDAE | SA | MRC_WRITE_TIMING_1D_ERROR
0xDDAF | SA | MRC_READ_TIMING_1D_ERROR
0xDDB0 | SA | MRC_DIMM_ODT_ERROR
0xDDB1 | SA | MRC_EARLY_WRITE_TIMING_ERROR
0xDDB2 | SA | MRC_WRITE_DS_ERROR
0xDDB3 | SA | MRC_WRITE_EQ_ERROR
0xDDB4 | SA | MRC_EARLY_READ_TIMING_ERROR
0xDDB5 | SA | MRC_READ_ODT_ERROR
0xDDB6 | SA | MRC_READ_EQ_ERROR
0xDDB7 | SA | MRC_READ_AMP_POWER_ERROR
0xDDB8 | SA | MRC_WRITE_TIMING_2D_ERROR
0xDDB9 | SA | MRC_READ_TIMING_2D_ERROR
0xDDBA | SA | MRC_CMD_VREF_ERROR
0xDDBB | SA | MRC_WRITE_VREF_2D_ERROR
0xDDBC | SA | MRC_READ_VREF_2D_ERROR
0xDDBD | SA | MRC_POST_TRAINING_ERROR
0xDDBE | SA | MRC_LATE_COMMAND_ERROR
0xDDBF | SA | MRC_ROUND_TRIP_LAT_ERROR
0xDDC0 | SA | MRC_TURN_AROUND_ERROR
0xDDC1 | SA | MRC_CMP_OPT_ERROR
0xDDC2 | SA | MRC_SAVE_MC_VALUES_ERROR
0xDDC3 | SA | MRC_RESTORE_TRAINING_ERROR
0xDDC4 | SA | MRC_RMT_TOOL_ERROR
0xDDC5 | SA | MRC_WRITE_SR_ERROR
0xDDC6 | SA | MRC_DIMM_RON_ERROR
0xDDC7 | SA | MRC_RCVEN_TIMING_1D_ERROR
0xDDC8 | SA | MRC_MR_FILL_ERROR
0xDDC9 | SA | MRC_PWR_MTR_ERROR
0xDDCA | SA | MRC_DDR4_MAPPING_ERROR
0xDDCB | SA | MRC_WRITE_VOLTAGE_1D_ERROR
0xDDCC | SA | MRC_EARLY_RDMPR_TIMING_2D_ERROR
0xDDCD | SA | MRC_FORCE_OLTM_ERROR
0xDDD0 | SA | MRC_MC_ACTIVATE_ERROR
0xDDD1 | SA | MRC_RH_PREVENTION_ERROR
0xDDD2 | SA | MRC_GET_MRC_DATA_ERROR
0xDDD3 | SA | Reserved
0xDDD8 | SA | MRC_RETRAIN_CHECK_ERROR
0xDDDA | SA | MRC_SA_GV_SWITCH_ERROR
0xDDDB | SA | MRC_ALIAS_CHECK_ERROR
0xDDDC | SA | MRC_ECC_CLEAN_ERROR
0xDDDD | SA | MRC_DONE_WITH_ERROR
0xDDDF | SA | MRC_CPGC_MEMORY_TEST_ERROR
0xDDE0 | SA | MRC_TXT_ALIAS_CHECK_ERROR
0xDDE1 | SA | MRC_ENG_PERF_GAIN_ERROR
0xDDE8 | SA | MRC_MEMORY_TEST_ERROR
0xDDE9 | SA | MRC_FILL_RMT_STRUCTURE_ERROR
0xDDF0 | SA | MRC_SELF_REFRESH_EXIT_ERROR
0xDDF1 | SA | MRC_MRC_NORMAL_MODE_ERROR
0xDDFD | SA | MRC_SSA_PRE_STOP_POINT_ERROR
0xDDFE | SA | MRC_NO_MEMORY_DETECTED

8.1.3 TempRamExit API Status Codes (0xBxxx)

PostCode | Module | Description
0xB800 | FSP | TempRamExit API Entry
0xB87F | FSP | TempRamExit API Exit

8.1.4 FspSiliconInit API Status Codes (0x9xxx)

PostCode | Module | Description
0x9800 | FSP | FspSiliconInit API Entry
0x987F | FSP | FspSiliconInit API Exit
0x9A00 | SA | PostMem SaInit Entry
0x9A01 | SA | DeviceConfigure Start
0x9A02 | SA | UpdateSaHobPostMem Start
0x9A03 | SA | Initializing Pei Display
0x9A04 | SA | PeiGraphicsNotifyCallback Entry
0x9A05 | SA | CallPpiAndFillFrameBuffer
0x9A06 | SA | GraphicsPpiInit
0x9A07 | SA | GraphicsPpiGetMode
0x9A08 | SA | FillFrameBufferAndShowLogo
0x9A0F | SA | PeiGraphicsNotifyCallback Exit
0x9A14 | SA | Initializing SA IPU device
0x9A16 | SA | Initializing SA GNA device
0x9A20 | SA | Initializing PciExpressInitPostMem
0x9A22 | SA | Initializing ConfigureNorthIntelTraceHub
0x9A30 | SA | Initializing Vtd
0x9A31 | SA | Initializing TCSS
0x9A32 | SA | Initializing Pavp
0x9A34 | SA | PeiInstallSmmAccessPpi Start
0x9A36 | SA | EdramWa Start
0x9A4F | SA | Post-Mem SaInit Exit
0x9A50 | SA | SaSecurityLock Start
0x9A5F | SA | SaSecurityLock End
0x9A60 | SA | SaSResetComplete Entry
0x9A61 | SA | Set BIOS_RESET_CPL to indicate all configurations complete
0x9A62 | SA | SaSvInit2 Start
0x9A63 | SA | GraphicsPmInit Start
0x9A64 | SA | SaPciPrint Start
0x9A6F | SA | SaSResetComplete Exit
0x9A70 | SA | SaS3ResumeAtEndOfPei Callback Entry
0x9A7F | SA | SaS3ResumeAtEndOfPei Callback Exit
0x9B00 | PCH | Post-Mem PchInit Entry
0x9B03 | PCH | Post-Mem Tune the USB 2.0 high-speed signals quality
0x9B04 | PCH | Post-Mem Tune the USB 3.0 signals quality
0x9B05 | PCH | Post-Mem Configure PCH xHCI
0x9B06 | PCH | Post-Mem Performs configuration of PCH xHCI SSIC
0x9B07 | PCH | Post-Mem Configure PCH xHCI after init
0x9B08 | PCH | Post-Mem Configures PCH USB device (xDCI)
0x9B0A | PCH | Post-Mem DMI/OP-DMI configuration
0x9B0B | PCH | Post-Mem Initialize P2SB controller
0x9B0C | PCH | Post-Mem IOAPIC initialization
0x9B0D | PCH | Post-Mem PCH devices interrupt configuration
0x9B0E | PCH | Post-Mem HD Audio initizalization
0x9B0F | PCH | Post-Mem HD Audio Codec enumeration
0x9B10 | PCH | Post-Mem HD Audio Codec not detected
0x9B13 | PCH | Post-Mem SCS initizalization
0x9B14 | PCH | Post-Mem ISH initizalization
0x9B15 | PCH | Post-Mem Configure SMBUS power management
0x9B16 | PCH | Post-Mem Reserved
0x9B17 | PCH | Post-Mem Performing global reset
0x9B18 | PCH | Post-Mem Reserved
0x9B19 | PCH | Post-Mem Reserved
0x9B40 | PCH | Post-Mem OnEndOfPEI Entry
0x9B41 | PCH | Post-Mem Initialize Thermal controller
0x9B42 | PCH | Post-Mem Configure Memory Throttling
0x9B47 | PCH | Post-Mem OnEndOfPEI Exit
0x9B4D | PCH | Post-Mem Trace Hub - Memory configuration
0x9B4E | PCH | Post-Mem Trace Hub - MSC0 configured
0x9B4F | PCH | Post-Mem Trace Hub - MSC1 configured
0x9B7F | PCH | Post-Mem PchInit Exit
0x9C00 | CPU | CPU Post-Mem Entry
0x9C09 | CPU | CpuAddConfigBlocks Done
0x9C0A | CPU | SetCpuStrapAndEarlyPowerOnConfig Start
0x9C13 | CPU | SetCpuStrapAndEarlyPowerOnConfig Reset
0x9C14 | CPU | SetCpuStrapAndEarlyPowerOnConfig Done
0x9C15 | CPU | CpuInit Start
0x9C17 | CPU | CollectProcessorFeature Start
0x9C18 | CPU | ProgramProcessorFeature Start
0x9C19 | CPU | ProgramProcessorFeature Done
0x9C20 | CPU | CpuInitPreResetCpl Start
0x9C21 | CPU | ProcessorsPrefetcherInitialization Start
0x9C22 | CPU | InitRatl Start
0x9C23 | CPU | ConfigureSvidVrs Start
0x9C24 | CPU | ConfigurePidSettings Start
0x9C25 | CPU | SetBootFrequency Start
0x9C26 | CPU | CpuOcInitPreMem Start
0x9C27 | CPU | CpuOcInit Reset
0x9C28 | CPU | BiosGuardInit Start
0x9C29 | CPU | BiosGuardInit Reset
0x9C3F | CPU | CpuInitPreResetCpl Done
0x9C42 | CPU | ApSafePostMicrocodePatchInit Start
0x9C43 | CPU | InitializeCpuDataHob Start
0x9C44 | CPU | InitializeCpuDataHob Done
0x9C4F | CPU | CpuInit Done
0x9C50 | CPU | S3InitializeCpu Start
0x9C55 | CPU | MpRendezvousProcedure Start
0x9C56 | CPU | MpRendezvousProcedure Done
0x9C69 | CPU | S3InitializeCpu Done
0x9C6A | CPU | CpuPowerMgmtInit Start
0x9C71 | CPU | InitPpm
0x9C7F | CPU | CPU Post-Mem Exit
0x9C80 | CPU | ReloadMicrocodePatch Start
0x9C81 | CPU | ReloadMicrocodePatch Done
0x9C82 | CPU | ApSafePostMicrocodePatchInit Start
0x9C83 | CPU | ApSafePostMicrocodePatchInit Done

8.1.5 NotifyPhase API Status Codes (0x6xxx)

PostCode | Module | Description
0x6800 | FSP | NotifyPhase API Entry
0x687F | FSP | NotifyPhase API Exit
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Todo List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Todo List
Page 4.2 Config Blocks

This list is from TigerLake, needs to be updated for MeteorLake

This list is from TigerLake, needs to be updated for MeteorLake

Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Class List
Here are the classes, structs, unions and interfaces with brief descriptions:
C _CONFIG_BLOCK | Config Block
C _CONFIG_BLOCK_HEADER | Config Block Header
C _CONFIG_BLOCK_TABLE_STRUCT | Config Block Table Header
C _EFI_MM_RESERVED_MMRAM_REGION | Structure describing a MMRAM region which cannot be used for the MMRAM heap
C _EFI_PEI_MP_SERVICES_PPI | This PPI is installed by some platform or chipset-specific PEIM that abstracts handling multiprocessor support
C _ITBT_GENERIC_CONFIG | ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and HOB
C _ITBT_ROOTPORT_CONFIG | ITBT RootPort Data Structure
C _LIST_ENTRY | _LIST_ENTRY structure definition
C _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI | This PPI provides function to install default silicon policy
C _PEI_SI_DEFAULT_POLICY_INIT_PPI | This PPI provides function to install default silicon policy
C _SI_POLICY_STRUCT | SI Policy PPI; All SI config block change history will be listed here
C _SI_PREMEM_POLICY_STRUCT | SI Policy PPI in Pre-Mem; All SI config block change history will be listed here
C ADR_CONFIG | ADR Configuration Revision 1: - Initial version
C ADR_GLOBAL_RESET_ENABLE | ADR Source Enable
C AMT_DXE_CONFIG | AMT Dxe Configuration Structure
C AMT_PEI_CONFIG | AMT Pei Configuration Structure
C BCLK_CONFIG | BCLK configuration
C CNVI_PIN_MUX | CNVi signals pin muxing settings
C CNVI_PREMEM_CONFIG | The CNVI_PREMEM_CONFIG block describes the expected configuration of the CNVi IP
C DMI_HW_WIDTH_CONTROL | This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec design
C DMI_LANE_CONFIG | The PCH_DMI_LANE_CONFIG block describes specific lane configuration
C EFI_HOB_CPU | Describes processor information, such as address space and I/O space capabilities
C EFI_HOB_FIRMWARE_VOLUME | Details the location of firmware volumes that contain firmware files
C EFI_HOB_FIRMWARE_VOLUME2 | Details the location of a firmware volume that was extracted from a file within another firmware volume
C EFI_HOB_FIRMWARE_VOLUME3 | Details the location of a firmware volume that was extracted from a file within another firmware volume
C EFI_HOB_GENERIC_HEADER | Describes the format and size of the data inside the HOB
C EFI_HOB_GUID_TYPE | Allows writers of executable content in the HOB producer phase to maintain and manage HOBs with specific GUID
C EFI_HOB_HANDOFF_INFO_TABLE | Contains general state information used by the HOB producer phase
C EFI_HOB_MEMORY_ALLOCATION | Describes all memory ranges used during the HOB producer phase that exist outside the HOB list
C EFI_HOB_MEMORY_ALLOCATION_BSP_STORE | Defines the location of the boot-strap processor (BSP) BSPStore ("Backing Store Pointer Store")
C EFI_HOB_MEMORY_ALLOCATION_HEADER | EFI_HOB_MEMORY_ALLOCATION_HEADER describes the various attributes of the logical memory allocation
C EFI_HOB_MEMORY_ALLOCATION_MODULE | Defines the location and entry point of the HOB consumer phase
C EFI_HOB_MEMORY_ALLOCATION_STACK | Describes the memory stack that is produced by the HOB producer phase and upon which all post-memory-installed executable content in the HOB producer phase is executing
C EFI_HOB_MEMORY_POOL | Describes pool memory allocations
C EFI_HOB_RESOURCE_DESCRIPTOR | Describes the resource properties of all fixed, nonrelocatable resource ranges found on the processor host bus during the HOB producer phase
C EFI_HOB_UEFI_CAPSULE | Each UEFI capsule HOB details the location of a UEFI capsule
C EFI_IP_ADDRESS | 16-byte buffer aligned on a 4-byte boundary
C EFI_MAC_ADDRESS | 32-byte buffer containing a network Media Access Control address
C EFI_MMRAM_DESCRIPTOR | Structure describing a MMRAM region and its accessibility attributes
C EFI_PEI_HOB_POINTERS | Union of all the possible HOB Types
C EFI_TIME | EFI Time Abstraction: Year: 1900 - 9999 Month: 1 - 12 Day: 1 - 31 Hour: 0 - 23 Minute: 0 - 59 Second: 0 - 59 Nanosecond: 0 - 999,999,999 TimeZone: -1440 to 1440 or 2047
C FIVR_EXT_RAIL_CONFIG | Structure for V1p05/Vnn VR rail configuration
C FIVR_VCCIN_AUX_CONFIG | Structure for VCCIN_AUX voltage rail configuration
C FSP_ERROR_INFO_HOB | FSP Error Information Block
C FSPM_ARCH_CONFIG_PPI | This PPI provides FSP-M Arch Config PPI
C GBE_CONFIG | PCH intergrated GBE controller configuration settings
C GNA_CONFIG | GNA config block for configuring GNA
C GPIO_CONFIG | GPIO configuration structure used for pin programming
C GUID | 128 bit buffer containing a unique identifier value
C HDA_LINK_DMIC | HD Audio DMIC Interface Policies
C HDA_LINK_HDA | HD Audio Link Policies
C HDA_LINK_SNDW | HD Audio SNDW Interface Policies
C HDA_LINK_SSP | HD Audio SSP Interface Policies
C HDA_VERB_TABLE_HEADER | Azalia verb table header Every verb table should contain this defined header and followed by azalia verb commands
C HDAUDIO_DXE_CONFIG | This structure contains the DXE policies which are related to HD Audio device (cAVS)
C HDAUDIO_PREMEM_CONFIG | This structure contains the premem policies which are related to HD Audio device (cAVS)
C HSIO_PARAMETERS | This structure describes USB3 Port N configuration parameters
C I2C_PIN_MUX | I2C signals pin muxing settings
C IEH_CONFIG | The IEH_CONFIG block describes the expected configuration of the PCH Integrated Error Handler
C IOM_AUX_ORI_PAD_CONFIG | The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin
C IOM_INTERFACE_CONFIG | The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC
C IPU_PREMEM_CONFIG | IPU PreMem configuration; Revision 1:
C IPv4_ADDRESS | 4-byte buffer
C IPv6_ADDRESS | 16-byte buffer
C ISH_CONFIG | The ISH_CONFIG block describes Integrated Sensor Hub device
C ISH_GP | Struct contains GPIO pins assigned and signal settings of GP
C ISH_GPIO_CONFIG | ISH GPIO settings
C ISH_I2C | Struct contains GPIO pins assigned and signal settings of I2C
C ISH_I2C_PIN_CONFIG | I2C signals settings
C ISH_I3C_CONFIG | The ISH_I3C_CONFIG block describes I3C in ISH device
C ISH_PREMEM_CONFIG | Premem Policy for Integrated Sensor Hub device
C ISH_SPI | Struct contains GPIO pins assigned and signal settings of SPI
C ISH_SPI_PIN_CONFIG | SPI signals settings
C ISH_UART | Struct contains GPIO pins assigned and signal settings of UART
C ISH_UART_PIN_CONFIG | UART signals settings
C ME_PEI_CONFIG | ME Pei Post-Memory Configuration Structure
C ME_PEI_PREMEM_CONFIG | ME Pei Pre-Memory Configuration Structure
C MUX_GPIO_CONFIG | I3C GPIO settings
C OVERCLOCKING_PREMEM_CONFIG | Overclocking Configuration Structure
C PCH_DCI_PREMEM_CONFIG | The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct Connection Interface (DCI)
C PCH_DEVICE_INTERRUPT_CONFIG | The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device
C PCH_DMI_CONFIG | The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI
C PCH_FIVR_CONFIG | The PCH_FIVR_CONFIG block describes FIVR settings
C PCH_FLASH_PROTECTION_CONFIG | The PCH provides a method for blocking writes and reads to specific ranges in the SPI flash when the Protected Ranges are enabled
C PCH_GENERAL_CONFIG | PCH General Configuration Revision 2: - Add VtdEnabled field
C PCH_HSIO_CONFIG | The PCH_HSIO_CONFIG block provides HSIO message related settings
C PCH_HSIO_PCIE_LANE_CONFIG | The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane
C PCH_HSIO_PCIE_PREMEM_CONFIG | The PCH_HSIO_PCIE_CONFIG block describes the configuration of the HSIO for PCIe lanes
C PCH_HSIO_PREMEM_CONFIG | The PCH_HSIO_PREMEM_CONFIG block provides HSIO message related settings
C PCH_HSIO_SATA_PORT_LANE | The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane
C PCH_HSIO_SATA_PREMEM_CONFIG | The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the SATA controller
C PCH_INTERRUPT_CONFIG | The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH
C PCH_IOAPIC_CONFIG | The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is not TRUE
C PCH_LPC_PREMEM_CONFIG | This structure contains the policies which are related to LPC
C PCH_P2SB_CONFIG | This structure contains the policies which are related to P2SB device
C PCH_PCIE_CLOCK | PCH_PCIE_CLOCK describes PCIe source clock generated by PCH
C PCH_PCIE_CONFIG | The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers Revision 1:
C PCH_PCIE_ROOT_PORT_CONFIG | The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port
C PCH_PCIE_RP_PREMEM_CONFIG | The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers Revision 1:
C PCH_PM_CONFIG | The PCH_PM_CONFIG block describes expected miscellaneous power management settings
C PCH_SATA_PORT_CONFIG | This structure configures the features, property, and capability for each SATA port
C PCH_SMBUS_PREMEM_CONFIG | The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform
C PCH_TRACE_HUB_PREMEM_CONFIG | PCH Trace Hub PreMem Configuration Contains Trace Hub settings for PCH side tracing Revision 1: - Initial version
C PCH_WAKE_CONFIG | This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL, LAN, PCIE wake events
C PCH_WDT_PREMEM_CONFIG | This policy clears status bits and disable watchdog, then lock the WDT registers
C PCIE_COMMON_CONFIG | PCIe Common Config
C PCIE_DEVICE_OVERRIDE | PCIe device table entry entry
C PCIE_EQ_PARAM | Represent lane specific PCIe Gen3 equalization parameters
C PCIE_IMR_CONFIG | PCIe IMR Config
C PCIE_LINK_EQ_PLATFORM_SETTINGS | PCIe Link EQ Platform Settings
C PCIE_PREMEM_CONFIG | PCIe Pre-Memory Configuration Revision 1: - Initial version
C PCIE_RP_DXE_CONFIG | The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers in DXE phase
C PMC_GLOBAL_RESET_MASK | Description of Global Reset Trigger/Event Mask register
C PMC_INTERFACE_CONFIG | The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC
C PMC_LPM_S0IX_SUB_STATE_EN | Low Power Mode Enable config
C PROTECTED_RANGE | Protected Flash Range
C RST_CONFIG | Rapid Storage Technology settings
C RST_HARDWARE_REMAPPED_STORAGE_CONFIG | This structure describes the details of Intel RST for PCIe Storage remapping Note: In order to use this feature, Intel RST Driver is required
C RTC_CONFIG | The RTC_CONFIG block describes the expected configuration of RTC configuration
C SA_MISC_PEI_PREMEM_CONFIG | This configuration block is to configure SA Miscellaneous variables during PEI Pre-Mem phase like programming different System Agent BARs, TsegSize, MmioSize required etc
C SA_XDCI_IRQ_INT_CONFIG | The SA XDCI INT Pin and IRQ number
C SATA_CONFIG | The SATA_CONFIG block describes the expected configuration of the SATA controllers
C SATA_THERMAL_THROTTLING | This structure lists PCH supported SATA thermal throttling register setting for customization
C SERIAL_IO_CONFIG | The SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers
C SERIAL_IO_I2C_CONFIG | Serial IO I2C Controller Configuration
C SERIAL_IO_I3C_CONFIG | The SERIAL_IO_I3C_CONFIG provides the configurations for Serial IO I3C controller
C SERIAL_IO_SPI_CONFIG | The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller
C SERIAL_IO_UART_ATTRIBUTES | UART Settings
C SERIAL_IO_UART_CONFIG | Serial IO UART Controller Configuration
C SI_CONFIG | The Silicon Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware
C SI_PREMEM_CONFIG | The Silicon PreMem Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware
C SPI_PIN_MUX | SPI signals pin muxing settings
C SVID_SID_VALUE | Subsystem Vendor ID / Subsystem ID
C TCSS_DEVEN_PEI_PREMEM_CONFIG | The TCSS_DEVEN_PEI_PREMEM_CONFIG block describes Device Enable settings for TCSS
C TCSS_IOM_ORI_OVERRIDE | The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS
C TCSS_IOM_PEI_CONFIG | The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS
C TCSS_MISC_PEI_CONFIG | The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS
C TCSS_PCIE_PEI_POLICY | TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS
C TCSS_PCIE_PORT_POLICY | The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS
C TCSS_PEI_CONFIG | The TCSS_PEI_CONFIG block describes TCSS settings for SA
C TCSS_PEI_PREMEM_CONFIG | This configuration block describes TCSS settings
C TCSS_USBTC_PEI_PERMEM_CONFIG | The TCSS_USBTC_PEI_PERMEM_CONFIG block describes IOM settings for TCSS
C TELEMETRY_PEI_CONFIG | This configuration block describes Telemetry settings in PostMem
C TELEMETRY_PEI_PREMEM_CONFIG | This configuration block describes Telemetry settings in PreMem
C THC_CONFIG | THC_CONFIG block provides the configurations forTouch Host Controllers
C THC_HID_OVER_I2C | THC Hid Over I2C mode related settings
C THC_HID_OVER_SPI | THC Hid Over SPI mode related settings
C THC_PORT | Port Configuration structure required for each Port that THC might use
C THC_RESET | THC Reset Pad related settings
C THERMAL_CONFIG | The THERMAL_CONFIG block describes the expected configuration of the Thermal IP block
C THERMAL_THROTTLE_LEVELS | This structure lists PCH supported throttling register setting for custimization
C TRACE_HUB_CONFIG | TRACE_HUB_CONFIG block describes TraceHub settings
C TRACE_HUB_PREMEM_CONFIG | Trace Hub PreMem Configuration Contains Trace Hub settings Revision 1: - Initial version
C UART_PIN_MUX | UART signals pin muxing settings
C USB2_PHY_CONFIG | This structure holds info on how to tune electrical parameters of USB2 ports based on board layout
C USB2_PHY_PARAMETERS | This structure configures per USB2 AFE settings
C USB2_PORT_CONFIG | This structure configures per USB2.0 port settings like enabling and overcurrent protection
C USB3_PORT_CONFIG | This structure configures per USB3.x port settings like enabling and overcurrent protection
C VMD_PEI_CONFIG | This configuration block is to configure VMD related variables used in PostMem PEI
C VTD_ENGINE_CONFIG | This structure describes each VT-d engine
C XDCI_CONFIG | The XDCI_CONFIG block describes the configurations of the xDCI Usb Device controller


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: _CONFIG_BLOCK Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
_CONFIG_BLOCK Struct Reference

Config Block. More...

#include <ConfigBlock.h>

Collaboration diagram for _CONFIG_BLOCK:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Header of config block.

Detailed Description

Config Block.

Definition at line 40 of file ConfigBlock.h.

The documentation for this struct was generated from the following file:
  • ConfigBlock.h
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
_CONFIG_BLOCK Member List

This is the complete list of members for _CONFIG_BLOCK, including all inherited members.

Header | _CONFIG_BLOCK
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: _CONFIG_BLOCK_HEADER Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
_CONFIG_BLOCK_HEADER Struct Reference

Config Block Header. More...

#include <ConfigBlock.h>

Collaboration diagram for _CONFIG_BLOCK_HEADER:
[legend]

Public Attributes

EFI_HOB_GUID_TYPE GuidHob
Offset 0-23 GUID extension HOB header.
UINT8 | Revision
Offset 24 Revision of this config block.
UINT8 | Attributes
Offset 25 The main revision for config block.
UINT8 | Reserved [2]
Offset 26-27 Reserved for future use.

Detailed Description

Config Block Header.

Definition at line 30 of file ConfigBlock.h.

The documentation for this struct was generated from the following file:
  • ConfigBlock.h
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
_CONFIG_BLOCK_HEADER Member List

This is the complete list of members for _CONFIG_BLOCK_HEADER, including all inherited members.

Attributes | _CONFIG_BLOCK_HEADER
GuidHob | _CONFIG_BLOCK_HEADER
Reserved | _CONFIG_BLOCK_HEADER
Revision | _CONFIG_BLOCK_HEADER
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: _CONFIG_BLOCK_TABLE_STRUCT Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
_CONFIG_BLOCK_TABLE_STRUCT Struct Reference

Config Block Table Header. More...

#include <ConfigBlock.h>

Collaboration diagram for _CONFIG_BLOCK_TABLE_STRUCT:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 GUID number for main entry of config block.
UINT8 | Rsvd0 [2]
Offset 28-29 Reserved for future use.
UINT16 | NumberOfBlocks
Offset 30-31 Number of config blocks (N)
UINT32 | AvailableSize
Offset 32-35 Current config block table size.

Detailed Description

Config Block Table Header.

Definition at line 50 of file ConfigBlock.h.

The documentation for this struct was generated from the following file:
  • ConfigBlock.h
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
_CONFIG_BLOCK_TABLE_STRUCT Member List

This is the complete list of members for _CONFIG_BLOCK_TABLE_STRUCT, including all inherited members.

AvailableSize | _CONFIG_BLOCK_TABLE_STRUCT
Header | _CONFIG_BLOCK_TABLE_STRUCT
NumberOfBlocks | _CONFIG_BLOCK_TABLE_STRUCT
Rsvd0 | _CONFIG_BLOCK_TABLE_STRUCT
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: _EFI_MM_RESERVED_MMRAM_REGION Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
_EFI_MM_RESERVED_MMRAM_REGION Struct Reference

Structure describing a MMRAM region which cannot be used for the MMRAM heap. More...

#include <PiMultiPhase.h>

Public Attributes

EFI_PHYSICAL_ADDRESS MmramReservedStart
Starting address of the reserved MMRAM area, as it appears while MMRAM is open. More...
UINT64 MmramReservedSize
Number of bytes occupied by the reserved MMRAM area. More...

Detailed Description

Structure describing a MMRAM region which cannot be used for the MMRAM heap.

Definition at line 139 of file PiMultiPhase.h.

Member Data Documentation

◆ MmramReservedSize

UINT64 _EFI_MM_RESERVED_MMRAM_REGION::MmramReservedSize

Number of bytes occupied by the reserved MMRAM area.

A size of zero indicates the last MMRAM area.

Definition at line 149 of file PiMultiPhase.h.

◆ MmramReservedStart

EFI_PHYSICAL_ADDRESS _EFI_MM_RESERVED_MMRAM_REGION::MmramReservedStart

Starting address of the reserved MMRAM area, as it appears while MMRAM is open.

Ignored if MmramReservedSize is 0.

Definition at line 144 of file PiMultiPhase.h.

The documentation for this struct was generated from the following file:
  • PiMultiPhase.h
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
_EFI_MM_RESERVED_MMRAM_REGION Member List

This is the complete list of members for _EFI_MM_RESERVED_MMRAM_REGION, including all inherited members.

MmramReservedSize | _EFI_MM_RESERVED_MMRAM_REGION
MmramReservedStart | _EFI_MM_RESERVED_MMRAM_REGION
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: _EFI_PEI_MP_SERVICES_PPI Struct Reference

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_EFI_PEI_MP_SERVICES_PPI Struct Reference

This PPI is installed by some platform or chipset-specific PEIM that abstracts handling multiprocessor support. More...

#include <MpServices.h>

Collaboration diagram for _EFI_PEI_MP_SERVICES_PPI:
[legend]

Detailed Description

This PPI is installed by some platform or chipset-specific PEIM that abstracts handling multiprocessor support.

Definition at line 265 of file MpServices.h.

The documentation for this struct was generated from the following file:
  • MpServices.h
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: _ITBT_GENERIC_CONFIG Struct Reference

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_ITBT_GENERIC_CONFIG Struct Reference

ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and HOB. More...

#include <PeiITbtGenericStructure.h>

Public Attributes

UINT16 | ITbtForcePowerOnTimeoutInMs
Timeout value for forcing power iTBT controller on every boot/reboot/Sx exit as a precondition for execution of following mailbox communication. More...
UINT16 | ITbtConnectTopologyTimeoutInMs
Timeout value while sending connect topology mailbox command in order to bring all connected TBT devices are available on PCIe before BIOS will enumerate them in BDS (Test) default is 5000 ms
UINT8 | Reserved2
Reserved and previously used for iTbt Security Level.
UINT8 | ITbtPcieTunnelingForUsb4
Disable/Enable PCIe tunneling for USB4. default is enable
UINT8 | Usb4CmMode
USB4 CM mode.
UINT8 | Reserved [1]
Reserved for DWORD alignment.

Detailed Description

ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and HOB.

Definition at line 52 of file PeiITbtGenericStructure.h.

Member Data Documentation

◆ ITbtForcePowerOnTimeoutInMs

UINT16 _ITBT_GENERIC_CONFIG::ITbtForcePowerOnTimeoutInMs

Timeout value for forcing power iTBT controller on every boot/reboot/Sx exit as a precondition for execution of following mailbox communication.

After applying Force Power Thunderbolt BIOS shall poll for iTBT readiness for mailbox communication If TBT cable is disconnected, iTBT microcontrollers are in lower power state. To ensure successful mailbox execution, independently on presence of TBT cable, TBT BIOS shall bring iTBT microcontrollers up by applying Force Power. iTBT microcontrollers will wake up either due to TBT cable presence or Force Power event. (Test) default is 500 ms

Definition at line 64 of file PeiITbtGenericStructure.h.

The documentation for this struct was generated from the following file:
  • PeiITbtGenericStructure.h
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ITbtConnectTopologyTimeoutInMs | _ITBT_GENERIC_CONFIG
ITbtForcePowerOnTimeoutInMs | _ITBT_GENERIC_CONFIG
ITbtPcieTunnelingForUsb4 | _ITBT_GENERIC_CONFIG
Reserved | _ITBT_GENERIC_CONFIG
Reserved2 | _ITBT_GENERIC_CONFIG
Usb4CmMode | _ITBT_GENERIC_CONFIG
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: _ITBT_ROOTPORT_CONFIG Struct Reference

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_ITBT_ROOTPORT_CONFIG Struct Reference

iTBT RootPort Data Structure More...

#include <PeiITbtGenericStructure.h>

Public Attributes

UINT8 | ITbtPcieRootPortEn
Disable/Enable iTBT PCIe Root Port.
UINT8 | Reserved [3]
Reserved for DWORD alignment.

Detailed Description

iTBT RootPort Data Structure

Definition at line 44 of file PeiITbtGenericStructure.h.

The documentation for this struct was generated from the following file:
  • PeiITbtGenericStructure.h
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ITbtPcieRootPortEn | _ITBT_ROOTPORT_CONFIG
Reserved | _ITBT_ROOTPORT_CONFIG
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: _LIST_ENTRY Struct Reference

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_LIST_ENTRY Struct Reference

_LIST_ENTRY structure definition. More...

#include <Base.h>

Collaboration diagram for _LIST_ENTRY:
[legend]

Detailed Description

_LIST_ENTRY structure definition.

Definition at line 247 of file Base.h.

The documentation for this struct was generated from the following file:
  • Base.h
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI Struct Reference

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_PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI Struct Reference

This PPI provides function to install default silicon policy. More...

#include <PeiPreMemSiDefaultPolicy.h>

Public Attributes

PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit
PeiPreMemPolicyInit()

Detailed Description

This PPI provides function to install default silicon policy.

Definition at line 55 of file PeiPreMemSiDefaultPolicy.h.

The documentation for this struct was generated from the following file:
  • PeiPreMemSiDefaultPolicy.h
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PeiPreMemPolicyInit | _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: _PEI_SI_DEFAULT_POLICY_INIT_PPI Struct Reference

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_PEI_SI_DEFAULT_POLICY_INIT_PPI Struct Reference

This PPI provides function to install default silicon policy. More...

#include <PeiSiDefaultPolicy.h>

Public Attributes

PEI_POLICY_INIT PeiPolicyInit
PeiPolicyInit()

Detailed Description

This PPI provides function to install default silicon policy.

Definition at line 55 of file PeiSiDefaultPolicy.h.

The documentation for this struct was generated from the following file:
  • PeiSiDefaultPolicy.h
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PeiPolicyInit | _PEI_SI_DEFAULT_POLICY_INIT_PPI
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: _SI_POLICY_STRUCT Struct Reference

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_SI_POLICY_STRUCT Struct Reference

SI Policy PPI
All SI config block change history will be listed here

. More...

#include <SiPolicyStruct.h>

Collaboration diagram for _SI_POLICY_STRUCT:
[legend]

Public Attributes

CONFIG_BLOCK_TABLE_HEADER TableHeader
Config Block Table Header.

Detailed Description

SI Policy PPI
All SI config block change history will be listed here

.

  • Revision 1:
    • Initial version.

Definition at line 85 of file SiPolicyStruct.h.

The documentation for this struct was generated from the following file:
  • SiPolicyStruct.h
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TableHeader | _SI_POLICY_STRUCT
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: _SI_PREMEM_POLICY_STRUCT Struct Reference

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_SI_PREMEM_POLICY_STRUCT Struct Reference

SI Policy PPI in Pre-Mem
All SI config block change history will be listed here

. More...

#include <SiPolicyStruct.h>

Collaboration diagram for _SI_PREMEM_POLICY_STRUCT:
[legend]

Public Attributes

CONFIG_BLOCK_TABLE_HEADER TableHeader
Config Block Table Header.

Detailed Description

SI Policy PPI in Pre-Mem
All SI config block change history will be listed here

.

  • Revision 1:
    • Initial version.

Definition at line 71 of file SiPolicyStruct.h.

The documentation for this struct was generated from the following file:
  • SiPolicyStruct.h
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TableHeader | _SI_PREMEM_POLICY_STRUCT
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ADR_CONFIG Struct Reference

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ADR_CONFIG Struct Reference

ADR Configuration Revision 1: - Initial version. More...

#include <AdrConfig.h>

Collaboration diagram for ADR_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | AdrEn: 2
Determine if Adr is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
UINT32 | AdrTimerEn: 2
Determine if Adr timer options are enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
UINT32 | AdrTimer1Val: 8
Determines the Timeout value used for the ADR timer 1. A value of zero bypasses the timer.
UINT32 | AdrMultiplier1Val: 3
Specifies the tick frequency upon which the timer 1 will increment. ADR_TIMER_SCALE should be used to encode values.
UINT32 | AdrTimer2Val: 8
Determines the Timeout value used for the ADR timer 2. A value of zero bypasses the timer.
UINT32 | AdrMultiplier2Val: 3
Specifies the tick frequency upon which the timer 2 will increment. ADR_TIMER_SCALE should be used to encode values.
UINT32 | AdrHostPartitionReset: 2
Determine if Host Partition Reset is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
UINT32 | AdrPlatAckEn: 2
Determine if Platform Acknowledge is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
ADR_GLOBAL_RESET_ENABLE AdrSrcOff
Determine which ADR sources are disabled. The code perform clearing bits in ADR Global Reset Enable register. This is first step.
ADR_GLOBAL_RESET_ENABLE AdrSrcOn
Determine which ADR sources are enabled. The code perform setting bits in ADR Global Reset Enable register. This is second step.

Detailed Description

ADR Configuration Revision 1: - Initial version.

Definition at line 97 of file AdrConfig.h.

The documentation for this struct was generated from the following file:
  • AdrConfig.h
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AdrEn | ADR_CONFIG
AdrHostPartitionReset | ADR_CONFIG
AdrMultiplier1Val | ADR_CONFIG
AdrMultiplier2Val | ADR_CONFIG
AdrPlatAckEn | ADR_CONFIG
AdrSrcOff | ADR_CONFIG
AdrSrcOn | ADR_CONFIG
AdrTimer1Val | ADR_CONFIG
AdrTimer2Val | ADR_CONFIG
AdrTimerEn | ADR_CONFIG
Header | ADR_CONFIG
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ADR_GLOBAL_RESET_ENABLE Union Reference

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ADR_GLOBAL_RESET_ENABLE Union Reference

ADR Source Enable. More...

#include <AdrConfig.h>

Detailed Description

ADR Source Enable.

Definition at line 59 of file AdrConfig.h.

The documentation for this union was generated from the following file:
  • AdrConfig.h
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: AMT_DXE_CONFIG Struct Reference

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AMT_DXE_CONFIG Struct Reference

AMT Dxe Configuration Structure. More...

#include <AmtConfig.h>

Collaboration diagram for AMT_DXE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | CiraRequest: 1
Trigger CIRA boot. 0: No CIRA request; 1: Trigger CIRA request.
UINT32 | UnConfigureMe: 1
OEMFlag Bit 15: Unconfigure ME with resetting MEBx password to default. 0: No; 1: Un-configure ME without password.
UINT32 | UsbProvision: 1
Enable/Disable of AMT USB Provisioning. 0: Disable; 1: Enable.
UINT32 | RsvdBits: 29
Reserved for future use & Config block alignment.
AMT_REPORT_ERROR AmtReportError
Function pointer for displaying error message on screen.

Detailed Description

AMT Dxe Configuration Structure.

Revision 1:

  • Initial version.

Definition at line 130 of file AmtConfig.h.

The documentation for this struct was generated from the following file:
  • AmtConfig.h
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AmtReportError | AMT_DXE_CONFIG
CiraRequest | AMT_DXE_CONFIG
Header | AMT_DXE_CONFIG
RsvdBits | AMT_DXE_CONFIG
UnConfigureMe | AMT_DXE_CONFIG
UsbProvision | AMT_DXE_CONFIG
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: AMT_PEI_CONFIG Struct Reference

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AMT_PEI_CONFIG Struct Reference

AMT Pei Configuration Structure. More...

#include <AmtConfig.h>

Collaboration diagram for AMT_PEI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | AmtEnabled: 1
Enable or Disable Intel Active Management Technology feature. More...
UINT32 | WatchDogEnabled: 1
ME WatchDog timer feature. More...
UINT32 | FwProgress: 1
PET Events Progress to receive PET Events. 0: Disable; 1: Enable
UINT32 | AmtSolEnabled: 1
Serial Over Lan retrieved from Mebx. The default value depends on CSME/AMT. 0: Disable, 1: Enable
UINT32 | RsvdBits: 28
Reserved for future use & Config block alignment.
UINT16 | WatchDogTimerOs
OS WatchDog Timer 0: Disable OS WDT won't be started after stopping BIOS WDT even if WatchDogEnabled is 1. More...
UINT16 | WatchDogTimerBios
BIOS WatchDog Timer 0: Disable BIOS WDT won't be started even if WatchDogEnabled is 1. More...

Detailed Description

AMT Pei Configuration Structure.

Revision 1:

  • Initial version.

Definition at line 89 of file AmtConfig.h.

Member Data Documentation

◆ AmtEnabled

UINT32 AMT_PEI_CONFIG::AmtEnabled

Enable or Disable Intel Active Management Technology feature.

If disabled, all Intel AMT features, including Alert Standard Format features, will not be supported. 0: Disable 1: Enable.

Definition at line 97 of file AmtConfig.h.

◆ WatchDogEnabled

UINT32 AMT_PEI_CONFIG::WatchDogEnabled

ME WatchDog timer feature.

If disabled, below WatchDogTimerOs/WatchDogTimerBios will be irrelevant. See WatchDogTimerOs and WatchDogTimerBios description. 0: Disable 1: Enable ME WDT if corresponding timer value is not zero.

Definition at line 104 of file AmtConfig.h.

◆ WatchDogTimerBios

UINT16 AMT_PEI_CONFIG::WatchDogTimerBios

BIOS WatchDog Timer 0: Disable BIOS WDT won't be started even if WatchDogEnabled is 1.

Non zero value - The BIOS WDT is set according to the value and started if WatchDogEnabled is 1.

Definition at line 120 of file AmtConfig.h.

◆ WatchDogTimerOs

UINT16 AMT_PEI_CONFIG::WatchDogTimerOs

OS WatchDog Timer 0: Disable OS WDT won't be started after stopping BIOS WDT even if WatchDogEnabled is 1.

Non zero value - OS WDT will be started after stopping BIOS WDT if WatchDogEnabled is 1. The timer is set according to the value.

Definition at line 114 of file AmtConfig.h.

The documentation for this struct was generated from the following file:
  • AmtConfig.h
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AMT_PEI_CONFIG Member List

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AmtEnabled | AMT_PEI_CONFIG
AmtSolEnabled | AMT_PEI_CONFIG
FwProgress | AMT_PEI_CONFIG
Header | AMT_PEI_CONFIG
RsvdBits | AMT_PEI_CONFIG
WatchDogEnabled | AMT_PEI_CONFIG
WatchDogTimerBios | AMT_PEI_CONFIG
WatchDogTimerOs | AMT_PEI_CONFIG
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: BCLK_CONFIG Struct Reference

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BCLK_CONFIG Struct Reference

BCLK configuration. More...

#include <PmConfig.h>

Collaboration diagram for BCLK_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 | SocBclkPllOn
Controls enable status of SOC BCLK. More...
UINT8 | CpuBclkPllOn
Controls enable status of CPU BCLK. More...

Detailed Description

BCLK configuration.

Only available on projects with SOC and CPU BCLK supported.

Definition at line 497 of file PmConfig.h.

Member Data Documentation

◆ CpuBclkPllOn

UINT8 BCLK_CONFIG::CpuBclkPllOn

Controls enable status of CPU BCLK.

0: HW default, 1: Force enable, 2: Force disable

Definition at line 509 of file PmConfig.h.

◆ SocBclkPllOn

UINT8 BCLK_CONFIG::SocBclkPllOn

Controls enable status of SOC BCLK.

0: HW default, 1: Force enable, 2: Force disable

Definition at line 504 of file PmConfig.h.

The documentation for this struct was generated from the following file:
  • PmConfig.h
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CpuBclkPllOn | BCLK_CONFIG
Header | BCLK_CONFIG
SocBclkPllOn | BCLK_CONFIG
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: CNVI_PIN_MUX Struct Reference

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CNVI_PIN_MUX Struct Reference

CNVi signals pin muxing settings. More...

#include <CnviConfig.h>

Public Attributes

UINT32 | RfReset
RF_RESET# Pin mux configuration. Refer to GPIO_*_MUXING_CNVI_RF_RESET_*.
UINT32 | Clkreq
CLKREQ Pin mux configuration. Refer to GPIO_*_MUXING_CNVI_*_CLKREQ_*.

Detailed Description

CNVi signals pin muxing settings.

If signal can be enable only on a single pin then this parameter is ignored by RC. Refer to GPIO_*_MUXING_CNVI_* in GpioPins*.h for supported settings on a given platform

Definition at line 81 of file CnviConfig.h.

The documentation for this struct was generated from the following file:
  • CnviConfig.h
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Clkreq | CNVI_PIN_MUX
RfReset | CNVI_PIN_MUX
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: CNVI_PREMEM_CONFIG Struct Reference

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CNVI_PREMEM_CONFIG Struct Reference

The CNVI_PREMEM_CONFIG block describes the expected configuration of the CNVi IP. More...

#include <CnviConfig.h>

Collaboration diagram for CNVI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 DdrRfim
The option to enable or disable DDR RFI Mitigation. 0: Disabled, 1: Enabled

Detailed Description

The CNVI_PREMEM_CONFIG block describes the expected configuration of the CNVi IP.

Revision 1: - Initial version.

Definition at line 126 of file CnviConfig.h.

The documentation for this struct was generated from the following file:
  • CnviConfig.h
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DdrRfim | CNVI_PREMEM_CONFIG
Header | CNVI_PREMEM_CONFIG
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: DMI_HW_WIDTH_CONTROL Struct Reference

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DMI_HW_WIDTH_CONTROL Struct Reference

This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec design. More...

#include <ThermalConfig.h>

Public Attributes

UINT32 | DmiTsawEn: 1
DMI Thermal Sensor Autonomous Width Enable.
UINT32 | SuggestedSetting: 1
0: Disable; 1: Enable suggested representative values
UINT32 | RsvdBits0: 6
Reserved bits.
UINT32 | TS0TW: 3
Thermal Sensor 0 Target Width (DmiThermSensWidthx8)
UINT32 | TS1TW: 3
Thermal Sensor 1 Target Width (DmiThermSensWidthx4)
UINT32 | TS2TW: 3
Thermal Sensor 2 Target Width (DmiThermSensWidthx2)
UINT32 | TS3TW: 3
Thermal Sensor 3 Target Width (DmiThermSensWidthx1)
UINT32 | RsvdBits1: 12
Reserved bits.

Detailed Description

This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec design.

When the SuggestedSetting is enabled, the customized values are ignored. Look at DMI_THERMAL_SENSOR_TARGET_WIDTH for possible values

Definition at line 83 of file ThermalConfig.h.

The documentation for this struct was generated from the following file:
  • ThermalConfig.h
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
DMI_HW_WIDTH_CONTROL Member List

This is the complete list of members for DMI_HW_WIDTH_CONTROL, including all inherited members.

DmiTsawEn | DMI_HW_WIDTH_CONTROL
RsvdBits0 | DMI_HW_WIDTH_CONTROL
RsvdBits1 | DMI_HW_WIDTH_CONTROL
SuggestedSetting | DMI_HW_WIDTH_CONTROL
TS0TW | DMI_HW_WIDTH_CONTROL
TS1TW | DMI_HW_WIDTH_CONTROL
TS2TW | DMI_HW_WIDTH_CONTROL
TS3TW | DMI_HW_WIDTH_CONTROL
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: DMI_LANE_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
DMI_LANE_CONFIG Struct Reference

The PCH_DMI_LANE_CONFIG block describes specific lane configuration. More...

#include <PchPcieRpConfig.h>

Public Attributes

UINT32 | DmiTranCoOverEn: 2
Enable/Disable Lane Transmitter Coefficient.
UINT32 | Rsvd1: 6
Reserved.
UINT32 | DmiTranCoOverPostCur: 6
Lane Transmitter Post-Cursor Coefficient Override.
UINT32 | Rsvd2: 2
Reserved.
UINT32 | DmiTranCoOverPreCur: 6
Lane Transmitter Pre-Cursor Coefficient Override.
UINT32 | Rsvd3: 2
Reserved.
UINT32 | DmiUpPortTranPreset: 4
Upstream Port Lane Transmitter Preset.
UINT32 | Rsvd4: 4
Reserved.

Detailed Description

The PCH_DMI_LANE_CONFIG block describes specific lane configuration.

Definition at line 169 of file PchPcieRpConfig.h.

The documentation for this struct was generated from the following file:
  • PchPcieRpConfig.h
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
DMI_LANE_CONFIG Member List

This is the complete list of members for DMI_LANE_CONFIG, including all inherited members.

DmiTranCoOverEn | DMI_LANE_CONFIG
DmiTranCoOverPostCur | DMI_LANE_CONFIG
DmiTranCoOverPreCur | DMI_LANE_CONFIG
DmiUpPortTranPreset | DMI_LANE_CONFIG
Rsvd1 | DMI_LANE_CONFIG
Rsvd2 | DMI_LANE_CONFIG
Rsvd3 | DMI_LANE_CONFIG
Rsvd4 | DMI_LANE_CONFIG
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_CPU Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
EFI_HOB_CPU Struct Reference

Describes processor information, such as address space and I/O space capabilities. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_CPU:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...
UINT8 | SizeOfMemorySpace
Identifies the maximum physical memory addressability of the processor.
UINT8 | SizeOfIoSpace
Identifies the maximum physical I/O addressability of the processor.
UINT8 | Reserved [6]
This field will always be set to zero.

Detailed Description

Describes processor information, such as address space and I/O space capabilities.

Definition at line 445 of file PiHob.h.

Member Data Documentation

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_CPU::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_CPU.

Definition at line 449 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
EFI_HOB_CPU Member List

This is the complete list of members for EFI_HOB_CPU, including all inherited members.

Header | EFI_HOB_CPU
Reserved | EFI_HOB_CPU
SizeOfIoSpace | EFI_HOB_CPU
SizeOfMemorySpace | EFI_HOB_CPU
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_FIRMWARE_VOLUME Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
EFI_HOB_FIRMWARE_VOLUME Struct Reference

Details the location of firmware volumes that contain firmware files. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_FIRMWARE_VOLUME:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...
EFI_PHYSICAL_ADDRESS BaseAddress
The physical memory-mapped base address of the firmware volume.
UINT64 Length
The length in bytes of the firmware volume.

Detailed Description

Details the location of firmware volumes that contain firmware files.

Definition at line 362 of file PiHob.h.

Member Data Documentation

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_FIRMWARE_VOLUME::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_FV.

Definition at line 366 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_FIRMWARE_VOLUME2 Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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EFI_HOB_FIRMWARE_VOLUME2 Struct Reference

Details the location of a firmware volume that was extracted from a file within another firmware volume. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_FIRMWARE_VOLUME2:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...
EFI_PHYSICAL_ADDRESS BaseAddress
The physical memory-mapped base address of the firmware volume.
UINT64 Length
The length in bytes of the firmware volume.
EFI_GUID FvName
The name of the firmware volume.
EFI_GUID FileName
The name of the firmware file that contained this firmware volume.

Detailed Description

Details the location of a firmware volume that was extracted from a file within another firmware volume.

Definition at line 381 of file PiHob.h.

Member Data Documentation

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_FIRMWARE_VOLUME2::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_FV2.

Definition at line 385 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
EFI_HOB_FIRMWARE_VOLUME2 Member List

This is the complete list of members for EFI_HOB_FIRMWARE_VOLUME2, including all inherited members.

BaseAddress | EFI_HOB_FIRMWARE_VOLUME2
FileName | EFI_HOB_FIRMWARE_VOLUME2
FvName | EFI_HOB_FIRMWARE_VOLUME2
Header | EFI_HOB_FIRMWARE_VOLUME2
Length | EFI_HOB_FIRMWARE_VOLUME2
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_FIRMWARE_VOLUME3 Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
EFI_HOB_FIRMWARE_VOLUME3 Struct Reference

Details the location of a firmware volume that was extracted from a file within another firmware volume. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_FIRMWARE_VOLUME3:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...
EFI_PHYSICAL_ADDRESS BaseAddress
The physical memory-mapped base address of the firmware volume.
UINT64 | Length
The length in bytes of the firmware volume.
UINT32 | AuthenticationStatus
The authentication status.
BOOLEAN | ExtractedFv
TRUE if the FV was extracted as a file within another firmware volume. More...
EFI_GUID FvName
The name of the firmware volume. More...
EFI_GUID FileName
The name of the firmware file that contained this firmware volume. More...

Detailed Description

Details the location of a firmware volume that was extracted from a file within another firmware volume.

Definition at line 408 of file PiHob.h.

Member Data Documentation

◆ ExtractedFv

BOOLEAN EFI_HOB_FIRMWARE_VOLUME3::ExtractedFv

TRUE if the FV was extracted as a file within another firmware volume.

FALSE otherwise.

Definition at line 429 of file PiHob.h.

◆ FileName

EFI_GUID EFI_HOB_FIRMWARE_VOLUME3::FileName

The name of the firmware file that contained this firmware volume.

Valid only if IsExtractedFv is TRUE.

Definition at line 439 of file PiHob.h.

◆ FvName

EFI_GUID EFI_HOB_FIRMWARE_VOLUME3::FvName

The name of the firmware volume.

Valid only if IsExtractedFv is TRUE.

Definition at line 434 of file PiHob.h.

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_FIRMWARE_VOLUME3::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_FV3.

Definition at line 412 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
EFI_HOB_FIRMWARE_VOLUME3 Member List

This is the complete list of members for EFI_HOB_FIRMWARE_VOLUME3, including all inherited members.

AuthenticationStatus | EFI_HOB_FIRMWARE_VOLUME3
BaseAddress | EFI_HOB_FIRMWARE_VOLUME3
ExtractedFv | EFI_HOB_FIRMWARE_VOLUME3
FileName | EFI_HOB_FIRMWARE_VOLUME3
FvName | EFI_HOB_FIRMWARE_VOLUME3
Header | EFI_HOB_FIRMWARE_VOLUME3
Length | EFI_HOB_FIRMWARE_VOLUME3
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_GENERIC_HEADER Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
EFI_HOB_GENERIC_HEADER Struct Reference

Describes the format and size of the data inside the HOB. More...

#include <PiHob.h>

Public Attributes

UINT16 | HobType
Identifies the HOB data structure type.
UINT16 | HobLength
The length in bytes of the HOB.
UINT32 | Reserved
This field must always be set to zero.

Detailed Description

Describes the format and size of the data inside the HOB.

All HOBs must contain this generic HOB header.

Definition at line 36 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
EFI_HOB_GENERIC_HEADER Member List

This is the complete list of members for EFI_HOB_GENERIC_HEADER, including all inherited members.

HobLength | EFI_HOB_GENERIC_HEADER
HobType | EFI_HOB_GENERIC_HEADER
Reserved | EFI_HOB_GENERIC_HEADER
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_GUID_TYPE Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
EFI_HOB_GUID_TYPE Struct Reference

Allows writers of executable content in the HOB producer phase to maintain and manage HOBs with specific GUID. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_GUID_TYPE:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...
EFI_GUID Name
A GUID that defines the contents of this HOB.

Detailed Description

Allows writers of executable content in the HOB producer phase to maintain and manage HOBs with specific GUID.

Definition at line 345 of file PiHob.h.

Member Data Documentation

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_GUID_TYPE::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_GUID_EXTENSION.

Definition at line 349 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
EFI_HOB_GUID_TYPE Member List

This is the complete list of members for EFI_HOB_GUID_TYPE, including all inherited members.

Header | EFI_HOB_GUID_TYPE
Name | EFI_HOB_GUID_TYPE
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_HANDOFF_INFO_TABLE Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
EFI_HOB_HANDOFF_INFO_TABLE Struct Reference

Contains general state information used by the HOB producer phase. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_HANDOFF_INFO_TABLE:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...
UINT32 | Version
The version number pertaining to the PHIT HOB definition. More...
EFI_BOOT_MODE | BootMode
The system boot mode as determined during the HOB producer phase.
EFI_PHYSICAL_ADDRESS EfiMemoryTop
The highest address location of memory that is allocated for use by the HOB producer phase. More...
EFI_PHYSICAL_ADDRESS EfiMemoryBottom
The lowest address location of memory that is allocated for use by the HOB producer phase.
EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop
The highest address location of free memory that is currently available for use by the HOB producer phase.
EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom
The lowest address location of free memory that is available for use by the HOB producer phase.
EFI_PHYSICAL_ADDRESS EfiEndOfHobList
The end of the HOB list.

Detailed Description

Contains general state information used by the HOB producer phase.

This HOB must be the first one in the HOB list.

Definition at line 60 of file PiHob.h.

Member Data Documentation

◆ EfiMemoryTop

EFI_PHYSICAL_ADDRESS EFI_HOB_HANDOFF_INFO_TABLE::EfiMemoryTop

The highest address location of memory that is allocated for use by the HOB producer phase.

This address must be 4-KB aligned to meet page restrictions of UEFI.

Definition at line 79 of file PiHob.h.

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_HANDOFF_INFO_TABLE::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_HANDOFF.

Definition at line 64 of file PiHob.h.

◆ Version

UINT32 EFI_HOB_HANDOFF_INFO_TABLE::Version

The version number pertaining to the PHIT HOB definition.

This value is four bytes in length to provide an 8-byte aligned entry when it is combined with the 4-byte BootMode.

Definition at line 70 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
EFI_HOB_HANDOFF_INFO_TABLE Member List

This is the complete list of members for EFI_HOB_HANDOFF_INFO_TABLE, including all inherited members.

BootMode | EFI_HOB_HANDOFF_INFO_TABLE
EfiEndOfHobList | EFI_HOB_HANDOFF_INFO_TABLE
EfiFreeMemoryBottom | EFI_HOB_HANDOFF_INFO_TABLE
EfiFreeMemoryTop | EFI_HOB_HANDOFF_INFO_TABLE
EfiMemoryBottom | EFI_HOB_HANDOFF_INFO_TABLE
EfiMemoryTop | EFI_HOB_HANDOFF_INFO_TABLE
Header | EFI_HOB_HANDOFF_INFO_TABLE
Version | EFI_HOB_HANDOFF_INFO_TABLE
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_MEMORY_ALLOCATION Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
EFI_HOB_MEMORY_ALLOCATION Struct Reference

Describes all memory ranges used during the HOB producer phase that exist outside the HOB list. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_MEMORY_ALLOCATION:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...
EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor
An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the various attributes of the logical memory allocation.

Detailed Description

Describes all memory ranges used during the HOB producer phase that exist outside the HOB list.

This HOB type describes how memory is used, not the physical attributes of memory.

Definition at line 144 of file PiHob.h.

Member Data Documentation

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_MEMORY_ALLOCATION::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.

Definition at line 148 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
EFI_HOB_MEMORY_ALLOCATION Member List

This is the complete list of members for EFI_HOB_MEMORY_ALLOCATION, including all inherited members.

AllocDescriptor | EFI_HOB_MEMORY_ALLOCATION
Header | EFI_HOB_MEMORY_ALLOCATION
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_MEMORY_ALLOCATION_BSP_STORE Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
EFI_HOB_MEMORY_ALLOCATION_BSP_STORE Struct Reference

Defines the location of the boot-strap processor (BSP) BSPStore ("Backing Store Pointer Store"). More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_MEMORY_ALLOCATION_BSP_STORE:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...
EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor
An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the various attributes of the logical memory allocation.

Detailed Description

Defines the location of the boot-strap processor (BSP) BSPStore ("Backing Store Pointer Store").

This HOB is valid for the Itanium processor family only register overflow store.

Definition at line 183 of file PiHob.h.

Member Data Documentation

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_MEMORY_ALLOCATION_BSP_STORE::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.

Definition at line 187 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
EFI_HOB_MEMORY_ALLOCATION_BSP_STORE Member List

This is the complete list of members for EFI_HOB_MEMORY_ALLOCATION_BSP_STORE, including all inherited members.

AllocDescriptor | EFI_HOB_MEMORY_ALLOCATION_BSP_STORE
Header | EFI_HOB_MEMORY_ALLOCATION_BSP_STORE
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_MEMORY_ALLOCATION_HEADER Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
EFI_HOB_MEMORY_ALLOCATION_HEADER Struct Reference

EFI_HOB_MEMORY_ALLOCATION_HEADER describes the various attributes of the logical memory allocation. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_MEMORY_ALLOCATION_HEADER:
[legend]

Public Attributes

EFI_GUID Name
A GUID that defines the memory allocation region's type and purpose, as well as other fields within the memory allocation HOB. More...
EFI_PHYSICAL_ADDRESS MemoryBaseAddress
The base address of memory allocated by this HOB. More...
UINT64 | MemoryLength
The length in bytes of memory allocated by this HOB.
EFI_MEMORY_TYPE | MemoryType
Defines the type of memory allocated by this HOB. More...
UINT8 | Reserved [4]
Padding for Itanium processor family.

Detailed Description

EFI_HOB_MEMORY_ALLOCATION_HEADER describes the various attributes of the logical memory allocation.

The type field will be used for subsequent inclusion in the UEFI memory map.

Definition at line 104 of file PiHob.h.

Member Data Documentation

◆ MemoryBaseAddress

EFI_PHYSICAL_ADDRESS EFI_HOB_MEMORY_ALLOCATION_HEADER::MemoryBaseAddress

The base address of memory allocated by this HOB.

Type EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in the UEFI 2.0 specification.

Definition at line 119 of file PiHob.h.

◆ MemoryType

EFI_MEMORY_TYPE EFI_HOB_MEMORY_ALLOCATION_HEADER::MemoryType

Defines the type of memory allocated by this HOB.

The memory type definition follows the EFI_MEMORY_TYPE definition. Type EFI_MEMORY_TYPE is defined in AllocatePages() in the UEFI 2.0 specification.

Definition at line 131 of file PiHob.h.

◆ Name

EFI_GUID EFI_HOB_MEMORY_ALLOCATION_HEADER::Name

A GUID that defines the memory allocation region's type and purpose, as well as other fields within the memory allocation HOB.

This GUID is used to define the additional data within the HOB that may be present for the memory allocation HOB. Type EFI_GUID is defined in InstallProtocolInterface() in the UEFI 2.0 specification.

Definition at line 112 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
EFI_HOB_MEMORY_ALLOCATION_HEADER Member List

This is the complete list of members for EFI_HOB_MEMORY_ALLOCATION_HEADER, including all inherited members.

MemoryBaseAddress | EFI_HOB_MEMORY_ALLOCATION_HEADER
MemoryLength | EFI_HOB_MEMORY_ALLOCATION_HEADER
MemoryType | EFI_HOB_MEMORY_ALLOCATION_HEADER
Name | EFI_HOB_MEMORY_ALLOCATION_HEADER
Reserved | EFI_HOB_MEMORY_ALLOCATION_HEADER
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_MEMORY_ALLOCATION_MODULE Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
EFI_HOB_MEMORY_ALLOCATION_MODULE Struct Reference

Defines the location and entry point of the HOB consumer phase. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_MEMORY_ALLOCATION_MODULE:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...
EFI_HOB_MEMORY_ALLOCATION_HEADER MemoryAllocationHeader
An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the various attributes of the logical memory allocation.
EFI_GUID ModuleName
The GUID specifying the values of the firmware file system name that contains the HOB consumer phase component.
EFI_PHYSICAL_ADDRESS EntryPoint
The address of the memory-mapped firmware volume that contains the HOB consumer phase firmware file.

Detailed Description

Defines the location and entry point of the HOB consumer phase.

Definition at line 198 of file PiHob.h.

Member Data Documentation

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_MEMORY_ALLOCATION_MODULE::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.

Definition at line 202 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
EFI_HOB_MEMORY_ALLOCATION_MODULE Member List

This is the complete list of members for EFI_HOB_MEMORY_ALLOCATION_MODULE, including all inherited members.

EntryPoint | EFI_HOB_MEMORY_ALLOCATION_MODULE
Header | EFI_HOB_MEMORY_ALLOCATION_MODULE
MemoryAllocationHeader | EFI_HOB_MEMORY_ALLOCATION_MODULE
ModuleName | EFI_HOB_MEMORY_ALLOCATION_MODULE
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_MEMORY_ALLOCATION_STACK Struct Reference

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EFI_HOB_MEMORY_ALLOCATION_STACK Struct Reference

Describes the memory stack that is produced by the HOB producer phase and upon which all post-memory-installed executable content in the HOB producer phase is executing. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_MEMORY_ALLOCATION_STACK:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...
EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor
An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the various attributes of the logical memory allocation.

Detailed Description

Describes the memory stack that is produced by the HOB producer phase and upon which all post-memory-installed executable content in the HOB producer phase is executing.

Definition at line 165 of file PiHob.h.

Member Data Documentation

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_MEMORY_ALLOCATION_STACK::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.

Definition at line 169 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
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AllocDescriptor | EFI_HOB_MEMORY_ALLOCATION_STACK
Header | EFI_HOB_MEMORY_ALLOCATION_STACK
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_MEMORY_POOL Struct Reference

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EFI_HOB_MEMORY_POOL Struct Reference

Describes pool memory allocations. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_MEMORY_POOL:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...

Detailed Description

Describes pool memory allocations.

Definition at line 467 of file PiHob.h.

Member Data Documentation

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_MEMORY_POOL::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_MEMORY_POOL.

Definition at line 471 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
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EFI_HOB_MEMORY_POOL Member List

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Header | EFI_HOB_MEMORY_POOL
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_RESOURCE_DESCRIPTOR Struct Reference

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EFI_HOB_RESOURCE_DESCRIPTOR Struct Reference

Describes the resource properties of all fixed, nonrelocatable resource ranges found on the processor host bus during the HOB producer phase. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_RESOURCE_DESCRIPTOR:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...
EFI_GUID Owner
A GUID representing the owner of the resource. More...
EFI_RESOURCE_TYPE ResourceType
The resource type enumeration as defined by EFI_RESOURCE_TYPE.
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute
Resource attributes as defined by EFI_RESOURCE_ATTRIBUTE_TYPE.
EFI_PHYSICAL_ADDRESS PhysicalStart
The physical start address of the resource region.
UINT64 ResourceLength
The number of bytes of the resource region.

Detailed Description

Describes the resource properties of all fixed, nonrelocatable resource ranges found on the processor host bus during the HOB producer phase.

Definition at line 313 of file PiHob.h.

Member Data Documentation

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_RESOURCE_DESCRIPTOR::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_RESOURCE_DESCRIPTOR.

Definition at line 317 of file PiHob.h.

◆ Owner

EFI_GUID EFI_HOB_RESOURCE_DESCRIPTOR::Owner

A GUID representing the owner of the resource.

This GUID is used by HOB consumer phase components to correlate device ownership of a resource.

Definition at line 322 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
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Header | EFI_HOB_RESOURCE_DESCRIPTOR
Owner | EFI_HOB_RESOURCE_DESCRIPTOR
PhysicalStart | EFI_HOB_RESOURCE_DESCRIPTOR
ResourceAttribute | EFI_HOB_RESOURCE_DESCRIPTOR
ResourceLength | EFI_HOB_RESOURCE_DESCRIPTOR
ResourceType | EFI_HOB_RESOURCE_DESCRIPTOR
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_UEFI_CAPSULE Struct Reference

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EFI_HOB_UEFI_CAPSULE Struct Reference

Each UEFI capsule HOB details the location of a UEFI capsule. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_UEFI_CAPSULE:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header where Header.HobType = EFI_HOB_TYPE_UEFI_CAPSULE.
EFI_PHYSICAL_ADDRESS BaseAddress
The physical memory-mapped base address of an UEFI capsule. More...

Detailed Description

Each UEFI capsule HOB details the location of a UEFI capsule.

It includes a base address and length which is based upon memory blocks with a EFI_CAPSULE_HEADER and the associated CapsuleImageSize-based payloads. These HOB's shall be created by the PEI PI firmware sometime after the UEFI UpdateCapsule service invocation with the CAPSULE_FLAGS_POPULATE_SYSTEM_TABLE flag set in the EFI_CAPSULE_HEADER.

Definition at line 481 of file PiHob.h.

Member Data Documentation

◆ BaseAddress

EFI_PHYSICAL_ADDRESS EFI_HOB_UEFI_CAPSULE::BaseAddress

The physical memory-mapped base address of an UEFI capsule.

This value is set to point to the base of the contiguous memory of the UEFI capsule. The length of the contiguous memory in bytes.

Definition at line 492 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
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BaseAddress | EFI_HOB_UEFI_CAPSULE
Header | EFI_HOB_UEFI_CAPSULE
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_IP_ADDRESS Union Reference

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EFI_IP_ADDRESS Union Reference

16-byte buffer aligned on a 4-byte boundary. More...

#include <UefiBaseType.h>

Collaboration diagram for EFI_IP_ADDRESS:
[legend]

Detailed Description

16-byte buffer aligned on a 4-byte boundary.

An IPv4 or IPv6 internet protocol address.

Definition at line 103 of file UefiBaseType.h.

The documentation for this union was generated from the following file:
  • UefiBaseType.h
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_MAC_ADDRESS Struct Reference

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EFI_MAC_ADDRESS Struct Reference

32-byte buffer containing a network Media Access Control address. More...

#include <UefiBaseType.h>

Detailed Description

32-byte buffer containing a network Media Access Control address.

Definition at line 95 of file UefiBaseType.h.

The documentation for this struct was generated from the following file:
  • UefiBaseType.h
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_MMRAM_DESCRIPTOR Struct Reference

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EFI_MMRAM_DESCRIPTOR Struct Reference

Structure describing a MMRAM region and its accessibility attributes. More...

#include <PiMultiPhase.h>

Public Attributes

EFI_PHYSICAL_ADDRESS PhysicalStart
Designates the physical address of the MMRAM in memory. More...
EFI_PHYSICAL_ADDRESS CpuStart
Designates the address of the MMRAM, as seen by software executing on the processors. More...
UINT64 | PhysicalSize
Describes the number of bytes in the MMRAM region.
UINT64 | RegionState
Describes the accessibility attributes of the MMRAM. More...

Detailed Description

Structure describing a MMRAM region and its accessibility attributes.

Definition at line 109 of file PiMultiPhase.h.

Member Data Documentation

◆ CpuStart

EFI_PHYSICAL_ADDRESS EFI_MMRAM_DESCRIPTOR::CpuStart

Designates the address of the MMRAM, as seen by software executing on the processors.

This address may or may not match PhysicalStart.

Definition at line 120 of file PiMultiPhase.h.

◆ PhysicalStart

EFI_PHYSICAL_ADDRESS EFI_MMRAM_DESCRIPTOR::PhysicalStart

Designates the physical address of the MMRAM in memory.

This view of memory is the same as seen by I/O-based agents, for example, but it may not be the address seen by the processors.

Definition at line 115 of file PiMultiPhase.h.

◆ RegionState

UINT64 EFI_MMRAM_DESCRIPTOR::RegionState

Describes the accessibility attributes of the MMRAM.

These attributes include the hardware state (e.g., Open/Closed/Locked), capability (e.g., cacheable), logical allocation (e.g., allocated), and pre-use initialization (e.g., needs testing/ECC initialization).

Definition at line 131 of file PiMultiPhase.h.

The documentation for this struct was generated from the following file:
  • PiMultiPhase.h
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CpuStart | EFI_MMRAM_DESCRIPTOR
PhysicalSize | EFI_MMRAM_DESCRIPTOR
PhysicalStart | EFI_MMRAM_DESCRIPTOR
RegionState | EFI_MMRAM_DESCRIPTOR
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_PEI_HOB_POINTERS Union Reference

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EFI_PEI_HOB_POINTERS Union Reference

Union of all the possible HOB Types. More...

#include <PiHob.h>

Collaboration diagram for EFI_PEI_HOB_POINTERS:
[legend]

Detailed Description

Union of all the possible HOB Types.

Definition at line 499 of file PiHob.h.

The documentation for this union was generated from the following file:
  • PiHob.h


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_TIME Struct Reference

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EFI_TIME Struct Reference

EFI Time Abstraction: Year: 1900 - 9999 Month: 1 - 12 Day: 1 - 31 Hour: 0 - 23 Minute: 0 - 59 Second: 0 - 59 Nanosecond: 0 - 999,999,999 TimeZone: -1440 to 1440 or 2047. More...

#include <UefiBaseType.h>

Detailed Description

EFI Time Abstraction: Year: 1900 - 9999 Month: 1 - 12 Day: 1 - 31 Hour: 0 - 23 Minute: 0 - 59 Second: 0 - 59 Nanosecond: 0 - 999,999,999 TimeZone: -1440 to 1440 or 2047.

Definition at line 68 of file UefiBaseType.h.

The documentation for this struct was generated from the following file:
  • UefiBaseType.h


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: FIVR_EXT_RAIL_CONFIG Struct Reference

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FIVR_EXT_RAIL_CONFIG Struct Reference

Structure for V1p05/Vnn VR rail configuration. More...

#include <FivrConfig.h>

Public Attributes

UINT32 | EnabledStates: 6
Mask to enable the usage of external VR rail in specific S0ix or Sx states Use values from FIVR_RAIL_SX_STATE The default is FivrRailDisabled.
UINT32 | Voltage: 11
VR rail voltage value that will be used in S0i2/S0i3 states. More...
UINT32 | RsvdBits1: 15
UINT32 Alignement.
UINT32 | CtrlRampTmr: 8
This register holds the control hold off values to be used when changing the rail control for external bypass value in us.
UINT32 | SupportedVoltageStates: 4
Mask to set the supported configuration in VR rail. More...
UINT32 | IccMaximum: 16
VR rail Icc Maximum Value Granularity of this setting is 1mA and maximal possible value is 500mA The default is 0mA .
UINT32 | RsvdBits2: 4
UINT32 Alignment.

Detailed Description

Structure for V1p05/Vnn VR rail configuration.

Definition at line 69 of file FivrConfig.h.

Member Data Documentation

◆ SupportedVoltageStates

UINT32 FIVR_EXT_RAIL_CONFIG::SupportedVoltageStates

Mask to set the supported configuration in VR rail.

Use values from FIVR_RAIL_SUPPORTED_VOLTAGE

Definition at line 97 of file FivrConfig.h.

◆ Voltage

UINT32 FIVR_EXT_RAIL_CONFIG::Voltage

VR rail voltage value that will be used in S0i2/S0i3 states.

This value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) The default for Vnn is set to 420 - 1050 mV.

Definition at line 82 of file FivrConfig.h.

The documentation for this struct was generated from the following file:
  • FivrConfig.h


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FIVR_EXT_RAIL_CONFIG Member List

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CtrlRampTmr | FIVR_EXT_RAIL_CONFIG
EnabledStates | FIVR_EXT_RAIL_CONFIG
IccMaximum | FIVR_EXT_RAIL_CONFIG
RsvdBits1 | FIVR_EXT_RAIL_CONFIG
RsvdBits2 | FIVR_EXT_RAIL_CONFIG
SupportedVoltageStates | FIVR_EXT_RAIL_CONFIG
Voltage | FIVR_EXT_RAIL_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: FIVR_VCCIN_AUX_CONFIG Struct Reference

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FIVR_VCCIN_AUX_CONFIG Struct Reference

Structure for VCCIN_AUX voltage rail configuration. More...

#include <FivrConfig.h>

Public Attributes

UINT8 | LowToHighCurModeVolTranTime
Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage. More...
UINT8 | RetToHighCurModeVolTranTime
Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage. More...
UINT8 | RetToLowCurModeVolTranTime
Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage. More...
UINT32 | OffToHighCurModeVolTranTime: 11
Transition time in microseconds from Off (0V) to High Current Mode Voltage. More...

Detailed Description

Structure for VCCIN_AUX voltage rail configuration.

Definition at line 116 of file FivrConfig.h.

Member Data Documentation

◆ LowToHighCurModeVolTranTime

UINT8 FIVR_VCCIN_AUX_CONFIG::LowToHighCurModeVolTranTime

Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage.

Voltage transition time required by motherboard voltage regulator when PCH changes the VCCIN_AUX regulator set point from the low current mode voltage and high current mode voltage. This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to low current mode voltage. The default is 0xC .

Definition at line 125 of file FivrConfig.h.

◆ OffToHighCurModeVolTranTime

UINT32 FIVR_VCCIN_AUX_CONFIG::OffToHighCurModeVolTranTime

Transition time in microseconds from Off (0V) to High Current Mode Voltage.

Voltage transition time required by motherboard voltage regulator when PCH changes the VCCIN_AUX regulator set point from 0V to the high current mode voltage. This field has 1us resolution. 0 = Transition to 0V is disabled Setting this field to 0 sets VCCIN_AUX as a fixed rail that stays on in all S0 & Sx power states after initial start up on G3 exit The default is 0x96 .

Definition at line 157 of file FivrConfig.h.

◆ RetToHighCurModeVolTranTime

UINT8 FIVR_VCCIN_AUX_CONFIG::RetToHighCurModeVolTranTime

Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage.

Voltage transition time required by motherboard voltage regulator when PCH changes the VCCIN_AUX regulator set point from the retention mode voltage to high current mode voltage. This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to retention voltage. The default is 0x36 .

Definition at line 135 of file FivrConfig.h.

◆ RetToLowCurModeVolTranTime

UINT8 FIVR_VCCIN_AUX_CONFIG::RetToLowCurModeVolTranTime

Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage.

Voltage transition time required by motherboard voltage regulator when PCH changes the VCCIN_AUX regulator set point from the retention mode voltage to low current mode voltage. This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to retention voltage. The default is 0x2B .

Definition at line 145 of file FivrConfig.h.

The documentation for this struct was generated from the following file:
  • FivrConfig.h


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LowToHighCurModeVolTranTime | FIVR_VCCIN_AUX_CONFIG
OffToHighCurModeVolTranTime | FIVR_VCCIN_AUX_CONFIG
RetToHighCurModeVolTranTime | FIVR_VCCIN_AUX_CONFIG
RetToLowCurModeVolTranTime | FIVR_VCCIN_AUX_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: FSP_ERROR_INFO_HOB Struct Reference

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FSP_ERROR_INFO_HOB Struct Reference

FSP Error Information Block. More...

#include <FspErrorInfo.h>

Collaboration diagram for FSP_ERROR_INFO_HOB:
[legend]

Public Attributes

EFI_HOB_GUID_TYPE GuidHob
GUID HOB header.
EFI_STATUS_CODE_TYPE | Type
ReportStatusCode () type identifier.
EFI_STATUS_CODE_VALUE | Value
ReportStatusCode () value.
UINT32 | Instance
ReportStatusCode () Instance number.
EFI_GUID CallerId
Optional GUID which may be used to identify which internal component of the FSP was executing at the time of the error.
EFI_GUID ErrorType
GUID identifying the nature of the fatal error.
UINT32 | Status
EFI_STATUS code describing the error encountered.

Detailed Description

FSP Error Information Block.

Definition at line 60 of file FspErrorInfo.h.

The documentation for this struct was generated from the following file:
  • FspErrorInfo.h


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CallerId | FSP_ERROR_INFO_HOB
ErrorType | FSP_ERROR_INFO_HOB
GuidHob | FSP_ERROR_INFO_HOB
Instance | FSP_ERROR_INFO_HOB
Status | FSP_ERROR_INFO_HOB
Type | FSP_ERROR_INFO_HOB
Value | FSP_ERROR_INFO_HOB


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: FSPM_ARCH_CONFIG_PPI Struct Reference

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FSPM_ARCH_CONFIG_PPI Struct Reference

This PPI provides FSP-M Arch Config PPI. More...

#include <FspmArchConfigPpi.h>

Detailed Description

This PPI provides FSP-M Arch Config PPI.

Definition at line 32 of file FspmArchConfigPpi.h.

The documentation for this struct was generated from the following file:
  • FspmArchConfigPpi.h


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: GBE_CONFIG Struct Reference

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GBE_CONFIG Struct Reference

PCH intergrated GBE controller configuration settings. More...

#include <GbeConfig.h>

Collaboration diagram for GBE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Enable: 1
Determines if enable PCH internal GBE, 0: Disable; 1: Enable. More...
UINT32 | LtrEnable: 1
0: Disable; 1: Enable LTR capabilty of PCH internal LAN.
UINT32 | PchWOLFastSupport: 1
Deprecated. More...
UINT32 | RsvdBits0: 29
Reserved bits.

Detailed Description

PCH intergrated GBE controller configuration settings.

Definition at line 46 of file GbeConfig.h.

Member Data Documentation

◆ Enable

UINT32 GBE_CONFIG::Enable

Determines if enable PCH internal GBE, 0: Disable; 1: Enable.

When Enable is changed (from disabled to enabled or from enabled to disabled), it needs to set LAN Disable regsiter, which might be locked by FDSWL register. So it's recommendated to issue a global reset when changing the status for PCH Internal LAN.

Definition at line 54 of file GbeConfig.h.

◆ PchWOLFastSupport

UINT32 GBE_CONFIG::PchWOLFastSupport

Deprecated.

Unused in MTL. Kept for compatibility. Enables bit B_PCH_ACPI_GPE0_EN_127_96_PME_B0 during PchLanSxCallback in PchLanSxSmm.

Definition at line 61 of file GbeConfig.h.

The documentation for this struct was generated from the following file:
  • GbeConfig.h


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GBE_CONFIG Member List

This is the complete list of members for GBE_CONFIG, including all inherited members.

Enable | GBE_CONFIG
Header | GBE_CONFIG
LtrEnable | GBE_CONFIG
PchWOLFastSupport | GBE_CONFIG
RsvdBits0 | GBE_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: GNA_CONFIG Struct Reference

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GNA_CONFIG Struct Reference

GNA config block for configuring GNA. More...

#include <GnaConfig.h>

Collaboration diagram for GNA_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT32 | GnaEnable: 1
Offset 28:0 This policy enables the GNA Device (SA Device 8) if supported. More...
UINT32 | RsvdBits0: 31
Offset 28:1 :Reserved for future use.

Detailed Description

GNA config block for configuring GNA.

Revision 1:

  • Initial version.

Definition at line 45 of file GnaConfig.h.

Member Data Documentation

◆ GnaEnable

UINT32 GNA_CONFIG::GnaEnable

Offset 28:0 This policy enables the GNA Device (SA Device 8) if supported.

If FALSE, all other policies in this config block will be ignored. 1=TRUE; 0=FALSE.

Definition at line 54 of file GnaConfig.h.

The documentation for this struct was generated from the following file:
  • GnaConfig.h


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This is the complete list of members for GNA_CONFIG, including all inherited members.

GnaEnable | GNA_CONFIG
Header | GNA_CONFIG
RsvdBits0 | GNA_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: GPIO_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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GPIO_CONFIG Struct Reference

GPIO configuration structure used for pin programming. More...

#include <GpioConfig.h>

Public Attributes

UINT32 | PadMode: 5
Pad Mode Pad can be set as GPIO or one of its native functions. More...
UINT32 | HostSoftPadOwn: 2
Host Software Pad Ownership Set pad to ACPI mode or GPIO Driver Mode. More...
UINT32 | Direction: 6
GPIO Direction Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both. More...
UINT32 | OutputState: 2
Output State Set Pad output value. More...
UINT32 | InterruptConfig: 9
GPIO Interrupt Configuration Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). More...
UINT32 | PowerConfig: 8
GPIO Power Configuration. More...
UINT32 | ElectricalConfig: 9
GPIO Electrical Configuration This setting controls pads termination and voltage tolerance. More...
UINT32 | LockConfig: 4
GPIO Lock Configuration This setting controls pads lock. More...
UINT32 | OtherSettings: 2
Additional GPIO configuration Refer to definition of GPIO_OTHER_CONFIG for supported settings.
UINT32 | RsvdBits: 17
Reserved bits for future extension.

Detailed Description

GPIO configuration structure used for pin programming.

Structure contains fields that can be used to configure pad.

Definition at line 55 of file GpioConfig.h.

Member Data Documentation

◆ Direction

UINT32 GPIO_CONFIG::Direction

GPIO Direction Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.

Refer to definition of GPIO_DIRECTION for supported settings.

Definition at line 76 of file GpioConfig.h.

◆ ElectricalConfig

UINT32 GPIO_CONFIG::ElectricalConfig

GPIO Electrical Configuration This setting controls pads termination and voltage tolerance.

Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.

Definition at line 102 of file GpioConfig.h.

◆ HostSoftPadOwn

UINT32 GPIO_CONFIG::HostSoftPadOwn

Host Software Pad Ownership Set pad to ACPI mode or GPIO Driver Mode.

Refer to definition of GPIO_HOSTSW_OWN.

Definition at line 70 of file GpioConfig.h.

◆ InterruptConfig

UINT32 GPIO_CONFIG::InterruptConfig

GPIO Interrupt Configuration Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).

This setting is applicable only if GPIO is in GpioMode with input enabled. Refer to definition of GPIO_INT_CONFIG for supported settings.

Definition at line 90 of file GpioConfig.h.

◆ LockConfig

UINT32 GPIO_CONFIG::LockConfig

GPIO Lock Configuration This setting controls pads lock.

Refer to definition of GPIO_LOCK_CONFIG for supported settings.

Definition at line 108 of file GpioConfig.h.

◆ OutputState

UINT32 GPIO_CONFIG::OutputState

Output State Set Pad output value.

Refer to definition of GPIO_OUTPUT_STATE for supported settings. This setting takes place when output is enabled.

Definition at line 83 of file GpioConfig.h.

◆ PadMode

UINT32 GPIO_CONFIG::PadMode

Pad Mode Pad can be set as GPIO or one of its native functions.

When in native mode setting Direction (except Inversion), OutputState, InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary. Refer to definition of GPIO_PAD_MODE. Refer to EDS for each native mode according to the pad.

Definition at line 64 of file GpioConfig.h.

◆ PowerConfig

UINT32 GPIO_CONFIG::PowerConfig

GPIO Power Configuration.

This setting controls Pad Reset Configuration. Refer to definition of GPIO_RESET_CONFIG for supported settings.

Definition at line 96 of file GpioConfig.h.

The documentation for this struct was generated from the following file:
  • GpioConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
GPIO_CONFIG Member List

This is the complete list of members for GPIO_CONFIG, including all inherited members.

Direction | GPIO_CONFIG
ElectricalConfig | GPIO_CONFIG
HostSoftPadOwn | GPIO_CONFIG
InterruptConfig | GPIO_CONFIG
LockConfig | GPIO_CONFIG
OtherSettings | GPIO_CONFIG
OutputState | GPIO_CONFIG
PadMode | GPIO_CONFIG
PowerConfig | GPIO_CONFIG
RsvdBits | GPIO_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: GUID Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
List of all members
GUID Struct Reference

128 bit buffer containing a unique identifier value. More...

#include <Base.h>

Detailed Description

128 bit buffer containing a unique identifier value.

Unless otherwise specified, aligned on a 64 bit boundary.

Definition at line 213 of file Base.h.

The documentation for this struct was generated from the following file:
  • Base.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
GUID Member List

This is the complete list of members for GUID, including all inherited members.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: HDA_LINK_DMIC Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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HDA_LINK_DMIC Struct Reference

HD Audio DMIC Interface Policies. More...

#include <HdAudioConfig.h>

Public Attributes

UINT32 | Enable: 1
HDA DMIC interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: Enable.
UINT32 | DmicClockSelect: 2
DMIC link clock select: 0: Both, 1: ClkA, 2: ClkB; default is "Both".
HDA_DMIC_PIN_MUX | PinMux
Pin mux configuration.

Detailed Description

HD Audio DMIC Interface Policies.

Definition at line 134 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
HDA_LINK_DMIC Member List

This is the complete list of members for HDA_LINK_DMIC, including all inherited members.

DmicClockSelect | HDA_LINK_DMIC
Enable | HDA_LINK_DMIC
PinMux | HDA_LINK_DMIC


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: HDA_LINK_HDA Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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HDA_LINK_HDA Struct Reference

HD Audio Link Policies. More...

#include <HdAudioConfig.h>

Public Attributes

UINT32 | Enable: 1
HDA interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: Enable.
UINT8 | SdiEnable [PCH_MAX_HDA_SDI]
HDA SDI signal enable. When enabled related SDI pins will be switched to appropriate native mode: 0: Disable; 1: Enable.
UINT8 | Reserved [(4 -(PCH_MAX_HDA_SDI % 4)) % 4]
Padding for SDI enable table.

Detailed Description

HD Audio Link Policies.

Definition at line 124 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

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HDA_LINK_HDA Member List

This is the complete list of members for HDA_LINK_HDA, including all inherited members.

Enable | HDA_LINK_HDA
Reserved | HDA_LINK_HDA
SdiEnable | HDA_LINK_HDA


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: HDA_LINK_SNDW Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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HDA_LINK_SNDW Struct Reference

HD Audio SNDW Interface Policies. More...

#include <HdAudioConfig.h>

Public Attributes

UINT32 Enable: 1
HDA SNDW interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: Enable.

Detailed Description

HD Audio SNDW Interface Policies.

Definition at line 152 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h


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HDA_LINK_SNDW Member List

This is the complete list of members for HDA_LINK_SNDW, including all inherited members.

Enable | HDA_LINK_SNDW


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: HDA_LINK_SSP Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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HDA_LINK_SSP Struct Reference

HD Audio SSP Interface Policies. More...

#include <HdAudioConfig.h>

Public Attributes

UINT32 Enable: 1
HDA SSP interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: Enable.

Detailed Description

HD Audio SSP Interface Policies.

Definition at line 144 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
HDA_LINK_SSP Member List

This is the complete list of members for HDA_LINK_SSP, including all inherited members.

Enable | HDA_LINK_SSP


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: HDA_VERB_TABLE_HEADER Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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HDA_VERB_TABLE_HEADER Struct Reference

Azalia verb table header Every verb table should contain this defined header and followed by azalia verb commands. More...

#include <HdAudioConfig.h>

Public Attributes

UINT16 | VendorId
Codec Vendor ID.
UINT16 | DeviceId
Codec Device ID.
UINT8 | RevisionId
Revision ID of the codec. 0xFF matches any revision.
UINT8 | SdiNum
SDI number, 0xFF matches any SDI.
UINT16 | DataDwords
Number of data DWORDs following the header.

Detailed Description

Azalia verb table header Every verb table should contain this defined header and followed by azalia verb commands.

Definition at line 91 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
HDA_VERB_TABLE_HEADER Member List

This is the complete list of members for HDA_VERB_TABLE_HEADER, including all inherited members.

DataDwords | HDA_VERB_TABLE_HEADER
DeviceId | HDA_VERB_TABLE_HEADER
RevisionId | HDA_VERB_TABLE_HEADER
SdiNum | HDA_VERB_TABLE_HEADER
VendorId | HDA_VERB_TABLE_HEADER


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: HDAUDIO_DXE_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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HDAUDIO_DXE_CONFIG Struct Reference

This structure contains the DXE policies which are related to HD Audio device (cAVS). More...

#include <HdAudioConfig.h>

Collaboration diagram for HDAUDIO_DXE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
HDAUDIO_SNDW_CONFIG | SndwConfig [PCH_MAX_HDA_SNDW_LINK_NUM]
SNDW configuration for exposed via SNDW ACPI tables:
UINT32 | DspFeatureMask
Bitmask of supported DSP features: [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6] - BT Intel A2DP [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel WoV, 1: Windows Voice Activation [BIT9] - BT Intel Low Energy;[BIT9] - 0 BT Intel Low Energy is not supported , 1: BT Intel Low Energy is supported Default is zero.
HDAUDIO_DISC_BT_OFFLOAD | HdaDiscBtOffload
Discrete BT HCI Audio Offload Support.

Detailed Description

This structure contains the DXE policies which are related to HD Audio device (cAVS).

Revision 1:

  • Inital version. Revision 2:
  • Add IoControlEnabled Revision 3:
  • Remove IoControlEnabled

Definition at line 268 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
HDAUDIO_DXE_CONFIG Member List

This is the complete list of members for HDAUDIO_DXE_CONFIG, including all inherited members.

DspFeatureMask | HDAUDIO_DXE_CONFIG
HdaDiscBtOffload | HDAUDIO_DXE_CONFIG
Header | HDAUDIO_DXE_CONFIG
SndwConfig | HDAUDIO_DXE_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: HDAUDIO_PREMEM_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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HDAUDIO_PREMEM_CONFIG Struct Reference

This structure contains the premem policies which are related to HD Audio device (cAVS). More...

#include <HdAudioConfig.h>

Collaboration diagram for HDAUDIO_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Enable: 1
Intel HD Audio (Azalia) enablement: 0: Disable, 1: Enable
UINT32 | DspEnable: 1
DSP enablement: 0: Disable; 1: Enable
UINT32 | VcType: 1
Virtual Channel Type Select: 0: VC0, 1: VC1.
UINT32 | DspUaaCompliance: 1
Universal Audio Architecture compliance for DSP enabled system: 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported)
UINT32 | IDispLinkFrequency: 4
iDisp-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz
UINT32 | IDispLinkTmode: 3
iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T, 2: 4T, 3: 8T, 4: 16T
UINT32 | IDispCodecDisconnect: 1
iDisplay Audio Codec disconnection, 0: Not disconnected, enumerable; 1: Disconnected SDI, not enumerable
UINT32 | PowerGatingSupported: 1
Power Gating supported: 0: Not supported, 1: Supported.
UINT32 | SndwMultilaneEnable: 2
Sndw0 Multiline enablement: 0: Disable, 1: Two lines enabled, 2: Three lines enabled, 3: Four Lines enabled.
UINT32 | RsvdBits: 17
Reserved bits 0.
HDA_LINK_HDA AudioLinkHda
Audio Link Mode configuration bitmask. More...
HDA_LINK_DMIC | AudioLinkDmic [PCH_MAX_HDA_DMIC_LINK_NUM]
DMIC link enablement: 0: Disable; 1: Enable. More...
HDA_LINK_SSP | AudioLinkSsp [PCH_MAX_HDA_SSP_LINK_NUM]
I2S/SSP link enablement: 0: Disable; 1: Enable. More...
HDA_LINK_SNDW | AudioLinkSndw [PCH_MAX_HDA_SNDW_LINK_NUM]
SoundWire link enablement: 0: Disable; 1: Enable. More...
UINT16 | ResetWaitTimer
(Test) The delay timer after Azalia reset, the value is number of microseconds. Default is 600.
UINT8 | Rsvd0 [2]
Reserved bytes, align to multiple 4.
UINT32 | SubSystemIds
Value for SID and SVID. If its set to 0 then default value is used.
HDAUDIO_DISC_BT_OFFLOAD | HdaDiscBtOffload
Discrete BT HCI Audio Offload Support.

Detailed Description

This structure contains the premem policies which are related to HD Audio device (cAVS).

Revision 1:

  • Inital version. Revision 2:
  • Add DmicClockSelect Revision 3:
  • Add AudioFpgaSocVer Revision 4:
  • Remove AudioFpgaSocVer Revision 5:
  • Add HdaDiscBtOffload

Definition at line 199 of file HdAudioConfig.h.

Member Data Documentation

◆ AudioLinkDmic

HDA_LINK_DMIC HDAUDIO_PREMEM_CONFIG::AudioLinkDmic[PCH_MAX_HDA_DMIC_LINK_NUM]

DMIC link enablement: 0: Disable; 1: Enable.

DMIC0 LKF: Muxed with SNDW2/SNDW4.

Definition at line 227 of file HdAudioConfig.h.

◆ AudioLinkHda

HDA_LINK_HDA HDAUDIO_PREMEM_CONFIG::AudioLinkHda

Audio Link Mode configuration bitmask.

Allows to configure enablement of the following interfaces: HDA-Link, DMIC, SSP, SoundWire. HDA-Link enablement: 0: Disable; 1: Enable.

Definition at line 222 of file HdAudioConfig.h.

◆ AudioLinkSndw

HDA_LINK_SNDW HDAUDIO_PREMEM_CONFIG::AudioLinkSndw[PCH_MAX_HDA_SNDW_LINK_NUM]

SoundWire link enablement: 0: Disable; 1: Enable.

SNDW2 LKF: Muxed with DMIC0/DMIC1. SNDW3 LKF: Muxed with DMIC1. SNDW4 LKF: Muxed with DMIC0.

Definition at line 241 of file HdAudioConfig.h.

◆ AudioLinkSsp

HDA_LINK_SSP HDAUDIO_PREMEM_CONFIG::AudioLinkSsp[PCH_MAX_HDA_SSP_LINK_NUM]

I2S/SSP link enablement: 0: Disable; 1: Enable.

SSP0/1 LKF: Muxed with HDA.

Note
Since the I2S/SSP2 pin set contains pads which are also used for CNVi purpose, enabling AudioLinkSsp2 is exclusive with CNVi is present.

Definition at line 234 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
HDAUDIO_PREMEM_CONFIG Member List

This is the complete list of members for HDAUDIO_PREMEM_CONFIG, including all inherited members.

AudioLinkDmic | HDAUDIO_PREMEM_CONFIG
AudioLinkHda | HDAUDIO_PREMEM_CONFIG
AudioLinkSndw | HDAUDIO_PREMEM_CONFIG
AudioLinkSsp | HDAUDIO_PREMEM_CONFIG
DspEnable | HDAUDIO_PREMEM_CONFIG
DspUaaCompliance | HDAUDIO_PREMEM_CONFIG
Enable | HDAUDIO_PREMEM_CONFIG
HdaDiscBtOffload | HDAUDIO_PREMEM_CONFIG
Header | HDAUDIO_PREMEM_CONFIG
IDispCodecDisconnect | HDAUDIO_PREMEM_CONFIG
IDispLinkFrequency | HDAUDIO_PREMEM_CONFIG
IDispLinkTmode | HDAUDIO_PREMEM_CONFIG
PowerGatingSupported | HDAUDIO_PREMEM_CONFIG
ResetWaitTimer | HDAUDIO_PREMEM_CONFIG
Rsvd0 | HDAUDIO_PREMEM_CONFIG
RsvdBits | HDAUDIO_PREMEM_CONFIG
SndwMultilaneEnable | HDAUDIO_PREMEM_CONFIG
SubSystemIds | HDAUDIO_PREMEM_CONFIG
VcType | HDAUDIO_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: HSIO_PARAMETERS Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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HSIO_PARAMETERS Struct Reference

This structure describes USB3 Port N configuration parameters. More...

#include <Usb3HsioConfig.h>

Public Attributes

UINT8 | HsioTxDownscaleAmp
USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin) HSIO_TX_DWORD8[21:16] Default = 00h
UINT8 | HsioTxDeEmph
USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting (ow2tapgen2deemph3p5) HSIO_TX_DWORD5[21:16] Default = 29h (approximately -3.5dB De-Emphasis)
UINT8 | HsioCtrlAdaptOffsetCfg
Signed Magnatude number added to the CTLE code. More...
UINT8 | HsioFilterSelN
LFPS filter select for n (filter_sel_n_2_0) HSIO_RX_DWORD51 [29:27] 0h:1.6ns 1h:2.4ns 2h:3.2ns 3h:4.0ns 4h:4.8ns 5h:5.6ns 6h:6.4ns Default = 0h
UINT8 | HsioFilterSelP
LFPS filter select for p (filter_sel_p_2_0) HSIO_RX_DWORD51 [26:24] 0h:1.6ns 1h:2.4ns 2h:3.2ns 3h:4.0ns 4h:4.8ns 5h:5.6ns 6h:6.4ns Default = 0h
UINT8 | HsioOlfpsCfgPullUpDwnRes
Controls the input offset (olfpscfgpullupdwnres_sus_usb_2_0) HSIO_RX_DWORD51 [2:0] 000 Prohibited 001 45K 010 Prohibited 011 31K 100 36K 101 36K 110 36K 111 36K Default = 3h
UINT8 | HsioTxDeEmphEnable
Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment, 0: Disable; 1: Enable.
UINT8 | HsioTxDownscaleAmpEnable
Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, 0: Disable; 1: Enable.
UINT8 | HsioCtrlAdaptOffsetCfgEnable
Enable the write to Signed Magnatude number added to the CTLE code, 0: Disable; 1: Enable.
UINT8 | HsioFilterSelNEnable
Enable the write to LFPS filter select for n, 0: Disable; 1: Enable.
UINT8 | HsioFilterSelPEnable
Enable the write to LFPS filter select for p, 0: Disable; 1: Enable.
UINT8 | HsioOlfpsCfgPullUpDwnResEnable
Enable the write to olfpscfgpullupdwnres, 0: Disable; 1: Enable.
UINT8 | HsioTxRate3UniqTran
USB 3.0 TX Output - Unique Transition Bit Scale for rate 3 (rate3UniqTranScale) HSIO_TX_DWORD9[6:0] Default = 4Ch
UINT8 | HsioTxRate2UniqTran
USB 3.0 TX Output -Unique Transition Bit Scale for rate 2 (rate2UniqTranScale) HSIO_TX_DWORD9[14:8] Default = 4Ch
UINT8 | HsioTxRate1UniqTran
USB 3.0 TX Output - Unique Transition Bit Scale for rate 1 (rate1UniqTranScale) HSIO_TX_DWORD9[22:16] Default = 4Ch
UINT8 | HsioTxRate0UniqTran
USB 3.0 TX Output - Unique Transition Bit Scale for rate 0 (rate0UniqTranScale) HSIO_TX_DWORD9[30:24] Default = 4Ch
UINT8 | HsioTxRate3UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 3, 0: Disable; 1: Enable.
UINT8 | HsioTxRate2UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 2, 0: Disable; 1: Enable.
UINT8 | HsioTxRate1UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 1, 0: Disable; 1: Enable.
UINT8 | HsioTxRate0UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 0, 0: Disable; 1: Enable.

Detailed Description

This structure describes USB3 Port N configuration parameters.

Definition at line 55 of file Usb3HsioConfig.h.

Member Data Documentation

◆ HsioCtrlAdaptOffsetCfg

UINT8 HSIO_PARAMETERS::HsioCtrlAdaptOffsetCfg

Signed Magnatude number added to the CTLE code.

(ctle_adapt_offset_cfg_4_0) HSIO_RX_DWORD25 [20:16] Ex: -1 – 1_0001. +1: 0_0001 Default = 0h

Definition at line 74 of file Usb3HsioConfig.h.

The documentation for this struct was generated from the following file:
  • Usb3HsioConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
HSIO_PARAMETERS Member List

This is the complete list of members for HSIO_PARAMETERS, including all inherited members.

HsioCtrlAdaptOffsetCfg | HSIO_PARAMETERS
HsioCtrlAdaptOffsetCfgEnable | HSIO_PARAMETERS
HsioFilterSelN | HSIO_PARAMETERS
HsioFilterSelNEnable | HSIO_PARAMETERS
HsioFilterSelP | HSIO_PARAMETERS
HsioFilterSelPEnable | HSIO_PARAMETERS
HsioOlfpsCfgPullUpDwnRes | HSIO_PARAMETERS
HsioOlfpsCfgPullUpDwnResEnable | HSIO_PARAMETERS
HsioTxDeEmph | HSIO_PARAMETERS
HsioTxDeEmphEnable | HSIO_PARAMETERS
HsioTxDownscaleAmp | HSIO_PARAMETERS
HsioTxDownscaleAmpEnable | HSIO_PARAMETERS
HsioTxRate0UniqTran | HSIO_PARAMETERS
HsioTxRate0UniqTranEnable | HSIO_PARAMETERS
HsioTxRate1UniqTran | HSIO_PARAMETERS
HsioTxRate1UniqTranEnable | HSIO_PARAMETERS
HsioTxRate2UniqTran | HSIO_PARAMETERS
HsioTxRate2UniqTranEnable | HSIO_PARAMETERS
HsioTxRate3UniqTran | HSIO_PARAMETERS
HsioTxRate3UniqTranEnable | HSIO_PARAMETERS


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: I2C_PIN_MUX Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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I2C_PIN_MUX Struct Reference

I2C signals pin muxing settings. More...

#include <SerialIoDevices.h>

Public Attributes

UINT32 | Sda
SDA Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA_*.
UINT32 | Scl
SCL Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL_*.

Detailed Description

I2C signals pin muxing settings.

If signal can be enable only on a single pin then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_* in GpioPins*.h for supported settings on a given platform

Definition at line 212 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h


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I2C_PIN_MUX Member List

This is the complete list of members for I2C_PIN_MUX, including all inherited members.

Scl | I2C_PIN_MUX
Sda | I2C_PIN_MUX


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: IEH_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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IEH_CONFIG Struct Reference

The IEH_CONFIG block describes the expected configuration of the PCH Integrated Error Handler. More...

#include <IehConfig.h>

Collaboration diagram for IEH_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Mode: 1
IEH mode 0: Bypass Mode; 1: Enable.
UINT32 | RsvdBits0: 31
Reserved bits.

Detailed Description

The IEH_CONFIG block describes the expected configuration of the PCH Integrated Error Handler.

Definition at line 53 of file IehConfig.h.

The documentation for this struct was generated from the following file:
  • IehConfig.h


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
IEH_CONFIG Member List

This is the complete list of members for IEH_CONFIG, including all inherited members.

Header | IEH_CONFIG
Mode | IEH_CONFIG
RsvdBits0 | IEH_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: IOM_AUX_ORI_PAD_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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IOM_AUX_ORI_PAD_CONFIG Struct Reference

The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin. More...

#include <TcssPeiConfig.h>

Public Attributes

UINT32 | GpioAuxBiasCtrlPuP
GPIO Aux Bias Ctrl Pull Up Pin number that is for IOM indicate the pull up pin from TypeC port.
UINT32 | GpioAuxBiasCtrlPdN
GPIO Aux Bais Ctrl Pull Down Pin number that is for IOM indicate the pull down pin from TypeC port.
UINT32 | GpioIsoCtrlPin
GPIO ISO control pin GPIO number that is IOM indicate the AUX active from SOC.

Detailed Description

The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin.

Those GPIO setting for DP Aux Orientation Bias Control when the TypeC port didn't have re-timer. IOM needs know Pull-Up and Pull-Down pin for Bias control

Definition at line 61 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h


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IOM_AUX_ORI_PAD_CONFIG Member List

This is the complete list of members for IOM_AUX_ORI_PAD_CONFIG, including all inherited members.

GpioAuxBiasCtrlPdN | IOM_AUX_ORI_PAD_CONFIG
GpioAuxBiasCtrlPuP | IOM_AUX_ORI_PAD_CONFIG
GpioIsoCtrlPin | IOM_AUX_ORI_PAD_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: IOM_INTERFACE_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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IOM_INTERFACE_CONFIG Struct Reference

The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC. More...

#include <TcssPeiConfig.h>

Public Attributes

UINT32 | VccSt
IOM VCCST request. (Not equal to actual VCCST value)
UINT32 | UsbOverride
IOM to override USB connection.
UINT32 | D3ColdEnable
Enable/disable D3 Cold support in TCSS.
UINT32 | D3HotEnable
Enable/disable D3 Hot support in TCSS.

Detailed Description

The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC.

Definition at line 71 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h


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IOM_INTERFACE_CONFIG Member List

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D3ColdEnable | IOM_INTERFACE_CONFIG
D3HotEnable | IOM_INTERFACE_CONFIG
UsbOverride | IOM_INTERFACE_CONFIG
VccSt | IOM_INTERFACE_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: IPU_PREMEM_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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IPU_PREMEM_CONFIG Struct Reference

IPU PreMem configuration
Revision 1: More...

#include <IpuPreMemConfig.h>

Collaboration diagram for IPU_PREMEM_CONFIG:
[legend]

Public Attributes

UINT8 | IpuEnable
Config Block Header. More...
UINT8 | ImguClkOutEn [GPIO_IMGUCLK_NUMBER_OF_PINS]
It enable the IMGU CLKOUT. More...
UINT8 | Rsvd [5]
Reserved for future use.

Detailed Description

IPU PreMem configuration
Revision 1:

  • Initial version.

Definition at line 62 of file IpuPreMemConfig.h.

Member Data Documentation

◆ ImguClkOutEn

UINT8 IPU_PREMEM_CONFIG::ImguClkOutEn[GPIO_IMGUCLK_NUMBER_OF_PINS]

It enable the IMGU CLKOUT.

TRUE FALSE

Definition at line 76 of file IpuPreMemConfig.h.

◆ IpuEnable

UINT8 IPU_PREMEM_CONFIG::IpuEnable

Config Block Header.

(Test) It enables the SA IPU Device if supported and not fused off. If FALSE, all other policies in this config block will be ignored. 1=TRUE; 0=FALSE.

Definition at line 70 of file IpuPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • IpuPreMemConfig.h


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IPU_PREMEM_CONFIG Member List

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ImguClkOutEn | IPU_PREMEM_CONFIG
IpuEnable | IPU_PREMEM_CONFIG
Rsvd | IPU_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: IPv4_ADDRESS Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
List of all members
IPv4_ADDRESS Struct Reference

4-byte buffer. More...

#include <Base.h>

Detailed Description

4-byte buffer.

An IPv4 internet protocol address.

Definition at line 223 of file Base.h.

The documentation for this struct was generated from the following file:
  • Base.h


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
IPv4_ADDRESS Member List

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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: IPv6_ADDRESS Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
List of all members
IPv6_ADDRESS Struct Reference

16-byte buffer. More...

#include <Base.h>

Detailed Description

16-byte buffer.

An IPv6 internet protocol address.

Definition at line 230 of file Base.h.

The documentation for this struct was generated from the following file:
  • Base.h


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IPv6_ADDRESS Member List

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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ISH_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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ISH_CONFIG Struct Reference

The ISH_CONFIG block describes Integrated Sensor Hub device. More...

#include <IshConfig.h>

Collaboration diagram for ISH_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | PdtUnlock: 1
ISH PDT Unlock Msg: 0: False 1: True.
UINT32 | MsiInterrupt: 1
ISH MSI Interrupts: 0: False 1: True.
UINT32 | RsvdBits0: 30
Reserved Bits.

Detailed Description

The ISH_CONFIG block describes Integrated Sensor Hub device.

Definition at line 155 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h


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ISH_CONFIG Member List

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Header | ISH_CONFIG
MsiInterrupt | ISH_CONFIG
PdtUnlock | ISH_CONFIG
RsvdBits0 | ISH_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ISH_GP Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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ISH_GP Struct Reference

Struct contains GPIO pins assigned and signal settings of GP. More...

#include <IshConfig.h>

Collaboration diagram for ISH_GP:
[legend]

Public Attributes

UINT32 | Enable: 1
ISH GP GPIO pins assigned: 0: False 1: True.
UINT32 | RsvdBits0: 31
Reserved Bits.

Detailed Description

Struct contains GPIO pins assigned and signal settings of GP.

Definition at line 146 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h


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ISH_GP Member List

This is the complete list of members for ISH_GP, including all inherited members.

Enable | ISH_GP
RsvdBits0 | ISH_GP


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ISH_GPIO_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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ISH_GPIO_CONFIG Struct Reference

ISH GPIO settings. More...

#include <IshConfig.h>

Public Attributes

UINT32 | PinMux
GPIO signals pin muxing settings. More...
UINT32 | PadTermination
GPIO Pads Internal Termination. More...

Detailed Description

ISH GPIO settings.

Definition at line 68 of file IshConfig.h.

Member Data Documentation

◆ PadTermination

UINT32 ISH_GPIO_CONFIG::PadTermination

GPIO Pads Internal Termination.

For more information please see Platform Design Guide. Check GPIO_ELECTRICAL_CONFIG for reference

Definition at line 80 of file IshConfig.h.

◆ PinMux

UINT32 ISH_GPIO_CONFIG::PinMux

GPIO signals pin muxing settings.

If signal can be enable only on a single pin then this parameter should be set to 0. Refer to GPIO_*_MUXING_ISH_*x_* in GpioPins*.h for supported settings on a given platform GPIO Pin mux configuration. Refer to GPIO_*_MUXING_ISH_*x_MOSI_*

Definition at line 74 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h


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ISH_GPIO_CONFIG Member List

This is the complete list of members for ISH_GPIO_CONFIG, including all inherited members.

PadTermination | ISH_GPIO_CONFIG
PinMux | ISH_GPIO_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ISH_I2C Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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ISH_I2C Struct Reference

Struct contains GPIO pins assigned and signal settings of I2C. More...

#include <IshConfig.h>

Collaboration diagram for ISH_I2C:
[legend]

Public Attributes

UINT32 | Enable: 1
ISH I2C GPIO pins assigned: 0: False 1: True.
UINT32 | RsvdBits0: 31
Reserved Bits.

Detailed Description

Struct contains GPIO pins assigned and signal settings of I2C.

Definition at line 137 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h


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ISH_I2C Member List

This is the complete list of members for ISH_I2C, including all inherited members.

Enable | ISH_I2C
RsvdBits0 | ISH_I2C


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ISH_I2C_PIN_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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ISH_I2C_PIN_CONFIG Struct Reference

I2C signals settings. More...

#include <IshConfig.h>

Collaboration diagram for ISH_I2C_PIN_CONFIG:
[legend]

Public Attributes

ISH_GPIO_CONFIG Sda
SDA Pin configuration.
ISH_GPIO_CONFIG Scl
SCL Pin configuration.

Detailed Description

I2C signals settings.

Definition at line 108 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h


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ISH_I2C_PIN_CONFIG Member List

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Scl | ISH_I2C_PIN_CONFIG
Sda | ISH_I2C_PIN_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ISH_I3C_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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ISH_I3C_CONFIG Struct Reference

The ISH_I3C_CONFIG block describes I3C in ISH device. More...

#include <IshConfig.h>

Collaboration diagram for ISH_I3C_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
ISH_I3C Controller
ISH I3C Controller.

Detailed Description

The ISH_I3C_CONFIG block describes I3C in ISH device.

Definition at line 171 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h


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ISH_I3C_CONFIG Member List

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Controller | ISH_I3C_CONFIG
Header | ISH_I3C_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ISH_PREMEM_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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ISH_PREMEM_CONFIG Struct Reference

Premem Policy for Integrated Sensor Hub device. More...

#include <IshConfig.h>

Collaboration diagram for ISH_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Enable: 1
ISH Controler 0: Disable; 1: Enable. More...
UINT32 | RsvdBits0: 31
Reserved Bits.

Detailed Description

Premem Policy for Integrated Sensor Hub device.

Definition at line 180 of file IshConfig.h.

Member Data Documentation

◆ Enable

UINT32 ISH_PREMEM_CONFIG::Enable

ISH Controler 0: Disable; 1: Enable.

For Desktop sku, the ISH POR should be disabled. 0:Disable .

Definition at line 186 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h


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ISH_PREMEM_CONFIG Member List

This is the complete list of members for ISH_PREMEM_CONFIG, including all inherited members.

Enable | ISH_PREMEM_CONFIG
Header | ISH_PREMEM_CONFIG
RsvdBits0 | ISH_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ISH_SPI Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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ISH_SPI Struct Reference

Struct contains GPIO pins assigned and signal settings of SPI. More...

#include <IshConfig.h>

Collaboration diagram for ISH_SPI:
[legend]

Public Attributes

UINT8 | Enable
ISH SPI GPIO pins assigned: 0: False 1: True.
UINT8 | CsEnable [PCH_MAX_ISH_SPI_CS_PINS]
ISH SPI CS pins assigned: 0: False 1: True.
UINT16 | RsvdField0
Reserved field.

Detailed Description

Struct contains GPIO pins assigned and signal settings of SPI.

Definition at line 117 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h


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CsEnable | ISH_SPI
Enable | ISH_SPI
RsvdField0 | ISH_SPI


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ISH_SPI_PIN_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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ISH_SPI_PIN_CONFIG Struct Reference

SPI signals settings. More...

#include <IshConfig.h>

Collaboration diagram for ISH_SPI_PIN_CONFIG:
[legend]

Public Attributes

ISH_GPIO_CONFIG Mosi
MOSI Pin configuration.
ISH_GPIO_CONFIG Miso
MISO Pin configuration.
ISH_GPIO_CONFIG Clk
CLK Pin configuration.
ISH_GPIO_CONFIG Cs [PCH_MAX_ISH_SPI_CS_PINS]
CS Pin configuration.

Detailed Description

SPI signals settings.

Definition at line 86 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h


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ISH_SPI_PIN_CONFIG Member List

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Clk | ISH_SPI_PIN_CONFIG
Cs | ISH_SPI_PIN_CONFIG
Miso | ISH_SPI_PIN_CONFIG
Mosi | ISH_SPI_PIN_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ISH_UART Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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ISH_UART Struct Reference

Struct contains GPIO pins assigned and signal settings of UART. More...

#include <IshConfig.h>

Collaboration diagram for ISH_UART:
[legend]

Public Attributes

UINT32 | Enable: 1
ISH UART GPIO pins assigned: 0: False 1: True.
UINT32 | RsvdBits0: 31
Reserved Bits.

Detailed Description

Struct contains GPIO pins assigned and signal settings of UART.

Definition at line 128 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h


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ISH_UART Member List

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Enable | ISH_UART
RsvdBits0 | ISH_UART


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ISH_UART_PIN_CONFIG Struct Reference

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ISH_UART_PIN_CONFIG Struct Reference

UART signals settings. More...

#include <IshConfig.h>

Collaboration diagram for ISH_UART_PIN_CONFIG:
[legend]

Public Attributes

ISH_GPIO_CONFIG Rx
RXD Pin configuration.
ISH_GPIO_CONFIG Tx
TXD Pin configuration.
ISH_GPIO_CONFIG Rts
RTS Pin configuration.
ISH_GPIO_CONFIG Cts
CTS Pin configuration.

Detailed Description

UART signals settings.

Definition at line 97 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h


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Cts | ISH_UART_PIN_CONFIG
Rts | ISH_UART_PIN_CONFIG
Rx | ISH_UART_PIN_CONFIG
Tx | ISH_UART_PIN_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ME_PEI_CONFIG Struct Reference

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ME_PEI_CONFIG Struct Reference

ME Pei Post-Memory Configuration Structure. More...

#include <MePeiConfig.h>

Collaboration diagram for ME_PEI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | EndOfPostMessage: 2
0: Disabled; 1: Send in PEI; 2: Send in DXE - Send EOP at specific phase.
UINT32 | DisableD0I3SettingForHeci: 1
(Test) 0: Disable; 1: Enable - Enable/Disable D0i3 for HECI.
UINT32 | MeUnconfigOnRtcClear: 2
Enable/Disable Me Unconfig On Rtc Clear. More...
UINT32 | MctpBroadcastCycle: 1
(Test) 0: Disable; 1: Enable - Program registers for MCTP Cycle.
UINT32 | EnforceEDebugMode: 1
0: Disable; 1: Enable - Enforces ME to enter Enhanced Debug Mode
UINT32 | CseDataResilience: 1
0: Disable; 1: Enable - CSE data resilience support
UINT32 | RsvdBits: 24
Reserved for future use & Config block alignment.

Detailed Description

ME Pei Post-Memory Configuration Structure.

Revision 1:

  • Initial version.

Definition at line 104 of file MePeiConfig.h.

Member Data Documentation

◆ MeUnconfigOnRtcClear

UINT32 ME_PEI_CONFIG::MeUnconfigOnRtcClear

Enable/Disable Me Unconfig On Rtc Clear.

If enabled, BIOS will send MeUnconfigOnRtcClearDisable Msg with parameter 0. It will cause ME to unconfig if RTC is cleared.

  • 0: Disable
  • 1: Enable
  • 2: Cmos is clear, status unkonwn
  • 3: Reserved

Definition at line 117 of file MePeiConfig.h.

The documentation for this struct was generated from the following file:
  • MePeiConfig.h


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ME_PEI_CONFIG Member List

This is the complete list of members for ME_PEI_CONFIG, including all inherited members.

CseDataResilience | ME_PEI_CONFIG
DisableD0I3SettingForHeci | ME_PEI_CONFIG
EndOfPostMessage | ME_PEI_CONFIG
EnforceEDebugMode | ME_PEI_CONFIG
Header | ME_PEI_CONFIG
MctpBroadcastCycle | ME_PEI_CONFIG
MeUnconfigOnRtcClear | ME_PEI_CONFIG
RsvdBits | ME_PEI_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ME_PEI_PREMEM_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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ME_PEI_PREMEM_CONFIG Struct Reference

ME Pei Pre-Memory Configuration Structure. More...

#include <MePeiConfig.h>

Collaboration diagram for ME_PEI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | HeciTimeouts: 1
0: Disable; 1: Enable - HECI Send/Receive Timeouts.
UINT32 | DidInitStat: 2
(Test) 0: Disabled 1: ME DID init stat 0 - Success 2: ME DID init stat 1 - No Memory in Channels 3: ME DID init stat 2 - Memory Init Error
UINT32 | DisableCpuReplacedPolling: 1
(Test) 0: Set to 0 to enable polling for CPU replacement 1: Set to 1 will disable polling for CPU replacement
UINT32 | DisableMessageCheck: 1
(Test) 0: ME BIOS will check each messages before sending 1: ME BIOS always sends messages without checking
UINT32 | SkipMbpHob: 1
(Test) The SkipMbpHob policy determines whether ME BIOS Payload data will be requested during boot. More...
UINT32 | HeciCommunication2: 1
(Test) 0: Disable; 1: Enable - Enable/Disable HECI2.
UINT32 | KtDeviceEnable: 2
(Test) 0: POR; 1: Enable; 2: Disable - Enable/Disable KT Device.
UINT32 | SkipCpuReplacementCheck: 1
(Test) 0: Disable; 1: Enable - Enable/Disable to skip CPU replacement check.
UINT32 | HeciFullTrace: 1
(Test) 0: Disable; 1: Enable - Enable/Disable Full HECI communication information logged to serial
UINT32 | RsvdBits: 21
Reserved for future use & Config block alignment.

Detailed Description

ME Pei Pre-Memory Configuration Structure.

Revision 1:

  • Initial version.

Definition at line 52 of file MePeiConfig.h.

Member Data Documentation

◆ SkipMbpHob

UINT32 ME_PEI_PREMEM_CONFIG::SkipMbpHob

(Test) The SkipMbpHob policy determines whether ME BIOS Payload data will be requested during boot.

If set to 1, BIOS will not send Get MBP message and not create MBP Hob. 0: ME BIOS will send Get MBP message and create HOB for MBP data 1: ME BIOS will not send Get MBP message

Definition at line 82 of file MePeiConfig.h.

The documentation for this struct was generated from the following file:
  • MePeiConfig.h


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ME_PEI_PREMEM_CONFIG Member List

This is the complete list of members for ME_PEI_PREMEM_CONFIG, including all inherited members.

DidInitStat | ME_PEI_PREMEM_CONFIG
DisableCpuReplacedPolling | ME_PEI_PREMEM_CONFIG
DisableMessageCheck | ME_PEI_PREMEM_CONFIG
Header | ME_PEI_PREMEM_CONFIG
HeciCommunication2 | ME_PEI_PREMEM_CONFIG
HeciFullTrace | ME_PEI_PREMEM_CONFIG
HeciTimeouts | ME_PEI_PREMEM_CONFIG
KtDeviceEnable | ME_PEI_PREMEM_CONFIG
RsvdBits | ME_PEI_PREMEM_CONFIG
SkipCpuReplacementCheck | ME_PEI_PREMEM_CONFIG
SkipMbpHob | ME_PEI_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: MUX_GPIO_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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MUX_GPIO_CONFIG Struct Reference

I3C GPIO settings. More...

#include <SerialIoDevices.h>

Public Attributes

UINT32 PadTermination
GPIO signals pin muxing settings.

Detailed Description

I3C GPIO settings.

Definition at line 261 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h


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MUX_GPIO_CONFIG Member List

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PadTermination | MUX_GPIO_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: OVERCLOCKING_PREMEM_CONFIG Struct Reference

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OVERCLOCKING_PREMEM_CONFIG Struct Reference

Overclocking Configuration Structure. More...

#include <OverclockingConfig.h>

Collaboration diagram for OVERCLOCKING_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | OcSupport: 1
Overclocking support. More...
UINT32 | CoreVoltageMode: 1
Core voltage mode, specifies which voltage mode the processor will be operating. More...
UINT32 | CoreVfPointOffsetMode: 1
Selects Core Voltage & Frequency Offset between Legacy and Selection modes. More...
UINT32 | CoreVfConfigScope: 1
Core VF Configuration Scope. More...
UINT32 | PerCoreRatioOverride: 1
Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new favored core ratio to each Core. 0: Disable, 1: enable.
UINT32 | CoreRatioExtensionMode:1
Enable or disable Core Ratio above 85 Extension Mode by writing BIOS MB 0x37 to enable FULL_RANGE_MULTIPLIER_UNLOCK_EN. 0: Disable, 1: enable.
UINT32 | RingDownBin: 1
Ring Downbin enable/disable. More...
UINT32 | RingVoltageMode: 1
Ring voltage mode, specifies which voltage mode the processor will be operating. More...
UINT32 | GtVoltageMode: 1
Specifies whether GT voltage is operating in Adaptive or Override mode: 0=Adaptive, 1=Override.
UINT32 | SaVoltageMode: 1
SA/Uncore voltage mode, specifies which voltage mode the processor will be operating. More...
UINT32 | TvbRatioClipping: 1
This service controls Core frequency reduction caused by high package temperatures for processors that implement the Intel Thermal Velocity Boost (TVB) feature. More...
UINT32 | TvbVoltageOptimization: 1
This service controls thermal based voltage optimizations for processors that implement the Intel Thermal Velocity Boost (TVB) feature. More...
UINT32 | IaIccUnlimitedMode: 1
Support IA Unlimited ICCMAX up to maximum value 512A., 0: Disable. 1: Enable.
UINT32 | GtIccUnlimitedMode: 1
Support GT Unlimited ICCMAX up to maximum value 512A., 0: Disable. 1: Enable.
UINT32 | VccsaBootVoltageSel: 1
This service controls VCCSA Boot Voltage by programming the EPOC2 bits (strap). More...
UINT32 | CpuBandgapRefMode: 1
This service controls CPU Bandgap bypass or not by programming the CPU EPOC2 bits (strap). More...
UINT32 | VcciaBootVoltageSel: 1
This service controls VCCIA boot voltage by programming SOC-North soft straps. More...
UINT32 | BclkAdaptiveVoltage: 1
Bclk Adaptive Voltage enable/disable. 0: Disabled, 1: Enabled. When enabled, the CPU V/F curves are aware of BCLK frequency when calculated.
UINT32 | RealtimeMemoryTiming: 1
Enable/Disable the message sent to the CPU to allow realtime memory timing changes after MRC_DONE. 0=Disable, 1=Enable.
UINT32 | Avx2RatioOffset: 5
AVX2 Ratio Offset. 0: No offset. Range is 0-31. Used to lower the AVX ratio to maximize possible ratio for SSE workload.
UINT32 | Avx3RatioOffset: 5
Deprecated from Revision 10.
UINT32 | GranularRatioOverride: 1
Enable or disable OC Granular Ratio Override. 0: Disable, 1: enable.
UINT32 | MemSSVoltageMode: 1
Memory Subsystem voltage mode, specifies which voltage mode the processor will be operating. More...
UINT8 | Avx2VoltageScaleFactor
Avx2 Voltage Guardband Scale Factor This controls the AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. More...
UINT8 | Avx512VoltageScaleFactor
Avx512 Voltage Guardband Scale Factor This controls the AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. More...
UINT8 | CoreMaxOcRatio
Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit (P0). More...
UINT8 | GtMaxOcRatio
Maximum GT turbo ratio override: 0=Minimal, 60=Maximum, 0=AUTO
UINT8 | RingMaxOcRatio
Maximum ring ratio override allows to increase CPU ring frequency beyond the fused max ring ratio limit. More...
UINT8 | TjMaxOffset
TjMax Offset. More...
UINT16 | CoreVoltageOverride
The core voltage override which is applied to the entire range of cpu core frequencies. More...
UINT16 | CoreAdaptiveVoltage
Adaptive voltage target used to define the interpolation voltage point when the cpu is operating in adaptive mode range. More...
INT16 | CoreVoltageOffset
The core voltage offset applied on top of all other voltage modes. More...
UINT16 | RingVoltageOverride
The ring voltage override which is applied to the entire range of cpu ring frequencies. More...
UINT16 | RingAdaptiveVoltage
Adaptive voltage target used to define the interpolation voltage point when the ring is operating in adaptive mode range. More...
INT16 | RingVoltageOffset
The ring voltage offset applied on top of all other voltage modes. More...
UINT16 | SaVoltageOverride
The SA/Uncore voltage override which is applied to the entire range of uncore frequencies. More...
UINT16 | SaAdaptiveVoltage
Adaptive voltage target used to define the interpolation voltage point when the SA/Uncore is operating in adaptive mode range. More...
UINT16 | IaIccMax
Voltage Regulator Current Limit (Icc Max) for IA, GT and SA. More...
INT16 | GtVoltageOffset
The voltage offset applied to GT slice. Valid range from -1000mv to 1000mv: 0=Minimal, 1000=Maximum.
UINT16 | GtVoltageOverride
The GT voltage override which is applied to the entire range of GT frequencies 0=Default
UINT16 | GtAdaptiveVoltage
The adaptive voltage applied during turbo frequencies. Valid range from 0 to 2000mV: 0=Minimal, 2000=Maximum.
UINT8 | GtVfPointOffsetMode
Selects GT Voltage & Frequency Point Offset between Legacy and Selection modes. More...
UINT8 | GtVfPointCount
Number of supported GR Voltage & Frequency Point.
INT16 | GtVfPointOffset [CPU_OC_MAX_VF_POINTS]
Array used to specifies the GT Voltage Offset applied to the each selected VF Point. More...
UINT8 | GtVfPointRatio [CPU_OC_MAX_VF_POINTS]
Array for the each selected VF Point to display the GT Ration.
INT16 | SaVoltageOffset
The voltage offset applied to the SA. Valid range from -1000mv to 1000mv: 0=Default
UINT32 | CorePllVoltageOffset: 4
Core PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
UINT32 | RingPllVoltageOffset: 4
Ring PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
UINT32 | SaPllVoltageOffset: 4
SOC System Agent PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
UINT32 | IaAtomPllVoltageOffset: 4
IA Atom PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
UINT32 | McPllVoltageOffset: 4
Memory Controller PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
UINT32 | CpuSaPllVoltageOffset: 4
Cpu SA PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
UINT32 | CpuDlvrMode: 1
Select Core(s) and RING DLVR Mode, 0: Regulation Mode. 1: Power Gate Mode.
UINT32 | SaPllFreqOverride: 1
Sa PLL Frequecy Override. 0: 2400MHz. 1: 1600MHz.
UINT32 | TscDisableHwFixup: 1
Core HW Fixup disable during TSC copy from PMA to APIC, 0: Enable. 1: Disable.
UINT32 | SaIccUnlimitedMode: 1
Support SA Unlimited ICCMAX up to maximum value 512A., 0: Disable. 1: Enable.
UINT32 | RsvdBits1: 4
Reserved bits.
UINT64 | DisablePerCoreMask
Core disable mask is a bitwise indication of which core should be disabled, while ActiveCoreCount is to set the number of active cores. More...
UINT16 | PerCoreHtDisable
Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, 0 - is ignored. More...
UINT8 | CoreVfPointCount
Number of supported Core Voltage & Frequency Point.
UINT8 | CoreVfPointRatio [CPU_OC_MAX_VF_POINTS]
Array for the each selected VF Point to display the Core Ration. It's only for read command and not for write.
INT16 | CoreVfPointOffset [CPU_OC_MAX_VF_POINTS]
Array used to specifies the Core Voltage Offset applied to the each selected VF Point. More...
UINT8 | RingVfPointOffsetMode
Selects Ring Voltage & Frequency Point Offset between Legacy and Selection modes. More...
UINT8 | RingVfPointCount
Number of supported Ring Voltage & Frequency Point.
INT16 | RingVfPointOffset [CPU_OC_MAX_VF_POINTS]
Array used to specifies the Ring Voltage Offset applied to the each selected VF Point. More...
UINT8 | RingVfPointRatio [CPU_OC_MAX_VF_POINTS]
Array for the each selected VF Point to display the Ring Ration. It's only for read command and not for write.
UINT8 | MemSSVfPointCount
Number of supported Memory Subsystem Voltage & Frequency Point.
INT16 | MemSSVfPointOffset [CPU_OC_MAX_VF_POINTS]
Array used to specifies the Memory Subsystem Voltage Offset applied to the each selected VF Point. More...
UINT8 | MemSSVfPointRatio [CPU_OC_MAX_VF_POINTS]
Array for the each selected VF Point to display the Memory Subsystem Ration. It's only for read command and not for write.
UINT8 | FllOverclockMode
FLL_OVERCLOCK_MODE: 0x0 = no overclocking, 0x1 = ratio overclocking with nominal (0.5-1x) reference clock frequency, 0x2 = BCLK overclocking with elevated (1-3x) reference clock frequency, 0x3 = BCLK overclocking with extreme elevated (3-5x) reference clock frequency and ratio limited to 63.
UINT8 | CpuD2dRatio
Set CPU D2D Ratio from Range 15 to 40. More...
UINT8 | UnderVoltProtection
When UnderVolt Protection is enabled, user will be not be able to program under voltage in OS runtime. More...
INT16 | PerCoreVoltageOffset [CPU_MAX_BIG_CORES]
Array used to specifies the selected Core Offset Voltage. More...
UINT8 | PerCoreVoltageMode [CPU_MAX_BIG_CORES]
Array used to specifies the selected Core Voltage Mode.
UINT16 | PerCoreVoltageOverride [CPU_MAX_BIG_CORES]
Array used to specifies the selected Core Voltage Override.
UINT16 | PerCoreAdaptiveVoltage [CPU_MAX_BIG_CORES]
Array used to specifies the selected Core Adaptive Voltage.
UINT8 | PerAtomClusterVoltageMode [CPU_MAX_ATOM_CLUSTERS]
Array used to specifies the selected Atom Core Voltage Mode.
UINT16 | PerAtomClusterVoltageOverride [CPU_MAX_ATOM_CLUSTERS]
Array used to specifies the selected Atom Core Voltage Override.
UINT16 | PerAtomClusterAdaptiveVoltage [CPU_MAX_ATOM_CLUSTERS]
Array used to specifies the selected Atom Core Adaptive Voltage.
UINT8 | AtomClusterRatio [CPU_MAX_ATOM_CLUSTERS]
The Atom cluster max ratio overrides. More...
UINT32 | CpuBclkOcFrequency
CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz 0 - Auto. Range is 8000-50000 (10KHz)
UINT32 | SocBclkOcFrequency
SOC BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz 0 - Auto. Range is 4000-100000 (10KHz)
UINT8 | PvdRatioThreshold [2]
The Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio (P0 to Pn) to select the multiplier so that the output is within the DCO frequency range. More...
UINT8 | PvdMode [2]
PVD Mode selects Static PVD ratio for SOC/CPU (when PVD THRESHOLD value is 0). More...
UINT8 | PerCoreGranularityBins [CPU_MAX_BIG_CORES]
Percore & PerAtomCluster Granularity Bins Override. More...
UINT16 | MemSSAdaptiveVoltage
Adaptive voltage target used to define the interpolation voltage point when the cpu is operating in adaptive mode range. More...
UINT16 | MemSSVoltageOverride
The Memory Subsystem voltage override which is applied to the entire range of uncore frequencies. More...
UINT8 | MemSSVfPointOffsetMode
Selects Memory Subsystem Voltage & Frequency Point Offset between Legacy and Selection modes. More...
UINT8 | MemSSMaxOcRatio
Maximum Memory Subsystem ratio override allows to increase memory frequency beyond the fused max ring ratio limit. More...
INT16 | MemSSVoltageOffset
The Memory Subsystem voltage offset applied on top of all other voltage modes. More...
UINT8 | OcTvb
OC TVB Enable/Disable. More...
UINT8 | PcoreTvbTempThreshold0
Temperature Threshold 0 for all Pcores (in degrees C). More...
UINT8 | PcoreTvbTempThreshold1
Temperature Threshold 1 for all Pcores (in degrees C). More...
UINT8 | EcoreTvbTempThreshold0
Temperature Threshold 0 for all Ecores (in degrees C). More...
UINT8 | EcoreTvbTempThreshold1
Temperature Threshold 1 for all Ecores (in degrees C). More...
UINT8 | TvbConfigLimitSelect
Limits Select, 0 - Per CCP (Module), Command Param2 = CCP ID, CCP ID can range from 0-15. More...
UINT8 | PerPcoreRatioDownBinAboveT0 [CPU_MAX_BIG_CORES]
Down Bins (delta) for Temperature Threshold 0. More...
UINT8 | PerPcoreRatioDownBinAboveT1 [CPU_MAX_BIG_CORES]
Down Bins (delta) for Temperature Threshold 1. More...
UINT8 | PerEcoreCcpRatioDownBinAboveT0 [CPU_MAX_ATOM_CLUSTERS]
Down Bins (delta) for Temperature Threshold 0. More...
UINT8 | PerEcoreCcpRatioDownBinAboveT1 [CPU_MAX_ATOM_CLUSTERS]
Down Bins (delta) for Temperature Threshold 1. More...
UINT8 | PerPcoreGrRatioDownBinAboveT0 [CPU_MAX_BIG_CORE_TRL_GROUPS]
Down Bins (delta) for Temperature Threshold 0. More...
UINT8 | PerPcoreGrRatioDownBinAboveT1 [CPU_MAX_BIG_CORE_TRL_GROUPS]
Down Bins (delta) for Temperature Threshold 1. More...
UINT8 | RingTurboThermalProtection
Ring Turbo Thermal Protection (TTP) control which allows user to disable Turbo Thermal Protection for Ring. More...
UINT8 | NclkTurboThermalProtection
NCLK Turbo Thermal Protection (TTP) control which allows user to disable Turbo Thermal Protection for SA. More...
UINT8 | ComputeDieSscEnable
Enable or Disable Compute Die SSC configuration. More...
UINT8 | SocDieSscEnable
Enable or Disable Soc Die SSC configuration. More...
UINT8 | PerCoreMaxRatio [CPU_MAX_BIG_CORES]
Array used to specifies the selected Core Max Ratio.
UINT8 | PerAtomClusterMaxRatio [CPU_MAX_ATOM_CLUSTERS]
Array used to specifies the selected Atom Cluster Max Ratio.
UINT8 | NguMaxOcRatio
Maximum NGU ratio override allows to increase CPU NGU frequency beyond the fused max NGU ratio limit. More...
UINT8 | NguRatio
Sets the Ratio for NGU using SAVG B2P Mailbox cmd 0x22 and subcommand 0x1. More...
UINT16 | NguVoltageOverride
The NGU voltage override which is applied to the entire range of cpu NGU frequencies. More...
UINT16 | NguAdaptiveVoltage
The adaptive voltage applied during turbo frequencies. Valid range from 0 to 2000mV: 0=Minimal, 2000=Maximum.
INT16 | NguVoltageOffset
The NGU voltage offset applied on top of all other voltage modes. More...
UINT8 | NguVfPointOffsetMode
Selects NGU Voltage & Frequency Point Offset between Legacy and Selection modes. More...
UINT8 | NguVfPointCount
Number of supported NGU Voltage & Frequency Point.
INT16 | NguVfPointOffset [CPU_OC_MAX_VF_POINTS]
Array used to specifies the NGU Voltage Offset applied to the each selected VF Point. More...
UINT8 | NguVfPointRatio [CPU_OC_MAX_VF_POINTS]
Array for the each selected VF Point to display the NGU Ration. It's only for read command and not for write.
UINT8 | ProcessVmaxLimit
Disabling Process Vmax Limit will allow user to set any voltage. More...
UINT8 | PcorePowerDensityThrottle
Pcore Power Density Throttle control allows user to disable P-core throttling for power density protection. More...
UINT16 | MaxVoltageLimit [MAX_OC_DOMAINS]
Array for the each Domain to set OC Max Voltage limits Default: 0 Range: 0 to 2000.
UINT8 | CorePllCurrentRefTuningOffset
Core PLL Current Reference Tuning Offset. 0: No offset. Range 0-15.
UINT8 | RingPllCurrentRefTuningOffset
Deprecated from Revision 11.
UINT8 | IaAtomPllCurrentRefTuningOffset
IaAtom PLL Current Reference Tuning Offset. 0: No offset. Range 0-15.
UINT8 | CoreMinRatio
Request Core Min Ratio. More...
UINT8 | PerCoreDisableConfiguration
This configuration allows OC user to either use legacy num of cores option or the OC specific per core disable configuration. More...
UINT8 | NpuMaxOcRatio
Deprecated from Revision 13.
UINT8 | NpuVoltageMode
Deprecated from Revision 13.
UINT16 | NpuVoltageOverride
Deprecated from Revision 13.
UINT16 | NpuAdaptiveVoltage
Deprecated from Revision 13.
INT16 | NpuVoltageOffset
Deprecated from Revision 13.
UINT8 | ForcePcoreResidency
Enable or disable Force Pcore Residency. 0: Disable, 1: enable.
UINT8 | VrLimitBypass
Enable or disable VR Limit Bypass. 0: Disable, 1: enable.
UINT8 | TurboThermalProtection
Turbo Thermal Protection (TTP) control allows user to disable Turbo Thermal Protection. More...

Detailed Description

Overclocking Configuration Structure.

Revision 1: - Initial version. Revision 2: - Added ProcessVmaxLimit Revision 3: - Added PcorePowerDensityThrottle Revision 4: - Added MaxVoltageLimit Revision 5: - Added CorePllCurrentRefTuningOffset,RingPllCurrentRefTuningOffset,IaAtomPllCurrentRefTuningOffset Revision 6: - Added CoreMinRatio Revision 7: - Added PerCoreDisableConfiguration Revision 8: - Added NguRatio Revision 9: - Added NpuMaxOcRatio,NpuVoltageMode,NpuVoltageOverride,NpuAdaptiveVoltage,NpuVoltageOffset Revision 10: - Deprecated Avx3RatioOffset and Avx512VoltageScaleFactor Revision 11: - Deprecated RingPllCurrentRefTuningOffset Revision 12: - Added ForcePcoreResidency and VrLimitBypass Revision 13: - Deprecated NpuMaxOcRatio,NpuVoltageMode,NpuVoltageOverride,NpuAdaptiveVoltage,NpuVoltageOffset Revision 14: - Added TurboThermalProtection Revision 15: - Added RingTurboThermalProtectionand,NclkTurboThermalProtection

Definition at line 73 of file OverclockingConfig.h.

Member Data Documentation

◆ AtomClusterRatio

UINT8 OVERCLOCKING_PREMEM_CONFIG::AtomClusterRatio[CPU_MAX_ATOM_CLUSTERS]

The Atom cluster max ratio overrides.

Default: 0 Range: 0 to 120.

Definition at line 370 of file OverclockingConfig.h.

◆ Avx2VoltageScaleFactor

UINT8 OVERCLOCKING_PREMEM_CONFIG::Avx2VoltageScaleFactor

Avx2 Voltage Guardband Scale Factor This controls the AVX2 Voltage Guardband Scale factor applied to AVX2 workloads.

Valid range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor. A value of 0 means no scale factor applied (no change to voltage on AVX commands) A value of 100 applies the default voltage guardband values (1.0 factor). A value > 100 will increase the voltage guardband on AVX2 workloads. A value < 100 will decrease the voltage guardband on AVX2 workloads. 0. No scale factor applied

Definition at line 183 of file OverclockingConfig.h.

◆ Avx512VoltageScaleFactor

UINT8 OVERCLOCKING_PREMEM_CONFIG::Avx512VoltageScaleFactor

Avx512 Voltage Guardband Scale Factor This controls the AVX512 Voltage Guardband Scale factor applied to AVX512 workloads.

Valid range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor. A value of 0 means no scale factor applied (no change to voltage on AVX commands) A value of 100 applies the default voltage guardband values (1.0 factor). A value > 100 will increase the voltage guardband on AVX512 workloads. A value < 100 will decrease the voltage guardband on AVX512 workloads. 0. No scale factor applied

Definition at line 194 of file OverclockingConfig.h.

◆ ComputeDieSscEnable

UINT8 OVERCLOCKING_PREMEM_CONFIG::ComputeDieSscEnable

Enable or Disable Compute Die SSC configuration.

  • 0: Disable
  • 1: Enable

Definition at line 519 of file OverclockingConfig.h.

◆ CoreAdaptiveVoltage

UINT16 OVERCLOCKING_PREMEM_CONFIG::CoreAdaptiveVoltage

Adaptive voltage target used to define the interpolation voltage point when the cpu is operating in adaptive mode range.

Used when CoreVoltageMode = Adaptive. 0. no override. Range 0-2000mV.

Definition at line 223 of file OverclockingConfig.h.

◆ CoreMaxOcRatio

UINT8 OVERCLOCKING_PREMEM_CONFIG::CoreMaxOcRatio

Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit (P0).

0. no override/HW defaults.. Range non-turbo max - 120 (Previously max turbo is 83).

Definition at line 200 of file OverclockingConfig.h.

◆ CoreMinRatio

UINT8 OVERCLOCKING_PREMEM_CONFIG::CoreMinRatio

Request Core Min Ratio.

Limit Core minimum ratio for extreme overclocking. Default 0 indicates no request.

Definition at line 592 of file OverclockingConfig.h.

◆ CoreVfConfigScope

UINT32 OVERCLOCKING_PREMEM_CONFIG::CoreVfConfigScope

Core VF Configuration Scope.

Alows both all-core VF curve or per-core VF curve configuration. 0: All-core Scope, setting the VF curve for all cores. 1: Per-core Scope, setting the VF curve per-core.

Definition at line 102 of file OverclockingConfig.h.

◆ CoreVfPointOffset

INT16 OVERCLOCKING_PREMEM_CONFIG::CoreVfPointOffset[CPU_OC_MAX_VF_POINTS]

Array used to specifies the Core Voltage Offset applied to the each selected VF Point.

This voltage is specified in millivolts. Default: 0 Range: 0 to 1000

Definition at line 316 of file OverclockingConfig.h.

◆ CoreVfPointOffsetMode

UINT32 OVERCLOCKING_PREMEM_CONFIG::CoreVfPointOffsetMode

Selects Core Voltage & Frequency Offset between Legacy and Selection modes.

Need Reset System after enabling OverClocking Feature to initialize the default value. 0: In Legacy Mode, setting a global offset for the entire VF curve. 1: In Selection Mode, setting a selected VF point.

Definition at line 95 of file OverclockingConfig.h.

◆ CoreVoltageMode

UINT32 OVERCLOCKING_PREMEM_CONFIG::CoreVoltageMode

Core voltage mode, specifies which voltage mode the processor will be operating.

0: Adaptive Mode allows the processor to interpolate a voltage curve when beyond fused P0 range; 1: Override, sets one voltage for the entire frequency range, Pn-P0.

Definition at line 88 of file OverclockingConfig.h.

◆ CoreVoltageOffset

INT16 OVERCLOCKING_PREMEM_CONFIG::CoreVoltageOffset

The core voltage offset applied on top of all other voltage modes.

This offset is applied over the entire frequency range. This is a 2's complement number in mV units. Default: 0 Range: -1000 to 1000.

Definition at line 228 of file OverclockingConfig.h.

◆ CoreVoltageOverride

UINT16 OVERCLOCKING_PREMEM_CONFIG::CoreVoltageOverride

The core voltage override which is applied to the entire range of cpu core frequencies.

Used when CoreVoltageMode = Override. 0. no override. Range 0-2000 mV.

Definition at line 217 of file OverclockingConfig.h.

◆ CpuBandgapRefMode

UINT32 OVERCLOCKING_PREMEM_CONFIG::CpuBandgapRefMode

This service controls CPU Bandgap bypass or not by programming the CPU EPOC2 bits (strap).

Default: 0: Normal 1: Bandgap Bypassed

Definition at line 150 of file OverclockingConfig.h.

◆ CpuD2dRatio

UINT8 OVERCLOCKING_PREMEM_CONFIG::CpuD2dRatio

Set CPU D2D Ratio from Range 15 to 40.

Default 0 indicates no setting.

Definition at line 348 of file OverclockingConfig.h.

◆ DisablePerCoreMask

UINT64 OVERCLOCKING_PREMEM_CONFIG::DisablePerCoreMask

Core disable mask is a bitwise indication of which core should be disabled, while ActiveCoreCount is to set the number of active cores.

Each bit represents physical core id for both P-core and E-core 1 - Disable 0 - Ignored Default is 0, means no Core disable mask setting.

Definition at line 302 of file OverclockingConfig.h.

◆ EcoreTvbTempThreshold0

UINT8 OVERCLOCKING_PREMEM_CONFIG::EcoreTvbTempThreshold0

Temperature Threshold 0 for all Ecores (in degrees C).

Running ABOVE this temperature will clip delta Down Bins for T0 from the resolved OC Ratio, when TVB ratio clipping is enabled from OCMB 0x18 Bit 2 = 0 (Enabled). 70 . Range 0-100.

Definition at line 451 of file OverclockingConfig.h.

◆ EcoreTvbTempThreshold1

UINT8 OVERCLOCKING_PREMEM_CONFIG::EcoreTvbTempThreshold1

Temperature Threshold 1 for all Ecores (in degrees C).

Running ABOVE this temperature will clip delta Down Bins for T1 from the resolved OC Ratio, when TVB ratio clipping is enabled from OCMB 0x18 Bit 2 = 0 (Enabled). 100 . Range 0-100.

Definition at line 457 of file OverclockingConfig.h.

◆ GtVfPointOffset

INT16 OVERCLOCKING_PREMEM_CONFIG::GtVfPointOffset[CPU_OC_MAX_VF_POINTS]

Array used to specifies the GT Voltage Offset applied to the each selected VF Point.

This voltage is specified in millivolts. Default: 0 Range: 0 to 1000

Definition at line 280 of file OverclockingConfig.h.

◆ GtVfPointOffsetMode

UINT8 OVERCLOCKING_PREMEM_CONFIG::GtVfPointOffsetMode

Selects GT Voltage & Frequency Point Offset between Legacy and Selection modes.

Need Reset System after enabling OverClocking Feature to initialize the default value. 0: In Legacy Mode, setting a global offset for the entire VF curve. 1: In Selection modes, setting a selected VF point.

Definition at line 274 of file OverclockingConfig.h.

◆ IaIccMax

UINT16 OVERCLOCKING_PREMEM_CONFIG::IaIccMax

Voltage Regulator Current Limit (Icc Max) for IA, GT and SA.

This value represents the Maximum instantaneous current allowed at any given time. The value is represented in 1/4 A increments. A value of 400 = 100A. 0 (HW default). Range is 4-2047.

Definition at line 262 of file OverclockingConfig.h.

◆ MemSSAdaptiveVoltage

UINT16 OVERCLOCKING_PREMEM_CONFIG::MemSSAdaptiveVoltage

Adaptive voltage target used to define the interpolation voltage point when the cpu is operating in adaptive mode range.

Used when MemSSVoltageMode = Adaptive. 0. no override. Range 0-2000mV.

Definition at line 401 of file OverclockingConfig.h.

◆ MemSSMaxOcRatio

UINT8 OVERCLOCKING_PREMEM_CONFIG::MemSSMaxOcRatio

Maximum Memory Subsystem ratio override allows to increase memory frequency beyond the fused max ring ratio limit.

0. no override/HW defaults.. Range non-turbo max - 109.

Definition at line 419 of file OverclockingConfig.h.

◆ MemSSVfPointOffset

INT16 OVERCLOCKING_PREMEM_CONFIG::MemSSVfPointOffset[CPU_OC_MAX_VF_POINTS]

Array used to specifies the Memory Subsystem Voltage Offset applied to the each selected VF Point.

This voltage is specified in millivolts. Default: 0 Range: 0 to 1000

Definition at line 336 of file OverclockingConfig.h.

◆ MemSSVfPointOffsetMode

UINT8 OVERCLOCKING_PREMEM_CONFIG::MemSSVfPointOffsetMode

Selects Memory Subsystem Voltage & Frequency Point Offset between Legacy and Selection modes.

Need Reset System after enabling OverClocking Feature to Initialize the default value. 0: In Legacy Mode, setting a global offset for the entire VF curve. 1: In Selection modes, setting a selected VF point.

Definition at line 414 of file OverclockingConfig.h.

◆ MemSSVoltageMode

UINT32 OVERCLOCKING_PREMEM_CONFIG::MemSSVoltageMode

Memory Subsystem voltage mode, specifies which voltage mode the processor will be operating.

0: Adaptive Mode allows the processor to interpolate a voltage curve when beyond fused P0 range; 1: Override, sets one voltage for the entire frequency range, Pn-P0.

Definition at line 166 of file OverclockingConfig.h.

◆ MemSSVoltageOffset

INT16 OVERCLOCKING_PREMEM_CONFIG::MemSSVoltageOffset

The Memory Subsystem voltage offset applied on top of all other voltage modes.

This offset is applied over the entire frequency range. This is a 2's complement number in mV units. Default: 0 Range: -1000 to 1000.

Definition at line 424 of file OverclockingConfig.h.

◆ MemSSVoltageOverride

UINT16 OVERCLOCKING_PREMEM_CONFIG::MemSSVoltageOverride

The Memory Subsystem voltage override which is applied to the entire range of uncore frequencies.

Used when MemSSVoltageMode = Override. 0. no override. Range 0-2000 mV.

Definition at line 407 of file OverclockingConfig.h.

◆ NclkTurboThermalProtection

UINT8 OVERCLOCKING_PREMEM_CONFIG::NclkTurboThermalProtection

NCLK Turbo Thermal Protection (TTP) control which allows user to disable Turbo Thermal Protection for SA.

This is a sticky bit, Once set, will remain set until cold or warm reset is performed. 0: Disable; 1: Enable

Definition at line 512 of file OverclockingConfig.h.

◆ NguMaxOcRatio

UINT8 OVERCLOCKING_PREMEM_CONFIG::NguMaxOcRatio

Maximum NGU ratio override allows to increase CPU NGU frequency beyond the fused max NGU ratio limit.

0. no override/HW defaults.. Range 0-34.

Definition at line 536 of file OverclockingConfig.h.

◆ NguRatio

UINT8 OVERCLOCKING_PREMEM_CONFIG::NguRatio

Sets the Ratio for NGU using SAVG B2P Mailbox cmd 0x22 and subcommand 0x1.

When this value is zero, dynamic mode is selected and NGU ratio can be modified using OCMB cmd 0x11. When valid ratio value is set, static mode is selected with the fixed ratio specified by this value.

Definition at line 542 of file OverclockingConfig.h.

◆ NguVfPointOffset

INT16 OVERCLOCKING_PREMEM_CONFIG::NguVfPointOffset[CPU_OC_MAX_VF_POINTS]

Array used to specifies the NGU Voltage Offset applied to the each selected VF Point.

This voltage is specified in millivolts. Default: 0 Range: 0 to 1000

Definition at line 567 of file OverclockingConfig.h.

◆ NguVfPointOffsetMode

UINT8 OVERCLOCKING_PREMEM_CONFIG::NguVfPointOffsetMode

Selects NGU Voltage & Frequency Point Offset between Legacy and Selection modes.

Need Reset System after enabling OverClocking Feature to initialize the default value. 0: In Legacy Mode, setting a global offset for the entire VF curve. 1: In Selection modes, setting a selected VF point.

Definition at line 561 of file OverclockingConfig.h.

◆ NguVoltageOffset

INT16 OVERCLOCKING_PREMEM_CONFIG::NguVoltageOffset

The NGU voltage offset applied on top of all other voltage modes.

This offset is applied over the entire frequency range. This is a 2's complement number in mV units. Default: 0 Range: -1000 to 1000.

Definition at line 554 of file OverclockingConfig.h.

◆ NguVoltageOverride

UINT16 OVERCLOCKING_PREMEM_CONFIG::NguVoltageOverride

The NGU voltage override which is applied to the entire range of cpu NGU frequencies.

Used when NguVoltageMode = Override. 0. no override. Range 0-2000 mV.

Definition at line 548 of file OverclockingConfig.h.

◆ OcSupport

UINT32 OVERCLOCKING_PREMEM_CONFIG::OcSupport

Overclocking support.

This controls whether OC mailbox transactions are sent. If disabled, all policies in this config block besides OcSupport and OcLock will be ignored. 0: Disable; 1: Enable.

Note
If PcdOverclockEnable is disabled, this should also be disabled.

Definition at line 82 of file OverclockingConfig.h.

◆ OcTvb

UINT8 OVERCLOCKING_PREMEM_CONFIG::OcTvb

OC TVB Enable/Disable.

This control will come into picture only when TVB Ratio clipping is enabled from OCMB 0x18/0x19 (bit 2). When disabled, BIOS will not send OC TVB parameter commands 0x24/0x25. When OcTvb is enabled, BIOS will allow user to modify and program new parameters for temperature thresholds T0, T1 and delta DownBins for T0 and T1. 0: Disable, 1: Enable.

Definition at line 433 of file OverclockingConfig.h.

◆ PcorePowerDensityThrottle

UINT8 OVERCLOCKING_PREMEM_CONFIG::PcorePowerDensityThrottle

Pcore Power Density Throttle control allows user to disable P-core throttling for power density protection.

This is a sticky bit, Once set, will remain set until cold or warm reset is performed. MailBox control is to disable the Pcore Power Density Throttling (reverse encoding is used). 0: Disable;1: Enable;

Definition at line 582 of file OverclockingConfig.h.

◆ PcoreTvbTempThreshold0

UINT8 OVERCLOCKING_PREMEM_CONFIG::PcoreTvbTempThreshold0

Temperature Threshold 0 for all Pcores (in degrees C).

Running ABOVE this temperature will clip delta Down Bins for T0 from the resolved OC Ratio, when TVB ratio clipping is enabled from OCMB 0x18 Bit 2 = 0 (Enabled). 70 . Range 0-100.

Definition at line 439 of file OverclockingConfig.h.

◆ PcoreTvbTempThreshold1

UINT8 OVERCLOCKING_PREMEM_CONFIG::PcoreTvbTempThreshold1

Temperature Threshold 1 for all Pcores (in degrees C).

Running ABOVE this temperature will clip delta Down Bins for T1 from the resolved OC Ratio, when TVB ratio clipping is enabled from OCMB 0x18 Bit 2 = 0 (Enabled). 100 . Range 0-100.

Definition at line 445 of file OverclockingConfig.h.

◆ PerCoreDisableConfiguration

UINT8 OVERCLOCKING_PREMEM_CONFIG::PerCoreDisableConfiguration

This configuration allows OC user to either use legacy num of cores option or the OC specific per core disable configuration.

0: Disable, 1: Enable

Definition at line 596 of file OverclockingConfig.h.

◆ PerCoreGranularityBins

UINT8 OVERCLOCKING_PREMEM_CONFIG::PerCoreGranularityBins[CPU_MAX_BIG_CORES]

Percore & PerAtomCluster Granularity Bins Override.

Array used to specifies the selected Core & AtomCluster Granularity Bins. It's a negative offset to current resolved P0 ratio, programming Granularity Bins will always reduce the core frequency. value is how many bins of 'Granularity Units' should be subtracted from the otherwise-configured P0 frequency. value = 0 (default) Range 0-255.

Definition at line 394 of file OverclockingConfig.h.

◆ PerCoreHtDisable

UINT16 OVERCLOCKING_PREMEM_CONFIG::PerCoreHtDisable

Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, 0 - is ignored.

Input is in HEX and each bit maps to a logical core. Ex. A value of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have HT enabled. Range is 0 - 0x1FF. You can only disable up to MAX_CORE_COUNT - 1.

Definition at line 308 of file OverclockingConfig.h.

◆ PerCoreVoltageOffset

INT16 OVERCLOCKING_PREMEM_CONFIG::PerCoreVoltageOffset[CPU_MAX_BIG_CORES]

Array used to specifies the selected Core Offset Voltage.

This voltage is specified in millivolts.

Definition at line 358 of file OverclockingConfig.h.

◆ PerEcoreCcpRatioDownBinAboveT0

UINT8 OVERCLOCKING_PREMEM_CONFIG::PerEcoreCcpRatioDownBinAboveT0[CPU_MAX_ATOM_CLUSTERS]

Down Bins (delta) for Temperature Threshold 0.

When running above T0, the ratio of Per Ecore module will be clipped by MAX_RATIO[n]-this value, when TVB ratio clipping is enabled from OCMB 0x18 Bit 2 = 0 (Enabled). 0 . Range 0-10.

Definition at line 482 of file OverclockingConfig.h.

◆ PerEcoreCcpRatioDownBinAboveT1

UINT8 OVERCLOCKING_PREMEM_CONFIG::PerEcoreCcpRatioDownBinAboveT1[CPU_MAX_ATOM_CLUSTERS]

Down Bins (delta) for Temperature Threshold 1.

When running above T1, the ratio of Per Ecore module will be clipped by MAX_RATIO[n]-this value, when TVB ratio clipping is enabled from OCMB 0x18 Bit 2 = 0 (Enabled). 0 . Range 0-10.

Definition at line 488 of file OverclockingConfig.h.

◆ PerPcoreGrRatioDownBinAboveT0

UINT8 OVERCLOCKING_PREMEM_CONFIG::PerPcoreGrRatioDownBinAboveT0[CPU_MAX_BIG_CORE_TRL_GROUPS]

Down Bins (delta) for Temperature Threshold 0.

When running above T0, the ratio of Per Pcore group will be clipped by MAX_RATIO[n]-this value, when TVB ratio clipping is enabled from OCMB 0x18 Bit 2 = 0 (Enabled). 1 . Range 0-10.

Definition at line 494 of file OverclockingConfig.h.

◆ PerPcoreGrRatioDownBinAboveT1

UINT8 OVERCLOCKING_PREMEM_CONFIG::PerPcoreGrRatioDownBinAboveT1[CPU_MAX_BIG_CORE_TRL_GROUPS]

Down Bins (delta) for Temperature Threshold 1.

When running above T1, the ratio of Per Pcore group will be clipped by MAX_RATIO[n]-this value, when TVB ratio clipping is enabled from OCMB 0x18 Bit 2 = 0 (Enabled). 2 . Range 0-10.

Definition at line 500 of file OverclockingConfig.h.

◆ PerPcoreRatioDownBinAboveT0

UINT8 OVERCLOCKING_PREMEM_CONFIG::PerPcoreRatioDownBinAboveT0[CPU_MAX_BIG_CORES]

Down Bins (delta) for Temperature Threshold 0.

When running above T0, the ratio of Per Pcore module will be clipped by MAX_RATIO[n]-this value, when TVB ratio clipping is enabled from OCMB 0x18 Bit 2 = 0 (Enabled). 1 . Range 0-10.

Definition at line 470 of file OverclockingConfig.h.

◆ PerPcoreRatioDownBinAboveT1

UINT8 OVERCLOCKING_PREMEM_CONFIG::PerPcoreRatioDownBinAboveT1[CPU_MAX_BIG_CORES]

Down Bins (delta) for Temperature Threshold 1.

When running above T1, the ratio of Per Pcore module will be clipped by MAX_RATIO[n]-this value, when TVB ratio clipping is enabled from OCMB 0x18 Bit 2 = 0 (Enabled). 2 . Range 0-10.

Definition at line 476 of file OverclockingConfig.h.

◆ ProcessVmaxLimit

UINT8 OVERCLOCKING_PREMEM_CONFIG::ProcessVmaxLimit

Disabling Process Vmax Limit will allow user to set any voltage.

If this limit is not disabled then, request above factory set limits will be rejected. This is a sticky bit, BIOS can only set this bit, it cannot be cleared by mailbox command. This setting persists over warm reset, and cleared on cold reset. MailBox control is to disable the ProcessVmaxLimit (reverse encoding is used). 0: Disable;1: Enable; Note: Disabling the voltage limit checks may cause permanent damage to processor. Note: This bit cannot be set after BIOS_RST_CPL.

Definition at line 576 of file OverclockingConfig.h.

◆ PvdMode

UINT8 OVERCLOCKING_PREMEM_CONFIG::PvdMode[2]

PVD Mode selects Static PVD ratio for SOC/CPU (when PVD THRESHOLD value is 0).

0x0 = div-1 (VCO = Output clock), 0x1 = div-2 (VCO = 2x Output clock) 0x2 = div-4 (VCO = 4x Output clock), 0x3 = div-8 (VCO = 8x Output clock)

Definition at line 386 of file OverclockingConfig.h.

◆ PvdRatioThreshold

UINT8 OVERCLOCKING_PREMEM_CONFIG::PvdRatioThreshold[2]

The Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio (P0 to Pn) to select the multiplier so that the output is within the DCO frequency range.

This threshold is applied to SA and MC/CMI PLL for SOC die and SA, Ring and Atom PLL when CPU die is selected. Range 0-63. When the threshold is 0, static PVD ratio is selected based on the PVD Mode for SOC. 0: Default.

Definition at line 380 of file OverclockingConfig.h.

◆ RingAdaptiveVoltage

UINT16 OVERCLOCKING_PREMEM_CONFIG::RingAdaptiveVoltage

Adaptive voltage target used to define the interpolation voltage point when the ring is operating in adaptive mode range.

Used when RingVoltageMode = Adaptive. 0. no override. Range 0-2000mV.

Definition at line 240 of file OverclockingConfig.h.

◆ RingDownBin

UINT32 OVERCLOCKING_PREMEM_CONFIG::RingDownBin

Ring Downbin enable/disable.

When enabled, the CPU will force the ring ratio to be lower than the core ratio. Disabling will allow the ring and core ratios to run at the same frequency. Uses OC Mailbox command 0x19. 0: Disables Ring Downbin feature. 1: Enables Ring downbin feature.

Definition at line 112 of file OverclockingConfig.h.

◆ RingMaxOcRatio

UINT8 OVERCLOCKING_PREMEM_CONFIG::RingMaxOcRatio

Maximum ring ratio override allows to increase CPU ring frequency beyond the fused max ring ratio limit.

0. no override/HW defaults.. Range non-turbo max - 85.

Definition at line 206 of file OverclockingConfig.h.

◆ RingTurboThermalProtection

UINT8 OVERCLOCKING_PREMEM_CONFIG::RingTurboThermalProtection

Ring Turbo Thermal Protection (TTP) control which allows user to disable Turbo Thermal Protection for Ring.

This is a sticky bit, Once set, will remain set until cold or warm reset is performed. 0: Disable; 1: Enable

Definition at line 506 of file OverclockingConfig.h.

◆ RingVfPointOffset

INT16 OVERCLOCKING_PREMEM_CONFIG::RingVfPointOffset[CPU_OC_MAX_VF_POINTS]

Array used to specifies the Ring Voltage Offset applied to the each selected VF Point.

This voltage is specified in millivolts. Default: 0 Range: 0 to 1000

Definition at line 329 of file OverclockingConfig.h.

◆ RingVfPointOffsetMode

UINT8 OVERCLOCKING_PREMEM_CONFIG::RingVfPointOffsetMode

Selects Ring Voltage & Frequency Point Offset between Legacy and Selection modes.

Need Reset System after enabling OverClocking Feature to initialize the default value. 0: In Legacy Mode, setting a global offset for the entire VF curve. 1: In Selection modes, setting a selected VF point.

Definition at line 323 of file OverclockingConfig.h.

◆ RingVoltageMode

UINT32 OVERCLOCKING_PREMEM_CONFIG::RingVoltageMode

Ring voltage mode, specifies which voltage mode the processor will be operating.

0: Adaptive Mode allows the processor to interpolate a voltage curve when beyond fused P0 range; 1: Override, sets one voltage for the entire frequency range, Pn-P0.

Definition at line 118 of file OverclockingConfig.h.

◆ RingVoltageOffset

INT16 OVERCLOCKING_PREMEM_CONFIG::RingVoltageOffset

The ring voltage offset applied on top of all other voltage modes.

This offset is applied over the entire frequency range. This is a 2's complement number in mV units. Default: 0 Range: -1000 to 1000.

Definition at line 245 of file OverclockingConfig.h.

◆ RingVoltageOverride

UINT16 OVERCLOCKING_PREMEM_CONFIG::RingVoltageOverride

The ring voltage override which is applied to the entire range of cpu ring frequencies.

Used when RingVoltageMode = Override. 0. no override. Range 0-2000 mV.

Definition at line 234 of file OverclockingConfig.h.

◆ SaAdaptiveVoltage

UINT16 OVERCLOCKING_PREMEM_CONFIG::SaAdaptiveVoltage

Adaptive voltage target used to define the interpolation voltage point when the SA/Uncore is operating in adaptive mode range.

Used when SaVoltageMode = Adaptive. 0. no override. Range 0-2000mV.

Definition at line 257 of file OverclockingConfig.h.

◆ SaVoltageMode

UINT32 OVERCLOCKING_PREMEM_CONFIG::SaVoltageMode

SA/Uncore voltage mode, specifies which voltage mode the processor will be operating.

0: Adaptive Mode allows the processor to interpolate a voltage curve when beyond fused P0 range; 1: Override, sets one voltage for the entire frequency range, Pn-P0.

Definition at line 125 of file OverclockingConfig.h.

◆ SaVoltageOverride

UINT16 OVERCLOCKING_PREMEM_CONFIG::SaVoltageOverride

The SA/Uncore voltage override which is applied to the entire range of uncore frequencies.

Used when SaVoltageMode = Override. 0. no override. Range 0-2000 mV.

Definition at line 251 of file OverclockingConfig.h.

◆ SocDieSscEnable

UINT8 OVERCLOCKING_PREMEM_CONFIG::SocDieSscEnable

Enable or Disable Soc Die SSC configuration.

  • 0: Disable
  • 1: Enable

Definition at line 526 of file OverclockingConfig.h.

◆ TjMaxOffset

UINT8 OVERCLOCKING_PREMEM_CONFIG::TjMaxOffset

TjMax Offset.

Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius. Default: 0 Hardware Defaults Range 10 to 63. 0 = No offset / Keep HW default.

Definition at line 211 of file OverclockingConfig.h.

◆ TurboThermalProtection

UINT8 OVERCLOCKING_PREMEM_CONFIG::TurboThermalProtection

Turbo Thermal Protection (TTP) control allows user to disable Turbo Thermal Protection.

This is a sticky bit, Once set, will remain set until cold or warm reset is performed. 0: Disable; 1: Enable

Definition at line 611 of file OverclockingConfig.h.

◆ TvbConfigLimitSelect

UINT8 OVERCLOCKING_PREMEM_CONFIG::TvbConfigLimitSelect

Limits Select, 0 - Per CCP (Module), Command Param2 = CCP ID, CCP ID can range from 0-15.

1 - Per Pcore group number, Command Param2 = Pcore Group Number (0-7), a Pcore active group has number of active cores as present in MSR 0x1AE. 0 .

Definition at line 464 of file OverclockingConfig.h.

◆ TvbRatioClipping

UINT32 OVERCLOCKING_PREMEM_CONFIG::TvbRatioClipping

This service controls Core frequency reduction caused by high package temperatures for processors that implement the Intel Thermal Velocity Boost (TVB) feature.

It is required to be disabled for supporting overclocking at frequencies higher than the default max turbo frequency. 0: Disables TVB ratio clipping. 1: Enables TVB ratio clipping.

Definition at line 132 of file OverclockingConfig.h.

◆ TvbVoltageOptimization

UINT32 OVERCLOCKING_PREMEM_CONFIG::TvbVoltageOptimization

This service controls thermal based voltage optimizations for processors that implement the Intel Thermal Velocity Boost (TVB) feature.

0: Disables TVB voltage optimization. 1: Enables TVB voltage optimization.

Definition at line 138 of file OverclockingConfig.h.

◆ UnderVoltProtection

UINT8 OVERCLOCKING_PREMEM_CONFIG::UnderVoltProtection

When UnderVolt Protection is enabled, user will be not be able to program under voltage in OS runtime.

0: protection is disabled, 1:protection is enabled .

Definition at line 353 of file OverclockingConfig.h.

◆ VcciaBootVoltageSel

UINT32 OVERCLOCKING_PREMEM_CONFIG::VcciaBootVoltageSel

This service controls VCCIA boot voltage by programming SOC-North soft straps.

Default: 0: Nominal 1: High Voltage (support VCCIA boot voltage higher than 1.65v (max 2.01v))

Definition at line 155 of file OverclockingConfig.h.

◆ VccsaBootVoltageSel

UINT32 OVERCLOCKING_PREMEM_CONFIG::VccsaBootVoltageSel

This service controls VCCSA Boot Voltage by programming the EPOC2 bits (strap).

Default: 0: Nominal 1: High Voltage(up to 1.2/1.3V)

Definition at line 145 of file OverclockingConfig.h.

The documentation for this struct was generated from the following file:
  • OverclockingConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
OVERCLOCKING_PREMEM_CONFIG Member List

This is the complete list of members for OVERCLOCKING_PREMEM_CONFIG, including all inherited members.

AtomClusterRatio | OVERCLOCKING_PREMEM_CONFIG
Avx2RatioOffset | OVERCLOCKING_PREMEM_CONFIG
Avx2VoltageScaleFactor | OVERCLOCKING_PREMEM_CONFIG
Avx3RatioOffset | OVERCLOCKING_PREMEM_CONFIG
Avx512VoltageScaleFactor | OVERCLOCKING_PREMEM_CONFIG
BclkAdaptiveVoltage | OVERCLOCKING_PREMEM_CONFIG
ComputeDieSscEnable | OVERCLOCKING_PREMEM_CONFIG
CoreAdaptiveVoltage | OVERCLOCKING_PREMEM_CONFIG
CoreMaxOcRatio | OVERCLOCKING_PREMEM_CONFIG
CoreMinRatio | OVERCLOCKING_PREMEM_CONFIG
CorePllCurrentRefTuningOffset | OVERCLOCKING_PREMEM_CONFIG
CorePllVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
CoreRatioExtensionMode | OVERCLOCKING_PREMEM_CONFIG
CoreVfConfigScope | OVERCLOCKING_PREMEM_CONFIG
CoreVfPointCount | OVERCLOCKING_PREMEM_CONFIG
CoreVfPointOffset | OVERCLOCKING_PREMEM_CONFIG
CoreVfPointOffsetMode | OVERCLOCKING_PREMEM_CONFIG
CoreVfPointRatio | OVERCLOCKING_PREMEM_CONFIG
CoreVoltageMode | OVERCLOCKING_PREMEM_CONFIG
CoreVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
CoreVoltageOverride | OVERCLOCKING_PREMEM_CONFIG
CpuBandgapRefMode | OVERCLOCKING_PREMEM_CONFIG
CpuBclkOcFrequency | OVERCLOCKING_PREMEM_CONFIG
CpuD2dRatio | OVERCLOCKING_PREMEM_CONFIG
CpuDlvrMode | OVERCLOCKING_PREMEM_CONFIG
CpuSaPllVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
DisablePerCoreMask | OVERCLOCKING_PREMEM_CONFIG
EcoreTvbTempThreshold0 | OVERCLOCKING_PREMEM_CONFIG
EcoreTvbTempThreshold1 | OVERCLOCKING_PREMEM_CONFIG
FllOverclockMode | OVERCLOCKING_PREMEM_CONFIG
ForcePcoreResidency | OVERCLOCKING_PREMEM_CONFIG
GranularRatioOverride | OVERCLOCKING_PREMEM_CONFIG
GtAdaptiveVoltage | OVERCLOCKING_PREMEM_CONFIG
GtIccUnlimitedMode | OVERCLOCKING_PREMEM_CONFIG
GtMaxOcRatio | OVERCLOCKING_PREMEM_CONFIG
GtVfPointCount | OVERCLOCKING_PREMEM_CONFIG
GtVfPointOffset | OVERCLOCKING_PREMEM_CONFIG
GtVfPointOffsetMode | OVERCLOCKING_PREMEM_CONFIG
GtVfPointRatio | OVERCLOCKING_PREMEM_CONFIG
GtVoltageMode | OVERCLOCKING_PREMEM_CONFIG
GtVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
GtVoltageOverride | OVERCLOCKING_PREMEM_CONFIG
Header | OVERCLOCKING_PREMEM_CONFIG
IaAtomPllCurrentRefTuningOffset | OVERCLOCKING_PREMEM_CONFIG
IaAtomPllVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
IaIccMax | OVERCLOCKING_PREMEM_CONFIG
IaIccUnlimitedMode | OVERCLOCKING_PREMEM_CONFIG
MaxVoltageLimit | OVERCLOCKING_PREMEM_CONFIG
McPllVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
MemSSAdaptiveVoltage | OVERCLOCKING_PREMEM_CONFIG
MemSSMaxOcRatio | OVERCLOCKING_PREMEM_CONFIG
MemSSVfPointCount | OVERCLOCKING_PREMEM_CONFIG
MemSSVfPointOffset | OVERCLOCKING_PREMEM_CONFIG
MemSSVfPointOffsetMode | OVERCLOCKING_PREMEM_CONFIG
MemSSVfPointRatio | OVERCLOCKING_PREMEM_CONFIG
MemSSVoltageMode | OVERCLOCKING_PREMEM_CONFIG
MemSSVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
MemSSVoltageOverride | OVERCLOCKING_PREMEM_CONFIG
NclkTurboThermalProtection | OVERCLOCKING_PREMEM_CONFIG
NguAdaptiveVoltage | OVERCLOCKING_PREMEM_CONFIG
NguMaxOcRatio | OVERCLOCKING_PREMEM_CONFIG
NguRatio | OVERCLOCKING_PREMEM_CONFIG
NguVfPointCount | OVERCLOCKING_PREMEM_CONFIG
NguVfPointOffset | OVERCLOCKING_PREMEM_CONFIG
NguVfPointOffsetMode | OVERCLOCKING_PREMEM_CONFIG
NguVfPointRatio | OVERCLOCKING_PREMEM_CONFIG
NguVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
NguVoltageOverride | OVERCLOCKING_PREMEM_CONFIG
NpuAdaptiveVoltage | OVERCLOCKING_PREMEM_CONFIG
NpuMaxOcRatio | OVERCLOCKING_PREMEM_CONFIG
NpuVoltageMode | OVERCLOCKING_PREMEM_CONFIG
NpuVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
NpuVoltageOverride | OVERCLOCKING_PREMEM_CONFIG
OcSupport | OVERCLOCKING_PREMEM_CONFIG
OcTvb | OVERCLOCKING_PREMEM_CONFIG
PcorePowerDensityThrottle | OVERCLOCKING_PREMEM_CONFIG
PcoreTvbTempThreshold0 | OVERCLOCKING_PREMEM_CONFIG
PcoreTvbTempThreshold1 | OVERCLOCKING_PREMEM_CONFIG
PerAtomClusterAdaptiveVoltage | OVERCLOCKING_PREMEM_CONFIG
PerAtomClusterMaxRatio | OVERCLOCKING_PREMEM_CONFIG
PerAtomClusterVoltageMode | OVERCLOCKING_PREMEM_CONFIG
PerAtomClusterVoltageOverride | OVERCLOCKING_PREMEM_CONFIG
PerCoreAdaptiveVoltage | OVERCLOCKING_PREMEM_CONFIG
PerCoreDisableConfiguration | OVERCLOCKING_PREMEM_CONFIG
PerCoreGranularityBins | OVERCLOCKING_PREMEM_CONFIG
PerCoreHtDisable | OVERCLOCKING_PREMEM_CONFIG
PerCoreMaxRatio | OVERCLOCKING_PREMEM_CONFIG
PerCoreRatioOverride | OVERCLOCKING_PREMEM_CONFIG
PerCoreVoltageMode | OVERCLOCKING_PREMEM_CONFIG
PerCoreVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
PerCoreVoltageOverride | OVERCLOCKING_PREMEM_CONFIG
PerEcoreCcpRatioDownBinAboveT0 | OVERCLOCKING_PREMEM_CONFIG
PerEcoreCcpRatioDownBinAboveT1 | OVERCLOCKING_PREMEM_CONFIG
PerPcoreGrRatioDownBinAboveT0 | OVERCLOCKING_PREMEM_CONFIG
PerPcoreGrRatioDownBinAboveT1 | OVERCLOCKING_PREMEM_CONFIG
PerPcoreRatioDownBinAboveT0 | OVERCLOCKING_PREMEM_CONFIG
PerPcoreRatioDownBinAboveT1 | OVERCLOCKING_PREMEM_CONFIG
ProcessVmaxLimit | OVERCLOCKING_PREMEM_CONFIG
PvdMode | OVERCLOCKING_PREMEM_CONFIG
PvdRatioThreshold | OVERCLOCKING_PREMEM_CONFIG
RealtimeMemoryTiming | OVERCLOCKING_PREMEM_CONFIG
RingAdaptiveVoltage | OVERCLOCKING_PREMEM_CONFIG
RingDownBin | OVERCLOCKING_PREMEM_CONFIG
RingMaxOcRatio | OVERCLOCKING_PREMEM_CONFIG
RingPllCurrentRefTuningOffset | OVERCLOCKING_PREMEM_CONFIG
RingPllVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
RingTurboThermalProtection | OVERCLOCKING_PREMEM_CONFIG
RingVfPointCount | OVERCLOCKING_PREMEM_CONFIG
RingVfPointOffset | OVERCLOCKING_PREMEM_CONFIG
RingVfPointOffsetMode | OVERCLOCKING_PREMEM_CONFIG
RingVfPointRatio | OVERCLOCKING_PREMEM_CONFIG
RingVoltageMode | OVERCLOCKING_PREMEM_CONFIG
RingVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
RingVoltageOverride | OVERCLOCKING_PREMEM_CONFIG
RsvdBits1 | OVERCLOCKING_PREMEM_CONFIG
SaAdaptiveVoltage | OVERCLOCKING_PREMEM_CONFIG
SaIccUnlimitedMode | OVERCLOCKING_PREMEM_CONFIG
SaPllFreqOverride | OVERCLOCKING_PREMEM_CONFIG
SaPllVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
SaVoltageMode | OVERCLOCKING_PREMEM_CONFIG
SaVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
SaVoltageOverride | OVERCLOCKING_PREMEM_CONFIG
SocBclkOcFrequency | OVERCLOCKING_PREMEM_CONFIG
SocDieSscEnable | OVERCLOCKING_PREMEM_CONFIG
TjMaxOffset | OVERCLOCKING_PREMEM_CONFIG
TscDisableHwFixup | OVERCLOCKING_PREMEM_CONFIG
TurboThermalProtection | OVERCLOCKING_PREMEM_CONFIG
TvbConfigLimitSelect | OVERCLOCKING_PREMEM_CONFIG
TvbRatioClipping | OVERCLOCKING_PREMEM_CONFIG
TvbVoltageOptimization | OVERCLOCKING_PREMEM_CONFIG
UnderVoltProtection | OVERCLOCKING_PREMEM_CONFIG
VcciaBootVoltageSel | OVERCLOCKING_PREMEM_CONFIG
VccsaBootVoltageSel | OVERCLOCKING_PREMEM_CONFIG
VrLimitBypass | OVERCLOCKING_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_DCI_PREMEM_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
PCH_DCI_PREMEM_CONFIG Struct Reference

The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct Connection Interface (DCI) More...

#include <DciConfig.h>

Collaboration diagram for PCH_DCI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 | DciEn
DCI enable. More...
UINT8 | DciDbcMode
USB DbC enable mode. More...
UINT8 | DciUsb3TypecUfpDbg
USB3 Type-C UFP2DFP kenel / platform debug support. More...
UINT8 | DciClkEnable
Determine if to enable or disable DCI clock request in lowest power state. More...
UINT8 | KeepEarlyTrace
Early trace is activated by default. More...

Detailed Description

The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct Connection Interface (DCI)

Revision 1:

  • Initial version.

Definition at line 74 of file DciConfig.h.

Member Data Documentation

◆ DciClkEnable

UINT8 PCH_DCI_PREMEM_CONFIG::DciClkEnable

Determine if to enable or disable DCI clock request in lowest power state.

0:Disabled; 1:Enabled

Definition at line 101 of file DciConfig.h.

◆ DciDbcMode

UINT8 PCH_DCI_PREMEM_CONFIG::DciDbcMode

USB DbC enable mode.

Disabled: Clear both USB2/3DBCEN; USB2: Set USB2DBCEN; USB3: Set USB3DBCEN; Both: Set both USB2/3DBCEN; No Change: Comply with HW value Refer to definition of DCI_USB_DBC_MODE for supported settings. 0:Disabled; 1:USB2; 2:USB3; 3:Both; 4:No Change

Definition at line 88 of file DciConfig.h.

◆ DciEn

UINT8 PCH_DCI_PREMEM_CONFIG::DciEn

DCI enable.

Determine if to enable DCI debug from host. 0:Disabled; 1:Enabled

Definition at line 81 of file DciConfig.h.

◆ DciUsb3TypecUfpDbg

UINT8 PCH_DCI_PREMEM_CONFIG::DciUsb3TypecUfpDbg

USB3 Type-C UFP2DFP kenel / platform debug support.

No change will do nothing to UFP2DFP configuration. When enabled, USB3 Type C UFP (upstream-facing port) may switch to DFP (downstream-facing port) for first connection. It must be enabled for USB3 kernel(kernel mode debug) and platform debug(DFx, DMA, Trace) over UFP Type-C receptacle. Refer to definition of DCI_USB_TYPE_C_DEBUG_MODE for supported settings. 0:Disabled; 1:Enabled; 2:No Change

Definition at line 96 of file DciConfig.h.

◆ KeepEarlyTrace

UINT8 PCH_DCI_PREMEM_CONFIG::KeepEarlyTrace

Early trace is activated by default.

Enable to keep early trace data and keep tracing; disable to stop tracing; When debug probe is connected and granted, force to no change, let host tool to set it. 0: Disable; 1: Enable early trace; 2:No Change;

Definition at line 108 of file DciConfig.h.

The documentation for this struct was generated from the following file:
  • DciConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_DCI_PREMEM_CONFIG Member List

This is the complete list of members for PCH_DCI_PREMEM_CONFIG, including all inherited members.

DciClkEnable | PCH_DCI_PREMEM_CONFIG
DciDbcMode | PCH_DCI_PREMEM_CONFIG
DciEn | PCH_DCI_PREMEM_CONFIG
DciUsb3TypecUfpDbg | PCH_DCI_PREMEM_CONFIG
Header | PCH_DCI_PREMEM_CONFIG
KeepEarlyTrace | PCH_DCI_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_DEVICE_INTERRUPT_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
PCH_DEVICE_INTERRUPT_CONFIG Struct Reference

The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. More...

#include <InterruptConfig.h>

Public Attributes

UINT8 | Device
Device number.
UINT8 | Function
Device function.
UINT8 | IntX
Interrupt pin: INTA-INTD (see PCH_INT_PIN)
UINT8 | Irq
IRQ to be set for device.

Detailed Description

The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.

Definition at line 59 of file InterruptConfig.h.

The documentation for this struct was generated from the following file:
  • InterruptConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_DEVICE_INTERRUPT_CONFIG Member List

This is the complete list of members for PCH_DEVICE_INTERRUPT_CONFIG, including all inherited members.

Device | PCH_DEVICE_INTERRUPT_CONFIG
Function | PCH_DEVICE_INTERRUPT_CONFIG
IntX | PCH_DEVICE_INTERRUPT_CONFIG
Irq | PCH_DEVICE_INTERRUPT_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_DMI_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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PCH_DMI_CONFIG Struct Reference

The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI. More...

#include <PchDmiConfig.h>

Collaboration diagram for PCH_DMI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | PwrOptEnable: 1
0: Disable; 1: Enable DMI Power Optimizer on PCH side.
UINT32 | DmiAspmCtrl: 8
ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig
UINT32 | CwbEnable: 1
0: Disable; 1: Enable Central Write Buffer feature configurable and enabled by default
UINT32 | L1RpCtl: 1
0: Disable; 1: Enable Allow DMI enter L1 when all root ports are in L1, L0s or link down. Disabled by default.
UINT32 | DmiPowerReduction: 1
When set to TRUE turns on: More...
UINT32 | ClockGating: 1
0: Disable; 1: Enable clock gating.
UINT32 | Rsvdbits: 19
Reserved bits.

Detailed Description

The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI.

Revision 1:

  • Initial version.

Definition at line 50 of file PchDmiConfig.h.

Member Data Documentation

◆ DmiPowerReduction

UINT32 PCH_DMI_CONFIG::DmiPowerReduction

When set to TRUE turns on:

  • L1 State Controller Power Gating
  • L1 State PHY Data Lane Power Gating
  • PHY Common Lane Power Gating
  • Hardware Autonomous Enable
  • PMC Request Enable and Sleep Enable

Definition at line 65 of file PchDmiConfig.h.

The documentation for this struct was generated from the following file:
  • PchDmiConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_DMI_CONFIG Member List

This is the complete list of members for PCH_DMI_CONFIG, including all inherited members.

ClockGating | PCH_DMI_CONFIG
CwbEnable | PCH_DMI_CONFIG
DmiAspmCtrl | PCH_DMI_CONFIG
DmiPowerReduction | PCH_DMI_CONFIG
Header | PCH_DMI_CONFIG
L1RpCtl | PCH_DMI_CONFIG
PwrOptEnable | PCH_DMI_CONFIG
Rsvdbits | PCH_DMI_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_FIVR_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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PCH_FIVR_CONFIG Struct Reference

The PCH_FIVR_CONFIG block describes FIVR settings. More...

#include <FivrConfig.h>

Collaboration diagram for PCH_FIVR_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
FIVR_EXT_RAIL_CONFIG ExtV1p05Rail
External V1P05 VR rail configuration.
FIVR_EXT_RAIL_CONFIG ExtVnnRail
External Vnn VR rail configuration.
FIVR_EXT_RAIL_CONFIG ExtVnnRailSx
Additional External Vnn VR rail configuration that will get applied in Sx entry SMI callback. More...
FIVR_VCCIN_AUX_CONFIG VccinAux
VCCIN_AUX voltage rail configuration.
UINT32 FivrDynPm: 1
Enable/Disable FIVR Dynamic Power Management Default is 1 .

Detailed Description

The PCH_FIVR_CONFIG block describes FIVR settings.

Definition at line 164 of file FivrConfig.h.

Member Data Documentation

◆ ExtVnnRailSx

FIVR_EXT_RAIL_CONFIG PCH_FIVR_CONFIG::ExtVnnRailSx

Additional External Vnn VR rail configuration that will get applied in Sx entry SMI callback.

Required only if External Vnn VR needs different settings for Sx than those specified in ExtVnnRail.

Definition at line 179 of file FivrConfig.h.

The documentation for this struct was generated from the following file:
  • FivrConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_FIVR_CONFIG Member List

This is the complete list of members for PCH_FIVR_CONFIG, including all inherited members.

ExtV1p05Rail | PCH_FIVR_CONFIG
ExtVnnRail | PCH_FIVR_CONFIG
ExtVnnRailSx | PCH_FIVR_CONFIG
FivrDynPm | PCH_FIVR_CONFIG
Header | PCH_FIVR_CONFIG
VccinAux | PCH_FIVR_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_FLASH_PROTECTION_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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PCH_FLASH_PROTECTION_CONFIG Struct Reference

The PCH provides a method for blocking writes and reads to specific ranges in the SPI flash when the Protected Ranges are enabled. More...

#include <FlashProtectionConfig.h>

Collaboration diagram for PCH_FLASH_PROTECTION_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
PROTECTED_RANGE ProtectRange [PCH_FLASH_PROTECTED_RANGES]
Protected Flash Ranges.

Detailed Description

The PCH provides a method for blocking writes and reads to specific ranges in the SPI flash when the Protected Ranges are enabled.

PROTECTED_RANGE is used to specify if flash protection are enabled, the write protection enable bit and the read protection enable bit, and to specify the upper limit and lower base for each register Platform code is responsible to get the range base by PchGetSpiRegionAddresses routine, and set the limit and base accordingly.

Definition at line 76 of file FlashProtectionConfig.h.

The documentation for this struct was generated from the following file:
  • FlashProtectionConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_FLASH_PROTECTION_CONFIG Member List

This is the complete list of members for PCH_FLASH_PROTECTION_CONFIG, including all inherited members.

Header | PCH_FLASH_PROTECTION_CONFIG
ProtectRange | PCH_FLASH_PROTECTION_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_GENERAL_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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PCH_GENERAL_CONFIG Struct Reference

PCH General Configuration Revision 2: - Add VtdEnabled field. More...

#include <PchGeneralConfig.h>

Collaboration diagram for PCH_GENERAL_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Crid: 1
This member describes whether or not the Compatibility Revision ID (CRID) feature of PCH should be enabled. More...
UINT32 | LegacyIoLowLatency: 1
Set to enable low latency of legacy IO. More...
UINT32 | VtdEnabled: 1
This member describes whether or not the VTD feature should be enabled in PCH. More...
UINT32 | RsvdBits0: 29
Reserved bits.

Detailed Description

PCH General Configuration Revision 2: - Add VtdEnabled field.

Definition at line 67 of file PchGeneralConfig.h.

Member Data Documentation

◆ Crid

UINT32 PCH_GENERAL_CONFIG::Crid

This member describes whether or not the Compatibility Revision ID (CRID) feature of PCH should be enabled.

0: Disable; 1: Enable

Definition at line 73 of file PchGeneralConfig.h.

◆ LegacyIoLowLatency

UINT32 PCH_GENERAL_CONFIG::LegacyIoLowLatency

Set to enable low latency of legacy IO.

Some systems require lower IO latency irrespective of power. This is a tradeoff between power and IO latency.

Note
: Once this is enabled, DmiAspm, Pcie DmiAspm in SystemAgent and ITSS Clock Gating are forced to disabled. 0: Disable, 1: Enable

Definition at line 82 of file PchGeneralConfig.h.

◆ VtdEnabled

UINT32 PCH_GENERAL_CONFIG::VtdEnabled

This member describes whether or not the VTD feature should be enabled in PCH.

0: Disable; 1: Enable

Definition at line 87 of file PchGeneralConfig.h.

The documentation for this struct was generated from the following file:
  • PchGeneralConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_GENERAL_CONFIG Member List

This is the complete list of members for PCH_GENERAL_CONFIG, including all inherited members.

Crid | PCH_GENERAL_CONFIG
Header | PCH_GENERAL_CONFIG
LegacyIoLowLatency | PCH_GENERAL_CONFIG
RsvdBits0 | PCH_GENERAL_CONFIG
VtdEnabled | PCH_GENERAL_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_HSIO_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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PCH_HSIO_CONFIG Struct Reference

The PCH_HSIO_CONFIG block provides HSIO message related settings. More...

#include <HsioConfig.h>

Collaboration diagram for PCH_HSIO_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | ChipsetInitBinPtr
Policy used to point to the Base (+ OEM) ChipsetInit binary used to sync between BIOS and CSME.
UINT32 | ChipsetInitBinLen
Policy used to indicate the size of the Base (+ OEM) ChipsetInit binary used to sync between BIOS and CSME.
UINT32 | NphyBinPtr
Policy used to point to the OEM Nphy binary used to sync between BIOS and CSME.
UINT32 | NphyBinLen
Policy used to indicate the size of the OEM Nphy binary used to sync between BIOS and CSME.
UINT32 | SynpsPhyBinPtr
Policy used to point to the OEM Synophsys Phy binary used to sync between BIOS and CSME.
UINT32 | SynpsPhyBinLen
Policy used to indicate the size of the OEM Synophsys Phy binary used to sync between BIOS and CSME.

Detailed Description

The PCH_HSIO_CONFIG block provides HSIO message related settings.

Definition at line 83 of file HsioConfig.h.

The documentation for this struct was generated from the following file:
  • HsioConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_HSIO_CONFIG Member List

This is the complete list of members for PCH_HSIO_CONFIG, including all inherited members.

ChipsetInitBinLen | PCH_HSIO_CONFIG
ChipsetInitBinPtr | PCH_HSIO_CONFIG
Header | PCH_HSIO_CONFIG
NphyBinLen | PCH_HSIO_CONFIG
NphyBinPtr | PCH_HSIO_CONFIG
SynpsPhyBinLen | PCH_HSIO_CONFIG
SynpsPhyBinPtr | PCH_HSIO_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_HSIO_PCIE_LANE_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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PCH_HSIO_PCIE_LANE_CONFIG Struct Reference

The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane. More...

#include <HsioPcieConfig.h>

Public Attributes

UINT32 | HsioRxSetCtleEnable: 1
0: Disable; 1: Enable PCH PCIe Gen 3 Set CTLE Value
UINT32 | HsioRxSetCtle: 6
PCH PCIe Gen 3 Set CTLE Value.
UINT32 | HsioTxGen1DownscaleAmpEnable: 1
0: Disable; 1: Enable PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value override
UINT32 | HsioTxGen1DownscaleAmp: 6
PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value.
UINT32 | HsioTxGen2DownscaleAmpEnable: 1
0: Disable; 1: Enable PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value override
UINT32 | HsioTxGen2DownscaleAmp: 6
PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
UINT32 | HsioTxGen3DownscaleAmpEnable: 1
0: Disable; 1: Enable PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value override
UINT32 | HsioTxGen3DownscaleAmp: 6
PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
UINT32 | RsvdBits0: 4
Reserved Bits.
UINT32 | HsioTxGen1DeEmphEnable: 1
0: Disable; 1: Enable PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting value override
UINT32 | HsioTxGen1DeEmph: 6
PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
UINT32 | HsioTxGen2DeEmph3p5Enable: 1
0: Disable; 1: Enable PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting value override
UINT32 | HsioTxGen2DeEmph3p5: 6
PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting.
UINT32 | HsioTxGen2DeEmph6p0Enable: 1
0: Disable; 1: Enable PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting value override
UINT32 | HsioTxGen2DeEmph6p0: 6
PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting.
UINT32 | RsvdBits1: 11
Reserved Bits.

Detailed Description

The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane.

Definition at line 48 of file HsioPcieConfig.h.

The documentation for this struct was generated from the following file:
  • HsioPcieConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_HSIO_PCIE_LANE_CONFIG Member List

This is the complete list of members for PCH_HSIO_PCIE_LANE_CONFIG, including all inherited members.

HsioRxSetCtle | PCH_HSIO_PCIE_LANE_CONFIG
HsioRxSetCtleEnable | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen1DeEmph | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen1DeEmphEnable | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen1DownscaleAmp | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen1DownscaleAmpEnable | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen2DeEmph3p5 | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen2DeEmph3p5Enable | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen2DeEmph6p0 | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen2DeEmph6p0Enable | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen2DownscaleAmp | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen2DownscaleAmpEnable | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen3DownscaleAmp | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen3DownscaleAmpEnable | PCH_HSIO_PCIE_LANE_CONFIG
RsvdBits0 | PCH_HSIO_PCIE_LANE_CONFIG
RsvdBits1 | PCH_HSIO_PCIE_LANE_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_HSIO_PCIE_PREMEM_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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PCH_HSIO_PCIE_PREMEM_CONFIG Struct Reference

The PCH_HSIO_PCIE_CONFIG block describes the configuration of the HSIO for PCIe lanes. More...

#include <HsioPcieConfig.h>

Collaboration diagram for PCH_HSIO_PCIE_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
PCH_HSIO_PCIE_LANE_CONFIG Lane [PCH_MAX_PCIE_ROOT_PORTS]
These members describe the configuration of HSIO for PCIe lanes.

Detailed Description

The PCH_HSIO_PCIE_CONFIG block describes the configuration of the HSIO for PCIe lanes.

Definition at line 76 of file HsioPcieConfig.h.

The documentation for this struct was generated from the following file:
  • HsioPcieConfig.h


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_HSIO_PCIE_PREMEM_CONFIG Member List

This is the complete list of members for PCH_HSIO_PCIE_PREMEM_CONFIG, including all inherited members.

Header | PCH_HSIO_PCIE_PREMEM_CONFIG
Lane | PCH_HSIO_PCIE_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_HSIO_PREMEM_CONFIG Struct Reference

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PCH_HSIO_PREMEM_CONFIG Struct Reference

The PCH_HSIO_PREMEM_CONFIG block provides HSIO message related settings. More...

#include <HsioConfig.h>

Collaboration diagram for PCH_HSIO_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 | ChipsetInitMessage
(Test) 0- Disable, disable will prevent the HSIO version check and ChipsetInit HECI message from being sent 1- Enable ChipsetInit HECI message
UINT8 | BypassPhySyncReset
(Test) 0- Disable 1- Enable When enabled, this is used to bypass the reset after ChipsetInit HECI message.

Detailed Description

The PCH_HSIO_PREMEM_CONFIG block provides HSIO message related settings.

Definition at line 60 of file HsioConfig.h.

The documentation for this struct was generated from the following file:
  • HsioConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_HSIO_PREMEM_CONFIG Member List

This is the complete list of members for PCH_HSIO_PREMEM_CONFIG, including all inherited members.

BypassPhySyncReset | PCH_HSIO_PREMEM_CONFIG
ChipsetInitMessage | PCH_HSIO_PREMEM_CONFIG
Header | PCH_HSIO_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_HSIO_SATA_PORT_LANE Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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PCH_HSIO_SATA_PORT_LANE Struct Reference

The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane. More...

#include <HsioSataConfig.h>

Public Attributes

UINT32 | HsioRxGen1EqBoostMagEnable: 1
0: Disable; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
UINT32 | HsioRxGen1EqBoostMag: 6
SATA 1.5 Gb/sReceiver Equalization Boost Magnitude Adjustment value.
UINT32 | HsioRxGen2EqBoostMagEnable: 1
0: Disable; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
UINT32 | HsioRxGen2EqBoostMag: 6
SATA 3.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value.
UINT32 | HsioRxGen3EqBoostMagEnable: 1
0: Disable; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
UINT32 | HsioRxGen3EqBoostMag: 6
SATA 6.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value.
UINT32 | HsioTxGen1DownscaleAmpEnable: 1
0: Disable; 1: Enable SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
UINT32 | HsioTxGen1DownscaleAmp: 6
SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.
UINT32 | RsvdBits0: 4
Reserved bits.
UINT32 | HsioTxGen2DownscaleAmpEnable: 1
0: Disable; 1: Enable SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
UINT32 | HsioTxGen2DownscaleAmp: 6
SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment.
UINT32 | HsioTxGen3DownscaleAmpEnable: 1
0: Disable; 1: Enable SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
UINT32 | HsioTxGen3DownscaleAmp: 6
SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment.
UINT32 | HsioTxGen1DeEmphEnable: 1
0: Disable; 1: Enable SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
UINT32 | HsioTxGen1DeEmph: 6
SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.
UINT32 | HsioTxGen2DeEmphEnable: 1
0: Disable; 1: Enable SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
UINT32 | HsioTxGen2DeEmph: 6
SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.
UINT32 | RsvdBits1: 4
Reserved bits.
UINT32 | HsioTxGen3DeEmphEnable: 1
0: Disable; 1: Enable SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
UINT32 | HsioTxGen3DeEmph: 6
SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override.
UINT32 | RsvdBits2: 25
Reserved bits.

Detailed Description

The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane.

Definition at line 46 of file HsioSataConfig.h.

The documentation for this struct was generated from the following file:
  • HsioSataConfig.h


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_HSIO_SATA_PORT_LANE Member List

This is the complete list of members for PCH_HSIO_SATA_PORT_LANE, including all inherited members.

HsioRxGen1EqBoostMag | PCH_HSIO_SATA_PORT_LANE
HsioRxGen1EqBoostMagEnable | PCH_HSIO_SATA_PORT_LANE
HsioRxGen2EqBoostMag | PCH_HSIO_SATA_PORT_LANE
HsioRxGen2EqBoostMagEnable | PCH_HSIO_SATA_PORT_LANE
HsioRxGen3EqBoostMag | PCH_HSIO_SATA_PORT_LANE
HsioRxGen3EqBoostMagEnable | PCH_HSIO_SATA_PORT_LANE
HsioTxGen1DeEmph | PCH_HSIO_SATA_PORT_LANE
HsioTxGen1DeEmphEnable | PCH_HSIO_SATA_PORT_LANE
HsioTxGen1DownscaleAmp | PCH_HSIO_SATA_PORT_LANE
HsioTxGen1DownscaleAmpEnable | PCH_HSIO_SATA_PORT_LANE
HsioTxGen2DeEmph | PCH_HSIO_SATA_PORT_LANE
HsioTxGen2DeEmphEnable | PCH_HSIO_SATA_PORT_LANE
HsioTxGen2DownscaleAmp | PCH_HSIO_SATA_PORT_LANE
HsioTxGen2DownscaleAmpEnable | PCH_HSIO_SATA_PORT_LANE
HsioTxGen3DeEmph | PCH_HSIO_SATA_PORT_LANE
HsioTxGen3DeEmphEnable | PCH_HSIO_SATA_PORT_LANE
HsioTxGen3DownscaleAmp | PCH_HSIO_SATA_PORT_LANE
HsioTxGen3DownscaleAmpEnable | PCH_HSIO_SATA_PORT_LANE
RsvdBits0 | PCH_HSIO_SATA_PORT_LANE
RsvdBits1 | PCH_HSIO_SATA_PORT_LANE
RsvdBits2 | PCH_HSIO_SATA_PORT_LANE


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_HSIO_SATA_PREMEM_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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PCH_HSIO_SATA_PREMEM_CONFIG Struct Reference

The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the SATA controller. More...

#include <HsioSataConfig.h>

Collaboration diagram for PCH_HSIO_SATA_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
PCH_HSIO_SATA_PORT_LANE PortLane [PCH_MAX_SATA_PORTS]
These members describe the configuration of HSIO for SATA lanes.

Detailed Description

The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the SATA controller.

Definition at line 82 of file HsioSataConfig.h.

The documentation for this struct was generated from the following file:
  • HsioSataConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_HSIO_SATA_PREMEM_CONFIG Member List

This is the complete list of members for PCH_HSIO_SATA_PREMEM_CONFIG, including all inherited members.

Header | PCH_HSIO_SATA_PREMEM_CONFIG
PortLane | PCH_HSIO_SATA_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_INTERRUPT_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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PCH_INTERRUPT_CONFIG Struct Reference

The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH. More...

#include <InterruptConfig.h>

Collaboration diagram for PCH_INTERRUPT_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 | NumOfDevIntConfig
Number of entries in DevIntConfig table.
UINT8 | Rsvd0 [3]
Reserved bytes, align to multiple 4.
PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig [PCH_MAX_DEVICE_INTERRUPT_CONFIG]
Array which stores PCH devices interrupts settings.
UINT8 | GpioIrqRoute
Interrupt routing for GPIO. Default is 14.
UINT8 | SciIrqSelect
Interrupt select for SCI. Default is 9.
UINT8 | TcoIrqSelect
Interrupt select for TCO. Default is 9.
UINT8 | TcoIrqEnable
Enable IRQ generation for TCO. 0: Disable; 1: Enable.

Detailed Description

The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH.

Definition at line 75 of file InterruptConfig.h.

The documentation for this struct was generated from the following file:
  • InterruptConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_INTERRUPT_CONFIG Member List

This is the complete list of members for PCH_INTERRUPT_CONFIG, including all inherited members.

DevIntConfig | PCH_INTERRUPT_CONFIG
GpioIrqRoute | PCH_INTERRUPT_CONFIG
Header | PCH_INTERRUPT_CONFIG
NumOfDevIntConfig | PCH_INTERRUPT_CONFIG
Rsvd0 | PCH_INTERRUPT_CONFIG
SciIrqSelect | PCH_INTERRUPT_CONFIG
TcoIrqEnable | PCH_INTERRUPT_CONFIG
TcoIrqSelect | PCH_INTERRUPT_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_IOAPIC_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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PCH_IOAPIC_CONFIG Struct Reference

The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is not TRUE. More...

#include <IoApicConfig.h>

Collaboration diagram for PCH_IOAPIC_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | IoApicEntry24_119: 1
0: Disable; 1: Enable IOAPIC Entry 24-119
UINT32 | Enable8254ClockGating: 1
Enable 8254 Static Clock Gating during early POST time. More...
UINT32 | Enable8254ClockGatingOnS3: 1
Enable 8254 Static Clock Gating on S3 resume path. More...
UINT32 | RsvdBits1: 29
Reserved bits.
UINT8 | IoApicId
This member determines IOAPIC ID. Default is 0x02.
UINT8 | Rsvd0 [3]
Reserved bytes.

Detailed Description

The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is not TRUE.

Bus:device:function fields will be programmed to the register P2SB IBDF(P2SB PCI offset R6Ch-6Dh), it's using for the following purpose: As the Requester ID when initiating Interrupt Messages to the processor. As the Completer ID when responding to the reads targeting the IOxAPI's Memory-Mapped I/O registers. This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can program this field to provide a unique Bus:Device:Function number for the internal IOxAPIC. The address resource range of IOAPIC must be reserved in E820 and ACPI as system resource.

Definition at line 57 of file IoApicConfig.h.

Member Data Documentation

◆ Enable8254ClockGating

UINT32 PCH_IOAPIC_CONFIG::Enable8254ClockGating

Enable 8254 Static Clock Gating during early POST time.

0: Disable, 1: Enable Setting 8254CGE is required to support SLP_S0. Enable this if 8254 timer is not used. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support legacy OS using 8254 timer.

Note
: For some OS environment that it needs to set 8254CGE in late state it should set this policy to FALSE and use ItssSet8254ClockGateState (TRUE) in SMM later. This is also required during S3 resume. To avoid SMI requirement in S3 reusme path, it can enable the Enable8254ClockGatingOnS3 and RC will do 8254 CGE programming in PEI during S3 resume with BOOT_SAI.

Definition at line 73 of file IoApicConfig.h.

◆ Enable8254ClockGatingOnS3

UINT32 PCH_IOAPIC_CONFIG::Enable8254ClockGatingOnS3

Enable 8254 Static Clock Gating on S3 resume path.

0: Disable, 1: Enable This is only applicable when Enable8254ClockGating is disabled. If Enable8254ClockGating is enabled, RC will do the 8254 CGE programming on S3 resume path as well.

Definition at line 80 of file IoApicConfig.h.

The documentation for this struct was generated from the following file:
  • IoApicConfig.h


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_IOAPIC_CONFIG Member List

This is the complete list of members for PCH_IOAPIC_CONFIG, including all inherited members.

Enable8254ClockGating | PCH_IOAPIC_CONFIG
Enable8254ClockGatingOnS3 | PCH_IOAPIC_CONFIG
Header | PCH_IOAPIC_CONFIG
IoApicEntry24_119 | PCH_IOAPIC_CONFIG
IoApicId | PCH_IOAPIC_CONFIG
Rsvd0 | PCH_IOAPIC_CONFIG
RsvdBits1 | PCH_IOAPIC_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_LPC_PREMEM_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
PCH_LPC_PREMEM_CONFIG Struct Reference

This structure contains the policies which are related to LPC. More...

#include <LpcConfig.h>

Collaboration diagram for PCH_LPC_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | EnhancePort8xhDecoding: 1
Enhance the port 8xh decoding. More...
UINT32 | LpcPmHAE: 1
Hardware Autonomous Enable. More...
UINT32 | RsvdBits: 30
Reserved bits.

Detailed Description

This structure contains the policies which are related to LPC.

Definition at line 46 of file LpcConfig.h.

Member Data Documentation

◆ EnhancePort8xhDecoding

UINT32 PCH_LPC_PREMEM_CONFIG::EnhancePort8xhDecoding

Enhance the port 8xh decoding.

Original LPC only decodes one byte of port 80h, with this enhancement LPC can decode word or dword of port 80h-83h.

Note
: this will occupy one LPC generic IO range register. While this is enabled, read from port 80h always return 0x00. 0: Disable, 1: Enable

Definition at line 54 of file LpcConfig.h.

◆ LpcPmHAE

UINT32 PCH_LPC_PREMEM_CONFIG::LpcPmHAE

Hardware Autonomous Enable.

When enabled, LPC will automatically engage power gating when it has reached its idle condition. 0: Disable, 1: Enable

Definition at line 60 of file LpcConfig.h.

The documentation for this struct was generated from the following file:
  • LpcConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_LPC_PREMEM_CONFIG Member List

This is the complete list of members for PCH_LPC_PREMEM_CONFIG, including all inherited members.

EnhancePort8xhDecoding | PCH_LPC_PREMEM_CONFIG
Header | PCH_LPC_PREMEM_CONFIG
LpcPmHAE | PCH_LPC_PREMEM_CONFIG
RsvdBits | PCH_LPC_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_P2SB_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
PCH_P2SB_CONFIG Struct Reference

This structure contains the policies which are related to P2SB device. More...

#include <P2sbConfig.h>

Collaboration diagram for PCH_P2SB_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | SbAccessUnlock: 1
(Test) The sideband MMIO register access to specific ports will be locked before 3rd party code execution. More...
UINT32 | Rsvdbits: 31
Reserved bits.

Detailed Description

This structure contains the policies which are related to P2SB device.

Definition at line 46 of file P2sbConfig.h.

Member Data Documentation

◆ SbAccessUnlock

UINT32 PCH_P2SB_CONFIG::SbAccessUnlock

(Test) The sideband MMIO register access to specific ports will be locked before 3rd party code execution.

Currently it disables PSFx access. This policy unlocks the sideband MMIO space for those IPs. 0: Lock sideband access ; 1: Unlock sideband access. NOTE: Do not set this policy "SbAccessUnlock" unless its necessary.

Definition at line 56 of file P2sbConfig.h.

The documentation for this struct was generated from the following file:
  • P2sbConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_P2SB_CONFIG Member List

This is the complete list of members for PCH_P2SB_CONFIG, including all inherited members.

Header | PCH_P2SB_CONFIG
Rsvdbits | PCH_P2SB_CONFIG
SbAccessUnlock | PCH_P2SB_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_PCIE_CLOCK Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
PCH_PCIE_CLOCK Struct Reference

PCH_PCIE_CLOCK describes PCIe source clock generated by PCH. More...

#include <PchPcieRpConfig.h>

Public Attributes

UINT8 | Usage
Purpose of given clock (see PCH_PCIE_CLOCK_USAGE). Default: Unused, 0xFF.
UINT8 | ClkReq
ClkSrc - ClkReq mapping. Default: 1:1 mapping with Clock numbers.
UINT8 | RsvdBytes [2]
Reserved byte.

Detailed Description

PCH_PCIE_CLOCK describes PCIe source clock generated by PCH.

Definition at line 159 of file PchPcieRpConfig.h.

The documentation for this struct was generated from the following file:
  • PchPcieRpConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_PCIE_CLOCK Member List

This is the complete list of members for PCH_PCIE_CLOCK, including all inherited members.

ClkReq | PCH_PCIE_CLOCK
RsvdBytes | PCH_PCIE_CLOCK
Usage | PCH_PCIE_CLOCK


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_PCIE_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
PCH_PCIE_CONFIG Struct Reference

The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers Revision 1: More...

#include <PchPcieRpConfig.h>

Collaboration diagram for PCH_PCIE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
PCIE_COMMON_CONFIG PcieCommonConfig
These members describe the configuration of each PCH PCIe root port.
UINT8 PchPciePort8xhDecodePortIndex
(Test) The Index of PCIe Port that is selected for Port8xh Decode (0 Based)

Detailed Description

The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers Revision 1:

  • Initial version. Revision 2:
  • Moved EnablePort8xhDecode policy to PCIE_COMMON_CONFIG Revision 3:
  • Add DmiPowerGatingDis

Definition at line 240 of file PchPcieRpConfig.h.

The documentation for this struct was generated from the following file:
  • PchPcieRpConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

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PCH_PCIE_CONFIG Member List

This is the complete list of members for PCH_PCIE_CONFIG, including all inherited members.

Header | PCH_PCIE_CONFIG
PchPciePort8xhDecodePortIndex | PCH_PCIE_CONFIG
PcieCommonConfig | PCH_PCIE_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_PCIE_ROOT_PORT_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
PCH_PCIE_ROOT_PORT_CONFIG Struct Reference

The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port. More...

#include <PchPcieRpConfig.h>

Public Attributes

UINT8 | ExtSync
an instance of Pcie Common Config More...
UINT8 | SystemErrorEnable
Indicate whether the System Error is enabled. 0: Disable; 1: Enable.
UINT8 | MvcEnabled
The Multiple VC (MVC) supports hardware to avoid HoQ block for latency sensitive TC. More...
UINT8 | VppPort
Virtual Pin Port is industry standard introduced to PCIe Hot Plug support in systems when GPIO pins expansion is needed. More...
UINT8 | VppAddress
PCIe Hot Plug VPP SMBus Address. Default is zero.
UINT8 | RsvdBytes0 [3]
Reserved bytes.

Detailed Description

The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port.

Definition at line 201 of file PchPcieRpConfig.h.

Member Data Documentation

◆ ExtSync

UINT8 PCH_PCIE_ROOT_PORT_CONFIG::ExtSync

an instance of Pcie Common Config

Indicate whether the extended synch is enabled. 0: Disable; 1: Enable.

Definition at line 203 of file PchPcieRpConfig.h.

◆ MvcEnabled

UINT8 PCH_PCIE_ROOT_PORT_CONFIG::MvcEnabled

The Multiple VC (MVC) supports hardware to avoid HoQ block for latency sensitive TC.

Currently it is only applicable to Root Ports with 2pX4 port configuration with 2 VCs,or DMI port configuration with 3 VCs. For Root Ports 2pX4 configuration, two RPs (RP0, RP2) shall support two PCIe VCs (VC0 & VC1) and the other RPs (RP1, RP3) shall be disabled. 0: Disable; 1: Enable

Definition at line 216 of file PchPcieRpConfig.h.

◆ VppPort

UINT8 PCH_PCIE_ROOT_PORT_CONFIG::VppPort

Virtual Pin Port is industry standard introduced to PCIe Hot Plug support in systems when GPIO pins expansion is needed.

It is server specific feature. 0x00: Default; 0xFF: Disabled

Definition at line 222 of file PchPcieRpConfig.h.

The documentation for this struct was generated from the following file:
  • PchPcieRpConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_PCIE_ROOT_PORT_CONFIG Member List

This is the complete list of members for PCH_PCIE_ROOT_PORT_CONFIG, including all inherited members.

ExtSync | PCH_PCIE_ROOT_PORT_CONFIG
MvcEnabled | PCH_PCIE_ROOT_PORT_CONFIG
RsvdBytes0 | PCH_PCIE_ROOT_PORT_CONFIG
SystemErrorEnable | PCH_PCIE_ROOT_PORT_CONFIG
VppAddress | PCH_PCIE_ROOT_PORT_CONFIG
VppPort | PCH_PCIE_ROOT_PORT_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_PCIE_RP_PREMEM_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
PCH_PCIE_RP_PREMEM_CONFIG Struct Reference

The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers Revision 1: More...

#include <PchPcieRpConfig.h>

Collaboration diagram for PCH_PCIE_RP_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | RpEnabledMask
Root Port enabling mask. More...
PCH_PCIE_CLOCK | PcieClock [PCH_MAX_PCIE_CLOCKS]
Configuration of PCIe source clocks.
UINT8 | Bifurcation [PCH_MAX_PCIE_CONTROLLERS]
Per Controller Bifurcation Configuration 0: Disabled; 1: 4x1; 2: 1x2_2x1; 3: 2x2; 4: 1x4; 5: 4x2; 6: 1x4_2x2; 7: 2x2_1x4; 8: 2x4; 9: 1x8 (see: PCIE_BIFURCATION_CONFIG)

Detailed Description

The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers Revision 1:

  • Initial version.

Definition at line 263 of file PchPcieRpConfig.h.

Member Data Documentation

◆ RpEnabledMask

UINT32 PCH_PCIE_RP_PREMEM_CONFIG::RpEnabledMask

Root Port enabling mask.

Bit0 presents RP1, Bit1 presents RP2, and so on. 0: Disable; 1: Enable.

Definition at line 270 of file PchPcieRpConfig.h.

The documentation for this struct was generated from the following file:
  • PchPcieRpConfig.h


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_PCIE_RP_PREMEM_CONFIG Member List

This is the complete list of members for PCH_PCIE_RP_PREMEM_CONFIG, including all inherited members.

Bifurcation | PCH_PCIE_RP_PREMEM_CONFIG
Header | PCH_PCIE_RP_PREMEM_CONFIG
PcieClock | PCH_PCIE_RP_PREMEM_CONFIG
RpEnabledMask | PCH_PCIE_RP_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_PM_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
PCH_PM_CONFIG Struct Reference

The PCH_PM_CONFIG block describes expected miscellaneous power management settings. More...

#include <PmConfig.h>

Collaboration diagram for PCH_PM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
PCH_WAKE_CONFIG WakeConfig
Specify Wake Policy.
UINT32 | PchDeepSxPol: 4
Deep Sx Policy. Refer to PCH_DEEP_SX_CONFIG for each value. Default is PchDeepSxPolDisable.
UINT32 | PchSlpS3MinAssert: 4
SLP_S3 Minimum Assertion Width Policy. Refer to PCH_SLP_S3_MIN_ASSERT for each value. Default is PchSlpS350ms.
UINT32 | PchSlpS4MinAssert: 4
SLP_S4 Minimum Assertion Width Policy. Refer to PCH_SLP_S4_MIN_ASSERT for each value. Default is PchSlpS44s.
UINT32 | PchSlpSusMinAssert: 4
SLP_SUS Minimum Assertion Width Policy. Refer to PCH_SLP_SUS_MIN_ASSERT for each value. Default is PchSlpSus4s.
UINT32 | PchSlpAMinAssert: 4
SLP_A Minimum Assertion Width Policy. Refer to PCH_SLP_A_MIN_ASSERT for each value. Default is PchSlpA2s.
UINT32 | SlpStrchSusUp: 1
This member describes whether or not the LPC ClockRun feature of PCH should be enabled. More...
UINT32 | SlpLanLowDc: 1
Enable/Disable SLP_LAN# Low on DC Power. More...
UINT32 | PwrBtnOverridePeriod: 3
PCH power button override period. More...
UINT32 | DisableEnergyReport: 1
(Test) Disable/Enable PCH to CPU enery report feature. More...
UINT32 | DisableDsxAcPresentPulldown: 1
When set to Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. More...
UINT32 | DisableNativePowerButton: 1
Power button native mode disable. More...
UINT32 | MeWakeSts: 1
Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable.
UINT32 | WolOvrWkSts: 1
Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable.
UINT32 | PsOnEnable: 1
Decide if PS_ON is to be enabled. More...
UINT32 | CppmFaEn: 1
Decide if CPPM Force Alignment is to be enabled. More...
UINT32 | CpuC10GatePinEnable: 1
Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin. More...
UINT32 | PmcDbgMsgEn: 1
Control whether to enable PMC debug messages to Trace Hub. More...
UINT32 | ModPhySusPgEnable: 1
Enable/Disable ModPHY SUS Power Domain Dynamic Gating. More...
UINT32 | Usb2PhySusPgEnable: 1
(Test) This policy option enables USB2 PHY SUS Well Power Gating functionality. More...
UINT32 | OsIdleEnable: 1
Enable Os Idle Mode. More...
UINT32 | V1p05PhyExtFetControlEn: 1
Enable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY 0: Disable; 1: Enable.
UINT32 | V1p05IsExtFetControlEn: 1
Enable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS supply 0: Disable; 1: Enable.
UINT32 | S0ixAutoDemotion: 1
Enable/Disable the Low Power Mode Host S0ix Auto-Demotion feature. More...
UINT32 | LatchEventsC10Exit: 1
Enable/Disable Latch Events C10 Exit. More...
UINT32 | PmcWdtTimerEn: 1
Enable/Disable PMC Watch Dog Timer. More...
UINT8 | PchPwrCycDur
Reset Power Cycle Duration could be customized in the unit of second. More...
UINT8 | PciePllSsc
Specifies the Pcie Pll Spread Spectrum Percentage The value of this policy is in 1/10th percent units. More...
UINT8 | C10DynamicThresholdAdjustment
Tells BIOS to enable C10 dynamic threshold adjustment mode. More...
UINT8 | Rsvd0 [1]
Reserved bytes.
PMC_LPM_S0IX_SUB_STATE_EN LpmS0ixSubStateEnable
(Test) Low Power Mode Enable/Disable config. More...
UINT8 | GlobalResetMasksOverride
Set true to enable override of Global Reset Event/Trigger masks. More...
UINT8 | Rsvd1 [3]
Reserved bytes.
UINT32 | ThermTimerDelay: 10
PMC Therm Timer Delay Register (THERM_TIMER_DELAY). More...
UINT32 | PmErDebugMode: 1
Energy Reporting Debug Mode.
UINT32 | PlatformAtxTelemetryUnit: 1
PMC_SUS_SPARE_GCR_0 bit 0, set by BIOS to indicate the telemetry type for Desktop Psys support. Set ATX Telemetry Unit in Watts or Percentage Default value is Watts; 0: Watts; 1: Percent.

Detailed Description

The PCH_PM_CONFIG block describes expected miscellaneous power management settings.

The PowerResetStatusClear field would clear the Power/Reset status bits, please set the bits if you want PCH Init driver to clear it, if you want to check the status later then clear the bits.

Revision 1:

  • Initial version. Revision 2
  • Added C10DynamicThresholdAdjustment Revision 3
  • Added PlatformAtxTelemetryUnit

Definition at line 240 of file PmConfig.h.

Member Data Documentation

◆ C10DynamicThresholdAdjustment

UINT8 PCH_PM_CONFIG::C10DynamicThresholdAdjustment

Tells BIOS to enable C10 dynamic threshold adjustment mode.

BIOS will only attemt to enable it on PCH SKUs which support it.

Definition at line 434 of file PmConfig.h.

◆ CppmFaEn

UINT32 PCH_PM_CONFIG::CppmFaEn

Decide if CPPM Force Alignment is to be enabled.

When enabled, PMC allows stalling of the backbone or blocking the DMI transmit arbiter. 0: Disable; 1: Enable

Definition at line 325 of file PmConfig.h.

◆ CpuC10GatePinEnable

UINT32 PCH_PM_CONFIG::CpuC10GatePinEnable

Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin.

This policy needs to be set if board design includes support for CPU_C10_GATE# pin. 0: Disable; 1: Enable

Definition at line 332 of file PmConfig.h.

◆ DisableDsxAcPresentPulldown

UINT32 PCH_PM_CONFIG::DisableDsxAcPresentPulldown

When set to Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.

When set to Enable, PCH will not pull down AC_PRESENT. This setting is ignored when DeepSx is not supported. Default is 0:Disable

Definition at line 287 of file PmConfig.h.

◆ DisableEnergyReport

UINT32 PCH_PM_CONFIG::DisableEnergyReport

(Test) Disable/Enable PCH to CPU enery report feature.

0: Disable; 1: Enable. Enery Report is must have feature. Wihtout Energy Report, the performance report by workloads/benchmarks will be unrealistic because PCH's energy is not being accounted in power/performance management algorithm. If for some reason PCH energy report is too high, which forces CPU to try to reduce its power by throttling, then it could try to disable Energy Report to do first debug. This might be due to energy scaling factors are not correct or the LPM settings are not kicking in.

Definition at line 280 of file PmConfig.h.

◆ DisableNativePowerButton

UINT32 PCH_PM_CONFIG::DisableNativePowerButton

Power button native mode disable.

While FALSE, the PMC's power button logic will act upon the input value from the GPIO unit, as normal. While TRUE, this will result in the PMC logic constantly seeing the power button as de-asserted. Default is FALSE.

Definition at line 294 of file PmConfig.h.

◆ GlobalResetMasksOverride

UINT8 PCH_PM_CONFIG::GlobalResetMasksOverride

Set true to enable override of Global Reset Event/Trigger masks.

Values from GlobalResetTriggerMask and GlobalResetEventMask will be used as override value. 0: Disable, 1: Enable

Definition at line 473 of file PmConfig.h.

◆ LatchEventsC10Exit

UINT32 PCH_PM_CONFIG::LatchEventsC10Exit

Enable/Disable Latch Events C10 Exit.

When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are captured on C10 exit (instead of C10 entry which is default) 0: Disable; 1: Enable.

Definition at line 388 of file PmConfig.h.

◆ LpmS0ixSubStateEnable

PMC_LPM_S0IX_SUB_STATE_EN PCH_PM_CONFIG::LpmS0ixSubStateEnable

(Test) Low Power Mode Enable/Disable config.

Configure if respective S0i2/3 sub-states are to be supported by the platform. By default all sub-states are enabled but for test purpose respective states can be disabled. Default is 0xFF

Definition at line 444 of file PmConfig.h.

◆ ModPhySusPgEnable

UINT32 PCH_PM_CONFIG::ModPhySusPgEnable

Enable/Disable ModPHY SUS Power Domain Dynamic Gating.

EXT_PWR_GATE# signal (if supported on platform) can be used to control external FET for power gating ModPHY

Note
: This setting is not supported and ignored on PCH-H 0: Disable; 1: Enable.

Definition at line 348 of file PmConfig.h.

◆ OsIdleEnable

UINT32 PCH_PM_CONFIG::OsIdleEnable

Enable Os Idle Mode.

0: Disable; 1: Enable.

Definition at line 361 of file PmConfig.h.

◆ PchPwrCycDur

UINT8 PCH_PM_CONFIG::PchPwrCycDur

Reset Power Cycle Duration could be customized in the unit of second.

Please refer to EDS for all support settings. PCH HW default is 4 seconds, and range is 1~4 seconds, where 0 is default, 1 is 1 second, 2 is 2 seconds, ... 4 is 4 seconds. And make sure the setting correct, which never less than the following register.

  • GEN_PMCON_B.SLP_S3_MIN_ASST_WDTH
  • GEN_PMCON_B.SLP_S4_MIN_ASST_WDTH
  • PWRM_CFG.SLP_A_MIN_ASST_WDTH
  • PWRM_CFG.SLP_LAN_MIN_ASST_WDTH

Definition at line 421 of file PmConfig.h.

◆ PciePllSsc

UINT8 PCH_PM_CONFIG::PciePllSsc

Specifies the Pcie Pll Spread Spectrum Percentage The value of this policy is in 1/10th percent units.

Valid spread range is 0-20. A value of 0xFF is reserved for AUTO. A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0% The default is 0xFF: AUTO - No BIOS override.

Definition at line 429 of file PmConfig.h.

◆ PmcDbgMsgEn

UINT32 PCH_PM_CONFIG::PmcDbgMsgEn

Control whether to enable PMC debug messages to Trace Hub.

When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW will never send debug meesages to trace hub.

Note
: When enabled, system may not enter S0ix 0: Disable; 1: Enable.

Definition at line 340 of file PmConfig.h.

◆ PmcWdtTimerEn

UINT32 PCH_PM_CONFIG::PmcWdtTimerEn

Enable/Disable PMC Watch Dog Timer.

When this bit is set to 1, timers are enabled that can trigger a system reset. 0: Disable; 1: Enable.

Definition at line 394 of file PmConfig.h.

◆ PsOnEnable

UINT32 PCH_PM_CONFIG::PsOnEnable

Decide if PS_ON is to be enabled.

This is available on desktop only. PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled.} 0: Disable; 1: Enable.

Definition at line 319 of file PmConfig.h.

◆ PwrBtnOverridePeriod

UINT32 PCH_PM_CONFIG::PwrBtnOverridePeriod

PCH power button override period.

000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s Default is 0: 4s

Definition at line 268 of file PmConfig.h.

◆ S0ixAutoDemotion

UINT32 PCH_PM_CONFIG::S0ixAutoDemotion

Enable/Disable the Low Power Mode Host S0ix Auto-Demotion feature.

This feature enables the PMC to autonomously manage the deepest allowed S0ix substate to combat thrashing between power management states. 0: Disable; 1: Enable.

Definition at line 381 of file PmConfig.h.

◆ SlpLanLowDc

UINT32 PCH_PM_CONFIG::SlpLanLowDc

Enable/Disable SLP_LAN# Low on DC Power.

0: Disable; 1: Enable. Configure On DC PHY Power Diable according to policy SlpLanLowDc. When this is enabled, SLP_LAN# will be driven low when ACPRESENT is low. This indicates that LAN PHY should be powered off on battery mode. This will override the DC_PP_DIS setting by WolEnableOverride.

Definition at line 262 of file PmConfig.h.

◆ SlpStrchSusUp

UINT32 PCH_PM_CONFIG::SlpStrchSusUp

This member describes whether or not the LPC ClockRun feature of PCH should be enabled.

0: Disable; 1: Enable 0: Disable; 1: Enable SLP_X Stretching After SUS Well Power Up

Definition at line 254 of file PmConfig.h.

◆ ThermTimerDelay

UINT32 PCH_PM_CONFIG::ThermTimerDelay

PMC Therm Timer Delay Register (THERM_TIMER_DELAY).

Unit in us(microseconds). Adding delay time between CPU thermal trip propagating through PCH and PCH generating a Global Reset Default is 500

Definition at line 488 of file PmConfig.h.

◆ Usb2PhySusPgEnable

UINT32 PCH_PM_CONFIG::Usb2PhySusPgEnable

(Test) This policy option enables USB2 PHY SUS Well Power Gating functionality.

Note
: This setting is not supported and ignored on PCH-H 0: disable USB2 PHY SUS Well Power Gating 1: enable USB2 PHY SUS Well Power Gating

Definition at line 356 of file PmConfig.h.

The documentation for this struct was generated from the following file:
  • PmConfig.h


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_PM_CONFIG Member List

This is the complete list of members for PCH_PM_CONFIG, including all inherited members.

C10DynamicThresholdAdjustment | PCH_PM_CONFIG
CppmFaEn | PCH_PM_CONFIG
CpuC10GatePinEnable | PCH_PM_CONFIG
DisableDsxAcPresentPulldown | PCH_PM_CONFIG
DisableEnergyReport | PCH_PM_CONFIG
DisableNativePowerButton | PCH_PM_CONFIG
GlobalResetMasksOverride | PCH_PM_CONFIG
Header | PCH_PM_CONFIG
LatchEventsC10Exit | PCH_PM_CONFIG
LpmS0ixSubStateEnable | PCH_PM_CONFIG
MeWakeSts | PCH_PM_CONFIG
ModPhySusPgEnable | PCH_PM_CONFIG
OsIdleEnable | PCH_PM_CONFIG
PchDeepSxPol | PCH_PM_CONFIG
PchPwrCycDur | PCH_PM_CONFIG
PchSlpAMinAssert | PCH_PM_CONFIG
PchSlpS3MinAssert | PCH_PM_CONFIG
PchSlpS4MinAssert | PCH_PM_CONFIG
PchSlpSusMinAssert | PCH_PM_CONFIG
PciePllSsc | PCH_PM_CONFIG
PlatformAtxTelemetryUnit | PCH_PM_CONFIG
PmcDbgMsgEn | PCH_PM_CONFIG
PmcWdtTimerEn | PCH_PM_CONFIG
PmErDebugMode | PCH_PM_CONFIG
PsOnEnable | PCH_PM_CONFIG
PwrBtnOverridePeriod | PCH_PM_CONFIG
Rsvd0 | PCH_PM_CONFIG
Rsvd1 | PCH_PM_CONFIG
S0ixAutoDemotion | PCH_PM_CONFIG
SlpLanLowDc | PCH_PM_CONFIG
SlpStrchSusUp | PCH_PM_CONFIG
ThermTimerDelay | PCH_PM_CONFIG
Usb2PhySusPgEnable | PCH_PM_CONFIG
V1p05IsExtFetControlEn | PCH_PM_CONFIG
V1p05PhyExtFetControlEn | PCH_PM_CONFIG
WakeConfig | PCH_PM_CONFIG
WolOvrWkSts | PCH_PM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_SATA_PORT_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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PCH_SATA_PORT_CONFIG Struct Reference

This structure configures the features, property, and capability for each SATA port. More...

#include <SataConfig.h>

Public Attributes

UINT32 | Enable: 1
Enable SATA port. More...
UINT32 | HotPlug: 1
0: Disable; 1: Enable
UINT32 | InterlockSw: 1
0: Disable; 1: Enable
UINT32 | External: 1
0: Disable; 1: Enable
UINT32 | SpinUp: 1
0: Disable; 1: Enable the COMRESET initialization Sequence to the device
UINT32 | SolidStateDrive: 1
0: HDD; 1: SSD
UINT32 | DevSlp: 1
0: Disable; 1: Enable DEVSLP on the port
UINT32 | EnableDitoConfig: 1
0: Disable; 1: Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)
UINT32 | DmVal: 4
DITO multiplier. Default is 15.
UINT32 | DitoVal: 10
DEVSLP Idle Timeout (DITO), Default is 625.
UINT32 | ZpOdd: 1
Support zero power ODD 0: Disable, 1: Enable. More...
UINT32 | DevSlpResetConfig: 4
0: Hardware default; 0x01: GpioResumeReset; 0x03: GpioHostDeepReset; 0x05: GpioPlatformReset; 0x07: GpioDswReset
UINT32 | RxPolarity: 1
0: Disable; 1: Enable; Rx Polarity
UINT32 | RsvdBits0: 4
Reserved fields for future expansion w/o protocol change.

Detailed Description

This structure configures the features, property, and capability for each SATA port.

Definition at line 75 of file SataConfig.h.

Member Data Documentation

◆ Enable

UINT32 PCH_SATA_PORT_CONFIG::Enable

Enable SATA port.

It is highly recommended to disable unused ports for power savings 0: Disable; 1: Enable

Definition at line 80 of file SataConfig.h.

◆ ZpOdd

UINT32 PCH_SATA_PORT_CONFIG::ZpOdd

Support zero power ODD 0: Disable, 1: Enable.

This is also used to disable ModPHY dynamic power gate.

Definition at line 94 of file SataConfig.h.

The documentation for this struct was generated from the following file:
  • SataConfig.h


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_SATA_PORT_CONFIG Member List

This is the complete list of members for PCH_SATA_PORT_CONFIG, including all inherited members.

DevSlp | PCH_SATA_PORT_CONFIG
DevSlpResetConfig | PCH_SATA_PORT_CONFIG
DitoVal | PCH_SATA_PORT_CONFIG
DmVal | PCH_SATA_PORT_CONFIG
Enable | PCH_SATA_PORT_CONFIG
EnableDitoConfig | PCH_SATA_PORT_CONFIG
External | PCH_SATA_PORT_CONFIG
HotPlug | PCH_SATA_PORT_CONFIG
InterlockSw | PCH_SATA_PORT_CONFIG
RsvdBits0 | PCH_SATA_PORT_CONFIG
RxPolarity | PCH_SATA_PORT_CONFIG
SolidStateDrive | PCH_SATA_PORT_CONFIG
SpinUp | PCH_SATA_PORT_CONFIG
ZpOdd | PCH_SATA_PORT_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_SMBUS_PREMEM_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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PCH_SMBUS_PREMEM_CONFIG Struct Reference

The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform. More...

#include <SmbusConfig.h>

Collaboration diagram for PCH_SMBUS_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Revision 1: Init version. More...
UINT32 | Enable: 1
This member describes whether or not the SMBus controller of PCH should be enabled. More...
UINT32 | ArpEnable: 1
Enable SMBus ARP support, 0: Disable; 1: Enable.
UINT32 | DynamicPowerGating: 1
(Test) Disable or Enable Smbus dynamic power gating.
UINT32 | SpdWriteDisable: 1
(Test) SPD Write Disable, 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. More...
UINT32 | SmbAlertEnable: 1
Enable SMBus Alert pin (SMBALERT#). 0: Disabled, 1: Enabled.
UINT32 | RsvdBits0: 27
Reserved bits.
UINT16 | SmbusIoBase
SMBUS Base Address (IO space). Default is 0xEFA0.
UINT8 | Rsvd0
Reserved bytes.
UINT8 | NumRsvdSmbusAddresses
The number of elements in the RsvdSmbusAddressTable.
UINT8 | RsvdSmbusAddressTable [PCH_MAX_SMBUS_RESERVED_ADDRESS]
Array of addresses reserved for non-ARP-capable SMBus devices.

Detailed Description

The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform.

Definition at line 48 of file SmbusConfig.h.

Member Data Documentation

◆ Enable

UINT32 PCH_SMBUS_PREMEM_CONFIG::Enable

This member describes whether or not the SMBus controller of PCH should be enabled.

0: Disable; 1: Enable.

Definition at line 57 of file SmbusConfig.h.

◆ Header

CONFIG_BLOCK_HEADER PCH_SMBUS_PREMEM_CONFIG::Header

Revision 1: Init version.

Config Block Header

Definition at line 52 of file SmbusConfig.h.

◆ SpdWriteDisable

UINT32 PCH_SMBUS_PREMEM_CONFIG::SpdWriteDisable

(Test) SPD Write Disable, 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit.

For security recommendations, SPD write disable bit must be set.

Definition at line 64 of file SmbusConfig.h.

The documentation for this struct was generated from the following file:
  • SmbusConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_SMBUS_PREMEM_CONFIG Member List

This is the complete list of members for PCH_SMBUS_PREMEM_CONFIG, including all inherited members.

ArpEnable | PCH_SMBUS_PREMEM_CONFIG
DynamicPowerGating | PCH_SMBUS_PREMEM_CONFIG
Enable | PCH_SMBUS_PREMEM_CONFIG
Header | PCH_SMBUS_PREMEM_CONFIG
NumRsvdSmbusAddresses | PCH_SMBUS_PREMEM_CONFIG
Rsvd0 | PCH_SMBUS_PREMEM_CONFIG
RsvdBits0 | PCH_SMBUS_PREMEM_CONFIG
RsvdSmbusAddressTable | PCH_SMBUS_PREMEM_CONFIG
SmbAlertEnable | PCH_SMBUS_PREMEM_CONFIG
SmbusIoBase | PCH_SMBUS_PREMEM_CONFIG
SpdWriteDisable | PCH_SMBUS_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_TRACE_HUB_PREMEM_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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PCH_TRACE_HUB_PREMEM_CONFIG Struct Reference

PCH Trace Hub PreMem Configuration Contains Trace Hub settings for PCH side tracing Revision 1: - Initial version. More...

#include <TraceHubConfig.h>

Collaboration diagram for PCH_TRACE_HUB_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
TRACE_HUB_CONFIG TraceHub
Trace Hub Config.

Detailed Description

PCH Trace Hub PreMem Configuration Contains Trace Hub settings for PCH side tracing Revision 1: - Initial version.

Definition at line 120 of file TraceHubConfig.h.

The documentation for this struct was generated from the following file:
  • TraceHubConfig.h


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_TRACE_HUB_PREMEM_CONFIG Member List

This is the complete list of members for PCH_TRACE_HUB_PREMEM_CONFIG, including all inherited members.

Header | PCH_TRACE_HUB_PREMEM_CONFIG
TraceHub | PCH_TRACE_HUB_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_WAKE_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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PCH_WAKE_CONFIG Struct Reference

This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL, LAN, PCIE wake events. More...

#include <PmConfig.h>

Public Attributes

UINT32 | PmeB0S5Dis: 1
Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. More...
UINT32 | WolEnableOverride: 1
Corresponds to the "WOL Enable Override" bit in the General PM Configuration B (GEN_PMCON_B) register. 0: Disable; 1: Enable.
UINT32 | PcieWakeFromDeepSx: 1
Determine if enable PCIe to wake from deep Sx. 0: Disable; 1: Enable.
UINT32 | WoWlanEnable: 1
Determine if WLAN wake from Sx, corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register. 0: Disable; 1: Enable.
UINT32 | WoWlanDeepSxEnable: 1
Determine if WLAN wake from DeepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3 register. 0: Disable; 1: Enable.
UINT32 | LanWakeFromDeepSx: 1
Determine if enable LAN to wake from deep Sx. 0: Disable; 1: Enable.

Detailed Description

This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL, LAN, PCIE wake events.

Definition at line 62 of file PmConfig.h.

Member Data Documentation

◆ PmeB0S5Dis

UINT32 PCH_WAKE_CONFIG::PmeB0S5Dis

Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register.

When set to 1, this bit blocks wake events from PME_B0_STS in S5, regardless of the state of PME_B0_EN. When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. 0: Disable; 1: Enable.

Definition at line 68 of file PmConfig.h.

The documentation for this struct was generated from the following file:
  • PmConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_WAKE_CONFIG Member List

This is the complete list of members for PCH_WAKE_CONFIG, including all inherited members.

LanWakeFromDeepSx | PCH_WAKE_CONFIG
PcieWakeFromDeepSx | PCH_WAKE_CONFIG
PmeB0S5Dis | PCH_WAKE_CONFIG
WolEnableOverride | PCH_WAKE_CONFIG
WoWlanDeepSxEnable | PCH_WAKE_CONFIG
WoWlanEnable | PCH_WAKE_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_WDT_PREMEM_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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PCH_WDT_PREMEM_CONFIG Struct Reference

This policy clears status bits and disable watchdog, then lock the WDT registers. More...

#include <WatchDogConfig.h>

Collaboration diagram for PCH_WDT_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 DisableAndLock: 1
(Test) Set 1 to clear WDT status, then disable and lock WDT registers. 0: Disable; 1: Enable.

Detailed Description

This policy clears status bits and disable watchdog, then lock the WDT registers.

while WDT is designed to be disabled and locked by Policy, bios should not enable WDT by WDT PPI. In such case, bios shows the warning message but not disable and lock WDT register to make sure WDT event trigger correctly.

Definition at line 51 of file WatchDogConfig.h.

The documentation for this struct was generated from the following file:
  • WatchDogConfig.h


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCH_WDT_PREMEM_CONFIG Member List

This is the complete list of members for PCH_WDT_PREMEM_CONFIG, including all inherited members.

DisableAndLock | PCH_WDT_PREMEM_CONFIG
Header | PCH_WDT_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCIE_COMMON_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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PCIE_COMMON_CONFIG Struct Reference

PCIe Common Config. More...

#include <PcieConfig.h>

Public Attributes

UINT32 | RpFunctionSwap: 1
RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled. More...
UINT32 | ComplianceTestMode: 1
Compliance Test Mode shall be enabled when using Compliance Load Board. More...
UINT32 | RsvdBits0: 29
Reserved bits.
UINT8 | EnablePort8xhDecode
(Test) This member describes whether PCIE root port Port 8xh Decode is enabled. More...

Detailed Description

PCIe Common Config.

Note
This structure will be expanded to hold all common PCIe policies between SA and PCH

Definition at line 302 of file PcieConfig.h.

Member Data Documentation

◆ ComplianceTestMode

UINT32 PCIE_COMMON_CONFIG::ComplianceTestMode

Compliance Test Mode shall be enabled when using Compliance Load Board.

0: Disable, 1: Enable

Definition at line 323 of file PcieConfig.h.

◆ EnablePort8xhDecode

UINT8 PCIE_COMMON_CONFIG::EnablePort8xhDecode

(Test) This member describes whether PCIE root port Port 8xh Decode is enabled.

0: Disable; 1: Enable.

Definition at line 329 of file PcieConfig.h.

◆ RpFunctionSwap

UINT32 PCIE_COMMON_CONFIG::RpFunctionSwap

RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled.

A PCIE device can have higher functions only when Function0 exists. To satisfy this requirement, BIOS will always enable Function0 of a device that contains more than 0 enabled root ports.

  • Enabled: One of enabled root ports get assigned to Function0. This offers no guarantee that any particular root port will be available at a specific DevNr:FuncNr location
  • Disabled: Root port that corresponds to Function0 will be kept visible even though it might be not used. That way rootport - to - DevNr:FuncNr assignment is constant. This option will impact ports 1, 9, 17. NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage or disabled through policy In other words, it only affects ports that would become hidden because they have no device connected. NOTE: Disabling function swap may have adverse impact on power management. This option should ONLY be used when each one of root ports 1, 9, 17:
    • is configured as PCIe and has correctly configured ClkReq signal, or
    • does not own any mPhy lanes (they are configured as SATA or USB)

Definition at line 318 of file PcieConfig.h.

The documentation for this struct was generated from the following file:
  • PcieConfig.h


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PCIE_COMMON_CONFIG Member List

This is the complete list of members for PCIE_COMMON_CONFIG, including all inherited members.

ComplianceTestMode | PCIE_COMMON_CONFIG
EnablePort8xhDecode | PCIE_COMMON_CONFIG
RpFunctionSwap | PCIE_COMMON_CONFIG
RsvdBits0 | PCIE_COMMON_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCIE_DEVICE_OVERRIDE Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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PCIE_DEVICE_OVERRIDE Struct Reference

PCIe device table entry entry. More...

#include <PcieConfig.h>

Public Attributes

UINT16 | VendorId
The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID.
UINT16 | DeviceId
The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID.
UINT8 | RevId
The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings.
UINT8 | BaseClassCode
The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class.
UINT8 | SubClassCode
The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class.
UINT8 | EndPointAspm
Override device ASPM (see: PCH_PCIE_ASPM_CONTROL) Bit 1 must be set in OverrideConfig for this field to take effect.
UINT16 | OverrideConfig
The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG).
UINT16 | L1SubstatesCapOffset
The L1Substates Capability Offset Override. More...
UINT8 | L1SubstatesCapMask
L1 Substate Capability Mask. More...
UINT8 | L1sCommonModeRestoreTime
L1 Substate Port Common Mode Restore Time Override. More...
UINT8 | L1sTpowerOnScale
L1 Substate Port Tpower_on Scale Override. More...
UINT8 | L1sTpowerOnValue
L1 Substate Port Tpower_on Value Override. More...
UINT16 | SnoopLatency
SnoopLatency bit definition Note: All Reserved bits must be set to 0. More...
UINT16 | NonSnoopLatency
NonSnoopLatency bit definition Note: All Reserved bits must be set to 0. More...
UINT8 | ForceLtrOverride
Forces LTR override to be permanent The default way LTR override works is: rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message This settings allows force override of LTR mechanism. More...

Detailed Description

PCIe device table entry entry.

The PCIe device table is being used to override PCIe device ASPM settings. To take effect table consisting of such entries must be instelled as PPI on gPchPcieDeviceTablePpiGuid. Last entry VendorId must be 0.

Definition at line 342 of file PcieConfig.h.

Member Data Documentation

◆ ForceLtrOverride

UINT8 PCIE_DEVICE_OVERRIDE::ForceLtrOverride

Forces LTR override to be permanent The default way LTR override works is: rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message This settings allows force override of LTR mechanism.

If it's enabled, then: rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored

Definition at line 436 of file PcieConfig.h.

◆ L1sCommonModeRestoreTime

UINT8 PCIE_DEVICE_OVERRIDE::L1sCommonModeRestoreTime

L1 Substate Port Common Mode Restore Time Override.

(applicable if bit 2 is set in OverrideConfig) L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue. If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored, and only L1SubstatesCapOffset is override.

Definition at line 368 of file PcieConfig.h.

◆ L1sTpowerOnScale

UINT8 PCIE_DEVICE_OVERRIDE::L1sTpowerOnScale

L1 Substate Port Tpower_on Scale Override.

(applicable if bit 2 is set in OverrideConfig) L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue. If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored, and only L1SubstatesCapOffset is override.

Definition at line 375 of file PcieConfig.h.

◆ L1sTpowerOnValue

UINT8 PCIE_DEVICE_OVERRIDE::L1sTpowerOnValue

L1 Substate Port Tpower_on Value Override.

(applicable if bit 2 is set in OverrideConfig) L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue. If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored, and only L1SubstatesCapOffset is override.

Definition at line 382 of file PcieConfig.h.

◆ L1SubstatesCapMask

UINT8 PCIE_DEVICE_OVERRIDE::L1SubstatesCapMask

L1 Substate Capability Mask.

(applicable if bit 2 is set in OverrideConfig) Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s values are override. Only bit [3:0] are applicable. Other bits are ignored.

Definition at line 361 of file PcieConfig.h.

◆ L1SubstatesCapOffset

UINT16 PCIE_DEVICE_OVERRIDE::L1SubstatesCapOffset

The L1Substates Capability Offset Override.

(applicable if bit 2 is set in OverrideConfig) This field can be zero if only the L1 Substate value is going to be override.

Definition at line 355 of file PcieConfig.h.

◆ NonSnoopLatency

UINT16 PCIE_DEVICE_OVERRIDE::NonSnoopLatency

NonSnoopLatency bit definition Note: All Reserved bits must be set to 0.

BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid When clear values in bits 9:0 will be ignored BITS[14:13] - Reserved BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits 000b - 1 ns 001b - 32 ns 010b - 1024 ns 011b - 32,768 ns 100b - 1,048,576 ns 101b - 33,554,432 ns 110b - Reserved 111b - Reserved BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with the scale in bits 12:10

This field takes effect only if bit 3 is set in OverrideConfig.

Definition at line 427 of file PcieConfig.h.

◆ SnoopLatency

UINT16 PCIE_DEVICE_OVERRIDE::SnoopLatency

SnoopLatency bit definition Note: All Reserved bits must be set to 0.

BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid When clear values in bits 9:0 will be ignored BITS[14:13] - Reserved BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits 000b - 1 ns 001b - 32 ns 010b - 1024 ns 011b - 32,768 ns 100b - 1,048,576 ns 101b - 33,554,432 ns 110b - Reserved 111b - Reserved BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with the scale in bits 12:10

This field takes effect only if bit 3 is set in OverrideConfig.

Definition at line 405 of file PcieConfig.h.

The documentation for this struct was generated from the following file:
  • PcieConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCIE_DEVICE_OVERRIDE Member List

This is the complete list of members for PCIE_DEVICE_OVERRIDE, including all inherited members.

BaseClassCode | PCIE_DEVICE_OVERRIDE
DeviceId | PCIE_DEVICE_OVERRIDE
EndPointAspm | PCIE_DEVICE_OVERRIDE
ForceLtrOverride | PCIE_DEVICE_OVERRIDE
L1sCommonModeRestoreTime | PCIE_DEVICE_OVERRIDE
L1sTpowerOnScale | PCIE_DEVICE_OVERRIDE
L1sTpowerOnValue | PCIE_DEVICE_OVERRIDE
L1SubstatesCapMask | PCIE_DEVICE_OVERRIDE
L1SubstatesCapOffset | PCIE_DEVICE_OVERRIDE
NonSnoopLatency | PCIE_DEVICE_OVERRIDE
OverrideConfig | PCIE_DEVICE_OVERRIDE
RevId | PCIE_DEVICE_OVERRIDE
SnoopLatency | PCIE_DEVICE_OVERRIDE
SubClassCode | PCIE_DEVICE_OVERRIDE
VendorId | PCIE_DEVICE_OVERRIDE


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCIE_EQ_PARAM Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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PCIE_EQ_PARAM Struct Reference

Represent lane specific PCIe Gen3 equalization parameters. More...

#include <PcieConfig.h>

Public Attributes

UINT8 | Cm
Coefficient C-1.
UINT8 | Cp
Coefficient C+1.
UINT8 | Rsvd0 [2]
Reserved bytes.

Detailed Description

Represent lane specific PCIe Gen3 equalization parameters.

Definition at line 74 of file PcieConfig.h.

The documentation for this struct was generated from the following file:
  • PcieConfig.h


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCIE_EQ_PARAM Member List

This is the complete list of members for PCIE_EQ_PARAM, including all inherited members.

Cm | PCIE_EQ_PARAM
Cp | PCIE_EQ_PARAM
Rsvd0 | PCIE_EQ_PARAM


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCIE_IMR_CONFIG Struct Reference

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PCIE_IMR_CONFIG Struct Reference

PCIe IMR Config. More...

#include <PciePreMemConfig.h>

Public Attributes

UINT8 | ImrEnabled
PCIe IMR. 0: Disable; 1: Enable.
UINT8 | ImrRpLocation
0: PCH_PCIe; 1: CPU_PCIe. If PCIeImrEnabled is TRUE then this will use to select the Root port location from PCH PCIe or CPU PCIe.Refer PCIE_IMR_ROOT_PORT_LOCATION above
UINT16 | ImrSize
PCIe IMR size in megabytes.
UINT8 | ImrRpSelection
Index of root port that is selected for PCIe IMR (0 based)

Detailed Description

PCIe IMR Config.

Definition at line 53 of file PciePreMemConfig.h.

The documentation for this struct was generated from the following file:
  • PciePreMemConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCIE_IMR_CONFIG Member List

This is the complete list of members for PCIE_IMR_CONFIG, including all inherited members.

ImrEnabled | PCIE_IMR_CONFIG
ImrRpLocation | PCIE_IMR_CONFIG
ImrRpSelection | PCIE_IMR_CONFIG
ImrSize | PCIE_IMR_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCIE_LINK_EQ_PLATFORM_SETTINGS Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
PCIE_LINK_EQ_PLATFORM_SETTINGS Struct Reference

PCIe Link EQ Platform Settings. More...

#include <PcieConfig.h>

Public Attributes

UINT8 | PcieLinkEqMethod
Tells BIOS which link EQ method should be used for this port. Please refer to PCIE_LINK_EQ_METHOD for details of supported methods. Default: PcieLinkHardwareEq.
UINT8 | PcieLinkEqMode
Tells BIOS which mode should be used for PCIe link EQ. Please refer to PCIE_LINK_EQ_MODE for details of supported modes. Default: depends on SoC.
UINT8 | LocalTxOverrideEn
Specifies if BIOS should perform local transmitter override during phase 2 of EQ process. More...
UINT8 | DefaultPresetEnable [PCIE_LINK_EQ_PRESETS_MAX]
Specifies if default settings should remain in use.
UINT8 | HapcsSearchEnable
Specifies setting for Hardware Autonomous Preset/Coefficient Search mechanism.
UINT32 | Ph2LocalTxOverridePreset
Specifies the preset that should be used during local transmitter override during phase 2 of EQ process. More...
UINT32 | PCETTimer
PCET Timer value for single PCIe speed.
UINT8 | RemotePresetCoeffoverride
Remote Transmitter Preset Coefficient Override for single PCIe speed.
UINT8 | EqPh3Bypass
PCIe Equalization Phase 3 Enable Control. More...
UINT8 | EqPh23Bypass
PCIe Equalization Phase 2-3 Enable Control. More...
UINT8 | TsLockTimer
8.0GT/s Training Sequence Wait Latency For Presets / Coefficients Evaluation - Gen3 TS Lock Timer
UINT8 | EqPhBypass
PCIe Equalization Phase Enable Control. More...
UINT8 | Ph3NoOfPresetOrCoeff
Tells BIOS how many presets/coefficients should be used during link EQ. More...
PCIE_LINK_EQ_COEFFICIENTS | Ph3CoefficientsList [PCIE_LINK_EQ_COEFFICIENTS_MAX]
List of the PCIe coefficients to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqCoefficientMode.
UINT32 | Ph3PresetList [PCIE_LINK_EQ_PRESETS_MAX]
List of the PCIe preset values to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqPresetMode.
UINT32 | EndPointPresetList [PCIE_LINK_EQ_PRESETS_MAX]
List of the PCIe preset values to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqPresetMode.
UINT32 | HintList [PCIE_LINK_EQ_PRESETS_MAX]
List of the Hint values to be used during equalization process for preset calculation.
UINT32 | Ph1DpTxPreset
Specifies the value of the downstream port transmitter preset to be used during phase 1 of the equalization process. Will be applied to all lanes.
UINT32 | Ph1UpTxPreset
Specifies the value of the upstream port transmitter preset to be used during phase 1 of the equalization process. Will be applied to all lanes.

Detailed Description

PCIe Link EQ Platform Settings.

Definition at line 131 of file PcieConfig.h.

Member Data Documentation

◆ EqPh23Bypass

UINT8 PCIE_LINK_EQ_PLATFORM_SETTINGS::EqPh23Bypass

PCIe Equalization Phase 2-3 Enable Control.

  • Disabled (0x0) : Disable Phase 2 - Phase 3 (Default)
  • Enabled (0x1) : Enable Phase 2 - Phase 3

Definition at line 162 of file PcieConfig.h.

◆ EqPh3Bypass

UINT8 PCIE_LINK_EQ_PLATFORM_SETTINGS::EqPh3Bypass

PCIe Equalization Phase 3 Enable Control.

  • Disabled (0x0) : Disable phase 3 (Default)
    • Enabled (0x1) : Enable phase 3

Definition at line 156 of file PcieConfig.h.

◆ EqPhBypass

UINT8 PCIE_LINK_EQ_PLATFORM_SETTINGS::EqPhBypass

PCIe Equalization Phase Enable Control.

  • Disabled (0x0) : Disable Phase (Default)
  • Enabled (0x1) : Enable Phase

Definition at line 169 of file PcieConfig.h.

◆ LocalTxOverrideEn

UINT8 PCIE_LINK_EQ_PLATFORM_SETTINGS::LocalTxOverrideEn

Specifies if BIOS should perform local transmitter override during phase 2 of EQ process.

If enabled value in Ph2LocalTxOverridePreset must be valid. 0: Disabled; 1: Enabled

Definition at line 139 of file PcieConfig.h.

◆ Ph2LocalTxOverridePreset

UINT32 PCIE_LINK_EQ_PLATFORM_SETTINGS::Ph2LocalTxOverridePreset

Specifies the preset that should be used during local transmitter override during phase 2 of EQ process.

Used only if LocalTxOverrideEn is TRUE. Will be applied to all PCIe lanes of the root port. Valid up to the PCIE_LINK_EQ_PRESET_MAX value. Default: 0< >

Definition at line 148 of file PcieConfig.h.

◆ Ph3NoOfPresetOrCoeff

UINT8 PCIE_LINK_EQ_PLATFORM_SETTINGS::Ph3NoOfPresetOrCoeff

Tells BIOS how many presets/coefficients should be used during link EQ.

Entries in the Ph3CoefficientsList or Ph3PresetList(depending on chosen mode) need to be valid up to the number specified in this field.

Definition at line 175 of file PcieConfig.h.

The documentation for this struct was generated from the following file:
  • PcieConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCIE_LINK_EQ_PLATFORM_SETTINGS Member List

This is the complete list of members for PCIE_LINK_EQ_PLATFORM_SETTINGS, including all inherited members.

DefaultPresetEnable | PCIE_LINK_EQ_PLATFORM_SETTINGS
EndPointPresetList | PCIE_LINK_EQ_PLATFORM_SETTINGS
EqPh23Bypass | PCIE_LINK_EQ_PLATFORM_SETTINGS
EqPh3Bypass | PCIE_LINK_EQ_PLATFORM_SETTINGS
EqPhBypass | PCIE_LINK_EQ_PLATFORM_SETTINGS
HapcsSearchEnable | PCIE_LINK_EQ_PLATFORM_SETTINGS
HintList | PCIE_LINK_EQ_PLATFORM_SETTINGS
LocalTxOverrideEn | PCIE_LINK_EQ_PLATFORM_SETTINGS
PCETTimer | PCIE_LINK_EQ_PLATFORM_SETTINGS
PcieLinkEqMethod | PCIE_LINK_EQ_PLATFORM_SETTINGS
PcieLinkEqMode | PCIE_LINK_EQ_PLATFORM_SETTINGS
Ph1DpTxPreset | PCIE_LINK_EQ_PLATFORM_SETTINGS
Ph1UpTxPreset | PCIE_LINK_EQ_PLATFORM_SETTINGS
Ph2LocalTxOverridePreset | PCIE_LINK_EQ_PLATFORM_SETTINGS
Ph3CoefficientsList | PCIE_LINK_EQ_PLATFORM_SETTINGS
Ph3NoOfPresetOrCoeff | PCIE_LINK_EQ_PLATFORM_SETTINGS
Ph3PresetList | PCIE_LINK_EQ_PLATFORM_SETTINGS
RemotePresetCoeffoverride | PCIE_LINK_EQ_PLATFORM_SETTINGS
TsLockTimer | PCIE_LINK_EQ_PLATFORM_SETTINGS


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCIE_PREMEM_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
PCIE_PREMEM_CONFIG Struct Reference

PCIe Pre-Memory Configuration Revision 1: - Initial version. More...

#include <PciePreMemConfig.h>

Collaboration diagram for PCIE_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0 - 27 Config Block Header.
PCIE_IMR_CONFIG PcieImr
IMR Configuration.

Detailed Description

PCIe Pre-Memory Configuration Revision 1: - Initial version.

Definition at line 65 of file PciePreMemConfig.h.

The documentation for this struct was generated from the following file:
  • PciePreMemConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCIE_PREMEM_CONFIG Member List

This is the complete list of members for PCIE_PREMEM_CONFIG, including all inherited members.

Header | PCIE_PREMEM_CONFIG
PcieImr | PCIE_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PCIE_RP_DXE_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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PCIE_RP_DXE_CONFIG Struct Reference

The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers in DXE phase. More...

#include <PchPcieRpConfig.h>

Collaboration diagram for PCIE_RP_DXE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
PCIE_DEVICE_OVERRIDE * PcieDeviceOverrideTablePtr
PCIe device override table The PCIe device table is being used to override PCIe device ASPM settings. More...

Detailed Description

The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers in DXE phase.

Revision 1:

  • Init version

Definition at line 290 of file PchPcieRpConfig.h.

Member Data Documentation

◆ PcieDeviceOverrideTablePtr

PCIE_DEVICE_OVERRIDE* PCIE_RP_DXE_CONFIG::PcieDeviceOverrideTablePtr

PCIe device override table The PCIe device table is being used to override PCIe device ASPM settings.

And it's only used in DXE phase. Please refer to PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId must be 0.

Definition at line 300 of file PchPcieRpConfig.h.

The documentation for this struct was generated from the following file:
  • PchPcieRpConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PCIE_RP_DXE_CONFIG Member List

This is the complete list of members for PCIE_RP_DXE_CONFIG, including all inherited members.

Header | PCIE_RP_DXE_CONFIG
PcieDeviceOverrideTablePtr | PCIE_RP_DXE_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PMC_GLOBAL_RESET_MASK Union Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
List of all members
PMC_GLOBAL_RESET_MASK Union Reference

Description of Global Reset Trigger/Event Mask register. More...

#include <PmConfig.h>

Detailed Description

Description of Global Reset Trigger/Event Mask register.

Definition at line 163 of file PmConfig.h.

The documentation for this union was generated from the following file:
  • PmConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PMC_GLOBAL_RESET_MASK Member List

This is the complete list of members for PMC_GLOBAL_RESET_MASK, including all inherited members.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PMC_INTERFACE_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
PMC_INTERFACE_CONFIG Struct Reference

The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC. More...

#include <TcssPeiConfig.h>

Public Attributes

UINT8 PmcPdEnable
PMC PD Solution Enable.

Detailed Description

The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC.

Definition at line 81 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PMC_INTERFACE_CONFIG Member List

This is the complete list of members for PMC_INTERFACE_CONFIG, including all inherited members.

PmcPdEnable | PMC_INTERFACE_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PMC_LPM_S0IX_SUB_STATE_EN Union Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
List of all members
PMC_LPM_S0IX_SUB_STATE_EN Union Reference

Low Power Mode Enable config. More...

#include <PmConfig.h>

Detailed Description

Low Power Mode Enable config.

Used to configure if respective S0i2/3 sub-states are to be supported by the platform. Each bit corresponds to one LPM state - LPMx->BITx. Some sub-states will require external FETs controlled by EXT_PWR_GATE#/EXT_PWR_GATE2# pins to gate v1p05-PHY or v1p05-IS supplies

Definition at line 130 of file PmConfig.h.

Member Data Documentation

◆ S0i2p2En

UINT32 PMC_LPM_S0IX_SUB_STATE_EN::S0i2p2En

LPM2 - S0i2.2 Enable.

Requires EXT_PWR_GATE# controlled FET to gate v1p05 PHY. Refer to V1p05PhyExtFetControlEn.

Definition at line 139 of file PmConfig.h.

◆ S0i3p3En

UINT32 PMC_LPM_S0IX_SUB_STATE_EN::S0i3p3En

LPM5 - S0i3.3 Enable.

Requires EXT_PWR_GATE# controlled FET to gate v1p05 PHY. Refer to V1p05PhyExtFetControlEn.

Definition at line 148 of file PmConfig.h.

◆ S0i3p4En

UINT32 PMC_LPM_S0IX_SUB_STATE_EN::S0i3p4En

LPM7 - S0i3.4 Enable.

Requires EXT_PWR_GATE2# controlled FET to gate v1p05-SRAM/ISCLK. Refer to V1p05IsExtFetControlEn.

Definition at line 154 of file PmConfig.h.

The documentation for this union was generated from the following file:
  • PmConfig.h


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PMC_LPM_S0IX_SUB_STATE_EN Member List

This is the complete list of members for PMC_LPM_S0IX_SUB_STATE_EN, including all inherited members.

Reserved | PMC_LPM_S0IX_SUB_STATE_EN
S0i2p0En | PMC_LPM_S0IX_SUB_STATE_EN
S0i2p1En | PMC_LPM_S0IX_SUB_STATE_EN
S0i2p2En | PMC_LPM_S0IX_SUB_STATE_EN
S0i3p0En | PMC_LPM_S0IX_SUB_STATE_EN
S0i3p1En | PMC_LPM_S0IX_SUB_STATE_EN
S0i3p2En | PMC_LPM_S0IX_SUB_STATE_EN
S0i3p3En | PMC_LPM_S0IX_SUB_STATE_EN
S0i3p4En | PMC_LPM_S0IX_SUB_STATE_EN


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PROTECTED_RANGE Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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PROTECTED_RANGE Struct Reference

Protected Flash Range. More...

#include <FlashProtectionConfig.h>

Public Attributes

UINT32 | WriteProtectionEnable: 1
Write or erase is blocked by hardware. 0: Disable; 1: Enable.
UINT32 | ReadProtectionEnable: 1
Read is blocked by hardware. 0: Disable; 1: Enable.
UINT32 | RsvdBits: 30
Reserved.
UINT16 | ProtectedRangeLimit
The address of the upper limit of protection This is a left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison.
UINT16 | ProtectedRangeBase
The address of the upper limit of protection This is a left shifted address by 12 bits with address bits 11:0 are assumed to be 0.

Detailed Description

Protected Flash Range.

Definition at line 51 of file FlashProtectionConfig.h.

The documentation for this struct was generated from the following file:
  • FlashProtectionConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
PROTECTED_RANGE Member List

This is the complete list of members for PROTECTED_RANGE, including all inherited members.

ProtectedRangeBase | PROTECTED_RANGE
ProtectedRangeLimit | PROTECTED_RANGE
ReadProtectionEnable | PROTECTED_RANGE
RsvdBits | PROTECTED_RANGE
WriteProtectionEnable | PROTECTED_RANGE


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: RST_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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RST_CONFIG Struct Reference

Rapid Storage Technology settings. More...

#include <RstConfig.h>

Collaboration diagram for RST_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Raid0: 1
0 : Disable; 1 : Enable RAID0
UINT32 | Raid1: 1
0 : Disable; 1 : Enable RAID1
UINT32 | Raid10: 1
0 : Disable; 1 : Enable RAID10
UINT32 | Raid5: 1
0 : Disable; 1 : Enable RAID5
UINT32 | Irrt: 1
0 : Disable; 1 : Enable Intel Rapid Recovery Technology
UINT32 | OromUiBanner: 1
0 : Disable; 1 : Enable OROM UI and BANNER
UINT32 | OromUiDelay: 2
00b : 2 secs; 01b : 4 secs; 10b : 6 secs; 11 : 8 secs (see : SATA_OROM_DELAY)
UINT32 | HddUnlock: 1
0 : Disable; 1 : Enable. Indicates that the HDD password unlock in the OS is enabled
UINT32 | LedLocate: 1
0 : Disable; 1 : Enable. Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS
UINT32 | IrrtOnly: 1
0 : Disable; 1 : Enable. Allow only IRRT drives to span internal and external ports
UINT32 | SmartStorage: 1
0 : Disable; 1 : Enable RST Smart Storage caching Bit
UINT32 | LegacyOrom: 1
0 : Disable; 1 : Enable RST Legacy OROM
UINT32 | OptaneMemory: 1
0: Disable; 1: Enable RST Optane(TM) Memory
UINT32 | CpuAttachedStorage: 1
0: Disable; 1: Enable CPU Attached Storage
UINT32 | RsvdBits0: 17
Reserved Bits.
RST_HARDWARE_REMAPPED_STORAGE_CONFIG | HardwareRemappedStorageConfig [PCH_MAX_RST_PCIE_STORAGE_CR]
This member describes the details of implementation of Intel RST for PCIe Storage remapping (Intel RST Driver is required) Note: RST for PCIe Sorage remapping is supported only for first SATA controller if more controllers are available.

Detailed Description

Rapid Storage Technology settings.

Revision 1:

  • Initial version.

Definition at line 84 of file RstConfig.h.

The documentation for this struct was generated from the following file:
  • RstConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
RST_CONFIG Member List

This is the complete list of members for RST_CONFIG, including all inherited members.

CpuAttachedStorage | RST_CONFIG
HardwareRemappedStorageConfig | RST_CONFIG
HddUnlock | RST_CONFIG
Header | RST_CONFIG
Irrt | RST_CONFIG
IrrtOnly | RST_CONFIG
LedLocate | RST_CONFIG
LegacyOrom | RST_CONFIG
OptaneMemory | RST_CONFIG
OromUiBanner | RST_CONFIG
OromUiDelay | RST_CONFIG
Raid0 | RST_CONFIG
Raid1 | RST_CONFIG
Raid10 | RST_CONFIG
Raid5 | RST_CONFIG
RsvdBits0 | RST_CONFIG
SmartStorage | RST_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: RST_HARDWARE_REMAPPED_STORAGE_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
RST_HARDWARE_REMAPPED_STORAGE_CONFIG Struct Reference

This structure describes the details of Intel RST for PCIe Storage remapping Note: In order to use this feature, Intel RST Driver is required. More...

#include <RstConfig.h>

Public Attributes

UINT32 | Enable: 1
This member describes whether or not the Intel RST for PCIe Storage remapping should be enabled. More...
UINT32 | RstPcieStoragePort: 5
Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect) The supported ports for PCIe Storage remapping is different depend on the platform and cycle router.
UINT32 | DeviceResetDelay: 8
PCIe Storage Device Reset Delay in milliseconds (ms), which it guarantees such delay gap is fulfilled before PCIe Storage Device configuration space is accessed after an reset caused by the link disable and enable step. More...
UINT32 | RsvdBits0: 18
Reserved bits.

Detailed Description

This structure describes the details of Intel RST for PCIe Storage remapping Note: In order to use this feature, Intel RST Driver is required.

Definition at line 56 of file RstConfig.h.

Member Data Documentation

◆ DeviceResetDelay

UINT32 RST_HARDWARE_REMAPPED_STORAGE_CONFIG::DeviceResetDelay

PCIe Storage Device Reset Delay in milliseconds (ms), which it guarantees such delay gap is fulfilled before PCIe Storage Device configuration space is accessed after an reset caused by the link disable and enable step.

Default value is 100ms.

Definition at line 73 of file RstConfig.h.

◆ Enable

UINT32 RST_HARDWARE_REMAPPED_STORAGE_CONFIG::Enable

This member describes whether or not the Intel RST for PCIe Storage remapping should be enabled.

0: Disable; 1: Enable. Note 1: If Sata Controller is disabled, PCIe Storage Remapping should be disabled as well Note 2: If PCIe Storage remapping is enabled, the PCH integrated AHCI controllers Class Code is configured as RAID

Definition at line 62 of file RstConfig.h.

The documentation for this struct was generated from the following file:
  • RstConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
RST_HARDWARE_REMAPPED_STORAGE_CONFIG Member List

This is the complete list of members for RST_HARDWARE_REMAPPED_STORAGE_CONFIG, including all inherited members.

DeviceResetDelay | RST_HARDWARE_REMAPPED_STORAGE_CONFIG
Enable | RST_HARDWARE_REMAPPED_STORAGE_CONFIG
RstPcieStoragePort | RST_HARDWARE_REMAPPED_STORAGE_CONFIG
RsvdBits0 | RST_HARDWARE_REMAPPED_STORAGE_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: RTC_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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RTC_CONFIG Struct Reference

The RTC_CONFIG block describes the expected configuration of RTC configuration. More...

#include <RtcConfig.h>

Collaboration diagram for RTC_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | BiosInterfaceLock: 1
When set, prevents RTC TS (BUC.TS) from being changed. More...
UINT32 | MemoryLock: 1
When set, bytes 38h-3Fh in the upper 128bytes bank of RTC RAM are locked and cannot be accessed. More...

Detailed Description

The RTC_CONFIG block describes the expected configuration of RTC configuration.

Definition at line 48 of file RtcConfig.h.

Member Data Documentation

◆ BiosInterfaceLock

UINT32 RTC_CONFIG::BiosInterfaceLock

When set, prevents RTC TS (BUC.TS) from being changed.

This BILD bit has different function compared to LPC/eSPI, SPI. 0: Disabled; 1: Enabled

Definition at line 55 of file RtcConfig.h.

◆ MemoryLock

UINT32 RTC_CONFIG::MemoryLock

When set, bytes 38h-3Fh in the upper 128bytes bank of RTC RAM are locked and cannot be accessed.

Writes will be droipped and reads will not return any guaranteed data. 0: Disabled; 1: Enabled

Definition at line 62 of file RtcConfig.h.

The documentation for this struct was generated from the following file:
  • RtcConfig.h


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
RTC_CONFIG Member List

This is the complete list of members for RTC_CONFIG, including all inherited members.

BiosInterfaceLock | RTC_CONFIG
Header | RTC_CONFIG
MemoryLock | RTC_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SA_MISC_PEI_PREMEM_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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SA_MISC_PEI_PREMEM_CONFIG Struct Reference

This configuration block is to configure SA Miscellaneous variables during PEI Pre-Mem phase like programming different System Agent BARs, TsegSize, MmioSize required etc. More...

#include <SaMiscPeiPreMemConfig.h>

Collaboration diagram for SA_MISC_PEI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT8 | SpdAddressTable [MEM_CFG_MAX_SOCKETS]
Offset 28 Memory DIMMs' SPD address for reading SPD data. More...
VOID * S3DataPtr
Offset 44 Memory data save pointer for S3 resume. The memory space should be allocated and filled with proper S3 resume data on a resume path.
UINT32 | SmbusBar
Offset 48 Address of System Agent SMBUS BAR: 0xEFA0
UINT32 | TsegSize
Offset 52 Size of TSEG in bytes. More...
UINT32 | SkipExtGfxScan:1
(Test) Offset 56:0 :1=Skip External Gfx Device Scan; 0=Scan for external graphics devices. Set this policy to skip External Graphics card scanning if the platform uses Internal Graphics only.
UINT32 | BdatEnable:1
Offset 56:1 :This field enables the generation of the BIOS DATA ACPI Tables: 0=FALSE, 1=TRUE.
UINT32 | TxtImplemented:1
OFfset 56:2 :This field currently is used to tell MRC if it should run after TXT initializatoin completed: 0=Run without waiting for TXT, 1=Run after TXT initialization by callback.
UINT32 | ScanExtGfxForLegacyOpRom:1
Offset 56:3 : (Test) Scan External Discrete Graphics Devices for Legacy Only VGA OpROMs. More...
UINT32 | RsvdBits0:28
Offset 56:4 :Reserved for future use.
UINT8 | UserBd
Offset 60 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server.
UINT8 | LockPTMregs
(Test) Offset 61 Lock PCU Thermal Management registers: 0=FALSE, 1=TRUE
UINT8 | BdatTestType
Offset 62 When BdatEnable is set to TRUE, this option selects the type of data which will be populated in the BIOS Data ACPI Tables: 0=RMT, 1=RMT Per Bit, 2=Margin 2D.
UINT8 | Rsvd4
Offset 63 Reserved for config block alignment.
UINT32 | AcpiReservedMemorySize
Offset 64 The Size of a Reserved memory buffer allocated in previous boot for S3 resume used. Originally it is retrieved from AcpiVariableCompatibility variable.
UINT32 | OpRomScanTempMmioBar
(Test) Offset 68 Temporary address to MMIO map OpROMs during VGA scanning. Used for ScanExtGfxForLegacyOpRom feature. MUST BE 16MB ALIGNED!
UINT32 | OpRomScanTempMmioLimit
(Test) Offset 72 Limit address for OpROM MMIO range. Used for ScanExtGfxForLegacyOpRom feature. (OpROMScanTempMmioLimit - OpRomScanTempMmioBar) MUST BE >= 16MB!
UINT32 | Rsvd3
Offset 76 Reserved for config block alignment.
UINT64 | AcpiReservedMemoryBase
Offset 80 The Base address of a Reserved memory buffer allocated in previous boot for S3 resume used. Originally it is retrieved from AcpiVariableCompatibility variable.
UINT64 | SystemMemoryLength
Offset 88 Total system memory length from previous boot, this is required for S3 resume. Originally it is retrieved from AcpiVariableCompatibility variable.
UINT8 | DisableMrcRetrainingOnRtcPowerLoss
Offset 96 Enable/Disable DisableMrcRetrainingOnRtcPowerLoss.
UINT8 | Reserved1 [3]
Offset 97 Reserved for config block alignment.
UINT8 | OfflineCrashDumpEnable
Offset 100 OfflineCrashDump feature enable. If this is enabled, memory must be reserved for BIOS execution for when an OfflineCrashDump occurs.
UINT8 | Rsvd [4]
Reserved for config block alignment.
UINT8 | CkdAddressTable [MEM_CFG_MAX_SOCKETS]
Memory DIMMs' CKD address for read/write CKD data. More...
UINT16 | MrcMustStaticSpdData
Although BIOS provides spd address, MRC need use static spd data in VPD. More...

Detailed Description

This configuration block is to configure SA Miscellaneous variables during PEI Pre-Mem phase like programming different System Agent BARs, TsegSize, MmioSize required etc.

Revision 1:

  • Initial version. Revision 2:
  • Add CkdAddress Table. Revision 3:
  • Add MrcMustStaticSpdData.

Definition at line 56 of file SaMiscPeiPreMemConfig.h.

Member Data Documentation

◆ CkdAddressTable

UINT8 SA_MISC_PEI_PREMEM_CONFIG::CkdAddressTable[MEM_CFG_MAX_SOCKETS]

Memory DIMMs' CKD address for read/write CKD data.

0 - Controller 0 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5 1 - Controller 0 Channel 0 Dimm 1 - DDR4 2 - Controller 0 Channel 1 Dimm 0 -----— DDR5 - LPDDR4 - LPDDR5 3 - Controller 0 Channel 1 Dimm 1 -----— DDR5 2DPC 4 - Controller 0 Channel 2 Dimm 0 ------------— LPDDR4 - LPDDR5 6 - Controller 0 Channel 3 Dimm 0 ------------— LPDDR4 - LPDDR5 8 - Controller 1 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5 9 - Controller 1 Channel 0 Dimm 1 - DDR4 10 - Controller 1 Channel 1 Dimm 0 -----— DDR5 - LPDDR4 - LPDDR5 11 - Controller 1 Channel 1 Dimm 1 -----— DDR5 2DPC 12 - Controller 1 Channel 2 Dimm 0 ------------— LPDDR4 - LPDDR5 14 - Controller 1 Channel 3 Dimm 0 ------------— LPDDR4 - LPDDR5

Definition at line 142 of file SaMiscPeiPreMemConfig.h.

◆ MrcMustStaticSpdData

UINT16 SA_MISC_PEI_PREMEM_CONFIG::MrcMustStaticSpdData

Although BIOS provides spd address, MRC need use static spd data in VPD.

Each bit maps to one dimm.

Definition at line 148 of file SaMiscPeiPreMemConfig.h.

◆ ScanExtGfxForLegacyOpRom

UINT32 SA_MISC_PEI_PREMEM_CONFIG::ScanExtGfxForLegacyOpRom

Offset 56:3 : (Test) Scan External Discrete Graphics Devices for Legacy Only VGA OpROMs.

When enabled, if the primary graphics device is an external discrete graphics device, Si will scan the graphics device for legacy only VGA OpROMs.

This is intended to ease the implementation of a BIOS feature to automatically enable CSM if the Primary Gfx device only supports Legacy VBIOS (No UEFI GOP Present). Otherwise disabling CSM won't result in no video being displayed. This is useful for platforms that implement PCIe slots that allow the end user to install an arbitrary Gfx device.

This setting will only take effect if SkipExtGfxScan == 0. It is ignored otherwise.

  • Disabled (0x0) : Don't Scan for Legacy Only VGA OpROMs (Default)
  • Enabled (0x1) : Scan External Gfx for Legacy Only VGA OpROM

Definition at line 102 of file SaMiscPeiPreMemConfig.h.

◆ SpdAddressTable

UINT8 SA_MISC_PEI_PREMEM_CONFIG::SpdAddressTable[MEM_CFG_MAX_SOCKETS]

Offset 28 Memory DIMMs' SPD address for reading SPD data.

TGL Mapping 0 - Controller 0 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5 1 - Controller 0 Channel 0 Dimm 1 - DDR4 2 - Controller 0 Channel 1 Dimm 0 -----— DDR5 - LPDDR4 - LPDDR5 3 - Controller 0 Channel 1 Dimm 1 -----— DDR5 2DPC 4 - Controller 0 Channel 2 Dimm 0 ------------— LPDDR4 - LPDDR5 6 - Controller 0 Channel 3 Dimm 0 ------------— LPDDR4 - LPDDR5 8 - Controller 1 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5 9 - Controller 1 Channel 0 Dimm 1 - DDR4 10 - Controller 1 Channel 1 Dimm 0 -----— DDR5 - LPDDR4 - LPDDR5 11 - Controller 1 Channel 1 Dimm 1 -----— DDR5 2DPC 12 - Controller 1 Channel 2 Dimm 0 ------------— LPDDR4 - LPDDR5 14 - Controller 1 Channel 3 Dimm 0 ------------— LPDDR4 - LPDDR5

Definition at line 74 of file SaMiscPeiPreMemConfig.h.

◆ TsegSize

UINT32 SA_MISC_PEI_PREMEM_CONFIG::TsegSize

Offset 52 Size of TSEG in bytes.

(Must be power of 2) 0x400000: 4MB for Release build 0x1000000 : 16MB for Debug build

Definition at line 82 of file SaMiscPeiPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • SaMiscPeiPreMemConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
SA_MISC_PEI_PREMEM_CONFIG Member List

This is the complete list of members for SA_MISC_PEI_PREMEM_CONFIG, including all inherited members.

AcpiReservedMemoryBase | SA_MISC_PEI_PREMEM_CONFIG
AcpiReservedMemorySize | SA_MISC_PEI_PREMEM_CONFIG
BdatEnable | SA_MISC_PEI_PREMEM_CONFIG
BdatTestType | SA_MISC_PEI_PREMEM_CONFIG
CkdAddressTable | SA_MISC_PEI_PREMEM_CONFIG
DisableMrcRetrainingOnRtcPowerLoss | SA_MISC_PEI_PREMEM_CONFIG
Header | SA_MISC_PEI_PREMEM_CONFIG
LockPTMregs | SA_MISC_PEI_PREMEM_CONFIG
MrcMustStaticSpdData | SA_MISC_PEI_PREMEM_CONFIG
OfflineCrashDumpEnable | SA_MISC_PEI_PREMEM_CONFIG
OpRomScanTempMmioBar | SA_MISC_PEI_PREMEM_CONFIG
OpRomScanTempMmioLimit | SA_MISC_PEI_PREMEM_CONFIG
Reserved1 | SA_MISC_PEI_PREMEM_CONFIG
Rsvd | SA_MISC_PEI_PREMEM_CONFIG
Rsvd3 | SA_MISC_PEI_PREMEM_CONFIG
Rsvd4 | SA_MISC_PEI_PREMEM_CONFIG
RsvdBits0 | SA_MISC_PEI_PREMEM_CONFIG
S3DataPtr | SA_MISC_PEI_PREMEM_CONFIG
ScanExtGfxForLegacyOpRom | SA_MISC_PEI_PREMEM_CONFIG
SkipExtGfxScan | SA_MISC_PEI_PREMEM_CONFIG
SmbusBar | SA_MISC_PEI_PREMEM_CONFIG
SpdAddressTable | SA_MISC_PEI_PREMEM_CONFIG
SystemMemoryLength | SA_MISC_PEI_PREMEM_CONFIG
TsegSize | SA_MISC_PEI_PREMEM_CONFIG
TxtImplemented | SA_MISC_PEI_PREMEM_CONFIG
UserBd | SA_MISC_PEI_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SA_XDCI_IRQ_INT_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
SA_XDCI_IRQ_INT_CONFIG Struct Reference

The SA XDCI INT Pin and IRQ number. More...

#include <TcssPeiConfig.h>

Public Attributes

UINT8 | IntPing
Int Pin Number.
UINT8 | Irq
Irq Number.

Detailed Description

The SA XDCI INT Pin and IRQ number.

Definition at line 89 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
SA_XDCI_IRQ_INT_CONFIG Member List

This is the complete list of members for SA_XDCI_IRQ_INT_CONFIG, including all inherited members.

IntPing | SA_XDCI_IRQ_INT_CONFIG
Irq | SA_XDCI_IRQ_INT_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SATA_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
SATA_CONFIG Struct Reference

The SATA_CONFIG block describes the expected configuration of the SATA controllers. More...

#include <SataConfig.h>

Collaboration diagram for SATA_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 | Enable
This member describes whether or not the SATA controllers should be enabled. More...
UINT8 | TestMode
(Test) 0: Disable; 1: Allow entrance to the PCH SATA test modes
UINT8 | SalpSupport
0: Disable; 1: Enable Aggressive Link Power Management
UINT8 | PwrOptEnable
0: Disable; 1: Enable SATA Power Optimizer on PCH side.
UINT8 | EsataSpeedLimit
EsataSpeedLimit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. More...
UINT8 | LedEnable
SATA LED indicates SATA controller activity. 0: Disable; 1: Enable SATA LED.
UINT8 | RaidDeviceId
This option allows to configure SATA controller device ID while in RAID mode. More...
UINT8 | SataRstInterrupt
Controlls which interrupts will be linked to SATA controller CAP list This option will take effect only if SATA controller is in RAID mode Default: PchSataMsix
UINT8 | SataMode
Determines the system will be configured to which SATA mode. More...
UINT8 | SpeedLimit
Indicates the maximum speed the SATA controller can support. More...
UINT8 | EnclosureSupport
Enclosure Management Support. 0: Disable; 1: Enable.
UINT8 | SgpioSupport
Controlls whenever Serial GPIO support is enabled for controller 0: Disable; 1: Enable.
PCH_SATA_PORT_CONFIG | PortSettings [PCH_MAX_SATA_PORTS]
This member configures the features, property, and capability for each SATA port.
SATA_THERMAL_THROTTLING ThermalThrottling
This field decides the settings of Sata thermal throttling. More...

Detailed Description

The SATA_CONFIG block describes the expected configuration of the SATA controllers.

Revision 1:

  • Initial version. Revision 2:
  • Added DevSlpGpioPinMux.

Definition at line 133 of file SataConfig.h.

Member Data Documentation

◆ Enable

UINT8 SATA_CONFIG::Enable

This member describes whether or not the SATA controllers should be enabled.

0: Disable; 1: Enable.

Definition at line 138 of file SataConfig.h.

◆ EsataSpeedLimit

UINT8 SATA_CONFIG::EsataSpeedLimit

EsataSpeedLimit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.

Please be noted, this setting could be cleared by HBA reset, which might be issued by EFI AHCI driver when POST time, or by SATA inbox driver/RST driver after POST. To support the Speed Limitation when POST, the EFI AHCI driver should preserve the setting before and after initialization. For support it after POST, it's dependent on driver's behavior. 0: Disable; 1: Enable

Definition at line 152 of file SataConfig.h.

◆ RaidDeviceId

UINT8 SATA_CONFIG::RaidDeviceId

This option allows to configure SATA controller device ID while in RAID mode.

Refer to SATA_RAID_DEV_ID enumeration for supported options. Choosing Client will allow RST driver loading, RSTe driver will not be able to load Choosing Alternate will not allow RST inbox driver loading in Windows Choosing Server will allow RSTe driver loading, RST driver will not load 0: Client; 1: Alternate; 2: Server

Definition at line 162 of file SataConfig.h.

◆ SataMode

UINT8 SATA_CONFIG::SataMode

Determines the system will be configured to which SATA mode.

Refer to SATA_MODE enumeration for supported options. Default is SataModeAhci.

Definition at line 174 of file SataConfig.h.

◆ SpeedLimit

UINT8 SATA_CONFIG::SpeedLimit

Indicates the maximum speed the SATA controller can support.

Refer to SATA_SPEED enumeration for supported options. 0h: SataSpeedDefault; 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2); 3h: 6 Gb/s (Gen 1)

Definition at line 180 of file SataConfig.h.

◆ ThermalThrottling

SATA_THERMAL_THROTTLING SATA_CONFIG::ThermalThrottling

This field decides the settings of Sata thermal throttling.

When the Suggested Setting is enabled, PCH RC will use the suggested representative values.

Definition at line 195 of file SataConfig.h.

The documentation for this struct was generated from the following file:
  • SataConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
SATA_CONFIG Member List

This is the complete list of members for SATA_CONFIG, including all inherited members.

Enable | SATA_CONFIG
EnclosureSupport | SATA_CONFIG
EsataSpeedLimit | SATA_CONFIG
Header | SATA_CONFIG
LedEnable | SATA_CONFIG
PortSettings | SATA_CONFIG
PwrOptEnable | SATA_CONFIG
RaidDeviceId | SATA_CONFIG
SalpSupport | SATA_CONFIG
SataMode | SATA_CONFIG
SataRstInterrupt | SATA_CONFIG
SgpioSupport | SATA_CONFIG
SpeedLimit | SATA_CONFIG
TestMode | SATA_CONFIG
ThermalThrottling | SATA_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SATA_THERMAL_THROTTLING Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
SATA_THERMAL_THROTTLING Struct Reference

This structure lists PCH supported SATA thermal throttling register setting for customization. More...

#include <SataConfig.h>

Public Attributes

UINT32 | P0T1M: 2
Port 0 T1 Multipler.
UINT32 | P0T2M: 2
Port 0 T2 Multipler.
UINT32 | P0T3M: 2
Port 0 T3 Multipler.
UINT32 | P0TDisp: 2
Port 0 Tdispatch.
UINT32 | P1T1M: 2
Port 1 T1 Multipler.
UINT32 | P1T2M: 2
Port 1 T2 Multipler.
UINT32 | P1T3M: 2
Port 1 T3 Multipler.
UINT32 | P1TDisp: 2
Port 1 Tdispatch.
UINT32 | P0Tinact: 2
Port 0 Tinactive.
UINT32 | P0TDispFinit: 1
Port 0 Alternate Fast Init Tdispatch.
UINT32 | P1Tinact: 2
Port 1 Tinactive.
UINT32 | P1TDispFinit: 1
Port 1 Alternate Fast Init Tdispatch.
UINT32 | SuggestedSetting: 1
0: Disable; 1: Enable suggested representative values
UINT32 | RsvdBits0: 9
Reserved bits.

Detailed Description

This structure lists PCH supported SATA thermal throttling register setting for customization.

The settings is programmed through SATA Index/Data registers. When the SuggestedSetting is enabled, the customized values are ignored.

Definition at line 106 of file SataConfig.h.

The documentation for this struct was generated from the following file:
  • SataConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
SATA_THERMAL_THROTTLING Member List

This is the complete list of members for SATA_THERMAL_THROTTLING, including all inherited members.

P0T1M | SATA_THERMAL_THROTTLING
P0T2M | SATA_THERMAL_THROTTLING
P0T3M | SATA_THERMAL_THROTTLING
P0TDisp | SATA_THERMAL_THROTTLING
P0TDispFinit | SATA_THERMAL_THROTTLING
P0Tinact | SATA_THERMAL_THROTTLING
P1T1M | SATA_THERMAL_THROTTLING
P1T2M | SATA_THERMAL_THROTTLING
P1T3M | SATA_THERMAL_THROTTLING
P1TDisp | SATA_THERMAL_THROTTLING
P1TDispFinit | SATA_THERMAL_THROTTLING
P1Tinact | SATA_THERMAL_THROTTLING
RsvdBits0 | SATA_THERMAL_THROTTLING
SuggestedSetting | SATA_THERMAL_THROTTLING


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SERIAL_IO_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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SERIAL_IO_CONFIG Struct Reference

The SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers. More...

#include <SerialIoConfig.h>

Collaboration diagram for SERIAL_IO_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
SERIAL_IO_SPI_CONFIG | SpiDeviceConfig [PCH_MAX_SERIALIO_SPI_CONTROLLERS]
SPI Configuration.
SERIAL_IO_I2C_CONFIG | I2cDeviceConfig [PCH_MAX_SERIALIO_I2C_CONTROLLERS]
I2C Configuration.
SERIAL_IO_I3C_CONFIG | I3cDeviceConfig [PCH_MAX_SERIALIO_I3C_CONTROLLERS]
I3C Configuration.
SERIAL_IO_UART_CONFIG | UartDeviceConfig [PCH_MAX_SERIALIO_UART_CONTROLLERS]
UART Configuration.

Detailed Description

The SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers.

Revision 1:

  • Inital version. Revision 2:
  • Modified SPI Config to support pinmux functionality. Revision 3:
  • Modified I3C Config to support more controllers.

Definition at line 61 of file SerialIoConfig.h.

The documentation for this struct was generated from the following file:
  • SerialIoConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
SERIAL_IO_CONFIG Member List

This is the complete list of members for SERIAL_IO_CONFIG, including all inherited members.

Header | SERIAL_IO_CONFIG
I2cDeviceConfig | SERIAL_IO_CONFIG
I3cDeviceConfig | SERIAL_IO_CONFIG
SpiDeviceConfig | SERIAL_IO_CONFIG
UartDeviceConfig | SERIAL_IO_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SERIAL_IO_I2C_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
SERIAL_IO_I2C_CONFIG Struct Reference

Serial IO I2C Controller Configuration. More...

#include <SerialIoDevices.h>

Collaboration diagram for SERIAL_IO_I2C_CONFIG:
[legend]

Public Attributes

UINT8 PadTermination
SerialIoI2cPci see SERIAL_IO_I2C_MODE More...
I2C_PIN_MUX PinMux
I2C pin mux configuration.

Detailed Description

Serial IO I2C Controller Configuration.

Definition at line 220 of file SerialIoDevices.h.

Member Data Documentation

◆ PadTermination

UINT8 SERIAL_IO_I2C_CONFIG::PadTermination

SerialIoI2cPci see SERIAL_IO_I2C_MODE

I2C Pads Internal Termination. For more information please see Platform Design Guide. Supported values (check GPIO_ELECTRICAL_CONFIG for reference): GpioTermNone: No termination, GpioTermWpu1K: 1kOhm weak pull-up, GpioTermWpu5K: 5kOhm weak pull-up, GpioTermWpu20K: 20kOhm weak pull-up

Definition at line 231 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
SERIAL_IO_I2C_CONFIG Member List

This is the complete list of members for SERIAL_IO_I2C_CONFIG, including all inherited members.

PadTermination | SERIAL_IO_I2C_CONFIG
PinMux | SERIAL_IO_I2C_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SERIAL_IO_I3C_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
SERIAL_IO_I3C_CONFIG Struct Reference

The SERIAL_IO_I3C_CONFIG provides the configurations for Serial IO I3C controller. More...

#include <SerialIoDevices.h>

Collaboration diagram for SERIAL_IO_I3C_CONFIG:
[legend]

Public Attributes

UINT8 | Mode
<b<SerialIoI3cPci see SERIAL_IO_I3C_MODE
UINT8 | Reserved [3]
Reserved bytes.

Detailed Description

The SERIAL_IO_I3C_CONFIG provides the configurations for Serial IO I3C controller.

Definition at line 269 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
SERIAL_IO_I3C_CONFIG Member List

This is the complete list of members for SERIAL_IO_I3C_CONFIG, including all inherited members.

Mode | SERIAL_IO_I3C_CONFIG
Reserved | SERIAL_IO_I3C_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SERIAL_IO_SPI_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
SERIAL_IO_SPI_CONFIG Struct Reference

The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller. More...

#include <SerialIoDevices.h>

Collaboration diagram for SERIAL_IO_SPI_CONFIG:
[legend]

Public Attributes

UINT8 | Mode
SerialIoSpiPci see SERIAL_IO_SPI_MODE
UINT8 | DefaultCsOutput
0 = CS0 CS1, CS2, CS3. Default CS used by the SPI HC
UINT8 | CsPolarity [PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]
Selects SPI ChipSelect signal polarity, 0 = low 1 = High
UINT8 | CsEnable [PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]
0 = Enable 1 = Disable. Based on this setting GPIO for given SPIx CSx will be configured in Native mode
UINT8 | CsMode
0 = HW Control 1 = SW Control. Sets Chip Select Control mode Hardware or Software.
UINT8 | CsState
0 = CS is set to low 1 = CS is set to high
SPI_PIN_MUX PinMux
SPI Pinmux configuration.

Detailed Description

The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller.

Definition at line 86 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h


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SERIAL_IO_SPI_CONFIG Member List

This is the complete list of members for SERIAL_IO_SPI_CONFIG, including all inherited members.

CsEnable | SERIAL_IO_SPI_CONFIG
CsMode | SERIAL_IO_SPI_CONFIG
CsPolarity | SERIAL_IO_SPI_CONFIG
CsState | SERIAL_IO_SPI_CONFIG
DefaultCsOutput | SERIAL_IO_SPI_CONFIG
Mode | SERIAL_IO_SPI_CONFIG
PinMux | SERIAL_IO_SPI_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SERIAL_IO_UART_ATTRIBUTES Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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SERIAL_IO_UART_ATTRIBUTES Struct Reference

UART Settings. More...

#include <SerialIoDevices.h>

Public Attributes

UINT32 | BaudRate
115200 Max 6000000 MdePkg.dec PcdUartDefaultBaudRate
UINT8 | Parity
1 - No Parity see EFI_PARITY_TYPE MdePkg.dec PcdUartDefaultParity
UINT8 | DataBits
8 MdePkg.dec PcdUartDefaultDataBits
UINT8 | StopBits
1 - One Stop Bit see EFI_STOP_BITS_TYPE MdePkg.dec PcdUartDefaultStopBits
UINT8 | AutoFlow
FALSE IntelFrameworkModulePkg.dsc PcdIsaBusSerialUseHalfHandshake

Detailed Description

UART Settings.

Definition at line 143 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
SERIAL_IO_UART_ATTRIBUTES Member List

This is the complete list of members for SERIAL_IO_UART_ATTRIBUTES, including all inherited members.

AutoFlow | SERIAL_IO_UART_ATTRIBUTES
BaudRate | SERIAL_IO_UART_ATTRIBUTES
DataBits | SERIAL_IO_UART_ATTRIBUTES
Parity | SERIAL_IO_UART_ATTRIBUTES
StopBits | SERIAL_IO_UART_ATTRIBUTES


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SERIAL_IO_UART_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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SERIAL_IO_UART_CONFIG Struct Reference

Serial IO UART Controller Configuration. More...

#include <SerialIoDevices.h>

Collaboration diagram for SERIAL_IO_UART_CONFIG:
[legend]

Public Attributes

SERIAL_IO_UART_ATTRIBUTES Attributes
see SERIAL_IO_UART_ATTRIBUTES
UART_PIN_MUX PinMux
UART pin mux configuration.
UINT8 | Mode
SerialIoUartPci see SERIAL_IO_UART_MODE
UINT8 | DBG2
FALSE If TRUE adds UART to DBG2 table and overrides UartPg to SerialIoUartPgDisabled
UINT8 | PowerGating
SerialIoUartPgAuto Applies to Hidden/COM/SkipInit see SERIAL_IO_UART_PG
UINT8 | DmaEnable
TRUE Applies to SerialIoUartPci only. Informs OS driver to use DMA, if false it will run in PIO mode

Detailed Description

Serial IO UART Controller Configuration.

Definition at line 166 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
SERIAL_IO_UART_CONFIG Member List

This is the complete list of members for SERIAL_IO_UART_CONFIG, including all inherited members.

Attributes | SERIAL_IO_UART_CONFIG
DBG2 | SERIAL_IO_UART_CONFIG
DmaEnable | SERIAL_IO_UART_CONFIG
Mode | SERIAL_IO_UART_CONFIG
PinMux | SERIAL_IO_UART_CONFIG
PowerGating | SERIAL_IO_UART_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SI_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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SI_CONFIG Struct Reference

The Silicon Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware. More...

#include <SiConfig.h>

Collaboration diagram for SI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0 - 27 Config Block Header.
UINT8 | SkipSsidProgramming
This is used to skip the SSID programming in silicon code. More...
UINT8 | RsvdBytes0 [3]
offset 29 - 31
UINT16 | CustomizedSvid
When SkipSsidProgramming is FALSE, silicon code will use this as default value to program the SVID for all internal devices. More...
UINT16 | CustomizedSsid
When SkipSsidProgramming is FALSE, silicon code will use this as default value to program the Sid for all internal devices. More...
UINT32 * | SsidTablePtr
SsidTablePtr contains the SVID_SID_INIT_ENTRY table. More...
UINT16 | NumberOfSsidTableEntry
Number of valid enties in SsidTablePtr. More...
UINT8 | RsvdBytes1 [2]
offset 42 - 43
UINT8 | SkipBiosDoneWhenFwUpdate
This is used to skip setting BIOS_DONE MSR during firmware update boot mode. More...
UINT8 | RsvdBytes2 [3]
Offset 45 - 47.

Detailed Description

The Silicon Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware.

Revision 1: - Initial version.

Definition at line 51 of file SiConfig.h.

Member Data Documentation

◆ CustomizedSsid

UINT16 SI_CONFIG::CustomizedSsid

When SkipSsidProgramming is FALSE, silicon code will use this as default value to program the Sid for all internal devices.

0: use silicon default SSID 0x7270 , Non-zero: use customized SSID. offset 34 - 35

Definition at line 75 of file SiConfig.h.

◆ CustomizedSvid

UINT16 SI_CONFIG::CustomizedSvid

When SkipSsidProgramming is FALSE, silicon code will use this as default value to program the SVID for all internal devices.

0: use silicon default SVID 0x8086 , Non-zero: use customized SVID. offset 32 - 33

Definition at line 69 of file SiConfig.h.

◆ NumberOfSsidTableEntry

UINT16 SI_CONFIG::NumberOfSsidTableEntry

Number of valid enties in SsidTablePtr.

This is valid when SkipSsidProgramming is FALSE; Default is 0. offset 40 - 41

Definition at line 114 of file SiConfig.h.

◆ SkipBiosDoneWhenFwUpdate

UINT8 SI_CONFIG::SkipBiosDoneWhenFwUpdate

This is used to skip setting BIOS_DONE MSR during firmware update boot mode.

When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, skip setting BIOS_DONE MSR at EndofPei. 0: FALSE, 1: TRUE Offset 44

Definition at line 122 of file SiConfig.h.

◆ SkipSsidProgramming

UINT8 SI_CONFIG::SkipSsidProgramming

This is used to skip the SSID programming in silicon code.

When set to TRUE, silicon code will not do any SSID programming and platform code needs to handle that by itself properly. 0: FALSE, 1: TRUE offset 28

Definition at line 62 of file SiConfig.h.

◆ SsidTablePtr

UINT32* SI_CONFIG::SsidTablePtr

SsidTablePtr contains the SVID_SID_INIT_ENTRY table.

This is valid when SkipSsidProgramming is FALSE; It doesn't need to contain entries for all Intel internal devices. It can only contains the SVID_SID_INIT_ENTRY entries for those Dev# Func# which needs to be overridden. In the enties, only Dev, Function, SubSystemVendorId, and SubSystemId are required. Default is NULL.

E.g. Platform only needs to override BDF 0:31:5 to AAAA:BBBB and BDF 0:31:3 to CCCC:DDDD, it can be done in platform like this: STATIC SVID_SID_INIT_ENTRY mSsidTablePtr[SI_MAX_DEVICE_COUNT] = {0};

VOID SiPolicyUpdate () { UINT32 EntryCount = 0; SiPolicy->SkipSsidProgramming = FALSE; SiPolicy->SsidTablePtr = mSsidTablePtr;

mSsidTablePtr[EntryCount].Address.Bits.Device = SpiDeviceNumber (); mSsidTablePtr[EntryCount].Address.Bits.Function = SpiFunctionNumber (); mSsidTablePtr[EntryCount].SvidSidValue.SubSystemVendorId = 0xAAAA; mSsidTablePtr[EntryCount].SvidSidValue.SubSystemId = 0xBBBB; EntryCount ++; mSsidTablePtr[EntryCount].Address.Bits.Device = HdaDevNumber (); mSsidTablePtr[EntryCount].Address.Bits.Function = HdaFuncNumber (); mSsidTablePtr[EntryCount].SvidSidValue.SubSystemVendorId = 0xCCCC; mSsidTablePtr[EntryCount].SvidSidValue.SubSystemId = 0xDDDD; EntryCount ++; ASSERT (EntryCount < SI_MAX_DEVICE_COUNT); SiPolicy->NumberOfSsidTableEntry = EntryCount; } offset 36 - 39

Definition at line 108 of file SiConfig.h.

The documentation for this struct was generated from the following file:
  • SiConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
SI_CONFIG Member List

This is the complete list of members for SI_CONFIG, including all inherited members.

CustomizedSsid | SI_CONFIG
CustomizedSvid | SI_CONFIG
Header | SI_CONFIG
NumberOfSsidTableEntry | SI_CONFIG
RsvdBytes0 | SI_CONFIG
RsvdBytes1 | SI_CONFIG
RsvdBytes2 | SI_CONFIG
SkipBiosDoneWhenFwUpdate | SI_CONFIG
SkipSsidProgramming | SI_CONFIG
SsidTablePtr | SI_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SI_PREMEM_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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SI_PREMEM_CONFIG Struct Reference

The Silicon PreMem Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware. More...

#include <SiPreMemConfig.h>

Collaboration diagram for SI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0 - 27 Config Block Header.
UINT32 | PlatformDebugOption: 4
Platform Debug Option As a main switch to enable platform debug capability and relevant settings. More...
UINT32 | RsvdBits: 28
offset 28 - 31
UINT8 | SkipOverrideBootModeWhenFwUpdate
This is used to skip override boot mode during firmware update boot mode. More...
UINT8 | RsvdBytes [3]
offset 32

Detailed Description

The Silicon PreMem Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware.

Revision 1:

  • Initial version.

Definition at line 58 of file SiPreMemConfig.h.

Member Data Documentation

◆ PlatformDebugOption

UINT32 SI_PREMEM_CONFIG::PlatformDebugOption

Platform Debug Option As a main switch to enable platform debug capability and relevant settings.

Manual: Do not use Platform Debug Option to override other debug-relevant policies, but the user must set each debug option manually, aimed at advanced users.

PlatformDebugOption related policies please refer to PLATFORM_DEBUG_OPTION 0:Disabled; 2:Enabled TraceHub active; 4:Enabled TraceHub ready; 6:Enabled TraceHub power off; 7:Manual

Definition at line 68 of file SiPreMemConfig.h.

◆ SkipOverrideBootModeWhenFwUpdate

UINT8 SI_PREMEM_CONFIG::SkipOverrideBootModeWhenFwUpdate

This is used to skip override boot mode during firmware update boot mode.

When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, skip setting boot mode to BOOT_WITH_FULL_CONFIGURATION in PEI memory init. 0: FALSE, 1: TRUE

Definition at line 76 of file SiPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • SiPreMemConfig.h


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This is the complete list of members for SI_PREMEM_CONFIG, including all inherited members.

Header | SI_PREMEM_CONFIG
PlatformDebugOption | SI_PREMEM_CONFIG
RsvdBits | SI_PREMEM_CONFIG
RsvdBytes | SI_PREMEM_CONFIG
SkipOverrideBootModeWhenFwUpdate | SI_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SPI_PIN_MUX Struct Reference

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SPI_PIN_MUX Struct Reference

SPI signals pin muxing settings. More...

#include <SerialIoDevices.h>

Public Attributes

UINT32 | Cs [PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]
CS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS_*.
UINT32 | Clk
CLK Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK_*.
UINT32 | Miso
MISO Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO_*.
UINT32 | Mosi
MOSI Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI_*.

Detailed Description

SPI signals pin muxing settings.

If signal can be enable only on a single pin then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_SPIx_* in GpioPins*.h for supported settings on a given platform

Definition at line 76 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h


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This is the complete list of members for SPI_PIN_MUX, including all inherited members.

Clk | SPI_PIN_MUX
Cs | SPI_PIN_MUX
Miso | SPI_PIN_MUX
Mosi | SPI_PIN_MUX


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SVID_SID_VALUE Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
List of all members
SVID_SID_VALUE Struct Reference

Subsystem Vendor ID / Subsystem ID. More...

#include <SiConfig.h>

Detailed Description

Subsystem Vendor ID / Subsystem ID.

Definition at line 135 of file SiConfig.h.

The documentation for this struct was generated from the following file:
  • SiConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
SVID_SID_VALUE Member List

This is the complete list of members for SVID_SID_VALUE, including all inherited members.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TCSS_DEVEN_PEI_PREMEM_CONFIG Union Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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TCSS_DEVEN_PEI_PREMEM_CONFIG Union Reference

The TCSS_DEVEN_PEI_PREMEM_CONFIG block describes Device Enable settings for TCSS. More...

#include <TcssPeiPreMemConfig.h>

Public Attributes

UINT32 TcssDevEn
Maps to bits in TCSS_DEVEN_0_0_0_MCHBAR_IMPH.

Detailed Description

The TCSS_DEVEN_PEI_PREMEM_CONFIG block describes Device Enable settings for TCSS.

Definition at line 48 of file TcssPeiPreMemConfig.h.

The documentation for this union was generated from the following file:
  • TcssPeiPreMemConfig.h


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TCSS_DEVEN_PEI_PREMEM_CONFIG Member List

This is the complete list of members for TCSS_DEVEN_PEI_PREMEM_CONFIG, including all inherited members.

TcssDevEn | TCSS_DEVEN_PEI_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TCSS_IOM_ORI_OVERRIDE Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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TCSS_IOM_ORI_OVERRIDE Struct Reference

The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS. More...

#include <TcssPeiConfig.h>

Public Attributes

UINT16 | AuxOri
Bits defining value for IOM Aux Orientation Register.
UINT16 | HslOri
Bits defining value for IOM HSL Orientation Register.

Detailed Description

The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS.

Definition at line 156 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
TCSS_IOM_ORI_OVERRIDE Member List

This is the complete list of members for TCSS_IOM_ORI_OVERRIDE, including all inherited members.

AuxOri | TCSS_IOM_ORI_OVERRIDE
HslOri | TCSS_IOM_ORI_OVERRIDE


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TCSS_IOM_PEI_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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TCSS_IOM_PEI_CONFIG Struct Reference

The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS. More...

#include <TcssPeiConfig.h>

Collaboration diagram for TCSS_IOM_PEI_CONFIG:
[legend]

Public Attributes

IOM_AUX_ORI_PAD_CONFIG | IomAuxPortPad [MAX_IOM_AUX_BIAS_COUNT]
The IOM_AUX_ORI_BIAS_CTRL port config setting.
IOM_INTERFACE_CONFIG IomInterface
Config settings are BIOS <-> IOM interface.
PMC_INTERFACE_CONFIG PmcInterface
Config settings for BIOS <-> PMC interface.
UINT8 | TcStateLimit
Tcss C-State deep stage.
UINT8 | TcNotifyIgd
Wake iGfx from D3 on HPD_ASSERT or HPD_IRQ assocaited with the DP_ALT and DP tunneling connection.
UINT8 | Reserved [2]
Reserved bytes for future use.

Detailed Description

The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS.

Definition at line 164 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h


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TCSS_IOM_PEI_CONFIG Member List

This is the complete list of members for TCSS_IOM_PEI_CONFIG, including all inherited members.

IomAuxPortPad | TCSS_IOM_PEI_CONFIG
IomInterface | TCSS_IOM_PEI_CONFIG
PmcInterface | TCSS_IOM_PEI_CONFIG
Reserved | TCSS_IOM_PEI_CONFIG
TcNotifyIgd | TCSS_IOM_PEI_CONFIG
TcStateLimit | TCSS_IOM_PEI_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TCSS_MISC_PEI_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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TCSS_MISC_PEI_CONFIG Struct Reference

The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS. More...

#include <TcssPeiConfig.h>

Collaboration diagram for TCSS_MISC_PEI_CONFIG:
[legend]

Public Attributes

SA_XDCI_IRQ_INT_CONFIG SaXdci
System Agent Xdci Int Pin and Irq setting.
TCSS_TYPEC_CONV_TYPEA | TcssConvTypeA [MAX_TCSS_USB3_PORTS]
TCSS Port Convert to TypeA.
UINT8 | Reserved [8]
Reserved bytes for future use.

Detailed Description

The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS.

Definition at line 177 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h


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This is the complete list of members for TCSS_MISC_PEI_CONFIG, including all inherited members.

Reserved | TCSS_MISC_PEI_CONFIG
SaXdci | TCSS_MISC_PEI_CONFIG
TcssConvTypeA | TCSS_MISC_PEI_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TCSS_PCIE_PEI_POLICY Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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TCSS_PCIE_PEI_POLICY Struct Reference

TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS. More...

#include <TcssPeiConfig.h>

Collaboration diagram for TCSS_PCIE_PEI_POLICY:
[legend]

Public Attributes

UINT8 Reserved [4]
Reserved bytes for future use.

Detailed Description

TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS.

Definition at line 148 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h


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Reserved | TCSS_PCIE_PEI_POLICY


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TCSS_PCIE_PORT_POLICY Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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TCSS_PCIE_PORT_POLICY Struct Reference

The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS. More...

#include <TcssPeiConfig.h>

Public Attributes

UINT8 | AcsEnabled
Indicate whether the ACS is enabled. 0: Disable; 1: Enable.
UINT8 | LtrEnable
Latency Tolerance Reporting Mechanism. 0: Disable; 1: Enable.
UINT8 | PtmEnabled
Enables PTM capability.
UINT8 | Aspm
The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
UINT8 | SlotNumber
Indicates the slot number for the root port. Default is the value as root port index.
UINT8 | SlotPowerLimitScale
(Test) Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is zero.
UINT16 | SlotPowerLimitValue
(Test) Specifies upper limit on power supplies by slot. Leave as 0 to set to default. Default is zero.
UINT8 | AdvancedErrorReporting
Indicate whether the Advanced Error Reporting is enabled. 0: Disable; 1: Enable.
UINT8 | UnsupportedRequestReport
Indicate whether the Unsupported Request Report is enabled. 0: Disable; 1: Enable.
UINT8 | FatalErrorReport
Indicate whether the Fatal Error Report is enabled. 0: Disable; 1: Enable.
UINT8 | NoFatalErrorReport
Indicate whether the No Fatal Error Report is enabled. 0: Disable; 1: Enable.
UINT8 | CorrectableErrorReport
Indicate whether the Correctable Error Report is enabled. 0: Disable; 1: Enable.
UINT8 | SystemErrorOnFatalError
Indicate whether the System Error on Fatal Error is enabled. 0: Disable; 1: Enable.
UINT8 | SystemErrorOnNonFatalError
Indicate whether the System Error on Non Fatal Error is enabled. 0: Disable; 1: Enable.
UINT8 | SystemErrorOnCorrectableError
Indicate whether the System Error on Correctable Error is enabled. 0: Disable; 1: Enable.
UINT16 | LtrMaxSnoopLatency
Latency Tolerance Reporting, Max Snoop Latency.
UINT16 | LtrMaxNoSnoopLatency
Latency Tolerance Reporting, Max Non-Snoop Latency.
UINT8 | SnoopLatencyOverrideMode
Latency Tolerance Reporting, Snoop Latency Override Mode.
UINT8 | SnoopLatencyOverrideMultiplier
Latency Tolerance Reporting, Snoop Latency Override Multiplier.
UINT16 | SnoopLatencyOverrideValue
Latency Tolerance Reporting, Snoop Latency Override Value.
UINT8 | NonSnoopLatencyOverrideMode
Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
UINT8 | NonSnoopLatencyOverrideMultiplier
Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
UINT16 | NonSnoopLatencyOverrideValue
Latency Tolerance Reporting, Non-Snoop Latency Override Value.
UINT8 | ForceLtrOverride
0: Disable; 1: Enable.
UINT8 | LtrConfigLock
0: Disable; 1: Enable.

Detailed Description

The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS.

Definition at line 113 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h


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TCSS_PCIE_PORT_POLICY Member List

This is the complete list of members for TCSS_PCIE_PORT_POLICY, including all inherited members.

AcsEnabled | TCSS_PCIE_PORT_POLICY
AdvancedErrorReporting | TCSS_PCIE_PORT_POLICY
Aspm | TCSS_PCIE_PORT_POLICY
CorrectableErrorReport | TCSS_PCIE_PORT_POLICY
FatalErrorReport | TCSS_PCIE_PORT_POLICY
ForceLtrOverride | TCSS_PCIE_PORT_POLICY
LtrConfigLock | TCSS_PCIE_PORT_POLICY
LtrEnable | TCSS_PCIE_PORT_POLICY
LtrMaxNoSnoopLatency | TCSS_PCIE_PORT_POLICY
LtrMaxSnoopLatency | TCSS_PCIE_PORT_POLICY
NoFatalErrorReport | TCSS_PCIE_PORT_POLICY
NonSnoopLatencyOverrideMode | TCSS_PCIE_PORT_POLICY
NonSnoopLatencyOverrideMultiplier | TCSS_PCIE_PORT_POLICY
NonSnoopLatencyOverrideValue | TCSS_PCIE_PORT_POLICY
PtmEnabled | TCSS_PCIE_PORT_POLICY
SlotNumber | TCSS_PCIE_PORT_POLICY
SlotPowerLimitScale | TCSS_PCIE_PORT_POLICY
SlotPowerLimitValue | TCSS_PCIE_PORT_POLICY
SnoopLatencyOverrideMode | TCSS_PCIE_PORT_POLICY
SnoopLatencyOverrideMultiplier | TCSS_PCIE_PORT_POLICY
SnoopLatencyOverrideValue | TCSS_PCIE_PORT_POLICY
SystemErrorOnCorrectableError | TCSS_PCIE_PORT_POLICY
SystemErrorOnFatalError | TCSS_PCIE_PORT_POLICY
SystemErrorOnNonFatalError | TCSS_PCIE_PORT_POLICY
UnsupportedRequestReport | TCSS_PCIE_PORT_POLICY


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TCSS_PEI_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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TCSS_PEI_CONFIG Struct Reference

The TCSS_PEI_CONFIG block describes TCSS settings for SA. More...

#include <TcssPeiConfig.h>

Collaboration diagram for TCSS_PEI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
TCSS_PCIE_PEI_POLICY PciePolicy
The PCIe Config.
USB_CONFIG UsbConfig
USB config is shared between PCH and SA.
TCSS_IOM_PEI_CONFIG IomConfig
The Iom Config.
TCSS_MISC_PEI_CONFIG MiscConfig
The MISC Config.

Detailed Description

The TCSS_PEI_CONFIG block describes TCSS settings for SA.

Definition at line 186 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
TCSS_PEI_CONFIG Member List

This is the complete list of members for TCSS_PEI_CONFIG, including all inherited members.

Header | TCSS_PEI_CONFIG
IomConfig | TCSS_PEI_CONFIG
MiscConfig | TCSS_PEI_CONFIG
PciePolicy | TCSS_PEI_CONFIG
UsbConfig | TCSS_PEI_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TCSS_PEI_PREMEM_CONFIG Struct Reference

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TCSS_PEI_PREMEM_CONFIG Struct Reference

This configuration block describes TCSS settings. More...

#include <TcssPeiPreMemConfig.h>

Collaboration diagram for TCSS_PEI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
TCSS_DEVEN_PEI_PREMEM_CONFIG DevEnConfig
TCSS DEVEN.
TCSS_USBTC_PEI_PERMEM_CONFIG UsbTcConfig
USB Type C Port Configuration.

Detailed Description

This configuration block describes TCSS settings.

Revision 1:

  • Initial version.

Definition at line 77 of file TcssPeiPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiPreMemConfig.h


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TCSS_PEI_PREMEM_CONFIG Member List

This is the complete list of members for TCSS_PEI_PREMEM_CONFIG, including all inherited members.

DevEnConfig | TCSS_PEI_PREMEM_CONFIG
Header | TCSS_PEI_PREMEM_CONFIG
UsbTcConfig | TCSS_PEI_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TCSS_USBTC_PEI_PERMEM_CONFIG Struct Reference

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TCSS_USBTC_PEI_PERMEM_CONFIG Struct Reference

The TCSS_USBTC_PEI_PERMEM_CONFIG block describes IOM settings for TCSS. More...

#include <TcssPeiPreMemConfig.h>

Public Attributes

UINT32 | UsbTcPortEn: 4
bitmap for USB Type C enabled ports
UINT32 | Rsvd: 28
Reserved bytes for future use.

Detailed Description

The TCSS_USBTC_PEI_PERMEM_CONFIG block describes IOM settings for TCSS.

Definition at line 67 of file TcssPeiPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiPreMemConfig.h


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TCSS_USBTC_PEI_PERMEM_CONFIG Member List

This is the complete list of members for TCSS_USBTC_PEI_PERMEM_CONFIG, including all inherited members.

Rsvd | TCSS_USBTC_PEI_PERMEM_CONFIG
UsbTcPortEn | TCSS_USBTC_PEI_PERMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TELEMETRY_PEI_CONFIG Struct Reference

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TELEMETRY_PEI_CONFIG Struct Reference

This configuration block describes Telemetry settings in PostMem. More...

#include <TelemetryPeiConfig.h>

Collaboration diagram for TELEMETRY_PEI_CONFIG:
[legend]

Public Attributes

UINT32 CpuCrashLogEnable
Config Block Header.

Detailed Description

This configuration block describes Telemetry settings in PostMem.

Revision 1:

  • Initial version.

Definition at line 63 of file TelemetryPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TelemetryPeiConfig.h


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TELEMETRY_PEI_CONFIG Member List

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CpuCrashLogEnable | TELEMETRY_PEI_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TELEMETRY_PEI_PREMEM_CONFIG Struct Reference

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TELEMETRY_PEI_PREMEM_CONFIG Struct Reference

This configuration block describes Telemetry settings in PreMem. More...

#include <TelemetryPeiConfig.h>

Collaboration diagram for TELEMETRY_PEI_PREMEM_CONFIG:
[legend]

Public Attributes

UINT32 CpuCrashLogDevice
Config Block Header.

Detailed Description

This configuration block describes Telemetry settings in PreMem.

Revision 1:

  • Initial version.

Definition at line 53 of file TelemetryPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TelemetryPeiConfig.h


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TELEMETRY_PEI_PREMEM_CONFIG Member List

This is the complete list of members for TELEMETRY_PEI_PREMEM_CONFIG, including all inherited members.

CpuCrashLogDevice | TELEMETRY_PEI_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: THC_CONFIG Struct Reference

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THC_CONFIG Struct Reference

THC_CONFIG block provides the configurations forTouch Host Controllers. More...

#include <ThcConfig.h>

Collaboration diagram for THC_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
THC_PORT ThcPort [2]
Port Configuration.

Detailed Description

THC_CONFIG block provides the configurations forTouch Host Controllers.

Assignment field in each THC port controlls the THC behavior.

Available scenarios: 1: Single Port 0 used by THC0

  • THC0 Enabled
  • Port0 assigned to THC0
  • Port1 unassigned
  • THC1 will be automatically Disabled. 2: Both ports used by THC0
  • THC0 Enabled
  • Port0 assigned to THC0
  • Port1 assigned to THC0
  • THC1 will be automatically Disabled. 3: Port 0 used by THC0 and Port 1 used by THC1
  • THC0 Enabled
  • Port0 assigned to THC0
  • THC1 Enabled
  • Port1 assigned to THC1. 4: Both Ports unassigned. Both THC Controllers will be disabled in that case.
Note
Invalid scenario that will cause ASSERT.
  1. Same port Number assigned to THC0 or THC1.
  2. Two Ports assigned to THC1.

Revision 1:

  • Inital version. Revision 2:
  • Add HidOverSpi THC_MODE Revision 3:
  • Expand HidOverSpi support Revision 4:
  • Add ResetSequencingDelay in THC_HID_OVER_SPI Revision 5:
  • Moved out reset data from THC_HID_OVER_SPI
  • Add THC_HID_OVER_I2C

Definition at line 196 of file ThcConfig.h.

The documentation for this struct was generated from the following file:
  • ThcConfig.h


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THC_CONFIG Member List

This is the complete list of members for THC_CONFIG, including all inherited members.

Header | THC_CONFIG
ThcPort | THC_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: THC_HID_OVER_I2C Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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THC_HID_OVER_I2C Struct Reference

THC Hid Over I2C mode related settings. More...

#include <ThcConfig.h>

Public Attributes

UINT32 | DeviceAddress
Device Address.
UINT32 | ConnectionSpeed
Connection Speed - Frequency [Hz].
UINT32 | AddressingMode
Addressing Mode 0x1: The connection uses 10-bit addressing. More...
UINT32 | StandardModeSerialClockLineHighPeriod
Serial Clock Line High Period.
UINT32 | StandardModeSerialClockLineLowPeriod
Standard Mode Serial Clock Line Low Period.
UINT32 | StandardModeSerialDataLineTransmitHoldPeriod
Standard Mode Serial Data Line Transmit Hold Period.
UINT32 | StandardModeSerialDataLineReceiveHoldPeriod
Standard Mode Serial Data Line Receive Hold Period.
UINT32 | FastModeSerialClockLineHighPeriod
Fast Mode Serial Clock Line High Period.
UINT32 | FastModeSerialClockLineLowPeriod
Fast Mode Serial Clock Line Low Period.
UINT32 | FastModeSerialDataLineTransmitHoldPeriod
Fast Mode Serial Data Line Transmit Hold Period.
UINT32 | FastModeSerialDataLineReceiveHoldPeriod
Fast Mode Serial Data Line Receive Hold Period.
UINT32 | MaxSuppressedSpikesSMFMFMP
Maximum Length Of Suppressed Spikes In Std Mode Fast Mode And Fast Mode Plus.
UINT32 | FastModePlusSerialClockLineHighPeriod
Fast Mode Plus Serial Clock Line High Period.
UINT32 | FastModePlusSerialClockLineLowPeriod
Fast Mode Plus Serial Clock Line Low Period.
UINT32 | FastModePlusSerialDataLineTransmitHoldPeriod
Fast Mode Plus Serial Data Line Transmit Hold Period.
UINT32 | FastModePlusSerialDataLineReceiveHoldPeriod
Fast Mode Plus Serial Data Line Receive Hold Period.
UINT32 | HighSpeedModePlusSerialClockLineHighPeriod
High Speed Mode Plus Serial Clock Line High Period.
UINT32 | HighSpeedModePlusSerialClockLineLowPeriod
High Speed Mode Plus Serial Clock Line Low Period.
UINT32 | HighSpeedModePlusSerialDataLineTransmitHoldPeriod
High Speed Mode Plus Serial Data Line Transmit Hold Period.
UINT32 | HighSpeedModePlusSerialDataLineReceiveHoldPeriod
High Speed Mode Plus Serial Data Line Receive Hold Period.
UINT32 | MaximumLengthOfSuppressedSpikesInHighSpeedMode
Maximum Length Of Suppressed Spikes In High Speed Mode.

Detailed Description

THC Hid Over I2C mode related settings.

Only applicable when HidOverI2c is enbled.

Definition at line 96 of file ThcConfig.h.

Member Data Documentation

◆ AddressingMode

UINT32 THC_HID_OVER_I2C::AddressingMode

Addressing Mode 0x1: The connection uses 10-bit addressing.

0x0: The connection uses 7-bit addressing.

Definition at line 104 of file ThcConfig.h.

The documentation for this struct was generated from the following file:
  • ThcConfig.h


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
THC_HID_OVER_I2C Member List

This is the complete list of members for THC_HID_OVER_I2C, including all inherited members.

AddressingMode | THC_HID_OVER_I2C
ConnectionSpeed | THC_HID_OVER_I2C
DeviceAddress | THC_HID_OVER_I2C
FastModePlusSerialClockLineHighPeriod | THC_HID_OVER_I2C
FastModePlusSerialClockLineLowPeriod | THC_HID_OVER_I2C
FastModePlusSerialDataLineReceiveHoldPeriod | THC_HID_OVER_I2C
FastModePlusSerialDataLineTransmitHoldPeriod | THC_HID_OVER_I2C
FastModeSerialClockLineHighPeriod | THC_HID_OVER_I2C
FastModeSerialClockLineLowPeriod | THC_HID_OVER_I2C
FastModeSerialDataLineReceiveHoldPeriod | THC_HID_OVER_I2C
FastModeSerialDataLineTransmitHoldPeriod | THC_HID_OVER_I2C
HighSpeedModePlusSerialClockLineHighPeriod | THC_HID_OVER_I2C
HighSpeedModePlusSerialClockLineLowPeriod | THC_HID_OVER_I2C
HighSpeedModePlusSerialDataLineReceiveHoldPeriod | THC_HID_OVER_I2C
HighSpeedModePlusSerialDataLineTransmitHoldPeriod | THC_HID_OVER_I2C
MaximumLengthOfSuppressedSpikesInHighSpeedMode | THC_HID_OVER_I2C
MaxSuppressedSpikesSMFMFMP | THC_HID_OVER_I2C
StandardModeSerialClockLineHighPeriod | THC_HID_OVER_I2C
StandardModeSerialClockLineLowPeriod | THC_HID_OVER_I2C
StandardModeSerialDataLineReceiveHoldPeriod | THC_HID_OVER_I2C
StandardModeSerialDataLineTransmitHoldPeriod | THC_HID_OVER_I2C


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: THC_HID_OVER_SPI Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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THC_HID_OVER_SPI Struct Reference

THC Hid Over SPI mode related settings. More...

#include <ThcConfig.h>

Public Attributes

UINT32 | Frequency
Connection Speed - SPI Frequency in Hz.
UINT32 | InputReportHeaderAddress
Input Report Header Address.
UINT32 | InputReportBodyAddress
Input Report Body Address.
UINT32 | OutputReportAddress
Output Report Address.
UINT32 | ReadOpcode
Read Opcode.
UINT32 | WriteOpcode
Write Opcode.
UINT32 | Flags
Flags.
UINT32 | LimitPacketSize
Limit Packet Size.

Detailed Description

THC Hid Over SPI mode related settings.

Only applicable when HidOverSpi is enbled.

Definition at line 73 of file ThcConfig.h.

The documentation for this struct was generated from the following file:
  • ThcConfig.h


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THC_HID_OVER_SPI Member List

This is the complete list of members for THC_HID_OVER_SPI, including all inherited members.

Flags | THC_HID_OVER_SPI
Frequency | THC_HID_OVER_SPI
InputReportBodyAddress | THC_HID_OVER_SPI
InputReportHeaderAddress | THC_HID_OVER_SPI
LimitPacketSize | THC_HID_OVER_SPI
OutputReportAddress | THC_HID_OVER_SPI
ReadOpcode | THC_HID_OVER_SPI
WriteOpcode | THC_HID_OVER_SPI


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: THC_PORT Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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THC_PORT Struct Reference

Port Configuration structure required for each Port that THC might use. More...

#include <ThcConfig.h>

Collaboration diagram for THC_PORT:
[legend]

Public Attributes

UINT32 | Assignment
Sets THCx assignment see THC_PORT_ASSIGNMENT.
UINT32 | InterruptPinMuxing
Each GPIO PORTx/SPIx INTB Pin has different muxing options refer to GPIO_*_MUXING_THC_SPIx_*.
UINT8 | WakeOnTouch
1 = Enable 0 = Disable. Based on this setting vGPIO for given THC will be in native mode, and additional _CRS for wake will be exposed in ACPI
UINT8 | Mode
1 = Hid over SPI 0 = THC. Switch between Intel THC protcol and Industry standard HID Over SPI protocol.
UINT8 | TimestampTimerMode
Timestamp timer behavior in D0i2 1 = Timer resets to 0 when entering D0i2 0 = Timer is paused instead of reset to 0 when entering D0i2.
UINT8 | Reserved [1]
Reserved.
THC_HID_OVER_SPI HidOverSpi
Hid Over Spi mode settings.
UINT32 | ActiveLtr
0xFFFFFFFF = Driver Default Active Ltr
UINT32 | IdleLtr
0xFFFFFFFF = Driver Default Idle Ltr
UINT32 | PerformanceLimitation
Performance Limitation.
UINT32 | DisplayFrameSyncPeriod
Period of the emulated display frame sync [ms] The minimum period is 2ms, maximum period is 100ms Default: 10ms.
THC_RESET Reset
Reset Line settings.
THC_HID_OVER_I2C HidOverI2c
Hid Over I2c mode settings.

Detailed Description

Port Configuration structure required for each Port that THC might use.

Definition at line 128 of file ThcConfig.h.

The documentation for this struct was generated from the following file:
  • ThcConfig.h


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THC_PORT Member List

This is the complete list of members for THC_PORT, including all inherited members.

ActiveLtr | THC_PORT
Assignment | THC_PORT
DisplayFrameSyncPeriod | THC_PORT
HidOverI2c | THC_PORT
HidOverSpi | THC_PORT
IdleLtr | THC_PORT
InterruptPinMuxing | THC_PORT
Mode | THC_PORT
PerformanceLimitation | THC_PORT
Reserved | THC_PORT
Reset | THC_PORT
TimestampTimerMode | THC_PORT
WakeOnTouch | THC_PORT


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: THC_RESET Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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THC_RESET Struct Reference

THC Reset Pad related settings. More...

#include <ThcConfig.h>

Public Attributes

UINT32 | ResetPad
Reset Pad - 0x0 = THC HW default BIOS will pass Pad infromation to ACPI, this Pad is used in _RST function.
UINT32 | ResetPadTrigger
Reset Pad Trigger.
UINT32 | ResetSequencingDelay
Policy control for reset sequencing delay (_INI, _RST)

Detailed Description

THC Reset Pad related settings.

Definition at line 87 of file ThcConfig.h.

The documentation for this struct was generated from the following file:
  • ThcConfig.h


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THC_RESET Member List

This is the complete list of members for THC_RESET, including all inherited members.

ResetPad | THC_RESET
ResetPadTrigger | THC_RESET
ResetSequencingDelay | THC_RESET


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: THERMAL_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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THERMAL_CONFIG Struct Reference

The THERMAL_CONFIG block describes the expected configuration of the Thermal IP block. More...

#include <ThermalConfig.h>

Collaboration diagram for THERMAL_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | PchHotEnable: 1
Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: Disabled, 1: Enabled.
THERMAL_THROTTLE_LEVELS TTLevels
This field decides the settings of Thermal throttling. More...
DMI_HW_WIDTH_CONTROL DmiHaAWC
This field decides the settings of DMI throttling. More...
UINT16 | PchHotLevel
The recommendation is the same as Cat Trip point. More...

Detailed Description

The THERMAL_CONFIG block describes the expected configuration of the Thermal IP block.

Definition at line 97 of file ThermalConfig.h.

Member Data Documentation

◆ DmiHaAWC

DMI_HW_WIDTH_CONTROL THERMAL_CONFIG::DmiHaAWC

This field decides the settings of DMI throttling.

When the Suggested Setting is enabled, PCH RC will use the suggested representative values.

Definition at line 110 of file ThermalConfig.h.

◆ PchHotLevel

UINT16 THERMAL_CONFIG::PchHotLevel

The recommendation is the same as Cat Trip point.

This field decides the temperature, default is 120. Temperature value used for PCHHOT# pin assertion based on 2s complement format

  • 0x001 positive 1'C
  • 0x000 0'C
  • 0x1FF negative 1'C
  • 0x1D8 negative 40'C
  • and so on

Definition at line 121 of file ThermalConfig.h.

◆ TTLevels

THERMAL_THROTTLE_LEVELS THERMAL_CONFIG::TTLevels

This field decides the settings of Thermal throttling.

When the Suggested Setting is enabled, PCH RC will use the suggested representative values.

Definition at line 105 of file ThermalConfig.h.

The documentation for this struct was generated from the following file:
  • ThermalConfig.h


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THERMAL_CONFIG Member List

This is the complete list of members for THERMAL_CONFIG, including all inherited members.

DmiHaAWC | THERMAL_CONFIG
Header | THERMAL_CONFIG
PchHotEnable | THERMAL_CONFIG
PchHotLevel | THERMAL_CONFIG
TTLevels | THERMAL_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: THERMAL_THROTTLE_LEVELS Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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THERMAL_THROTTLE_LEVELS Struct Reference

This structure lists PCH supported throttling register setting for custimization. More...

#include <ThermalConfig.h>

Public Attributes

UINT32 | T0Level: 9
Custimized T0Level value. If SuggestedSetting is used, this setting is ignored.
UINT32 | T1Level: 9
Custimized T1Level value. If SuggestedSetting is used, this setting is ignored.
UINT32 | T2Level: 9
Custimized T2Level value. If SuggestedSetting is used, this setting is ignored.
UINT32 | TTEnable: 1
Enable the thermal throttle function. If SuggestedSetting is used, this settings is ignored.
UINT32 | TTState13Enable: 1
When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state. More...
UINT32 | TTLock: 1
When set to 1, this entire register (TL) is locked and remains locked until the next platform reset. More...
UINT32 | SuggestedSetting: 1
0: Disable; 1: Enable suggested representative values.
UINT32 | RsvdBits0: 1
Reserved bits.
UINT32 | Rsvd0
Reserved bytes.

Detailed Description

This structure lists PCH supported throttling register setting for custimization.

When the SuggestedSetting is enabled, the customized values are ignored.

Definition at line 47 of file ThermalConfig.h.

Member Data Documentation

◆ TTLock

UINT32 THERMAL_THROTTLE_LEVELS::TTLock

When set to 1, this entire register (TL) is locked and remains locked until the next platform reset.

If SuggestedSetting is used, this setting is ignored.

Definition at line 61 of file ThermalConfig.h.

◆ TTState13Enable

UINT32 THERMAL_THROTTLE_LEVELS::TTState13Enable

When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state.

If SuggestedSetting is used, this setting is ignored.

Definition at line 56 of file ThermalConfig.h.

The documentation for this struct was generated from the following file:
  • ThermalConfig.h


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THERMAL_THROTTLE_LEVELS Member List

This is the complete list of members for THERMAL_THROTTLE_LEVELS, including all inherited members.

Rsvd0 | THERMAL_THROTTLE_LEVELS
RsvdBits0 | THERMAL_THROTTLE_LEVELS
SuggestedSetting | THERMAL_THROTTLE_LEVELS
T0Level | THERMAL_THROTTLE_LEVELS
T1Level | THERMAL_THROTTLE_LEVELS
T2Level | THERMAL_THROTTLE_LEVELS
TTEnable | THERMAL_THROTTLE_LEVELS
TTLock | THERMAL_THROTTLE_LEVELS
TTState13Enable | THERMAL_THROTTLE_LEVELS


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TRACE_HUB_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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TRACE_HUB_CONFIG Struct Reference

TRACE_HUB_CONFIG block describes TraceHub settings. More...

#include <TraceHubConfig.h>

Public Attributes

UINT64 | MemReg0Size
Trace hub memory buffer region size value. More...
UINT8 | EnableMode
Trace hub mode. More...
UINT8 | AetEnabled
AET is one of FW trace agents which is exclusively rounted to one TraceHub. More...
UINT8 | BiosTraceSink
Indicate if BIOS trace is sent to this TraceHub instance 0 = Disable; 1 = Enabled.
UINT8 | Reserved [5]
Filling reserved for future use & Config block DW alignment.

Detailed Description

TRACE_HUB_CONFIG block describes TraceHub settings.

Definition at line 84 of file TraceHubConfig.h.

Member Data Documentation

◆ AetEnabled

UINT8 TRACE_HUB_CONFIG::AetEnabled

AET is one of FW trace agents which is exclusively rounted to one TraceHub.

i.e. when one TraceHub device enableds it, the other one must disable it. 0 = Disable; 1 = Enabled

Definition at line 103 of file TraceHubConfig.h.

◆ EnableMode

UINT8 TRACE_HUB_CONFIG::EnableMode

Trace hub mode.

Default is disabled. 0 = Disable; 1 = Enabled Refer to TRACE_HUB_ENABLE_MODE

Definition at line 97 of file TraceHubConfig.h.

◆ MemReg0Size

UINT64 TRACE_HUB_CONFIG::MemReg0Size

Trace hub memory buffer region size value.

Supported size refer to TRACE_BUFFER_SIZE

Definition at line 90 of file TraceHubConfig.h.

The documentation for this struct was generated from the following file:
  • TraceHubConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

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TRACE_HUB_CONFIG Member List

This is the complete list of members for TRACE_HUB_CONFIG, including all inherited members.

AetEnabled | TRACE_HUB_CONFIG
BiosTraceSink | TRACE_HUB_CONFIG
EnableMode | TRACE_HUB_CONFIG
MemReg0Size | TRACE_HUB_CONFIG
Reserved | TRACE_HUB_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TRACE_HUB_PREMEM_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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TRACE_HUB_PREMEM_CONFIG Struct Reference

Trace Hub PreMem Configuration Contains Trace Hub settings Revision 1: - Initial version. More...

#include <TraceHubConfig.h>

Collaboration diagram for TRACE_HUB_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
TRACE_HUB_CONFIG TraceHub [MaxTraceHub]
Trace Hub Config.

Detailed Description

Trace Hub PreMem Configuration Contains Trace Hub settings Revision 1: - Initial version.

Definition at line 131 of file TraceHubConfig.h.

The documentation for this struct was generated from the following file:
  • TraceHubConfig.h


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TRACE_HUB_PREMEM_CONFIG Member List

This is the complete list of members for TRACE_HUB_PREMEM_CONFIG, including all inherited members.

Header | TRACE_HUB_PREMEM_CONFIG
TraceHub | TRACE_HUB_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: UART_PIN_MUX Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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UART_PIN_MUX Struct Reference

UART signals pin muxing settings. More...

#include <SerialIoDevices.h>

Public Attributes

UINT32 | Rx
RXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RXD_*.
UINT32 | Tx
TXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TXD_*.
UINT32 | Rts
RTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS_*.
UINT32 | Cts
CTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS_*.

Detailed Description

UART signals pin muxing settings.

If signal can be enable only on a single pin then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_UARTx_* in GpioPins*.h for supported settings on a given platform

Definition at line 156 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h


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UART_PIN_MUX Member List

This is the complete list of members for UART_PIN_MUX, including all inherited members.

Cts | UART_PIN_MUX
Rts | UART_PIN_MUX
Rx | UART_PIN_MUX
Tx | UART_PIN_MUX


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: USB2_PHY_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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USB2_PHY_CONFIG Struct Reference

This structure holds info on how to tune electrical parameters of USB2 ports based on board layout. More...

#include <Usb2PhyConfig.h>

Collaboration diagram for USB2_PHY_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
USB2_PHY_PARAMETERS Port [MAX_USB2_PORTS]
This structure configures per USB2 port physical settings. More...

Detailed Description

This structure holds info on how to tune electrical parameters of USB2 ports based on board layout.

Revision 1:

  • Initial version.

Definition at line 102 of file Usb2PhyConfig.h.

Member Data Documentation

◆ Port

USB2_PHY_PARAMETERS USB2_PHY_CONFIG::Port[MAX_USB2_PORTS]

This structure configures per USB2 port physical settings.

It allows to setup the port location and port length, and configures the port strength accordingly. Changing this policy values from default ones may require disabling USB2 PHY Sus Well Power Gating through Usb2PhySusPgEnable on PCH-LP

Definition at line 110 of file Usb2PhyConfig.h.

The documentation for this struct was generated from the following file:
  • Usb2PhyConfig.h


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USB2_PHY_CONFIG Member List

This is the complete list of members for USB2_PHY_CONFIG, including all inherited members.

Header | USB2_PHY_CONFIG
Port | USB2_PHY_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: USB2_PHY_PARAMETERS Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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USB2_PHY_PARAMETERS Struct Reference

This structure configures per USB2 AFE settings. More...

#include <Usb2PhyConfig.h>

Public Attributes

UINT8 | Petxiset
Per Port HS Preemphasis Bias (PERPORTPETXISET) 000b - 0mV 001b - 11.25mV 010b - 16.9mV 011b - 28.15mV 100b - 28.15mV 101b - 39.35mV 110b - 45mV 111b - 56.3mV.
UINT8 | Txiset
Per Port HS Transmitter Bias (PERPORTTXISET) 000b - 0mV 001b - 11.25mV 010b - 16.9mV 011b - 28.15mV 100b - 28.15mV 101b - 39.35mV 110b - 45mV 111b - 56.3mV.
UINT8 | Predeemp
Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN) 00b - Emphasis OFF 01b - De-emphasis ON 10b - Pre-emphasis ON 11b - Pre-emphasis & De-emphasis ON.
UINT8 | Pehalfbit
Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF) 1b - half-bit pre-emphasis 0b - full-bit pre-emphasis.
UINT8 | PredeempSemiflexEn
Semi Flexi Pre/DE-emphasis (reg_predeemp_semiflexi_en): 1: Choose the predeemp setting (increase the DC amplitude) 0: Choose the predeemp setting (decrease the DC amplitude)

Detailed Description

This structure configures per USB2 AFE settings.

It allows to setup the port electrical parameters.

Definition at line 49 of file Usb2PhyConfig.h.

The documentation for this struct was generated from the following file:
  • Usb2PhyConfig.h


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USB2_PHY_PARAMETERS Member List

This is the complete list of members for USB2_PHY_PARAMETERS, including all inherited members.

Pehalfbit | USB2_PHY_PARAMETERS
Petxiset | USB2_PHY_PARAMETERS
Predeemp | USB2_PHY_PARAMETERS
PredeempSemiflexEn | USB2_PHY_PARAMETERS
Txiset | USB2_PHY_PARAMETERS


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: USB2_PORT_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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USB2_PORT_CONFIG Struct Reference

This structure configures per USB2.0 port settings like enabling and overcurrent protection. More...

#include <UsbConfig.h>

Public Attributes

UINT32 | OverCurrentPin: 8
These members describe the specific over current pin number of USB 2.0 Port N. More...
UINT32 | Enable: 1
0: Disable; 1: Enable.
UINT32 | PortResetMessageEnable: 1
0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message
UINT32 | SwDeviceModeEnable: 1
0: Disable USB2 Port Device Mode; 1: Force USB2 Port Device Mode
UINT32 | RsvdBits0: 21
Reserved bits.

Detailed Description

This structure configures per USB2.0 port settings like enabling and overcurrent protection.

Definition at line 60 of file UsbConfig.h.

Member Data Documentation

◆ OverCurrentPin

UINT32 USB2_PORT_CONFIG::OverCurrentPin

These members describe the specific over current pin number of USB 2.0 Port N.

It is SW's responsibility to ensure that a given port's bit map is set only for one OC pin Description. USB2 and USB3 on the same combo Port must use the same OC pin.

Definition at line 66 of file UsbConfig.h.

The documentation for this struct was generated from the following file:
  • UsbConfig.h


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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
USB2_PORT_CONFIG Member List

This is the complete list of members for USB2_PORT_CONFIG, including all inherited members.

Enable | USB2_PORT_CONFIG
OverCurrentPin | USB2_PORT_CONFIG
PortResetMessageEnable | USB2_PORT_CONFIG
RsvdBits0 | USB2_PORT_CONFIG
SwDeviceModeEnable | USB2_PORT_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: USB3_PORT_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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USB3_PORT_CONFIG Struct Reference

This structure configures per USB3.x port settings like enabling and overcurrent protection. More...

#include <UsbConfig.h>

Public Attributes

UINT32 | OverCurrentPin: 8
These members describe the specific over current pin number of USB 3.x Port N. More...
UINT32 | Enable: 1
0: Disable; 1: Enable.
UINT32 | RsvdBits0: 23
Reserved bits.

Detailed Description

This structure configures per USB3.x port settings like enabling and overcurrent protection.

Definition at line 76 of file UsbConfig.h.

Member Data Documentation

◆ OverCurrentPin

UINT32 USB3_PORT_CONFIG::OverCurrentPin

These members describe the specific over current pin number of USB 3.x Port N.

It is SW's responsibility to ensure that a given port's bit map is set only for one OC pin Description. USB2 and USB3 on the same combo Port must use the same OC pin.

Definition at line 82 of file UsbConfig.h.

The documentation for this struct was generated from the following file:
  • UsbConfig.h


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USB3_PORT_CONFIG Member List

This is the complete list of members for USB3_PORT_CONFIG, including all inherited members.

Enable | USB3_PORT_CONFIG
OverCurrentPin | USB3_PORT_CONFIG
RsvdBits0 | USB3_PORT_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: VMD_PEI_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
VMD_PEI_CONFIG Struct Reference

This configuration block is to configure VMD related variables used in PostMem PEI. More...

#include <VmdPeiConfig.h>

Collaboration diagram for VMD_PEI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT8 | VmdEnable
Offset 28 This field used to enable VMD controller 1=Enable(default) 0=Disable.
UINT8 | VmdGlobalMapping
Offset 29 This field used to enable Global Mapping 1=Enable 0=Disable(default)
UINT8 | Rsvd [2]
Offset 30-39 Reserved.
RP_BDF_DATA | VmdPortEnable [VMD_MAX_DEVICES]
Offset 40 to 163 This field used to to store b/d/f for each root port along with enable Support 1=Enable 0=Disable (default)
VOID * VmdVariablePtr
This config block will be updated as per the EFI variable.
UINT32 | VmdCfgBarBase
Temp Address VMD CFG BAR Default is 0xA0000000
UINT32 | VmdMemBar1Base
Temp Address VMD CFG BAR Default is 0xA2000000
UINT32 | VmdMemBar2Base
Temp Address VMD CFG BAR Default is 0xA4000000

Detailed Description

This configuration block is to configure VMD related variables used in PostMem PEI.

If VMD Device is not supported, all policies can be ignored. Revision 1:

  • Initial version.

Definition at line 61 of file VmdPeiConfig.h.

The documentation for this struct was generated from the following file:
  • VmdPeiConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
VMD_PEI_CONFIG Member List

This is the complete list of members for VMD_PEI_CONFIG, including all inherited members.

Header | VMD_PEI_CONFIG
Rsvd | VMD_PEI_CONFIG
VmdCfgBarBase | VMD_PEI_CONFIG
VmdEnable | VMD_PEI_CONFIG
VmdGlobalMapping | VMD_PEI_CONFIG
VmdMemBar1Base | VMD_PEI_CONFIG
VmdMemBar2Base | VMD_PEI_CONFIG
VmdPortEnable | VMD_PEI_CONFIG
VmdVariablePtr | VMD_PEI_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: VTD_ENGINE_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
List of all members
VTD_ENGINE_CONFIG Struct Reference

This structure describes each VT-d engine. More...

#include <VtdConfig.h>

Detailed Description

This structure describes each VT-d engine.

Definition at line 80 of file VtdConfig.h.

The documentation for this struct was generated from the following file:
  • VtdConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
VTD_ENGINE_CONFIG Member List

This is the complete list of members for VTD_ENGINE_CONFIG, including all inherited members.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: XDCI_CONFIG Struct Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Public Attributes | List of all members
XDCI_CONFIG Struct Reference

The XDCI_CONFIG block describes the configurations of the xDCI Usb Device controller. More...

#include <UsbConfig.h>

Public Attributes

UINT32 | Enable: 1
This member describes whether or not the xDCI controller should be enabled. More...
UINT32 | RsvdBits0: 31
Reserved bits.

Detailed Description

The XDCI_CONFIG block describes the configurations of the xDCI Usb Device controller.

Definition at line 91 of file UsbConfig.h.

Member Data Documentation

◆ Enable

UINT32 XDCI_CONFIG::Enable

This member describes whether or not the xDCI controller should be enabled.

0: Disable; 1: Enable.

Definition at line 96 of file UsbConfig.h.

The documentation for this struct was generated from the following file:
  • UsbConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
XDCI_CONFIG Member List

This is the complete list of members for XDCI_CONFIG, including all inherited members.

Enable | XDCI_CONFIG
RsvdBits0 | XDCI_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Index

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Class Index
_ | a | b | c | d | e | f | g | h | i | m | o | p | r | s | t | u | v | x
_
EFI_HOB_MEMORY_ALLOCATION IOM_INTERFACE_CONFIG PCH_P2SB_CONFIG SI_PREMEM_CONFIG
EFI_HOB_MEMORY_ALLOCATION_BSP_STORE IPU_PREMEM_CONFIG PCH_PCIE_CLOCK SPI_PIN_MUX
_CONFIG_BLOCK EFI_HOB_MEMORY_ALLOCATION_HEADER IPv4_ADDRESS PCH_PCIE_CONFIG SVID_SID_VALUE
_CONFIG_BLOCK_HEADER EFI_HOB_MEMORY_ALLOCATION_MODULE IPv6_ADDRESS PCH_PCIE_ROOT_PORT_CONFIG
t
_CONFIG_BLOCK_TABLE_STRUCT EFI_HOB_MEMORY_ALLOCATION_STACK ISH_CONFIG PCH_PCIE_RP_PREMEM_CONFIG
_EFI_MM_RESERVED_MMRAM_REGION EFI_HOB_MEMORY_POOL ISH_GP PCH_PM_CONFIG TCSS_DEVEN_PEI_PREMEM_CONFIG
_EFI_PEI_MP_SERVICES_PPI EFI_HOB_RESOURCE_DESCRIPTOR ISH_GPIO_CONFIG PCH_SATA_PORT_CONFIG TCSS_IOM_ORI_OVERRIDE
_ITBT_GENERIC_CONFIG EFI_HOB_UEFI_CAPSULE ISH_I2C PCH_SMBUS_PREMEM_CONFIG TCSS_IOM_PEI_CONFIG
_ITBT_ROOTPORT_CONFIG EFI_IP_ADDRESS ISH_I2C_PIN_CONFIG PCH_TRACE_HUB_PREMEM_CONFIG TCSS_MISC_PEI_CONFIG
_LIST_ENTRY EFI_MAC_ADDRESS ISH_I3C_CONFIG PCH_WAKE_CONFIG TCSS_PCIE_PEI_POLICY
_PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI EFI_MMRAM_DESCRIPTOR ISH_PREMEM_CONFIG PCH_WDT_PREMEM_CONFIG TCSS_PCIE_PORT_POLICY
_PEI_SI_DEFAULT_POLICY_INIT_PPI EFI_PEI_HOB_POINTERS ISH_SPI PCIE_COMMON_CONFIG TCSS_PEI_CONFIG
_SI_POLICY_STRUCT EFI_TIME ISH_SPI_PIN_CONFIG PCIE_DEVICE_OVERRIDE TCSS_PEI_PREMEM_CONFIG
_SI_PREMEM_POLICY_STRUCT
f
ISH_UART PCIE_EQ_PARAM TCSS_USBTC_PEI_PERMEM_CONFIG
a
ISH_UART_PIN_CONFIG PCIE_IMR_CONFIG TELEMETRY_PEI_CONFIG
FIVR_EXT_RAIL_CONFIG
m
PCIE_LINK_EQ_PLATFORM_SETTINGS TELEMETRY_PEI_PREMEM_CONFIG
ADR_CONFIG FIVR_VCCIN_AUX_CONFIG PCIE_PREMEM_CONFIG THC_CONFIG
ADR_GLOBAL_RESET_ENABLE FSP_ERROR_INFO_HOB ME_PEI_CONFIG PCIE_RP_DXE_CONFIG THC_HID_OVER_I2C
AMT_DXE_CONFIG FSPM_ARCH_CONFIG_PPI ME_PEI_PREMEM_CONFIG PMC_GLOBAL_RESET_MASK THC_HID_OVER_SPI
AMT_PEI_CONFIG
g
MUX_GPIO_CONFIG PMC_INTERFACE_CONFIG THC_PORT
b
o
PMC_LPM_S0IX_SUB_STATE_EN THC_RESET
GBE_CONFIG PROTECTED_RANGE THERMAL_CONFIG
BCLK_CONFIG GNA_CONFIG OVERCLOCKING_PREMEM_CONFIG
r
THERMAL_THROTTLE_LEVELS
c
GPIO_CONFIG
p
TRACE_HUB_CONFIG
GUID RST_CONFIG TRACE_HUB_PREMEM_CONFIG
CNVI_PIN_MUX
h
PCH_DCI_PREMEM_CONFIG RST_HARDWARE_REMAPPED_STORAGE_CONFIG
u
CNVI_PREMEM_CONFIG PCH_DEVICE_INTERRUPT_CONFIG RTC_CONFIG
d
HDA_LINK_DMIC PCH_DMI_CONFIG
s
UART_PIN_MUX
HDA_LINK_HDA PCH_FIVR_CONFIG USB2_PHY_CONFIG
DMI_HW_WIDTH_CONTROL HDA_LINK_SNDW PCH_FLASH_PROTECTION_CONFIG SA_MISC_PEI_PREMEM_CONFIG USB2_PHY_PARAMETERS
DMI_LANE_CONFIG HDA_LINK_SSP PCH_GENERAL_CONFIG SA_XDCI_IRQ_INT_CONFIG USB2_PORT_CONFIG
e
HDA_VERB_TABLE_HEADER PCH_HSIO_CONFIG SATA_CONFIG USB3_PORT_CONFIG
HDAUDIO_DXE_CONFIG PCH_HSIO_PCIE_LANE_CONFIG SATA_THERMAL_THROTTLING
v
EFI_HOB_CPU HDAUDIO_PREMEM_CONFIG PCH_HSIO_PCIE_PREMEM_CONFIG SERIAL_IO_CONFIG
EFI_HOB_FIRMWARE_VOLUME HSIO_PARAMETERS PCH_HSIO_PREMEM_CONFIG SERIAL_IO_I2C_CONFIG VMD_PEI_CONFIG
EFI_HOB_FIRMWARE_VOLUME2
i
PCH_HSIO_SATA_PORT_LANE SERIAL_IO_I3C_CONFIG VTD_ENGINE_CONFIG
EFI_HOB_FIRMWARE_VOLUME3 PCH_HSIO_SATA_PREMEM_CONFIG SERIAL_IO_SPI_CONFIG
x
EFI_HOB_GENERIC_HEADER I2C_PIN_MUX PCH_INTERRUPT_CONFIG SERIAL_IO_UART_ATTRIBUTES
EFI_HOB_GUID_TYPE IEH_CONFIG PCH_IOAPIC_CONFIG SERIAL_IO_UART_CONFIG XDCI_CONFIG
EFI_HOB_HANDOFF_INFO_TABLE IOM_AUX_ORI_PAD_CONFIG PCH_LPC_PREMEM_CONFIG SI_CONFIG
_ | a | b | c | d | e | f | g | h | i | m | o | p | r | s | t | u | v | x


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented class members with links to the class documentation for each member:

- a -

  • AcpiReservedMemoryBase : SA_MISC_PEI_PREMEM_CONFIG
  • AcpiReservedMemorySize : SA_MISC_PEI_PREMEM_CONFIG
  • AcsEnabled : TCSS_PCIE_PORT_POLICY
  • ActiveLtr : THC_PORT
  • AddressingMode : THC_HID_OVER_I2C
  • AdrEn : ADR_CONFIG
  • AdrHostPartitionReset : ADR_CONFIG
  • AdrMultiplier1Val : ADR_CONFIG
  • AdrMultiplier2Val : ADR_CONFIG
  • AdrPlatAckEn : ADR_CONFIG
  • AdrSrcOff : ADR_CONFIG
  • AdrSrcOn : ADR_CONFIG
  • AdrTimer1Val : ADR_CONFIG
  • AdrTimer2Val : ADR_CONFIG
  • AdrTimerEn : ADR_CONFIG
  • AdvancedErrorReporting : TCSS_PCIE_PORT_POLICY
  • AetEnabled : TRACE_HUB_CONFIG
  • AllocDescriptor : EFI_HOB_MEMORY_ALLOCATION , EFI_HOB_MEMORY_ALLOCATION_BSP_STORE , EFI_HOB_MEMORY_ALLOCATION_STACK
  • AmtEnabled : AMT_PEI_CONFIG
  • AmtReportError : AMT_DXE_CONFIG
  • AmtSolEnabled : AMT_PEI_CONFIG
  • ArpEnable : PCH_SMBUS_PREMEM_CONFIG
  • Aspm : TCSS_PCIE_PORT_POLICY
  • Assignment : THC_PORT
  • AtomClusterRatio : OVERCLOCKING_PREMEM_CONFIG
  • Attributes : _CONFIG_BLOCK_HEADER , SERIAL_IO_UART_CONFIG
  • AudioLinkDmic : HDAUDIO_PREMEM_CONFIG
  • AudioLinkHda : HDAUDIO_PREMEM_CONFIG
  • AudioLinkSndw : HDAUDIO_PREMEM_CONFIG
  • AudioLinkSsp : HDAUDIO_PREMEM_CONFIG
  • AuthenticationStatus : EFI_HOB_FIRMWARE_VOLUME3
  • AutoFlow : SERIAL_IO_UART_ATTRIBUTES
  • AuxOri : TCSS_IOM_ORI_OVERRIDE
  • AvailableSize : _CONFIG_BLOCK_TABLE_STRUCT
  • Avx2RatioOffset : OVERCLOCKING_PREMEM_CONFIG
  • Avx2VoltageScaleFactor : OVERCLOCKING_PREMEM_CONFIG
  • Avx3RatioOffset : OVERCLOCKING_PREMEM_CONFIG
  • Avx512VoltageScaleFactor : OVERCLOCKING_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented class members with links to the class documentation for each member:

- b -

  • BaseAddress : EFI_HOB_FIRMWARE_VOLUME2 , EFI_HOB_FIRMWARE_VOLUME3 , EFI_HOB_FIRMWARE_VOLUME , EFI_HOB_UEFI_CAPSULE
  • BaseClassCode : PCIE_DEVICE_OVERRIDE
  • BaudRate : SERIAL_IO_UART_ATTRIBUTES
  • BclkAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • BdatEnable : SA_MISC_PEI_PREMEM_CONFIG
  • BdatTestType : SA_MISC_PEI_PREMEM_CONFIG
  • Bifurcation : PCH_PCIE_RP_PREMEM_CONFIG
  • BiosInterfaceLock : RTC_CONFIG
  • BiosTraceSink : TRACE_HUB_CONFIG
  • BootMode : EFI_HOB_HANDOFF_INFO_TABLE
  • BypassPhySyncReset : PCH_HSIO_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented class members with links to the class documentation for each member:

- c -

  • C10DynamicThresholdAdjustment : PCH_PM_CONFIG
  • CallerId : FSP_ERROR_INFO_HOB
  • ChipsetInitBinLen : PCH_HSIO_CONFIG
  • ChipsetInitBinPtr : PCH_HSIO_CONFIG
  • ChipsetInitMessage : PCH_HSIO_PREMEM_CONFIG
  • CiraRequest : AMT_DXE_CONFIG
  • CkdAddressTable : SA_MISC_PEI_PREMEM_CONFIG
  • Clk : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • Clkreq : CNVI_PIN_MUX
  • ClkReq : PCH_PCIE_CLOCK
  • ClockGating : PCH_DMI_CONFIG
  • Cm : PCIE_EQ_PARAM
  • ComplianceTestMode : PCIE_COMMON_CONFIG
  • ComputeDieSscEnable : OVERCLOCKING_PREMEM_CONFIG
  • ConnectionSpeed : THC_HID_OVER_I2C
  • Controller : ISH_I3C_CONFIG
  • CoreAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • CoreMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • CoreMinRatio : OVERCLOCKING_PREMEM_CONFIG
  • CorePllCurrentRefTuningOffset : OVERCLOCKING_PREMEM_CONFIG
  • CorePllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • CoreRatioExtensionMode : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfConfigScope : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointCount : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointOffset : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointOffsetMode : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointRatio : OVERCLOCKING_PREMEM_CONFIG
  • CoreVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • CoreVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • CoreVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • CorrectableErrorReport : TCSS_PCIE_PORT_POLICY
  • Cp : PCIE_EQ_PARAM
  • CppmFaEn : PCH_PM_CONFIG
  • CpuAttachedStorage : RST_CONFIG
  • CpuBandgapRefMode : OVERCLOCKING_PREMEM_CONFIG
  • CpuBclkOcFrequency : OVERCLOCKING_PREMEM_CONFIG
  • CpuBclkPllOn : BCLK_CONFIG
  • CpuC10GatePinEnable : PCH_PM_CONFIG
  • CpuCrashLogDevice : TELEMETRY_PEI_PREMEM_CONFIG
  • CpuCrashLogEnable : TELEMETRY_PEI_CONFIG
  • CpuD2dRatio : OVERCLOCKING_PREMEM_CONFIG
  • CpuDlvrMode : OVERCLOCKING_PREMEM_CONFIG
  • CpuSaPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • CpuStart : EFI_MMRAM_DESCRIPTOR
  • Crid : PCH_GENERAL_CONFIG
  • Cs : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • CseDataResilience : ME_PEI_CONFIG
  • CsEnable : ISH_SPI , SERIAL_IO_SPI_CONFIG
  • CsMode : SERIAL_IO_SPI_CONFIG
  • CsPolarity : SERIAL_IO_SPI_CONFIG
  • CsState : SERIAL_IO_SPI_CONFIG
  • CtrlRampTmr : FIVR_EXT_RAIL_CONFIG
  • Cts : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • CustomizedSsid : SI_CONFIG
  • CustomizedSvid : SI_CONFIG
  • CwbEnable : PCH_DMI_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented class members with links to the class documentation for each member:

- d -

  • D3ColdEnable : IOM_INTERFACE_CONFIG
  • D3HotEnable : IOM_INTERFACE_CONFIG
  • DataBits : SERIAL_IO_UART_ATTRIBUTES
  • DataDwords : HDA_VERB_TABLE_HEADER
  • DBG2 : SERIAL_IO_UART_CONFIG
  • DciClkEnable : PCH_DCI_PREMEM_CONFIG
  • DciDbcMode : PCH_DCI_PREMEM_CONFIG
  • DciEn : PCH_DCI_PREMEM_CONFIG
  • DciUsb3TypecUfpDbg : PCH_DCI_PREMEM_CONFIG
  • DdrRfim : CNVI_PREMEM_CONFIG
  • DefaultCsOutput : SERIAL_IO_SPI_CONFIG
  • DefaultPresetEnable : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • DevEnConfig : TCSS_PEI_PREMEM_CONFIG
  • Device : PCH_DEVICE_INTERRUPT_CONFIG
  • DeviceAddress : THC_HID_OVER_I2C
  • DeviceId : HDA_VERB_TABLE_HEADER , PCIE_DEVICE_OVERRIDE
  • DeviceResetDelay : RST_HARDWARE_REMAPPED_STORAGE_CONFIG
  • DevIntConfig : PCH_INTERRUPT_CONFIG
  • DevSlp : PCH_SATA_PORT_CONFIG
  • DevSlpResetConfig : PCH_SATA_PORT_CONFIG
  • DidInitStat : ME_PEI_PREMEM_CONFIG
  • Direction : GPIO_CONFIG
  • DisableAndLock : PCH_WDT_PREMEM_CONFIG
  • DisableCpuReplacedPolling : ME_PEI_PREMEM_CONFIG
  • DisableD0I3SettingForHeci : ME_PEI_CONFIG
  • DisableDsxAcPresentPulldown : PCH_PM_CONFIG
  • DisableEnergyReport : PCH_PM_CONFIG
  • DisableMessageCheck : ME_PEI_PREMEM_CONFIG
  • DisableMrcRetrainingOnRtcPowerLoss : SA_MISC_PEI_PREMEM_CONFIG
  • DisableNativePowerButton : PCH_PM_CONFIG
  • DisablePerCoreMask : OVERCLOCKING_PREMEM_CONFIG
  • DisplayFrameSyncPeriod : THC_PORT
  • DitoVal : PCH_SATA_PORT_CONFIG
  • DmaEnable : SERIAL_IO_UART_CONFIG
  • DmiAspmCtrl : PCH_DMI_CONFIG
  • DmicClockSelect : HDA_LINK_DMIC
  • DmiHaAWC : THERMAL_CONFIG
  • DmiPowerReduction : PCH_DMI_CONFIG
  • DmiTranCoOverEn : DMI_LANE_CONFIG
  • DmiTranCoOverPostCur : DMI_LANE_CONFIG
  • DmiTranCoOverPreCur : DMI_LANE_CONFIG
  • DmiTsawEn : DMI_HW_WIDTH_CONTROL
  • DmiUpPortTranPreset : DMI_LANE_CONFIG
  • DmVal : PCH_SATA_PORT_CONFIG
  • DspEnable : HDAUDIO_PREMEM_CONFIG
  • DspFeatureMask : HDAUDIO_DXE_CONFIG
  • DspUaaCompliance : HDAUDIO_PREMEM_CONFIG
  • DynamicPowerGating : PCH_SMBUS_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented class members with links to the class documentation for each member:

- e -

  • EcoreTvbTempThreshold0 : OVERCLOCKING_PREMEM_CONFIG
  • EcoreTvbTempThreshold1 : OVERCLOCKING_PREMEM_CONFIG
  • EfiEndOfHobList : EFI_HOB_HANDOFF_INFO_TABLE
  • EfiFreeMemoryBottom : EFI_HOB_HANDOFF_INFO_TABLE
  • EfiFreeMemoryTop : EFI_HOB_HANDOFF_INFO_TABLE
  • EfiMemoryBottom : EFI_HOB_HANDOFF_INFO_TABLE
  • EfiMemoryTop : EFI_HOB_HANDOFF_INFO_TABLE
  • ElectricalConfig : GPIO_CONFIG
  • Enable : GBE_CONFIG , HDA_LINK_DMIC , HDA_LINK_HDA , HDA_LINK_SNDW , HDA_LINK_SSP , HDAUDIO_PREMEM_CONFIG , ISH_GP , ISH_I2C , ISH_PREMEM_CONFIG , ISH_SPI , ISH_UART , PCH_SATA_PORT_CONFIG , PCH_SMBUS_PREMEM_CONFIG , RST_HARDWARE_REMAPPED_STORAGE_CONFIG , SATA_CONFIG , USB2_PORT_CONFIG , USB3_PORT_CONFIG , XDCI_CONFIG
  • Enable8254ClockGating : PCH_IOAPIC_CONFIG
  • Enable8254ClockGatingOnS3 : PCH_IOAPIC_CONFIG
  • EnableDitoConfig : PCH_SATA_PORT_CONFIG
  • EnabledStates : FIVR_EXT_RAIL_CONFIG
  • EnableMode : TRACE_HUB_CONFIG
  • EnablePort8xhDecode : PCIE_COMMON_CONFIG
  • EnclosureSupport : SATA_CONFIG
  • EndOfPostMessage : ME_PEI_CONFIG
  • EndPointAspm : PCIE_DEVICE_OVERRIDE
  • EndPointPresetList : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • EnforceEDebugMode : ME_PEI_CONFIG
  • EnhancePort8xhDecoding : PCH_LPC_PREMEM_CONFIG
  • EntryPoint : EFI_HOB_MEMORY_ALLOCATION_MODULE
  • EqPh23Bypass : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • EqPh3Bypass : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • EqPhBypass : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • ErrorType : FSP_ERROR_INFO_HOB
  • EsataSpeedLimit : SATA_CONFIG
  • External : PCH_SATA_PORT_CONFIG
  • ExtractedFv : EFI_HOB_FIRMWARE_VOLUME3
  • ExtSync : PCH_PCIE_ROOT_PORT_CONFIG
  • ExtV1p05Rail : PCH_FIVR_CONFIG
  • ExtVnnRail : PCH_FIVR_CONFIG
  • ExtVnnRailSx : PCH_FIVR_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented class members with links to the class documentation for each member:

- f -

  • FastModePlusSerialClockLineHighPeriod : THC_HID_OVER_I2C
  • FastModePlusSerialClockLineLowPeriod : THC_HID_OVER_I2C
  • FastModePlusSerialDataLineReceiveHoldPeriod : THC_HID_OVER_I2C
  • FastModePlusSerialDataLineTransmitHoldPeriod : THC_HID_OVER_I2C
  • FastModeSerialClockLineHighPeriod : THC_HID_OVER_I2C
  • FastModeSerialClockLineLowPeriod : THC_HID_OVER_I2C
  • FastModeSerialDataLineReceiveHoldPeriod : THC_HID_OVER_I2C
  • FastModeSerialDataLineTransmitHoldPeriod : THC_HID_OVER_I2C
  • FatalErrorReport : TCSS_PCIE_PORT_POLICY
  • FileName : EFI_HOB_FIRMWARE_VOLUME2 , EFI_HOB_FIRMWARE_VOLUME3
  • FivrDynPm : PCH_FIVR_CONFIG
  • Flags : THC_HID_OVER_SPI
  • FllOverclockMode : OVERCLOCKING_PREMEM_CONFIG
  • ForceLtrOverride : PCIE_DEVICE_OVERRIDE , TCSS_PCIE_PORT_POLICY
  • ForcePcoreResidency : OVERCLOCKING_PREMEM_CONFIG
  • Frequency : THC_HID_OVER_SPI
  • Function : PCH_DEVICE_INTERRUPT_CONFIG
  • FvName : EFI_HOB_FIRMWARE_VOLUME2 , EFI_HOB_FIRMWARE_VOLUME3
  • FwProgress : AMT_PEI_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented class members with links to the class documentation for each member:

- g -

  • GlobalResetMasksOverride : PCH_PM_CONFIG
  • GnaEnable : GNA_CONFIG
  • GpioAuxBiasCtrlPdN : IOM_AUX_ORI_PAD_CONFIG
  • GpioAuxBiasCtrlPuP : IOM_AUX_ORI_PAD_CONFIG
  • GpioIrqRoute : PCH_INTERRUPT_CONFIG
  • GpioIsoCtrlPin : IOM_AUX_ORI_PAD_CONFIG
  • GranularRatioOverride : OVERCLOCKING_PREMEM_CONFIG
  • GtAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • GtIccUnlimitedMode : OVERCLOCKING_PREMEM_CONFIG
  • GtMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • GtVfPointCount : OVERCLOCKING_PREMEM_CONFIG
  • GtVfPointOffset : OVERCLOCKING_PREMEM_CONFIG
  • GtVfPointOffsetMode : OVERCLOCKING_PREMEM_CONFIG
  • GtVfPointRatio : OVERCLOCKING_PREMEM_CONFIG
  • GtVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • GtVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • GtVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • GuidHob : _CONFIG_BLOCK_HEADER , FSP_ERROR_INFO_HOB


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented class members with links to the class documentation for each member:

- h -

  • HapcsSearchEnable : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • HardwareRemappedStorageConfig : RST_CONFIG
  • HdaDiscBtOffload : HDAUDIO_DXE_CONFIG , HDAUDIO_PREMEM_CONFIG
  • HddUnlock : RST_CONFIG
  • Header : _CONFIG_BLOCK , _CONFIG_BLOCK_TABLE_STRUCT , ADR_CONFIG , AMT_DXE_CONFIG , AMT_PEI_CONFIG , BCLK_CONFIG , CNVI_PREMEM_CONFIG , EFI_HOB_CPU , EFI_HOB_FIRMWARE_VOLUME2 , EFI_HOB_FIRMWARE_VOLUME3 , EFI_HOB_FIRMWARE_VOLUME , EFI_HOB_GUID_TYPE , EFI_HOB_HANDOFF_INFO_TABLE , EFI_HOB_MEMORY_ALLOCATION , EFI_HOB_MEMORY_ALLOCATION_BSP_STORE , EFI_HOB_MEMORY_ALLOCATION_MODULE , EFI_HOB_MEMORY_ALLOCATION_STACK , EFI_HOB_MEMORY_POOL , EFI_HOB_RESOURCE_DESCRIPTOR , EFI_HOB_UEFI_CAPSULE , GBE_CONFIG , GNA_CONFIG , HDAUDIO_DXE_CONFIG , HDAUDIO_PREMEM_CONFIG , IEH_CONFIG , ISH_CONFIG , ISH_I3C_CONFIG , ISH_PREMEM_CONFIG , ME_PEI_CONFIG , ME_PEI_PREMEM_CONFIG , OVERCLOCKING_PREMEM_CONFIG , PCH_DCI_PREMEM_CONFIG , PCH_DMI_CONFIG , PCH_FIVR_CONFIG , PCH_FLASH_PROTECTION_CONFIG , PCH_GENERAL_CONFIG , PCH_HSIO_CONFIG , PCH_HSIO_PCIE_PREMEM_CONFIG , PCH_HSIO_PREMEM_CONFIG , PCH_HSIO_SATA_PREMEM_CONFIG , PCH_INTERRUPT_CONFIG , PCH_IOAPIC_CONFIG , PCH_LPC_PREMEM_CONFIG , PCH_P2SB_CONFIG , PCH_PCIE_CONFIG , PCH_PCIE_RP_PREMEM_CONFIG , PCH_PM_CONFIG , PCH_SMBUS_PREMEM_CONFIG , PCH_TRACE_HUB_PREMEM_CONFIG , PCH_WDT_PREMEM_CONFIG , PCIE_PREMEM_CONFIG , PCIE_RP_DXE_CONFIG , RST_CONFIG , RTC_CONFIG , SA_MISC_PEI_PREMEM_CONFIG , SATA_CONFIG , SERIAL_IO_CONFIG , SI_CONFIG , SI_PREMEM_CONFIG , TCSS_PEI_CONFIG , TCSS_PEI_PREMEM_CONFIG , THC_CONFIG , THERMAL_CONFIG , TRACE_HUB_PREMEM_CONFIG , USB2_PHY_CONFIG , VMD_PEI_CONFIG
  • HeciCommunication2 : ME_PEI_PREMEM_CONFIG
  • HeciFullTrace : ME_PEI_PREMEM_CONFIG
  • HeciTimeouts : ME_PEI_PREMEM_CONFIG
  • HidOverI2c : THC_PORT
  • HidOverSpi : THC_PORT
  • HighSpeedModePlusSerialClockLineHighPeriod : THC_HID_OVER_I2C
  • HighSpeedModePlusSerialClockLineLowPeriod : THC_HID_OVER_I2C
  • HighSpeedModePlusSerialDataLineReceiveHoldPeriod : THC_HID_OVER_I2C
  • HighSpeedModePlusSerialDataLineTransmitHoldPeriod : THC_HID_OVER_I2C
  • HintList : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • HobLength : EFI_HOB_GENERIC_HEADER
  • HobType : EFI_HOB_GENERIC_HEADER
  • HostSoftPadOwn : GPIO_CONFIG
  • HotPlug : PCH_SATA_PORT_CONFIG
  • HsioCtrlAdaptOffsetCfg : HSIO_PARAMETERS
  • HsioCtrlAdaptOffsetCfgEnable : HSIO_PARAMETERS
  • HsioFilterSelN : HSIO_PARAMETERS
  • HsioFilterSelNEnable : HSIO_PARAMETERS
  • HsioFilterSelP : HSIO_PARAMETERS
  • HsioFilterSelPEnable : HSIO_PARAMETERS
  • HsioOlfpsCfgPullUpDwnRes : HSIO_PARAMETERS
  • HsioOlfpsCfgPullUpDwnResEnable : HSIO_PARAMETERS
  • HsioRxGen1EqBoostMag : PCH_HSIO_SATA_PORT_LANE
  • HsioRxGen1EqBoostMagEnable : PCH_HSIO_SATA_PORT_LANE
  • HsioRxGen2EqBoostMag : PCH_HSIO_SATA_PORT_LANE
  • HsioRxGen2EqBoostMagEnable : PCH_HSIO_SATA_PORT_LANE
  • HsioRxGen3EqBoostMag : PCH_HSIO_SATA_PORT_LANE
  • HsioRxGen3EqBoostMagEnable : PCH_HSIO_SATA_PORT_LANE
  • HsioRxSetCtle : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioRxSetCtleEnable : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioTxDeEmph : HSIO_PARAMETERS
  • HsioTxDeEmphEnable : HSIO_PARAMETERS
  • HsioTxDownscaleAmp : HSIO_PARAMETERS
  • HsioTxDownscaleAmpEnable : HSIO_PARAMETERS
  • HsioTxGen1DeEmph : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen1DeEmphEnable : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen1DownscaleAmp : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen1DownscaleAmpEnable : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen2DeEmph : PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen2DeEmph3p5 : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioTxGen2DeEmph3p5Enable : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioTxGen2DeEmph6p0 : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioTxGen2DeEmph6p0Enable : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioTxGen2DeEmphEnable : PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen2DownscaleAmp : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen2DownscaleAmpEnable : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen3DeEmph : PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen3DeEmphEnable : PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen3DownscaleAmp : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen3DownscaleAmpEnable : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxRate0UniqTran : HSIO_PARAMETERS
  • HsioTxRate0UniqTranEnable : HSIO_PARAMETERS
  • HsioTxRate1UniqTran : HSIO_PARAMETERS
  • HsioTxRate1UniqTranEnable : HSIO_PARAMETERS
  • HsioTxRate2UniqTran : HSIO_PARAMETERS
  • HsioTxRate2UniqTranEnable : HSIO_PARAMETERS
  • HsioTxRate3UniqTran : HSIO_PARAMETERS
  • HsioTxRate3UniqTranEnable : HSIO_PARAMETERS
  • HslOri : TCSS_IOM_ORI_OVERRIDE


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented class members with links to the class documentation for each member:

- i -

  • I2cDeviceConfig : SERIAL_IO_CONFIG
  • I3cDeviceConfig : SERIAL_IO_CONFIG
  • IaAtomPllCurrentRefTuningOffset : OVERCLOCKING_PREMEM_CONFIG
  • IaAtomPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • IaIccMax : OVERCLOCKING_PREMEM_CONFIG
  • IaIccUnlimitedMode : OVERCLOCKING_PREMEM_CONFIG
  • IccMaximum : FIVR_EXT_RAIL_CONFIG
  • IDispCodecDisconnect : HDAUDIO_PREMEM_CONFIG
  • IDispLinkFrequency : HDAUDIO_PREMEM_CONFIG
  • IDispLinkTmode : HDAUDIO_PREMEM_CONFIG
  • IdleLtr : THC_PORT
  • ImguClkOutEn : IPU_PREMEM_CONFIG
  • ImrEnabled : PCIE_IMR_CONFIG
  • ImrRpLocation : PCIE_IMR_CONFIG
  • ImrRpSelection : PCIE_IMR_CONFIG
  • ImrSize : PCIE_IMR_CONFIG
  • InputReportBodyAddress : THC_HID_OVER_SPI
  • InputReportHeaderAddress : THC_HID_OVER_SPI
  • Instance : FSP_ERROR_INFO_HOB
  • InterlockSw : PCH_SATA_PORT_CONFIG
  • InterruptConfig : GPIO_CONFIG
  • InterruptPinMuxing : THC_PORT
  • IntPing : SA_XDCI_IRQ_INT_CONFIG
  • IntX : PCH_DEVICE_INTERRUPT_CONFIG
  • IoApicEntry24_119 : PCH_IOAPIC_CONFIG
  • IoApicId : PCH_IOAPIC_CONFIG
  • IomAuxPortPad : TCSS_IOM_PEI_CONFIG
  • IomConfig : TCSS_PEI_CONFIG
  • IomInterface : TCSS_IOM_PEI_CONFIG
  • IpuEnable : IPU_PREMEM_CONFIG
  • Irq : PCH_DEVICE_INTERRUPT_CONFIG , SA_XDCI_IRQ_INT_CONFIG
  • Irrt : RST_CONFIG
  • IrrtOnly : RST_CONFIG
  • ITbtConnectTopologyTimeoutInMs : _ITBT_GENERIC_CONFIG
  • ITbtForcePowerOnTimeoutInMs : _ITBT_GENERIC_CONFIG
  • ITbtPcieRootPortEn : _ITBT_ROOTPORT_CONFIG
  • ITbtPcieTunnelingForUsb4 : _ITBT_GENERIC_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented class members with links to the class documentation for each member:

- k -

  • KeepEarlyTrace : PCH_DCI_PREMEM_CONFIG
  • KtDeviceEnable : ME_PEI_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented class members with links to the class documentation for each member:

- l -

  • L1RpCtl : PCH_DMI_CONFIG
  • L1sCommonModeRestoreTime : PCIE_DEVICE_OVERRIDE
  • L1sTpowerOnScale : PCIE_DEVICE_OVERRIDE
  • L1sTpowerOnValue : PCIE_DEVICE_OVERRIDE
  • L1SubstatesCapMask : PCIE_DEVICE_OVERRIDE
  • L1SubstatesCapOffset : PCIE_DEVICE_OVERRIDE
  • Lane : PCH_HSIO_PCIE_PREMEM_CONFIG
  • LanWakeFromDeepSx : PCH_WAKE_CONFIG
  • LatchEventsC10Exit : PCH_PM_CONFIG
  • LedEnable : SATA_CONFIG
  • LedLocate : RST_CONFIG
  • LegacyIoLowLatency : PCH_GENERAL_CONFIG
  • LegacyOrom : RST_CONFIG
  • Length : EFI_HOB_FIRMWARE_VOLUME2 , EFI_HOB_FIRMWARE_VOLUME3 , EFI_HOB_FIRMWARE_VOLUME
  • LimitPacketSize : THC_HID_OVER_SPI
  • LocalTxOverrideEn : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • LockConfig : GPIO_CONFIG
  • LockPTMregs : SA_MISC_PEI_PREMEM_CONFIG
  • LowToHighCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • LpcPmHAE : PCH_LPC_PREMEM_CONFIG
  • LpmS0ixSubStateEnable : PCH_PM_CONFIG
  • LtrConfigLock : TCSS_PCIE_PORT_POLICY
  • LtrEnable : GBE_CONFIG , TCSS_PCIE_PORT_POLICY
  • LtrMaxNoSnoopLatency : TCSS_PCIE_PORT_POLICY
  • LtrMaxSnoopLatency : TCSS_PCIE_PORT_POLICY


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented class members with links to the class documentation for each member:

- m -

  • MaximumLengthOfSuppressedSpikesInHighSpeedMode : THC_HID_OVER_I2C
  • MaxSuppressedSpikesSMFMFMP : THC_HID_OVER_I2C
  • MaxVoltageLimit : OVERCLOCKING_PREMEM_CONFIG
  • McPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • MctpBroadcastCycle : ME_PEI_CONFIG
  • MemoryAllocationHeader : EFI_HOB_MEMORY_ALLOCATION_MODULE
  • MemoryBaseAddress : EFI_HOB_MEMORY_ALLOCATION_HEADER
  • MemoryLength : EFI_HOB_MEMORY_ALLOCATION_HEADER
  • MemoryLock : RTC_CONFIG
  • MemoryType : EFI_HOB_MEMORY_ALLOCATION_HEADER
  • MemReg0Size : TRACE_HUB_CONFIG
  • MemSSAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • MemSSMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • MemSSVfPointCount : OVERCLOCKING_PREMEM_CONFIG
  • MemSSVfPointOffset : OVERCLOCKING_PREMEM_CONFIG
  • MemSSVfPointOffsetMode : OVERCLOCKING_PREMEM_CONFIG
  • MemSSVfPointRatio : OVERCLOCKING_PREMEM_CONFIG
  • MemSSVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • MemSSVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • MemSSVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • MeUnconfigOnRtcClear : ME_PEI_CONFIG
  • MeWakeSts : PCH_PM_CONFIG
  • MiscConfig : TCSS_PEI_CONFIG
  • Miso : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • MmramReservedSize : _EFI_MM_RESERVED_MMRAM_REGION
  • MmramReservedStart : _EFI_MM_RESERVED_MMRAM_REGION
  • Mode : IEH_CONFIG , SERIAL_IO_I3C_CONFIG , SERIAL_IO_SPI_CONFIG , SERIAL_IO_UART_CONFIG , THC_PORT
  • ModPhySusPgEnable : PCH_PM_CONFIG
  • ModuleName : EFI_HOB_MEMORY_ALLOCATION_MODULE
  • Mosi : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • MrcMustStaticSpdData : SA_MISC_PEI_PREMEM_CONFIG
  • MsiInterrupt : ISH_CONFIG
  • MvcEnabled : PCH_PCIE_ROOT_PORT_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented class members with links to the class documentation for each member:

- n -

  • Name : EFI_HOB_GUID_TYPE , EFI_HOB_MEMORY_ALLOCATION_HEADER
  • NclkTurboThermalProtection : OVERCLOCKING_PREMEM_CONFIG
  • NguAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • NguMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • NguRatio : OVERCLOCKING_PREMEM_CONFIG
  • NguVfPointCount : OVERCLOCKING_PREMEM_CONFIG
  • NguVfPointOffset : OVERCLOCKING_PREMEM_CONFIG
  • NguVfPointOffsetMode : OVERCLOCKING_PREMEM_CONFIG
  • NguVfPointRatio : OVERCLOCKING_PREMEM_CONFIG
  • NguVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • NguVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • NoFatalErrorReport : TCSS_PCIE_PORT_POLICY
  • NonSnoopLatency : PCIE_DEVICE_OVERRIDE
  • NonSnoopLatencyOverrideMode : TCSS_PCIE_PORT_POLICY
  • NonSnoopLatencyOverrideMultiplier : TCSS_PCIE_PORT_POLICY
  • NonSnoopLatencyOverrideValue : TCSS_PCIE_PORT_POLICY
  • NphyBinLen : PCH_HSIO_CONFIG
  • NphyBinPtr : PCH_HSIO_CONFIG
  • NpuAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • NpuMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • NpuVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • NpuVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • NpuVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • NumberOfBlocks : _CONFIG_BLOCK_TABLE_STRUCT
  • NumberOfSsidTableEntry : SI_CONFIG
  • NumOfDevIntConfig : PCH_INTERRUPT_CONFIG
  • NumRsvdSmbusAddresses : PCH_SMBUS_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented class members with links to the class documentation for each member:

- o -

  • OcSupport : OVERCLOCKING_PREMEM_CONFIG
  • OcTvb : OVERCLOCKING_PREMEM_CONFIG
  • OfflineCrashDumpEnable : SA_MISC_PEI_PREMEM_CONFIG
  • OffToHighCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • OpRomScanTempMmioBar : SA_MISC_PEI_PREMEM_CONFIG
  • OpRomScanTempMmioLimit : SA_MISC_PEI_PREMEM_CONFIG
  • OptaneMemory : RST_CONFIG
  • OromUiBanner : RST_CONFIG
  • OromUiDelay : RST_CONFIG
  • OsIdleEnable : PCH_PM_CONFIG
  • OtherSettings : GPIO_CONFIG
  • OutputReportAddress : THC_HID_OVER_SPI
  • OutputState : GPIO_CONFIG
  • OverCurrentPin : USB2_PORT_CONFIG , USB3_PORT_CONFIG
  • OverrideConfig : PCIE_DEVICE_OVERRIDE
  • Owner : EFI_HOB_RESOURCE_DESCRIPTOR


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented class members with links to the class documentation for each member:

- p -

  • P0T1M : SATA_THERMAL_THROTTLING
  • P0T2M : SATA_THERMAL_THROTTLING
  • P0T3M : SATA_THERMAL_THROTTLING
  • P0TDisp : SATA_THERMAL_THROTTLING
  • P0TDispFinit : SATA_THERMAL_THROTTLING
  • P0Tinact : SATA_THERMAL_THROTTLING
  • P1T1M : SATA_THERMAL_THROTTLING
  • P1T2M : SATA_THERMAL_THROTTLING
  • P1T3M : SATA_THERMAL_THROTTLING
  • P1TDisp : SATA_THERMAL_THROTTLING
  • P1TDispFinit : SATA_THERMAL_THROTTLING
  • P1Tinact : SATA_THERMAL_THROTTLING
  • PadMode : GPIO_CONFIG
  • PadTermination : ISH_GPIO_CONFIG , MUX_GPIO_CONFIG , SERIAL_IO_I2C_CONFIG
  • Parity : SERIAL_IO_UART_ATTRIBUTES
  • PCETTimer : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PchDeepSxPol : PCH_PM_CONFIG
  • PchHotEnable : THERMAL_CONFIG
  • PchHotLevel : THERMAL_CONFIG
  • PchPciePort8xhDecodePortIndex : PCH_PCIE_CONFIG
  • PchPwrCycDur : PCH_PM_CONFIG
  • PchSlpAMinAssert : PCH_PM_CONFIG
  • PchSlpS3MinAssert : PCH_PM_CONFIG
  • PchSlpS4MinAssert : PCH_PM_CONFIG
  • PchSlpSusMinAssert : PCH_PM_CONFIG
  • PchWOLFastSupport : GBE_CONFIG
  • PcieClock : PCH_PCIE_RP_PREMEM_CONFIG
  • PcieCommonConfig : PCH_PCIE_CONFIG
  • PcieDeviceOverrideTablePtr : PCIE_RP_DXE_CONFIG
  • PcieImr : PCIE_PREMEM_CONFIG
  • PcieLinkEqMethod : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PcieLinkEqMode : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PciePllSsc : PCH_PM_CONFIG
  • PciePolicy : TCSS_PEI_CONFIG
  • PcieWakeFromDeepSx : PCH_WAKE_CONFIG
  • PcorePowerDensityThrottle : OVERCLOCKING_PREMEM_CONFIG
  • PcoreTvbTempThreshold0 : OVERCLOCKING_PREMEM_CONFIG
  • PcoreTvbTempThreshold1 : OVERCLOCKING_PREMEM_CONFIG
  • PdtUnlock : ISH_CONFIG
  • Pehalfbit : USB2_PHY_PARAMETERS
  • PeiPolicyInit : _PEI_SI_DEFAULT_POLICY_INIT_PPI
  • PeiPreMemPolicyInit : _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI
  • PerAtomClusterAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • PerAtomClusterMaxRatio : OVERCLOCKING_PREMEM_CONFIG
  • PerAtomClusterVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • PerAtomClusterVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreDisableConfiguration : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreGranularityBins : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreHtDisable : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreMaxRatio : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreRatioOverride : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • PerEcoreCcpRatioDownBinAboveT0 : OVERCLOCKING_PREMEM_CONFIG
  • PerEcoreCcpRatioDownBinAboveT1 : OVERCLOCKING_PREMEM_CONFIG
  • PerformanceLimitation : THC_PORT
  • PerPcoreGrRatioDownBinAboveT0 : OVERCLOCKING_PREMEM_CONFIG
  • PerPcoreGrRatioDownBinAboveT1 : OVERCLOCKING_PREMEM_CONFIG
  • PerPcoreRatioDownBinAboveT0 : OVERCLOCKING_PREMEM_CONFIG
  • PerPcoreRatioDownBinAboveT1 : OVERCLOCKING_PREMEM_CONFIG
  • Petxiset : USB2_PHY_PARAMETERS
  • Ph1DpTxPreset : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph1UpTxPreset : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph2LocalTxOverridePreset : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph3CoefficientsList : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph3NoOfPresetOrCoeff : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph3PresetList : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PhysicalSize : EFI_MMRAM_DESCRIPTOR
  • PhysicalStart : EFI_HOB_RESOURCE_DESCRIPTOR , EFI_MMRAM_DESCRIPTOR
  • PinMux : HDA_LINK_DMIC , ISH_GPIO_CONFIG , SERIAL_IO_I2C_CONFIG , SERIAL_IO_SPI_CONFIG , SERIAL_IO_UART_CONFIG
  • PlatformAtxTelemetryUnit : PCH_PM_CONFIG
  • PlatformDebugOption : SI_PREMEM_CONFIG
  • PmcDbgMsgEn : PCH_PM_CONFIG
  • PmcInterface : TCSS_IOM_PEI_CONFIG
  • PmcPdEnable : PMC_INTERFACE_CONFIG
  • PmcWdtTimerEn : PCH_PM_CONFIG
  • PmeB0S5Dis : PCH_WAKE_CONFIG
  • PmErDebugMode : PCH_PM_CONFIG
  • Port : USB2_PHY_CONFIG
  • PortLane : PCH_HSIO_SATA_PREMEM_CONFIG
  • PortResetMessageEnable : USB2_PORT_CONFIG
  • PortSettings : SATA_CONFIG
  • PowerConfig : GPIO_CONFIG
  • PowerGating : SERIAL_IO_UART_CONFIG
  • PowerGatingSupported : HDAUDIO_PREMEM_CONFIG
  • Predeemp : USB2_PHY_PARAMETERS
  • PredeempSemiflexEn : USB2_PHY_PARAMETERS
  • ProcessVmaxLimit : OVERCLOCKING_PREMEM_CONFIG
  • ProtectedRangeBase : PROTECTED_RANGE
  • ProtectedRangeLimit : PROTECTED_RANGE
  • ProtectRange : PCH_FLASH_PROTECTION_CONFIG
  • PsOnEnable : PCH_PM_CONFIG
  • PtmEnabled : TCSS_PCIE_PORT_POLICY
  • PvdMode : OVERCLOCKING_PREMEM_CONFIG
  • PvdRatioThreshold : OVERCLOCKING_PREMEM_CONFIG
  • PwrBtnOverridePeriod : PCH_PM_CONFIG
  • PwrOptEnable : PCH_DMI_CONFIG , SATA_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented class members with links to the class documentation for each member:

- r -

  • Raid0 : RST_CONFIG
  • Raid1 : RST_CONFIG
  • Raid10 : RST_CONFIG
  • Raid5 : RST_CONFIG
  • RaidDeviceId : SATA_CONFIG
  • ReadOpcode : THC_HID_OVER_SPI
  • ReadProtectionEnable : PROTECTED_RANGE
  • RealtimeMemoryTiming : OVERCLOCKING_PREMEM_CONFIG
  • RegionState : EFI_MMRAM_DESCRIPTOR
  • RemotePresetCoeffoverride : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Reserved : _CONFIG_BLOCK_HEADER , _ITBT_GENERIC_CONFIG , _ITBT_ROOTPORT_CONFIG , EFI_HOB_CPU , EFI_HOB_GENERIC_HEADER , EFI_HOB_MEMORY_ALLOCATION_HEADER , HDA_LINK_HDA , PMC_LPM_S0IX_SUB_STATE_EN , SERIAL_IO_I3C_CONFIG , TCSS_IOM_PEI_CONFIG , TCSS_MISC_PEI_CONFIG , TCSS_PCIE_PEI_POLICY , THC_PORT , TRACE_HUB_CONFIG
  • Reserved1 : SA_MISC_PEI_PREMEM_CONFIG
  • Reserved2 : _ITBT_GENERIC_CONFIG
  • Reset : THC_PORT
  • ResetPad : THC_RESET
  • ResetPadTrigger : THC_RESET
  • ResetSequencingDelay : THC_RESET
  • ResetWaitTimer : HDAUDIO_PREMEM_CONFIG
  • ResourceAttribute : EFI_HOB_RESOURCE_DESCRIPTOR
  • ResourceLength : EFI_HOB_RESOURCE_DESCRIPTOR
  • ResourceType : EFI_HOB_RESOURCE_DESCRIPTOR
  • RetToHighCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • RetToLowCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • RevId : PCIE_DEVICE_OVERRIDE
  • Revision : _CONFIG_BLOCK_HEADER
  • RevisionId : HDA_VERB_TABLE_HEADER
  • RfReset : CNVI_PIN_MUX
  • RingAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • RingDownBin : OVERCLOCKING_PREMEM_CONFIG
  • RingMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • RingPllCurrentRefTuningOffset : OVERCLOCKING_PREMEM_CONFIG
  • RingPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • RingTurboThermalProtection : OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointCount : OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointOffset : OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointOffsetMode : OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointRatio : OVERCLOCKING_PREMEM_CONFIG
  • RingVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • RingVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • RingVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • RpEnabledMask : PCH_PCIE_RP_PREMEM_CONFIG
  • RpFunctionSwap : PCIE_COMMON_CONFIG
  • RstPcieStoragePort : RST_HARDWARE_REMAPPED_STORAGE_CONFIG
  • Rsvd : IPU_PREMEM_CONFIG , SA_MISC_PEI_PREMEM_CONFIG , TCSS_USBTC_PEI_PERMEM_CONFIG , VMD_PEI_CONFIG
  • Rsvd0 : _CONFIG_BLOCK_TABLE_STRUCT , HDAUDIO_PREMEM_CONFIG , PCH_INTERRUPT_CONFIG , PCH_IOAPIC_CONFIG , PCH_PM_CONFIG , PCH_SMBUS_PREMEM_CONFIG , PCIE_EQ_PARAM , THERMAL_THROTTLE_LEVELS
  • Rsvd1 : DMI_LANE_CONFIG , PCH_PM_CONFIG
  • Rsvd2 : DMI_LANE_CONFIG
  • Rsvd3 : DMI_LANE_CONFIG , SA_MISC_PEI_PREMEM_CONFIG
  • Rsvd4 : DMI_LANE_CONFIG , SA_MISC_PEI_PREMEM_CONFIG
  • RsvdBits : AMT_DXE_CONFIG , AMT_PEI_CONFIG , GPIO_CONFIG , HDAUDIO_PREMEM_CONFIG , ME_PEI_CONFIG , ME_PEI_PREMEM_CONFIG
  • Rsvdbits : PCH_DMI_CONFIG
  • RsvdBits : PCH_LPC_PREMEM_CONFIG
  • Rsvdbits : PCH_P2SB_CONFIG
  • RsvdBits : PROTECTED_RANGE , SI_PREMEM_CONFIG
  • RsvdBits0 : DMI_HW_WIDTH_CONTROL , GBE_CONFIG , GNA_CONFIG , IEH_CONFIG , ISH_CONFIG , ISH_GP , ISH_I2C , ISH_PREMEM_CONFIG , ISH_UART , PCH_GENERAL_CONFIG , PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE , PCH_SATA_PORT_CONFIG , PCH_SMBUS_PREMEM_CONFIG , PCIE_COMMON_CONFIG , RST_CONFIG , RST_HARDWARE_REMAPPED_STORAGE_CONFIG , SA_MISC_PEI_PREMEM_CONFIG , SATA_THERMAL_THROTTLING , THERMAL_THROTTLE_LEVELS , USB2_PORT_CONFIG , USB3_PORT_CONFIG , XDCI_CONFIG
  • RsvdBits1 : DMI_HW_WIDTH_CONTROL , FIVR_EXT_RAIL_CONFIG , OVERCLOCKING_PREMEM_CONFIG , PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE , PCH_IOAPIC_CONFIG
  • RsvdBits2 : FIVR_EXT_RAIL_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • RsvdBytes : PCH_PCIE_CLOCK , SI_PREMEM_CONFIG
  • RsvdBytes0 : PCH_PCIE_ROOT_PORT_CONFIG , SI_CONFIG
  • RsvdBytes1 : SI_CONFIG
  • RsvdBytes2 : SI_CONFIG
  • RsvdField0 : ISH_SPI
  • RsvdSmbusAddressTable : PCH_SMBUS_PREMEM_CONFIG
  • Rts : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • Rx : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • RxPolarity : PCH_SATA_PORT_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented class members with links to the class documentation for each member:

- s -

  • S0i2p0En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i2p1En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i2p2En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p0En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p1En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p2En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p3En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p4En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0ixAutoDemotion : PCH_PM_CONFIG
  • S3DataPtr : SA_MISC_PEI_PREMEM_CONFIG
  • SaAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • SaIccUnlimitedMode : OVERCLOCKING_PREMEM_CONFIG
  • SalpSupport : SATA_CONFIG
  • SaPllFreqOverride : OVERCLOCKING_PREMEM_CONFIG
  • SaPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • SataMode : SATA_CONFIG
  • SataRstInterrupt : SATA_CONFIG
  • SaVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • SaVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • SaVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • SaXdci : TCSS_MISC_PEI_CONFIG
  • SbAccessUnlock : PCH_P2SB_CONFIG
  • ScanExtGfxForLegacyOpRom : SA_MISC_PEI_PREMEM_CONFIG
  • SciIrqSelect : PCH_INTERRUPT_CONFIG
  • Scl : I2C_PIN_MUX , ISH_I2C_PIN_CONFIG
  • Sda : I2C_PIN_MUX , ISH_I2C_PIN_CONFIG
  • SdiEnable : HDA_LINK_HDA
  • SdiNum : HDA_VERB_TABLE_HEADER
  • SgpioSupport : SATA_CONFIG
  • SizeOfIoSpace : EFI_HOB_CPU
  • SizeOfMemorySpace : EFI_HOB_CPU
  • SkipBiosDoneWhenFwUpdate : SI_CONFIG
  • SkipCpuReplacementCheck : ME_PEI_PREMEM_CONFIG
  • SkipExtGfxScan : SA_MISC_PEI_PREMEM_CONFIG
  • SkipMbpHob : ME_PEI_PREMEM_CONFIG
  • SkipOverrideBootModeWhenFwUpdate : SI_PREMEM_CONFIG
  • SkipSsidProgramming : SI_CONFIG
  • SlotNumber : TCSS_PCIE_PORT_POLICY
  • SlotPowerLimitScale : TCSS_PCIE_PORT_POLICY
  • SlotPowerLimitValue : TCSS_PCIE_PORT_POLICY
  • SlpLanLowDc : PCH_PM_CONFIG
  • SlpStrchSusUp : PCH_PM_CONFIG
  • SmartStorage : RST_CONFIG
  • SmbAlertEnable : PCH_SMBUS_PREMEM_CONFIG
  • SmbusBar : SA_MISC_PEI_PREMEM_CONFIG
  • SmbusIoBase : PCH_SMBUS_PREMEM_CONFIG
  • SndwConfig : HDAUDIO_DXE_CONFIG
  • SndwMultilaneEnable : HDAUDIO_PREMEM_CONFIG
  • SnoopLatency : PCIE_DEVICE_OVERRIDE
  • SnoopLatencyOverrideMode : TCSS_PCIE_PORT_POLICY
  • SnoopLatencyOverrideMultiplier : TCSS_PCIE_PORT_POLICY
  • SnoopLatencyOverrideValue : TCSS_PCIE_PORT_POLICY
  • SocBclkOcFrequency : OVERCLOCKING_PREMEM_CONFIG
  • SocBclkPllOn : BCLK_CONFIG
  • SocDieSscEnable : OVERCLOCKING_PREMEM_CONFIG
  • SolidStateDrive : PCH_SATA_PORT_CONFIG
  • SpdAddressTable : SA_MISC_PEI_PREMEM_CONFIG
  • SpdWriteDisable : PCH_SMBUS_PREMEM_CONFIG
  • SpeedLimit : SATA_CONFIG
  • SpiDeviceConfig : SERIAL_IO_CONFIG
  • SpinUp : PCH_SATA_PORT_CONFIG
  • SsidTablePtr : SI_CONFIG
  • StandardModeSerialClockLineHighPeriod : THC_HID_OVER_I2C
  • StandardModeSerialClockLineLowPeriod : THC_HID_OVER_I2C
  • StandardModeSerialDataLineReceiveHoldPeriod : THC_HID_OVER_I2C
  • StandardModeSerialDataLineTransmitHoldPeriod : THC_HID_OVER_I2C
  • Status : FSP_ERROR_INFO_HOB
  • StopBits : SERIAL_IO_UART_ATTRIBUTES
  • SubClassCode : PCIE_DEVICE_OVERRIDE
  • SubSystemIds : HDAUDIO_PREMEM_CONFIG
  • SuggestedSetting : DMI_HW_WIDTH_CONTROL , SATA_THERMAL_THROTTLING , THERMAL_THROTTLE_LEVELS
  • SupportedVoltageStates : FIVR_EXT_RAIL_CONFIG
  • SwDeviceModeEnable : USB2_PORT_CONFIG
  • SynpsPhyBinLen : PCH_HSIO_CONFIG
  • SynpsPhyBinPtr : PCH_HSIO_CONFIG
  • SystemErrorEnable : PCH_PCIE_ROOT_PORT_CONFIG
  • SystemErrorOnCorrectableError : TCSS_PCIE_PORT_POLICY
  • SystemErrorOnFatalError : TCSS_PCIE_PORT_POLICY
  • SystemErrorOnNonFatalError : TCSS_PCIE_PORT_POLICY
  • SystemMemoryLength : SA_MISC_PEI_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented class members with links to the class documentation for each member:

- t -

  • T0Level : THERMAL_THROTTLE_LEVELS
  • T1Level : THERMAL_THROTTLE_LEVELS
  • T2Level : THERMAL_THROTTLE_LEVELS
  • TableHeader : _SI_POLICY_STRUCT , _SI_PREMEM_POLICY_STRUCT
  • TcNotifyIgd : TCSS_IOM_PEI_CONFIG
  • TcoIrqEnable : PCH_INTERRUPT_CONFIG
  • TcoIrqSelect : PCH_INTERRUPT_CONFIG
  • TcssConvTypeA : TCSS_MISC_PEI_CONFIG
  • TcssDevEn : TCSS_DEVEN_PEI_PREMEM_CONFIG
  • TcStateLimit : TCSS_IOM_PEI_CONFIG
  • TestMode : SATA_CONFIG
  • ThcPort : THC_CONFIG
  • ThermalThrottling : SATA_CONFIG
  • ThermTimerDelay : PCH_PM_CONFIG
  • TimestampTimerMode : THC_PORT
  • TjMaxOffset : OVERCLOCKING_PREMEM_CONFIG
  • TraceHub : PCH_TRACE_HUB_PREMEM_CONFIG , TRACE_HUB_PREMEM_CONFIG
  • TS0TW : DMI_HW_WIDTH_CONTROL
  • TS1TW : DMI_HW_WIDTH_CONTROL
  • TS2TW : DMI_HW_WIDTH_CONTROL
  • TS3TW : DMI_HW_WIDTH_CONTROL
  • TscDisableHwFixup : OVERCLOCKING_PREMEM_CONFIG
  • TsegSize : SA_MISC_PEI_PREMEM_CONFIG
  • TsLockTimer : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • TTEnable : THERMAL_THROTTLE_LEVELS
  • TTLevels : THERMAL_CONFIG
  • TTLock : THERMAL_THROTTLE_LEVELS
  • TTState13Enable : THERMAL_THROTTLE_LEVELS
  • TurboThermalProtection : OVERCLOCKING_PREMEM_CONFIG
  • TvbConfigLimitSelect : OVERCLOCKING_PREMEM_CONFIG
  • TvbRatioClipping : OVERCLOCKING_PREMEM_CONFIG
  • TvbVoltageOptimization : OVERCLOCKING_PREMEM_CONFIG
  • Tx : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • Txiset : USB2_PHY_PARAMETERS
  • TxtImplemented : SA_MISC_PEI_PREMEM_CONFIG
  • Type : FSP_ERROR_INFO_HOB


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented class members with links to the class documentation for each member:

- u -

  • UartDeviceConfig : SERIAL_IO_CONFIG
  • UnConfigureMe : AMT_DXE_CONFIG
  • UnderVoltProtection : OVERCLOCKING_PREMEM_CONFIG
  • UnsupportedRequestReport : TCSS_PCIE_PORT_POLICY
  • Usage : PCH_PCIE_CLOCK
  • Usb2PhySusPgEnable : PCH_PM_CONFIG
  • Usb4CmMode : _ITBT_GENERIC_CONFIG
  • UsbConfig : TCSS_PEI_CONFIG
  • UsbOverride : IOM_INTERFACE_CONFIG
  • UsbProvision : AMT_DXE_CONFIG
  • UsbTcConfig : TCSS_PEI_PREMEM_CONFIG
  • UsbTcPortEn : TCSS_USBTC_PEI_PERMEM_CONFIG
  • UserBd : SA_MISC_PEI_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented class members with links to the class documentation for each member:

- v -

  • V1p05IsExtFetControlEn : PCH_PM_CONFIG
  • V1p05PhyExtFetControlEn : PCH_PM_CONFIG
  • Value : FSP_ERROR_INFO_HOB
  • VcciaBootVoltageSel : OVERCLOCKING_PREMEM_CONFIG
  • VccinAux : PCH_FIVR_CONFIG
  • VccsaBootVoltageSel : OVERCLOCKING_PREMEM_CONFIG
  • VccSt : IOM_INTERFACE_CONFIG
  • VcType : HDAUDIO_PREMEM_CONFIG
  • VendorId : HDA_VERB_TABLE_HEADER , PCIE_DEVICE_OVERRIDE
  • Version : EFI_HOB_HANDOFF_INFO_TABLE
  • VmdCfgBarBase : VMD_PEI_CONFIG
  • VmdEnable : VMD_PEI_CONFIG
  • VmdGlobalMapping : VMD_PEI_CONFIG
  • VmdMemBar1Base : VMD_PEI_CONFIG
  • VmdMemBar2Base : VMD_PEI_CONFIG
  • VmdPortEnable : VMD_PEI_CONFIG
  • VmdVariablePtr : VMD_PEI_CONFIG
  • Voltage : FIVR_EXT_RAIL_CONFIG
  • VppAddress : PCH_PCIE_ROOT_PORT_CONFIG
  • VppPort : PCH_PCIE_ROOT_PORT_CONFIG
  • VrLimitBypass : OVERCLOCKING_PREMEM_CONFIG
  • VtdEnabled : PCH_GENERAL_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented class members with links to the class documentation for each member:

- w -

  • WakeConfig : PCH_PM_CONFIG
  • WakeOnTouch : THC_PORT
  • WatchDogEnabled : AMT_PEI_CONFIG
  • WatchDogTimerBios : AMT_PEI_CONFIG
  • WatchDogTimerOs : AMT_PEI_CONFIG
  • WolEnableOverride : PCH_WAKE_CONFIG
  • WolOvrWkSts : PCH_PM_CONFIG
  • WoWlanDeepSxEnable : PCH_WAKE_CONFIG
  • WoWlanEnable : PCH_WAKE_CONFIG
  • WriteOpcode : THC_HID_OVER_SPI
  • WriteProtectionEnable : PROTECTED_RANGE


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented class members with links to the class documentation for each member:

- z -

  • ZpOdd : PCH_SATA_PORT_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- a -

  • AcpiReservedMemoryBase : SA_MISC_PEI_PREMEM_CONFIG
  • AcpiReservedMemorySize : SA_MISC_PEI_PREMEM_CONFIG
  • AcsEnabled : TCSS_PCIE_PORT_POLICY
  • ActiveLtr : THC_PORT
  • AddressingMode : THC_HID_OVER_I2C
  • AdrEn : ADR_CONFIG
  • AdrHostPartitionReset : ADR_CONFIG
  • AdrMultiplier1Val : ADR_CONFIG
  • AdrMultiplier2Val : ADR_CONFIG
  • AdrPlatAckEn : ADR_CONFIG
  • AdrSrcOff : ADR_CONFIG
  • AdrSrcOn : ADR_CONFIG
  • AdrTimer1Val : ADR_CONFIG
  • AdrTimer2Val : ADR_CONFIG
  • AdrTimerEn : ADR_CONFIG
  • AdvancedErrorReporting : TCSS_PCIE_PORT_POLICY
  • AetEnabled : TRACE_HUB_CONFIG
  • AllocDescriptor : EFI_HOB_MEMORY_ALLOCATION , EFI_HOB_MEMORY_ALLOCATION_BSP_STORE , EFI_HOB_MEMORY_ALLOCATION_STACK
  • AmtEnabled : AMT_PEI_CONFIG
  • AmtReportError : AMT_DXE_CONFIG
  • AmtSolEnabled : AMT_PEI_CONFIG
  • ArpEnable : PCH_SMBUS_PREMEM_CONFIG
  • Aspm : TCSS_PCIE_PORT_POLICY
  • Assignment : THC_PORT
  • AtomClusterRatio : OVERCLOCKING_PREMEM_CONFIG
  • Attributes : _CONFIG_BLOCK_HEADER , SERIAL_IO_UART_CONFIG
  • AudioLinkDmic : HDAUDIO_PREMEM_CONFIG
  • AudioLinkHda : HDAUDIO_PREMEM_CONFIG
  • AudioLinkSndw : HDAUDIO_PREMEM_CONFIG
  • AudioLinkSsp : HDAUDIO_PREMEM_CONFIG
  • AuthenticationStatus : EFI_HOB_FIRMWARE_VOLUME3
  • AutoFlow : SERIAL_IO_UART_ATTRIBUTES
  • AuxOri : TCSS_IOM_ORI_OVERRIDE
  • AvailableSize : _CONFIG_BLOCK_TABLE_STRUCT
  • Avx2RatioOffset : OVERCLOCKING_PREMEM_CONFIG
  • Avx2VoltageScaleFactor : OVERCLOCKING_PREMEM_CONFIG
  • Avx3RatioOffset : OVERCLOCKING_PREMEM_CONFIG
  • Avx512VoltageScaleFactor : OVERCLOCKING_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- b -

  • BaseAddress : EFI_HOB_FIRMWARE_VOLUME2 , EFI_HOB_FIRMWARE_VOLUME3 , EFI_HOB_FIRMWARE_VOLUME , EFI_HOB_UEFI_CAPSULE
  • BaseClassCode : PCIE_DEVICE_OVERRIDE
  • BaudRate : SERIAL_IO_UART_ATTRIBUTES
  • BclkAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • BdatEnable : SA_MISC_PEI_PREMEM_CONFIG
  • BdatTestType : SA_MISC_PEI_PREMEM_CONFIG
  • Bifurcation : PCH_PCIE_RP_PREMEM_CONFIG
  • BiosInterfaceLock : RTC_CONFIG
  • BiosTraceSink : TRACE_HUB_CONFIG
  • BootMode : EFI_HOB_HANDOFF_INFO_TABLE
  • BypassPhySyncReset : PCH_HSIO_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- c -

  • C10DynamicThresholdAdjustment : PCH_PM_CONFIG
  • CallerId : FSP_ERROR_INFO_HOB
  • ChipsetInitBinLen : PCH_HSIO_CONFIG
  • ChipsetInitBinPtr : PCH_HSIO_CONFIG
  • ChipsetInitMessage : PCH_HSIO_PREMEM_CONFIG
  • CiraRequest : AMT_DXE_CONFIG
  • CkdAddressTable : SA_MISC_PEI_PREMEM_CONFIG
  • Clk : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • Clkreq : CNVI_PIN_MUX
  • ClkReq : PCH_PCIE_CLOCK
  • ClockGating : PCH_DMI_CONFIG
  • Cm : PCIE_EQ_PARAM
  • ComplianceTestMode : PCIE_COMMON_CONFIG
  • ComputeDieSscEnable : OVERCLOCKING_PREMEM_CONFIG
  • ConnectionSpeed : THC_HID_OVER_I2C
  • Controller : ISH_I3C_CONFIG
  • CoreAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • CoreMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • CoreMinRatio : OVERCLOCKING_PREMEM_CONFIG
  • CorePllCurrentRefTuningOffset : OVERCLOCKING_PREMEM_CONFIG
  • CorePllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • CoreRatioExtensionMode : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfConfigScope : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointCount : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointOffset : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointOffsetMode : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointRatio : OVERCLOCKING_PREMEM_CONFIG
  • CoreVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • CoreVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • CoreVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • CorrectableErrorReport : TCSS_PCIE_PORT_POLICY
  • Cp : PCIE_EQ_PARAM
  • CppmFaEn : PCH_PM_CONFIG
  • CpuAttachedStorage : RST_CONFIG
  • CpuBandgapRefMode : OVERCLOCKING_PREMEM_CONFIG
  • CpuBclkOcFrequency : OVERCLOCKING_PREMEM_CONFIG
  • CpuBclkPllOn : BCLK_CONFIG
  • CpuC10GatePinEnable : PCH_PM_CONFIG
  • CpuCrashLogDevice : TELEMETRY_PEI_PREMEM_CONFIG
  • CpuCrashLogEnable : TELEMETRY_PEI_CONFIG
  • CpuD2dRatio : OVERCLOCKING_PREMEM_CONFIG
  • CpuDlvrMode : OVERCLOCKING_PREMEM_CONFIG
  • CpuSaPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • CpuStart : EFI_MMRAM_DESCRIPTOR
  • Crid : PCH_GENERAL_CONFIG
  • Cs : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • CseDataResilience : ME_PEI_CONFIG
  • CsEnable : ISH_SPI , SERIAL_IO_SPI_CONFIG
  • CsMode : SERIAL_IO_SPI_CONFIG
  • CsPolarity : SERIAL_IO_SPI_CONFIG
  • CsState : SERIAL_IO_SPI_CONFIG
  • CtrlRampTmr : FIVR_EXT_RAIL_CONFIG
  • Cts : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • CustomizedSsid : SI_CONFIG
  • CustomizedSvid : SI_CONFIG
  • CwbEnable : PCH_DMI_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- d -

  • D3ColdEnable : IOM_INTERFACE_CONFIG
  • D3HotEnable : IOM_INTERFACE_CONFIG
  • DataBits : SERIAL_IO_UART_ATTRIBUTES
  • DataDwords : HDA_VERB_TABLE_HEADER
  • DBG2 : SERIAL_IO_UART_CONFIG
  • DciClkEnable : PCH_DCI_PREMEM_CONFIG
  • DciDbcMode : PCH_DCI_PREMEM_CONFIG
  • DciEn : PCH_DCI_PREMEM_CONFIG
  • DciUsb3TypecUfpDbg : PCH_DCI_PREMEM_CONFIG
  • DdrRfim : CNVI_PREMEM_CONFIG
  • DefaultCsOutput : SERIAL_IO_SPI_CONFIG
  • DefaultPresetEnable : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • DevEnConfig : TCSS_PEI_PREMEM_CONFIG
  • Device : PCH_DEVICE_INTERRUPT_CONFIG
  • DeviceAddress : THC_HID_OVER_I2C
  • DeviceId : HDA_VERB_TABLE_HEADER , PCIE_DEVICE_OVERRIDE
  • DeviceResetDelay : RST_HARDWARE_REMAPPED_STORAGE_CONFIG
  • DevIntConfig : PCH_INTERRUPT_CONFIG
  • DevSlp : PCH_SATA_PORT_CONFIG
  • DevSlpResetConfig : PCH_SATA_PORT_CONFIG
  • DidInitStat : ME_PEI_PREMEM_CONFIG
  • Direction : GPIO_CONFIG
  • DisableAndLock : PCH_WDT_PREMEM_CONFIG
  • DisableCpuReplacedPolling : ME_PEI_PREMEM_CONFIG
  • DisableD0I3SettingForHeci : ME_PEI_CONFIG
  • DisableDsxAcPresentPulldown : PCH_PM_CONFIG
  • DisableEnergyReport : PCH_PM_CONFIG
  • DisableMessageCheck : ME_PEI_PREMEM_CONFIG
  • DisableMrcRetrainingOnRtcPowerLoss : SA_MISC_PEI_PREMEM_CONFIG
  • DisableNativePowerButton : PCH_PM_CONFIG
  • DisablePerCoreMask : OVERCLOCKING_PREMEM_CONFIG
  • DisplayFrameSyncPeriod : THC_PORT
  • DitoVal : PCH_SATA_PORT_CONFIG
  • DmaEnable : SERIAL_IO_UART_CONFIG
  • DmiAspmCtrl : PCH_DMI_CONFIG
  • DmicClockSelect : HDA_LINK_DMIC
  • DmiHaAWC : THERMAL_CONFIG
  • DmiPowerReduction : PCH_DMI_CONFIG
  • DmiTranCoOverEn : DMI_LANE_CONFIG
  • DmiTranCoOverPostCur : DMI_LANE_CONFIG
  • DmiTranCoOverPreCur : DMI_LANE_CONFIG
  • DmiTsawEn : DMI_HW_WIDTH_CONTROL
  • DmiUpPortTranPreset : DMI_LANE_CONFIG
  • DmVal : PCH_SATA_PORT_CONFIG
  • DspEnable : HDAUDIO_PREMEM_CONFIG
  • DspFeatureMask : HDAUDIO_DXE_CONFIG
  • DspUaaCompliance : HDAUDIO_PREMEM_CONFIG
  • DynamicPowerGating : PCH_SMBUS_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- e -

  • EcoreTvbTempThreshold0 : OVERCLOCKING_PREMEM_CONFIG
  • EcoreTvbTempThreshold1 : OVERCLOCKING_PREMEM_CONFIG
  • EfiEndOfHobList : EFI_HOB_HANDOFF_INFO_TABLE
  • EfiFreeMemoryBottom : EFI_HOB_HANDOFF_INFO_TABLE
  • EfiFreeMemoryTop : EFI_HOB_HANDOFF_INFO_TABLE
  • EfiMemoryBottom : EFI_HOB_HANDOFF_INFO_TABLE
  • EfiMemoryTop : EFI_HOB_HANDOFF_INFO_TABLE
  • ElectricalConfig : GPIO_CONFIG
  • Enable : GBE_CONFIG , HDA_LINK_DMIC , HDA_LINK_HDA , HDA_LINK_SNDW , HDA_LINK_SSP , HDAUDIO_PREMEM_CONFIG , ISH_GP , ISH_I2C , ISH_PREMEM_CONFIG , ISH_SPI , ISH_UART , PCH_SATA_PORT_CONFIG , PCH_SMBUS_PREMEM_CONFIG , RST_HARDWARE_REMAPPED_STORAGE_CONFIG , SATA_CONFIG , USB2_PORT_CONFIG , USB3_PORT_CONFIG , XDCI_CONFIG
  • Enable8254ClockGating : PCH_IOAPIC_CONFIG
  • Enable8254ClockGatingOnS3 : PCH_IOAPIC_CONFIG
  • EnableDitoConfig : PCH_SATA_PORT_CONFIG
  • EnabledStates : FIVR_EXT_RAIL_CONFIG
  • EnableMode : TRACE_HUB_CONFIG
  • EnablePort8xhDecode : PCIE_COMMON_CONFIG
  • EnclosureSupport : SATA_CONFIG
  • EndOfPostMessage : ME_PEI_CONFIG
  • EndPointAspm : PCIE_DEVICE_OVERRIDE
  • EndPointPresetList : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • EnforceEDebugMode : ME_PEI_CONFIG
  • EnhancePort8xhDecoding : PCH_LPC_PREMEM_CONFIG
  • EntryPoint : EFI_HOB_MEMORY_ALLOCATION_MODULE
  • EqPh23Bypass : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • EqPh3Bypass : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • EqPhBypass : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • ErrorType : FSP_ERROR_INFO_HOB
  • EsataSpeedLimit : SATA_CONFIG
  • External : PCH_SATA_PORT_CONFIG
  • ExtractedFv : EFI_HOB_FIRMWARE_VOLUME3
  • ExtSync : PCH_PCIE_ROOT_PORT_CONFIG
  • ExtV1p05Rail : PCH_FIVR_CONFIG
  • ExtVnnRail : PCH_FIVR_CONFIG
  • ExtVnnRailSx : PCH_FIVR_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- f -

  • FastModePlusSerialClockLineHighPeriod : THC_HID_OVER_I2C
  • FastModePlusSerialClockLineLowPeriod : THC_HID_OVER_I2C
  • FastModePlusSerialDataLineReceiveHoldPeriod : THC_HID_OVER_I2C
  • FastModePlusSerialDataLineTransmitHoldPeriod : THC_HID_OVER_I2C
  • FastModeSerialClockLineHighPeriod : THC_HID_OVER_I2C
  • FastModeSerialClockLineLowPeriod : THC_HID_OVER_I2C
  • FastModeSerialDataLineReceiveHoldPeriod : THC_HID_OVER_I2C
  • FastModeSerialDataLineTransmitHoldPeriod : THC_HID_OVER_I2C
  • FatalErrorReport : TCSS_PCIE_PORT_POLICY
  • FileName : EFI_HOB_FIRMWARE_VOLUME2 , EFI_HOB_FIRMWARE_VOLUME3
  • FivrDynPm : PCH_FIVR_CONFIG
  • Flags : THC_HID_OVER_SPI
  • FllOverclockMode : OVERCLOCKING_PREMEM_CONFIG
  • ForceLtrOverride : PCIE_DEVICE_OVERRIDE , TCSS_PCIE_PORT_POLICY
  • ForcePcoreResidency : OVERCLOCKING_PREMEM_CONFIG
  • Frequency : THC_HID_OVER_SPI
  • Function : PCH_DEVICE_INTERRUPT_CONFIG
  • FvName : EFI_HOB_FIRMWARE_VOLUME2 , EFI_HOB_FIRMWARE_VOLUME3
  • FwProgress : AMT_PEI_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- g -

  • GlobalResetMasksOverride : PCH_PM_CONFIG
  • GnaEnable : GNA_CONFIG
  • GpioAuxBiasCtrlPdN : IOM_AUX_ORI_PAD_CONFIG
  • GpioAuxBiasCtrlPuP : IOM_AUX_ORI_PAD_CONFIG
  • GpioIrqRoute : PCH_INTERRUPT_CONFIG
  • GpioIsoCtrlPin : IOM_AUX_ORI_PAD_CONFIG
  • GranularRatioOverride : OVERCLOCKING_PREMEM_CONFIG
  • GtAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • GtIccUnlimitedMode : OVERCLOCKING_PREMEM_CONFIG
  • GtMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • GtVfPointCount : OVERCLOCKING_PREMEM_CONFIG
  • GtVfPointOffset : OVERCLOCKING_PREMEM_CONFIG
  • GtVfPointOffsetMode : OVERCLOCKING_PREMEM_CONFIG
  • GtVfPointRatio : OVERCLOCKING_PREMEM_CONFIG
  • GtVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • GtVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • GtVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • GuidHob : _CONFIG_BLOCK_HEADER , FSP_ERROR_INFO_HOB


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- h -

  • HapcsSearchEnable : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • HardwareRemappedStorageConfig : RST_CONFIG
  • HdaDiscBtOffload : HDAUDIO_DXE_CONFIG , HDAUDIO_PREMEM_CONFIG
  • HddUnlock : RST_CONFIG
  • Header : _CONFIG_BLOCK , _CONFIG_BLOCK_TABLE_STRUCT , ADR_CONFIG , AMT_DXE_CONFIG , AMT_PEI_CONFIG , BCLK_CONFIG , CNVI_PREMEM_CONFIG , EFI_HOB_CPU , EFI_HOB_FIRMWARE_VOLUME2 , EFI_HOB_FIRMWARE_VOLUME3 , EFI_HOB_FIRMWARE_VOLUME , EFI_HOB_GUID_TYPE , EFI_HOB_HANDOFF_INFO_TABLE , EFI_HOB_MEMORY_ALLOCATION , EFI_HOB_MEMORY_ALLOCATION_BSP_STORE , EFI_HOB_MEMORY_ALLOCATION_MODULE , EFI_HOB_MEMORY_ALLOCATION_STACK , EFI_HOB_MEMORY_POOL , EFI_HOB_RESOURCE_DESCRIPTOR , EFI_HOB_UEFI_CAPSULE , GBE_CONFIG , GNA_CONFIG , HDAUDIO_DXE_CONFIG , HDAUDIO_PREMEM_CONFIG , IEH_CONFIG , ISH_CONFIG , ISH_I3C_CONFIG , ISH_PREMEM_CONFIG , ME_PEI_CONFIG , ME_PEI_PREMEM_CONFIG , OVERCLOCKING_PREMEM_CONFIG , PCH_DCI_PREMEM_CONFIG , PCH_DMI_CONFIG , PCH_FIVR_CONFIG , PCH_FLASH_PROTECTION_CONFIG , PCH_GENERAL_CONFIG , PCH_HSIO_CONFIG , PCH_HSIO_PCIE_PREMEM_CONFIG , PCH_HSIO_PREMEM_CONFIG , PCH_HSIO_SATA_PREMEM_CONFIG , PCH_INTERRUPT_CONFIG , PCH_IOAPIC_CONFIG , PCH_LPC_PREMEM_CONFIG , PCH_P2SB_CONFIG , PCH_PCIE_CONFIG , PCH_PCIE_RP_PREMEM_CONFIG , PCH_PM_CONFIG , PCH_SMBUS_PREMEM_CONFIG , PCH_TRACE_HUB_PREMEM_CONFIG , PCH_WDT_PREMEM_CONFIG , PCIE_PREMEM_CONFIG , PCIE_RP_DXE_CONFIG , RST_CONFIG , RTC_CONFIG , SA_MISC_PEI_PREMEM_CONFIG , SATA_CONFIG , SERIAL_IO_CONFIG , SI_CONFIG , SI_PREMEM_CONFIG , TCSS_PEI_CONFIG , TCSS_PEI_PREMEM_CONFIG , THC_CONFIG , THERMAL_CONFIG , TRACE_HUB_PREMEM_CONFIG , USB2_PHY_CONFIG , VMD_PEI_CONFIG
  • HeciCommunication2 : ME_PEI_PREMEM_CONFIG
  • HeciFullTrace : ME_PEI_PREMEM_CONFIG
  • HeciTimeouts : ME_PEI_PREMEM_CONFIG
  • HidOverI2c : THC_PORT
  • HidOverSpi : THC_PORT
  • HighSpeedModePlusSerialClockLineHighPeriod : THC_HID_OVER_I2C
  • HighSpeedModePlusSerialClockLineLowPeriod : THC_HID_OVER_I2C
  • HighSpeedModePlusSerialDataLineReceiveHoldPeriod : THC_HID_OVER_I2C
  • HighSpeedModePlusSerialDataLineTransmitHoldPeriod : THC_HID_OVER_I2C
  • HintList : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • HobLength : EFI_HOB_GENERIC_HEADER
  • HobType : EFI_HOB_GENERIC_HEADER
  • HostSoftPadOwn : GPIO_CONFIG
  • HotPlug : PCH_SATA_PORT_CONFIG
  • HsioCtrlAdaptOffsetCfg : HSIO_PARAMETERS
  • HsioCtrlAdaptOffsetCfgEnable : HSIO_PARAMETERS
  • HsioFilterSelN : HSIO_PARAMETERS
  • HsioFilterSelNEnable : HSIO_PARAMETERS
  • HsioFilterSelP : HSIO_PARAMETERS
  • HsioFilterSelPEnable : HSIO_PARAMETERS
  • HsioOlfpsCfgPullUpDwnRes : HSIO_PARAMETERS
  • HsioOlfpsCfgPullUpDwnResEnable : HSIO_PARAMETERS
  • HsioRxGen1EqBoostMag : PCH_HSIO_SATA_PORT_LANE
  • HsioRxGen1EqBoostMagEnable : PCH_HSIO_SATA_PORT_LANE
  • HsioRxGen2EqBoostMag : PCH_HSIO_SATA_PORT_LANE
  • HsioRxGen2EqBoostMagEnable : PCH_HSIO_SATA_PORT_LANE
  • HsioRxGen3EqBoostMag : PCH_HSIO_SATA_PORT_LANE
  • HsioRxGen3EqBoostMagEnable : PCH_HSIO_SATA_PORT_LANE
  • HsioRxSetCtle : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioRxSetCtleEnable : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioTxDeEmph : HSIO_PARAMETERS
  • HsioTxDeEmphEnable : HSIO_PARAMETERS
  • HsioTxDownscaleAmp : HSIO_PARAMETERS
  • HsioTxDownscaleAmpEnable : HSIO_PARAMETERS
  • HsioTxGen1DeEmph : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen1DeEmphEnable : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen1DownscaleAmp : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen1DownscaleAmpEnable : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen2DeEmph : PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen2DeEmph3p5 : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioTxGen2DeEmph3p5Enable : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioTxGen2DeEmph6p0 : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioTxGen2DeEmph6p0Enable : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioTxGen2DeEmphEnable : PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen2DownscaleAmp : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen2DownscaleAmpEnable : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen3DeEmph : PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen3DeEmphEnable : PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen3DownscaleAmp : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen3DownscaleAmpEnable : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxRate0UniqTran : HSIO_PARAMETERS
  • HsioTxRate0UniqTranEnable : HSIO_PARAMETERS
  • HsioTxRate1UniqTran : HSIO_PARAMETERS
  • HsioTxRate1UniqTranEnable : HSIO_PARAMETERS
  • HsioTxRate2UniqTran : HSIO_PARAMETERS
  • HsioTxRate2UniqTranEnable : HSIO_PARAMETERS
  • HsioTxRate3UniqTran : HSIO_PARAMETERS
  • HsioTxRate3UniqTranEnable : HSIO_PARAMETERS
  • HslOri : TCSS_IOM_ORI_OVERRIDE


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- i -

  • I2cDeviceConfig : SERIAL_IO_CONFIG
  • I3cDeviceConfig : SERIAL_IO_CONFIG
  • IaAtomPllCurrentRefTuningOffset : OVERCLOCKING_PREMEM_CONFIG
  • IaAtomPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • IaIccMax : OVERCLOCKING_PREMEM_CONFIG
  • IaIccUnlimitedMode : OVERCLOCKING_PREMEM_CONFIG
  • IccMaximum : FIVR_EXT_RAIL_CONFIG
  • IDispCodecDisconnect : HDAUDIO_PREMEM_CONFIG
  • IDispLinkFrequency : HDAUDIO_PREMEM_CONFIG
  • IDispLinkTmode : HDAUDIO_PREMEM_CONFIG
  • IdleLtr : THC_PORT
  • ImguClkOutEn : IPU_PREMEM_CONFIG
  • ImrEnabled : PCIE_IMR_CONFIG
  • ImrRpLocation : PCIE_IMR_CONFIG
  • ImrRpSelection : PCIE_IMR_CONFIG
  • ImrSize : PCIE_IMR_CONFIG
  • InputReportBodyAddress : THC_HID_OVER_SPI
  • InputReportHeaderAddress : THC_HID_OVER_SPI
  • Instance : FSP_ERROR_INFO_HOB
  • InterlockSw : PCH_SATA_PORT_CONFIG
  • InterruptConfig : GPIO_CONFIG
  • InterruptPinMuxing : THC_PORT
  • IntPing : SA_XDCI_IRQ_INT_CONFIG
  • IntX : PCH_DEVICE_INTERRUPT_CONFIG
  • IoApicEntry24_119 : PCH_IOAPIC_CONFIG
  • IoApicId : PCH_IOAPIC_CONFIG
  • IomAuxPortPad : TCSS_IOM_PEI_CONFIG
  • IomConfig : TCSS_PEI_CONFIG
  • IomInterface : TCSS_IOM_PEI_CONFIG
  • IpuEnable : IPU_PREMEM_CONFIG
  • Irq : PCH_DEVICE_INTERRUPT_CONFIG , SA_XDCI_IRQ_INT_CONFIG
  • Irrt : RST_CONFIG
  • IrrtOnly : RST_CONFIG
  • ITbtConnectTopologyTimeoutInMs : _ITBT_GENERIC_CONFIG
  • ITbtForcePowerOnTimeoutInMs : _ITBT_GENERIC_CONFIG
  • ITbtPcieRootPortEn : _ITBT_ROOTPORT_CONFIG
  • ITbtPcieTunnelingForUsb4 : _ITBT_GENERIC_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- k -

  • KeepEarlyTrace : PCH_DCI_PREMEM_CONFIG
  • KtDeviceEnable : ME_PEI_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- l -

  • L1RpCtl : PCH_DMI_CONFIG
  • L1sCommonModeRestoreTime : PCIE_DEVICE_OVERRIDE
  • L1sTpowerOnScale : PCIE_DEVICE_OVERRIDE
  • L1sTpowerOnValue : PCIE_DEVICE_OVERRIDE
  • L1SubstatesCapMask : PCIE_DEVICE_OVERRIDE
  • L1SubstatesCapOffset : PCIE_DEVICE_OVERRIDE
  • Lane : PCH_HSIO_PCIE_PREMEM_CONFIG
  • LanWakeFromDeepSx : PCH_WAKE_CONFIG
  • LatchEventsC10Exit : PCH_PM_CONFIG
  • LedEnable : SATA_CONFIG
  • LedLocate : RST_CONFIG
  • LegacyIoLowLatency : PCH_GENERAL_CONFIG
  • LegacyOrom : RST_CONFIG
  • Length : EFI_HOB_FIRMWARE_VOLUME2 , EFI_HOB_FIRMWARE_VOLUME3 , EFI_HOB_FIRMWARE_VOLUME
  • LimitPacketSize : THC_HID_OVER_SPI
  • LocalTxOverrideEn : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • LockConfig : GPIO_CONFIG
  • LockPTMregs : SA_MISC_PEI_PREMEM_CONFIG
  • LowToHighCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • LpcPmHAE : PCH_LPC_PREMEM_CONFIG
  • LpmS0ixSubStateEnable : PCH_PM_CONFIG
  • LtrConfigLock : TCSS_PCIE_PORT_POLICY
  • LtrEnable : GBE_CONFIG , TCSS_PCIE_PORT_POLICY
  • LtrMaxNoSnoopLatency : TCSS_PCIE_PORT_POLICY
  • LtrMaxSnoopLatency : TCSS_PCIE_PORT_POLICY


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- m -

  • MaximumLengthOfSuppressedSpikesInHighSpeedMode : THC_HID_OVER_I2C
  • MaxSuppressedSpikesSMFMFMP : THC_HID_OVER_I2C
  • MaxVoltageLimit : OVERCLOCKING_PREMEM_CONFIG
  • McPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • MctpBroadcastCycle : ME_PEI_CONFIG
  • MemoryAllocationHeader : EFI_HOB_MEMORY_ALLOCATION_MODULE
  • MemoryBaseAddress : EFI_HOB_MEMORY_ALLOCATION_HEADER
  • MemoryLength : EFI_HOB_MEMORY_ALLOCATION_HEADER
  • MemoryLock : RTC_CONFIG
  • MemoryType : EFI_HOB_MEMORY_ALLOCATION_HEADER
  • MemReg0Size : TRACE_HUB_CONFIG
  • MemSSAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • MemSSMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • MemSSVfPointCount : OVERCLOCKING_PREMEM_CONFIG
  • MemSSVfPointOffset : OVERCLOCKING_PREMEM_CONFIG
  • MemSSVfPointOffsetMode : OVERCLOCKING_PREMEM_CONFIG
  • MemSSVfPointRatio : OVERCLOCKING_PREMEM_CONFIG
  • MemSSVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • MemSSVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • MemSSVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • MeUnconfigOnRtcClear : ME_PEI_CONFIG
  • MeWakeSts : PCH_PM_CONFIG
  • MiscConfig : TCSS_PEI_CONFIG
  • Miso : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • MmramReservedSize : _EFI_MM_RESERVED_MMRAM_REGION
  • MmramReservedStart : _EFI_MM_RESERVED_MMRAM_REGION
  • Mode : IEH_CONFIG , SERIAL_IO_I3C_CONFIG , SERIAL_IO_SPI_CONFIG , SERIAL_IO_UART_CONFIG , THC_PORT
  • ModPhySusPgEnable : PCH_PM_CONFIG
  • ModuleName : EFI_HOB_MEMORY_ALLOCATION_MODULE
  • Mosi : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • MrcMustStaticSpdData : SA_MISC_PEI_PREMEM_CONFIG
  • MsiInterrupt : ISH_CONFIG
  • MvcEnabled : PCH_PCIE_ROOT_PORT_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- n -

  • Name : EFI_HOB_GUID_TYPE , EFI_HOB_MEMORY_ALLOCATION_HEADER
  • NclkTurboThermalProtection : OVERCLOCKING_PREMEM_CONFIG
  • NguAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • NguMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • NguRatio : OVERCLOCKING_PREMEM_CONFIG
  • NguVfPointCount : OVERCLOCKING_PREMEM_CONFIG
  • NguVfPointOffset : OVERCLOCKING_PREMEM_CONFIG
  • NguVfPointOffsetMode : OVERCLOCKING_PREMEM_CONFIG
  • NguVfPointRatio : OVERCLOCKING_PREMEM_CONFIG
  • NguVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • NguVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • NoFatalErrorReport : TCSS_PCIE_PORT_POLICY
  • NonSnoopLatency : PCIE_DEVICE_OVERRIDE
  • NonSnoopLatencyOverrideMode : TCSS_PCIE_PORT_POLICY
  • NonSnoopLatencyOverrideMultiplier : TCSS_PCIE_PORT_POLICY
  • NonSnoopLatencyOverrideValue : TCSS_PCIE_PORT_POLICY
  • NphyBinLen : PCH_HSIO_CONFIG
  • NphyBinPtr : PCH_HSIO_CONFIG
  • NpuAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • NpuMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • NpuVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • NpuVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • NpuVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • NumberOfBlocks : _CONFIG_BLOCK_TABLE_STRUCT
  • NumberOfSsidTableEntry : SI_CONFIG
  • NumOfDevIntConfig : PCH_INTERRUPT_CONFIG
  • NumRsvdSmbusAddresses : PCH_SMBUS_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- o -

  • OcSupport : OVERCLOCKING_PREMEM_CONFIG
  • OcTvb : OVERCLOCKING_PREMEM_CONFIG
  • OfflineCrashDumpEnable : SA_MISC_PEI_PREMEM_CONFIG
  • OffToHighCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • OpRomScanTempMmioBar : SA_MISC_PEI_PREMEM_CONFIG
  • OpRomScanTempMmioLimit : SA_MISC_PEI_PREMEM_CONFIG
  • OptaneMemory : RST_CONFIG
  • OromUiBanner : RST_CONFIG
  • OromUiDelay : RST_CONFIG
  • OsIdleEnable : PCH_PM_CONFIG
  • OtherSettings : GPIO_CONFIG
  • OutputReportAddress : THC_HID_OVER_SPI
  • OutputState : GPIO_CONFIG
  • OverCurrentPin : USB2_PORT_CONFIG , USB3_PORT_CONFIG
  • OverrideConfig : PCIE_DEVICE_OVERRIDE
  • Owner : EFI_HOB_RESOURCE_DESCRIPTOR


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- p -

  • P0T1M : SATA_THERMAL_THROTTLING
  • P0T2M : SATA_THERMAL_THROTTLING
  • P0T3M : SATA_THERMAL_THROTTLING
  • P0TDisp : SATA_THERMAL_THROTTLING
  • P0TDispFinit : SATA_THERMAL_THROTTLING
  • P0Tinact : SATA_THERMAL_THROTTLING
  • P1T1M : SATA_THERMAL_THROTTLING
  • P1T2M : SATA_THERMAL_THROTTLING
  • P1T3M : SATA_THERMAL_THROTTLING
  • P1TDisp : SATA_THERMAL_THROTTLING
  • P1TDispFinit : SATA_THERMAL_THROTTLING
  • P1Tinact : SATA_THERMAL_THROTTLING
  • PadMode : GPIO_CONFIG
  • PadTermination : ISH_GPIO_CONFIG , MUX_GPIO_CONFIG , SERIAL_IO_I2C_CONFIG
  • Parity : SERIAL_IO_UART_ATTRIBUTES
  • PCETTimer : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PchDeepSxPol : PCH_PM_CONFIG
  • PchHotEnable : THERMAL_CONFIG
  • PchHotLevel : THERMAL_CONFIG
  • PchPciePort8xhDecodePortIndex : PCH_PCIE_CONFIG
  • PchPwrCycDur : PCH_PM_CONFIG
  • PchSlpAMinAssert : PCH_PM_CONFIG
  • PchSlpS3MinAssert : PCH_PM_CONFIG
  • PchSlpS4MinAssert : PCH_PM_CONFIG
  • PchSlpSusMinAssert : PCH_PM_CONFIG
  • PchWOLFastSupport : GBE_CONFIG
  • PcieClock : PCH_PCIE_RP_PREMEM_CONFIG
  • PcieCommonConfig : PCH_PCIE_CONFIG
  • PcieDeviceOverrideTablePtr : PCIE_RP_DXE_CONFIG
  • PcieImr : PCIE_PREMEM_CONFIG
  • PcieLinkEqMethod : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PcieLinkEqMode : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PciePllSsc : PCH_PM_CONFIG
  • PciePolicy : TCSS_PEI_CONFIG
  • PcieWakeFromDeepSx : PCH_WAKE_CONFIG
  • PcorePowerDensityThrottle : OVERCLOCKING_PREMEM_CONFIG
  • PcoreTvbTempThreshold0 : OVERCLOCKING_PREMEM_CONFIG
  • PcoreTvbTempThreshold1 : OVERCLOCKING_PREMEM_CONFIG
  • PdtUnlock : ISH_CONFIG
  • Pehalfbit : USB2_PHY_PARAMETERS
  • PeiPolicyInit : _PEI_SI_DEFAULT_POLICY_INIT_PPI
  • PeiPreMemPolicyInit : _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI
  • PerAtomClusterAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • PerAtomClusterMaxRatio : OVERCLOCKING_PREMEM_CONFIG
  • PerAtomClusterVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • PerAtomClusterVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreDisableConfiguration : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreGranularityBins : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreHtDisable : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreMaxRatio : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreRatioOverride : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • PerEcoreCcpRatioDownBinAboveT0 : OVERCLOCKING_PREMEM_CONFIG
  • PerEcoreCcpRatioDownBinAboveT1 : OVERCLOCKING_PREMEM_CONFIG
  • PerformanceLimitation : THC_PORT
  • PerPcoreGrRatioDownBinAboveT0 : OVERCLOCKING_PREMEM_CONFIG
  • PerPcoreGrRatioDownBinAboveT1 : OVERCLOCKING_PREMEM_CONFIG
  • PerPcoreRatioDownBinAboveT0 : OVERCLOCKING_PREMEM_CONFIG
  • PerPcoreRatioDownBinAboveT1 : OVERCLOCKING_PREMEM_CONFIG
  • Petxiset : USB2_PHY_PARAMETERS
  • Ph1DpTxPreset : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph1UpTxPreset : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph2LocalTxOverridePreset : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph3CoefficientsList : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph3NoOfPresetOrCoeff : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph3PresetList : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PhysicalSize : EFI_MMRAM_DESCRIPTOR
  • PhysicalStart : EFI_HOB_RESOURCE_DESCRIPTOR , EFI_MMRAM_DESCRIPTOR
  • PinMux : HDA_LINK_DMIC , ISH_GPIO_CONFIG , SERIAL_IO_I2C_CONFIG , SERIAL_IO_SPI_CONFIG , SERIAL_IO_UART_CONFIG
  • PlatformAtxTelemetryUnit : PCH_PM_CONFIG
  • PlatformDebugOption : SI_PREMEM_CONFIG
  • PmcDbgMsgEn : PCH_PM_CONFIG
  • PmcInterface : TCSS_IOM_PEI_CONFIG
  • PmcPdEnable : PMC_INTERFACE_CONFIG
  • PmcWdtTimerEn : PCH_PM_CONFIG
  • PmeB0S5Dis : PCH_WAKE_CONFIG
  • PmErDebugMode : PCH_PM_CONFIG
  • Port : USB2_PHY_CONFIG
  • PortLane : PCH_HSIO_SATA_PREMEM_CONFIG
  • PortResetMessageEnable : USB2_PORT_CONFIG
  • PortSettings : SATA_CONFIG
  • PowerConfig : GPIO_CONFIG
  • PowerGating : SERIAL_IO_UART_CONFIG
  • PowerGatingSupported : HDAUDIO_PREMEM_CONFIG
  • Predeemp : USB2_PHY_PARAMETERS
  • PredeempSemiflexEn : USB2_PHY_PARAMETERS
  • ProcessVmaxLimit : OVERCLOCKING_PREMEM_CONFIG
  • ProtectedRangeBase : PROTECTED_RANGE
  • ProtectedRangeLimit : PROTECTED_RANGE
  • ProtectRange : PCH_FLASH_PROTECTION_CONFIG
  • PsOnEnable : PCH_PM_CONFIG
  • PtmEnabled : TCSS_PCIE_PORT_POLICY
  • PvdMode : OVERCLOCKING_PREMEM_CONFIG
  • PvdRatioThreshold : OVERCLOCKING_PREMEM_CONFIG
  • PwrBtnOverridePeriod : PCH_PM_CONFIG
  • PwrOptEnable : PCH_DMI_CONFIG , SATA_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- r -

  • Raid0 : RST_CONFIG
  • Raid1 : RST_CONFIG
  • Raid10 : RST_CONFIG
  • Raid5 : RST_CONFIG
  • RaidDeviceId : SATA_CONFIG
  • ReadOpcode : THC_HID_OVER_SPI
  • ReadProtectionEnable : PROTECTED_RANGE
  • RealtimeMemoryTiming : OVERCLOCKING_PREMEM_CONFIG
  • RegionState : EFI_MMRAM_DESCRIPTOR
  • RemotePresetCoeffoverride : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Reserved : _CONFIG_BLOCK_HEADER , _ITBT_GENERIC_CONFIG , _ITBT_ROOTPORT_CONFIG , EFI_HOB_CPU , EFI_HOB_GENERIC_HEADER , EFI_HOB_MEMORY_ALLOCATION_HEADER , HDA_LINK_HDA , PMC_LPM_S0IX_SUB_STATE_EN , SERIAL_IO_I3C_CONFIG , TCSS_IOM_PEI_CONFIG , TCSS_MISC_PEI_CONFIG , TCSS_PCIE_PEI_POLICY , THC_PORT , TRACE_HUB_CONFIG
  • Reserved1 : SA_MISC_PEI_PREMEM_CONFIG
  • Reserved2 : _ITBT_GENERIC_CONFIG
  • Reset : THC_PORT
  • ResetPad : THC_RESET
  • ResetPadTrigger : THC_RESET
  • ResetSequencingDelay : THC_RESET
  • ResetWaitTimer : HDAUDIO_PREMEM_CONFIG
  • ResourceAttribute : EFI_HOB_RESOURCE_DESCRIPTOR
  • ResourceLength : EFI_HOB_RESOURCE_DESCRIPTOR
  • ResourceType : EFI_HOB_RESOURCE_DESCRIPTOR
  • RetToHighCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • RetToLowCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • RevId : PCIE_DEVICE_OVERRIDE
  • Revision : _CONFIG_BLOCK_HEADER
  • RevisionId : HDA_VERB_TABLE_HEADER
  • RfReset : CNVI_PIN_MUX
  • RingAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • RingDownBin : OVERCLOCKING_PREMEM_CONFIG
  • RingMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • RingPllCurrentRefTuningOffset : OVERCLOCKING_PREMEM_CONFIG
  • RingPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • RingTurboThermalProtection : OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointCount : OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointOffset : OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointOffsetMode : OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointRatio : OVERCLOCKING_PREMEM_CONFIG
  • RingVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • RingVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • RingVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • RpEnabledMask : PCH_PCIE_RP_PREMEM_CONFIG
  • RpFunctionSwap : PCIE_COMMON_CONFIG
  • RstPcieStoragePort : RST_HARDWARE_REMAPPED_STORAGE_CONFIG
  • Rsvd : IPU_PREMEM_CONFIG , SA_MISC_PEI_PREMEM_CONFIG , TCSS_USBTC_PEI_PERMEM_CONFIG , VMD_PEI_CONFIG
  • Rsvd0 : _CONFIG_BLOCK_TABLE_STRUCT , HDAUDIO_PREMEM_CONFIG , PCH_INTERRUPT_CONFIG , PCH_IOAPIC_CONFIG , PCH_PM_CONFIG , PCH_SMBUS_PREMEM_CONFIG , PCIE_EQ_PARAM , THERMAL_THROTTLE_LEVELS
  • Rsvd1 : DMI_LANE_CONFIG , PCH_PM_CONFIG
  • Rsvd2 : DMI_LANE_CONFIG
  • Rsvd3 : DMI_LANE_CONFIG , SA_MISC_PEI_PREMEM_CONFIG
  • Rsvd4 : DMI_LANE_CONFIG , SA_MISC_PEI_PREMEM_CONFIG
  • RsvdBits : AMT_DXE_CONFIG , AMT_PEI_CONFIG , GPIO_CONFIG , HDAUDIO_PREMEM_CONFIG , ME_PEI_CONFIG , ME_PEI_PREMEM_CONFIG
  • Rsvdbits : PCH_DMI_CONFIG
  • RsvdBits : PCH_LPC_PREMEM_CONFIG
  • Rsvdbits : PCH_P2SB_CONFIG
  • RsvdBits : PROTECTED_RANGE , SI_PREMEM_CONFIG
  • RsvdBits0 : DMI_HW_WIDTH_CONTROL , GBE_CONFIG , GNA_CONFIG , IEH_CONFIG , ISH_CONFIG , ISH_GP , ISH_I2C , ISH_PREMEM_CONFIG , ISH_UART , PCH_GENERAL_CONFIG , PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE , PCH_SATA_PORT_CONFIG , PCH_SMBUS_PREMEM_CONFIG , PCIE_COMMON_CONFIG , RST_CONFIG , RST_HARDWARE_REMAPPED_STORAGE_CONFIG , SA_MISC_PEI_PREMEM_CONFIG , SATA_THERMAL_THROTTLING , THERMAL_THROTTLE_LEVELS , USB2_PORT_CONFIG , USB3_PORT_CONFIG , XDCI_CONFIG
  • RsvdBits1 : DMI_HW_WIDTH_CONTROL , FIVR_EXT_RAIL_CONFIG , OVERCLOCKING_PREMEM_CONFIG , PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE , PCH_IOAPIC_CONFIG
  • RsvdBits2 : FIVR_EXT_RAIL_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • RsvdBytes : PCH_PCIE_CLOCK , SI_PREMEM_CONFIG
  • RsvdBytes0 : PCH_PCIE_ROOT_PORT_CONFIG , SI_CONFIG
  • RsvdBytes1 : SI_CONFIG
  • RsvdBytes2 : SI_CONFIG
  • RsvdField0 : ISH_SPI
  • RsvdSmbusAddressTable : PCH_SMBUS_PREMEM_CONFIG
  • Rts : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • Rx : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • RxPolarity : PCH_SATA_PORT_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- s -

  • S0i2p0En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i2p1En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i2p2En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p0En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p1En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p2En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p3En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p4En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0ixAutoDemotion : PCH_PM_CONFIG
  • S3DataPtr : SA_MISC_PEI_PREMEM_CONFIG
  • SaAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • SaIccUnlimitedMode : OVERCLOCKING_PREMEM_CONFIG
  • SalpSupport : SATA_CONFIG
  • SaPllFreqOverride : OVERCLOCKING_PREMEM_CONFIG
  • SaPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • SataMode : SATA_CONFIG
  • SataRstInterrupt : SATA_CONFIG
  • SaVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • SaVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • SaVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • SaXdci : TCSS_MISC_PEI_CONFIG
  • SbAccessUnlock : PCH_P2SB_CONFIG
  • ScanExtGfxForLegacyOpRom : SA_MISC_PEI_PREMEM_CONFIG
  • SciIrqSelect : PCH_INTERRUPT_CONFIG
  • Scl : I2C_PIN_MUX , ISH_I2C_PIN_CONFIG
  • Sda : I2C_PIN_MUX , ISH_I2C_PIN_CONFIG
  • SdiEnable : HDA_LINK_HDA
  • SdiNum : HDA_VERB_TABLE_HEADER
  • SgpioSupport : SATA_CONFIG
  • SizeOfIoSpace : EFI_HOB_CPU
  • SizeOfMemorySpace : EFI_HOB_CPU
  • SkipBiosDoneWhenFwUpdate : SI_CONFIG
  • SkipCpuReplacementCheck : ME_PEI_PREMEM_CONFIG
  • SkipExtGfxScan : SA_MISC_PEI_PREMEM_CONFIG
  • SkipMbpHob : ME_PEI_PREMEM_CONFIG
  • SkipOverrideBootModeWhenFwUpdate : SI_PREMEM_CONFIG
  • SkipSsidProgramming : SI_CONFIG
  • SlotNumber : TCSS_PCIE_PORT_POLICY
  • SlotPowerLimitScale : TCSS_PCIE_PORT_POLICY
  • SlotPowerLimitValue : TCSS_PCIE_PORT_POLICY
  • SlpLanLowDc : PCH_PM_CONFIG
  • SlpStrchSusUp : PCH_PM_CONFIG
  • SmartStorage : RST_CONFIG
  • SmbAlertEnable : PCH_SMBUS_PREMEM_CONFIG
  • SmbusBar : SA_MISC_PEI_PREMEM_CONFIG
  • SmbusIoBase : PCH_SMBUS_PREMEM_CONFIG
  • SndwConfig : HDAUDIO_DXE_CONFIG
  • SndwMultilaneEnable : HDAUDIO_PREMEM_CONFIG
  • SnoopLatency : PCIE_DEVICE_OVERRIDE
  • SnoopLatencyOverrideMode : TCSS_PCIE_PORT_POLICY
  • SnoopLatencyOverrideMultiplier : TCSS_PCIE_PORT_POLICY
  • SnoopLatencyOverrideValue : TCSS_PCIE_PORT_POLICY
  • SocBclkOcFrequency : OVERCLOCKING_PREMEM_CONFIG
  • SocBclkPllOn : BCLK_CONFIG
  • SocDieSscEnable : OVERCLOCKING_PREMEM_CONFIG
  • SolidStateDrive : PCH_SATA_PORT_CONFIG
  • SpdAddressTable : SA_MISC_PEI_PREMEM_CONFIG
  • SpdWriteDisable : PCH_SMBUS_PREMEM_CONFIG
  • SpeedLimit : SATA_CONFIG
  • SpiDeviceConfig : SERIAL_IO_CONFIG
  • SpinUp : PCH_SATA_PORT_CONFIG
  • SsidTablePtr : SI_CONFIG
  • StandardModeSerialClockLineHighPeriod : THC_HID_OVER_I2C
  • StandardModeSerialClockLineLowPeriod : THC_HID_OVER_I2C
  • StandardModeSerialDataLineReceiveHoldPeriod : THC_HID_OVER_I2C
  • StandardModeSerialDataLineTransmitHoldPeriod : THC_HID_OVER_I2C
  • Status : FSP_ERROR_INFO_HOB
  • StopBits : SERIAL_IO_UART_ATTRIBUTES
  • SubClassCode : PCIE_DEVICE_OVERRIDE
  • SubSystemIds : HDAUDIO_PREMEM_CONFIG
  • SuggestedSetting : DMI_HW_WIDTH_CONTROL , SATA_THERMAL_THROTTLING , THERMAL_THROTTLE_LEVELS
  • SupportedVoltageStates : FIVR_EXT_RAIL_CONFIG
  • SwDeviceModeEnable : USB2_PORT_CONFIG
  • SynpsPhyBinLen : PCH_HSIO_CONFIG
  • SynpsPhyBinPtr : PCH_HSIO_CONFIG
  • SystemErrorEnable : PCH_PCIE_ROOT_PORT_CONFIG
  • SystemErrorOnCorrectableError : TCSS_PCIE_PORT_POLICY
  • SystemErrorOnFatalError : TCSS_PCIE_PORT_POLICY
  • SystemErrorOnNonFatalError : TCSS_PCIE_PORT_POLICY
  • SystemMemoryLength : SA_MISC_PEI_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- t -

  • T0Level : THERMAL_THROTTLE_LEVELS
  • T1Level : THERMAL_THROTTLE_LEVELS
  • T2Level : THERMAL_THROTTLE_LEVELS
  • TableHeader : _SI_POLICY_STRUCT , _SI_PREMEM_POLICY_STRUCT
  • TcNotifyIgd : TCSS_IOM_PEI_CONFIG
  • TcoIrqEnable : PCH_INTERRUPT_CONFIG
  • TcoIrqSelect : PCH_INTERRUPT_CONFIG
  • TcssConvTypeA : TCSS_MISC_PEI_CONFIG
  • TcssDevEn : TCSS_DEVEN_PEI_PREMEM_CONFIG
  • TcStateLimit : TCSS_IOM_PEI_CONFIG
  • TestMode : SATA_CONFIG
  • ThcPort : THC_CONFIG
  • ThermalThrottling : SATA_CONFIG
  • ThermTimerDelay : PCH_PM_CONFIG
  • TimestampTimerMode : THC_PORT
  • TjMaxOffset : OVERCLOCKING_PREMEM_CONFIG
  • TraceHub : PCH_TRACE_HUB_PREMEM_CONFIG , TRACE_HUB_PREMEM_CONFIG
  • TS0TW : DMI_HW_WIDTH_CONTROL
  • TS1TW : DMI_HW_WIDTH_CONTROL
  • TS2TW : DMI_HW_WIDTH_CONTROL
  • TS3TW : DMI_HW_WIDTH_CONTROL
  • TscDisableHwFixup : OVERCLOCKING_PREMEM_CONFIG
  • TsegSize : SA_MISC_PEI_PREMEM_CONFIG
  • TsLockTimer : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • TTEnable : THERMAL_THROTTLE_LEVELS
  • TTLevels : THERMAL_CONFIG
  • TTLock : THERMAL_THROTTLE_LEVELS
  • TTState13Enable : THERMAL_THROTTLE_LEVELS
  • TurboThermalProtection : OVERCLOCKING_PREMEM_CONFIG
  • TvbConfigLimitSelect : OVERCLOCKING_PREMEM_CONFIG
  • TvbRatioClipping : OVERCLOCKING_PREMEM_CONFIG
  • TvbVoltageOptimization : OVERCLOCKING_PREMEM_CONFIG
  • Tx : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • Txiset : USB2_PHY_PARAMETERS
  • TxtImplemented : SA_MISC_PEI_PREMEM_CONFIG
  • Type : FSP_ERROR_INFO_HOB


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- u -

  • UartDeviceConfig : SERIAL_IO_CONFIG
  • UnConfigureMe : AMT_DXE_CONFIG
  • UnderVoltProtection : OVERCLOCKING_PREMEM_CONFIG
  • UnsupportedRequestReport : TCSS_PCIE_PORT_POLICY
  • Usage : PCH_PCIE_CLOCK
  • Usb2PhySusPgEnable : PCH_PM_CONFIG
  • Usb4CmMode : _ITBT_GENERIC_CONFIG
  • UsbConfig : TCSS_PEI_CONFIG
  • UsbOverride : IOM_INTERFACE_CONFIG
  • UsbProvision : AMT_DXE_CONFIG
  • UsbTcConfig : TCSS_PEI_PREMEM_CONFIG
  • UsbTcPortEn : TCSS_USBTC_PEI_PERMEM_CONFIG
  • UserBd : SA_MISC_PEI_PREMEM_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- v -

  • V1p05IsExtFetControlEn : PCH_PM_CONFIG
  • V1p05PhyExtFetControlEn : PCH_PM_CONFIG
  • Value : FSP_ERROR_INFO_HOB
  • VcciaBootVoltageSel : OVERCLOCKING_PREMEM_CONFIG
  • VccinAux : PCH_FIVR_CONFIG
  • VccsaBootVoltageSel : OVERCLOCKING_PREMEM_CONFIG
  • VccSt : IOM_INTERFACE_CONFIG
  • VcType : HDAUDIO_PREMEM_CONFIG
  • VendorId : HDA_VERB_TABLE_HEADER , PCIE_DEVICE_OVERRIDE
  • Version : EFI_HOB_HANDOFF_INFO_TABLE
  • VmdCfgBarBase : VMD_PEI_CONFIG
  • VmdEnable : VMD_PEI_CONFIG
  • VmdGlobalMapping : VMD_PEI_CONFIG
  • VmdMemBar1Base : VMD_PEI_CONFIG
  • VmdMemBar2Base : VMD_PEI_CONFIG
  • VmdPortEnable : VMD_PEI_CONFIG
  • VmdVariablePtr : VMD_PEI_CONFIG
  • Voltage : FIVR_EXT_RAIL_CONFIG
  • VppAddress : PCH_PCIE_ROOT_PORT_CONFIG
  • VppPort : PCH_PCIE_ROOT_PORT_CONFIG
  • VrLimitBypass : OVERCLOCKING_PREMEM_CONFIG
  • VtdEnabled : PCH_GENERAL_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- w -

  • WakeConfig : PCH_PM_CONFIG
  • WakeOnTouch : THC_PORT
  • WatchDogEnabled : AMT_PEI_CONFIG
  • WatchDogTimerBios : AMT_PEI_CONFIG
  • WatchDogTimerOs : AMT_PEI_CONFIG
  • WolEnableOverride : PCH_WAKE_CONFIG
  • WolOvrWkSts : PCH_PM_CONFIG
  • WoWlanDeepSxEnable : PCH_WAKE_CONFIG
  • WoWlanEnable : PCH_WAKE_CONFIG
  • WriteOpcode : THC_HID_OVER_SPI
  • WriteProtectionEnable : PROTECTED_RANGE


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- z -

  • ZpOdd : PCH_SATA_PORT_CONFIG


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
File List
Here is a list of all documented files with brief descriptions:
AdrConfig.h | ADR policy
AmtConfig.h | AMT Config Block for PEI/DXE phase
Base.h | Root include file for Mde Package Base type modules
CnviConfig.h | CNVi policy
ConfigBlock.h | Header file for Config Block Lib implementation
ConfigBlockLib.h | Header file for Config Block Lib implementation
CpuPowerMgmtVrConfig.h | CPU Power Management VR Config Block
DciConfig.h | Dci policy
EspiConfig.h | Espi policy
FivrConfig.h | PCH FIVR policy
FlashProtectionConfig.h | FlashProtection policy
FspErrorInfo.h | FSP Error Information HOB to describe errors inside FSP that bootloader may take some actions to handle those error scenarios
FspFixedPcds.h | This file lists all FixedAtBuild PCDs referenced in FSP integration guide
FspmArchConfigPpi.h | Header file for FSP-M Arch Config PPI
GbeConfig.h | Gigabit Ethernet policy
GnaConfig.h | Policy definition for GNA Config Block
GpioConfig.h | Header file for GpioConfig structure used by GPIO library
GpioSampleDef.h | Copyright (c) 2015 - 2017, Intel Corporation
HdAudioConfig.h | HDAUDIO policy
HostBridgeConfig.h | Configurations for HostBridge
HsioConfig.h | HSIO policy
HsioPcieConfig.h | HSIO pcie policy
HsioSataConfig.h | Hsio Sata policy
HybridGraphicsConfig.h | Hybrid Graphics policy definitions
IehConfig.h | Integrated Error Handler policy
InterruptConfig.h | Interrupt policy
IoApicConfig.h | IoApic policy
IpuPreMemConfig.h | IPU policy definitions
IshConfig.h | ISH policy
LpcConfig.h | Lpc policy
MePeiConfig.h | ME config block for PEI phase
MpServices.h | This file declares UEFI PI Multi-processor PPI
OverclockingConfig.h | Overclocking Config Block
P2sbConfig.h | P2sb policy
PchDmiConfig.h | DMI policy
PchGeneralConfig.h | PCH General policy
PchPcieRpConfig.h | PCH Pcie root port policy
PcieConfig.h | PCIe Config Block
PciePreMemConfig.h | PCIe Config Block PreMem
PeiITbtConfig.h | Header file for TBT PEI Policy
PeiITbtGenericStructure.h | ITBT Policy definition to be referred in both PEI and DXE phase
PeiPreMemSiDefaultPolicy.h | This file defines the function to initialize default silicon policy PPI
PeiSiDefaultPolicy.h | This file defines the function to initialize default silicon policy PPI
PiHob.h | HOB related definitions in PI
PiMultiPhase.h | Include file matches things in PI for multiple module types
PmConfig.h | Power Management policy
RstConfig.h | Rst policy
RtcConfig.h | RTC policy
SaMiscPeiPreMemConfig.h | Policy details for miscellaneous configuration in System Agent
SataConfig.h | Sata policy
SerialIoConfig.h | Serial IO policy
SerialIoDevices.h | Serial IO policy
SiConfig.h | Si Config Block
SiPolicy.h | Silicon Policy PPI is used for specifying platform related Intel silicon information and policy setting
SiPolicyStruct.h | Intel reference code configuration policies
SiPreMemConfig.h | Si Config Block PreMem
SmbusConfig.h | Smbus policy
TcssPeiConfig.h | TCSS PEI policy
TcssPeiPreMemConfig.h | TCSS PEI PreMem policy
TelemetryPeiConfig.h | Configurations for Telemetry
ThcConfig.h | Touch Host Controller policy
ThermalConfig.h | Thermal policy
TraceHubConfig.h | Configurations for TraceHub
TsnConfig.h | TSN Config policy
UefiBaseType.h | Defines data types and constants introduced in UEFI
Usb2PhyConfig.h | USB2 PHY configuration policy
Usb3HsioConfig.h | USB3 Mod PHY configuration policy
UsbConfig.h | Common USB policy shared between PCH and CPU Contains general features settings for xHCI and xDCI
VmdPeiConfig.h | VMD PEI policy VMD Config Block
VtdConfig.h | VT-d policy definitions
WatchDogConfig.h | WatchDog policy


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: AdrConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Pmc
Classes
AdrConfig.h File Reference

ADR policy. More...

#include <ConfigBlock.h>
Include dependency graph for AdrConfig.h:

Go to the source code of this file.

Classes

union | ADR_GLOBAL_RESET_ENABLE
ADR Source Enable. More...
struct | ADR_CONFIG
ADR Configuration Revision 1: - Initial version. More...

Detailed Description

ADR policy.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file AdrConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: AdrConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Pmc
AdrConfig.h
Go to the documentation of this file.
1 /** @file
2 ADR policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _ADR_CONFIG_H_
36 #define _ADR_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 #define ADR_CONFIG_REVISION 1
41 extern EFI_GUID gAdrConfigGuid;
42
43 #pragma pack (push,1)
44
45 typedef enum {
46 AdrScale1us,
47 AdrScale10us,
48 AdrScale100us,
49 AdrScale1ms,
50 AdrScale10ms,
51 AdrScale100ms,
52 AdrScale1s,
53 AdrScale10s
54 } ADR_TIMER_SCALE;
55
56 /**
57 ADR Source Enable
58 **/
59 typedef union {
60 struct {
61 UINT32 Reserved1 : 1;
62 UINT32 AdrSrcPbo : 1;
63 UINT32 AdrSrcPmcUncErr : 1;
64 UINT32 AdrSrcPchThrm : 1;
65 UINT32 AdrSrcMePbo : 1;
66 UINT32 AdrSrcCpuThrm : 1;
67 UINT32 AdrSrcMegbl : 1;
68 UINT32 AdrSrcLtReset : 1;
69 UINT32 AdrSrcPmcWdt : 1;
70 UINT32 AdrSrcMeWdt : 1;
71 UINT32 AdrSrcPmcFw : 1;
72 UINT32 AdrSrcPchpwrFlr : 1;
73 UINT32 AdrSrcSyspwrFlr : 1;
74 UINT32 Reserved2 : 1;
75 UINT32 AdrSrcMiaUxsErr : 1;
76 UINT32 AdrSrcMiaUxErr : 1;
77 UINT32 AdrSrcCpuThrmWdt : 1;
78 UINT32 AdrSrcMeUncErr : 1;
79 UINT32 AdrSrcAdrGpio : 1;
80 UINT32 AdrSrcOcwdtNoicc : 1;
81 UINT32 AdrSrcOcwdtIcc : 1;
82 UINT32 AdrSrcCseHecUncErr : 1;
83 UINT32 AdrSrcPmcSramUncErr : 1;
84 UINT32 AdrSrcPmcIromParity : 1;
85 UINT32 AdrSrcPmcRfFusaErr : 1;
86 UINT32 Reserved3 : 4;
87 UINT32 AdrSrcPpbrParityErr : 1;
88 UINT32 Reserved4 : 2;
89 } Field;
90 UINT32 Value;
91 } ADR_GLOBAL_RESET_ENABLE;
92
93 /**
94 ADR Configuration
95 <b>Revision 1</b>: - Initial version.
96 **/
97 typedef struct {
98 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
99 UINT32 AdrEn : 2; ///< Determine if Adr is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
100 UINT32 AdrTimerEn : 2; ///< Determine if Adr timer options are enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
101 UINT32 AdrTimer1Val : 8; ///< Determines the Timeout value used for the ADR timer 1. A value of zero bypasses the timer
102 UINT32 AdrMultiplier1Val : 3; ///< Specifies the tick frequency upon which the timer 1 will increment. ADR_TIMER_SCALE should be used to encode values
103 UINT32 AdrTimer2Val : 8; ///< Determines the Timeout value used for the ADR timer 2. A value of zero bypasses the timer
104 UINT32 AdrMultiplier2Val : 3; ///< Specifies the tick frequency upon which the timer 2 will increment. ADR_TIMER_SCALE should be used to encode values
105 UINT32 AdrHostPartitionReset : 2; ///< Determine if Host Partition Reset is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
106 UINT32 AdrPlatAckEn : 2; ///< Determine if Platform Acknowledge is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
107 UINT32 ReservedBits : 2;
108 ADR_GLOBAL_RESET_ENABLE AdrSrcOff; ///< Determine which ADR sources are disabled. The code perform clearing bits in ADR Global Reset Enable register. This is first step.
109 ADR_GLOBAL_RESET_ENABLE AdrSrcOn; ///< Determine which ADR sources are enabled. The code perform setting bits in ADR Global Reset Enable register. This is second step.
110 } ADR_CONFIG;
111
112 #pragma pack (pop)
113
114 #endif // _ADR_CONFIG_H_
ADR_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: AdrConfig.h:98
ConfigBlock.h
Header file for Config Block Lib implementation.
ADR_GLOBAL_RESET_ENABLE
ADR Source Enable.
Definition: AdrConfig.h:59
ADR_CONFIG::AdrSrcOff
ADR_GLOBAL_RESET_ENABLE AdrSrcOff
Determine which ADR sources are disabled. The code perform clearing bits in ADR Global Reset Enable r...
Definition: AdrConfig.h:108
ADR_CONFIG::AdrHostPartitionReset
UINT32 AdrHostPartitionReset
Determine if Host Partition Reset is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
Definition: AdrConfig.h:105
ADR_CONFIG::AdrTimerEn
UINT32 AdrTimerEn
Determine if Adr timer options are enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
Definition: AdrConfig.h:100
ADR_CONFIG::AdrTimer1Val
UINT32 AdrTimer1Val
Determines the Timeout value used for the ADR timer 1. A value of zero bypasses the timer.
Definition: AdrConfig.h:101
ADR_CONFIG::AdrMultiplier2Val
UINT32 AdrMultiplier2Val
Specifies the tick frequency upon which the timer 2 will increment. ADR_TIMER_SCALE should be used to...
Definition: AdrConfig.h:104
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
ADR_CONFIG::AdrSrcOn
ADR_GLOBAL_RESET_ENABLE AdrSrcOn
Determine which ADR sources are enabled. The code perform setting bits in ADR Global Reset Enable reg...
Definition: AdrConfig.h:109
ADR_CONFIG::AdrPlatAckEn
UINT32 AdrPlatAckEn
Determine if Platform Acknowledge is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
Definition: AdrConfig.h:106
ADR_CONFIG
ADR Configuration Revision 1: - Initial version.
Definition: AdrConfig.h:97
ADR_CONFIG::AdrMultiplier1Val
UINT32 AdrMultiplier1Val
Specifies the tick frequency upon which the timer 1 will increment. ADR_TIMER_SCALE should be used to...
Definition: AdrConfig.h:102
ADR_CONFIG::AdrTimer2Val
UINT32 AdrTimer2Val
Determines the Timeout value used for the ADR timer 2. A value of zero bypasses the timer.
Definition: AdrConfig.h:103
ADR_CONFIG::AdrEn
UINT32 AdrEn
Determine if Adr is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
Definition: AdrConfig.h:99
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:46 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: AmtConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Amt
Classes | Typedefs | Enumerations
AmtConfig.h File Reference

AMT Config Block for PEI/DXE phase. More...

#include <Library/ConfigBlockLib.h>
#include <ConfigBlock.h>
Include dependency graph for AmtConfig.h:
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Classes

struct | AMT_PEI_CONFIG
AMT Pei Configuration Structure. More...
struct | AMT_DXE_CONFIG
AMT Dxe Configuration Structure. More...

Typedefs

typedef VOID(* AMT_REPORT_ERROR) (IN AMT_ERROR_MSG_ID MsgId)
Show AMT Error message. More...

Enumerations

enum AMT_ERROR_MSG_ID
AMT Error Message ID.

Detailed Description

AMT Config Block for PEI/DXE phase.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file AmtConfig.h.

Typedef Documentation

◆ AMT_REPORT_ERROR

typedef VOID(* AMT_REPORT_ERROR) (IN AMT_ERROR_MSG_ID MsgId)

Show AMT Error message.

This is to display localized message in the console. This is used to display message strings in local language. To display the message, the routine will check the message ID and ConOut the message strings. For example, the End of Post error displayed in English will be: gST->ConOut->OutputString (gST->ConOut, L"Error sending End Of Post message to ME\n"); It is recommended to clear the screen before displaying the error message and keep the message on the screen for several seconds. A sample is provided, see ShowAmtReportError () to retrieve details.

Parameters
[in] MsgId AMT error message ID for displaying on screen message

Definition at line 75 of file AmtConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: AmtConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Amt
AmtConfig.h
Go to the documentation of this file.
1 /** @file
2 AMT Config Block for PEI/DXE phase
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _AMT_CONFIG_H_
36 #define _AMT_CONFIG_H_
37
38 #include <Library/ConfigBlockLib.h>
39 #include <ConfigBlock.h>
40
41 #define AMT_PEI_CONFIG_REVISION 1
42 extern EFI_GUID gAmtPeiConfigGuid;
43
44 #define AMT_DXE_CONFIG_REVISION 1
45 extern EFI_GUID gAmtDxeConfigGuid;
46
47 ///
48 /// AMT Error Message ID
49 ///
50 typedef enum {
51 MSG_ASF_BOOT_DISK_MISSING,
52 MSG_KVM_TIMES_UP,
53 MSG_KVM_REJECTED,
54 MSG_KVM_WAIT,
55 MAX_AMT_ERROR_ENUM
56 } AMT_ERROR_MSG_ID;
57
58 /**
59 Show AMT Error message. This is to display localized message in
60 the console. This is used to display message strings in local
61 language. To display the message, the routine will check the
62 message ID and ConOut the message strings. For example, the
63 End of Post error displayed in English will be:
64 gST->ConOut->OutputString (gST->ConOut, L"Error sending End Of
65 Post message to ME\n"); It is recommended to clear the screen
66 before displaying the error message and keep the message on
67 the screen for several seconds.
68 A sample is provided, see ShowAmtReportError () to retrieve
69 details.
70
71 @param[in] MsgId AMT error message ID for displaying on screen message
72
73 **/
74 typedef
75 VOID
76 (*AMT_REPORT_ERROR) (
77 IN AMT_ERROR_MSG_ID MsgId
78 );
79
80
81 #pragma pack (1)
82
83 /**
84 AMT Pei Configuration Structure.
85
86 <b>Revision 1</b>:
87 - Initial version.
88 **/
89 typedef struct {
90 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
91 /**
92 Enable or Disable Intel Active Management Technology feature.
93 If disabled, all Intel AMT features, including Alert Standard Format features, will not be supported.
94 0: Disable
95 <b>1: Enable.</b>
96 **/
97 UINT32 AmtEnabled : 1;
98 /**
99 ME WatchDog timer feature. If disabled, below WatchDogTimerOs/WatchDogTimerBios will be irrelevant.
100 See WatchDogTimerOs and WatchDogTimerBios description.
101 <b>0: Disable</b>
102 1: Enable ME WDT if corresponding timer value is not zero.
103 **/
104 UINT32 WatchDogEnabled : 1;
105 UINT32 FwProgress : 1; ///< PET Events Progress to receive PET Events. 0: Disable; <b>1: Enable</b>
106 UINT32 AmtSolEnabled : 1; ///< Serial Over Lan retrieved from Mebx. The default value depends on CSME/AMT. 0: Disable, <b>1: Enable</b>
107 UINT32 RsvdBits : 28; ///< Reserved for future use & Config block alignment
108 /**
109 OS WatchDog Timer
110 <b>0: Disable</b> OS WDT won't be started after stopping BIOS WDT even if WatchDogEnabled is 1.
111 Non zero value - OS WDT will be started after stopping BIOS WDT if WatchDogEnabled is 1. The timer is set
112 according to the value.
113 **/
114 UINT16 WatchDogTimerOs;
115 /**
116 BIOS WatchDog Timer
117 <b>0: Disable</b> BIOS WDT won't be started even if WatchDogEnabled is 1.
118 Non zero value - The BIOS WDT is set according to the value and started if WatchDogEnabled is 1.
119 **/
120 UINT16 WatchDogTimerBios;
121 } AMT_PEI_CONFIG;
122
123
124 /**
125 AMT Dxe Configuration Structure.
126
127 <b>Revision 1</b>:
128 - Initial version.
129 **/
130 typedef struct {
131 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
132 UINT32 CiraRequest : 1; ///< Trigger CIRA boot. <b>0: No CIRA request</b>; 1: Trigger CIRA request
133 UINT32 UnConfigureMe : 1; ///< OEMFlag Bit 15: Unconfigure ME with resetting MEBx password to default. <b>0: No</b>; 1: Un-configure ME without password
134 UINT32 UsbProvision : 1; ///< Enable/Disable of AMT USB Provisioning. <b>0: Disable</b>; 1: Enable
135 UINT32 RsvdBits : 29; ///< Reserved for future use & Config block alignment
136 /**
137 Function pointer for displaying error message on screen
138 **/
139 AMT_REPORT_ERROR AmtReportError;
140 } AMT_DXE_CONFIG;
141
142 #pragma pack ()
143
144 #endif // _AMT_CONFIG_H_
AMT_PEI_CONFIG::FwProgress
UINT32 FwProgress
PET Events Progress to receive PET Events. 0: Disable; 1: Enable
Definition: AmtConfig.h:105
ConfigBlock.h
Header file for Config Block Lib implementation.
AMT_DXE_CONFIG::CiraRequest
UINT32 CiraRequest
Trigger CIRA boot. 0: No CIRA request; 1: Trigger CIRA request.
Definition: AmtConfig.h:132
IN
#define IN
Datum is passed to the function.
Definition: Base.h:279
AMT_PEI_CONFIG
AMT Pei Configuration Structure.
Definition: AmtConfig.h:89
AMT_PEI_CONFIG::AmtSolEnabled
UINT32 AmtSolEnabled
Serial Over Lan retrieved from Mebx. The default value depends on CSME/AMT. 0: Disable,...
Definition: AmtConfig.h:106
AMT_DXE_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use & Config block alignment.
Definition: AmtConfig.h:135
AMT_PEI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: AmtConfig.h:90
AMT_PEI_CONFIG::AmtEnabled
UINT32 AmtEnabled
Enable or Disable Intel Active Management Technology feature.
Definition: AmtConfig.h:97
VOID
#define VOID
Undeclared type.
Definition: Base.h:269
AMT_ERROR_MSG_ID
AMT_ERROR_MSG_ID
AMT Error Message ID.
Definition: AmtConfig.h:50
AMT_PEI_CONFIG::WatchDogTimerOs
UINT16 WatchDogTimerOs
OS WatchDog Timer 0: Disable OS WDT won't be started after stopping BIOS WDT even if WatchDogEnabled ...
Definition: AmtConfig.h:114
AMT_REPORT_ERROR
VOID(* AMT_REPORT_ERROR)(IN AMT_ERROR_MSG_ID MsgId)
Show AMT Error message.
Definition: AmtConfig.h:76
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
AMT_DXE_CONFIG::UsbProvision
UINT32 UsbProvision
Enable/Disable of AMT USB Provisioning. 0: Disable; 1: Enable.
Definition: AmtConfig.h:134
ConfigBlockLib.h
Header file for Config Block Lib implementation.
AMT_DXE_CONFIG::AmtReportError
AMT_REPORT_ERROR AmtReportError
Function pointer for displaying error message on screen.
Definition: AmtConfig.h:139
AMT_PEI_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use & Config block alignment.
Definition: AmtConfig.h:107
AMT_DXE_CONFIG::UnConfigureMe
UINT32 UnConfigureMe
OEMFlag Bit 15: Unconfigure ME with resetting MEBx password to default. 0: No; 1: Un-configure ME wit...
Definition: AmtConfig.h:133
AMT_PEI_CONFIG::WatchDogEnabled
UINT32 WatchDogEnabled
ME WatchDog timer feature.
Definition: AmtConfig.h:104
AMT_PEI_CONFIG::WatchDogTimerBios
UINT16 WatchDogTimerBios
BIOS WatchDog Timer 0: Disable BIOS WDT won't be started even if WatchDogEnabled is 1.
Definition: AmtConfig.h:120
AMT_DXE_CONFIG
AMT Dxe Configuration Structure.
Definition: AmtConfig.h:130
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
AMT_DXE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: AmtConfig.h:131
Generated on Mon Dec 29 2025 02:15:46 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Base.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Edk2
  • MdePkg
  • Include
Classes | Macros | Typedefs
Base.h File Reference

Root include file for Mde Package Base type modules. More...

#include <ProcessorBind.h>
Include dependency graph for Base.h:
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Classes

struct | GUID
128 bit buffer containing a unique identifier value. More...
struct | IPv4_ADDRESS
4-byte buffer. More...
struct | IPv6_ADDRESS
16-byte buffer. More...
struct | _LIST_ENTRY
_LIST_ENTRY structure definition. More...

Macros

#define | GLOBAL_REMOVE_IF_UNREFERENCED
Remove the global variable from the linked image if there are no references to it after all compiler and linker optimizations have been performed.
#define | UNREACHABLE()
Signal compilers and analyzers that this call is not reachable. More...
#define | NORETURN
Signal compilers and analyzers that the function cannot return. More...
#define | ANALYZER_UNREACHABLE()
Signal the analyzer that this call is not reachable. More...
#define | ANALYZER_NORETURN
Signal the analyzer that the function cannot return. More...
#define | RETURNS_TWICE
Tell the code optimizer that the function will return twice. More...
#define | _CONCATENATE(a, b) __CONCATENATE(a, b)
Private worker functions for ASM_PFX()
#define | ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name)
The USER_LABEL_PREFIX macro predefined by GNUC represents the prefix on symbols in assembly language.
#define | CONST const
Datum is read-only.
#define | STATIC static
Datum is scoped to the current file or function.
#define | VOID void
Undeclared type.
#define | IN
Datum is passed to the function.
#define | OUT
Datum is returned from the function.
#define | OPTIONAL
Passing the datum to the function is optional, and a NULL is passed if the value is not supplied.
#define | TRUE ((BOOLEAN)(1==1))
Boolean true value. More...
#define | FALSE ((BOOLEAN)(0==1))
Boolean false value. More...
#define | NULL ((VOID *) 0)
NULL pointer (VOID *)
#define | MAX_INT8 ((INT8)0x7F)
Maximum values for common UEFI Data Types.
#define | MIN_INT8 (((INT8) -127) - 1)
Minimum values for the signed UEFI Data Types.
#define | _INT_SIZE_OF(n) ((sizeof (n) + sizeof (UINTN) - 1) &~(sizeof (UINTN) - 1))
Return the size of argument that has been aligned to sizeof (UINTN). More...
#define | VA_START(Marker, Parameter) (Marker = (VA_LIST) ((UINTN) & (Parameter) + _INT_SIZE_OF (Parameter)))
Retrieves a pointer to the beginning of a variable argument list, based on the name of the parameter that immediately precedes the variable argument list. More...
#define | VA_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _INT_SIZE_OF (TYPE)) - _INT_SIZE_OF (TYPE)))
Returns an argument of a specified type from a variable argument list and updates the pointer to the variable argument list to point to the next argument. More...
#define | VA_END(Marker) (Marker = (VA_LIST) 0)
Terminates the use of a variable argument list. More...
#define | VA_COPY(Dest, Start) ((void)((Dest) = (Start)))
Initializes a VA_LIST as a copy of an existing VA_LIST. More...
#define | _BASE_INT_SIZE_OF(TYPE) ((sizeof (TYPE) + sizeof (UINTN) - 1) / sizeof (UINTN))
Returns the size of a data type in sizeof(UINTN) units rounded up to the nearest UINTN boundary. More...
#define | BASE_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _BASE_INT_SIZE_OF (TYPE)) - _BASE_INT_SIZE_OF (TYPE)))
Returns an argument of a specified type from a variable argument list and updates the pointer to the variable argument list to point to the next argument. More...
#define | OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field))
The macro that returns the byte offset of a field in a data structure. More...
#define | ALIGNOF(TYPE) OFFSET_OF (struct { CHAR8 C; TYPE A; }, A)
Returns the alignment requirement of a type. More...
#define | STATIC_ASSERT _Static_assert
Portable definition for compile time assertions. More...
#define | BASE_CR(Record, TYPE, Field) ((TYPE *) ((CHAR8 *) (Record) - OFFSET_OF (TYPE, Field)))
Macro that returns a pointer to the data structure that contains a specified field of that data structure. More...
#define | IS_POW2(Value) ((Value) != 0U && ((Value) & ((Value) - 1U)) == 0U)
Checks whether a value is a power of two. More...
#define | IS_ALIGNED(Value, Alignment) (((Value) & ((Alignment) - 1U)) == 0U)
Checks whether a value is aligned by a specified alignment. More...
#define | ADDRESS_IS_ALIGNED(Address, Alignment) IS_ALIGNED ((UINTN) (Address), Alignment)
Checks whether a pointer or address is aligned by a specified alignment. More...
#define | ALIGN_VALUE_ADDEND(Value, Alignment) (((Alignment) - (Value)) & ((Alignment) - 1U))
Determines the addend to add to a value to round it up to the next boundary of a specified alignment. More...
#define | ALIGN_VALUE(Value, Alignment) ((Value) + ALIGN_VALUE_ADDEND (Value, Alignment))
Rounds a value up to the next boundary using a specified alignment. More...
#define | ALIGN_POINTER(Pointer, Alignment) ((VOID *) (ALIGN_VALUE ((UINTN)(Pointer), (Alignment))))
Adjust a pointer by adding the minimum offset required for it to be aligned on a specified alignment boundary. More...
#define | ALIGN_VARIABLE(Value) ALIGN_VALUE ((Value), sizeof (UINTN))
Rounds a value up to the next natural boundary for the current CPU. More...
#define | MAX(a, b) (((a) > (b)) ? (a) : (b))
Return the maximum of two operands. More...
#define | MIN(a, b) (((a) < (b)) ? (a) : (b))
Return the minimum of two operands. More...
#define | ABS(a) (((a) < 0) ? (-(a)) : (a))
Return the absolute value of a signed operand. More...
#define | ENCODE_ERROR(StatusCode) ((RETURN_STATUS)(MAX_BIT | (StatusCode)))
Produces a RETURN_STATUS code with the highest bit set. More...
#define | ENCODE_WARNING(StatusCode) ((RETURN_STATUS)(StatusCode))
Produces a RETURN_STATUS code with the highest bit clear. More...
#define | RETURN_ERROR(StatusCode) (((INTN)(RETURN_STATUS)(StatusCode)) < 0)
Returns TRUE if a specified RETURN_STATUS code is an error code. More...
#define | RETURN_SUCCESS (RETURN_STATUS)(0)
The operation completed successfully.
#define | RETURN_LOAD_ERROR ENCODE_ERROR (1)
The image failed to load.
#define | RETURN_INVALID_PARAMETER ENCODE_ERROR (2)
The parameter was incorrect.
#define | RETURN_UNSUPPORTED ENCODE_ERROR (3)
The operation is not supported.
#define | RETURN_BAD_BUFFER_SIZE ENCODE_ERROR (4)
The buffer was not the proper size for the request.
#define | RETURN_BUFFER_TOO_SMALL ENCODE_ERROR (5)
The buffer was not large enough to hold the requested data. More...
#define | RETURN_NOT_READY ENCODE_ERROR (6)
There is no data pending upon return.
#define | RETURN_DEVICE_ERROR ENCODE_ERROR (7)
The physical device reported an error while attempting the operation.
#define | RETURN_WRITE_PROTECTED ENCODE_ERROR (8)
The device can not be written to.
#define | RETURN_OUT_OF_RESOURCES ENCODE_ERROR (9)
The resource has run out.
#define | RETURN_VOLUME_CORRUPTED ENCODE_ERROR (10)
An inconsistency was detected on the file system causing the operation to fail.
#define | RETURN_VOLUME_FULL ENCODE_ERROR (11)
There is no more space on the file system.
#define | RETURN_NO_MEDIA ENCODE_ERROR (12)
The device does not contain any medium to perform the operation.
#define | RETURN_MEDIA_CHANGED ENCODE_ERROR (13)
The medium in the device has changed since the last access.
#define | RETURN_NOT_FOUND ENCODE_ERROR (14)
The item was not found.
#define | RETURN_ACCESS_DENIED ENCODE_ERROR (15)
Access was denied.
#define | RETURN_NO_RESPONSE ENCODE_ERROR (16)
The server was not found or did not respond to the request.
#define | RETURN_NO_MAPPING ENCODE_ERROR (17)
A mapping to the device does not exist.
#define | RETURN_TIMEOUT ENCODE_ERROR (18)
A timeout time expired.
#define | RETURN_NOT_STARTED ENCODE_ERROR (19)
The protocol has not been started.
#define | RETURN_ALREADY_STARTED ENCODE_ERROR (20)
The protocol has already been started.
#define | RETURN_ABORTED ENCODE_ERROR (21)
The operation was aborted.
#define | RETURN_ICMP_ERROR ENCODE_ERROR (22)
An ICMP error occurred during the network operation.
#define | RETURN_TFTP_ERROR ENCODE_ERROR (23)
A TFTP error occurred during the network operation.
#define | RETURN_PROTOCOL_ERROR ENCODE_ERROR (24)
A protocol error occurred during the network operation.
#define | RETURN_INCOMPATIBLE_VERSION ENCODE_ERROR (25)
A function encountered an internal version that was incompatible with a version requested by the caller.
#define | RETURN_SECURITY_VIOLATION ENCODE_ERROR (26)
The function was not performed due to a security violation.
#define | RETURN_CRC_ERROR ENCODE_ERROR (27)
A CRC error was detected.
#define | RETURN_END_OF_MEDIA ENCODE_ERROR (28)
The beginning or end of media was reached.
#define | RETURN_END_OF_FILE ENCODE_ERROR (31)
The end of the file was reached.
#define | RETURN_INVALID_LANGUAGE ENCODE_ERROR (32)
The language specified was invalid.
#define | RETURN_COMPROMISED_DATA ENCODE_ERROR (33)
The security status of the data is unknown or compromised and the data must be updated or replaced to restore a valid security status.
#define | RETURN_HTTP_ERROR ENCODE_ERROR (35)
A HTTP error occurred during the network operation.
#define | RETURN_WARN_UNKNOWN_GLYPH ENCODE_WARNING (1)
The string contained one or more characters that the device could not render and were skipped.
#define | RETURN_WARN_DELETE_FAILURE ENCODE_WARNING (2)
The handle was closed, but the file was not deleted.
#define | RETURN_WARN_WRITE_FAILURE ENCODE_WARNING (3)
The handle was closed, but the data to the file was not flushed properly.
#define | RETURN_WARN_BUFFER_TOO_SMALL ENCODE_WARNING (4)
The resulting buffer was too small, and the data was truncated to the buffer size.
#define | RETURN_WARN_STALE_DATA ENCODE_WARNING (5)
The data has not been updated within the timeframe set by local policy for this type of data.
#define | RETURN_WARN_FILE_SYSTEM ENCODE_WARNING (6)
The resulting buffer contains UEFI-compliant file system.
#define | SIGNATURE_16(A, B) ((A) | (B << 8))
Returns a 16-bit signature built from 2 ASCII characters. More...
#define | SIGNATURE_32(A, B, C, D) (SIGNATURE_16 (A, B) | (SIGNATURE_16 (C, D) << 16))
Returns a 32-bit signature built from 4 ASCII characters. More...
#define | SIGNATURE_64(A, B, C, D, E, F, G, H) (SIGNATURE_32 (A, B, C, D) | ((UINT64) (SIGNATURE_32 (E, F, G, H)) << 32))
Returns a 64-bit signature built from 8 ASCII characters. More...
#define | RETURN_ADDRESS(L) ((VOID *) 0)
Get the return address of the calling function. More...
#define | ARRAY_SIZE(Array) (sizeof (Array) / sizeof ((Array)[0]))
Return the number of elements in an array. More...

Typedefs

typedef struct _LIST_ENTRY | LIST_ENTRY
LIST_ENTRY structure definition.
typedef CHAR8 * | VA_LIST
Variable used to traverse the list of arguments. More...
typedef UINTN * | BASE_LIST
Pointer to the start of a variable argument list stored in a memory buffer. More...

Detailed Description

Root include file for Mde Package Base type modules.

This is the include file for any module of type base. Base modules only use types defined via this include file and can be ported easily to any environment. There are a set of base libraries in the Mde Package that can be used to implement base modules.

Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file Base.h.

Macro Definition Documentation

◆ _BASE_INT_SIZE_OF

#define _BASE_INT_SIZE_OF ( TYPE ) ((sizeof (TYPE) + sizeof (UINTN) - 1) / sizeof (UINTN))

Returns the size of a data type in sizeof(UINTN) units rounded up to the nearest UINTN boundary.

Parameters
TYPE The date type to determine the size of.
Returns
The size of TYPE in sizeof (UINTN) units rounded up to the nearest UINTN boundary.

Definition at line 720 of file Base.h.

◆ _INT_SIZE_OF

#define _INT_SIZE_OF ( n ) ((sizeof (n) + sizeof (UINTN) - 1) &~(sizeof (UINTN) - 1))

Return the size of argument that has been aligned to sizeof (UINTN).

Parameters
n The parameter size to be aligned.
Returns
The aligned size.

Definition at line 579 of file Base.h.

◆ ABS

#define ABS ( a ) (((a) < 0) ? (-(a)) : (a))

Return the absolute value of a signed operand.

This macro returns the absolute value of the signed operand specified by a.

Parameters
a The signed operand.
Returns
The absolute value of the signed operand.

Definition at line 1020 of file Base.h.

◆ ADDRESS_IS_ALIGNED

#define ADDRESS_IS_ALIGNED | ( | Address,
 |  | Alignment
 | ) | IS_ALIGNED ((UINTN) (Address), Alignment)

Checks whether a pointer or address is aligned by a specified alignment.

Parameters
Address | The pointer or address to check.
Alignment | The alignment boundary used to check against.
Return values
TRUE | Address is aligned by Alignment.
FALSE | Address is not aligned by Alignment.

Definition at line 923 of file Base.h.

◆ ALIGN_POINTER

#define ALIGN_POINTER | ( | Pointer,
 |  | Alignment
 | ) | ((VOID *) (ALIGN_VALUE ((UINTN)(Pointer), (Alignment))))

Adjust a pointer by adding the minimum offset required for it to be aligned on a specified alignment boundary.

This function rounds the pointer specified by Pointer to the next alignment boundary specified by Alignment. The pointer to the aligned address is returned.

Parameters
Pointer | The pointer to round up.
Alignment | The alignment boundary to use to return an aligned pointer.
Returns
Pointer to the aligned address.

Definition at line 963 of file Base.h.

◆ ALIGN_VALUE

#define ALIGN_VALUE | ( | Value,
 |  | Alignment
 | ) | ((Value) + ALIGN_VALUE_ADDEND (Value, Alignment))

Rounds a value up to the next boundary using a specified alignment.

This function rounds Value up to the next boundary using the specified Alignment. This aligned value is returned.

Parameters
Value | The value to round up.
Alignment | The alignment boundary used to return the aligned value.
Returns
A value up to the next boundary.

Definition at line 948 of file Base.h.

◆ ALIGN_VALUE_ADDEND

#define ALIGN_VALUE_ADDEND | ( | Value,
 |  | Alignment
 | ) | (((Alignment) - (Value)) & ((Alignment) - 1U))

Determines the addend to add to a value to round it up to the next boundary of a specified alignment.

Parameters
Value | The value to round up.
Alignment | The alignment boundary used to return the addend.
Returns
Addend to round Value up to alignment boundary Alignment.

Definition at line 934 of file Base.h.

◆ ALIGN_VARIABLE

#define ALIGN_VARIABLE ( Value ) ALIGN_VALUE ((Value), sizeof (UINTN))

Rounds a value up to the next natural boundary for the current CPU.

This is 4-bytes for 32-bit CPUs and 8-bytes for 64-bit CPUs.

This function rounds the value specified by Value up to the next natural boundary for the current CPU. This rounded value is returned.

Parameters
Value The value to round up.
Returns
Rounded value specified by Value.

Definition at line 977 of file Base.h.

◆ ALIGNOF

#define ALIGNOF ( TYPE ) OFFSET_OF (struct { CHAR8 C; TYPE A; }, A)

Returns the alignment requirement of a type.

Parameters
TYPE The name of the type to retrieve the alignment requirement of.
Returns
Alignment requirement, in Bytes, of TYPE.

Definition at line 792 of file Base.h.

◆ ANALYZER_NORETURN

#define ANALYZER_NORETURN

Signal the analyzer that the function cannot return.

This excludes compilers.

Definition at line 157 of file Base.h.

◆ ANALYZER_UNREACHABLE

#define ANALYZER_UNREACHABLE ( )

Signal the analyzer that this call is not reachable.

This excludes compilers.

Definition at line 131 of file Base.h.

◆ ARRAY_SIZE

#define ARRAY_SIZE ( Array ) (sizeof (Array) / sizeof ((Array)[0]))

Return the number of elements in an array.

Parameters
Array An object of array type. Array is only used as an argument to the sizeof operator, therefore Array is never evaluated. The caller is responsible for ensuring that Array's type is not incomplete; that is, Array must have known constant size.
Returns
The number of elements in Array. The result has type UINTN.

Definition at line 1383 of file Base.h.

◆ BASE_ARG

#define BASE_ARG | ( | Marker,
 |  | TYPE
 | ) | (*(TYPE *) ((Marker += _BASE_INT_SIZE_OF (TYPE)) - _BASE_INT_SIZE_OF (TYPE)))

Returns an argument of a specified type from a variable argument list and updates the pointer to the variable argument list to point to the next argument.

This function returns an argument of the type specified by TYPE from the beginning of the variable argument list specified by Marker. Marker is then updated to point to the next argument in the variable argument list. The method for computing the pointer to the next argument in the argument list is CPU specific following the EFIAPI ABI.

Parameters
Marker | The pointer to the beginning of a variable argument list.
TYPE | The type of argument to retrieve from the beginning of the variable argument list.
Returns
An argument of the type specified by TYPE.

Definition at line 738 of file Base.h.

◆ BASE_CR

#define BASE_CR | ( | Record,
 |  | TYPE,
 |  | Field
 | ) | ((TYPE *) ((CHAR8 *) (Record) - OFFSET_OF (TYPE, Field)))

Macro that returns a pointer to the data structure that contains a specified field of that data structure.

This is a lightweight method to hide information by placing a public data structure inside a larger private data structure and using a pointer to the public data structure to retrieve a pointer to the private data structure.

This function computes the offset, in bytes, of field specified by Field from the beginning of the data structure specified by TYPE. This offset is subtracted from Record, and is used to return a pointer to a data structure of the type specified by TYPE. If the data type specified by TYPE does not contain the field specified by Field, then the module will not compile.

Parameters
Record | Pointer to the field specified by Field within a data structure of type TYPE.
TYPE | The name of the data structure type to return. This data structure must contain the field specified by Field.
Field | The name of the field in the data structure specified by TYPE to which Record points.
Returns
A pointer to the structure from one of it's elements.

Definition at line 891 of file Base.h.

◆ ENCODE_ERROR

#define ENCODE_ERROR ( StatusCode ) ((RETURN_STATUS)(MAX_BIT | (StatusCode)))

Produces a RETURN_STATUS code with the highest bit set.

Parameters
StatusCode The status code value to convert into a warning code. StatusCode must be in the range 0x00000000..0x7FFFFFFF.
Returns
The value specified by StatusCode with the highest bit set.

Definition at line 1037 of file Base.h.

◆ ENCODE_WARNING

#define ENCODE_WARNING ( StatusCode ) ((RETURN_STATUS)(StatusCode))

Produces a RETURN_STATUS code with the highest bit clear.

Parameters
StatusCode The status code value to convert into a warning code. StatusCode must be in the range 0x00000000..0x7FFFFFFF.
Returns
The value specified by StatusCode with the highest bit clear.

Definition at line 1048 of file Base.h.

◆ FALSE

#define FALSE ((BOOLEAN)(0==1))

Boolean false value.

UEFI Specification defines this value to be 0, but this form is more portable.

Definition at line 307 of file Base.h.

◆ IS_ALIGNED

#define IS_ALIGNED | ( | Value,
 |  | Alignment
 | ) | (((Value) & ((Alignment) - 1U)) == 0U)

Checks whether a value is aligned by a specified alignment.

Parameters
Value | The value to check.
Alignment | The alignment boundary used to check against.
Return values
TRUE | Value is aligned by Alignment.
FALSE | Value is not aligned by Alignment.

Definition at line 912 of file Base.h.

◆ IS_POW2

#define IS_POW2 ( Value ) ((Value) != 0U && ((Value) & ((Value) - 1U)) == 0U)

Checks whether a value is a power of two.

Parameters
Value The value to check.
Return values
TRUE | Value is a power of two.
FALSE | Value is not a power of two.

Definition at line 901 of file Base.h.

◆ MAX

#define MAX | ( | a,
 |  | b
 | ) | (((a) > (b)) ? (a) : (b))

Return the maximum of two operands.

This macro returns the maximum of two operand specified by a and b. Both a and b must be the same numerical types, signed or unsigned.

Parameters
a | The first operand with any numerical type.
b | The second operand. Can be any numerical type as long as is the same type as a.
Returns
Maximum of two operands.

Definition at line 992 of file Base.h.

◆ MIN

#define MIN | ( | a,
 |  | b
 | ) | (((a) < (b)) ? (a) : (b))

Return the minimum of two operands.

This macro returns the minimal of two operand specified by a and b. Both a and b must be the same numerical types, signed or unsigned.

Parameters
a | The first operand with any numerical type.
b | The second operand. It should be the same any numerical type with a.
Returns
Minimum of two operands.

Definition at line 1007 of file Base.h.

◆ NORETURN

#define NORETURN

Signal compilers and analyzers that the function cannot return.

It is up to the compiler to remove any code past a call to functions flagged with this attribute.

Definition at line 107 of file Base.h.

◆ OFFSET_OF

#define OFFSET_OF | ( | TYPE,
 |  | Field
 | ) | ((UINTN) &(((TYPE *)0)->Field))

The macro that returns the byte offset of a field in a data structure.

This function returns the offset, in bytes, of field specified by Field from the beginning of the data structure specified by TYPE. If TYPE does not contain Field, the module will not compile.

Parameters
TYPE | The name of the data structure that contains the field specified by Field.
Field | The name of the field in the data structure.
Returns
Offset, in bytes, of field.

Definition at line 758 of file Base.h.

◆ RETURN_ADDRESS

#define RETURN_ADDRESS ( L ) ((VOID *) 0)

Get the return address of the calling function.

Parameters
L Return Level.
Returns
0 as compilers don't support this feature.

Definition at line 1369 of file Base.h.

◆ RETURN_BUFFER_TOO_SMALL

#define RETURN_BUFFER_TOO_SMALL ENCODE_ERROR (5)

The buffer was not large enough to hold the requested data.

The required buffer size is returned in the appropriate parameter when this error occurs.

Definition at line 1093 of file Base.h.

◆ RETURN_ERROR

#define RETURN_ERROR ( StatusCode ) (((INTN)(RETURN_STATUS)(StatusCode)) < 0)

Returns TRUE if a specified RETURN_STATUS code is an error code.

This function returns TRUE if StatusCode has the high bit set. Otherwise, FALSE is returned.

Parameters
StatusCode The status code value to evaluate.
Return values
TRUE | The high bit of StatusCode is set.
FALSE | The high bit of StatusCode is clear.

Definition at line 1061 of file Base.h.

◆ RETURNS_TWICE

#define RETURNS_TWICE

Tell the code optimizer that the function will return twice.

This prevents wrong optimizations which can cause bugs. Tell the code optimizer that the function will return twice. This prevents wrong optimizations which can cause bugs.

Definition at line 177 of file Base.h.

◆ SIGNATURE_16

#define SIGNATURE_16 | ( | A,
 |  | B
 | ) | ((A) | (B << 8))

Returns a 16-bit signature built from 2 ASCII characters.

This macro returns a 16-bit value built from the two ASCII characters specified by A and B.

Parameters
A | The first ASCII character.
B | The second ASCII character.
Returns
A 16-bit value built from the two ASCII characters specified by A and B.

Definition at line 1283 of file Base.h.

◆ SIGNATURE_32

#define SIGNATURE_32 | ( | A,
 |  | B,
 |  | C,
 |  | D
 | ) | (SIGNATURE_16 (A, B) | (SIGNATURE_16 (C, D) << 16))

Returns a 32-bit signature built from 4 ASCII characters.

This macro returns a 32-bit value built from the four ASCII characters specified by A, B, C, and D.

Parameters
A | The first ASCII character.
B | The second ASCII character.
C | The third ASCII character.
D | The fourth ASCII character.
Returns
A 32-bit value built from the two ASCII characters specified by A, B, C and D.

Definition at line 1300 of file Base.h.

◆ SIGNATURE_64

#define SIGNATURE_64 | ( | A,
 |  | B,
 |  | C,
 |  | D,
 |  | E,
 |  | F,
 |  | G,
 |  | H
 | ) | (SIGNATURE_32 (A, B, C, D) | ((UINT64) (SIGNATURE_32 (E, F, G, H)) << 32))

Returns a 64-bit signature built from 8 ASCII characters.

This macro returns a 64-bit value built from the eight ASCII characters specified by A, B, C, D, E, F, G,and H.

Parameters
A | The first ASCII character.
B | The second ASCII character.
C | The third ASCII character.
D | The fourth ASCII character.
E | The fifth ASCII character.
F | The sixth ASCII character.
G | The seventh ASCII character.
H | The eighth ASCII character.
Returns
A 64-bit value built from the two ASCII characters specified by A, B, C, D, E, F, G and H.

Definition at line 1321 of file Base.h.

◆ STATIC_ASSERT

#define STATIC_ASSERT _Static_assert

Portable definition for compile time assertions.

Equivalent to C11 static_assert macro from assert.h.

Parameters
Expression | Boolean expression.
Message | Raised compiler diagnostic message when expression is false.

Definition at line 808 of file Base.h.

◆ TRUE

#define TRUE ((BOOLEAN)(1==1))

Boolean true value.

UEFI Specification defines this value to be 1, but this form is more portable.

Definition at line 301 of file Base.h.

◆ UNREACHABLE

#define UNREACHABLE ( )

Signal compilers and analyzers that this call is not reachable.

It is up to the compiler to remove any code past that point.

Definition at line 77 of file Base.h.

◆ VA_ARG

#define VA_ARG | ( | Marker,
 |  | TYPE
 | ) | (*(TYPE *) ((Marker += _INT_SIZE_OF (TYPE)) - _INT_SIZE_OF (TYPE)))

Returns an argument of a specified type from a variable argument list and updates the pointer to the variable argument list to point to the next argument.

This function returns an argument of the type specified by TYPE from the beginning of the variable argument list specified by Marker. Marker is then updated to point to the next argument in the variable argument list. The method for computing the pointer to the next argument in the argument list is CPU-specific following the EFIAPI ABI.

Parameters
Marker | VA_LIST used to traverse the list of arguments.
TYPE | The type of argument to retrieve from the beginning of the variable argument list.
Returns
An argument of the type specified by TYPE.

Definition at line 679 of file Base.h.

◆ VA_COPY

#define VA_COPY | ( | Dest,
 |  | Start
 | ) | ((void)((Dest) = (Start)))

Initializes a VA_LIST as a copy of an existing VA_LIST.

This macro initializes Dest as a copy of Start, as if the VA_START macro had been applied to Dest followed by the same sequence of uses of the VA_ARG macro as had previously been used to reach the present state of Start.

Parameters
Dest | VA_LIST used to traverse the list of arguments.
Start | VA_LIST used to traverse the list of arguments.

Definition at line 704 of file Base.h.

◆ VA_END

#define VA_END ( Marker ) (Marker = (VA_LIST) 0)

Terminates the use of a variable argument list.

This function initializes Marker so it can no longer be used with VA_ARG(). After this macro is used, the only way to access the variable argument list is by using VA_START() again.

Parameters
Marker VA_LIST used to traverse the list of arguments.

Definition at line 691 of file Base.h.

◆ VA_START

#define VA_START | ( | Marker,
 |  | Parameter
 | ) | (Marker = (VA_LIST) ((UINTN) & (Parameter) + _INT_SIZE_OF (Parameter)))

Retrieves a pointer to the beginning of a variable argument list, based on the name of the parameter that immediately precedes the variable argument list.

This function initializes Marker to point to the beginning of the variable argument list that immediately follows Parameter. The method for computing the pointer to the next argument in the argument list is CPU-specific following the EFIAPI ABI.

Parameters
Marker | The VA_LIST used to traverse the list of arguments.
Parameter | The name of the parameter that immediately precedes the variable argument list.
Returns
A pointer to the beginning of a variable argument list.

Definition at line 661 of file Base.h.

Typedef Documentation

◆ BASE_LIST

typedef UINTN* BASE_LIST

Pointer to the start of a variable argument list stored in a memory buffer.

Same as UINT8 *.

Definition at line 711 of file Base.h.

◆ VA_LIST

typedef CHAR8* VA_LIST

Variable used to traverse the list of arguments.

This type can vary by implementation and could be an array or structure.

Definition at line 643 of file Base.h.

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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Base.h Source File

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  • Edk2
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Base.h
Go to the documentation of this file.
1 /** @file
2 Root include file for Mde Package Base type modules
3
4 This is the include file for any module of type base. Base modules only use
5 types defined via this include file and can be ported easily to any
6 environment. There are a set of base libraries in the Mde Package that can
7 be used to implement base modules.
8
9 Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
10 Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
11 SPDX-License-Identifier: BSD-2-Clause-Patent
12
13 **/
14
15 #ifndef __BASE_H__
16 #define __BASE_H__
17
18 //
19 // Include processor specific binding
20 //
21 #include <ProcessorBind.h>
22
23 #if defined (_MSC_EXTENSIONS)
24 //
25 // Disable warning when last field of data structure is a zero sized array.
26 //
27 #pragma warning ( disable : 4200 )
28 #endif
29
30 //
31 // The Microsoft* C compiler can removed references to unreferenced data items
32 // if the /OPT:REF linker option is used. We defined a macro as this is a
33 // a non standard extension
34 //
35 #if defined (_MSC_VER) && _MSC_VER < 1800 && !defined (MDE_CPU_EBC)
36 ///
37 /// Remove global variable from the linked image if there are no references to
38 /// it after all compiler and linker optimizations have been performed.
39 ///
40 ///
41 #define GLOBAL_REMOVE_IF_UNREFERENCED __declspec(selectany)
42 #else
43 ///
44 /// Remove the global variable from the linked image if there are no references
45 /// to it after all compiler and linker optimizations have been performed.
46 ///
47 ///
48 #define GLOBAL_REMOVE_IF_UNREFERENCED
49 #endif
50
51 //
52 // Should be used in combination with NORETURN to avoid 'noreturn' returns
53 // warnings.
54 //
55 #ifndef UNREACHABLE
56 #ifdef __GNUC__
57 ///
58 /// Signal compilers and analyzers that this call is not reachable. It is
59 /// up to the compiler to remove any code past that point.
60 ///
61 #define UNREACHABLE() __builtin_unreachable ()
62 #elif defined (__has_feature)
63 #if __has_builtin (__builtin_unreachable)
64 ///
65 /// Signal compilers and analyzers that this call is not reachable. It is
66 /// up to the compiler to remove any code past that point.
67 ///
68 #define UNREACHABLE() __builtin_unreachable ()
69 #endif
70 #endif
71
72 #ifndef UNREACHABLE
73 ///
74 /// Signal compilers and analyzers that this call is not reachable. It is
75 /// up to the compiler to remove any code past that point.
76 ///
77 #define UNREACHABLE()
78 #endif
79 #endif
80
81 //
82 // Signaling compilers and analyzers that a certain function cannot return may
83 // remove all following code and thus lead to better optimization and less
84 // false positives.
85 //
86 #ifndef NORETURN
87 #if defined (__GNUC__) || defined (__clang__)
88 ///
89 /// Signal compilers and analyzers that the function cannot return.
90 /// It is up to the compiler to remove any code past a call to functions
91 /// flagged with this attribute.
92 ///
93 #define NORETURN __attribute__((noreturn))
94 #elif defined (_MSC_EXTENSIONS) && !defined (MDE_CPU_EBC)
95 ///
96 /// Signal compilers and analyzers that the function cannot return.
97 /// It is up to the compiler to remove any code past a call to functions
98 /// flagged with this attribute.
99 ///
100 #define NORETURN __declspec(noreturn)
101 #else
102 ///
103 /// Signal compilers and analyzers that the function cannot return.
104 /// It is up to the compiler to remove any code past a call to functions
105 /// flagged with this attribute.
106 ///
107 #define NORETURN
108 #endif
109 #endif
110
111 //
112 // Should be used in combination with ANALYZER_NORETURN to avoid 'noreturn'
113 // returns warnings.
114 //
115 #ifndef ANALYZER_UNREACHABLE
116 #ifdef __clang_analyzer__
117 #if __has_builtin (__builtin_unreachable)
118 ///
119 /// Signal the analyzer that this call is not reachable.
120 /// This excludes compilers.
121 ///
122 #define ANALYZER_UNREACHABLE() __builtin_unreachable ()
123 #endif
124 #endif
125
126 #ifndef ANALYZER_UNREACHABLE
127 ///
128 /// Signal the analyzer that this call is not reachable.
129 /// This excludes compilers.
130 ///
131 #define ANALYZER_UNREACHABLE()
132 #endif
133 #endif
134
135 //
136 // Static Analyzers may issue errors about potential NULL-dereferences when
137 // dereferencing a pointer, that has been checked before, outside of a
138 // NULL-check. This may lead to false positives, such as when using ASSERT()
139 // for verification.
140 //
141 #ifndef ANALYZER_NORETURN
142 #ifdef __has_feature
143 #if __has_feature (attribute_analyzer_noreturn)
144 ///
145 /// Signal analyzers that the function cannot return.
146 /// This excludes compilers.
147 ///
148 #define ANALYZER_NORETURN __attribute__((analyzer_noreturn))
149 #endif
150 #endif
151
152 #ifndef ANALYZER_NORETURN
153 ///
154 /// Signal the analyzer that the function cannot return.
155 /// This excludes compilers.
156 ///
157 #define ANALYZER_NORETURN
158 #endif
159 #endif
160
161 ///
162 /// Tell the code optimizer that the function will return twice.
163 /// This prevents wrong optimizations which can cause bugs.
164 ///
165 #ifndef RETURNS_TWICE
166 #if defined (__GNUC__) || defined (__clang__)
167 ///
168 /// Tell the code optimizer that the function will return twice.
169 /// This prevents wrong optimizations which can cause bugs.
170 ///
171 #define RETURNS_TWICE __attribute__((returns_twice))
172 #else
173 ///
174 /// Tell the code optimizer that the function will return twice.
175 /// This prevents wrong optimizations which can cause bugs.
176 ///
177 #define RETURNS_TWICE
178 #endif
179 #endif
180
181 //
182 // For symbol name in assembly code, an extra "_" is sometimes necessary
183 //
184
185 ///
186 /// Private worker functions for ASM_PFX()
187 ///
188 #define _CONCATENATE(a, b) __CONCATENATE(a, b)
189 #define __CONCATENATE(a, b) a ## b
190
191 ///
192 /// The __USER_LABEL_PREFIX__ macro predefined by GNUC represents the prefix
193 /// on symbols in assembly language.
194 ///
195 #define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name)
196
197 #ifdef __APPLE__
198 //
199 // Apple extension that is used by the linker to optimize code size
200 // with assembly functions. Put at the end of your .S files
201 //
202 #define ASM_FUNCTION_REMOVE_IF_UNREFERENCED .subsections_via_symbols
203 #else
204 #define ASM_FUNCTION_REMOVE_IF_UNREFERENCED
205 #endif
206
207 #define PACKED
208
209 ///
210 /// 128 bit buffer containing a unique identifier value.
211 /// Unless otherwise specified, aligned on a 64 bit boundary.
212 ///
213 typedef struct {
214 UINT32 Data1;
215 UINT16 Data2;
216 UINT16 Data3;
217 UINT8 Data4[8];
218 } GUID;
219
220 ///
221 /// 4-byte buffer. An IPv4 internet protocol address.
222 ///
223 typedef struct {
224 UINT8 Addr[4];
225 } IPv4_ADDRESS;
226
227 ///
228 /// 16-byte buffer. An IPv6 internet protocol address.
229 ///
230 typedef struct {
231 UINT8 Addr[16];
232 } IPv6_ADDRESS;
233
234 //
235 // 8-bytes unsigned value that represents a physical system address.
236 //
237 typedef UINT64 PHYSICAL_ADDRESS;
238
239 ///
240 /// LIST_ENTRY structure definition.
241 ///
242 typedef struct _LIST_ENTRY LIST_ENTRY;
243
244 ///
245 /// _LIST_ENTRY structure definition.
246 ///
247 struct _LIST_ENTRY {
248 LIST_ENTRY *ForwardLink;
249 LIST_ENTRY *BackLink;
250 };
251
252 //
253 // Modifiers to abstract standard types to aid in debug of problems
254 //
255
256 ///
257 /// Datum is read-only.
258 ///
259 #define CONST const
260
261 ///
262 /// Datum is scoped to the current file or function.
263 ///
264 #define STATIC static
265
266 ///
267 /// Undeclared type.
268 ///
269 #define VOID void
270
271 //
272 // Modifiers for Data Types used to self document code.
273 // This concept is borrowed for UEFI specification.
274 //
275
276 ///
277 /// Datum is passed to the function.
278 ///
279 #define IN
280
281 ///
282 /// Datum is returned from the function.
283 ///
284 #define OUT
285
286 ///
287 /// Passing the datum to the function is optional, and a NULL
288 /// is passed if the value is not supplied.
289 ///
290 #define OPTIONAL
291
292 //
293 // UEFI specification claims 1 and 0. We are concerned about the
294 // compiler portability so we did it this way.
295 //
296
297 ///
298 /// Boolean true value. UEFI Specification defines this value to be 1,
299 /// but this form is more portable.
300 ///
301 #define TRUE ((BOOLEAN)(1==1))
302
303 ///
304 /// Boolean false value. UEFI Specification defines this value to be 0,
305 /// but this form is more portable.
306 ///
307 #define FALSE ((BOOLEAN)(0==1))
308
309 ///
310 /// NULL pointer (VOID *)
311 ///
312 #if defined (__cplusplus)
313 #if defined (_MSC_EXTENSIONS)
314 #define NULL nullptr
315 #else
316 #define NULL __null
317 #endif
318 #else
319 #define NULL ((VOID *) 0)
320 #endif
321
322 //
323 // Null character
324 //
325 #define CHAR_NULL 0x0000
326
327 ///
328 /// Maximum values for common UEFI Data Types
329 ///
330 #define MAX_INT8 ((INT8)0x7F)
331 #define MAX_UINT8 ((UINT8)0xFF)
332 #define MAX_INT16 ((INT16)0x7FFF)
333 #define MAX_UINT16 ((UINT16)0xFFFF)
334 #define MAX_INT32 ((INT32)0x7FFFFFFF)
335 #define MAX_UINT32 ((UINT32)0xFFFFFFFF)
336 #define MAX_INT64 ((INT64)0x7FFFFFFFFFFFFFFFULL)
337 #define MAX_UINT64 ((UINT64)0xFFFFFFFFFFFFFFFFULL)
338
339 ///
340 /// Minimum values for the signed UEFI Data Types
341 ///
342 #define MIN_INT8 (((INT8) -127) - 1)
343 #define MIN_INT16 (((INT16) -32767) - 1)
344 #define MIN_INT32 (((INT32) -2147483647) - 1)
345 #define MIN_INT64 (((INT64) -9223372036854775807LL) - 1)
346
347 #define BIT0 0x00000001
348 #define BIT1 0x00000002
349 #define BIT2 0x00000004
350 #define BIT3 0x00000008
351 #define BIT4 0x00000010
352 #define BIT5 0x00000020
353 #define BIT6 0x00000040
354 #define BIT7 0x00000080
355 #define BIT8 0x00000100
356 #define BIT9 0x00000200
357 #define BIT10 0x00000400
358 #define BIT11 0x00000800
359 #define BIT12 0x00001000
360 #define BIT13 0x00002000
361 #define BIT14 0x00004000
362 #define BIT15 0x00008000
363 #define BIT16 0x00010000
364 #define BIT17 0x00020000
365 #define BIT18 0x00040000
366 #define BIT19 0x00080000
367 #define BIT20 0x00100000
368 #define BIT21 0x00200000
369 #define BIT22 0x00400000
370 #define BIT23 0x00800000
371 #define BIT24 0x01000000
372 #define BIT25 0x02000000
373 #define BIT26 0x04000000
374 #define BIT27 0x08000000
375 #define BIT28 0x10000000
376 #define BIT29 0x20000000
377 #define BIT30 0x40000000
378 #define BIT31 0x80000000
379 #define BIT32 0x0000000100000000ULL
380 #define BIT33 0x0000000200000000ULL
381 #define BIT34 0x0000000400000000ULL
382 #define BIT35 0x0000000800000000ULL
383 #define BIT36 0x0000001000000000ULL
384 #define BIT37 0x0000002000000000ULL
385 #define BIT38 0x0000004000000000ULL
386 #define BIT39 0x0000008000000000ULL
387 #define BIT40 0x0000010000000000ULL
388 #define BIT41 0x0000020000000000ULL
389 #define BIT42 0x0000040000000000ULL
390 #define BIT43 0x0000080000000000ULL
391 #define BIT44 0x0000100000000000ULL
392 #define BIT45 0x0000200000000000ULL
393 #define BIT46 0x0000400000000000ULL
394 #define BIT47 0x0000800000000000ULL
395 #define BIT48 0x0001000000000000ULL
396 #define BIT49 0x0002000000000000ULL
397 #define BIT50 0x0004000000000000ULL
398 #define BIT51 0x0008000000000000ULL
399 #define BIT52 0x0010000000000000ULL
400 #define BIT53 0x0020000000000000ULL
401 #define BIT54 0x0040000000000000ULL
402 #define BIT55 0x0080000000000000ULL
403 #define BIT56 0x0100000000000000ULL
404 #define BIT57 0x0200000000000000ULL
405 #define BIT58 0x0400000000000000ULL
406 #define BIT59 0x0800000000000000ULL
407 #define BIT60 0x1000000000000000ULL
408 #define BIT61 0x2000000000000000ULL
409 #define BIT62 0x4000000000000000ULL
410 #define BIT63 0x8000000000000000ULL
411
412 #define SIZE_1KB 0x00000400
413 #define SIZE_2KB 0x00000800
414 #define SIZE_4KB 0x00001000
415 #define SIZE_8KB 0x00002000
416 #define SIZE_16KB 0x00004000
417 #define SIZE_32KB 0x00008000
418 #define SIZE_64KB 0x00010000
419 #define SIZE_128KB 0x00020000
420 #define SIZE_256KB 0x00040000
421 #define SIZE_512KB 0x00080000
422 #define SIZE_1MB 0x00100000
423 #define SIZE_2MB 0x00200000
424 #define SIZE_4MB 0x00400000
425 #define SIZE_8MB 0x00800000
426 #define SIZE_16MB 0x01000000
427 #define SIZE_32MB 0x02000000
428 #define SIZE_64MB 0x04000000
429 #define SIZE_128MB 0x08000000
430 #define SIZE_256MB 0x10000000
431 #define SIZE_512MB 0x20000000
432 #define SIZE_1GB 0x40000000
433 #define SIZE_2GB 0x80000000
434 #define SIZE_4GB 0x0000000100000000ULL
435 #define SIZE_8GB 0x0000000200000000ULL
436 #define SIZE_16GB 0x0000000400000000ULL
437 #define SIZE_32GB 0x0000000800000000ULL
438 #define SIZE_64GB 0x0000001000000000ULL
439 #define SIZE_128GB 0x0000002000000000ULL
440 #define SIZE_256GB 0x0000004000000000ULL
441 #define SIZE_512GB 0x0000008000000000ULL
442 #define SIZE_1TB 0x0000010000000000ULL
443 #define SIZE_2TB 0x0000020000000000ULL
444 #define SIZE_4TB 0x0000040000000000ULL
445 #define SIZE_8TB 0x0000080000000000ULL
446 #define SIZE_16TB 0x0000100000000000ULL
447 #define SIZE_32TB 0x0000200000000000ULL
448 #define SIZE_64TB 0x0000400000000000ULL
449 #define SIZE_128TB 0x0000800000000000ULL
450 #define SIZE_256TB 0x0001000000000000ULL
451 #define SIZE_512TB 0x0002000000000000ULL
452 #define SIZE_1PB 0x0004000000000000ULL
453 #define SIZE_2PB 0x0008000000000000ULL
454 #define SIZE_4PB 0x0010000000000000ULL
455 #define SIZE_8PB 0x0020000000000000ULL
456 #define SIZE_16PB 0x0040000000000000ULL
457 #define SIZE_32PB 0x0080000000000000ULL
458 #define SIZE_64PB 0x0100000000000000ULL
459 #define SIZE_128PB 0x0200000000000000ULL
460 #define SIZE_256PB 0x0400000000000000ULL
461 #define SIZE_512PB 0x0800000000000000ULL
462 #define SIZE_1EB 0x1000000000000000ULL
463 #define SIZE_2EB 0x2000000000000000ULL
464 #define SIZE_4EB 0x4000000000000000ULL
465 #define SIZE_8EB 0x8000000000000000ULL
466
467 #define BASE_1KB 0x00000400
468 #define BASE_2KB 0x00000800
469 #define BASE_4KB 0x00001000
470 #define BASE_8KB 0x00002000
471 #define BASE_16KB 0x00004000
472 #define BASE_32KB 0x00008000
473 #define BASE_64KB 0x00010000
474 #define BASE_128KB 0x00020000
475 #define BASE_256KB 0x00040000
476 #define BASE_512KB 0x00080000
477 #define BASE_1MB 0x00100000
478 #define BASE_2MB 0x00200000
479 #define BASE_4MB 0x00400000
480 #define BASE_8MB 0x00800000
481 #define BASE_16MB 0x01000000
482 #define BASE_32MB 0x02000000
483 #define BASE_64MB 0x04000000
484 #define BASE_128MB 0x08000000
485 #define BASE_256MB 0x10000000
486 #define BASE_512MB 0x20000000
487 #define BASE_1GB 0x40000000
488 #define BASE_2GB 0x80000000
489 #define BASE_4GB 0x0000000100000000ULL
490 #define BASE_8GB 0x0000000200000000ULL
491 #define BASE_16GB 0x0000000400000000ULL
492 #define BASE_32GB 0x0000000800000000ULL
493 #define BASE_64GB 0x0000001000000000ULL
494 #define BASE_128GB 0x0000002000000000ULL
495 #define BASE_256GB 0x0000004000000000ULL
496 #define BASE_512GB 0x0000008000000000ULL
497 #define BASE_1TB 0x0000010000000000ULL
498 #define BASE_2TB 0x0000020000000000ULL
499 #define BASE_4TB 0x0000040000000000ULL
500 #define BASE_8TB 0x0000080000000000ULL
501 #define BASE_16TB 0x0000100000000000ULL
502 #define BASE_32TB 0x0000200000000000ULL
503 #define BASE_64TB 0x0000400000000000ULL
504 #define BASE_128TB 0x0000800000000000ULL
505 #define BASE_256TB 0x0001000000000000ULL
506 #define BASE_512TB 0x0002000000000000ULL
507 #define BASE_1PB 0x0004000000000000ULL
508 #define BASE_2PB 0x0008000000000000ULL
509 #define BASE_4PB 0x0010000000000000ULL
510 #define BASE_8PB 0x0020000000000000ULL
511 #define BASE_16PB 0x0040000000000000ULL
512 #define BASE_32PB 0x0080000000000000ULL
513 #define BASE_64PB 0x0100000000000000ULL
514 #define BASE_128PB 0x0200000000000000ULL
515 #define BASE_256PB 0x0400000000000000ULL
516 #define BASE_512PB 0x0800000000000000ULL
517 #define BASE_1EB 0x1000000000000000ULL
518 #define BASE_2EB 0x2000000000000000ULL
519 #define BASE_4EB 0x4000000000000000ULL
520 #define BASE_8EB 0x8000000000000000ULL
521
522 //
523 // Support for variable argument lists in freestanding edk2 modules.
524 //
525 // For modules that use the ISO C library interfaces for variable
526 // argument lists, refer to "StdLib/Include/stdarg.h".
527 //
528 // VA_LIST - typedef for argument list.
529 // VA_START (VA_LIST Marker, argument before the ...) - Init Marker for use.
530 // VA_END (VA_LIST Marker) - Clear Marker
531 // VA_ARG (VA_LIST Marker, var arg type) - Use Marker to get an argument from
532 // the ... list. You must know the type and pass it in this macro. Type
533 // must be compatible with the type of the actual next argument (as promoted
534 // according to the default argument promotions.)
535 // VA_COPY (VA_LIST Dest, VA_LIST Start) - Initialize Dest as a copy of Start.
536 //
537 // Example:
538 //
539 // UINTN
540 // EFIAPI
541 // ExampleVarArg (
542 // IN UINTN NumberOfArgs,
543 // ...
544 // )
545 // {
546 // VA_LIST Marker;
547 // UINTN Index;
548 // UINTN Result;
549 //
550 // //
551 // // Initialize the Marker
552 // //
553 // VA_START (Marker, NumberOfArgs);
554 // for (Index = 0, Result = 0; Index < NumberOfArgs; Index++) {
555 // //
556 // // The ... list is a series of UINTN values, so sum them up.
557 // //
558 // Result += VA_ARG (Marker, UINTN);
559 // }
560 //
561 // VA_END (Marker);
562 // return Result;
563 // }
564 //
565 // Notes:
566 // - Functions that call VA_START() / VA_END() must have a variable
567 // argument list and must be declared EFIAPI.
568 // - Functions that call VA_COPY() / VA_END() must be declared EFIAPI.
569 // - Functions that only use VA_LIST and VA_ARG() need not be EFIAPI.
570 //
571
572 /**
573 Return the size of argument that has been aligned to sizeof (UINTN).
574
575 @param n The parameter size to be aligned.
576
577 @return The aligned size.
578 **/
579 #define _INT_SIZE_OF(n) ((sizeof (n) + sizeof (UINTN) - 1) &~(sizeof (UINTN) - 1))
580
581 #if defined (_M_ARM) || defined (_M_ARM64)
582 //
583 // MSFT ARM variable argument list support.
584 //
585
586 typedef char *VA_LIST;
587
588 #define VA_START(Marker, Parameter) __va_start (&Marker, &Parameter, _INT_SIZE_OF (Parameter), __alignof(Parameter), &Parameter)
589 #define VA_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _INT_SIZE_OF (TYPE) + ((-(INTN)Marker) & (sizeof(TYPE) - 1))) - _INT_SIZE_OF (TYPE)))
590 #define VA_END(Marker) (Marker = (VA_LIST) 0)
591 #define VA_COPY(Dest, Start) ((void)((Dest) = (Start)))
592
593 #elif defined (__GNUC__) || defined (__clang__)
594
595 #if defined (MDE_CPU_X64) && !defined (NO_MSABI_VA_FUNCS)
596 //
597 // X64 only. Use MS ABI version of GCC built-in macros for variable argument lists.
598 //
599 ///
600 /// Both GCC and LLVM 3.8 for X64 support new variable argument intrinsics for Microsoft ABI
601 ///
602
603 ///
604 /// Variable used to traverse the list of arguments. This type can vary by
605 /// implementation and could be an array or structure.
606 ///
607 typedef __builtin_ms_va_list VA_LIST;
608
609 #define VA_START(Marker, Parameter) __builtin_ms_va_start (Marker, Parameter)
610
611 #define VA_ARG(Marker, TYPE) ((sizeof (TYPE) < sizeof (UINTN)) ? (TYPE)(__builtin_va_arg (Marker, UINTN)) : (TYPE)(__builtin_va_arg (Marker, TYPE)))
612
613 #define VA_END(Marker) __builtin_ms_va_end (Marker)
614
615 #define VA_COPY(Dest, Start) __builtin_ms_va_copy (Dest, Start)
616
617 #else
618 //
619 // Use GCC built-in macros for variable argument lists.
620 //
621
622 ///
623 /// Variable used to traverse the list of arguments. This type can vary by
624 /// implementation and could be an array or structure.
625 ///
626 typedef __builtin_va_list VA_LIST;
627
628 #define VA_START(Marker, Parameter) __builtin_va_start (Marker, Parameter)
629
630 #define VA_ARG(Marker, TYPE) ((sizeof (TYPE) < sizeof (UINTN)) ? (TYPE)(__builtin_va_arg (Marker, UINTN)) : (TYPE)(__builtin_va_arg (Marker, TYPE)))
631
632 #define VA_END(Marker) __builtin_va_end (Marker)
633
634 #define VA_COPY(Dest, Start) __builtin_va_copy (Dest, Start)
635
636 #endif
637
638 #else
639 ///
640 /// Variable used to traverse the list of arguments. This type can vary by
641 /// implementation and could be an array or structure.
642 ///
643 typedef CHAR8 *VA_LIST;
644
645 /**
646 Retrieves a pointer to the beginning of a variable argument list, based on
647 the name of the parameter that immediately precedes the variable argument list.
648
649 This function initializes Marker to point to the beginning of the variable
650 argument list that immediately follows Parameter. The method for computing the
651 pointer to the next argument in the argument list is CPU-specific following the
652 EFIAPI ABI.
653
654 @param Marker The VA_LIST used to traverse the list of arguments.
655 @param Parameter The name of the parameter that immediately precedes
656 the variable argument list.
657
658 @return A pointer to the beginning of a variable argument list.
659
660 **/
661 #define VA_START(Marker, Parameter) (Marker = (VA_LIST) ((UINTN) & (Parameter) + _INT_SIZE_OF (Parameter)))
662
663 /**
664 Returns an argument of a specified type from a variable argument list and updates
665 the pointer to the variable argument list to point to the next argument.
666
667 This function returns an argument of the type specified by TYPE from the beginning
668 of the variable argument list specified by Marker. Marker is then updated to point
669 to the next argument in the variable argument list. The method for computing the
670 pointer to the next argument in the argument list is CPU-specific following the EFIAPI ABI.
671
672 @param Marker VA_LIST used to traverse the list of arguments.
673 @param TYPE The type of argument to retrieve from the beginning
674 of the variable argument list.
675
676 @return An argument of the type specified by TYPE.
677
678 **/
679 #define VA_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _INT_SIZE_OF (TYPE)) - _INT_SIZE_OF (TYPE)))
680
681 /**
682 Terminates the use of a variable argument list.
683
684 This function initializes Marker so it can no longer be used with VA_ARG().
685 After this macro is used, the only way to access the variable argument list is
686 by using VA_START() again.
687
688 @param Marker VA_LIST used to traverse the list of arguments.
689
690 **/
691 #define VA_END(Marker) (Marker = (VA_LIST) 0)
692
693 /**
694 Initializes a VA_LIST as a copy of an existing VA_LIST.
695
696 This macro initializes Dest as a copy of Start, as if the VA_START macro had been applied to Dest
697 followed by the same sequence of uses of the VA_ARG macro as had previously been used to reach
698 the present state of Start.
699
700 @param Dest VA_LIST used to traverse the list of arguments.
701 @param Start VA_LIST used to traverse the list of arguments.
702
703 **/
704 #define VA_COPY(Dest, Start) ((void)((Dest) = (Start)))
705
706 #endif
707
708 ///
709 /// Pointer to the start of a variable argument list stored in a memory buffer. Same as UINT8 *.
710 ///
711 typedef UINTN *BASE_LIST;
712
713 /**
714 Returns the size of a data type in sizeof(UINTN) units rounded up to the nearest UINTN boundary.
715
716 @param TYPE The date type to determine the size of.
717
718 @return The size of TYPE in sizeof (UINTN) units rounded up to the nearest UINTN boundary.
719 **/
720 #define _BASE_INT_SIZE_OF(TYPE) ((sizeof (TYPE) + sizeof (UINTN) - 1) / sizeof (UINTN))
721
722 /**
723 Returns an argument of a specified type from a variable argument list and updates
724 the pointer to the variable argument list to point to the next argument.
725
726 This function returns an argument of the type specified by TYPE from the beginning
727 of the variable argument list specified by Marker. Marker is then updated to point
728 to the next argument in the variable argument list. The method for computing the
729 pointer to the next argument in the argument list is CPU specific following the EFIAPI ABI.
730
731 @param Marker The pointer to the beginning of a variable argument list.
732 @param TYPE The type of argument to retrieve from the beginning
733 of the variable argument list.
734
735 @return An argument of the type specified by TYPE.
736
737 **/
738 #define BASE_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _BASE_INT_SIZE_OF (TYPE)) - _BASE_INT_SIZE_OF (TYPE)))
739
740 /**
741 The macro that returns the byte offset of a field in a data structure.
742
743 This function returns the offset, in bytes, of field specified by Field from the
744 beginning of the data structure specified by TYPE. If TYPE does not contain Field,
745 the module will not compile.
746
747 @param TYPE The name of the data structure that contains the field specified by Field.
748 @param Field The name of the field in the data structure.
749
750 @return Offset, in bytes, of field.
751
752 **/
753 #if (defined (__GNUC__) && __GNUC__ >= 4) || defined (__clang__)
754 #define OFFSET_OF(TYPE, Field) ((UINTN) __builtin_offsetof(TYPE, Field))
755 #endif
756
757 #ifndef OFFSET_OF
758 #define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field))
759 #endif
760
761 /**
762 Returns the alignment requirement of a type.
763
764 @param TYPE The name of the type to retrieve the alignment requirement of.
765
766 @return Alignment requirement, in Bytes, of TYPE.
767 **/
768 #if defined (__cplusplus)
769 //
770 // Standard C++ operator.
771 //
772 #define ALIGNOF(TYPE) alignof (TYPE)
773 #elif defined (__GNUC__) || defined (__clang__) || (defined (_MSC_VER) && _MSC_VER >= 1900)
774 //
775 // All supported versions of GCC and Clang, as well as MSVC 2015 and later,
776 // support the standard operator _Alignof.
777 //
778 #define ALIGNOF(TYPE) _Alignof (TYPE)
779 #elif defined (_MSC_EXTENSIONS)
780 //
781 // Earlier versions of MSVC, at least MSVC 2008 and later, support the vendor
782 // extension __alignof.
783 //
784 #define ALIGNOF(TYPE) __alignof (TYPE)
785 #else
786 //
787 // For compilers that do not support inbuilt alignof operators, use OFFSET_OF.
788 // CHAR8 is known to have both a size and an alignment requirement of 1 Byte.
789 // As such, A must be located exactly at the offset equal to its alignment
790 // requirement.
791 //
792 #define ALIGNOF(TYPE) OFFSET_OF (struct { CHAR8 C; TYPE A; }, A)
793 #endif
794
795 /**
796 Portable definition for compile time assertions.
797 Equivalent to C11 static_assert macro from assert.h.
798
799 @param Expression Boolean expression.
800 @param Message Raised compiler diagnostic message when expression is false.
801
802 **/
803 #ifdef MDE_CPU_EBC
804 #define STATIC_ASSERT(Expression, Message)
805 #elif defined (_MSC_EXTENSIONS) || defined (__cplusplus)
806 #define STATIC_ASSERT static_assert
807 #else
808 #define STATIC_ASSERT _Static_assert
809 #endif
810
811 //
812 // Verify that ProcessorBind.h produced UEFI Data Types that are compliant with
813 // Section 2.3.1 of the UEFI 2.3 Specification.
814 //
815
816 STATIC_ASSERT (sizeof (BOOLEAN) == 1, "sizeof (BOOLEAN) does not meet UEFI Specification Data Type requirements");
817 STATIC_ASSERT (sizeof (INT8) == 1, "sizeof (INT8) does not meet UEFI Specification Data Type requirements");
818 STATIC_ASSERT (sizeof (UINT8) == 1, "sizeof (UINT8) does not meet UEFI Specification Data Type requirements");
819 STATIC_ASSERT (sizeof (INT16) == 2, "sizeof (INT16) does not meet UEFI Specification Data Type requirements");
820 STATIC_ASSERT (sizeof (UINT16) == 2, "sizeof (UINT16) does not meet UEFI Specification Data Type requirements");
821 STATIC_ASSERT (sizeof (INT32) == 4, "sizeof (INT32) does not meet UEFI Specification Data Type requirements");
822 STATIC_ASSERT (sizeof (UINT32) == 4, "sizeof (UINT32) does not meet UEFI Specification Data Type requirements");
823 STATIC_ASSERT (sizeof (INT64) == 8, "sizeof (INT64) does not meet UEFI Specification Data Type requirements");
824 STATIC_ASSERT (sizeof (UINT64) == 8, "sizeof (UINT64) does not meet UEFI Specification Data Type requirements");
825 STATIC_ASSERT (sizeof (CHAR8) == 1, "sizeof (CHAR8) does not meet UEFI Specification Data Type requirements");
826 STATIC_ASSERT (sizeof (CHAR16) == 2, "sizeof (CHAR16) does not meet UEFI Specification Data Type requirements");
827 STATIC_ASSERT (sizeof (L'A') == 2, "sizeof (L'A') does not meet UEFI Specification Data Type requirements");
828 STATIC_ASSERT (sizeof (L"A") == 4, "sizeof (L\"A\") does not meet UEFI Specification Data Type requirements");
829
830 STATIC_ASSERT (ALIGNOF (BOOLEAN) == sizeof (BOOLEAN), "Alignment of BOOLEAN does not meet UEFI Specification Data Type requirements");
831 STATIC_ASSERT (ALIGNOF (INT8) == sizeof (INT8), "Alignment of INT8 does not meet UEFI Specification Data Type requirements");
832 STATIC_ASSERT (ALIGNOF (UINT8) == sizeof (UINT8), "Alignment of INT16 does not meet UEFI Specification Data Type requirements");
833 STATIC_ASSERT (ALIGNOF (INT16) == sizeof (INT16), "Alignment of INT16 does not meet UEFI Specification Data Type requirements");
834 STATIC_ASSERT (ALIGNOF (UINT16) == sizeof (UINT16), "Alignment of UINT16 does not meet UEFI Specification Data Type requirements");
835 STATIC_ASSERT (ALIGNOF (INT32) == sizeof (INT32), "Alignment of INT32 does not meet UEFI Specification Data Type requirements");
836 STATIC_ASSERT (ALIGNOF (UINT32) == sizeof (UINT32), "Alignment of UINT32 does not meet UEFI Specification Data Type requirements");
837 STATIC_ASSERT (ALIGNOF (INT64) == sizeof (INT64), "Alignment of INT64 does not meet UEFI Specification Data Type requirements");
838 STATIC_ASSERT (ALIGNOF (UINT64) == sizeof (UINT64), "Alignment of UINT64 does not meet UEFI Specification Data Type requirements");
839 STATIC_ASSERT (ALIGNOF (CHAR8) == sizeof (CHAR8), "Alignment of CHAR8 does not meet UEFI Specification Data Type requirements");
840 STATIC_ASSERT (ALIGNOF (CHAR16) == sizeof (CHAR16), "Alignment of CHAR16 does not meet UEFI Specification Data Type requirements");
841 STATIC_ASSERT (ALIGNOF (INTN) == sizeof (INTN), "Alignment of INTN does not meet UEFI Specification Data Type requirements");
842 STATIC_ASSERT (ALIGNOF (UINTN) == sizeof (UINTN), "Alignment of UINTN does not meet UEFI Specification Data Type requirements");
843 STATIC_ASSERT (ALIGNOF (VOID *) == sizeof (VOID *), "Alignment of VOID * does not meet UEFI Specification Data Type requirements");
844
845 //
846 // The following three enum types are used to verify that the compiler
847 // configuration for enum types is compliant with Section 2.3.1 of the
848 // UEFI 2.3.1 Errata C Specification. These enum types and enum values
849 // are not intended to be used. A prefix of '__' is used avoid
850 // conflicts with other types.
851 //
852 typedef enum {
853 __VerifyUint8EnumValue = 0xff
854 } __VERIFY_UINT8_ENUM_SIZE;
855
856 typedef enum {
857 __VerifyUint16EnumValue = 0xffff
858 } __VERIFY_UINT16_ENUM_SIZE;
859
860 typedef enum {
861 __VerifyInt32EnumValue = 0x7fffffff
862 } __VERIFY_INT32_ENUM_SIZE;
863
864 STATIC_ASSERT (sizeof (__VERIFY_UINT8_ENUM_SIZE) == 4, "Size of enum does not meet UEFI Specification Data Type requirements");
865 STATIC_ASSERT (sizeof (__VERIFY_UINT16_ENUM_SIZE) == 4, "Size of enum does not meet UEFI Specification Data Type requirements");
866 STATIC_ASSERT (sizeof (__VERIFY_INT32_ENUM_SIZE) == 4, "Size of enum does not meet UEFI Specification Data Type requirements");
867
868 STATIC_ASSERT (ALIGNOF (__VERIFY_UINT8_ENUM_SIZE) == sizeof (__VERIFY_UINT8_ENUM_SIZE), "Alignment of enum does not meet UEFI Specification Data Type requirements");
869 STATIC_ASSERT (ALIGNOF (__VERIFY_UINT16_ENUM_SIZE) == sizeof (__VERIFY_UINT16_ENUM_SIZE), "Alignment of enum does not meet UEFI Specification Data Type requirements");
870 STATIC_ASSERT (ALIGNOF (__VERIFY_INT32_ENUM_SIZE) == sizeof (__VERIFY_INT32_ENUM_SIZE), "Alignment of enum does not meet UEFI Specification Data Type requirements");
871
872 /**
873 Macro that returns a pointer to the data structure that contains a specified field of
874 that data structure. This is a lightweight method to hide information by placing a
875 public data structure inside a larger private data structure and using a pointer to
876 the public data structure to retrieve a pointer to the private data structure.
877
878 This function computes the offset, in bytes, of field specified by Field from the beginning
879 of the data structure specified by TYPE. This offset is subtracted from Record, and is
880 used to return a pointer to a data structure of the type specified by TYPE. If the data type
881 specified by TYPE does not contain the field specified by Field, then the module will not compile.
882
883 @param Record Pointer to the field specified by Field within a data structure of type TYPE.
884 @param TYPE The name of the data structure type to return. This data structure must
885 contain the field specified by Field.
886 @param Field The name of the field in the data structure specified by TYPE to which Record points.
887
888 @return A pointer to the structure from one of it's elements.
889
890 **/
891 #define BASE_CR(Record, TYPE, Field) ((TYPE *) ((CHAR8 *) (Record) - OFFSET_OF (TYPE, Field)))
892
893 /**
894 Checks whether a value is a power of two.
895
896 @param Value The value to check.
897
898 @retval TRUE Value is a power of two.
899 @retval FALSE Value is not a power of two.
900 **/
901 #define IS_POW2(Value) ((Value) != 0U && ((Value) & ((Value) - 1U)) == 0U)
902
903 /**
904 Checks whether a value is aligned by a specified alignment.
905
906 @param Value The value to check.
907 @param Alignment The alignment boundary used to check against.
908
909 @retval TRUE Value is aligned by Alignment.
910 @retval FALSE Value is not aligned by Alignment.
911 **/
912 #define IS_ALIGNED(Value, Alignment) (((Value) & ((Alignment) - 1U)) == 0U)
913
914 /**
915 Checks whether a pointer or address is aligned by a specified alignment.
916
917 @param Address The pointer or address to check.
918 @param Alignment The alignment boundary used to check against.
919
920 @retval TRUE Address is aligned by Alignment.
921 @retval FALSE Address is not aligned by Alignment.
922 **/
923 #define ADDRESS_IS_ALIGNED(Address, Alignment) IS_ALIGNED ((UINTN) (Address), Alignment)
924
925 /**
926 Determines the addend to add to a value to round it up to the next boundary of
927 a specified alignment.
928
929 @param Value The value to round up.
930 @param Alignment The alignment boundary used to return the addend.
931
932 @return Addend to round Value up to alignment boundary Alignment.
933 **/
934 #define ALIGN_VALUE_ADDEND(Value, Alignment) (((Alignment) - (Value)) & ((Alignment) - 1U))
935
936 /**
937 Rounds a value up to the next boundary using a specified alignment.
938
939 This function rounds Value up to the next boundary using the specified Alignment.
940 This aligned value is returned.
941
942 @param Value The value to round up.
943 @param Alignment The alignment boundary used to return the aligned value.
944
945 @return A value up to the next boundary.
946
947 **/
948 #define ALIGN_VALUE(Value, Alignment) ((Value) + ALIGN_VALUE_ADDEND (Value, Alignment))
949
950 /**
951 Adjust a pointer by adding the minimum offset required for it to be aligned on
952 a specified alignment boundary.
953
954 This function rounds the pointer specified by Pointer to the next alignment boundary
955 specified by Alignment. The pointer to the aligned address is returned.
956
957 @param Pointer The pointer to round up.
958 @param Alignment The alignment boundary to use to return an aligned pointer.
959
960 @return Pointer to the aligned address.
961
962 **/
963 #define ALIGN_POINTER(Pointer, Alignment) ((VOID *) (ALIGN_VALUE ((UINTN)(Pointer), (Alignment))))
964
965 /**
966 Rounds a value up to the next natural boundary for the current CPU.
967 This is 4-bytes for 32-bit CPUs and 8-bytes for 64-bit CPUs.
968
969 This function rounds the value specified by Value up to the next natural boundary for the
970 current CPU. This rounded value is returned.
971
972 @param Value The value to round up.
973
974 @return Rounded value specified by Value.
975
976 **/
977 #define ALIGN_VARIABLE(Value) ALIGN_VALUE ((Value), sizeof (UINTN))
978
979 /**
980 Return the maximum of two operands.
981
982 This macro returns the maximum of two operand specified by a and b.
983 Both a and b must be the same numerical types, signed or unsigned.
984
985 @param a The first operand with any numerical type.
986 @param b The second operand. Can be any numerical type as long as is
987 the same type as a.
988
989 @return Maximum of two operands.
990
991 **/
992 #define MAX(a, b) \
993 (((a) > (b)) ? (a) : (b))
994
995 /**
996 Return the minimum of two operands.
997
998 This macro returns the minimal of two operand specified by a and b.
999 Both a and b must be the same numerical types, signed or unsigned.
1000
1001 @param a The first operand with any numerical type.
1002 @param b The second operand. It should be the same any numerical type with a.
1003
1004 @return Minimum of two operands.
1005
1006 **/
1007 #define MIN(a, b) \
1008 (((a) < (b)) ? (a) : (b))
1009
1010 /**
1011 Return the absolute value of a signed operand.
1012
1013 This macro returns the absolute value of the signed operand specified by a.
1014
1015 @param a The signed operand.
1016
1017 @return The absolute value of the signed operand.
1018
1019 **/
1020 #define ABS(a) \
1021 (((a) < 0) ? (-(a)) : (a))
1022
1023 //
1024 // Status codes common to all execution phases
1025 //
1026 typedef UINTN RETURN_STATUS;
1027
1028 /**
1029 Produces a RETURN_STATUS code with the highest bit set.
1030
1031 @param StatusCode The status code value to convert into a warning code.
1032 StatusCode must be in the range 0x00000000..0x7FFFFFFF.
1033
1034 @return The value specified by StatusCode with the highest bit set.
1035
1036 **/
1037 #define ENCODE_ERROR(StatusCode) ((RETURN_STATUS)(MAX_BIT | (StatusCode)))
1038
1039 /**
1040 Produces a RETURN_STATUS code with the highest bit clear.
1041
1042 @param StatusCode The status code value to convert into a warning code.
1043 StatusCode must be in the range 0x00000000..0x7FFFFFFF.
1044
1045 @return The value specified by StatusCode with the highest bit clear.
1046
1047 **/
1048 #define ENCODE_WARNING(StatusCode) ((RETURN_STATUS)(StatusCode))
1049
1050 /**
1051 Returns TRUE if a specified RETURN_STATUS code is an error code.
1052
1053 This function returns TRUE if StatusCode has the high bit set. Otherwise, FALSE is returned.
1054
1055 @param StatusCode The status code value to evaluate.
1056
1057 @retval TRUE The high bit of StatusCode is set.
1058 @retval FALSE The high bit of StatusCode is clear.
1059
1060 **/
1061 #define RETURN_ERROR(StatusCode) (((INTN)(RETURN_STATUS)(StatusCode)) < 0)
1062
1063 ///
1064 /// The operation completed successfully.
1065 ///
1066 #define RETURN_SUCCESS (RETURN_STATUS)(0)
1067
1068 ///
1069 /// The image failed to load.
1070 ///
1071 #define RETURN_LOAD_ERROR ENCODE_ERROR (1)
1072
1073 ///
1074 /// The parameter was incorrect.
1075 ///
1076 #define RETURN_INVALID_PARAMETER ENCODE_ERROR (2)
1077
1078 ///
1079 /// The operation is not supported.
1080 ///
1081 #define RETURN_UNSUPPORTED ENCODE_ERROR (3)
1082
1083 ///
1084 /// The buffer was not the proper size for the request.
1085 ///
1086 #define RETURN_BAD_BUFFER_SIZE ENCODE_ERROR (4)
1087
1088 ///
1089 /// The buffer was not large enough to hold the requested data.
1090 /// The required buffer size is returned in the appropriate
1091 /// parameter when this error occurs.
1092 ///
1093 #define RETURN_BUFFER_TOO_SMALL ENCODE_ERROR (5)
1094
1095 ///
1096 /// There is no data pending upon return.
1097 ///
1098 #define RETURN_NOT_READY ENCODE_ERROR (6)
1099
1100 ///
1101 /// The physical device reported an error while attempting the
1102 /// operation.
1103 ///
1104 #define RETURN_DEVICE_ERROR ENCODE_ERROR (7)
1105
1106 ///
1107 /// The device can not be written to.
1108 ///
1109 #define RETURN_WRITE_PROTECTED ENCODE_ERROR (8)
1110
1111 ///
1112 /// The resource has run out.
1113 ///
1114 #define RETURN_OUT_OF_RESOURCES ENCODE_ERROR (9)
1115
1116 ///
1117 /// An inconsistency was detected on the file system causing the
1118 /// operation to fail.
1119 ///
1120 #define RETURN_VOLUME_CORRUPTED ENCODE_ERROR (10)
1121
1122 ///
1123 /// There is no more space on the file system.
1124 ///
1125 #define RETURN_VOLUME_FULL ENCODE_ERROR (11)
1126
1127 ///
1128 /// The device does not contain any medium to perform the
1129 /// operation.
1130 ///
1131 #define RETURN_NO_MEDIA ENCODE_ERROR (12)
1132
1133 ///
1134 /// The medium in the device has changed since the last
1135 /// access.
1136 ///
1137 #define RETURN_MEDIA_CHANGED ENCODE_ERROR (13)
1138
1139 ///
1140 /// The item was not found.
1141 ///
1142 #define RETURN_NOT_FOUND ENCODE_ERROR (14)
1143
1144 ///
1145 /// Access was denied.
1146 ///
1147 #define RETURN_ACCESS_DENIED ENCODE_ERROR (15)
1148
1149 ///
1150 /// The server was not found or did not respond to the request.
1151 ///
1152 #define RETURN_NO_RESPONSE ENCODE_ERROR (16)
1153
1154 ///
1155 /// A mapping to the device does not exist.
1156 ///
1157 #define RETURN_NO_MAPPING ENCODE_ERROR (17)
1158
1159 ///
1160 /// A timeout time expired.
1161 ///
1162 #define RETURN_TIMEOUT ENCODE_ERROR (18)
1163
1164 ///
1165 /// The protocol has not been started.
1166 ///
1167 #define RETURN_NOT_STARTED ENCODE_ERROR (19)
1168
1169 ///
1170 /// The protocol has already been started.
1171 ///
1172 #define RETURN_ALREADY_STARTED ENCODE_ERROR (20)
1173
1174 ///
1175 /// The operation was aborted.
1176 ///
1177 #define RETURN_ABORTED ENCODE_ERROR (21)
1178
1179 ///
1180 /// An ICMP error occurred during the network operation.
1181 ///
1182 #define RETURN_ICMP_ERROR ENCODE_ERROR (22)
1183
1184 ///
1185 /// A TFTP error occurred during the network operation.
1186 ///
1187 #define RETURN_TFTP_ERROR ENCODE_ERROR (23)
1188
1189 ///
1190 /// A protocol error occurred during the network operation.
1191 ///
1192 #define RETURN_PROTOCOL_ERROR ENCODE_ERROR (24)
1193
1194 ///
1195 /// A function encountered an internal version that was
1196 /// incompatible with a version requested by the caller.
1197 ///
1198 #define RETURN_INCOMPATIBLE_VERSION ENCODE_ERROR (25)
1199
1200 ///
1201 /// The function was not performed due to a security violation.
1202 ///
1203 #define RETURN_SECURITY_VIOLATION ENCODE_ERROR (26)
1204
1205 ///
1206 /// A CRC error was detected.
1207 ///
1208 #define RETURN_CRC_ERROR ENCODE_ERROR (27)
1209
1210 ///
1211 /// The beginning or end of media was reached.
1212 ///
1213 #define RETURN_END_OF_MEDIA ENCODE_ERROR (28)
1214
1215 ///
1216 /// The end of the file was reached.
1217 ///
1218 #define RETURN_END_OF_FILE ENCODE_ERROR (31)
1219
1220 ///
1221 /// The language specified was invalid.
1222 ///
1223 #define RETURN_INVALID_LANGUAGE ENCODE_ERROR (32)
1224
1225 ///
1226 /// The security status of the data is unknown or compromised
1227 /// and the data must be updated or replaced to restore a valid
1228 /// security status.
1229 ///
1230 #define RETURN_COMPROMISED_DATA ENCODE_ERROR (33)
1231
1232 ///
1233 /// A HTTP error occurred during the network operation.
1234 ///
1235 #define RETURN_HTTP_ERROR ENCODE_ERROR (35)
1236
1237 ///
1238 /// The string contained one or more characters that
1239 /// the device could not render and were skipped.
1240 ///
1241 #define RETURN_WARN_UNKNOWN_GLYPH ENCODE_WARNING (1)
1242
1243 ///
1244 /// The handle was closed, but the file was not deleted.
1245 ///
1246 #define RETURN_WARN_DELETE_FAILURE ENCODE_WARNING (2)
1247
1248 ///
1249 /// The handle was closed, but the data to the file was not
1250 /// flushed properly.
1251 ///
1252 #define RETURN_WARN_WRITE_FAILURE ENCODE_WARNING (3)
1253
1254 ///
1255 /// The resulting buffer was too small, and the data was
1256 /// truncated to the buffer size.
1257 ///
1258 #define RETURN_WARN_BUFFER_TOO_SMALL ENCODE_WARNING (4)
1259
1260 ///
1261 /// The data has not been updated within the timeframe set by
1262 /// local policy for this type of data.
1263 ///
1264 #define RETURN_WARN_STALE_DATA ENCODE_WARNING (5)
1265
1266 ///
1267 /// The resulting buffer contains UEFI-compliant file system.
1268 ///
1269 #define RETURN_WARN_FILE_SYSTEM ENCODE_WARNING (6)
1270
1271 /**
1272 Returns a 16-bit signature built from 2 ASCII characters.
1273
1274 This macro returns a 16-bit value built from the two ASCII characters specified
1275 by A and B.
1276
1277 @param A The first ASCII character.
1278 @param B The second ASCII character.
1279
1280 @return A 16-bit value built from the two ASCII characters specified by A and B.
1281
1282 **/
1283 #define SIGNATURE_16(A, B) ((A) | (B << 8))
1284
1285 /**
1286 Returns a 32-bit signature built from 4 ASCII characters.
1287
1288 This macro returns a 32-bit value built from the four ASCII characters specified
1289 by A, B, C, and D.
1290
1291 @param A The first ASCII character.
1292 @param B The second ASCII character.
1293 @param C The third ASCII character.
1294 @param D The fourth ASCII character.
1295
1296 @return A 32-bit value built from the two ASCII characters specified by A, B,
1297 C and D.
1298
1299 **/
1300 #define SIGNATURE_32(A, B, C, D) (SIGNATURE_16 (A, B) | (SIGNATURE_16 (C, D) << 16))
1301
1302 /**
1303 Returns a 64-bit signature built from 8 ASCII characters.
1304
1305 This macro returns a 64-bit value built from the eight ASCII characters specified
1306 by A, B, C, D, E, F, G,and H.
1307
1308 @param A The first ASCII character.
1309 @param B The second ASCII character.
1310 @param C The third ASCII character.
1311 @param D The fourth ASCII character.
1312 @param E The fifth ASCII character.
1313 @param F The sixth ASCII character.
1314 @param G The seventh ASCII character.
1315 @param H The eighth ASCII character.
1316
1317 @return A 64-bit value built from the two ASCII characters specified by A, B,
1318 C, D, E, F, G and H.
1319
1320 **/
1321 #define SIGNATURE_64(A, B, C, D, E, F, G, H) \
1322 (SIGNATURE_32 (A, B, C, D) | ((UINT64) (SIGNATURE_32 (E, F, G, H)) << 32))
1323
1324 #if defined (_MSC_EXTENSIONS) && !defined (__INTEL_COMPILER) && !defined (MDE_CPU_EBC)
1325 void *
1326 _ReturnAddress (
1327 void
1328 );
1329
1330 #pragma intrinsic(_ReturnAddress)
1331
1332 /**
1333 Get the return address of the calling function.
1334
1335 Based on intrinsic function _ReturnAddress that provides the address of
1336 the instruction in the calling function that will be executed after
1337 control returns to the caller.
1338
1339 @param L Return Level.
1340
1341 @return The return address of the calling function or 0 if L != 0.
1342
1343 **/
1344 #define RETURN_ADDRESS(L) ((L == 0) ? _ReturnAddress() : (VOID *) 0)
1345 #elif defined (__GNUC__) || defined (__clang__)
1346
1347 /**
1348 Get the return address of the calling function.
1349
1350 Based on built-in Function __builtin_return_address that returns
1351 the return address of the current function, or of one of its callers.
1352
1353 @param L Return Level.
1354
1355 @return The return address of the calling function.
1356
1357 **/
1358 #define RETURN_ADDRESS(L) __builtin_return_address (L)
1359 #else
1360
1361 /**
1362 Get the return address of the calling function.
1363
1364 @param L Return Level.
1365
1366 @return 0 as compilers don't support this feature.
1367
1368 **/
1369 #define RETURN_ADDRESS(L) ((VOID *) 0)
1370 #endif
1371
1372 /**
1373 Return the number of elements in an array.
1374
1375 @param Array An object of array type. Array is only used as an argument to
1376 the sizeof operator, therefore Array is never evaluated. The
1377 caller is responsible for ensuring that Array's type is not
1378 incomplete; that is, Array must have known constant size.
1379
1380 @return The number of elements in Array. The result has type UINTN.
1381
1382 **/
1383 #define ARRAY_SIZE(Array) (sizeof (Array) / sizeof ((Array)[0]))
1384
1385 #endif
ALIGNOF
#define ALIGNOF(TYPE)
Returns the alignment requirement of a type.
Definition: Base.h:792
IPv4_ADDRESS
4-byte buffer.
Definition: Base.h:223
BASE_LIST
UINTN * BASE_LIST
Pointer to the start of a variable argument list stored in a memory buffer.
Definition: Base.h:711
VOID
#define VOID
Undeclared type.
Definition: Base.h:269
IPv6_ADDRESS
16-byte buffer.
Definition: Base.h:230
VA_LIST
CHAR8 * VA_LIST
Variable used to traverse the list of arguments.
Definition: Base.h:643
STATIC_ASSERT
#define STATIC_ASSERT
Portable definition for compile time assertions.
Definition: Base.h:808
_LIST_ENTRY
_LIST_ENTRY structure definition.
Definition: Base.h:247
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:46 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: CnviConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Cnvi
Classes | Macros | Enumerations
CnviConfig.h File Reference

CNVi policy. More...

#include <ConfigBlock.h>
Include dependency graph for CnviConfig.h:

Go to the source code of this file.

Classes

struct | CNVI_PIN_MUX
CNVi signals pin muxing settings. More...
struct | CNVI_PREMEM_CONFIG
The CNVI_PREMEM_CONFIG block describes the expected configuration of the CNVi IP. More...

Macros

#define | CNVI_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.
#define | CNVI_PREMEM_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Enumerations

enum | CNVI_MODE
CNVi Mode options.
enum | CNVI_BT_INTERFACE
CNVi Bluetooth interface options.

Detailed Description

CNVi policy.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CnviConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: CnviConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Cnvi
CnviConfig.h
Go to the documentation of this file.
1 /** @file
2 CNVi policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CNVI_CONFIG_H_
36 #define _CNVI_CONFIG_H_
37
38 #include <ConfigBlock.h>
39 /**
40 Making any structure change after API Lock
41 will need to maintain backward compatibility, bump up
42 structure revision and update below history table\n
43 <b>Revision 1</b>: - Initial version.
44 **/
45 #define CNVI_CONFIG_REVISION 1
46 extern EFI_GUID gCnviConfigGuid;
47
48 /**
49 Making any structure change after API Lock
50 will need to maintain backward compatibility, bump up
51 structure revision and update below history table\n
52 <b>Revision 1</b>: - Initial version.
53 **/
54 #define CNVI_PREMEM_CONFIG_REVISION 1
55 extern EFI_GUID gCnviPreMemConfigGuid;
56
57 #pragma pack (push,1)
58
59 /**
60 CNVi Mode options
61 **/
62 typedef enum {
63 CnviModeDisabled = 0,
64 CnviModeAuto
65 } CNVI_MODE;
66
67 /**
68 CNVi Bluetooth interface options
69 **/
70 typedef enum {
71 CnviBtIfUsb = 1,
72 CnviBtIfPci = 2
73 } CNVI_BT_INTERFACE;
74
75
76 /**
77 CNVi signals pin muxing settings. If signal can be enable only on a single pin
78 then this parameter is ignored by RC. Refer to GPIO_*_MUXING_CNVI_* in GpioPins*.h
79 for supported settings on a given platform
80 **/
81 typedef struct {
82 UINT32 RfReset; ///< RF_RESET# Pin mux configuration. Refer to GPIO_*_MUXING_CNVI_RF_RESET_*
83 UINT32 Clkreq; ///< CLKREQ Pin mux configuration. Refer to GPIO_*_MUXING_CNVI_*_CLKREQ_*
84 } CNVI_PIN_MUX;
85
86 typedef struct {
87 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
88 /**
89 This option allows for automatic detection of Connectivity Solution.
90 Auto Detection assumes that CNVi will be enabled when available;
91 Disable allows for disabling CNVi.
92 CnviModeDisabled = Disabled,
93 <b>CnviModeAuto = Auto Detection</b>
94 **/
95 UINT32 Mode : 1;
96 UINT32 BtCore : 1; ///< The option to turn ON or OFF the BT Core. 0: Disabled, <b>1: Enabled</b>
97 /**
98 The option to enable or disable BT Audio Offload.
99 0: Disabled, <b>1: Enabled</b>
100 @note This feature supports from Intel(R) Wireless-AX 22560
101 **/
102 UINT32 BtAudioOffload : 1;
103 UINT32 WifiCore : 1; ///< The option to turn ON or OFF the Wi-Fi Core. 0: Disabled, <b>1: Enabled</b>
104 /**
105 This option allows configuration of BT interface to USB or PCIe
106 Use CNVI_BT_INTERFACE enum for selection:
107 <b>CnviBtIfUsb = BT over USB interface</b>
108 CnviBtIfPci = BT over PCIe interface
109 @note PCIe interface supports from Blazar generation
110 **/
111 UINT32 BtInterface : 2;
112 UINT32 RsvdBits : 26;
113 /**
114 CNVi PinMux Configuration
115 RESET#/CLKREQ to CRF, can have two alternative mappings, depending on board routing requirements.
116 **/
117 CNVI_PIN_MUX PinMux;
118 } CNVI_CONFIG;
119
120
121 /**
122 The CNVI_PREMEM_CONFIG block describes the expected configuration of the CNVi IP.
123
124 <b>Revision 1</b>: - Initial version.
125 **/
126 typedef struct {
127 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
128 UINT8 DdrRfim; ///< The option to enable or disable DDR RFI Mitigation. 0: Disabled, <b>1: Enabled</b>
129 UINT8 RsvdByte[3];
130 } CNVI_PREMEM_CONFIG;
131
132 #pragma pack (pop)
133
134 #endif // _CNVI_CONFIG_H_
ConfigBlock.h
Header file for Config Block Lib implementation.
CNVI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CnviConfig.h:127
CNVI_BT_INTERFACE
CNVI_BT_INTERFACE
CNVi Bluetooth interface options.
Definition: CnviConfig.h:70
CNVI_PIN_MUX::Clkreq
UINT32 Clkreq
CLKREQ Pin mux configuration. Refer to GPIO_*_MUXING_CNVI_*_CLKREQ_*.
Definition: CnviConfig.h:83
CNVI_PREMEM_CONFIG::DdrRfim
UINT8 DdrRfim
The option to enable or disable DDR RFI Mitigation. 0: Disabled, 1: Enabled
Definition: CnviConfig.h:128
CNVI_PIN_MUX
CNVi signals pin muxing settings.
Definition: CnviConfig.h:81
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CNVI_PIN_MUX::RfReset
UINT32 RfReset
RF_RESET# Pin mux configuration. Refer to GPIO_*_MUXING_CNVI_RF_RESET_*.
Definition: CnviConfig.h:82
CNVI_MODE
CNVI_MODE
CNVi Mode options.
Definition: CnviConfig.h:62
CNVI_PREMEM_CONFIG
The CNVI_PREMEM_CONFIG block describes the expected configuration of the CNVi IP.
Definition: CnviConfig.h:126
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ConfigBlock.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Typedefs
ConfigBlock.h File Reference

Header file for Config Block Lib implementation. More...

#include <Uefi/UefiBaseType.h>
#include <Uefi/UefiMultiPhase.h>
#include <Pi/PiBootMode.h>
#include <Pi/PiHob.h>
Include dependency graph for ConfigBlock.h:
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Classes

struct | _CONFIG_BLOCK_HEADER
Config Block Header. More...
struct | _CONFIG_BLOCK
Config Block. More...
struct | _CONFIG_BLOCK_TABLE_STRUCT
Config Block Table Header. More...

Typedefs

typedef struct _CONFIG_BLOCK_HEADER | CONFIG_BLOCK_HEADER
Config Block Header.
typedef struct _CONFIG_BLOCK | CONFIG_BLOCK
Config Block.
typedef struct _CONFIG_BLOCK_TABLE_STRUCT | CONFIG_BLOCK_TABLE_HEADER
Config Block Table Header.

Detailed Description

Header file for Config Block Lib implementation.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2019, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file ConfigBlock.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ConfigBlock.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
ConfigBlock.h
Go to the documentation of this file.
1 /** @file
2 Header file for Config Block Lib implementation
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
7 This program and the accompanying materials are licensed and made available under
8 the terms and conditions of the BSD License that accompanies this distribution.
9 The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php.
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #ifndef _CONFIG_BLOCK_H_
18 #define _CONFIG_BLOCK_H_
19
20 #include <Uefi/UefiBaseType.h>
21 #include <Uefi/UefiMultiPhase.h>
22 #include <Pi/PiBootMode.h>
23 #include <Pi/PiHob.h>
24
25 #pragma pack (push,1)
26
27 ///
28 /// Config Block Header
29 ///
30 typedef struct _CONFIG_BLOCK_HEADER {
31 EFI_HOB_GUID_TYPE GuidHob; ///< Offset 0-23 GUID extension HOB header
32 UINT8 Revision; ///< Offset 24 Revision of this config block
33 UINT8 Attributes; ///< Offset 25 The main revision for config block
34 UINT8 Reserved[2]; ///< Offset 26-27 Reserved for future use
35 } CONFIG_BLOCK_HEADER;
36
37 ///
38 /// Config Block
39 ///
40 typedef struct _CONFIG_BLOCK {
41 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Header of config block
42 //
43 // Config Block Data
44 //
45 } CONFIG_BLOCK;
46
47 ///
48 /// Config Block Table Header
49 ///
50 typedef struct _CONFIG_BLOCK_TABLE_STRUCT {
51 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 GUID number for main entry of config block
52 UINT8 Rsvd0[2]; ///< Offset 28-29 Reserved for future use
53 UINT16 NumberOfBlocks; ///< Offset 30-31 Number of config blocks (N)
54 UINT32 AvailableSize; ///< Offset 32-35 Current config block table size
55 ///
56 /// Individual Config Block Structures are added here in memory as part of AddConfigBlock()
57 ///
58 } CONFIG_BLOCK_TABLE_HEADER;
59 #pragma pack (pop)
60
61 #endif // _CONFIG_BLOCK_H_
62
CONFIG_BLOCK_HEADER
struct _CONFIG_BLOCK_HEADER CONFIG_BLOCK_HEADER
Config Block Header.
UefiBaseType.h
Defines data types and constants introduced in UEFI.
CONFIG_BLOCK
struct _CONFIG_BLOCK CONFIG_BLOCK
Config Block.
_CONFIG_BLOCK_HEADER::Reserved
UINT8 Reserved[2]
Offset 26-27 Reserved for future use.
Definition: ConfigBlock.h:34
_CONFIG_BLOCK_TABLE_STRUCT::NumberOfBlocks
UINT16 NumberOfBlocks
Offset 30-31 Number of config blocks (N)
Definition: ConfigBlock.h:53
_CONFIG_BLOCK_HEADER::Revision
UINT8 Revision
Offset 24 Revision of this config block.
Definition: ConfigBlock.h:32
_CONFIG_BLOCK_TABLE_STRUCT::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 GUID number for main entry of config block.
Definition: ConfigBlock.h:51
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CONFIG_BLOCK_TABLE_HEADER
struct _CONFIG_BLOCK_TABLE_STRUCT CONFIG_BLOCK_TABLE_HEADER
Config Block Table Header.
_CONFIG_BLOCK::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Header of config block.
Definition: ConfigBlock.h:41
_CONFIG_BLOCK_HEADER::Attributes
UINT8 Attributes
Offset 25 The main revision for config block.
Definition: ConfigBlock.h:33
_CONFIG_BLOCK
Config Block.
Definition: ConfigBlock.h:40
_CONFIG_BLOCK_TABLE_STRUCT::Rsvd0
UINT8 Rsvd0[2]
Offset 28-29 Reserved for future use.
Definition: ConfigBlock.h:52
EFI_HOB_GUID_TYPE
Allows writers of executable content in the HOB producer phase to maintain and manage HOBs with speci...
Definition: PiHob.h:345
PiHob.h
HOB related definitions in PI.
_CONFIG_BLOCK_TABLE_STRUCT
Config Block Table Header.
Definition: ConfigBlock.h:50
_CONFIG_BLOCK_TABLE_STRUCT::AvailableSize
UINT32 AvailableSize
Offset 32-35 Current config block table size.
Definition: ConfigBlock.h:54
_CONFIG_BLOCK_HEADER::GuidHob
EFI_HOB_GUID_TYPE GuidHob
Offset 0-23 GUID extension HOB header.
Definition: ConfigBlock.h:31
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ConfigBlockLib.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
ConfigBlockLib.h File Reference

Header file for Config Block Lib implementation. More...

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Functions

EFI_STATUS | CreateConfigBlockTable (IN UINT16 TotalSize, OUT VOID **ConfigBlockTableAddress)
Create config block table. More...
EFI_STATUS | AddConfigBlock (IN VOID *ConfigBlockTableAddress, OUT VOID **ConfigBlockAddress)
Add config block into config block table structure. More...
EFI_STATUS | GetConfigBlock (IN VOID *ConfigBlockTableAddress, IN EFI_GUID *ConfigBlockGuid, OUT VOID **ConfigBlockAddress)
Retrieve a specific Config Block data by GUID. More...

Detailed Description

Header file for Config Block Lib implementation.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2019, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file ConfigBlockLib.h.

Function Documentation

◆ AddConfigBlock()

EFI_STATUS AddConfigBlock | ( | IN VOID * | ConfigBlockTableAddress,
 |  | OUT VOID ** | ConfigBlockAddress
 | ) |  |

Add config block into config block table structure.

Parameters
[in] | ConfigBlockTableAddress | - A pointer to the beginning of Config Block Table Address
[out] | ConfigBlockAddress | - On return, points to a pointer to the beginning of Config Block Address
Return values
EFI_OUT_OF_RESOURCES | - Config Block Table is full and cannot add new Config Block or Config Block Offset Table is full and cannot add new Config Block.
EFI_SUCCESS | - Successfully added Config Block

◆ CreateConfigBlockTable()

EFI_STATUS CreateConfigBlockTable | ( | IN UINT16 | TotalSize,
 |  | OUT VOID ** | ConfigBlockTableAddress
 | ) |  |

Create config block table.

Parameters
[in] | TotalSize | - Max size to be allocated for the Config Block Table
[out] | ConfigBlockTableAddress | - On return, points to a pointer to the beginning of Config Block Table Address
Return values
EFI_INVALID_PARAMETER | - Invalid Parameter
EFI_OUT_OF_RESOURCES | - Out of resources
EFI_SUCCESS | - Successfully created Config Block Table at ConfigBlockTableAddress

◆ GetConfigBlock()

EFI_STATUS GetConfigBlock | ( | IN VOID * | ConfigBlockTableAddress,
 |  | IN EFI_GUID * | ConfigBlockGuid,
 |  | OUT VOID ** | ConfigBlockAddress
 | ) |  |

Retrieve a specific Config Block data by GUID.

Parameters
[in] | ConfigBlockTableAddress | - A pointer to the beginning of Config Block Table Address
[in] | ConfigBlockGuid | - A pointer to the GUID uses to search specific Config Block
[out] | ConfigBlockAddress | - On return, points to a pointer to the beginning of Config Block Address
Return values
EFI_NOT_FOUND | - Could not find the Config Block
EFI_SUCCESS | - Config Block found and return
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ConfigBlockLib.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
ConfigBlockLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for Config Block Lib implementation
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
7 This program and the accompanying materials are licensed and made available under
8 the terms and conditions of the BSD License that accompanies this distribution.
9 The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php.
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #ifndef _CONFIG_BLOCK_LIB_H_
18 #define _CONFIG_BLOCK_LIB_H_
19
20 /**
21 Create config block table
22
23 @param[in] TotalSize - Max size to be allocated for the Config Block Table
24 @param[out] ConfigBlockTableAddress - On return, points to a pointer to the beginning of Config Block Table Address
25
26 @retval EFI_INVALID_PARAMETER - Invalid Parameter
27 @retval EFI_OUT_OF_RESOURCES - Out of resources
28 @retval EFI_SUCCESS - Successfully created Config Block Table at ConfigBlockTableAddress
29 **/
30 EFI_STATUS
31 EFIAPI
32 CreateConfigBlockTable (
33 IN UINT16 TotalSize,
34 OUT VOID **ConfigBlockTableAddress
35 );
36
37 /**
38 Add config block into config block table structure
39
40 @param[in] ConfigBlockTableAddress - A pointer to the beginning of Config Block Table Address
41 @param[out] ConfigBlockAddress - On return, points to a pointer to the beginning of Config Block Address
42
43 @retval EFI_OUT_OF_RESOURCES - Config Block Table is full and cannot add new Config Block or
44 Config Block Offset Table is full and cannot add new Config Block.
45 @retval EFI_SUCCESS - Successfully added Config Block
46 **/
47 EFI_STATUS
48 EFIAPI
49 AddConfigBlock (
50 IN VOID *ConfigBlockTableAddress,
51 OUT VOID **ConfigBlockAddress
52 );
53
54 /**
55 Retrieve a specific Config Block data by GUID
56
57 @param[in] ConfigBlockTableAddress - A pointer to the beginning of Config Block Table Address
58 @param[in] ConfigBlockGuid - A pointer to the GUID uses to search specific Config Block
59 @param[out] ConfigBlockAddress - On return, points to a pointer to the beginning of Config Block Address
60
61 @retval EFI_NOT_FOUND - Could not find the Config Block
62 @retval EFI_SUCCESS - Config Block found and return
63 **/
64 EFI_STATUS
65 EFIAPI
66 GetConfigBlock (
67 IN VOID *ConfigBlockTableAddress,
68 IN EFI_GUID *ConfigBlockGuid,
69 OUT VOID **ConfigBlockAddress
70 );
71
72 #endif // _CONFIG_BLOCK_LIB_H_
73
IN
#define IN
Datum is passed to the function.
Definition: Base.h:279
VOID
#define VOID
Undeclared type.
Definition: Base.h:269
OUT
#define OUT
Datum is returned from the function.
Definition: Base.h:284
EFI_STATUS
RETURN_STATUS EFI_STATUS
Function return status for EFI API.
Definition: UefiBaseType.h:29
AddConfigBlock
EFI_STATUS AddConfigBlock(IN VOID *ConfigBlockTableAddress, OUT VOID **ConfigBlockAddress)
Add config block into config block table structure.
GetConfigBlock
EFI_STATUS GetConfigBlock(IN VOID *ConfigBlockTableAddress, IN EFI_GUID *ConfigBlockGuid, OUT VOID **ConfigBlockAddress)
Retrieve a specific Config Block data by GUID.
CreateConfigBlockTable
EFI_STATUS CreateConfigBlockTable(IN UINT16 TotalSize, OUT VOID **ConfigBlockTableAddress)
Create config block table.
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: CpuPowerMgmtVrConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • VoltageRegulator
Macros
CpuPowerMgmtVrConfig.h File Reference

CPU Power Management VR Config Block. More...

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Macros

#define | MAX_NUM_VRS 6
Defines the maximum number of VR domains supported. More...
#define | CPU_POWER_MGMT_VR_CONFIG_REVISION 2
CPU Power Management VR Configuration Structure. More...

Detailed Description

CPU Power Management VR Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2022 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuPowerMgmtVrConfig.h.

Macro Definition Documentation

◆ CPU_POWER_MGMT_VR_CONFIG_REVISION

#define CPU_POWER_MGMT_VR_CONFIG_REVISION 2

CPU Power Management VR Configuration Structure.

Revision 1:

  • Initial version. Revision 2:
  • Deprecated VccInDemotionEnable, VccInDemotionQuiescentPowerInMw and VccInDemotionCapacitanceInUf Added VccDemotionShutdownThreshold

Definition at line 58 of file CpuPowerMgmtVrConfig.h.

◆ MAX_NUM_VRS

#define MAX_NUM_VRS 6

Defines the maximum number of VR domains supported.

Warning
: Changing this define would cause DWORD alignment issues in policy structures.

Definition at line 46 of file CpuPowerMgmtVrConfig.h.

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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: CpuPowerMgmtVrConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • VoltageRegulator
CpuPowerMgmtVrConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU Power Management VR Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2022 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_POWER_MGMT_VR_CONFIG_H_
36 #define _CPU_POWER_MGMT_VR_CONFIG_H_
37
38 extern EFI_GUID gCpuPowerMgmtVrConfigGuid;
39
40 #pragma pack (push,1)
41
42 ///
43 /// Defines the maximum number of VR domains supported.
44 /// @warning: Changing this define would cause DWORD alignment issues in policy structures.
45 ///
46 #define MAX_NUM_VRS 6
47
48 /**
49 CPU Power Management VR Configuration Structure.
50
51 <b>Revision 1</b>:
52 - Initial version.
53 <b>Revision 2</b>:
54 - Deprecated VccInDemotionEnable, VccInDemotionQuiescentPowerInMw and VccInDemotionCapacitanceInUf
55 Added VccDemotionShutdownThreshold
56 **/
57
58 #define CPU_POWER_MGMT_VR_CONFIG_REVISION 2
59
60 typedef struct {
61 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
62 UINT32 AcousticNoiseMitigation : 1; ///< Enable or Disable Acoustic Noise Mitigation feature. <b>0: Disabled</b>; 1: Enabled
63
64 UINT32 RfiMitigation : 1; ///< Enable or Disable RFI Mitigation. <b>0: Disable - DCM is the IO_N default</b>; 1: Enable - Enable IO_N DCM/CCM switching as RFI mitigation.
65 UINT32 RsvdBits : 30; ///< Reserved for future use.
66 UINT8 PsysSlope; ///< PCODE MMIO Mailbox: Platform Psys slope correction. <b>0: Auto</b> Specified in 1/100 increment values. Range is 0-200. 125 = 1.25.
67 UINT8 Rsvd;
68 UINT16 PsysPmax; ///< PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments. 0-1024 Watts. Value of 800 = 100W.
69
70 /** @name VR Settings
71 The VR related settings are sorted in an array where each index maps to the VR domain as defined below:
72 - 0 = System Agent VR
73 - 1 = IA Core VR
74 - 2 = Ring Vr
75 - 3 = GT VR
76 - 4 = FIVR VR
77
78 The VR settings for a given domain must be populated in the appropriate index.
79 **/
80 ///@{
81 UINT16 TdcCurrentLimit[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. Range is 0-4095. 1000 = 125A. <b>0: 0 Amps</b>
82 UINT16 AcLoadline[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249. <b>Intel Recommended Defaults vary by domain and SKU.</b>
83 UINT16 DcLoadline[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b>
84 UINT16 Psi1Threshold[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A.
85 UINT16 Psi2Threshold[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A.
86 UINT16 Psi3Threshold[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A.
87 INT32 ImonOffset[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range is [-128000, 127999]. For an offset = 12.580, use 12580. <b>0: Auto</b>
88 UINT16 IccMax[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A. <b>Default: 0 - Auto, no override</b>
89 UINT16 VrVoltageLimit[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV.
90 UINT16 ImonSlope[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. <b>0: Auto</b>
91 UINT8 Psi3Enable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.
92 UINT8 Psi4Enable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.
93 UINT8 VrConfigEnable[MAX_NUM_VRS]; ///< Enable/Disable BIOS configuration of VR; 0: Disable; <b>1: Enable.</b>
94 UINT8 TdcEnable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable; </b>1: Enable
95 UINT8 TdcLock[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.
96 UINT8 FastPkgCRampDisable[MAX_NUM_VRS]; ///< Disable Fast Slew Rate for Deep Package C States for VR IA,GT,SA,VLCC,FIVR domain based on Acoustic Noise Mitigation feature enabled. <b>0: False</b>; 1: True
97 UINT8 SlowSlewRate[MAX_NUM_VRS]; ///< Slew Rate configuration for Deep Package C States for VR VR IA,GT,SA,VLCC,FIVR domain based on Acoustic Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
98 ///@}
99 UINT8 Rsvd1[2]; /// Make sure nature alignment
100 INT32 PsysOffset; ///< PCODE MMIO Mailbox: Platform Psys offset correction. <b>0: Auto</b> 32-bit signed value (2's complement). Units 1/1000, Range is [-128000, 127999]. For an offset of 25.348, enter 25348.
101 UINT32 TdcTimeWindow[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. <b>1ms default</b>
102 UINT8 Irms[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Current root mean square. <b>0: Disable</b>; 1: Enable.
103 UINT8 FivrSpectrumEnable; ///< Enable or Disable FIVR Spread Spectrum 0: Disable; <b> 1: Enable.</b>
104 UINT8 DlvrSpreadSpectrumPercentage; ///< PCODE MMIO Mailbox: Encoded DLVR SSC value. 0x0 = Disabled. u3.2 value from 0% - 7.75%.
105 UINT8 DlvrRfiEnable; ///< PCODE MMIO Mailbox: Enable/Disable RFI frequency hopping. 0: Disable; <b>1: Enable.</b>
106 UINT8 PreWake; ///< PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMitigation is enabled.<b>Default Value = 0 micro ticks</b> Defines the max pre-wake randomization time in micro ticks. Range is 0-255.
107 UINT8 RampUp; ///< PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMitigation is enabled.<b>Default Value = 0 micro ticks</b> Defines the max ramp up randomization time in micro ticks. Range is 0-255.
108 UINT8 RampDown; ///< PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMitigation is enabled.<b>Default Value = 0 micro ticks</b> Defines the max ramp down randomization time in micro ticks. Range is 0-255.
109 UINT16 DlvrRfiFrequency; ///< PCODE MMIO Mailbox: DLVR clock frequency in MHz.
110 UINT8 PS1toPS0DynamicCutoffEnable[MAX_NUM_VRS];///< Enable/Disable PS1 to PS0 Dynamic Cutoff; <b>0: Disable</b>; 1: Enable.
111 UINT8 PS2toPS1DynamicCutoffEnable[MAX_NUM_VRS];///< Enable/Disable:PS2 to PS1 Dynamic Cutoff; <b>0: Disable</b>; 1: Enable.
112 UINT16 PS1toPS0MCoef[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: PS1 to PS0 M Coef. This number is in M*100 units. <b>Default: 100</b> Range: 0-4096.
113 INT16 PS1toPS0CCoef[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: PS1 to PS0 C Coef. This number is in C*100 units. <b>Default: 2000</b> Range: 0-4096.
114 UINT16 PS2toPS1MCoef[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: PS2 to PS1 M Coef. This number is in M*100 units. <b>Default: 100</b> Range: 0-4096.
115 INT16 PS2toPS1CCoef[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: PS2 to PS1 C Coef. This number is in C*100 units. <b>Default: 500</b> Range: 0-4096.
116 /**
117 This field is required to be non-zero on Desktop platforms.
118
119 Used to communicate the power delivery design capability of the board. This value is an
120 enum of the available power delivery segments that are defined in the Platform Design Guide.
121 This is required due to CPU socket compatibility across different board designs. Without
122 this field populated, the system may experience VR OCP/OVP shutdowns, hangs, thermal and
123 performance loss.
124 <b> 0 - Disable </b>
125 **/
126 UINT8 VrPowerDeliveryDesign;
127 /**
128 Enables / Disables DLVR's PHASE_SSC feature.
129 **/
130 UINT8 DlvrPhaseSsc; ///< Enable/Disable DLVR PHASE_SSC. <b>0: Disable.</b> 1:Disable
131 /**
132 Enable VCC Demotion.
133 0: Disable;
134 <b>1: Enable with default threshold</b>;
135 2: Enable with user configured threshold.
136 **/
137 UINT8 VccInDemotionEnable[MAX_NUM_VRS]; // Deprecated from Revision 2
138 /**
139 User configured platform quiescent threshold in milli-watt
140 when VCC Demotion is enabled with user configured threshold.
141 Range: 0-255.
142 **/
143 UINT8 VccInDemotionQuiescentPowerInMw[MAX_NUM_VRS]; // Deprecated from Revision 2
144 /**
145 User configured VR's quiescent power threshold in micro-farad
146 when VCC Demotion is enabled with user configured threshold.
147 Range: 0-2000.
148 **/
149 UINT32 VccInDemotionCapacitanceInUf[MAX_NUM_VRS]; // Deprecated from Revision 2
150
151 UINT8 EnableVsysCritical; ///< PCODE MMIO Mailbox: Enable/Disable Vsys Critical; <b>0: Disable</b>; 1: Enable.
152 /**
153 Set Assertion Deglitch [0x4F] and De-Assertion Deglitch [0x49]
154 Provide 2 fields in BIOS Menu for Assertion/De-Assertion Deglitch: Mantissa and Exponent.
155 The format for Assertion/De-Assertion Deglitch: 0.002ms * Mantissa * 2^(Exponent).
156 **/
157 UINT8 VsysAssertionDeglitchMantissa;
158 UINT8 VsysAssertionDeglitchExponent;
159 UINT8 VsysDeassertionDeglitchMantissa;
160 UINT8 VsysDeassertionDeglitchExponent;
161 UINT8 Rsvd2;
162 /**
163 PCODE VR Mailbox: Voltage Regulator Fast Vmode ICC Limit.
164 This value represents the current threshold where the VR would initiate reactive protection if Fast Vmode is enabled.
165 A value of 0 corresponds to feature disabled (no reactive protection).
166 <b>Default: 0 - Disable, no override</b>
167 **/
168 UINT16 IccLimit[MAX_NUM_VRS];
169 UINT8 CepEnable[MAX_NUM_VRS]; ///< Enable IA/GT/SA Current Excursion Protection. <b>1: Enable</b>. 0: Disable.
170 UINT8 SirpEnable[MAX_NUM_VRS]; ///< Enable IA SoC Iccmax Reactive Protector. <b>1: Enable</b>. 0: Disable.
171 /**
172 VR Fast Vmode.
173 Use to control Fast Vmode Enable/Disable by VR domain.
174 <b>Default: 0 - Disable, no override</b>
175 **/
176 UINT8 EnableFastVmode[MAX_NUM_VRS];
177 UINT8 FastVmodeOffset[MAX_NUM_VRS];
178 UINT8 SvidStabilizationDelay;
179 UINT8 Rsvd3;
180 /**
181 Set Vsys/Pysy Critical [0x4A]
182 Write to 0x4A to program Vsys Critical Threshold which is a linear fractional value of the Vsys input full scale voltage
183 where minimun is 0 and maximum is 255000mv
184 For example: Vsys_Crit (0x4A) = (Critical Threshold/Full Scale) * 0xFF
185 **/
186 UINT32 VsysFullScale;
187 UINT32 VsysCriticalThreshold;
188 UINT32 PsysFullScale;
189 UINT32 PsysCriticalThreshold;
190 /**
191 VCC Demotion Shutdown Threshold
192 User configured time threshold in msec.
193 Range: 0-255.
194 **/
195 UINT8 VccDemotionShutdownThreshold[MAX_NUM_VRS];
196 UINT8 Rsvd4[2]; /// Make sure nature alignment
197 } CPU_POWER_MGMT_VR_CONFIG;
198
199 #pragma pack (pop)
200
201 #endif // _CPU_POWER_MGMT_VR_CONFIG_H_
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
MAX_NUM_VRS
#define MAX_NUM_VRS
Defines the maximum number of VR domains supported.
Definition: CpuPowerMgmtVrConfig.h:46
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:46 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: DciConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Dci
Classes
DciConfig.h File Reference

Dci policy. More...

#include <ConfigBlock.h>
Include dependency graph for DciConfig.h:

Go to the source code of this file.

Classes

struct PCH_DCI_PREMEM_CONFIG
The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct Connection Interface (DCI) More...

Detailed Description

Dci policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file DciConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: DciConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Dci
DciConfig.h
Go to the documentation of this file.
1 /** @file
2 Dci policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _DCI_CONFIG_H_
36 #define _DCI_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 #define PCH_DCI_PREMEM_CONFIG_REVISION 1
41 extern EFI_GUID gDciPreMemConfigGuid;
42
43 #pragma pack (push,1)
44
45 typedef enum {
46 DciDbcDisabled = 0x0,
47 DciDbcUsb2 = 0x1,
48 DciDbcUsb3 = 0x2,
49 DciDbcBoth = 0x3,
50 DciDbcNoChange = 0x4,
51 DciDbcMax
52 } DCI_DBC_MODE;
53
54 typedef enum {
55 Usb3TcDbgDisabled = 0x0,
56 Usb3TcDbgEnabled = 0x1,
57 Usb3TcDbgNoChange = 0x2,
58 Usb3TcDbgMax
59 } DCI_USB3_TYPE_C_DEBUG_MODE;
60
61 typedef enum {
62 KetDisabled = 0x0,
63 KetEnabled = 0x1,
64 KetNoChange = 0x2,
65 KetMax
66 } KET_MODE;
67
68 /**
69 The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct Connection Interface (DCI)
70
71 <b>Revision 1</b>:
72 - Initial version.
73 **/
74 typedef struct {
75 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
76 /**
77 DCI enable.
78 Determine if to enable DCI debug from host.
79 <b>0:Disabled</b>; 1:Enabled
80 **/
81 UINT8 DciEn;
82 /**
83 USB DbC enable mode.
84 Disabled: Clear both USB2/3DBCEN; USB2: Set USB2DBCEN; USB3: Set USB3DBCEN; Both: Set both USB2/3DBCEN; No Change: Comply with HW value
85 Refer to definition of DCI_USB_DBC_MODE for supported settings.
86 0:Disabled; 1:USB2; 2:USB3; 3:Both; <b>4:No Change</b>
87 **/
88 UINT8 DciDbcMode;
89 /**
90 USB3 Type-C UFP2DFP kenel / platform debug support. No change will do nothing to UFP2DFP configuration.
91 When enabled, USB3 Type C UFP (upstream-facing port) may switch to DFP (downstream-facing port) for first connection.
92 It must be enabled for USB3 kernel(kernel mode debug) and platform debug(DFx, DMA, Trace) over UFP Type-C receptacle.
93 Refer to definition of DCI_USB_TYPE_C_DEBUG_MODE for supported settings.
94 0:Disabled; 1:Enabled; <b>2:No Change</b>
95 **/
96 UINT8 DciUsb3TypecUfpDbg;
97 /**
98 Determine if to enable or disable DCI clock request in lowest power state.
99 0:Disabled; <b>1:Enabled</b>
100 **/
101 UINT8 DciClkEnable;
102 /**
103 Early trace is activated by default.
104 Enable to keep early trace data and keep tracing; disable to stop tracing;
105 When debug probe is connected and granted, force to no change, let host tool to set it.
106 <b>0: Disable</b>; 1: Enable early trace; 2:No Change;
107 **/
108 UINT8 KeepEarlyTrace;
109 UINT8 ReservedBytes[3];
110 } PCH_DCI_PREMEM_CONFIG;
111
112 #pragma pack (pop)
113
114 #endif // _DCI_CONFIG_H_
PCH_DCI_PREMEM_CONFIG::DciEn
UINT8 DciEn
DCI enable.
Definition: DciConfig.h:81
ConfigBlock.h
Header file for Config Block Lib implementation.
PCH_DCI_PREMEM_CONFIG::KeepEarlyTrace
UINT8 KeepEarlyTrace
Early trace is activated by default.
Definition: DciConfig.h:108
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_DCI_PREMEM_CONFIG::DciDbcMode
UINT8 DciDbcMode
USB DbC enable mode.
Definition: DciConfig.h:88
PCH_DCI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: DciConfig.h:75
PCH_DCI_PREMEM_CONFIG::DciClkEnable
UINT8 DciClkEnable
Determine if to enable or disable DCI clock request in lowest power state.
Definition: DciConfig.h:101
PCH_DCI_PREMEM_CONFIG::DciUsb3TypecUfpDbg
UINT8 DciUsb3TypecUfpDbg
USB3 Type-C UFP2DFP kenel / platform debug support.
Definition: DciConfig.h:96
PCH_DCI_PREMEM_CONFIG
The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct Connection Interface (DCI)
Definition: DciConfig.h:74
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:46 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: EspiConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Espi
Macros
EspiConfig.h File Reference

Espi policy. More...

Go to the source code of this file.

Macros

#define PCH_ESPI_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Detailed Description

Espi policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file EspiConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: EspiConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Espi
EspiConfig.h
Go to the documentation of this file.
1 /** @file
2 Espi policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ESPI_CONFIG_H_
36 #define _ESPI_CONFIG_H_
37
38 /**
39 Making any structure change after API Lock
40 will need to maintain backward compatibility, bump up
41 structure revision and update below history table\n
42 <b>Revision 1</b>: - Initial version.
43 **/
44 #define PCH_ESPI_CONFIG_REVISION 1
45 extern EFI_GUID gEspiConfigGuid;
46
47 #pragma pack (push,1)
48
49 typedef struct {
50 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
51 /**
52 LPC (eSPI) Memory Range Decode Enable. When TRUE, then the range
53 specified in PCLGMR[31:16] is enabled for decoding to LPC (eSPI).
54 <b>0: FALSE</b>, 1: TRUE
55 **/
56 UINT32 LgmrEnable : 1;
57 /**
58 eSPI host and device BME settings.
59 When TRUE, then the BME bit enabled in eSPI host and device.
60 0: FALSE, <b>1: TRUE </b>
61 **/
62 UINT32 BmeHostDeviceEnabled : 1;
63 /**
64 Host HOST_C10 (Virtual Wire) to device Enable (VWHC10OE)
65 <b>0b: Disable HOST_C10 reporting (HOST_C10 indication from PMC is ignored)</b>
66 1b: Enable HOST_C10 reporting to device via eSPI Virtual Wire (upon receiving a HOST_C10 indication from PMC)
67 **/
68 UINT32 HostC10ReportEnable : 1;
69 /**
70 eSPI Link Configuration Lock (SBLCL)
71 If set to TRUE then communication through SET_CONFIG/GET_CONFIG
72 to eSPI device addresses from range 0x0 - 0x7FF
73 <b>1: TRUE</b>, 0: FALSE
74 **/
75 UINT32 LockLinkConfiguration : 1;
76 /**
77 Hardware Autonomous Enable (HAE)
78 If set to TRUE, then the IP may request a PG whenever it is idle
79 **/
80 UINT32 EspiPmHAE : 1;
81 /**
82 Disable/Enable Non-Fatal Error Reporting (PCNFEE)
83 If set to TRUE, then NFE bit of PCERR_SLV0 and PCERR_SLV1 is cleared which disables non-fatal error reporting
84 **/
85 UINT32 HideNonFatalErrors : 1;
86
87 UINT32 RsvdBits : 26; ///< Reserved bits
88 } PCH_ESPI_CONFIG;
89
90 #pragma pack (pop)
91
92 #endif // _ESPI_CONFIG_H_
93
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:46 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: FivrConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Fivr
Classes | Enumerations
FivrConfig.h File Reference

PCH FIVR policy. More...

Go to the source code of this file.

Classes

struct | FIVR_EXT_RAIL_CONFIG
Structure for V1p05/Vnn VR rail configuration. More...
struct | FIVR_VCCIN_AUX_CONFIG
Structure for VCCIN_AUX voltage rail configuration. More...
struct | PCH_FIVR_CONFIG
The PCH_FIVR_CONFIG block describes FIVR settings. More...

Enumerations

enum FIVR_RAIL_SX_STATE
Rail support in S0ix and Sx Settings other than FivrRailDisabled can be OR'ed.

Detailed Description

PCH FIVR policy.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file FivrConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: FivrConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Fivr
FivrConfig.h
Go to the documentation of this file.
1 /** @file
2 PCH FIVR policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _FIVR_CONFIG_H_
36 #define _FIVR_CONFIG_H_
37
38 #define PCH_FIVR_CONFIG_REVISION 1
39 extern EFI_GUID gFivrConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 Rail support in S0ix and Sx
45 Settings other than FivrRailDisabled can be OR'ed
46 **/
47 typedef enum {
48 FivrRailDisabled = 0,
49 FivrRailInS0i1S0i2 = BIT0,
50 FivrRailInS0i3 = BIT1,
51 FivrRailInS3 = BIT2,
52 FivrRailInS4 = BIT3,
53 FivrRailInS5 = BIT4,
54 FivrRailInS0ix = FivrRailInS0i1S0i2 | FivrRailInS0i3,
55 FivrRailInSx = FivrRailInS3 | FivrRailInS4 | FivrRailInS5,
56 FivrRailAlwaysOn = FivrRailInS0ix | FivrRailInSx
57 } FIVR_RAIL_SX_STATE;
58
59 typedef enum {
60 FivrRetentionActive = BIT0,
61 FivrNormActive = BIT1,
62 FivrMinActive = BIT2,
63 FivrMinRetention = BIT3
64 } FIVR_RAIL_SUPPORTED_VOLTAGE;
65
66 /**
67 Structure for V1p05/Vnn VR rail configuration
68 **/
69 typedef struct {
70 /**
71 Mask to enable the usage of external VR rail in specific S0ix or Sx states
72 Use values from FIVR_RAIL_SX_STATE
73 The default is <b>FivrRailDisabled</b>.
74 **/
75 UINT32 EnabledStates : 6;
76
77 /**
78 VR rail voltage value that will be used in S0i2/S0i3 states.
79 This value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
80 The default for Vnn is set to <b>420 - 1050 mV</b>.
81 **/
82 UINT32 Voltage : 11;
83 /**
84 UINT32 Alignement
85 **/
86 UINT32 RsvdBits1 : 15;
87 /**
88 This register holds the control hold off values to be used when
89 changing the rail control for external bypass value in us
90 **/
91 UINT32 CtrlRampTmr : 8;
92
93 /**
94 Mask to set the supported configuration in VR rail.
95 Use values from FIVR_RAIL_SUPPORTED_VOLTAGE
96 **/
97 UINT32 SupportedVoltageStates : 4;
98
99 /**
100 VR rail Icc Maximum Value
101 Granularity of this setting is 1mA and maximal possible value is 500mA
102 The default is <b> 0mA </b>.
103 **/
104 UINT32 IccMaximum : 16;
105 /**
106 UINT32 Alignment
107 **/
108 UINT32 RsvdBits2 : 4;
109
110 } FIVR_EXT_RAIL_CONFIG;
111
112
113 /**
114 Structure for VCCIN_AUX voltage rail configuration
115 **/
116 typedef struct {
117 /**
118 Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage.
119 Voltage transition time required by motherboard voltage regulator when PCH changes
120 the VCCIN_AUX regulator set point from the low current mode voltage and high current mode voltage.
121 This field has 1us resolution.
122 When value is 0 PCH will not transition VCCIN_AUX to low current mode voltage.
123 The default is <b> 0xC </b>.
124 **/
125 UINT8 LowToHighCurModeVolTranTime;
126
127 /**
128 Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage.
129 Voltage transition time required by motherboard voltage regulator when PCH changes
130 the VCCIN_AUX regulator set point from the retention mode voltage to high current mode voltage.
131 This field has 1us resolution.
132 When value is 0 PCH will not transition VCCIN_AUX to retention voltage.
133 The default is <b> 0x36 </b>.
134 **/
135 UINT8 RetToHighCurModeVolTranTime;
136
137 /**
138 Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage.
139 Voltage transition time required by motherboard voltage regulator when PCH changes
140 the VCCIN_AUX regulator set point from the retention mode voltage to low current mode voltage.
141 This field has 1us resolution.
142 When value is 0 PCH will not transition VCCIN_AUX to retention voltage.
143 The default is <b> 0x2B </b>.
144 **/
145 UINT8 RetToLowCurModeVolTranTime;
146 UINT8 RsvdByte1;
147 /**
148 Transition time in microseconds from Off (0V) to High Current Mode Voltage.
149 Voltage transition time required by motherboard voltage regulator when PCH changes
150 the VCCIN_AUX regulator set point from 0V to the high current mode voltage.
151 This field has 1us resolution.
152 0 = Transition to 0V is disabled
153 Setting this field to 0 sets VCCIN_AUX as a fixed rail that stays on
154 in all S0 & Sx power states after initial start up on G3 exit
155 The default is <b> 0x96 </b>.
156 **/
157 UINT32 OffToHighCurModeVolTranTime : 11;
158 UINT32 RsvdBits1 : 21;
159 } FIVR_VCCIN_AUX_CONFIG;
160
161 /**
162 The PCH_FIVR_CONFIG block describes FIVR settings.
163 **/
164 typedef struct {
165 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
166 /**
167 External V1P05 VR rail configuration.
168 **/
169 FIVR_EXT_RAIL_CONFIG ExtV1p05Rail;
170 /**
171 External Vnn VR rail configuration.
172 **/
173 FIVR_EXT_RAIL_CONFIG ExtVnnRail;
174 /**
175 Additional External Vnn VR rail configuration that will get applied
176 in Sx entry SMI callback. Required only if External Vnn VR
177 needs different settings for Sx than those specified in ExtVnnRail.
178 **/
179 FIVR_EXT_RAIL_CONFIG ExtVnnRailSx;
180 /**
181 VCCIN_AUX voltage rail configuration.
182 **/
183 FIVR_VCCIN_AUX_CONFIG VccinAux;
184
185 /**
186 Enable/Disable FIVR Dynamic Power Management
187 Default is <b> 1 </b>.
188 **/
189 UINT32 FivrDynPm : 1;
190 UINT32 RsvdBits2 : 31;
191 } PCH_FIVR_CONFIG;
192
193 #pragma pack (pop)
194
195 #endif // _FIVR_CONFIG_H_
FIVR_EXT_RAIL_CONFIG::IccMaximum
UINT32 IccMaximum
VR rail Icc Maximum Value Granularity of this setting is 1mA and maximal possible value is 500mA The ...
Definition: FivrConfig.h:104
PCH_FIVR_CONFIG
The PCH_FIVR_CONFIG block describes FIVR settings.
Definition: FivrConfig.h:164
FIVR_EXT_RAIL_CONFIG
Structure for V1p05/Vnn VR rail configuration.
Definition: FivrConfig.h:69
FIVR_VCCIN_AUX_CONFIG::OffToHighCurModeVolTranTime
UINT32 OffToHighCurModeVolTranTime
Transition time in microseconds from Off (0V) to High Current Mode Voltage.
Definition: FivrConfig.h:157
PCH_FIVR_CONFIG::ExtV1p05Rail
FIVR_EXT_RAIL_CONFIG ExtV1p05Rail
External V1P05 VR rail configuration.
Definition: FivrConfig.h:169
PCH_FIVR_CONFIG::VccinAux
FIVR_VCCIN_AUX_CONFIG VccinAux
VCCIN_AUX voltage rail configuration.
Definition: FivrConfig.h:183
PCH_FIVR_CONFIG::ExtVnnRail
FIVR_EXT_RAIL_CONFIG ExtVnnRail
External Vnn VR rail configuration.
Definition: FivrConfig.h:173
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
FIVR_VCCIN_AUX_CONFIG::RetToLowCurModeVolTranTime
UINT8 RetToLowCurModeVolTranTime
Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage.
Definition: FivrConfig.h:145
FIVR_RAIL_SX_STATE
FIVR_RAIL_SX_STATE
Rail support in S0ix and Sx Settings other than FivrRailDisabled can be OR'ed.
Definition: FivrConfig.h:47
FIVR_EXT_RAIL_CONFIG::Voltage
UINT32 Voltage
VR rail voltage value that will be used in S0i2/S0i3 states.
Definition: FivrConfig.h:82
PCH_FIVR_CONFIG::FivrDynPm
UINT32 FivrDynPm
Enable/Disable FIVR Dynamic Power Management Default is 1 .
Definition: FivrConfig.h:189
FIVR_EXT_RAIL_CONFIG::CtrlRampTmr
UINT32 CtrlRampTmr
This register holds the control hold off values to be used when changing the rail control for externa...
Definition: FivrConfig.h:91
FIVR_EXT_RAIL_CONFIG::SupportedVoltageStates
UINT32 SupportedVoltageStates
Mask to set the supported configuration in VR rail.
Definition: FivrConfig.h:97
PCH_FIVR_CONFIG::ExtVnnRailSx
FIVR_EXT_RAIL_CONFIG ExtVnnRailSx
Additional External Vnn VR rail configuration that will get applied in Sx entry SMI callback.
Definition: FivrConfig.h:179
FIVR_EXT_RAIL_CONFIG::EnabledStates
UINT32 EnabledStates
Mask to enable the usage of external VR rail in specific S0ix or Sx states Use values from FIVR_RAIL_...
Definition: FivrConfig.h:75
FIVR_VCCIN_AUX_CONFIG
Structure for VCCIN_AUX voltage rail configuration.
Definition: FivrConfig.h:116
FIVR_VCCIN_AUX_CONFIG::LowToHighCurModeVolTranTime
UINT8 LowToHighCurModeVolTranTime
Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage.
Definition: FivrConfig.h:125
FIVR_VCCIN_AUX_CONFIG::RetToHighCurModeVolTranTime
UINT8 RetToHighCurModeVolTranTime
Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage.
Definition: FivrConfig.h:135
PCH_FIVR_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: FivrConfig.h:165
FIVR_EXT_RAIL_CONFIG::RsvdBits2
UINT32 RsvdBits2
UINT32 Alignment.
Definition: FivrConfig.h:108
FIVR_EXT_RAIL_CONFIG::RsvdBits1
UINT32 RsvdBits1
UINT32 Alignement.
Definition: FivrConfig.h:86
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:46 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: FlashProtectionConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Spi
Classes
FlashProtectionConfig.h File Reference

FlashProtection policy. More...

Go to the source code of this file.

Classes

struct | PROTECTED_RANGE
Protected Flash Range. More...
struct | PCH_FLASH_PROTECTION_CONFIG
The PCH provides a method for blocking writes and reads to specific ranges in the SPI flash when the Protected Ranges are enabled. More...

Detailed Description

FlashProtection policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file FlashProtectionConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: FlashProtectionConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Spi
FlashProtectionConfig.h
Go to the documentation of this file.
1 /** @file
2 FlashProtection policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _FLASH_PROTECTION_CONFIG_H_
36 #define _FLASH_PROTECTION_CONFIG_H_
37
38 #define PCH_FLASH_PROTECTION_CONFIG_REVISION 1
39 extern EFI_GUID gFlashProtectionConfigGuid;
40
41 #pragma pack (push,1)
42
43 //
44 // Flash Protection Range Register
45 //
46 #define PCH_FLASH_PROTECTED_RANGES 5
47
48 /**
49 Protected Flash Range
50 **/
51 typedef struct {
52 UINT32 WriteProtectionEnable : 1; ///< Write or erase is blocked by hardware. <b>0: Disable</b>; 1: Enable.
53 UINT32 ReadProtectionEnable : 1; ///< Read is blocked by hardware. <b>0: Disable</b>; 1: Enable.
54 UINT32 RsvdBits : 30; ///< Reserved
55 /**
56 The address of the upper limit of protection
57 This is a left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison
58 **/
59 UINT16 ProtectedRangeLimit;
60 /**
61 The address of the upper limit of protection
62 This is a left shifted address by 12 bits with address bits 11:0 are assumed to be 0
63 **/
64 UINT16 ProtectedRangeBase;
65 } PROTECTED_RANGE;
66
67 /**
68 The PCH provides a method for blocking writes and reads to specific ranges
69 in the SPI flash when the Protected Ranges are enabled.
70 PROTECTED_RANGE is used to specify if flash protection are enabled,
71 the write protection enable bit and the read protection enable bit,
72 and to specify the upper limit and lower base for each register
73 Platform code is responsible to get the range base by PchGetSpiRegionAddresses routine,
74 and set the limit and base accordingly.
75 **/
76 typedef struct {
77 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
78 PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES]; ///< Protected Flash Ranges
79 } PCH_FLASH_PROTECTION_CONFIG;
80
81 #pragma pack (pop)
82
83 #endif // _FLASH_PROTECTION_CONFIG_H_
PROTECTED_RANGE::ReadProtectionEnable
UINT32 ReadProtectionEnable
Read is blocked by hardware. 0: Disable; 1: Enable.
Definition: FlashProtectionConfig.h:53
PROTECTED_RANGE::RsvdBits
UINT32 RsvdBits
Reserved.
Definition: FlashProtectionConfig.h:54
PROTECTED_RANGE
Protected Flash Range.
Definition: FlashProtectionConfig.h:51
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PROTECTED_RANGE::ProtectedRangeBase
UINT16 ProtectedRangeBase
The address of the upper limit of protection This is a left shifted address by 12 bits with address b...
Definition: FlashProtectionConfig.h:64
PROTECTED_RANGE::WriteProtectionEnable
UINT32 WriteProtectionEnable
Write or erase is blocked by hardware. 0: Disable; 1: Enable.
Definition: FlashProtectionConfig.h:52
PCH_FLASH_PROTECTION_CONFIG
The PCH provides a method for blocking writes and reads to specific ranges in the SPI flash when the ...
Definition: FlashProtectionConfig.h:76
PCH_FLASH_PROTECTION_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: FlashProtectionConfig.h:77
PROTECTED_RANGE::ProtectedRangeLimit
UINT16 ProtectedRangeLimit
The address of the upper limit of protection This is a left shifted address by 12 bits with address b...
Definition: FlashProtectionConfig.h:59
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:46 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: FspErrorInfo.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • Guid
Classes | Macros
FspErrorInfo.h File Reference

FSP Error Information HOB to describe errors inside FSP that bootloader may take some actions to handle those error scenarios. More...

Go to the source code of this file.

Classes

struct FSP_ERROR_INFO_HOB
FSP Error Information Block. More...

Macros

#define FSP_ERROR_INFO_HOB_GUID
GUID value indicating the FSP error information.

Detailed Description

FSP Error Information HOB to describe errors inside FSP that bootloader may take some actions to handle those error scenarios.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file FspErrorInfo.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: FspErrorInfo.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • Guid
FspErrorInfo.h
Go to the documentation of this file.
1 /** @file
2 FSP Error Information HOB to describe errors inside FSP that bootloader may
3 take some actions to handle those error scenarios.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2019 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
30 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
31 the terms of your license agreement with Intel or your vendor. This file may
32 be modified by the user, subject to additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36
37 #ifndef _FSP_ERROR_INFO_H_
38 #define _FSP_ERROR_INFO_H_
39
40 ///
41 /// GUID value indicating the FSP error information.
42 ///
43 #define FSP_ERROR_INFO_HOB_GUID \
44 { \
45 0x611e6a88, 0xadb7, 0x4301, { 0x93, 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6 } \
46 }
47 #define STATUS_CODE_DATA_TYPE_FSP_ERROR_GUID \
48 { \
49 0x611e6a88, 0xadb7, 0x4301, { 0x93, 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6 } \
50 }
51
52 #define FSP_ERROR_INFO_STATUS_CODE_TYPE (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED)
53 #define FSP_ERROR_INFO_STATUS_CODE_VALUE 0
54 #define FSP_ERROR_INFO_STATUS_CODE_INSTANCE 0
55
56 ///
57 /// FSP Error Information Block.
58 ///
59 #pragma pack(1)
60 typedef struct {
61 ///
62 /// GUID HOB header.
63 ///
64 EFI_HOB_GUID_TYPE GuidHob;
65
66 ///
67 /// ReportStatusCode () type identifier.
68 ///
69 EFI_STATUS_CODE_TYPE Type;
70
71 ///
72 /// ReportStatusCode () value.
73 ///
74 EFI_STATUS_CODE_VALUE Value;
75
76 ///
77 /// ReportStatusCode () Instance number.
78 ///
79 UINT32 Instance;
80
81 ///
82 /// Optional GUID which may be used to identify
83 /// which internal component of the FSP was
84 /// executing at the time of the error.
85 ///
86 EFI_GUID CallerId;
87
88 ///
89 /// GUID identifying the nature of the fatal error.
90 ///
91 EFI_GUID ErrorType;
92
93 ///
94 /// EFI_STATUS code describing the error encountered.
95 ///
96 UINT32 Status;
97 } FSP_ERROR_INFO_HOB;
98
99 typedef struct {
100 ///
101 /// A GUID identifying the nature of the fatal error.
102 /// This GUID is platform speciic.
103 ///
104 EFI_GUID ErrorType;
105
106 ///
107 /// A code describing the error encountered.
108 ///
109 EFI_STATUS Status;
110 } FSP_ERROR_INFO;
111
112 #pragma pack()
113
114 extern GUID gFspErrorInfoHobGuid;
115
116 #endif //_FSP_ERROR_INFO_H_
FSP_ERROR_INFO_HOB::Value
EFI_STATUS_CODE_VALUE Value
ReportStatusCode () value.
Definition: FspErrorInfo.h:74
FSP_ERROR_INFO_HOB::CallerId
EFI_GUID CallerId
Optional GUID which may be used to identify which internal component of the FSP was executing at the ...
Definition: FspErrorInfo.h:86
FSP_ERROR_INFO_HOB::Instance
UINT32 Instance
ReportStatusCode () Instance number.
Definition: FspErrorInfo.h:79
FSP_ERROR_INFO_HOB::Status
UINT32 Status
EFI_STATUS code describing the error encountered.
Definition: FspErrorInfo.h:96
EFI_STATUS
RETURN_STATUS EFI_STATUS
Function return status for EFI API.
Definition: UefiBaseType.h:29
FSP_ERROR_INFO_HOB
FSP Error Information Block.
Definition: FspErrorInfo.h:60
FSP_ERROR_INFO_HOB::GuidHob
EFI_HOB_GUID_TYPE GuidHob
GUID HOB header.
Definition: FspErrorInfo.h:64
EFI_HOB_GUID_TYPE
Allows writers of executable content in the HOB producer phase to maintain and manage HOBs with speci...
Definition: PiHob.h:345
FSP_ERROR_INFO_HOB::Type
EFI_STATUS_CODE_TYPE Type
ReportStatusCode () type identifier.
Definition: FspErrorInfo.h:69
FSP_ERROR_INFO_HOB::ErrorType
EFI_GUID ErrorType
GUID identifying the nature of the fatal error.
Definition: FspErrorInfo.h:91
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:46 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: FspFixedPcds.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • MeteorLakeFspBinPkg
  • DoxygenInternalOnly
Macros
FspFixedPcds.h File Reference

This file lists all FixedAtBuild PCDs referenced in FSP integration guide. More...

Go to the source code of this file.

Macros

#define | PcdFspAreaBaseAddress 0xFFD00000
FspAreaBaseAddress.
#define | PcdFspImageIdString $MTLFSP$
FspImageIdString.
#define | PcdSiliconInitVersionMajor 0x0D
SiliconInitVersionMajor.
#define | PcdSiliconInitVersionMinor 0x00
SiliconInitVersionMinor.
#define | PcdSiliconInitVersionRevision 0x05
SiliconInitVersionRevision.
#define | PcdSiliconInitVersionBuild 0x10
SiliconInitVersionBuild.
#define | PcdGlobalDataPointerAddress 0xFED00148
GlobalDataPointerAddress.
#define | PcdTemporaryRamBase 0xFEF00000
TemporaryRamBase.
#define | PcdTemporaryRamSize 0x00100000
TemporaryRamSize.
#define | PcdFspReservedBufferSize 0x100
FspReservedBufferSize.

Detailed Description

This file lists all FixedAtBuild PCDs referenced in FSP integration guide.

Those value may vary in different FSP revision to meet different requirements.

Definition in file FspFixedPcds.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: FspFixedPcds.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • MeteorLakeFspBinPkg
  • DoxygenInternalOnly
FspFixedPcds.h
Go to the documentation of this file.
1 /** @file
2
3 This file lists all FixedAtBuild PCDs referenced in FSP integration guide.
4 Those value may vary in different FSP revision to meet different requirements.
5
6 **/
7
8 #ifndef __FSPFIXEDPCDS_H__
9 #define __FSPFIXEDPCDS_H__
10
11 #pragma pack(1)
12
13 #define PcdFspAreaBaseAddress 0xFFD00000 ///< FspAreaBaseAddress
14 #define PcdFspImageIdString $MTLFSP$ ///< FspImageIdString
15 #define PcdSiliconInitVersionMajor 0x0D ///< SiliconInitVersionMajor
16 #define PcdSiliconInitVersionMinor 0x00 ///< SiliconInitVersionMinor
17 #define PcdSiliconInitVersionRevision 0x05 ///< SiliconInitVersionRevision
18 #define PcdSiliconInitVersionBuild 0x10 ///< SiliconInitVersionBuild
19 #define PcdGlobalDataPointerAddress 0xFED00148 ///< GlobalDataPointerAddress
20 #define PcdTemporaryRamBase 0xFEF00000 ///< TemporaryRamBase
21 #define PcdTemporaryRamSize 0x00100000 ///< TemporaryRamSize
22 #define PcdFspReservedBufferSize 0x100 ///< FspReservedBufferSize
23 #pragma pack()
24
25 #endif
Generated on Mon Dec 29 2025 02:15:46 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: FspmArchConfigPpi.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Classes | Macros
FspmArchConfigPpi.h File Reference

Header file for FSP-M Arch Config PPI. More...

Go to the source code of this file.

Classes

struct FSPM_ARCH_CONFIG_PPI
This PPI provides FSP-M Arch Config PPI. More...

Macros

#define FSPM_ARCH_CONFIG_GUID
Global ID for the FSPM_ARCH_CONFIG_PPI.

Detailed Description

Header file for FSP-M Arch Config PPI.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file FspmArchConfigPpi.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: FspmArchConfigPpi.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
FspmArchConfigPpi.h
Go to the documentation of this file.
1 /** @file
2 Header file for FSP-M Arch Config PPI
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
7
8 This program and the accompanying materials are licensed and made available under
9 the terms and conditions of the BSD License which accompanies this distribution.
10 The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
12
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15
16 **/
17
18 #ifndef _FSPM_ARCH_CONFIG_PPI_H_
19 #define _FSPM_ARCH_CONFIG_PPI_H_
20
21 ///
22 /// Global ID for the FSPM_ARCH_CONFIG_PPI.
23 ///
24 #define FSPM_ARCH_CONFIG_GUID \
25 { \
26 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } \
27 }
28
29 ///
30 /// This PPI provides FSP-M Arch Config PPI.
31 ///
32 typedef struct {
33 UINT8 Revision;
34 UINT8 Reserved[3];
35 VOID *NvsBufferPtr;
36 UINT32 BootLoaderTolumSize;
37 UINT8 Reserved1[4];
38 } FSPM_ARCH_CONFIG_PPI;
39
40 extern EFI_GUID gFspmArchConfigPpiGuid;
41
42 #endif // _FSPM_ARCH_CONFIG_PPI_H_
VOID
#define VOID
Undeclared type.
Definition: Base.h:269
FSPM_ARCH_CONFIG_PPI
This PPI provides FSP-M Arch Config PPI.
Definition: FspmArchConfigPpi.h:32
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:46 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: GbeConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Gbe
Classes
GbeConfig.h File Reference

Gigabit Ethernet policy. More...

Go to the source code of this file.

Classes

struct GBE_CONFIG
PCH intergrated GBE controller configuration settings. More...

Detailed Description

Gigabit Ethernet policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GbeConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: GbeConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Gbe
GbeConfig.h
Go to the documentation of this file.
1 /** @file
2 Gigabit Ethernet policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _GBE_CONFIG_H_
36 #define _GBE_CONFIG_H_
37
38 #define GBE_CONFIG_REVISION 1
39 extern EFI_GUID gGbeConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 PCH intergrated GBE controller configuration settings.
45 **/
46 typedef struct {
47 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
48 /**
49 Determines if enable PCH internal GBE, 0: Disable; <b>1: Enable</b>.
50 When Enable is changed (from disabled to enabled or from enabled to disabled),
51 it needs to set LAN Disable regsiter, which might be locked by FDSWL register.
52 So it's recommendated to issue a global reset when changing the status for PCH Internal LAN.
53 **/
54 UINT32 Enable : 1;
55 UINT32 LtrEnable : 1; ///< <b>0: Disable</b>; 1: Enable LTR capabilty of PCH internal LAN.
56 /**
57 Deprecated.
58 Unused in MTL. Kept for compatibility.
59 Enables bit B_PCH_ACPI_GPE0_EN_127_96_PME_B0 during PchLanSxCallback in PchLanSxSmm.
60 **/
61 UINT32 PchWOLFastSupport : 1;
62 UINT32 RsvdBits0 : 29; ///< Reserved bits
63 } GBE_CONFIG;
64
65 #pragma pack (pop)
66
67 #endif // _GBE_CONFIG_H_
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
GBE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: GbeConfig.h:47
GBE_CONFIG::Enable
UINT32 Enable
Determines if enable PCH internal GBE, 0: Disable; 1: Enable.
Definition: GbeConfig.h:54
GBE_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: GbeConfig.h:62
GBE_CONFIG
PCH intergrated GBE controller configuration settings.
Definition: GbeConfig.h:46
GBE_CONFIG::PchWOLFastSupport
UINT32 PchWOLFastSupport
Deprecated.
Definition: GbeConfig.h:61
GBE_CONFIG::LtrEnable
UINT32 LtrEnable
0: Disable; 1: Enable LTR capabilty of PCH internal LAN.
Definition: GbeConfig.h:55
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:46 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: GnaConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Gna
Classes
GnaConfig.h File Reference

Policy definition for GNA Config Block. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct GNA_CONFIG
GNA config block for configuring GNA. More...

Detailed Description

Policy definition for GNA Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GnaConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: GnaConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Gna
GnaConfig.h
Go to the documentation of this file.
1 /** @file
2 Policy definition for GNA Config Block
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _GNA_CONFIG_H_
36 #define _GNA_CONFIG_H_
37 #pragma pack(push, 1)
38
39 #define GNA_CONFIG_REVISION 1
40 /**
41 GNA config block for configuring GNA.\n
42 <b>Revision 1</b>:
43 - Initial version.
44 **/
45 typedef struct {
46 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
47 /**
48 Offset 28:0
49 This policy enables the GNA Device (SA Device 8) if supported.
50 If FALSE, all other policies in this config block will be ignored.
51 <b>1=TRUE</b>;
52 0=FALSE.
53 **/
54 UINT32 GnaEnable : 1;
55 UINT32 RsvdBits0 : 31; ///< Offset 28:1 :Reserved for future use
56 } GNA_CONFIG;
57 #pragma pack(pop)
58
59 #endif // _GNA_CONFIG_H_
GNA_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: GnaConfig.h:46
GNA_CONFIG::RsvdBits0
UINT32 RsvdBits0
Offset 28:1 :Reserved for future use.
Definition: GnaConfig.h:55
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
GNA_CONFIG::GnaEnable
UINT32 GnaEnable
Offset 28:0 This policy enables the GNA Device (SA Device 8) if supported.
Definition: GnaConfig.h:54
GNA_CONFIG
GNA config block for configuring GNA.
Definition: GnaConfig.h:45
Generated on Mon Dec 29 2025 02:15:46 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: GpioConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • MeteorLakeFspBinPkg
  • Include
Classes | Macros | Typedefs | Enumerations
GpioConfig.h File Reference

Header file for GpioConfig structure used by GPIO library. More...

Go to the source code of this file.

Classes

struct GPIO_CONFIG
GPIO configuration structure used for pin programming. More...

Macros

#define | B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F
Mask for GPIO_INT_CONFIG for interrupt source.
#define | B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0
Mask for GPIO_INT_CONFIG for interrupt type.
#define | B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F
Mask for GPIO_ELECTRICAL_CONFIG for termination value.
#define | B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK 0x60
Mask for GPIO_ELECTRICAL_CONFIG for 1v8 tolerance setting.
#define | B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3
Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock.
#define | B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0x5
Mask for GPIO_LOCK_CONFIG for Pad Output Lock.
#define | B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3
Mask for GPIO_OTHER_CONFIG for RxRaw1 setting.

Typedefs

typedef UINT32 | GPIO_PAD
For any GpioPad usage in code use GPIO_PAD type.
typedef UINT32 | GPIO_GROUP
For any GpioGroup usage in code use GPIO_GROUP type.

Enumerations

enum | GPIO_HARDWARE_DEFAULT
enum | GPIO_PAD_MODE
GPIO Pad Mode Refer to GPIO documentation on native functions available for certain pad. More...
enum | GPIO_HOSTSW_OWN
Host Software Pad Ownership modes This setting affects GPIO interrupt status registers. More...
enum | GPIO_DIRECTION
GPIO Direction. More...
enum | GPIO_OUTPUT_STATE
GPIO Output State This field is relevant only if output is enabled. More...
enum | GPIO_INT_CONFIG
GPIO interrupt configuration This setting is applicable only if pad is in GPIO mode and has input enabled. More...
enum | GPIO_RESET_CONFIG
GPIO Power Configuration GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will be used to reset certain GPIO settings. More...
enum | GPIO_ELECTRICAL_CONFIG
GPIO Electrical Configuration Set GPIO termination and Pad Tolerance (applicable only for some pads) Field from GpioTermNone to GpioTermNative can be OR'ed with GpioTolerance1v8. More...
enum | GPIO_LOCK_CONFIG
GPIO LockConfiguration Set GPIO configuration lock and output state lock. More...
enum | GPIO_OTHER_CONFIG
Other GPIO Configuration GPIO_OTHER_CONFIG is used for less often settings and for future extensions Supported settings: More...

Detailed Description

Header file for GpioConfig structure used by GPIO library.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GpioConfig.h.

Enumeration Type Documentation

◆ GPIO_DIRECTION

enum GPIO_DIRECTION

GPIO Direction.

Enumerator
GpioDirDefault | Leave pad direction setting unmodified.
GpioDirInOut | Set pad for both output and input.
GpioDirInInvOut | Set pad for both output and input with inversion.
GpioDirIn | Set pad for input only.
GpioDirInInv | Set pad for input with inversion.
GpioDirOut | Set pad for output only.
GpioDirNone | Disable both output and input.

Definition at line 167 of file GpioConfig.h.

◆ GPIO_ELECTRICAL_CONFIG

enum GPIO_ELECTRICAL_CONFIG

GPIO Electrical Configuration Set GPIO termination and Pad Tolerance (applicable only for some pads) Field from GpioTermNone to GpioTermNative can be OR'ed with GpioTolerance1v8.

Enumerator
GpioTermDefault | Leave termination setting unmodified.
GpioTermNone | none
GpioTermWpd5K | 5kOhm weak pull-down
GpioTermWpd20K | 20kOhm weak pull-down
GpioTermWpu1K | 1kOhm weak pull-up
GpioTermWpu2K | 2kOhm weak pull-up
GpioTermWpu5K | 5kOhm weak pull-up
GpioTermWpu20K | 20kOhm weak pull-up
GpioTermWpu1K2K | 1kOhm & 2kOhm weak pull-up
GpioTermNative | Native function controls pads termination This setting is applicable only to some native modes. Please check EDS to determine which native functionality can control pads termination
GpioNoTolerance1v8 | Disable 1.8V pad tolerance.
GpioTolerance1v8 | Enable 1.8V pad tolerance.

Definition at line 289 of file GpioConfig.h.

◆ GPIO_HARDWARE_DEFAULT

enum GPIO_HARDWARE_DEFAULT
Enumerator
GpioHardwareDefault

Leave setting unmodified.

Definition at line 118 of file GpioConfig.h.

◆ GPIO_HOSTSW_OWN

enum GPIO_HOSTSW_OWN

Host Software Pad Ownership modes This setting affects GPIO interrupt status registers.

Depending on chosen ownership some GPIO Interrupt status register get updated and other masked. Please refer to EDS for HOSTSW_OWN register description.

Enumerator
GpioHostOwnDefault | Leave ownership value unmodified.
GpioHostOwnAcpi | Set HOST ownership to ACPI. Use this setting if pad is not going to be used by GPIO OS driver. If GPIO is configured to generate SCI/SMI/NMI then this setting must be used for interrupts to work
GpioHostOwnGpio | Set HOST ownership to GPIO Driver mode. Use this setting only if GPIO pad should be controlled by GPIO OS Driver. GPIO OS Driver will be able to control the pad if appropriate entry in ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)

Definition at line 146 of file GpioConfig.h.

◆ GPIO_INT_CONFIG

enum GPIO_INT_CONFIG

GPIO interrupt configuration This setting is applicable only if pad is in GPIO mode and has input enabled.

GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI) and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in EDS for details on this settings. Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge to describe an interrupt e.g. GpioIntApic | GpioIntLevel If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad. If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad. Not all GPIO are capable of generating an SMI or NMI interrupt. When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this interrupt cannot be shared and its IRQn number is not configurable. Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel) If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge). This type of GPIO Driver interrupt doesn't have any additional routing setting required to be set by BIOS. Interrupt is handled by GPIO OS Driver.

Enumerator
GpioIntDefault | Leave value of interrupt routing unmodified.
GpioIntDis | Disable IOxAPIC/SCI/SMI/NMI interrupt generation.
GpioIntNmi | Enable NMI interrupt only.
GpioIntSmi | Enable SMI interrupt only.
GpioIntSci | Enable SCI interrupt only.
GpioIntApic | Enable IOxAPIC interrupt only.
GpioIntLevel | Set interrupt as level triggered.
GpioIntEdge | Set interrupt as edge triggered (type of edge depends on input inversion)
GpioIntLvlEdgDis | Disable interrupt trigger.
GpioIntBothEdge | Set interrupt as both edge triggered.

Definition at line 207 of file GpioConfig.h.

◆ GPIO_LOCK_CONFIG

enum GPIO_LOCK_CONFIG

GPIO LockConfiguration Set GPIO configuration lock and output state lock.

GpioLockPadConfig and GpioLockOutputState can be OR'ed. Lock settings reset is in Powergood domain. Care must be taken when using this setting as fields it locks may be reset by a different signal and can be controllable by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides functions which allow to unlock a GPIO pad.

Enumerator
GpioLockDefault | Leave lock setting unmodified.
GpioPadConfigLock | Lock Pad Configuration.
GpioOutputStateLock | Lock GPIO pad output value.

Definition at line 322 of file GpioConfig.h.

◆ GPIO_OTHER_CONFIG

enum GPIO_OTHER_CONFIG

Other GPIO Configuration GPIO_OTHER_CONFIG is used for less often settings and for future extensions Supported settings:

  • RX raw override to '1' - allows to override input value to '1' This setting is applicable only if in input mode (both in GPIO and native usage). The override takes place at the internal pad state directly from buffer and before the RXINV.
Enumerator
GpioRxRaw1Default | Use default input override value.
GpioRxRaw1Dis | Don't override input.
GpioRxRaw1En | Override input to '1'.

Definition at line 339 of file GpioConfig.h.

◆ GPIO_OUTPUT_STATE

enum GPIO_OUTPUT_STATE

GPIO Output State This field is relevant only if output is enabled.

Enumerator
GpioOutDefault | Leave output value unmodified.
GpioOutLow | Set output to low.
GpioOutHigh | Set output to high.

Definition at line 181 of file GpioConfig.h.

◆ GPIO_PAD_MODE

enum GPIO_PAD_MODE

GPIO Pad Mode Refer to GPIO documentation on native functions available for certain pad.

If GPIO is set to one of NativeX modes then following settings are not applicable and can be skipped:

  • Interrupt related settings
  • Host Software Ownership
  • Output/Input enabling/disabling
  • Output lock

Definition at line 132 of file GpioConfig.h.

◆ GPIO_RESET_CONFIG

enum GPIO_RESET_CONFIG

GPIO Power Configuration GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will be used to reset certain GPIO settings.

Refer to EDS for settings that are controllable by PadRstCfg.

Enumerator
GpioResetDefault

Leave value of pad reset unmodified.

GpioResumeReset

New GPIO reset configuration options.

Resume Reset (RSMRST) GPP: PadRstCfg = 00b = "Powergood" GPD: PadRstCfg = 11b = "Resume Reset" Pad setting will reset on:

  • DeepSx transition
  • G3 Pad settings will not reset on:
  • S3/S4/S5 transition
  • Warm/Cold/Global reset
GpioHostDeepReset

Host Deep Reset PadRstCfg = 01b = "Deep GPIO Reset" Pad settings will reset on:

  • Warm/Cold/Global reset
  • DeepSx transition
  • G3 Pad settings will not reset on:
  • S3/S4/S5 transition
GpioPlatformReset

Platform Reset (PLTRST) PadRstCfg = 10b = "GPIO Reset" Pad settings will reset on:

  • S3/S4/S5 transition
  • Warm/Cold/Global reset
  • DeepSx transition
  • G3
GpioDswReset

Deep Sleep Well Reset (DSW_PWROK) GPP: not applicable GPD: PadRstCfg = 00b = "Powergood" Pad settings will reset on:

  • G3 Pad settings will not reset on:
  • S3/S4/S5 transition
  • Warm/Cold/Global reset
  • DeepSx transition

Definition at line 229 of file GpioConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: GpioConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • MeteorLakeFspBinPkg
  • Include
GpioConfig.h
Go to the documentation of this file.
1 /** @file
2 Header file for GpioConfig structure used by GPIO library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _GPIO_CONFIG_H_
36 #define _GPIO_CONFIG_H_
37
38 #pragma pack(push, 1)
39
40 ///
41 /// For any GpioPad usage in code use GPIO_PAD type
42 ///
43 typedef UINT32 GPIO_PAD;
44
45
46 ///
47 /// For any GpioGroup usage in code use GPIO_GROUP type
48 ///
49 typedef UINT32 GPIO_GROUP;
50
51 /**
52 GPIO configuration structure used for pin programming.
53 Structure contains fields that can be used to configure pad.
54 **/
55 typedef struct {
56 /**
57 Pad Mode
58 Pad can be set as GPIO or one of its native functions.
59 When in native mode setting Direction (except Inversion), OutputState,
60 InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary.
61 Refer to definition of GPIO_PAD_MODE.
62 Refer to EDS for each native mode according to the pad.
63 **/
64 UINT32 PadMode : 5;
65 /**
66 Host Software Pad Ownership
67 Set pad to ACPI mode or GPIO Driver Mode.
68 Refer to definition of GPIO_HOSTSW_OWN.
69 **/
70 UINT32 HostSoftPadOwn : 2;
71 /**
72 GPIO Direction
73 Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.
74 Refer to definition of GPIO_DIRECTION for supported settings.
75 **/
76 UINT32 Direction : 6;
77 /**
78 Output State
79 Set Pad output value.
80 Refer to definition of GPIO_OUTPUT_STATE for supported settings.
81 This setting takes place when output is enabled.
82 **/
83 UINT32 OutputState : 2;
84 /**
85 GPIO Interrupt Configuration
86 Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
87 This setting is applicable only if GPIO is in GpioMode with input enabled.
88 Refer to definition of GPIO_INT_CONFIG for supported settings.
89 **/
90 UINT32 InterruptConfig : 9;
91 /**
92 GPIO Power Configuration.
93 This setting controls Pad Reset Configuration.
94 Refer to definition of GPIO_RESET_CONFIG for supported settings.
95 **/
96 UINT32 PowerConfig : 8;
97 /**
98 GPIO Electrical Configuration
99 This setting controls pads termination and voltage tolerance.
100 Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
101 **/
102 UINT32 ElectricalConfig : 9;
103 /**
104 GPIO Lock Configuration
105 This setting controls pads lock.
106 Refer to definition of GPIO_LOCK_CONFIG for supported settings.
107 **/
108 UINT32 LockConfig : 4;
109 /**
110 Additional GPIO configuration
111 Refer to definition of GPIO_OTHER_CONFIG for supported settings.
112 **/
113 UINT32 OtherSettings : 2;
114 UINT32 RsvdBits : 17; ///< Reserved bits for future extension
115 } GPIO_CONFIG;
116
117
118 typedef enum {
119 GpioHardwareDefault = 0x0 ///< Leave setting unmodified
120 } GPIO_HARDWARE_DEFAULT;
121
122 /**
123 GPIO Pad Mode
124 Refer to GPIO documentation on native functions available for certain pad.
125 If GPIO is set to one of NativeX modes then following settings are not applicable
126 and can be skipped:
127 - Interrupt related settings
128 - Host Software Ownership
129 - Output/Input enabling/disabling
130 - Output lock
131 **/
132 typedef enum {
133 GpioPadModeGpio = 0x1,
134 GpioPadModeNative1 = 0x3,
135 GpioPadModeNative2 = 0x5,
136 GpioPadModeNative3 = 0x7,
137 GpioPadModeNative4 = 0x9
138 } GPIO_PAD_MODE;
139
140 /**
141 Host Software Pad Ownership modes
142 This setting affects GPIO interrupt status registers. Depending on chosen ownership
143 some GPIO Interrupt status register get updated and other masked.
144 Please refer to EDS for HOSTSW_OWN register description.
145 **/
146 typedef enum {
147 GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified
148 /**
149 Set HOST ownership to ACPI.
150 Use this setting if pad is not going to be used by GPIO OS driver.
151 If GPIO is configured to generate SCI/SMI/NMI then this setting must be
152 used for interrupts to work
153 **/
154 GpioHostOwnAcpi = 0x1,
155 /**
156 Set HOST ownership to GPIO Driver mode.
157 Use this setting only if GPIO pad should be controlled by GPIO OS Driver.
158 GPIO OS Driver will be able to control the pad if appropriate entry in
159 ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)
160 **/
161 GpioHostOwnGpio = 0x3
162 } GPIO_HOSTSW_OWN;
163
164 ///
165 /// GPIO Direction
166 ///
167 typedef enum {
168 GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified
169 GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input
170 GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion
171 GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only
172 GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
173 GpioDirOut = 0x5, ///< Set pad for output only
174 GpioDirNone = 0x7 ///< Disable both output and input
175 } GPIO_DIRECTION;
176
177 /**
178 GPIO Output State
179 This field is relevant only if output is enabled
180 **/
181 typedef enum {
182 GpioOutDefault = 0x0, ///< Leave output value unmodified
183 GpioOutLow = 0x1, ///< Set output to low
184 GpioOutHigh = 0x3 ///< Set output to high
185 } GPIO_OUTPUT_STATE;
186
187 /**
188 GPIO interrupt configuration
189 This setting is applicable only if pad is in GPIO mode and has input enabled.
190 GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI)
191 and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in
192 EDS for details on this settings.
193 Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge
194 to describe an interrupt e.g. GpioIntApic | GpioIntLevel
195 If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad.
196 If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad.
197 Not all GPIO are capable of generating an SMI or NMI interrupt.
198 When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this
199 interrupt cannot be shared and its IRQn number is not configurable.
200 Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel)
201 If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor
202 exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge).
203 This type of GPIO Driver interrupt doesn't have any additional routing setting
204 required to be set by BIOS. Interrupt is handled by GPIO OS Driver.
205 **/
206
207 typedef enum {
208 GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified
209 GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
210 GpioIntNmi = 0x3, ///< Enable NMI interrupt only
211 GpioIntSmi = 0x5, ///< Enable SMI interrupt only
212 GpioIntSci = 0x9, ///< Enable SCI interrupt only
213 GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only
214 GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered
215 GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion)
216 GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger
217 GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered
218 } GPIO_INT_CONFIG;
219
220 #define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source
221 #define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type
222
223 /**
224 GPIO Power Configuration
225 GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will
226 be used to reset certain GPIO settings.
227 Refer to EDS for settings that are controllable by PadRstCfg.
228 **/
229 typedef enum {
230
231
232 GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified
233
234 ///
235 /// New GPIO reset configuration options
236 ///
237 /**
238 Resume Reset (RSMRST)
239 GPP: PadRstCfg = 00b = "Powergood"
240 GPD: PadRstCfg = 11b = "Resume Reset"
241 Pad setting will reset on:
242 - DeepSx transition
243 - G3
244 Pad settings will not reset on:
245 - S3/S4/S5 transition
246 - Warm/Cold/Global reset
247 **/
248 GpioResumeReset = 0x01,
249 /**
250 Host Deep Reset
251 PadRstCfg = 01b = "Deep GPIO Reset"
252 Pad settings will reset on:
253 - Warm/Cold/Global reset
254 - DeepSx transition
255 - G3
256 Pad settings will not reset on:
257 - S3/S4/S5 transition
258 **/
259 GpioHostDeepReset = 0x03,
260 /**
261 Platform Reset (PLTRST)
262 PadRstCfg = 10b = "GPIO Reset"
263 Pad settings will reset on:
264 - S3/S4/S5 transition
265 - Warm/Cold/Global reset
266 - DeepSx transition
267 - G3
268 **/
269 GpioPlatformReset = 0x05,
270 /**
271 Deep Sleep Well Reset (DSW_PWROK)
272 GPP: not applicable
273 GPD: PadRstCfg = 00b = "Powergood"
274 Pad settings will reset on:
275 - G3
276 Pad settings will not reset on:
277 - S3/S4/S5 transition
278 - Warm/Cold/Global reset
279 - DeepSx transition
280 **/
281 GpioDswReset = 0x07
282 } GPIO_RESET_CONFIG;
283
284 /**
285 GPIO Electrical Configuration
286 Set GPIO termination and Pad Tolerance (applicable only for some pads)
287 Field from GpioTermNone to GpioTermNative can be OR'ed with GpioTolerance1v8.
288 **/
289 typedef enum {
290 GpioTermDefault = 0x0, ///< Leave termination setting unmodified
291 GpioTermNone = 0x1, ///< none
292 GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down
293 GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down
294 GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up
295 GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up
296 GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up
297 GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up
298 GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
299 /**
300 Native function controls pads termination
301 This setting is applicable only to some native modes.
302 Please check EDS to determine which native functionality
303 can control pads termination
304 **/
305 GpioTermNative = 0x1F,
306 GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance
307 GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance
308 } GPIO_ELECTRICAL_CONFIG;
309
310 #define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value
311 #define B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK 0x60 ///< Mask for GPIO_ELECTRICAL_CONFIG for 1v8 tolerance setting
312
313 /**
314 GPIO LockConfiguration
315 Set GPIO configuration lock and output state lock.
316 GpioLockPadConfig and GpioLockOutputState can be OR'ed.
317 Lock settings reset is in Powergood domain. Care must be taken when using this setting
318 as fields it locks may be reset by a different signal and can be controllable
319 by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides
320 functions which allow to unlock a GPIO pad.
321 **/
322 typedef enum {
323 GpioLockDefault = 0x0, ///< Leave lock setting unmodified
324 GpioPadConfigLock = 0x3, ///< Lock Pad Configuration
325 GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value
326 } GPIO_LOCK_CONFIG;
327
328 #define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock
329 #define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0x5 ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock
330
331 /**
332 Other GPIO Configuration
333 GPIO_OTHER_CONFIG is used for less often settings and for future extensions
334 Supported settings:
335 - RX raw override to '1' - allows to override input value to '1'
336 This setting is applicable only if in input mode (both in GPIO and native usage).
337 The override takes place at the internal pad state directly from buffer and before the RXINV.
338 **/
339 typedef enum {
340 GpioRxRaw1Default = 0x0, ///< Use default input override value
341 GpioRxRaw1Dis = 0x1, ///< Don't override input
342 GpioRxRaw1En = 0x3 ///< Override input to '1'
343 } GPIO_OTHER_CONFIG;
344
345 #define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting
346
347 #pragma pack(pop)
348
349 #endif //_GPIO_CONFIG_H_
GpioTermWpu5K
@ GpioTermWpu5K
5kOhm weak pull-up
Definition: GpioConfig.h:296
GpioOutDefault
@ GpioOutDefault
Leave output value unmodified.
Definition: GpioConfig.h:182
GPIO_RESET_CONFIG
GPIO_RESET_CONFIG
GPIO Power Configuration GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0....
Definition: GpioConfig.h:229
GpioRxRaw1Default
@ GpioRxRaw1Default
Use default input override value.
Definition: GpioConfig.h:340
GpioDirInInv
@ GpioDirInInv
Set pad for input with inversion.
Definition: GpioConfig.h:172
GpioOutLow
@ GpioOutLow
Set output to low.
Definition: GpioConfig.h:183
GPIO_CONFIG::Direction
UINT32 Direction
GPIO Direction Can choose between In, In with inversion, Out, both In and Out, both In with inversion...
Definition: GpioConfig.h:76
GPIO_CONFIG::PadMode
UINT32 PadMode
Pad Mode Pad can be set as GPIO or one of its native functions.
Definition: GpioConfig.h:64
GPIO_CONFIG::OutputState
UINT32 OutputState
Output State Set Pad output value.
Definition: GpioConfig.h:83
GpioTermWpu1K
@ GpioTermWpu1K
1kOhm weak pull-up
Definition: GpioConfig.h:294
GPIO_CONFIG::PowerConfig
UINT32 PowerConfig
GPIO Power Configuration.
Definition: GpioConfig.h:96
GpioNoTolerance1v8
@ GpioNoTolerance1v8
Disable 1.8V pad tolerance.
Definition: GpioConfig.h:306
GPIO_CONFIG::LockConfig
UINT32 LockConfig
GPIO Lock Configuration This setting controls pads lock.
Definition: GpioConfig.h:108
GpioDirOut
@ GpioDirOut
Set pad for output only.
Definition: GpioConfig.h:173
GpioIntEdge
@ GpioIntEdge
Set interrupt as edge triggered (type of edge depends on input inversion)
Definition: GpioConfig.h:215
GpioTermWpu2K
@ GpioTermWpu2K
2kOhm weak pull-up
Definition: GpioConfig.h:295
GpioTermNative
@ GpioTermNative
Native function controls pads termination This setting is applicable only to some native modes.
Definition: GpioConfig.h:305
GpioDirDefault
@ GpioDirDefault
Leave pad direction setting unmodified.
Definition: GpioConfig.h:168
GpioTermWpu20K
@ GpioTermWpu20K
20kOhm weak pull-up
Definition: GpioConfig.h:297
GpioTermWpd20K
@ GpioTermWpd20K
20kOhm weak pull-down
Definition: GpioConfig.h:293
GpioDirIn
@ GpioDirIn
Set pad for input only.
Definition: GpioConfig.h:171
GpioRxRaw1En
@ GpioRxRaw1En
Override input to '1'.
Definition: GpioConfig.h:342
GpioRxRaw1Dis
@ GpioRxRaw1Dis
Don't override input.
Definition: GpioConfig.h:341
GpioOutputStateLock
@ GpioOutputStateLock
Lock GPIO pad output value.
Definition: GpioConfig.h:325
GPIO_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved bits for future extension.
Definition: GpioConfig.h:114
GpioTermNone
@ GpioTermNone
none
Definition: GpioConfig.h:291
GPIO_PAD
UINT32 GPIO_PAD
For any GpioPad usage in code use GPIO_PAD type.
Definition: GpioConfig.h:43
GPIO_OTHER_CONFIG
GPIO_OTHER_CONFIG
Other GPIO Configuration GPIO_OTHER_CONFIG is used for less often settings and for future extensions ...
Definition: GpioConfig.h:339
GPIO_HARDWARE_DEFAULT
GPIO_HARDWARE_DEFAULT
Definition: GpioConfig.h:118
GpioIntApic
@ GpioIntApic
Enable IOxAPIC interrupt only.
Definition: GpioConfig.h:213
GPIO_DIRECTION
GPIO_DIRECTION
GPIO Direction.
Definition: GpioConfig.h:167
GpioTermWpu1K2K
@ GpioTermWpu1K2K
1kOhm & 2kOhm weak pull-up
Definition: GpioConfig.h:298
GPIO_CONFIG::ElectricalConfig
UINT32 ElectricalConfig
GPIO Electrical Configuration This setting controls pads termination and voltage tolerance.
Definition: GpioConfig.h:102
GpioTermWpd5K
@ GpioTermWpd5K
5kOhm weak pull-down
Definition: GpioConfig.h:292
GpioIntDefault
@ GpioIntDefault
Leave value of interrupt routing unmodified.
Definition: GpioConfig.h:208
GPIO_CONFIG::InterruptConfig
UINT32 InterruptConfig
GPIO Interrupt Configuration Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
Definition: GpioConfig.h:90
GpioIntLevel
@ GpioIntLevel
Set interrupt as level triggered.
Definition: GpioConfig.h:214
GpioLockDefault
@ GpioLockDefault
Leave lock setting unmodified.
Definition: GpioConfig.h:323
GpioTermDefault
@ GpioTermDefault
Leave termination setting unmodified.
Definition: GpioConfig.h:290
GpioResumeReset
@ GpioResumeReset
New GPIO reset configuration options.
Definition: GpioConfig.h:248
GpioDswReset
@ GpioDswReset
Deep Sleep Well Reset (DSW_PWROK) GPP: not applicable GPD: PadRstCfg = 00b = "Powergood" Pad settings...
Definition: GpioConfig.h:281
GpioIntSmi
@ GpioIntSmi
Enable SMI interrupt only.
Definition: GpioConfig.h:211
GPIO_LOCK_CONFIG
GPIO_LOCK_CONFIG
GPIO LockConfiguration Set GPIO configuration lock and output state lock.
Definition: GpioConfig.h:322
GpioIntDis
@ GpioIntDis
Disable IOxAPIC/SCI/SMI/NMI interrupt generation.
Definition: GpioConfig.h:209
GPIO_PAD_MODE
GPIO_PAD_MODE
GPIO Pad Mode Refer to GPIO documentation on native functions available for certain pad.
Definition: GpioConfig.h:132
GpioHostDeepReset
@ GpioHostDeepReset
Host Deep Reset PadRstCfg = 01b = "Deep GPIO Reset" Pad settings will reset on:
Definition: GpioConfig.h:259
GPIO_CONFIG::OtherSettings
UINT32 OtherSettings
Additional GPIO configuration Refer to definition of GPIO_OTHER_CONFIG for supported settings.
Definition: GpioConfig.h:113
GpioResetDefault
@ GpioResetDefault
Leave value of pad reset unmodified.
Definition: GpioConfig.h:232
GpioIntNmi
@ GpioIntNmi
Enable NMI interrupt only.
Definition: GpioConfig.h:210
GpioIntSci
@ GpioIntSci
Enable SCI interrupt only.
Definition: GpioConfig.h:212
GpioHostOwnDefault
@ GpioHostOwnDefault
Leave ownership value unmodified.
Definition: GpioConfig.h:147
GpioDirInOut
@ GpioDirInOut
Set pad for both output and input.
Definition: GpioConfig.h:169
GpioHardwareDefault
@ GpioHardwareDefault
Leave setting unmodified.
Definition: GpioConfig.h:119
GPIO_HOSTSW_OWN
GPIO_HOSTSW_OWN
Host Software Pad Ownership modes This setting affects GPIO interrupt status registers.
Definition: GpioConfig.h:146
GPIO_INT_CONFIG
GPIO_INT_CONFIG
GPIO interrupt configuration This setting is applicable only if pad is in GPIO mode and has input ena...
Definition: GpioConfig.h:207
GpioPlatformReset
@ GpioPlatformReset
Platform Reset (PLTRST) PadRstCfg = 10b = "GPIO Reset" Pad settings will reset on:
Definition: GpioConfig.h:269
GpioTolerance1v8
@ GpioTolerance1v8
Enable 1.8V pad tolerance.
Definition: GpioConfig.h:307
GPIO_OUTPUT_STATE
GPIO_OUTPUT_STATE
GPIO Output State This field is relevant only if output is enabled.
Definition: GpioConfig.h:181
GpioPadConfigLock
@ GpioPadConfigLock
Lock Pad Configuration.
Definition: GpioConfig.h:324
GPIO_ELECTRICAL_CONFIG
GPIO_ELECTRICAL_CONFIG
GPIO Electrical Configuration Set GPIO termination and Pad Tolerance (applicable only for some pads) ...
Definition: GpioConfig.h:289
GpioOutHigh
@ GpioOutHigh
Set output to high.
Definition: GpioConfig.h:184
GpioIntBothEdge
@ GpioIntBothEdge
Set interrupt as both edge triggered.
Definition: GpioConfig.h:217
GpioHostOwnGpio
@ GpioHostOwnGpio
Set HOST ownership to GPIO Driver mode.
Definition: GpioConfig.h:161
GPIO_GROUP
UINT32 GPIO_GROUP
For any GpioGroup usage in code use GPIO_GROUP type.
Definition: GpioConfig.h:49
GPIO_CONFIG::HostSoftPadOwn
UINT32 HostSoftPadOwn
Host Software Pad Ownership Set pad to ACPI mode or GPIO Driver Mode.
Definition: GpioConfig.h:70
GpioDirInInvOut
@ GpioDirInInvOut
Set pad for both output and input with inversion.
Definition: GpioConfig.h:170
GPIO_CONFIG
GPIO configuration structure used for pin programming.
Definition: GpioConfig.h:55
GpioDirNone
@ GpioDirNone
Disable both output and input.
Definition: GpioConfig.h:174
GpioHostOwnAcpi
@ GpioHostOwnAcpi
Set HOST ownership to ACPI.
Definition: GpioConfig.h:154
GpioIntLvlEdgDis
@ GpioIntLvlEdgDis
Disable interrupt trigger.
Definition: GpioConfig.h:216
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: GpioSampleDef.h File Reference

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GpioSampleDef.h File Reference

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#include <FsptUpd.h>
#include <FspmUpd.h>
#include <FspsUpd.h>
Include dependency graph for GpioSampleDef.h:

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Detailed Description

Copyright (c) 2015 - 2017, Intel Corporation.

All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

This file is automatically generated. Please do NOT modify !!!

Definition in file GpioSampleDef.h.

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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: GpioSampleDef.h Source File

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GpioSampleDef.h
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1 /** @file
2
3 Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
4
5 Redistribution and use in source and binary forms, with or without modification,
6 are permitted provided that the following conditions are met:
7
8 * Redistributions of source code must retain the above copyright notice, this
9 list of conditions and the following disclaimer.
10 * Redistributions in binary form must reproduce the above copyright notice, this
11 list of conditions and the following disclaimer in the documentation and/or
12 other materials provided with the distribution.
13 * Neither the name of Intel Corporation nor the names of its contributors may
14 be used to endorse or promote products derived from this software without
15 specific prior written permission.
16
17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 THE POSSIBILITY OF SUCH DAMAGE.
28
29 This file is automatically generated. Please do NOT modify !!!
30
31 **/
32
33 #ifndef __GPIOCONFIG_H__
34 #define __GPIOCONFIG_H__
35 #include <FsptUpd.h>
36 #include <FspmUpd.h>
37 #include <FspsUpd.h>
38
39 /*
40 SKL LP GPIO pins
41 Use below for functions from PCH GPIO Lib which
42 require GpioPad as argument. Encoding used here
43 has all information required by library functions
44 */
45 #define GPIO_SKL_LP_GPP_A0 0x02000000
46 #define GPIO_SKL_LP_GPP_A1 0x02000001
47 #define GPIO_SKL_LP_GPP_A2 0x02000002
48 #define GPIO_SKL_LP_GPP_A3 0x02000003
49 #define GPIO_SKL_LP_GPP_A4 0x02000004
50 #define GPIO_SKL_LP_GPP_A5 0x02000005
51 #define GPIO_SKL_LP_GPP_A6 0x02000006
52 #define GPIO_SKL_LP_GPP_A7 0x02000007
53 #define GPIO_SKL_LP_GPP_A8 0x02000008
54 #define GPIO_SKL_LP_GPP_A9 0x02000009
55 #define GPIO_SKL_LP_GPP_A10 0x0200000A
56 #define GPIO_SKL_LP_GPP_A11 0x0200000B
57 #define GPIO_SKL_LP_GPP_A12 0x0200000C
58 #define GPIO_SKL_LP_GPP_A13 0x0200000D
59 #define GPIO_SKL_LP_GPP_A14 0x0200000E
60 #define GPIO_SKL_LP_GPP_A15 0x0200000F
61 #define GPIO_SKL_LP_GPP_A16 0x02000010
62 #define GPIO_SKL_LP_GPP_A17 0x02000011
63 #define GPIO_SKL_LP_GPP_A18 0x02000012
64 #define GPIO_SKL_LP_GPP_A19 0x02000013
65 #define GPIO_SKL_LP_GPP_A20 0x02000014
66 #define GPIO_SKL_LP_GPP_A21 0x02000015
67 #define GPIO_SKL_LP_GPP_A22 0x02000016
68 #define GPIO_SKL_LP_GPP_A23 0x02000017
69 #define GPIO_SKL_LP_GPP_B0 0x02010000
70 #define GPIO_SKL_LP_GPP_B1 0x02010001
71 #define GPIO_SKL_LP_GPP_B2 0x02010002
72 #define GPIO_SKL_LP_GPP_B3 0x02010003
73 #define GPIO_SKL_LP_GPP_B4 0x02010004
74 #define GPIO_SKL_LP_GPP_B5 0x02010005
75 #define GPIO_SKL_LP_GPP_B6 0x02010006
76 #define GPIO_SKL_LP_GPP_B7 0x02010007
77 #define GPIO_SKL_LP_GPP_B8 0x02010008
78 #define GPIO_SKL_LP_GPP_B9 0x02010009
79 #define GPIO_SKL_LP_GPP_B10 0x0201000A
80 #define GPIO_SKL_LP_GPP_B11 0x0201000B
81 #define GPIO_SKL_LP_GPP_B12 0x0201000C
82 #define GPIO_SKL_LP_GPP_B13 0x0201000D
83 #define GPIO_SKL_LP_GPP_B14 0x0201000E
84 #define GPIO_SKL_LP_GPP_B15 0x0201000F
85 #define GPIO_SKL_LP_GPP_B16 0x02010010
86 #define GPIO_SKL_LP_GPP_B17 0x02010011
87 #define GPIO_SKL_LP_GPP_B18 0x02010012
88 #define GPIO_SKL_LP_GPP_B19 0x02010013
89 #define GPIO_SKL_LP_GPP_B20 0x02010014
90 #define GPIO_SKL_LP_GPP_B21 0x02010015
91 #define GPIO_SKL_LP_GPP_B22 0x02010016
92 #define GPIO_SKL_LP_GPP_B23 0x02010017
93 #define GPIO_SKL_LP_GPP_C0 0x02020000
94 #define GPIO_SKL_LP_GPP_C1 0x02020001
95 #define GPIO_SKL_LP_GPP_C2 0x02020002
96 #define GPIO_SKL_LP_GPP_C3 0x02020003
97 #define GPIO_SKL_LP_GPP_C4 0x02020004
98 #define GPIO_SKL_LP_GPP_C5 0x02020005
99 #define GPIO_SKL_LP_GPP_C6 0x02020006
100 #define GPIO_SKL_LP_GPP_C7 0x02020007
101 #define GPIO_SKL_LP_GPP_C8 0x02020008
102 #define GPIO_SKL_LP_GPP_C9 0x02020009
103 #define GPIO_SKL_LP_GPP_C10 0x0202000A
104 #define GPIO_SKL_LP_GPP_C11 0x0202000B
105 #define GPIO_SKL_LP_GPP_C12 0x0202000C
106 #define GPIO_SKL_LP_GPP_C13 0x0202000D
107 #define GPIO_SKL_LP_GPP_C14 0x0202000E
108 #define GPIO_SKL_LP_GPP_C15 0x0202000F
109 #define GPIO_SKL_LP_GPP_C16 0x02020010
110 #define GPIO_SKL_LP_GPP_C17 0x02020011
111 #define GPIO_SKL_LP_GPP_C18 0x02020012
112 #define GPIO_SKL_LP_GPP_C19 0x02020013
113 #define GPIO_SKL_LP_GPP_C20 0x02020014
114 #define GPIO_SKL_LP_GPP_C21 0x02020015
115 #define GPIO_SKL_LP_GPP_C22 0x02020016
116 #define GPIO_SKL_LP_GPP_C23 0x02020017
117 #define GPIO_SKL_LP_GPP_D0 0x02030000
118 #define GPIO_SKL_LP_GPP_D1 0x02030001
119 #define GPIO_SKL_LP_GPP_D2 0x02030002
120 #define GPIO_SKL_LP_GPP_D3 0x02030003
121 #define GPIO_SKL_LP_GPP_D4 0x02030004
122 #define GPIO_SKL_LP_GPP_D5 0x02030005
123 #define GPIO_SKL_LP_GPP_D6 0x02030006
124 #define GPIO_SKL_LP_GPP_D7 0x02030007
125 #define GPIO_SKL_LP_GPP_D8 0x02030008
126 #define GPIO_SKL_LP_GPP_D9 0x02030009
127 #define GPIO_SKL_LP_GPP_D10 0x0203000A
128 #define GPIO_SKL_LP_GPP_D11 0x0203000B
129 #define GPIO_SKL_LP_GPP_D12 0x0203000C
130 #define GPIO_SKL_LP_GPP_D13 0x0203000D
131 #define GPIO_SKL_LP_GPP_D14 0x0203000E
132 #define GPIO_SKL_LP_GPP_D15 0x0203000F
133 #define GPIO_SKL_LP_GPP_D16 0x02030010
134 #define GPIO_SKL_LP_GPP_D17 0x02030011
135 #define GPIO_SKL_LP_GPP_D18 0x02030012
136 #define GPIO_SKL_LP_GPP_D19 0x02030013
137 #define GPIO_SKL_LP_GPP_D20 0x02030014
138 #define GPIO_SKL_LP_GPP_D21 0x02030015
139 #define GPIO_SKL_LP_GPP_D22 0x02030016
140 #define GPIO_SKL_LP_GPP_D23 0x02030017
141 #define GPIO_SKL_LP_GPP_E0 0x02040000
142 #define GPIO_SKL_LP_GPP_E1 0x02040001
143 #define GPIO_SKL_LP_GPP_E2 0x02040002
144 #define GPIO_SKL_LP_GPP_E3 0x02040003
145 #define GPIO_SKL_LP_GPP_E4 0x02040004
146 #define GPIO_SKL_LP_GPP_E5 0x02040005
147 #define GPIO_SKL_LP_GPP_E6 0x02040006
148 #define GPIO_SKL_LP_GPP_E7 0x02040007
149 #define GPIO_SKL_LP_GPP_E8 0x02040008
150 #define GPIO_SKL_LP_GPP_E9 0x02040009
151 #define GPIO_SKL_LP_GPP_E10 0x0204000A
152 #define GPIO_SKL_LP_GPP_E11 0x0204000B
153 #define GPIO_SKL_LP_GPP_E12 0x0204000C
154 #define GPIO_SKL_LP_GPP_E13 0x0204000D
155 #define GPIO_SKL_LP_GPP_E14 0x0204000E
156 #define GPIO_SKL_LP_GPP_E15 0x0204000F
157 #define GPIO_SKL_LP_GPP_E16 0x02040010
158 #define GPIO_SKL_LP_GPP_E17 0x02040011
159 #define GPIO_SKL_LP_GPP_E18 0x02040012
160 #define GPIO_SKL_LP_GPP_E19 0x02040013
161 #define GPIO_SKL_LP_GPP_E20 0x02040014
162 #define GPIO_SKL_LP_GPP_E21 0x02040015
163 #define GPIO_SKL_LP_GPP_E22 0x02040016
164 #define GPIO_SKL_LP_GPP_E23 0x02040017
165 #define GPIO_SKL_LP_GPP_F0 0x02050000
166 #define GPIO_SKL_LP_GPP_F1 0x02050001
167 #define GPIO_SKL_LP_GPP_F2 0x02050002
168 #define GPIO_SKL_LP_GPP_F3 0x02050003
169 #define GPIO_SKL_LP_GPP_F4 0x02050004
170 #define GPIO_SKL_LP_GPP_F5 0x02050005
171 #define GPIO_SKL_LP_GPP_F6 0x02050006
172 #define GPIO_SKL_LP_GPP_F7 0x02050007
173 #define GPIO_SKL_LP_GPP_F8 0x02050008
174 #define GPIO_SKL_LP_GPP_F9 0x02050009
175 #define GPIO_SKL_LP_GPP_F10 0x0205000A
176 #define GPIO_SKL_LP_GPP_F11 0x0205000B
177 #define GPIO_SKL_LP_GPP_F12 0x0205000C
178 #define GPIO_SKL_LP_GPP_F13 0x0205000D
179 #define GPIO_SKL_LP_GPP_F14 0x0205000E
180 #define GPIO_SKL_LP_GPP_F15 0x0205000F
181 #define GPIO_SKL_LP_GPP_F16 0x02050010
182 #define GPIO_SKL_LP_GPP_F17 0x02050011
183 #define GPIO_SKL_LP_GPP_F18 0x02050012
184 #define GPIO_SKL_LP_GPP_F19 0x02050013
185 #define GPIO_SKL_LP_GPP_F20 0x02050014
186 #define GPIO_SKL_LP_GPP_F21 0x02050015
187 #define GPIO_SKL_LP_GPP_F22 0x02050016
188 #define GPIO_SKL_LP_GPP_F23 0x02050017
189 #define GPIO_SKL_LP_GPP_G0 0x02060000
190 #define GPIO_SKL_LP_GPP_G1 0x02060001
191 #define GPIO_SKL_LP_GPP_G2 0x02060002
192 #define GPIO_SKL_LP_GPP_G3 0x02060003
193 #define GPIO_SKL_LP_GPP_G4 0x02060004
194 #define GPIO_SKL_LP_GPP_G5 0x02060005
195 #define GPIO_SKL_LP_GPP_G6 0x02060006
196 #define GPIO_SKL_LP_GPP_G7 0x02060007
197 #define GPIO_SKL_LP_GPD0 0x02070000
198 #define GPIO_SKL_LP_GPD1 0x02070001
199 #define GPIO_SKL_LP_GPD2 0x02070002
200 #define GPIO_SKL_LP_GPD3 0x02070003
201 #define GPIO_SKL_LP_GPD4 0x02070004
202 #define GPIO_SKL_LP_GPD5 0x02070005
203 #define GPIO_SKL_LP_GPD6 0x02070006
204 #define GPIO_SKL_LP_GPD7 0x02070007
205 #define GPIO_SKL_LP_GPD8 0x02070008
206 #define GPIO_SKL_LP_GPD9 0x02070009
207 #define GPIO_SKL_LP_GPD10 0x0207000A
208 #define GPIO_SKL_LP_GPD11 0x0207000B
209
210 #define END_OF_GPIO_TABLE 0xFFFFFFFF
211
212 //Sample GPIO Table
213
214 static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] =
215 {
216 //skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//H_RCIN_N
217 //skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0
218 //skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1
219 //skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2
220 //skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3
221 //skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//LPC_FRAME_ESPI_CS_N
222 //skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//INT_SERIRQ
223 //skip for eSPI function {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_S0ix_R_N
224 {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_CLKRUN_N
225 //skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK
226 {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//PCH_CLK_PCI_TPM
227 {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//EC_HID_INTR
228 {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N
229 {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SUS_PWR_ACK_R
230 //skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N
231 {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SUSACK_R_N
232 {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_SEL
233 {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_EN_N
234 {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_0_SENSOR
235 {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_1_SENSOR
236 {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_2_SENSOR
237 {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CHUB_IRQ
238 {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP_N
239 {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//FPS_DRDY
240 {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID0
241 {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID1
242 {GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRALERTB
243 {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}},//TCH_PAD_INTR_R_N
244 {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_KILL_N
245 {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_BT_UART_WAKE_N
246 // {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT1_N
247 // {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT2_LAN_N
248 // {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N
249 // {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WIGIG_N
250 // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WLAN_N
251 {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EXT_PWR_GATEB
252 {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP_S0_N
253 {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST_N
254 {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_PWREN
255 {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_DFU
256 {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N
257 {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset, GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N
258 {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//PCH_SLOT1_WAKE_N
259 {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GSPI1_CS_R1_N
260 {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_CLK_R1
261 {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MISO_R1
262 {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1
263 {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N
264 {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK
265 {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_DATA
266 {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N
267 {GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CLK
268 {GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DATA
269 {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N
270 {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CLK
271 {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_DATA
272 {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RXD
273 {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_TXD
274 {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RTS_N
275 {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_CTS_N
276 {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD
277 {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD
278 {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N
279 {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N
280 {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SDA
281 {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SCL
282 {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SDA
283 {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SCL
284 {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RXD
285 {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_TXD
286 {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RTS_N
287 {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_CTS_N
288 {GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CS_N
289 {GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CLK
290 {GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MISO
291 {GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MOSI
292 {GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FLASH_STROBE
293 {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SDA
294 {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SCL
295 {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SDA
296 {GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SCL
297 {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//HOME_BTN
298 {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SCREEN_LOCK_PCH
299 {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_UP_PCH
300 {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_DOWN_PCH
301 {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA
302 {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK
303 {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RTS_N
304 {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N
305 {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_1
306 {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_1
307 {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_0
308 {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_0
309 {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO2
310 {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO3
311 {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCLK
312 {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//SPI_TPM_HDR_IRQ_N
313 {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_ODD_PRSNT_N
314 {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N
315 {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_DFU_N
316 {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_RESET
317 {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R
318 {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R
319 {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SATA_LED_N
320 {GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_0_WP1_OTG_N
321 {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_1_WP4_N
322 {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N
323 {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_IRQ
324 {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HPD_Q
325 {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HPD_Q
326 {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNone}},//SMC_EXTSMI_R_N
327 {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//SMC_RUNTIME_SCI_R_N
328 {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD
329 {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CTRL_CLK
330 {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_CTRL_DATA
331 {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CTRL_CLK
332 {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_CTRL_DATA
333 {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_CODEC_IRQ
334 {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_RST_N
335 {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SCLK
336 {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SFRM
337 {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TXD
338 {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RXD
339 {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA
340 {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL
341 {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA
342 {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL
343 {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA
344 {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL
345 {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA
346 {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL
347 {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD
348 {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA0
349 {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA1
350 {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA2
351 {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA3
352 {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA4
353 {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA5
354 {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA6
355 {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA7
356 {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCLK
357 {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK
358 {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET
359 {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD
360 {GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA0
361 {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA1
362 {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA2
363 {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA3
364 {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB
365 {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK
366 {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP
367 {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N
368 {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R
369 {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N
370 {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R_N
371 {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N
372 {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N
373 {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N
374 {GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_INTRUDET_N
375 {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK
376 {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_N
377 {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N
378 {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENABLE
379 {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of Table
380 };
381
382 #endif //_GPIO_CONFIG_H_
GpioOutDefault
@ GpioOutDefault
Leave output value unmodified.
Definition: GpioConfig.h:182
GpioDirInInv
@ GpioDirInInv
Set pad for input with inversion.
Definition: GpioConfig.h:172
GpioOutLow
@ GpioOutLow
Set output to low.
Definition: GpioConfig.h:183
GpioDirOut
@ GpioDirOut
Set pad for output only.
Definition: GpioConfig.h:173
GpioIntEdge
@ GpioIntEdge
Set interrupt as edge triggered (type of edge depends on input inversion)
Definition: GpioConfig.h:215
GpioTermWpu20K
@ GpioTermWpu20K
20kOhm weak pull-up
Definition: GpioConfig.h:297
GpioTermWpd20K
@ GpioTermWpd20K
20kOhm weak pull-down
Definition: GpioConfig.h:293
GpioDirIn
@ GpioDirIn
Set pad for input only.
Definition: GpioConfig.h:171
GpioTermNone
@ GpioTermNone
none
Definition: GpioConfig.h:291
GpioIntApic
@ GpioIntApic
Enable IOxAPIC interrupt only.
Definition: GpioConfig.h:213
GpioIntLevel
@ GpioIntLevel
Set interrupt as level triggered.
Definition: GpioConfig.h:214
GpioResumeReset
@ GpioResumeReset
New GPIO reset configuration options.
Definition: GpioConfig.h:248
GpioDswReset
@ GpioDswReset
Deep Sleep Well Reset (DSW_PWROK) GPP: not applicable GPD: PadRstCfg = 00b = "Powergood" Pad settings...
Definition: GpioConfig.h:281
GpioIntSmi
@ GpioIntSmi
Enable SMI interrupt only.
Definition: GpioConfig.h:211
GpioIntDis
@ GpioIntDis
Disable IOxAPIC/SCI/SMI/NMI interrupt generation.
Definition: GpioConfig.h:209
GpioHostDeepReset
@ GpioHostDeepReset
Host Deep Reset PadRstCfg = 01b = "Deep GPIO Reset" Pad settings will reset on:
Definition: GpioConfig.h:259
GpioIntSci
@ GpioIntSci
Enable SCI interrupt only.
Definition: GpioConfig.h:212
GpioPlatformReset
@ GpioPlatformReset
Platform Reset (PLTRST) PadRstCfg = 10b = "GPIO Reset" Pad settings will reset on:
Definition: GpioConfig.h:269
GpioTolerance1v8
@ GpioTolerance1v8
Enable 1.8V pad tolerance.
Definition: GpioConfig.h:307
GpioOutHigh
@ GpioOutHigh
Set output to high.
Definition: GpioConfig.h:184
GpioHostOwnGpio
@ GpioHostOwnGpio
Set HOST ownership to GPIO Driver mode.
Definition: GpioConfig.h:161
GpioDirNone
@ GpioDirNone
Disable both output and input.
Definition: GpioConfig.h:174
GpioHostOwnAcpi
@ GpioHostOwnAcpi
Set HOST ownership to ACPI.
Definition: GpioConfig.h:154
GpioIntLvlEdgDis
@ GpioIntLvlEdgDis
Disable interrupt trigger.
Definition: GpioConfig.h:216
Generated on Mon Dec 29 2025 02:15:46 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: HdAudioConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hda
Classes | Macros
HdAudioConfig.h File Reference

HDAUDIO policy. More...

#include <ConfigBlock.h>
#include <PchLimits.h>
Include dependency graph for HdAudioConfig.h:

Go to the source code of this file.

Classes

struct | HDA_VERB_TABLE_HEADER
Azalia verb table header Every verb table should contain this defined header and followed by azalia verb commands. More...
struct | HDA_LINK_HDA
HD Audio Link Policies. More...
struct | HDA_LINK_DMIC
HD Audio DMIC Interface Policies. More...
struct | HDA_LINK_SSP
HD Audio SSP Interface Policies. More...
struct | HDA_LINK_SNDW
HD Audio SNDW Interface Policies. More...
struct | HDAUDIO_PREMEM_CONFIG
This structure contains the premem policies which are related to HD Audio device (cAVS). More...
struct | HDAUDIO_DXE_CONFIG
This structure contains the DXE policies which are related to HD Audio device (cAVS). More...

Macros

#define | HDAUDIO_PREMEM_CONFIG_REVISION 2
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version. More...
#define | HDAUDIO_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.
#define | HDAUDIO_DXE_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.
#define | HDAUDIO_VERB_TABLE_VIDDID(Vid, Did) (UINT32)((UINT16)Vid | ((UINT16)Did << 16))
The PCH_HDAUDIO_CONFIG block describes the expected configuration of the Intel HD Audio feature.
#define | HDAUDIO_VERB_TABLE_INIT(Vid, Did, Rid, Sdi, ...)
Use this macro to create HDAUDIO_VERB_TABLE and populate size automatically.

Detailed Description

HDAUDIO policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2022 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HdAudioConfig.h.

Macro Definition Documentation

◆ HDAUDIO_PREMEM_CONFIG_REVISION

#define HDAUDIO_PREMEM_CONFIG_REVISION 2

Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Revision 2: - Add HdaDiscBtOffload.

Definition at line 48 of file HdAudioConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: HdAudioConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hda
HdAudioConfig.h
Go to the documentation of this file.
1 /** @file
2 HDAUDIO policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2022 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _HDAUDIO_CONFIG_H_
36 #define _HDAUDIO_CONFIG_H_
37
38 #include <ConfigBlock.h>
39 #include <PchLimits.h>
40
41 /**
42 Making any structure change after API Lock
43 will need to maintain backward compatibility, bump up
44 structure revision and update below history table\n
45 <b>Revision 1</b>: - Initial version.
46 <b>Revision 2</b>: - Add HdaDiscBtOffload.
47 **/
48 #define HDAUDIO_PREMEM_CONFIG_REVISION 2
49 /**
50 Making any structure change after API Lock
51 will need to maintain backward compatibility, bump up
52 structure revision and update below history table\n
53 <b>Revision 1</b>: - Initial version.
54 **/
55 #define HDAUDIO_CONFIG_REVISION 1
56 /**
57 Making any structure change after API Lock
58 will need to maintain backward compatibility, bump up
59 structure revision and update below history table\n
60 <b>Revision 1</b>: - Initial version.
61 **/
62 #define HDAUDIO_DXE_CONFIG_REVISION 1
63
64 extern EFI_GUID gHdAudioPreMemConfigGuid;
65 extern EFI_GUID gHdAudioConfigGuid;
66 extern EFI_GUID gHdAudioDxeConfigGuid;
67
68 #pragma pack (push,1)
69
70 ///
71 /// The PCH_HDAUDIO_CONFIG block describes the expected configuration of the Intel HD Audio feature.
72 ///
73
74 #define HDAUDIO_VERB_TABLE_VIDDID(Vid,Did) (UINT32)((UINT16)Vid | ((UINT16)Did << 16))
75 #define HDAUDIO_VERB_TABLE_RID_SDI_SIZE(Rid,Sdi,VerbTableSize) (UINT32)((UINT8)Rid | ((UINT8)Sdi << 8) | ((UINT16)VerbTableSize << 16))
76 #define HDAUDIO_VERB_TABLE_CMD_SIZE(VerbTable) ((sizeof (VerbTable) - sizeof (HDA_VERB_TABLE_HEADER)) / (sizeof (UINT32)))
77
78 ///
79 /// Use this macro to create HDAUDIO_VERB_TABLE and populate size automatically
80 ///
81 #define HDAUDIO_VERB_TABLE_INIT(Vid,Did,Rid,Sdi,...) \
82 { \
83 { Vid, Did, Rid, Sdi, (sizeof((UINT32[]){__VA_ARGS__})/sizeof(UINT32)) }, \
84 { __VA_ARGS__ } \
85 }
86
87 /**
88 Azalia verb table header
89 Every verb table should contain this defined header and followed by azalia verb commands.
90 **/
91 typedef struct {
92 UINT16 VendorId; ///< Codec Vendor ID
93 UINT16 DeviceId; ///< Codec Device ID
94 UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
95 UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
96 UINT16 DataDwords; ///< Number of data DWORDs following the header.
97 } HDA_VERB_TABLE_HEADER;
98
99 #ifdef _MSC_VER
100 //
101 // Disable "zero-sized array in struct/union" extension warning.
102 // Used for neater verb table definitions.
103 //
104 #pragma warning (push)
105 #pragma warning (disable: 4200)
106 #endif
107 typedef struct {
108 HDA_VERB_TABLE_HEADER Header;
109 UINT32 Data[];
110 } HDAUDIO_VERB_TABLE;
111 #ifdef _MSC_VER
112 #pragma warning (pop)
113 #endif
114
115 typedef struct {
116 UINT32 ClkA; ///< Pin mux configuration. Refer to GPIO_*_MUXING_DMIC*_CLKA_*
117 UINT32 ClkB; ///< Pin mux configuration. Refer to GPIO_*_MUXING_DMIC*_CLKB_*
118 UINT32 Data; ///< Pin mux configuration. Refer to GPIO_*_MUXING_DMIC*_DATA_*
119 } HDA_DMIC_PIN_MUX;
120
121 /**
122 HD Audio Link Policies
123 **/
124 typedef struct {
125 UINT32 Enable : 1; ///< HDA interface enable. When enabled related pins will be switched to native mode: <b>0: Disable</b>; 1: Enable.
126 UINT32 RsvdBits0 : 31;
127 UINT8 SdiEnable[PCH_MAX_HDA_SDI]; ///< HDA SDI signal enable. When enabled related SDI pins will be switched to appropriate native mode: <b>0: Disable</b>; 1: Enable
128 UINT8 Reserved[(4 - (PCH_MAX_HDA_SDI % 4)) % 4]; ///< Padding for SDI enable table.
129 } HDA_LINK_HDA;
130
131 /**
132 HD Audio DMIC Interface Policies
133 **/
134 typedef struct {
135 UINT32 Enable : 1; ///< HDA DMIC interface enable. When enabled related pins will be switched to native mode: <b>0: Disable</b>; 1: Enable.
136 UINT32 DmicClockSelect : 2; ///< DMIC link clock select: <b>0: Both</b>, 1: ClkA, 2: ClkB; default is "Both"
137 UINT32 RsvdBits0 : 29;
138 HDA_DMIC_PIN_MUX PinMux; ///< Pin mux configuration.
139 } HDA_LINK_DMIC;
140
141 /**
142 HD Audio SSP Interface Policies
143 **/
144 typedef struct {
145 UINT32 Enable : 1; ///< HDA SSP interface enable. When enabled related pins will be switched to native mode: <b>0: Disable</b>; 1: Enable.
146 UINT32 RsvdBits0 : 31;
147 } HDA_LINK_SSP;
148
149 /**
150 HD Audio SNDW Interface Policies
151 **/
152 typedef struct {
153 UINT32 Enable : 1; ///< HDA SNDW interface enable. When enabled related pins will be switched to native mode: <b>0: Disable</b>; 1: Enable.
154 UINT32 RsvdBits0 : 31;
155 } HDA_LINK_SNDW;
156
157 typedef struct {
158 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
159 UINT32 Pme : 1; ///< Azalia wake-on-ring, <b>0: Disable</b>; 1: Enable
160 UINT32 CodecSxWakeCapability : 1; ///< Capability to detect wake initiated by a codec in Sx (eg by modem codec), <b>0: Disable</b>; 1: Enable
161 UINT32 HdAudioLinkFrequency : 4; ///< HDA-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): <b>2: 24MHz</b>, 1: 12MHz, 0: 6MHz
162 UINT32 RsvdBits0 : 26; ///< Reserved bits 0
163 /**
164 Number of the verb table entry defined in VerbTablePtr.
165 Each entry points to a verb table which contains HDAUDIO_VERB_TABLE structure and verb command blocks.
166 **/
167 UINT8 VerbTableEntryNum;
168 UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4
169 /**
170 Pointer to a verb table array.
171 This pointer points to 32bits address, and is only eligible and consumed in post mem phase.
172 Each entry points to a verb table which contains HDAUDIO_VERB_TABLE structure and verb command blocks.
173 The prototype of this is:
174 HDAUDIO_VERB_TABLE **VerbTablePtr;
175 **/
176 UINTN VerbTablePtr;
177 } HDAUDIO_CONFIG;
178
179 typedef struct {
180 UINT32 HdaDiscBtOffEnabled : 1; ///< Discrete BT Offload Enabled
181 UINT32 HdaDiscBtOffSspLink : 3; ///< Discrete BT Offload Ssp Link
182 UINT32 Reserved : 28; ///< Reserved bits
183 } HDAUDIO_DISC_BT_OFFLOAD;
184
185 /**
186 This structure contains the premem policies which are related to HD Audio device (cAVS).
187
188 <b>Revision 1:</b>
189 - Inital version.
190 <b>Revision 2:</b>
191 - Add DmicClockSelect
192 <b>Revision 3:</b>
193 - Add AudioFpgaSocVer
194 <b>Revision 4:</b>
195 - Remove AudioFpgaSocVer
196 <b>Revision 5:</b>
197 - Add HdaDiscBtOffload
198 **/
199 typedef struct {
200 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
201 UINT32 Enable : 1; ///< Intel HD Audio (Azalia) enablement: 0: Disable, <b>1: Enable</b>
202 UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; <b>1: Enable</b>
203 UINT32 VcType : 1; ///< Virtual Channel Type Select: <b>0: VC0</b>, 1: VC1
204 /**
205 Universal Audio Architecture compliance for DSP enabled system:
206 <b>0: Not-UAA Compliant (Intel SST driver supported only)</b>,
207 1: UAA Compliant (HDA Inbox driver or SST driver supported)
208 **/
209 UINT32 DspUaaCompliance : 1;
210 UINT32 IDispLinkFrequency : 4; ///< iDisp-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): <b>4: 96MHz</b>, 3: 48MHz
211 UINT32 IDispLinkTmode : 3; ///< iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T, 2: 4T, <b>3: 8T</b>, 4: 16T
212 UINT32 IDispCodecDisconnect : 1; ///< iDisplay Audio Codec disconnection, <b>0: Not disconnected, enumerable</b>; 1: Disconnected SDI, not enumerable
213 UINT32 PowerGatingSupported : 1; ///< Power Gating supported: <b>0: Not supported</b>, 1: Supported
214 UINT32 SndwMultilaneEnable : 2; ///< Sndw0 Multiline enablement: <b>0: Disable</b>, 1: Two lines enabled, 2: Three lines enabled, 3: Four Lines enabled
215 UINT32 RsvdBits : 17; ///< Reserved bits 0
216
217 /**
218 Audio Link Mode configuration bitmask.
219 Allows to configure enablement of the following interfaces: HDA-Link, DMIC, SSP, SoundWire.
220 **/
221
222 HDA_LINK_HDA AudioLinkHda; ///< HDA-Link enablement: 0: Disable; <b>1: Enable</b>.
223 /**
224 DMIC link enablement: 0: Disable; <b>1: Enable</b>.
225 DMIC0 LKF: Muxed with SNDW2/SNDW4.
226 **/
227 HDA_LINK_DMIC AudioLinkDmic [PCH_MAX_HDA_DMIC_LINK_NUM];
228 /**
229 I2S/SSP link enablement: <b>0: Disable</b>; 1: Enable.
230 SSP0/1 LKF: Muxed with HDA.
231 @note Since the I2S/SSP2 pin set contains pads which are also used for CNVi purpose, enabling AudioLinkSsp2
232 is exclusive with CNVi is present.
233 **/
234 HDA_LINK_SSP AudioLinkSsp [PCH_MAX_HDA_SSP_LINK_NUM];
235 /**
236 SoundWire link enablement: <b>0: Disable</b>; 1: Enable.
237 SNDW2 LKF: Muxed with DMIC0/DMIC1.
238 SNDW3 LKF: Muxed with DMIC1.
239 SNDW4 LKF: Muxed with DMIC0.
240 **/
241 HDA_LINK_SNDW AudioLinkSndw [PCH_MAX_HDA_SNDW_LINK_NUM];
242
243 UINT16 ResetWaitTimer; ///< <b>(Test)</b> The delay timer after Azalia reset, the value is number of microseconds. Default is <b>600</b>.
244 UINT8 Rsvd0[2]; ///< Reserved bytes, align to multiple 4
245 UINT32 SubSystemIds; ///< Value for SID and SVID. If its set to 0 then default value is used.
246 /**
247 Discrete BT HCI Audio Offload Support
248 **/
249 HDAUDIO_DISC_BT_OFFLOAD HdaDiscBtOffload;
250 } HDAUDIO_PREMEM_CONFIG;
251
252 typedef struct {
253 UINT32 AutonomousClockStop : 1; ///< SoundWire1 link autonomous clock stop capability: <b>0: Disable</b>; 1: Enable
254 UINT32 DataOnActiveIntervalSelect : 2; ///< SoundWire1 link data on active interval select 0: 6 clock periods; <b>1: 7 clock periods</b>; 2: 8 clock periods; 3: 11 clock periods
255 UINT32 DataOnDelaySelect : 1; ///< SoundWire1 link data on delay select 0: 2 clock periods; <b>1: 3 clock periods</b>
256 UINT32 RsvdBits1 : 28; ///< Reserved bits 1
257 } HDAUDIO_SNDW_CONFIG;
258
259 /**
260 This structure contains the DXE policies which are related to HD Audio device (cAVS).
261 <b>Revision 1:</b>
262 - Inital version.
263 <b>Revision 2:</b>
264 - Add IoControlEnabled
265 <b>Revision 3:</b>
266 - Remove IoControlEnabled
267 **/
268 typedef struct {
269 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
270 /**
271 SNDW configuration for exposed via SNDW ACPI tables:
272 **/
273 HDAUDIO_SNDW_CONFIG SndwConfig[PCH_MAX_HDA_SNDW_LINK_NUM];
274 /**
275 Bitmask of supported DSP features:
276 [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6] - BT Intel A2DP
277 [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel WoV, 1: Windows Voice Activation
278 [BIT9] - BT Intel Low Energy;[BIT9] - 0 BT Intel Low Energy is not supported , 1: BT Intel Low Energy is supported
279 Default is <b>zero</b>.
280 **/
281 UINT32 DspFeatureMask;
282 /**
283 * Discrete BT HCI Audio Offload Support
284 **/
285 HDAUDIO_DISC_BT_OFFLOAD HdaDiscBtOffload;
286 } HDAUDIO_DXE_CONFIG;
287
288 #pragma pack (pop)
289
290 #endif // _HDAUDIO_CONFIG_H_
HDA_VERB_TABLE_HEADER::SdiNum
UINT8 SdiNum
SDI number, 0xFF matches any SDI.
Definition: HdAudioConfig.h:95
HDA_LINK_SSP
HD Audio SSP Interface Policies.
Definition: HdAudioConfig.h:144
HDAUDIO_PREMEM_CONFIG::HdaDiscBtOffload
HDAUDIO_DISC_BT_OFFLOAD HdaDiscBtOffload
Discrete BT HCI Audio Offload Support.
Definition: HdAudioConfig.h:249
ConfigBlock.h
Header file for Config Block Lib implementation.
HDAUDIO_PREMEM_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved bits 0.
Definition: HdAudioConfig.h:215
HDAUDIO_PREMEM_CONFIG::SndwMultilaneEnable
UINT32 SndwMultilaneEnable
Sndw0 Multiline enablement: 0: Disable, 1: Two lines enabled, 2: Three lines enabled,...
Definition: HdAudioConfig.h:214
HDA_LINK_SNDW::Enable
UINT32 Enable
HDA SNDW interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: ...
Definition: HdAudioConfig.h:153
HDA_LINK_DMIC::PinMux
HDA_DMIC_PIN_MUX PinMux
Pin mux configuration.
Definition: HdAudioConfig.h:138
HDA_LINK_HDA
HD Audio Link Policies.
Definition: HdAudioConfig.h:124
HDAUDIO_DXE_CONFIG
This structure contains the DXE policies which are related to HD Audio device (cAVS).
Definition: HdAudioConfig.h:268
HDA_VERB_TABLE_HEADER::VendorId
UINT16 VendorId
Codec Vendor ID.
Definition: HdAudioConfig.h:92
HDAUDIO_PREMEM_CONFIG::DspUaaCompliance
UINT32 DspUaaCompliance
Universal Audio Architecture compliance for DSP enabled system: 0: Not-UAA Compliant (Intel SST drive...
Definition: HdAudioConfig.h:209
HDA_LINK_DMIC::Enable
UINT32 Enable
HDA DMIC interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: ...
Definition: HdAudioConfig.h:135
HDAUDIO_PREMEM_CONFIG::Enable
UINT32 Enable
Intel HD Audio (Azalia) enablement: 0: Disable, 1: Enable
Definition: HdAudioConfig.h:201
HDA_VERB_TABLE_HEADER::RevisionId
UINT8 RevisionId
Revision ID of the codec. 0xFF matches any revision.
Definition: HdAudioConfig.h:94
HDAUDIO_PREMEM_CONFIG::SubSystemIds
UINT32 SubSystemIds
Value for SID and SVID. If its set to 0 then default value is used.
Definition: HdAudioConfig.h:245
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
HDAUDIO_PREMEM_CONFIG::AudioLinkHda
HDA_LINK_HDA AudioLinkHda
Audio Link Mode configuration bitmask.
Definition: HdAudioConfig.h:222
HDAUDIO_PREMEM_CONFIG::IDispLinkFrequency
UINT32 IDispLinkFrequency
iDisp-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz
Definition: HdAudioConfig.h:210
HDA_LINK_DMIC
HD Audio DMIC Interface Policies.
Definition: HdAudioConfig.h:134
HDAUDIO_PREMEM_CONFIG::DspEnable
UINT32 DspEnable
DSP enablement: 0: Disable; 1: Enable
Definition: HdAudioConfig.h:202
HDAUDIO_PREMEM_CONFIG::PowerGatingSupported
UINT32 PowerGatingSupported
Power Gating supported: 0: Not supported, 1: Supported.
Definition: HdAudioConfig.h:213
HDA_LINK_DMIC::DmicClockSelect
UINT32 DmicClockSelect
DMIC link clock select: 0: Both, 1: ClkA, 2: ClkB; default is "Both".
Definition: HdAudioConfig.h:136
HDAUDIO_PREMEM_CONFIG::VcType
UINT32 VcType
Virtual Channel Type Select: 0: VC0, 1: VC1.
Definition: HdAudioConfig.h:203
HDAUDIO_DXE_CONFIG::HdaDiscBtOffload
HDAUDIO_DISC_BT_OFFLOAD HdaDiscBtOffload
Discrete BT HCI Audio Offload Support.
Definition: HdAudioConfig.h:285
HDA_VERB_TABLE_HEADER::DeviceId
UINT16 DeviceId
Codec Device ID.
Definition: HdAudioConfig.h:93
HDAUDIO_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: HdAudioConfig.h:200
HDAUDIO_PREMEM_CONFIG::ResetWaitTimer
UINT16 ResetWaitTimer
(Test) The delay timer after Azalia reset, the value is number of microseconds. Default is 600.
Definition: HdAudioConfig.h:243
HDA_LINK_SSP::Enable
UINT32 Enable
HDA SSP interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: E...
Definition: HdAudioConfig.h:145
HDAUDIO_DXE_CONFIG::DspFeatureMask
UINT32 DspFeatureMask
Bitmask of supported DSP features: [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - B...
Definition: HdAudioConfig.h:281
HDAUDIO_PREMEM_CONFIG::IDispCodecDisconnect
UINT32 IDispCodecDisconnect
iDisplay Audio Codec disconnection, 0: Not disconnected, enumerable; 1: Disconnected SDI,...
Definition: HdAudioConfig.h:212
HDA_VERB_TABLE_HEADER::DataDwords
UINT16 DataDwords
Number of data DWORDs following the header.
Definition: HdAudioConfig.h:96
HDAUDIO_DXE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: HdAudioConfig.h:269
HDA_LINK_HDA::Enable
UINT32 Enable
HDA interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: Enabl...
Definition: HdAudioConfig.h:125
HDAUDIO_PREMEM_CONFIG
This structure contains the premem policies which are related to HD Audio device (cAVS).
Definition: HdAudioConfig.h:199
HDA_LINK_SNDW
HD Audio SNDW Interface Policies.
Definition: HdAudioConfig.h:152
HDAUDIO_PREMEM_CONFIG::IDispLinkTmode
UINT32 IDispLinkTmode
iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T, 2: 4T, 3: 8T, 4: 16T
Definition: HdAudioConfig.h:211
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
HDA_VERB_TABLE_HEADER
Azalia verb table header Every verb table should contain this defined header and followed by azalia v...
Definition: HdAudioConfig.h:91
Generated on Mon Dec 29 2025 02:15:46 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: HostBridgeConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HostBridge
  • Ver2
Macros
HostBridgeConfig.h File Reference

Configurations for HostBridge. More...

#include <ConfigBlock.h>
Include dependency graph for HostBridgeConfig.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | HOST_BRIDGE_PREMEM_CONFIG_REVISION 2
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version. More...
#define | HOST_BRIDGE_PEI_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Detailed Description

Configurations for HostBridge.

Copyright
INTEL CONFIDENTIAL Copyright 2020 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HostBridgeConfig.h.

Macro Definition Documentation

◆ HOST_BRIDGE_PREMEM_CONFIG_REVISION

#define HOST_BRIDGE_PREMEM_CONFIG_REVISION 2

Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Revision 2: - Added RootBridgeReservedMmio. Revision 3 - Added RootBridgeReservedIo.

Definition at line 48 of file HostBridgeConfig.h.

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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: HostBridgeConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HostBridge
  • Ver2
HostBridgeConfig.h
Go to the documentation of this file.
1 /** @file
2 Configurations for HostBridge
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _HOST_BRIDGE_CONFIG_H_
36 #define _HOST_BRIDGE_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 /**
41 Making any structure change after API Lock
42 will need to maintain backward compatibility, bump up
43 structure revision and update below history table\n
44 <b>Revision 1</b>: - Initial version.
45 <b>Revision 2</b>: - Added RootBridgeReservedMmio.
46 <b>Revision 3</b> - Added RootBridgeReservedIo.
47 **/
48 #define HOST_BRIDGE_PREMEM_CONFIG_REVISION 2
49 /**
50 Making any structure change after API Lock
51 will need to maintain backward compatibility, bump up
52 structure revision and update below history table\n
53 <b>Revision 1</b>: - Initial version.
54 **/
55 #define HOST_BRIDGE_PEI_CONFIG_REVISION 1
56
57 #define MAX_ROOT_BRIDGES 2
58
59 extern EFI_GUID gHostBridgePeiPreMemConfigGuid;
60 extern EFI_GUID gHostBridgePeiConfigGuid;
61
62 #pragma pack (push,1)
63
64 typedef struct {
65 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
66 UINT32 MchBar; ///< Offset 28 Address of System Agent MCHBAR: <b>0xFEDC0000(TGL)/0xFEA80000(JSL)<b>
67 UINT32 DmiBar; ///< Offset 32 Address of System Agent DMIBAR: <b>0xFEDA0000</b>
68 UINT32 RegBar; ///< Offset 36 Address of System Agent REGBAR: <b>0xD0000000</b>
69 /**
70 Offset 40 :
71 Size of reserved MMIO space for PCI devices\n
72 <b>0=AUTO</b>, 512=512MB, 768=768MB, 1024=1024MB, 1280=1280MB, 1536=1536MB, 1792=1792MB,
73 2048=2048MB, 2304=2304MB, 2560=2560MB, 2816=2816MB, 3072=3072MB\n
74 When AUTO mode selected, the MMIO size will be calculated by required MMIO size from PCIe devices detected.
75 **/
76 UINT32 MmioSize;
77 UINT32 MmioSizeAdjustment; ///< Offset 44 Increase (given positive value) or Decrease (given negative value) the Reserved MMIO size when Dynamic Tolud/AUTO mode enabled (in MBs): <b>0=no adjustment</b>
78 UINT32 ApicLocalAddress; ///< Offset 48 Address of System Agent ApicLocalAddress: <b>0xFEE00000</b>
79 UINT32 NvmeHcPeiMmioBase; ///< Offset 52 Address of System Agent NvmeHcPeiMmioBase: <b>0xA0000000</b>
80 UINT32 NvmeHcPeiMmioLimit; ///< Offset 56 Address of System Agent NvmeHcPeiMmioLimit: <b>0xA1000000</b>
81 UINT32 AhciPeiMmioBase; ///< Offset 60 Address of System Agent AhciPeiMmioBase: <b>0xD1000000</b>
82 UINT32 AhciPeiMmioLimit; ///< Offset 64 Address of System Agent AhciPeiMmioLimit: <b>0xD10FFFFF</b>
83 UINT16 EcExtraIoBase; ///< Offset 68 Address of System Agent EcExtraIoBase: <b>0x6A0</b>
84 UINT16 SioBaseAddress; ///< Offset 70 Address of System Agent SioBaseAddress: <b>0x0680</b>
85 UINT32 VmdCfgBarBar; ///< Offset 72 Address of System Agent VmdCfgBarBase: <b>0xA0000000</b>
86 UINT32 VmdMemBar2Bar; ///< Offset 76 Address of System Agent VmdMemBar2Base: <b>0xA4000000</b>
87 UINT32 VmdMemBar1Bar; ///< Offset 80 Address of System Agent VmdMemBar1Base: <b>0xA2000000</b>
88 UINT8 CridEnable; ///< Offset 84 For Platforms supporting Intel(R) SIPP, this policy is use control enable/disable Compatibility Revision ID (CRID) feature: <b>0=FALSE</b>, 1=TRUE
89 UINT8 EnableAbove4GBMmio; ///< Offset 85 Enable/disable above 4GB MMIO resource support: 0=Disable, <b>1=Enable</b>
90 UINT16 RootBridgeReservedMmio[MAX_ROOT_BRIDGES]; ///< Offset 86 MMIO32 reserved for each rootbridge in the system.
91 UINT8 RootBridgeReservedIo[MAX_ROOT_BRIDGES]; ///< Offset 90 IO reserved for each rootbridge in the system.
92 UINT8 Rsvd[4]; ///< Offset 92 Reserved for future use.
93 } HOST_BRIDGE_PREMEM_CONFIG;
94
95 typedef struct {
96 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
97 UINT8 Device4Enable; ///< Offser 28 :This policy is used to control enable or disable System Agent Thermal device (0,4,0). <b>0=FALSE</b>, 1=TRUE.
98 UINT8 SkipPamLock; ///< Offset 29 :To skip PAM register locking. @note It is still recommended to set PCI Config space B0: D0: F0: Offset 80h[0]=1 in platform code even Silicon code skipped this.\n <b>0=All PAM registers will be locked in Silicon code</b>, 1=Skip lock PAM registers in Silicon code.
99 UINT8 Reserved[2]; ///< Offset 31 Reserved for future use.
100 } HOST_BRIDGE_PEI_CONFIG;
101
102 #pragma pack (pop)
103
104 #endif
ConfigBlock.h
Header file for Config Block Lib implementation.
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: HsioConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hsio
Classes | Macros
HsioConfig.h File Reference

HSIO policy. More...

Go to the source code of this file.

Classes

struct | PCH_HSIO_PREMEM_CONFIG
The PCH_HSIO_PREMEM_CONFIG block provides HSIO message related settings. More...
struct | PCH_HSIO_CONFIG
The PCH_HSIO_CONFIG block provides HSIO message related settings. More...

Macros

#define | PCH_HSIO_PREMEM_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.
#define | PCH_HSIO_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Detailed Description

HSIO policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HsioConfig.h.

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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: HsioConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hsio
HsioConfig.h
Go to the documentation of this file.
1 /** @file
2 HSIO policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _HSIO_CONFIG_H_
36 #define _HSIO_CONFIG_H_
37 /**
38 Making any structure change after API Lock
39 will need to maintain backward compatibility, bump up
40 structure revision and update below history table\n
41 <b>Revision 1</b>: - Initial version.
42 **/
43 #define PCH_HSIO_PREMEM_CONFIG_REVISION 1
44 extern EFI_GUID gHsioPreMemConfigGuid;
45
46 /**
47 Making any structure change after API Lock
48 will need to maintain backward compatibility, bump up
49 structure revision and update below history table\n
50 <b>Revision 1</b>: - Initial version.
51 **/
52 #define PCH_HSIO_CONFIG_REVISION 1
53 extern EFI_GUID gHsioConfigGuid;
54
55 #pragma pack (push,1)
56
57 /**
58 The PCH_HSIO_PREMEM_CONFIG block provides HSIO message related settings.
59 **/
60 typedef struct {
61 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
62
63 /**
64 <b>(Test)</b>
65 0- Disable, disable will prevent the HSIO version check and ChipsetInit HECI message from being sent
66 <b>1- Enable</b> ChipsetInit HECI message
67 **/
68 UINT8 ChipsetInitMessage;
69 /**
70 <b>(Test)</b>
71 <b>0- Disable</b>
72 1- Enable When enabled, this is used to bypass the reset after ChipsetInit HECI message.
73 **/
74 UINT8 BypassPhySyncReset;
75 UINT8 RsvdBytes[2];
76
77 } PCH_HSIO_PREMEM_CONFIG;
78
79
80 /**
81 The PCH_HSIO_CONFIG block provides HSIO message related settings.
82 **/
83 typedef struct {
84 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
85 UINT32 ChipsetInitBinPtr; ///< Policy used to point to the Base (+ OEM) ChipsetInit binary used to sync between BIOS and CSME
86 UINT32 ChipsetInitBinLen; ///< Policy used to indicate the size of the Base (+ OEM) ChipsetInit binary used to sync between BIOS and CSME
87 UINT32 NphyBinPtr; ///< Policy used to point to the OEM Nphy binary used to sync between BIOS and CSME
88 UINT32 NphyBinLen; ///< Policy used to indicate the size of the OEM Nphy binary used to sync between BIOS and CSME
89 UINT8 EnableIoMargining;
90 UINT8 ReservedBits[3];
91 UINT32 SynpsPhyBinPtr; ///< Policy used to point to the OEM Synophsys Phy binary used to sync between BIOS and CSME
92 UINT32 SynpsPhyBinLen; ///< Policy used to indicate the size of the OEM Synophsys Phy binary used to sync between BIOS and CSME
93 } PCH_HSIO_CONFIG;
94
95 #pragma pack (pop)
96
97 #endif // _HSIO_CONFIG_H_
PCH_HSIO_CONFIG::SynpsPhyBinLen
UINT32 SynpsPhyBinLen
Policy used to indicate the size of the OEM Synophsys Phy binary used to sync between BIOS and CSME.
Definition: HsioConfig.h:92
PCH_HSIO_CONFIG::SynpsPhyBinPtr
UINT32 SynpsPhyBinPtr
Policy used to point to the OEM Synophsys Phy binary used to sync between BIOS and CSME.
Definition: HsioConfig.h:91
PCH_HSIO_CONFIG::ChipsetInitBinLen
UINT32 ChipsetInitBinLen
Policy used to indicate the size of the Base (+ OEM) ChipsetInit binary used to sync between BIOS and...
Definition: HsioConfig.h:86
PCH_HSIO_PREMEM_CONFIG
The PCH_HSIO_PREMEM_CONFIG block provides HSIO message related settings.
Definition: HsioConfig.h:60
PCH_HSIO_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: HsioConfig.h:84
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_HSIO_CONFIG
The PCH_HSIO_CONFIG block provides HSIO message related settings.
Definition: HsioConfig.h:83
PCH_HSIO_PREMEM_CONFIG::BypassPhySyncReset
UINT8 BypassPhySyncReset
(Test) 0- Disable 1- Enable When enabled, this is used to bypass the reset after ChipsetInit HECI mes...
Definition: HsioConfig.h:74
PCH_HSIO_CONFIG::NphyBinPtr
UINT32 NphyBinPtr
Policy used to point to the OEM Nphy binary used to sync between BIOS and CSME.
Definition: HsioConfig.h:87
PCH_HSIO_CONFIG::NphyBinLen
UINT32 NphyBinLen
Policy used to indicate the size of the OEM Nphy binary used to sync between BIOS and CSME.
Definition: HsioConfig.h:88
PCH_HSIO_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: HsioConfig.h:61
PCH_HSIO_CONFIG::ChipsetInitBinPtr
UINT32 ChipsetInitBinPtr
Policy used to point to the Base (+ OEM) ChipsetInit binary used to sync between BIOS and CSME.
Definition: HsioConfig.h:85
PCH_HSIO_PREMEM_CONFIG::ChipsetInitMessage
UINT8 ChipsetInitMessage
(Test) 0- Disable, disable will prevent the HSIO version check and ChipsetInit HECI message from bein...
Definition: HsioConfig.h:68
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:46 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: HsioPcieConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hsio
Classes
HsioPcieConfig.h File Reference

HSIO pcie policy. More...

#include <PchLimits.h>
Include dependency graph for HsioPcieConfig.h:

Go to the source code of this file.

Classes

struct | PCH_HSIO_PCIE_LANE_CONFIG
The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane. More...
struct | PCH_HSIO_PCIE_PREMEM_CONFIG
The PCH_HSIO_PCIE_CONFIG block describes the configuration of the HSIO for PCIe lanes. More...

Detailed Description

HSIO pcie policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HsioPcieConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: HsioPcieConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hsio
HsioPcieConfig.h
Go to the documentation of this file.
1 /** @file
2 HSIO pcie policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _HSIO_PCIE_CONFIG_H_
36 #define _HSIO_PCIE_CONFIG_H_
37
38 #include <PchLimits.h>
39
40 #define PCH_HSIO_PCIE_PREMEM_CONFIG_REVISION 1
41 extern EFI_GUID gHsioPciePreMemConfigGuid;
42
43 #pragma pack (push,1)
44
45 /**
46 The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane
47 **/
48 typedef struct {
49 //
50 // HSIO Rx Eq
51 // Refer to the EDS for recommended values.
52 // Note that these setting are per-lane and not per-port
53 //
54 UINT32 HsioRxSetCtleEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 3 Set CTLE Value
55 UINT32 HsioRxSetCtle : 6; ///< PCH PCIe Gen 3 Set CTLE Value
56 UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value override
57 UINT32 HsioTxGen1DownscaleAmp : 6; ///< PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value
58 UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value override
59 UINT32 HsioTxGen2DownscaleAmp : 6; ///< PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value
60 UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value override
61 UINT32 HsioTxGen3DownscaleAmp : 6; ///< PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value
62 UINT32 RsvdBits0 : 4; ///< Reserved Bits
63
64 UINT32 HsioTxGen1DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting value override
65 UINT32 HsioTxGen1DeEmph : 6; ///< PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting
66 UINT32 HsioTxGen2DeEmph3p5Enable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting value override
67 UINT32 HsioTxGen2DeEmph3p5 : 6; ///< PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting
68 UINT32 HsioTxGen2DeEmph6p0Enable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting value override
69 UINT32 HsioTxGen2DeEmph6p0 : 6; ///< PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting
70 UINT32 RsvdBits1 : 11; ///< Reserved Bits
71 } PCH_HSIO_PCIE_LANE_CONFIG;
72
73 ///
74 /// The PCH_HSIO_PCIE_CONFIG block describes the configuration of the HSIO for PCIe lanes
75 ///
76 typedef struct {
77 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
78 ///
79 /// These members describe the configuration of HSIO for PCIe lanes.
80 ///
81 PCH_HSIO_PCIE_LANE_CONFIG Lane[PCH_MAX_PCIE_ROOT_PORTS];
82 } PCH_HSIO_PCIE_PREMEM_CONFIG;
83
84 #pragma pack (pop)
85
86 #endif // _HSIO_PCIE_LANE_CONFIG_H_
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen2DeEmph3p5
UINT32 HsioTxGen2DeEmph3p5
PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting.
Definition: HsioPcieConfig.h:67
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen3DownscaleAmp
UINT32 HsioTxGen3DownscaleAmp
PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
Definition: HsioPcieConfig.h:61
PCH_HSIO_PCIE_LANE_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved Bits.
Definition: HsioPcieConfig.h:62
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen3DownscaleAmpEnable
UINT32 HsioTxGen3DownscaleAmpEnable
0: Disable; 1: Enable PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value override
Definition: HsioPcieConfig.h:60
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen2DownscaleAmpEnable
UINT32 HsioTxGen2DownscaleAmpEnable
0: Disable; 1: Enable PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value override
Definition: HsioPcieConfig.h:58
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen1DeEmph
UINT32 HsioTxGen1DeEmph
PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
Definition: HsioPcieConfig.h:65
PCH_HSIO_PCIE_LANE_CONFIG
The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane.
Definition: HsioPcieConfig.h:48
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen2DownscaleAmp
UINT32 HsioTxGen2DownscaleAmp
PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
Definition: HsioPcieConfig.h:59
PCH_HSIO_PCIE_PREMEM_CONFIG
The PCH_HSIO_PCIE_CONFIG block describes the configuration of the HSIO for PCIe lanes.
Definition: HsioPcieConfig.h:76
PCH_HSIO_PCIE_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: HsioPcieConfig.h:77
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen2DeEmph6p0
UINT32 HsioTxGen2DeEmph6p0
PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting.
Definition: HsioPcieConfig.h:69
PCH_HSIO_PCIE_LANE_CONFIG::HsioRxSetCtleEnable
UINT32 HsioRxSetCtleEnable
0: Disable; 1: Enable PCH PCIe Gen 3 Set CTLE Value
Definition: HsioPcieConfig.h:54
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen1DownscaleAmp
UINT32 HsioTxGen1DownscaleAmp
PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value.
Definition: HsioPcieConfig.h:57
PCH_HSIO_PCIE_LANE_CONFIG::HsioRxSetCtle
UINT32 HsioRxSetCtle
PCH PCIe Gen 3 Set CTLE Value.
Definition: HsioPcieConfig.h:55
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen1DownscaleAmpEnable
UINT32 HsioTxGen1DownscaleAmpEnable
0: Disable; 1: Enable PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value override
Definition: HsioPcieConfig.h:56
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen2DeEmph6p0Enable
UINT32 HsioTxGen2DeEmph6p0Enable
0: Disable; 1: Enable PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting value overr...
Definition: HsioPcieConfig.h:68
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen1DeEmphEnable
UINT32 HsioTxGen1DeEmphEnable
0: Disable; 1: Enable PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting value override
Definition: HsioPcieConfig.h:64
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen2DeEmph3p5Enable
UINT32 HsioTxGen2DeEmph3p5Enable
0: Disable; 1: Enable PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting value overr...
Definition: HsioPcieConfig.h:66
PCH_HSIO_PCIE_LANE_CONFIG::RsvdBits1
UINT32 RsvdBits1
Reserved Bits.
Definition: HsioPcieConfig.h:70
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:46 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: HsioSataConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hsio
Classes
HsioSataConfig.h File Reference

Hsio Sata policy. More...

Go to the source code of this file.

Classes

struct | PCH_HSIO_SATA_PORT_LANE
The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane. More...
struct | PCH_HSIO_SATA_PREMEM_CONFIG
The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the SATA controller. More...

Detailed Description

Hsio Sata policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HsioSataConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: HsioSataConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hsio
HsioSataConfig.h
Go to the documentation of this file.
1 /** @file
2 Hsio Sata policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _HSIO_SATA_CONFIG_H_
36 #define _HSIO_SATA_CONFIG_H_
37
38 #define PCH_HSIO_SATA_PREMEM_CONFIG_REVISION 1
39 extern EFI_GUID gHsioSataPreMemConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane
45 **/
46 typedef struct {
47 //
48 // HSIO Rx Eq
49 //
50 UINT32 HsioRxGen1EqBoostMagEnable : 1; ///< <b>0: Disable</b>; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
51 UINT32 HsioRxGen1EqBoostMag : 6; ///< SATA 1.5 Gb/sReceiver Equalization Boost Magnitude Adjustment value
52 UINT32 HsioRxGen2EqBoostMagEnable : 1; ///< <b>0: Disable</b>; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
53 UINT32 HsioRxGen2EqBoostMag : 6; ///< SATA 3.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value
54 UINT32 HsioRxGen3EqBoostMagEnable : 1; ///< <b>0: Disable</b>; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
55 UINT32 HsioRxGen3EqBoostMag : 6; ///< SATA 6.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value
56 //
57 // HSIO Tx Eq
58 //
59 UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
60 UINT32 HsioTxGen1DownscaleAmp : 6; ///< SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
61 UINT32 RsvdBits0 : 4; ///< Reserved bits
62
63 UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
64 UINT32 HsioTxGen2DownscaleAmp : 6; ///< SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment
65 UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
66 UINT32 HsioTxGen3DownscaleAmp : 6; ///< SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment
67 UINT32 HsioTxGen1DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
68 UINT32 HsioTxGen1DeEmph : 6; ///< SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
69
70 UINT32 HsioTxGen2DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
71 UINT32 HsioTxGen2DeEmph : 6; ///< SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
72 UINT32 RsvdBits1 : 4; ///< Reserved bits
73
74 UINT32 HsioTxGen3DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
75 UINT32 HsioTxGen3DeEmph : 6; ///< SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
76 UINT32 RsvdBits2 : 25; ///< Reserved bits
77 } PCH_HSIO_SATA_PORT_LANE;
78
79 ///
80 /// The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the SATA controller.
81 ///
82 typedef struct {
83 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
84 ///
85 /// These members describe the configuration of HSIO for SATA lanes.
86 ///
87 PCH_HSIO_SATA_PORT_LANE PortLane[PCH_MAX_SATA_PORTS];
88 } PCH_HSIO_SATA_PREMEM_CONFIG;
89
90 #pragma pack (pop)
91
92 #endif // _HSIO_SATA_CONFIG_H_
PCH_HSIO_SATA_PORT_LANE
The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane.
Definition: HsioSataConfig.h:46
PCH_HSIO_SATA_PORT_LANE::HsioTxGen2DownscaleAmp
UINT32 HsioTxGen2DownscaleAmp
SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment.
Definition: HsioSataConfig.h:64
PCH_HSIO_SATA_PORT_LANE::HsioTxGen2DeEmphEnable
UINT32 HsioTxGen2DeEmphEnable
0: Disable; 1: Enable SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
Definition: HsioSataConfig.h:70
PCH_HSIO_SATA_PORT_LANE::HsioTxGen3DeEmph
UINT32 HsioTxGen3DeEmph
SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override.
Definition: HsioSataConfig.h:75
PCH_HSIO_SATA_PORT_LANE::RsvdBits2
UINT32 RsvdBits2
Reserved bits.
Definition: HsioSataConfig.h:76
PCH_HSIO_SATA_PORT_LANE::HsioTxGen1DeEmphEnable
UINT32 HsioTxGen1DeEmphEnable
0: Disable; 1: Enable SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
Definition: HsioSataConfig.h:67
PCH_HSIO_SATA_PORT_LANE::HsioRxGen2EqBoostMagEnable
UINT32 HsioRxGen2EqBoostMagEnable
0: Disable; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
Definition: HsioSataConfig.h:52
PCH_HSIO_SATA_PORT_LANE::RsvdBits1
UINT32 RsvdBits1
Reserved bits.
Definition: HsioSataConfig.h:72
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_HSIO_SATA_PORT_LANE::HsioRxGen3EqBoostMag
UINT32 HsioRxGen3EqBoostMag
SATA 6.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value.
Definition: HsioSataConfig.h:55
PCH_HSIO_SATA_PORT_LANE::HsioTxGen1DeEmph
UINT32 HsioTxGen1DeEmph
SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.
Definition: HsioSataConfig.h:68
PCH_HSIO_SATA_PORT_LANE::HsioTxGen1DownscaleAmp
UINT32 HsioTxGen1DownscaleAmp
SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.
Definition: HsioSataConfig.h:60
PCH_HSIO_SATA_PORT_LANE::HsioTxGen1DownscaleAmpEnable
UINT32 HsioTxGen1DownscaleAmpEnable
0: Disable; 1: Enable SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
Definition: HsioSataConfig.h:59
PCH_HSIO_SATA_PORT_LANE::HsioRxGen1EqBoostMag
UINT32 HsioRxGen1EqBoostMag
SATA 1.5 Gb/sReceiver Equalization Boost Magnitude Adjustment value.
Definition: HsioSataConfig.h:51
PCH_HSIO_SATA_PORT_LANE::HsioTxGen3DeEmphEnable
UINT32 HsioTxGen3DeEmphEnable
0: Disable; 1: Enable SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
Definition: HsioSataConfig.h:74
PCH_HSIO_SATA_PORT_LANE::HsioTxGen2DownscaleAmpEnable
UINT32 HsioTxGen2DownscaleAmpEnable
0: Disable; 1: Enable SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
Definition: HsioSataConfig.h:63
PCH_HSIO_SATA_PORT_LANE::HsioTxGen3DownscaleAmpEnable
UINT32 HsioTxGen3DownscaleAmpEnable
0: Disable; 1: Enable SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
Definition: HsioSataConfig.h:65
PCH_HSIO_SATA_PORT_LANE::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: HsioSataConfig.h:61
PCH_HSIO_SATA_PORT_LANE::HsioRxGen1EqBoostMagEnable
UINT32 HsioRxGen1EqBoostMagEnable
0: Disable; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
Definition: HsioSataConfig.h:50
PCH_HSIO_SATA_PORT_LANE::HsioRxGen2EqBoostMag
UINT32 HsioRxGen2EqBoostMag
SATA 3.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value.
Definition: HsioSataConfig.h:53
PCH_HSIO_SATA_PORT_LANE::HsioTxGen2DeEmph
UINT32 HsioTxGen2DeEmph
SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.
Definition: HsioSataConfig.h:71
PCH_HSIO_SATA_PORT_LANE::HsioRxGen3EqBoostMagEnable
UINT32 HsioRxGen3EqBoostMagEnable
0: Disable; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
Definition: HsioSataConfig.h:54
PCH_HSIO_SATA_PREMEM_CONFIG
The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the SATA controller.
Definition: HsioSataConfig.h:82
PCH_HSIO_SATA_PORT_LANE::HsioTxGen3DownscaleAmp
UINT32 HsioTxGen3DownscaleAmp
SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment.
Definition: HsioSataConfig.h:66
PCH_HSIO_SATA_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: HsioSataConfig.h:83
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:46 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: HybridGraphicsConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HybridGraphics
Macros
HybridGraphicsConfig.h File Reference

Hybrid Graphics policy definitions. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define HYBRID_GRAPHICS_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Detailed Description

Hybrid Graphics policy definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HybridGraphicsConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: HybridGraphicsConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HybridGraphics
HybridGraphicsConfig.h
Go to the documentation of this file.
1 /** @file
2 Hybrid Graphics policy definitions
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _HYBRID_GRAPHICS_CONFIG_H_
36 #define _HYBRID_GRAPHICS_CONFIG_H_
37
38 /**
39 Making any structure change after API Lock
40 will need to maintain backward compatibility, bump up
41 structure revision and update below history table\n
42 <b>Revision 1</b>: - Initial version.
43 **/
44 #define HYBRID_GRAPHICS_CONFIG_REVISION 1
45
46 #pragma pack(push, 1)
47 typedef struct {
48 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
49 UINT16 HgSubSystemId; ///< Offset 54 Hybrid Graphics Subsystem ID: <b>2212</b>
50 UINT16 Reserved;
51 } HYBRID_GRAPHICS_CONFIG;
52 #pragma pack(pop)
53 #endif // _HYBRID_GRAPHICS_CONFIG_H_
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: IehConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ieh
Classes
IehConfig.h File Reference

Integrated Error Handler policy. More...

#include <ConfigBlock.h>
Include dependency graph for IehConfig.h:

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Classes

struct IEH_CONFIG
The IEH_CONFIG block describes the expected configuration of the PCH Integrated Error Handler. More...

Detailed Description

Integrated Error Handler policy.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file IehConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: IehConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ieh
IehConfig.h
Go to the documentation of this file.
1 /** @file
2 Integrated Error Handler policy.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _IEH_CONFIG_H_
37 #define _IEH_CONFIG_H_
38
39 #include <ConfigBlock.h>
40
41 #define IEH_MODE_BYPASS 0
42 #define IEH_MODE_ENABLE 1
43
44 #define IEH_CONFIG_REVISION 1
45 extern EFI_GUID gIehConfigGuid;
46
47 #pragma pack (push,1)
48
49 /**
50 The IEH_CONFIG block describes the expected configuration of the PCH
51 Integrated Error Handler.
52 **/
53 typedef struct {
54 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
55 /**
56 IEH mode <b>0: Bypass Mode</b>; 1: Enable
57 **/
58 UINT32 Mode : 1;
59 UINT32 RsvdBits0 : 31; ///< Reserved bits
60 } IEH_CONFIG;
61
62 #pragma pack (pop)
63
64 #endif // _IEH_CONFIG_H_
ConfigBlock.h
Header file for Config Block Lib implementation.
IEH_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: IehConfig.h:59
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
IEH_CONFIG
The IEH_CONFIG block describes the expected configuration of the PCH Integrated Error Handler.
Definition: IehConfig.h:53
IEH_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: IehConfig.h:54
IEH_CONFIG::Mode
UINT32 Mode
IEH mode 0: Bypass Mode; 1: Enable.
Definition: IehConfig.h:58
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: InterruptConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Itss
Classes | Macros | Enumerations
InterruptConfig.h File Reference

Interrupt policy. More...

#include <ConfigBlock.h>
Include dependency graph for InterruptConfig.h:

Go to the source code of this file.

Classes

struct | PCH_DEVICE_INTERRUPT_CONFIG
The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. More...
struct | PCH_INTERRUPT_CONFIG
The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH. More...

Macros

#define | PCH_MAX_DEVICE_INTERRUPT_CONFIG 128
Number of all PCH devices.
#define | PCH_MAX_PXRC_CONFIG 8
Number of PXRC registers in ITSS.
#define | PCH_MAX_ITSS_IPC_REGS 4
Number of IPC registers in ITSS.
#define | PCH_MAX_ITSS_IRQ_NUM 120
Maximum number of IRQs.

Enumerations

enum PCH_INT_PIN

Detailed Description

Interrupt policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file InterruptConfig.h.

Enumeration Type Documentation

◆ PCH_INT_PIN

enum PCH_INT_PIN
Enumerator
PchNoInt

No Interrupt Pin.

Definition at line 48 of file InterruptConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: InterruptConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Itss
InterruptConfig.h
Go to the documentation of this file.
1 /** @file
2 Interrupt policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _INTERRUPT_CONFIG_H_
36 #define _INTERRUPT_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 #define PCH_INTERRUPT_CONFIG_REVISION 1
41 extern EFI_GUID gInterruptConfigGuid;
42
43 #pragma pack (push,1)
44
45 //
46 // --------------------- Interrupts Config ------------------------------
47 //
48 typedef enum {
49 PchNoInt, ///< No Interrupt Pin
50 PchIntA,
51 PchIntB,
52 PchIntC,
53 PchIntD
54 } PCH_INT_PIN;
55
56 ///
57 /// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
58 ///
59 typedef struct {
60 UINT8 Device; ///< Device number
61 UINT8 Function; ///< Device function
62 UINT8 IntX; ///< Interrupt pin: INTA-INTD (see PCH_INT_PIN)
63 UINT8 Irq; ///< IRQ to be set for device.
64 } PCH_DEVICE_INTERRUPT_CONFIG;
65
66 #define PCH_MAX_DEVICE_INTERRUPT_CONFIG 128 ///< Number of all PCH devices
67 #define PCH_MAX_PXRC_CONFIG 8 ///< Number of PXRC registers in ITSS
68 #define PCH_MAX_ITSS_IPC_REGS 4 ///< Number of IPC registers in ITSS
69 #define PCH_MAX_ITSS_IRQ_NUM 120 ///< Maximum number of IRQs
70
71
72 ///
73 /// The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH.
74 ///
75 typedef struct {
76 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
77 UINT8 NumOfDevIntConfig; ///< Number of entries in DevIntConfig table
78 UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4.
79 PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFIG]; ///< Array which stores PCH devices interrupts settings
80 UINT8 GpioIrqRoute; ///< Interrupt routing for GPIO. Default is <b>14</b>.
81 UINT8 SciIrqSelect; ///< Interrupt select for SCI. Default is <b>9</b>.
82 UINT8 TcoIrqSelect; ///< Interrupt select for TCO. Default is <b>9</b>.
83 UINT8 TcoIrqEnable; ///< Enable IRQ generation for TCO. <b>0: Disable</b>; 1: Enable.
84 } PCH_INTERRUPT_CONFIG;
85
86 #pragma pack (pop)
87
88 #endif // _INTERRUPT_CONFIG_H_
ConfigBlock.h
Header file for Config Block Lib implementation.
PCH_DEVICE_INTERRUPT_CONFIG::Function
UINT8 Function
Device function.
Definition: InterruptConfig.h:61
PCH_INTERRUPT_CONFIG::TcoIrqEnable
UINT8 TcoIrqEnable
Enable IRQ generation for TCO. 0: Disable; 1: Enable.
Definition: InterruptConfig.h:83
PCH_DEVICE_INTERRUPT_CONFIG::IntX
UINT8 IntX
Interrupt pin: INTA-INTD (see PCH_INT_PIN)
Definition: InterruptConfig.h:62
PCH_INTERRUPT_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: InterruptConfig.h:76
PCH_DEVICE_INTERRUPT_CONFIG::Irq
UINT8 Irq
IRQ to be set for device.
Definition: InterruptConfig.h:63
PCH_DEVICE_INTERRUPT_CONFIG::Device
UINT8 Device
Device number.
Definition: InterruptConfig.h:60
PCH_MAX_DEVICE_INTERRUPT_CONFIG
#define PCH_MAX_DEVICE_INTERRUPT_CONFIG
Number of all PCH devices.
Definition: InterruptConfig.h:66
PCH_DEVICE_INTERRUPT_CONFIG
The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
Definition: InterruptConfig.h:59
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_INTERRUPT_CONFIG::NumOfDevIntConfig
UINT8 NumOfDevIntConfig
Number of entries in DevIntConfig table.
Definition: InterruptConfig.h:77
PCH_INT_PIN
PCH_INT_PIN
Definition: InterruptConfig.h:48
PCH_INTERRUPT_CONFIG::TcoIrqSelect
UINT8 TcoIrqSelect
Interrupt select for TCO. Default is 9.
Definition: InterruptConfig.h:82
PCH_INTERRUPT_CONFIG::GpioIrqRoute
UINT8 GpioIrqRoute
Interrupt routing for GPIO. Default is 14.
Definition: InterruptConfig.h:80
PchNoInt
@ PchNoInt
No Interrupt Pin.
Definition: InterruptConfig.h:49
PCH_INTERRUPT_CONFIG::SciIrqSelect
UINT8 SciIrqSelect
Interrupt select for SCI. Default is 9.
Definition: InterruptConfig.h:81
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
PCH_INTERRUPT_CONFIG
The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH.
Definition: InterruptConfig.h:75
Generated on Mon Dec 29 2025 02:15:46 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: IoApicConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Itss
Classes
IoApicConfig.h File Reference

IoApic policy. More...

Go to the source code of this file.

Classes

struct PCH_IOAPIC_CONFIG
The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is not TRUE. More...

Detailed Description

IoApic policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file IoApicConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: IoApicConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Itss
IoApicConfig.h
Go to the documentation of this file.
1 /** @file
2 IoApic policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _IOAPIC_CONFIG_H_
36 #define _IOAPIC_CONFIG_H_
37
38 #define PCH_IOAPIC_CONFIG_REVISION 1
39 extern EFI_GUID gIoApicConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH
45 IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is
46 not TRUE. Bus:device:function fields will be programmed to the register
47 P2SB IBDF(P2SB PCI offset R6Ch-6Dh), it's using for the following purpose:
48 As the Requester ID when initiating Interrupt Messages to the processor.
49 As the Completer ID when responding to the reads targeting the IOxAPI's
50 Memory-Mapped I/O registers.
51 This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can
52 program this field to provide a unique Bus:Device:Function number for the
53 internal IOxAPIC.
54 The address resource range of IOAPIC must be reserved in E820 and ACPI as
55 system resource.
56 **/
57 typedef struct {
58 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
59 UINT32 IoApicEntry24_119 : 1; ///< 0: Disable; <b>1: Enable</b> IOAPIC Entry 24-119
60 /**
61 Enable 8254 Static Clock Gating during early POST time. 0: Disable, <b>1: Enable</b>
62 Setting 8254CGE is required to support SLP_S0.
63 Enable this if 8254 timer is not used.
64 However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer.
65 Make sure it is disabled to support legacy OS using 8254 timer.
66 @note:
67 For some OS environment that it needs to set 8254CGE in late state it should
68 set this policy to FALSE and use ItssSet8254ClockGateState (TRUE) in SMM later.
69 This is also required during S3 resume.
70 To avoid SMI requirement in S3 reusme path, it can enable the Enable8254ClockGatingOnS3
71 and RC will do 8254 CGE programming in PEI during S3 resume with BOOT_SAI.
72 **/
73 UINT32 Enable8254ClockGating : 1;
74 /**
75 Enable 8254 Static Clock Gating on S3 resume path. 0: Disable, <b>1: Enable</b>
76 This is only applicable when Enable8254ClockGating is disabled.
77 If Enable8254ClockGating is enabled, RC will do the 8254 CGE programming on
78 S3 resume path as well.
79 **/
80 UINT32 Enable8254ClockGatingOnS3 : 1;
81 UINT32 RsvdBits1 : 29; ///< Reserved bits
82 UINT8 IoApicId; ///< This member determines IOAPIC ID. Default is <b>0x02</b>.
83 UINT8 Rsvd0[3]; ///< Reserved bytes
84 } PCH_IOAPIC_CONFIG;
85
86 #pragma pack (pop)
87
88 #endif // _IOAPIC_CONFIG_H_
PCH_IOAPIC_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: IoApicConfig.h:58
PCH_IOAPIC_CONFIG::IoApicId
UINT8 IoApicId
This member determines IOAPIC ID. Default is 0x02.
Definition: IoApicConfig.h:82
PCH_IOAPIC_CONFIG::IoApicEntry24_119
UINT32 IoApicEntry24_119
0: Disable; 1: Enable IOAPIC Entry 24-119
Definition: IoApicConfig.h:59
PCH_IOAPIC_CONFIG::Enable8254ClockGating
UINT32 Enable8254ClockGating
Enable 8254 Static Clock Gating during early POST time.
Definition: IoApicConfig.h:73
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_IOAPIC_CONFIG::RsvdBits1
UINT32 RsvdBits1
Reserved bits.
Definition: IoApicConfig.h:81
PCH_IOAPIC_CONFIG::Enable8254ClockGatingOnS3
UINT32 Enable8254ClockGatingOnS3
Enable 8254 Static Clock Gating on S3 resume path.
Definition: IoApicConfig.h:80
PCH_IOAPIC_CONFIG
The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH IO APIC,...
Definition: IoApicConfig.h:57
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:46 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: IpuPreMemConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ipu
Classes
IpuPreMemConfig.h File Reference

IPU policy definitions. More...

#include <ConfigBlock.h>
Include dependency graph for IpuPreMemConfig.h:

Go to the source code of this file.

Classes

struct IPU_PREMEM_CONFIG
IPU PreMem configuration
Revision 1: More...

Detailed Description

IPU policy definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file IpuPreMemConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: IpuPreMemConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ipu
IpuPreMemConfig.h
Go to the documentation of this file.
1 /** @file
2 IPU policy definitions
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _IPU_CONFIG_PREMEM_H_
36 #define _IPU_CONFIG_PREMEM_H_
37
38 #pragma pack(push, 1)
39 #include <ConfigBlock.h>
40
41 #define IPU_PREMEM_CONFIG_REVISION 1
42
43 //
44 // GPIO native features pins data
45 //
46 #define GPIO_IMGUCLK_NUMBER_OF_PINS 6
47
48 //
49 // Maximum CSI (Camera Serial Interface) Port
50 //
51 #define MAX_CSI_PORT 8
52
53 // @todo file name will be changed to IpuConfig.h.
54
55 extern EFI_GUID gIpuPreMemConfigGuid;
56
57 /**
58 IPU PreMem configuration\n
59 <b>Revision 1</b>:
60 - Initial version.
61 **/
62 typedef struct {
63 CONFIG_BLOCK_HEADER Header; /// Config Block Header
64 /**
65 <b>(Test)</b> It enables the SA IPU Device if supported and not fused off.
66 If FALSE, all other policies in this config block will be ignored.
67 <b>1=TRUE</b>;
68 0=FALSE.
69 **/
70 UINT8 IpuEnable;
71 /**
72 It enable the IMGU CLKOUT.
73 <b>TRUE</b>
74 FALSE
75 **/
76 UINT8 ImguClkOutEn[GPIO_IMGUCLK_NUMBER_OF_PINS];
77 UINT8 Rsvd[5]; ///< Reserved for future use
78
79 } IPU_PREMEM_CONFIG;
80 #pragma pack(pop)
81
82 #endif // _IPU_PREMEM_CONFIG_H_
ConfigBlock.h
Header file for Config Block Lib implementation.
IPU_PREMEM_CONFIG
IPU PreMem configuration Revision 1:
Definition: IpuPreMemConfig.h:62
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
IPU_PREMEM_CONFIG::IpuEnable
UINT8 IpuEnable
Config Block Header.
Definition: IpuPreMemConfig.h:70
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:46 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: IshConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ish
Classes | Macros
IshConfig.h File Reference

ISH policy. More...

Go to the source code of this file.

Classes

struct | ISH_GPIO_CONFIG
ISH GPIO settings. More...
struct | ISH_SPI_PIN_CONFIG
SPI signals settings. More...
struct | ISH_UART_PIN_CONFIG
UART signals settings. More...
struct | ISH_I2C_PIN_CONFIG
I2C signals settings. More...
struct | ISH_SPI
Struct contains GPIO pins assigned and signal settings of SPI. More...
struct | ISH_UART
Struct contains GPIO pins assigned and signal settings of UART. More...
struct | ISH_I2C
Struct contains GPIO pins assigned and signal settings of I2C. More...
struct | ISH_GP
Struct contains GPIO pins assigned and signal settings of GP. More...
struct | ISH_CONFIG
The ISH_CONFIG block describes Integrated Sensor Hub device. More...
struct | ISH_I3C_CONFIG
The ISH_I3C_CONFIG block describes I3C in ISH device. More...
struct | ISH_PREMEM_CONFIG
Premem Policy for Integrated Sensor Hub device. More...

Macros

#define | ISH_PREMEM_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.
#define | ISH_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.
#define | ISH_I3C_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Detailed Description

ISH policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file IshConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: IshConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ish
IshConfig.h
Go to the documentation of this file.
1 /** @file
2 ISH policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ISH_CONFIG_H_
36 #define _ISH_CONFIG_H_
37
38 /**
39 Making any structure change after API Lock
40 will need to maintain backward compatibility, bump up
41 structure revision and update below history table\n
42 <b>Revision 1</b>: - Initial version.
43 **/
44 #define ISH_PREMEM_CONFIG_REVISION 1
45 /**
46 Making any structure change after API Lock
47 will need to maintain backward compatibility, bump up
48 structure revision and update below history table\n
49 <b>Revision 1</b>: - Initial version.
50 **/
51 #define ISH_CONFIG_REVISION 1
52 /**
53 Making any structure change after API Lock
54 will need to maintain backward compatibility, bump up
55 structure revision and update below history table\n
56 <b>Revision 1</b>: - Initial version.
57 **/
58 #define ISH_I3C_CONFIG_REVISION 1
59 extern EFI_GUID gIshPreMemConfigGuid;
60 extern EFI_GUID gIshConfigGuid;
61 extern EFI_GUID gIshI3cConfigGuid;
62
63 #pragma pack (push,1)
64
65 /**
66 ISH GPIO settings
67 **/
68 typedef struct {
69 /**
70 GPIO signals pin muxing settings. If signal can be enable only on a single pin
71 then this parameter should be set to 0. Refer to GPIO_*_MUXING_ISH_*x_* in GpioPins*.h
72 for supported settings on a given platform
73 **/
74 UINT32 PinMux; ///< GPIO Pin mux configuration. Refer to GPIO_*_MUXING_ISH_*x_MOSI_*
75 /**
76 GPIO Pads Internal Termination.
77 For more information please see Platform Design Guide.
78 Check GPIO_ELECTRICAL_CONFIG for reference
79 **/
80 UINT32 PadTermination;
81 } ISH_GPIO_CONFIG;
82
83 /**
84 SPI signals settings.
85 **/
86 typedef struct {
87 ISH_GPIO_CONFIG Mosi; ///< MOSI Pin configuration.
88 ISH_GPIO_CONFIG Miso; ///< MISO Pin configuration.
89 ISH_GPIO_CONFIG Clk; ///< CLK Pin configuration.
90 ISH_GPIO_CONFIG Cs[PCH_MAX_ISH_SPI_CS_PINS]; ///< CS Pin configuration.
91 } ISH_SPI_PIN_CONFIG;
92
93
94 /**
95 UART signals settings.
96 **/
97 typedef struct {
98 ISH_GPIO_CONFIG Rx; ///< RXD Pin configuration.
99 ISH_GPIO_CONFIG Tx; ///< TXD Pin configuration.
100 ISH_GPIO_CONFIG Rts; ///< RTS Pin configuration.
101 ISH_GPIO_CONFIG Cts; ///< CTS Pin configuration.
102 } ISH_UART_PIN_CONFIG;
103
104
105 /**
106 I2C signals settings.
107 **/
108 typedef struct {
109 ISH_GPIO_CONFIG Sda; ///< SDA Pin configuration.
110 ISH_GPIO_CONFIG Scl; ///< SCL Pin configuration.
111 } ISH_I2C_PIN_CONFIG;
112
113
114 /**
115 Struct contains GPIO pins assigned and signal settings of SPI
116 **/
117 typedef struct {
118 UINT8 Enable; ///< ISH SPI GPIO pins assigned: <b>0: False</b> 1: True
119 UINT8 CsEnable[PCH_MAX_ISH_SPI_CS_PINS]; ///< ISH SPI CS pins assigned: <b>0: False</b> 1: True
120 UINT16 RsvdField0; ///< Reserved field
121 ISH_SPI_PIN_CONFIG PinConfig;
122 } ISH_SPI;
123
124
125 /**
126 Struct contains GPIO pins assigned and signal settings of UART
127 **/
128 typedef struct {
129 UINT32 Enable : 1; ///< ISH UART GPIO pins assigned: <b>0: False</b> 1: True
130 UINT32 RsvdBits0 : 31; ///< Reserved Bits
131 ISH_UART_PIN_CONFIG PinConfig;
132 } ISH_UART;
133
134 /**
135 Struct contains GPIO pins assigned and signal settings of I2C
136 **/
137 typedef struct {
138 UINT32 Enable : 1; ///< ISH I2C GPIO pins assigned: <b>0: False</b> 1: True
139 UINT32 RsvdBits0 : 31; ///< Reserved Bits
140 ISH_I2C_PIN_CONFIG PinConfig;
141 } ISH_I2C;
142
143 /**
144 Struct contains GPIO pins assigned and signal settings of GP
145 **/
146 typedef struct {
147 UINT32 Enable : 1; ///< ISH GP GPIO pins assigned: <b>0: False</b> 1: True
148 UINT32 RsvdBits0 : 31; ///< Reserved Bits
149 ISH_GPIO_CONFIG PinConfig;
150 } ISH_GP;
151
152 ///
153 /// The ISH_CONFIG block describes Integrated Sensor Hub device.
154 ///
155 typedef struct {
156 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
157 ISH_SPI Spi[PCH_MAX_ISH_SPI_CONTROLLERS];
158 ISH_UART Uart[PCH_MAX_ISH_UART_CONTROLLERS];
159 ISH_I2C I2c[PCH_MAX_ISH_I2C_CONTROLLERS];
160 ISH_GP Gp[PCH_MAX_ISH_GP_PINS];
161
162 UINT32 PdtUnlock : 1; ///< ISH PDT Unlock Msg: <b>0: False</b> 1: True
163 UINT32 MsiInterrupt : 1; ///< ISH MSI Interrupts: <b>0: False</b> 1: True
164 UINT32 RsvdBits0 : 30; ///< Reserved Bits
165 } ISH_CONFIG;
166
167 typedef ISH_I2C ISH_I3C;
168 ///
169 /// The ISH_I3C_CONFIG block describes I3C in ISH device.
170 ///
171 typedef struct {
172 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
173
174 ISH_I3C Controller; ///< ISH I3C Controller
175 } ISH_I3C_CONFIG;
176
177 ///
178 /// Premem Policy for Integrated Sensor Hub device.
179 ///
180 typedef struct {
181 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
182 /**
183 ISH Controler 0: Disable; <b>1: Enable</b>.
184 For Desktop sku, the ISH POR should be disabled. <b> 0:Disable </b>.
185 **/
186 UINT32 Enable : 1;
187 UINT32 RsvdBits0 : 31; ///< Reserved Bits
188 } ISH_PREMEM_CONFIG;
189
190 #pragma pack (pop)
191
192 #endif // _ISH_CONFIG_H_
ISH_PREMEM_CONFIG
Premem Policy for Integrated Sensor Hub device.
Definition: IshConfig.h:180
ISH_I3C_CONFIG
The ISH_I3C_CONFIG block describes I3C in ISH device.
Definition: IshConfig.h:171
ISH_SPI::Enable
UINT8 Enable
ISH SPI GPIO pins assigned: 0: False 1: True.
Definition: IshConfig.h:118
ISH_UART::RsvdBits0
UINT32 RsvdBits0
Reserved Bits.
Definition: IshConfig.h:130
ISH_I2C_PIN_CONFIG::Sda
ISH_GPIO_CONFIG Sda
SDA Pin configuration.
Definition: IshConfig.h:109
ISH_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved Bits.
Definition: IshConfig.h:164
ISH_I2C
Struct contains GPIO pins assigned and signal settings of I2C.
Definition: IshConfig.h:137
ISH_UART_PIN_CONFIG::Cts
ISH_GPIO_CONFIG Cts
CTS Pin configuration.
Definition: IshConfig.h:101
ISH_GPIO_CONFIG::PadTermination
UINT32 PadTermination
GPIO Pads Internal Termination.
Definition: IshConfig.h:80
ISH_UART_PIN_CONFIG::Rx
ISH_GPIO_CONFIG Rx
RXD Pin configuration.
Definition: IshConfig.h:98
ISH_GP
Struct contains GPIO pins assigned and signal settings of GP.
Definition: IshConfig.h:146
ISH_I2C::Enable
UINT32 Enable
ISH I2C GPIO pins assigned: 0: False 1: True.
Definition: IshConfig.h:138
ISH_UART_PIN_CONFIG
UART signals settings.
Definition: IshConfig.h:97
ISH_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: IshConfig.h:156
ISH_GPIO_CONFIG::PinMux
UINT32 PinMux
GPIO signals pin muxing settings.
Definition: IshConfig.h:74
ISH_GP::RsvdBits0
UINT32 RsvdBits0
Reserved Bits.
Definition: IshConfig.h:148
ISH_UART::Enable
UINT32 Enable
ISH UART GPIO pins assigned: 0: False 1: True.
Definition: IshConfig.h:129
ISH_GP::Enable
UINT32 Enable
ISH GP GPIO pins assigned: 0: False 1: True.
Definition: IshConfig.h:147
ISH_I2C::RsvdBits0
UINT32 RsvdBits0
Reserved Bits.
Definition: IshConfig.h:139
ISH_SPI::RsvdField0
UINT16 RsvdField0
Reserved field.
Definition: IshConfig.h:120
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
ISH_SPI
Struct contains GPIO pins assigned and signal settings of SPI.
Definition: IshConfig.h:117
ISH_SPI_PIN_CONFIG::Clk
ISH_GPIO_CONFIG Clk
CLK Pin configuration.
Definition: IshConfig.h:89
ISH_UART
Struct contains GPIO pins assigned and signal settings of UART.
Definition: IshConfig.h:128
ISH_UART_PIN_CONFIG::Tx
ISH_GPIO_CONFIG Tx
TXD Pin configuration.
Definition: IshConfig.h:99
ISH_I2C_PIN_CONFIG
I2C signals settings.
Definition: IshConfig.h:108
ISH_I3C_CONFIG::Controller
ISH_I3C Controller
ISH I3C Controller.
Definition: IshConfig.h:174
ISH_PREMEM_CONFIG::Enable
UINT32 Enable
ISH Controler 0: Disable; 1: Enable.
Definition: IshConfig.h:186
ISH_SPI_PIN_CONFIG
SPI signals settings.
Definition: IshConfig.h:86
ISH_GPIO_CONFIG
ISH GPIO settings.
Definition: IshConfig.h:68
ISH_I2C_PIN_CONFIG::Scl
ISH_GPIO_CONFIG Scl
SCL Pin configuration.
Definition: IshConfig.h:110
ISH_I3C_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: IshConfig.h:172
ISH_CONFIG
The ISH_CONFIG block describes Integrated Sensor Hub device.
Definition: IshConfig.h:155
ISH_PREMEM_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved Bits.
Definition: IshConfig.h:187
ISH_CONFIG::PdtUnlock
UINT32 PdtUnlock
ISH PDT Unlock Msg: 0: False 1: True.
Definition: IshConfig.h:162
ISH_UART_PIN_CONFIG::Rts
ISH_GPIO_CONFIG Rts
RTS Pin configuration.
Definition: IshConfig.h:100
ISH_CONFIG::MsiInterrupt
UINT32 MsiInterrupt
ISH MSI Interrupts: 0: False 1: True.
Definition: IshConfig.h:163
ISH_SPI_PIN_CONFIG::Miso
ISH_GPIO_CONFIG Miso
MISO Pin configuration.
Definition: IshConfig.h:88
ISH_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: IshConfig.h:181
ISH_SPI_PIN_CONFIG::Mosi
ISH_GPIO_CONFIG Mosi
MOSI Pin configuration.
Definition: IshConfig.h:87
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: LpcConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Espi
Classes
LpcConfig.h File Reference

Lpc policy. More...

Go to the source code of this file.

Classes

struct PCH_LPC_PREMEM_CONFIG
This structure contains the policies which are related to LPC. More...

Detailed Description

Lpc policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file LpcConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: LpcConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Espi
LpcConfig.h
Go to the documentation of this file.
1 /** @file
2 Lpc policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _LPC_CONFIG_H_
36 #define _LPC_CONFIG_H_
37
38 #define PCH_LPC_PREMEM_CONFIG_REVISION 1
39 extern EFI_GUID gLpcPreMemConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 This structure contains the policies which are related to LPC.
45 **/
46 typedef struct {
47 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
48 /**
49 Enhance the port 8xh decoding.
50 Original LPC only decodes one byte of port 80h, with this enhancement LPC can decode word or dword of port 80h-83h.
51 @note: this will occupy one LPC generic IO range register. While this is enabled, read from port 80h always return 0x00.
52 0: Disable, <b>1: Enable</b>
53 **/
54 UINT32 EnhancePort8xhDecoding : 1;
55 /**
56 Hardware Autonomous Enable.
57 When enabled, LPC will automatically engage power gating when it has reached its idle condition.
58 0: Disable, <b>1: Enable</b>
59 **/
60 UINT32 LpcPmHAE : 1;
61 UINT32 RsvdBits : 30; ///< Reserved bits
62 } PCH_LPC_PREMEM_CONFIG;
63
64 #pragma pack (pop)
65
66 #endif // _LPC_CONFIG_H_
PCH_LPC_PREMEM_CONFIG
This structure contains the policies which are related to LPC.
Definition: LpcConfig.h:46
PCH_LPC_PREMEM_CONFIG::LpcPmHAE
UINT32 LpcPmHAE
Hardware Autonomous Enable.
Definition: LpcConfig.h:60
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_LPC_PREMEM_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved bits.
Definition: LpcConfig.h:61
PCH_LPC_PREMEM_CONFIG::EnhancePort8xhDecoding
UINT32 EnhancePort8xhDecoding
Enhance the port 8xh decoding.
Definition: LpcConfig.h:54
PCH_LPC_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: LpcConfig.h:47
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: MePeiConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Me
Classes
MePeiConfig.h File Reference

ME config block for PEI phase. More...

#include <Uefi.h>
#include <ConfigBlock.h>
Include dependency graph for MePeiConfig.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | ME_PEI_PREMEM_CONFIG
ME Pei Pre-Memory Configuration Structure. More...
struct | ME_PEI_CONFIG
ME Pei Post-Memory Configuration Structure. More...

Detailed Description

ME config block for PEI phase.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MePeiConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: MePeiConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Me
MePeiConfig.h
Go to the documentation of this file.
1 /** @file
2 ME config block for PEI phase
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ME_PEI_CONFIG_H_
36 #define _ME_PEI_CONFIG_H_
37
38 #include <Uefi.h>
39 #include <ConfigBlock.h>
40
41 #define ME_PEI_PREMEM_CONFIG_REVISION 1
42 extern EFI_GUID gMePeiPreMemConfigGuid;
43
44 #pragma pack (push,1)
45
46 /**
47 ME Pei Pre-Memory Configuration Structure.
48
49 <b>Revision 1:</b>
50 - Initial version.
51 **/
52 typedef struct {
53 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
54 UINT32 HeciTimeouts : 1; ///< 0: Disable; <b>1: Enable</b> - HECI Send/Receive Timeouts.
55 /**
56 <b>(Test)</b>
57 <b>0: Disabled</b>
58 1: ME DID init stat 0 - Success
59 2: ME DID init stat 1 - No Memory in Channels
60 3: ME DID init stat 2 - Memory Init Error
61 **/
62 UINT32 DidInitStat : 2;
63 /**
64 <b>(Test)</b>
65 <b>0: Set to 0 to enable polling for CPU replacement</b>
66 1: Set to 1 will disable polling for CPU replacement
67 **/
68 UINT32 DisableCpuReplacedPolling : 1;
69 /**
70 <b>(Test)</b>
71 <b>0: ME BIOS will check each messages before sending</b>
72 1: ME BIOS always sends messages without checking
73 **/
74 UINT32 DisableMessageCheck : 1;
75 /**
76 <b>(Test)</b>
77 The SkipMbpHob policy determines whether ME BIOS Payload data will be requested during boot.
78 If set to 1, BIOS will not send Get MBP message and not create MBP Hob.
79 <b>0: ME BIOS will send Get MBP message and create HOB for MBP data</b>
80 1: ME BIOS will not send Get MBP message
81 **/
82 UINT32 SkipMbpHob : 1;
83 UINT32 HeciCommunication2 : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Enable - Enable/Disable HECI2.
84 UINT32 KtDeviceEnable : 2; ///< <b>(Test)</b> <b>0: POR</b>; 1: Enable; 2: Disable - Enable/Disable KT Device.
85 UINT32 SkipCpuReplacementCheck : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Enable - Enable/Disable to skip CPU replacement check.
86 UINT32 HeciFullTrace : 1; ///< <b>(Test)</b> 0: Disable; <b>1: Enable</b> - Enable/Disable Full HECI communication information logged to serial
87 UINT32 RsvdBits : 21; ///< Reserved for future use & Config block alignment
88 } ME_PEI_PREMEM_CONFIG;
89 #pragma pack (pop)
90
91
92 #define ME_PEI_CONFIG_REVISION 1
93 extern EFI_GUID gMePeiConfigGuid;
94
95 #pragma pack (push,1)
96
97 /**
98 ME Pei Post-Memory Configuration Structure.
99
100 <b>Revision 1:</b>
101 - Initial version.
102 **/
103
104 typedef struct {
105 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
106
107 UINT32 EndOfPostMessage : 2; ///< 0: Disabled; 1: Send in PEI; <b>2: Send in DXE</b> - Send EOP at specific phase.
108 UINT32 DisableD0I3SettingForHeci : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Enable - Enable/Disable D0i3 for HECI.
109 /**
110 Enable/Disable Me Unconfig On Rtc Clear. If enabled, BIOS will send MeUnconfigOnRtcClearDisable Msg with parameter 0.
111 It will cause ME to unconfig if RTC is cleared.
112 - 0: Disable
113 - <b>1: Enable</b>
114 - 2: Cmos is clear, status unkonwn
115 - 3: Reserved
116 **/
117 UINT32 MeUnconfigOnRtcClear : 2;
118 UINT32 MctpBroadcastCycle : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Enable - Program registers for MCTP Cycle.
119 UINT32 EnforceEDebugMode : 1; ///< <b>0: Disable</b>; 1: Enable - Enforces ME to enter Enhanced Debug Mode
120 UINT32 CseDataResilience : 1; ///< 0: Disable; <b>1: Enable</b> - CSE data resilience support
121 UINT32 RsvdBits : 24; ///< Reserved for future use & Config block alignment
122 } ME_PEI_CONFIG;
123
124 #pragma pack (pop)
125
126 #endif // _ME_PEI_CONFIG_H_
ME_PEI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: MePeiConfig.h:53
ME_PEI_PREMEM_CONFIG::KtDeviceEnable
UINT32 KtDeviceEnable
(Test) 0: POR; 1: Enable; 2: Disable - Enable/Disable KT Device.
Definition: MePeiConfig.h:84
ME_PEI_CONFIG
ME Pei Post-Memory Configuration Structure.
Definition: MePeiConfig.h:104
ConfigBlock.h
Header file for Config Block Lib implementation.
ME_PEI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: MePeiConfig.h:105
ME_PEI_CONFIG::MctpBroadcastCycle
UINT32 MctpBroadcastCycle
(Test) 0: Disable; 1: Enable - Program registers for MCTP Cycle.
Definition: MePeiConfig.h:118
ME_PEI_PREMEM_CONFIG::HeciCommunication2
UINT32 HeciCommunication2
(Test) 0: Disable; 1: Enable - Enable/Disable HECI2.
Definition: MePeiConfig.h:83
ME_PEI_CONFIG::MeUnconfigOnRtcClear
UINT32 MeUnconfigOnRtcClear
Enable/Disable Me Unconfig On Rtc Clear.
Definition: MePeiConfig.h:117
ME_PEI_PREMEM_CONFIG::SkipMbpHob
UINT32 SkipMbpHob
(Test) The SkipMbpHob policy determines whether ME BIOS Payload data will be requested during boot.
Definition: MePeiConfig.h:82
ME_PEI_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use & Config block alignment.
Definition: MePeiConfig.h:121
ME_PEI_PREMEM_CONFIG::DisableCpuReplacedPolling
UINT32 DisableCpuReplacedPolling
(Test) 0: Set to 0 to enable polling for CPU replacement 1: Set to 1 will disable polling for CPU rep...
Definition: MePeiConfig.h:68
ME_PEI_PREMEM_CONFIG
ME Pei Pre-Memory Configuration Structure.
Definition: MePeiConfig.h:52
ME_PEI_PREMEM_CONFIG::HeciTimeouts
UINT32 HeciTimeouts
0: Disable; 1: Enable - HECI Send/Receive Timeouts.
Definition: MePeiConfig.h:54
ME_PEI_CONFIG::CseDataResilience
UINT32 CseDataResilience
0: Disable; 1: Enable - CSE data resilience support
Definition: MePeiConfig.h:120
ME_PEI_PREMEM_CONFIG::SkipCpuReplacementCheck
UINT32 SkipCpuReplacementCheck
(Test) 0: Disable; 1: Enable - Enable/Disable to skip CPU replacement check.
Definition: MePeiConfig.h:85
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
ME_PEI_PREMEM_CONFIG::HeciFullTrace
UINT32 HeciFullTrace
(Test) 0: Disable; 1: Enable - Enable/Disable Full HECI communication information logged to serial
Definition: MePeiConfig.h:86
ME_PEI_CONFIG::EndOfPostMessage
UINT32 EndOfPostMessage
0: Disabled; 1: Send in PEI; 2: Send in DXE - Send EOP at specific phase.
Definition: MePeiConfig.h:107
ME_PEI_CONFIG::EnforceEDebugMode
UINT32 EnforceEDebugMode
0: Disable; 1: Enable - Enforces ME to enter Enhanced Debug Mode
Definition: MePeiConfig.h:119
ME_PEI_PREMEM_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use & Config block alignment.
Definition: MePeiConfig.h:87
ME_PEI_PREMEM_CONFIG::DisableMessageCheck
UINT32 DisableMessageCheck
(Test) 0: ME BIOS will check each messages before sending 1: ME BIOS always sends messages without ch...
Definition: MePeiConfig.h:74
ME_PEI_CONFIG::DisableD0I3SettingForHeci
UINT32 DisableD0I3SettingForHeci
(Test) 0: Disable; 1: Enable - Enable/Disable D0i3 for HECI.
Definition: MePeiConfig.h:108
ME_PEI_PREMEM_CONFIG::DidInitStat
UINT32 DidInitStat
(Test) 0: Disabled 1: ME DID init stat 0 - Success 2: ME DID init stat 1 - No Memory in Channels 3: M...
Definition: MePeiConfig.h:62
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: MpServices.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Edk2
  • MdePkg
  • Include
  • Ppi
Classes | Typedefs
MpServices.h File Reference

This file declares UEFI PI Multi-processor PPI. More...

#include <Protocol/MpService.h>
Include dependency graph for MpServices.h:

Go to the source code of this file.

Classes

struct _EFI_PEI_MP_SERVICES_PPI
This PPI is installed by some platform or chipset-specific PEIM that abstracts handling multiprocessor support. More...

Typedefs

typedef EFI_STATUS(* | EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, OUT UINTN *NumberOfProcessors, OUT UINTN *NumberOfEnabledProcessors)
Get the number of CPU's. More...
typedef EFI_STATUS(* | EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer)
Get information on a specific CPU. More...
typedef EFI_STATUS(* | EFI_PEI_MP_SERVICES_STARTUP_ALL_APS) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_AP_PROCEDURE Procedure, IN BOOLEAN SingleThread, IN UINTN TimeoutInMicroSeconds, IN VOID *ProcedureArgument OPTIONAL)
Activate all of the application processors. More...
typedef EFI_STATUS(* | EFI_PEI_MP_SERVICES_STARTUP_THIS_AP) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_AP_PROCEDURE Procedure, IN UINTN ProcessorNumber, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL)
Activate a specific application processor. More...
typedef EFI_STATUS(* | EFI_PEI_MP_SERVICES_SWITCH_BSP) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableOldBSP)
Switch the boot strap processor. More...
typedef EFI_STATUS(* | EFI_PEI_MP_SERVICES_ENABLEDISABLEAP) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableAP, IN UINT32 *HealthFlag OPTIONAL)
Enable or disable an application processor. More...
typedef EFI_STATUS(* | EFI_PEI_MP_SERVICES_WHOAMI) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, OUT UINTN *ProcessorNumber)
Identify the currently executing processor. More...

Detailed Description

This file declares UEFI PI Multi-processor PPI.

This PPI is installed by some platform or chipset-specific PEIM that abstracts handling multiprocessor support.

Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Revision Reference:
This PPI is introduced in PI Version 1.4.

Definition in file MpServices.h.

Typedef Documentation

◆ EFI_PEI_MP_SERVICES_ENABLEDISABLEAP

typedef EFI_STATUS( * EFI_PEI_MP_SERVICES_ENABLEDISABLEAP) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableAP, IN UINT32 *HealthFlag OPTIONAL)

Enable or disable an application processor.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
[in] | ProcessorNumber | The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
[in] | EnableAP | Specifies the new state for the processor for enabled, FALSE for disabled.
[in] | HealthFlag | If not NULL, a pointer to a value that specifies the new health status of the AP. This flag corresponds to StatusFlag defined in EFI_PEI_MP_SERVICES_PPI.GetProcessorInfo(). Only the PROCESSOR_HEALTH_STATUS_BIT is used. All other bits are ignored. If it is NULL, this parameter is ignored.
Return values
EFI_SUCCESS | The specified AP was enabled or disabled successfully.
EFI_UNSUPPORTED | Enabling or disabling an AP cannot be completed prior to this service returning.
EFI_UNSUPPORTED | Enabling or disabling an AP is not supported.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_NOT_FOUND | Processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the BSP.

Definition at line 229 of file MpServices.h.

◆ EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS

typedef EFI_STATUS( * EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, OUT UINTN *NumberOfProcessors, OUT UINTN *NumberOfEnabledProcessors)

Get the number of CPU's.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to this instance of the PPI.
[out] | NumberOfProcessors | Pointer to the total number of logical processors in the system, including the BSP and disabled APs.
[out] | NumberOfEnabledProcessors | Number of processors in the system that are enabled.
Return values
EFI_SUCCESS | The number of logical processors and enabled logical processors was retrieved.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_INVALID_PARAMETER | NumberOfProcessors is NULL. NumberOfEnabledProcessors is NULL.

Definition at line 44 of file MpServices.h.

◆ EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO

typedef EFI_STATUS( * EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer)

Get information on a specific CPU.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to this instance of the PPI.
[in] | ProcessorNumber | Pointer to the total number of logical processors in the system, including the BSP and disabled APs.
[out] | ProcessorInfoBuffer | Number of processors in the system that are enabled.
Return values
EFI_SUCCESS | Processor information was returned.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_INVALID_PARAMETER | ProcessorInfoBuffer is NULL.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist in the platform.

Definition at line 69 of file MpServices.h.

◆ EFI_PEI_MP_SERVICES_STARTUP_ALL_APS

typedef EFI_STATUS( * EFI_PEI_MP_SERVICES_STARTUP_ALL_APS) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_AP_PROCEDURE Procedure, IN BOOLEAN SingleThread, IN UINTN TimeoutInMicroSeconds, IN VOID *ProcedureArgument OPTIONAL)

Activate all of the application processors.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
[in] | Procedure | A pointer to the function to be run on enabled APs of the system.
[in] | SingleThread | If TRUE, then all the enabled APs execute the function specified by Procedure one by one, in ascending order of processor handle number. If FALSE, then all the enabled APs execute the function specified by Procedure simultaneously.
[in] | TimeoutInMicroSeconds | Indicates the time limit in microseconds for APs to return from Procedure, for blocking mode only. Zero means infinity. If the timeout expires before all APs return from Procedure, then Procedure on the failed APs is terminated. All enabled APs are available for next function assigned by EFI_PEI_MP_SERVICES_PPI.StartupAllAPs() or EFI_PEI_MP_SERVICES_PPI.StartupThisAP(). If the timeout expires in blocking mode, BSP returns EFI_TIMEOUT.
[in] | ProcedureArgument | The parameter passed into Procedure for all APs.
Return values
EFI_SUCCESS | In blocking mode, all APs have finished before the timeout expired.
EFI_DEVICE_ERROR | Caller processor is AP.
EFI_NOT_STARTED | No enabled APs exist in the system.
EFI_NOT_READY | Any enabled APs are busy.
EFI_TIMEOUT | In blocking mode, the timeout expired before all enabled APs have finished.
EFI_INVALID_PARAMETER | Procedure is NULL.

Definition at line 112 of file MpServices.h.

◆ EFI_PEI_MP_SERVICES_STARTUP_THIS_AP

typedef EFI_STATUS( * EFI_PEI_MP_SERVICES_STARTUP_THIS_AP) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_AP_PROCEDURE Procedure, IN UINTN ProcessorNumber, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL)

Activate a specific application processor.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
[in] | Procedure | A pointer to the function to be run on enabled APs of the system.
[in] | ProcessorNumber | The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
[in] | TimeoutInMicroSeconds | Indicates the time limit in microseconds for APs to return from Procedure, for blocking mode only. Zero means infinity. If the timeout expires before all APs return from Procedure, then Procedure on the failed APs is terminated. All enabled APs are available for next function assigned by EFI_PEI_MP_SERVICES_PPI.StartupAllAPs() or EFI_PEI_MP_SERVICES_PPI.StartupThisAP(). If the timeout expires in blocking mode, BSP returns EFI_TIMEOUT.
[in] | ProcedureArgument | The parameter passed into Procedure for all APs.
Return values
EFI_SUCCESS | In blocking mode, specified AP finished before the timeout expires.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_TIMEOUT | In blocking mode, the timeout expired before the specified AP has finished.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the BSP or disabled AP.
EFI_INVALID_PARAMETER | Procedure is NULL.

Definition at line 157 of file MpServices.h.

◆ EFI_PEI_MP_SERVICES_SWITCH_BSP

typedef EFI_STATUS( * EFI_PEI_MP_SERVICES_SWITCH_BSP) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableOldBSP)

Switch the boot strap processor.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
[in] | ProcessorNumber | The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
[in] | EnableOldBSP | If TRUE, then the old BSP will be listed as an enabled AP. Otherwise, it will be disabled.
Return values
EFI_SUCCESS | BSP successfully switched.
EFI_UNSUPPORTED | Switching the BSP cannot be completed prior to this service returning.
EFI_UNSUPPORTED | Switching the BSP is not supported.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the current BSP or a disabled AP.
EFI_NOT_READY | The specified AP is busy.

Definition at line 192 of file MpServices.h.

◆ EFI_PEI_MP_SERVICES_WHOAMI

typedef EFI_STATUS( * EFI_PEI_MP_SERVICES_WHOAMI) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, OUT UINTN *ProcessorNumber)

Identify the currently executing processor.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
[out] | ProcessorNumber | The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
Return values
EFI_SUCCESS | The current processor handle number was returned in ProcessorNumber.
EFI_INVALID_PARAMETER | ProcessorNumber is NULL.

Definition at line 254 of file MpServices.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: MpServices.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Edk2
  • MdePkg
  • Include
  • Ppi
MpServices.h
Go to the documentation of this file.
1 /** @file
2 This file declares UEFI PI Multi-processor PPI.
3 This PPI is installed by some platform or chipset-specific PEIM that abstracts
4 handling multiprocessor support.
5
6 Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
8
9 @par Revision Reference:
10 This PPI is introduced in PI Version 1.4.
11
12 **/
13
14 #ifndef __PEI_MP_SERVICES_PPI_H__
15 #define __PEI_MP_SERVICES_PPI_H__
16
17 #include <Protocol/MpService.h>
18
19 #define EFI_PEI_MP_SERVICES_PPI_GUID \
20 { \
21 0xee16160a, 0xe8be, 0x47a6, { 0x82, 0xa, 0xc6, 0x90, 0xd, 0xb0, 0x25, 0xa } \
22 }
23
24 typedef struct _EFI_PEI_MP_SERVICES_PPI EFI_PEI_MP_SERVICES_PPI;
25
26 /**
27 Get the number of CPU's.
28
29 @param[in] PeiServices An indirect pointer to the PEI Services Table
30 published by the PEI Foundation.
31 @param[in] This Pointer to this instance of the PPI.
32 @param[out] NumberOfProcessors Pointer to the total number of logical processors in
33 the system, including the BSP and disabled APs.
34 @param[out] NumberOfEnabledProcessors
35 Number of processors in the system that are enabled.
36
37 @retval EFI_SUCCESS The number of logical processors and enabled
38 logical processors was retrieved.
39 @retval EFI_DEVICE_ERROR The calling processor is an AP.
40 @retval EFI_INVALID_PARAMETER NumberOfProcessors is NULL.
41 NumberOfEnabledProcessors is NULL.
42 **/
43 typedef
44 EFI_STATUS
45 (EFIAPI *EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS)(
46 IN CONST EFI_PEI_SERVICES **PeiServices,
47 IN EFI_PEI_MP_SERVICES_PPI *This,
48 OUT UINTN *NumberOfProcessors,
49 OUT UINTN *NumberOfEnabledProcessors
50 );
51
52 /**
53 Get information on a specific CPU.
54
55 @param[in] PeiServices An indirect pointer to the PEI Services Table
56 published by the PEI Foundation.
57 @param[in] This Pointer to this instance of the PPI.
58 @param[in] ProcessorNumber Pointer to the total number of logical processors in
59 the system, including the BSP and disabled APs.
60 @param[out] ProcessorInfoBuffer Number of processors in the system that are enabled.
61
62 @retval EFI_SUCCESS Processor information was returned.
63 @retval EFI_DEVICE_ERROR The calling processor is an AP.
64 @retval EFI_INVALID_PARAMETER ProcessorInfoBuffer is NULL.
65 @retval EFI_NOT_FOUND The processor with the handle specified by
66 ProcessorNumber does not exist in the platform.
67 **/
68 typedef
69 EFI_STATUS
70 (EFIAPI *EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO)(
71 IN CONST EFI_PEI_SERVICES **PeiServices,
72 IN EFI_PEI_MP_SERVICES_PPI *This,
73 IN UINTN ProcessorNumber,
74 OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
75 );
76
77 /**
78 Activate all of the application processors.
79
80 @param[in] PeiServices An indirect pointer to the PEI Services Table
81 published by the PEI Foundation.
82 @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
83 @param[in] Procedure A pointer to the function to be run on enabled APs of
84 the system.
85 @param[in] SingleThread If TRUE, then all the enabled APs execute the function
86 specified by Procedure one by one, in ascending order
87 of processor handle number. If FALSE, then all the
88 enabled APs execute the function specified by Procedure
89 simultaneously.
90 @param[in] TimeoutInMicroSeconds
91 Indicates the time limit in microseconds for APs to
92 return from Procedure, for blocking mode only. Zero
93 means infinity. If the timeout expires before all APs
94 return from Procedure, then Procedure on the failed APs
95 is terminated. All enabled APs are available for next
96 function assigned by EFI_PEI_MP_SERVICES_PPI.StartupAllAPs()
97 or EFI_PEI_MP_SERVICES_PPI.StartupThisAP(). If the
98 timeout expires in blocking mode, BSP returns
99 EFI_TIMEOUT.
100 @param[in] ProcedureArgument The parameter passed into Procedure for all APs.
101
102 @retval EFI_SUCCESS In blocking mode, all APs have finished before the
103 timeout expired.
104 @retval EFI_DEVICE_ERROR Caller processor is AP.
105 @retval EFI_NOT_STARTED No enabled APs exist in the system.
106 @retval EFI_NOT_READY Any enabled APs are busy.
107 @retval EFI_TIMEOUT In blocking mode, the timeout expired before all
108 enabled APs have finished.
109 @retval EFI_INVALID_PARAMETER Procedure is NULL.
110 **/
111 typedef
112 EFI_STATUS
113 (EFIAPI *EFI_PEI_MP_SERVICES_STARTUP_ALL_APS)(
114 IN CONST EFI_PEI_SERVICES **PeiServices,
115 IN EFI_PEI_MP_SERVICES_PPI *This,
116 IN EFI_AP_PROCEDURE Procedure,
117 IN BOOLEAN SingleThread,
118 IN UINTN TimeoutInMicroSeconds,
119 IN VOID *ProcedureArgument OPTIONAL
120 );
121
122 /**
123 Activate a specific application processor.
124
125 @param[in] PeiServices An indirect pointer to the PEI Services Table
126 published by the PEI Foundation.
127 @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
128 @param[in] Procedure A pointer to the function to be run on enabled APs of
129 the system.
130 @param[in] ProcessorNumber The handle number of the AP. The range is from 0 to the
131 total number of logical processors minus 1. The total
132 number of logical processors can be retrieved by
133 EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
134 @param[in] TimeoutInMicroSeconds
135 Indicates the time limit in microseconds for APs to
136 return from Procedure, for blocking mode only. Zero
137 means infinity. If the timeout expires before all APs
138 return from Procedure, then Procedure on the failed APs
139 is terminated. All enabled APs are available for next
140 function assigned by EFI_PEI_MP_SERVICES_PPI.StartupAllAPs()
141 or EFI_PEI_MP_SERVICES_PPI.StartupThisAP(). If the
142 timeout expires in blocking mode, BSP returns
143 EFI_TIMEOUT.
144 @param[in] ProcedureArgument The parameter passed into Procedure for all APs.
145
146 @retval EFI_SUCCESS In blocking mode, specified AP finished before the
147 timeout expires.
148 @retval EFI_DEVICE_ERROR The calling processor is an AP.
149 @retval EFI_TIMEOUT In blocking mode, the timeout expired before the
150 specified AP has finished.
151 @retval EFI_NOT_FOUND The processor with the handle specified by
152 ProcessorNumber does not exist.
153 @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the BSP or disabled AP.
154 @retval EFI_INVALID_PARAMETER Procedure is NULL.
155 **/
156 typedef
157 EFI_STATUS
158 (EFIAPI *EFI_PEI_MP_SERVICES_STARTUP_THIS_AP)(
159 IN CONST EFI_PEI_SERVICES **PeiServices,
160 IN EFI_PEI_MP_SERVICES_PPI *This,
161 IN EFI_AP_PROCEDURE Procedure,
162 IN UINTN ProcessorNumber,
163 IN UINTN TimeoutInMicroseconds,
164 IN VOID *ProcedureArgument OPTIONAL
165 );
166
167 /**
168 Switch the boot strap processor.
169
170 @param[in] PeiServices An indirect pointer to the PEI Services Table
171 published by the PEI Foundation.
172 @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
173 @param[in] ProcessorNumber The handle number of the AP. The range is from 0 to the
174 total number of logical processors minus 1. The total
175 number of logical processors can be retrieved by
176 EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
177 @param[in] EnableOldBSP If TRUE, then the old BSP will be listed as an enabled
178 AP. Otherwise, it will be disabled.
179
180 @retval EFI_SUCCESS BSP successfully switched.
181 @retval EFI_UNSUPPORTED Switching the BSP cannot be completed prior to this
182 service returning.
183 @retval EFI_UNSUPPORTED Switching the BSP is not supported.
184 @retval EFI_DEVICE_ERROR The calling processor is an AP.
185 @retval EFI_NOT_FOUND The processor with the handle specified by
186 ProcessorNumber does not exist.
187 @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the current BSP or a disabled
188 AP.
189 @retval EFI_NOT_READY The specified AP is busy.
190 **/
191 typedef
192 EFI_STATUS
193 (EFIAPI *EFI_PEI_MP_SERVICES_SWITCH_BSP)(
194 IN CONST EFI_PEI_SERVICES **PeiServices,
195 IN EFI_PEI_MP_SERVICES_PPI *This,
196 IN UINTN ProcessorNumber,
197 IN BOOLEAN EnableOldBSP
198 );
199
200 /**
201 Enable or disable an application processor.
202
203 @param[in] PeiServices An indirect pointer to the PEI Services Table
204 published by the PEI Foundation.
205 @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
206 @param[in] ProcessorNumber The handle number of the AP. The range is from 0 to the
207 total number of logical processors minus 1. The total
208 number of logical processors can be retrieved by
209 EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
210 @param[in] EnableAP Specifies the new state for the processor for enabled,
211 FALSE for disabled.
212 @param[in] HealthFlag If not NULL, a pointer to a value that specifies the
213 new health status of the AP. This flag corresponds to
214 StatusFlag defined in EFI_PEI_MP_SERVICES_PPI.GetProcessorInfo().
215 Only the PROCESSOR_HEALTH_STATUS_BIT is used. All other
216 bits are ignored. If it is NULL, this parameter is
217 ignored.
218
219 @retval EFI_SUCCESS The specified AP was enabled or disabled successfully.
220 @retval EFI_UNSUPPORTED Enabling or disabling an AP cannot be completed prior
221 to this service returning.
222 @retval EFI_UNSUPPORTED Enabling or disabling an AP is not supported.
223 @retval EFI_DEVICE_ERROR The calling processor is an AP.
224 @retval EFI_NOT_FOUND Processor with the handle specified by ProcessorNumber
225 does not exist.
226 @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the BSP.
227 **/
228 typedef
229 EFI_STATUS
230 (EFIAPI *EFI_PEI_MP_SERVICES_ENABLEDISABLEAP)(
231 IN CONST EFI_PEI_SERVICES **PeiServices,
232 IN EFI_PEI_MP_SERVICES_PPI *This,
233 IN UINTN ProcessorNumber,
234 IN BOOLEAN EnableAP,
235 IN UINT32 *HealthFlag OPTIONAL
236 );
237
238 /**
239 Identify the currently executing processor.
240
241 @param[in] PeiServices An indirect pointer to the PEI Services Table
242 published by the PEI Foundation.
243 @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
244 @param[out] ProcessorNumber The handle number of the AP. The range is from 0 to the
245 total number of logical processors minus 1. The total
246 number of logical processors can be retrieved by
247 EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
248
249 @retval EFI_SUCCESS The current processor handle number was returned in
250 ProcessorNumber.
251 @retval EFI_INVALID_PARAMETER ProcessorNumber is NULL.
252 **/
253 typedef
254 EFI_STATUS
255 (EFIAPI *EFI_PEI_MP_SERVICES_WHOAMI)(
256 IN CONST EFI_PEI_SERVICES **PeiServices,
257 IN EFI_PEI_MP_SERVICES_PPI *This,
258 OUT UINTN *ProcessorNumber
259 );
260
261 ///
262 /// This PPI is installed by some platform or chipset-specific PEIM that abstracts
263 /// handling multiprocessor support.
264 ///
265 struct _EFI_PEI_MP_SERVICES_PPI {
266 EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors;
267 EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO GetProcessorInfo;
268 EFI_PEI_MP_SERVICES_STARTUP_ALL_APS StartupAllAPs;
269 EFI_PEI_MP_SERVICES_STARTUP_THIS_AP StartupThisAP;
270 EFI_PEI_MP_SERVICES_SWITCH_BSP SwitchBSP;
271 EFI_PEI_MP_SERVICES_ENABLEDISABLEAP EnableDisableAP;
272 EFI_PEI_MP_SERVICES_WHOAMI WhoAmI;
273 };
274
275 extern EFI_GUID gEfiPeiMpServicesPpiGuid;
276
277 #endif
EFI_PEI_MP_SERVICES_ENABLEDISABLEAP
EFI_STATUS(* EFI_PEI_MP_SERVICES_ENABLEDISABLEAP)(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableAP, IN UINT32 *HealthFlag OPTIONAL)
Enable or disable an application processor.
Definition: MpServices.h:230
IN
#define IN
Datum is passed to the function.
Definition: Base.h:279
VOID
#define VOID
Undeclared type.
Definition: Base.h:269
EFI_AP_PROCEDURE
VOID(* EFI_AP_PROCEDURE)(IN OUT VOID *Buffer)
The function prototype for invoking a function on an Application Processor.
Definition: PiMultiPhase.h:191
EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS
EFI_STATUS(* EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS)(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, OUT UINTN *NumberOfProcessors, OUT UINTN *NumberOfEnabledProcessors)
Get the number of CPU's.
Definition: MpServices.h:45
OUT
#define OUT
Datum is returned from the function.
Definition: Base.h:284
EFI_STATUS
RETURN_STATUS EFI_STATUS
Function return status for EFI API.
Definition: UefiBaseType.h:29
EFI_PEI_MP_SERVICES_WHOAMI
EFI_STATUS(* EFI_PEI_MP_SERVICES_WHOAMI)(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, OUT UINTN *ProcessorNumber)
Identify the currently executing processor.
Definition: MpServices.h:255
OPTIONAL
#define OPTIONAL
Passing the datum to the function is optional, and a NULL is passed if the value is not supplied.
Definition: Base.h:290
EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO
EFI_STATUS(* EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO)(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer)
Get information on a specific CPU.
Definition: MpServices.h:70
CONST
#define CONST
Datum is read-only.
Definition: Base.h:259
EFI_PEI_MP_SERVICES_STARTUP_ALL_APS
EFI_STATUS(* EFI_PEI_MP_SERVICES_STARTUP_ALL_APS)(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_AP_PROCEDURE Procedure, IN BOOLEAN SingleThread, IN UINTN TimeoutInMicroSeconds, IN VOID *ProcedureArgument OPTIONAL)
Activate all of the application processors.
Definition: MpServices.h:113
EFI_PEI_MP_SERVICES_STARTUP_THIS_AP
EFI_STATUS(* EFI_PEI_MP_SERVICES_STARTUP_THIS_AP)(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_AP_PROCEDURE Procedure, IN UINTN ProcessorNumber, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL)
Activate a specific application processor.
Definition: MpServices.h:158
_EFI_PEI_MP_SERVICES_PPI
This PPI is installed by some platform or chipset-specific PEIM that abstracts handling multiprocesso...
Definition: MpServices.h:265
EFI_PEI_MP_SERVICES_SWITCH_BSP
EFI_STATUS(* EFI_PEI_MP_SERVICES_SWITCH_BSP)(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableOldBSP)
Switch the boot strap processor.
Definition: MpServices.h:193
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: OverclockingConfig.h File Reference

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OverclockingConfig.h File Reference

Overclocking Config Block. More...

#include <CpuLimits.h>
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struct OVERCLOCKING_PREMEM_CONFIG
Overclocking Configuration Structure. More...

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Overclocking Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file OverclockingConfig.h.

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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: OverclockingConfig.h Source File

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OverclockingConfig.h
Go to the documentation of this file.
1 /** @file
2 Overclocking Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _OVERCLOCKING_PREMEM_CONFIG_H_
36 #define _OVERCLOCKING_PREMEM_CONFIG_H_
37
38 #include <CpuLimits.h>
39
40 #define OVERCLOCKING_PREMEM_CONFIG_REVISION 15
41
42 extern EFI_GUID gOverclockingPreMemConfigGuid;
43
44 #pragma pack (push,1)
45
46 //
47 // Max number of VF point offset
48 //
49 #ifndef CPU_OC_MAX_VF_POINTS
50 #define CPU_OC_MAX_VF_POINTS 0xF
51 #endif
52
53 /**
54 Overclocking Configuration Structure.
55
56 <b>Revision 1</b>: - Initial version.
57 <b>Revision 2</b>: - Added ProcessVmaxLimit
58 <b>Revision 3</b>: - Added PcorePowerDensityThrottle
59 <b>Revision 4</b>: - Added MaxVoltageLimit
60 <b>Revision 5</b>: - Added CorePllCurrentRefTuningOffset,RingPllCurrentRefTuningOffset,IaAtomPllCurrentRefTuningOffset
61 <b>Revision 6</b>: - Added CoreMinRatio
62 <b>Revision 7</b>: - Added PerCoreDisableConfiguration
63 <b>Revision 8</b>: - Added NguRatio
64 <b>Revision 9</b>: - Added NpuMaxOcRatio,NpuVoltageMode,NpuVoltageOverride,NpuAdaptiveVoltage,NpuVoltageOffset
65 <b>Revision 10</b>: - Deprecated Avx3RatioOffset and Avx512VoltageScaleFactor
66 <b>Revision 11</b>: - Deprecated RingPllCurrentRefTuningOffset
67 <b>Revision 12</b>: - Added ForcePcoreResidency and VrLimitBypass
68 <b>Revision 13</b>: - Deprecated NpuMaxOcRatio,NpuVoltageMode,NpuVoltageOverride,NpuAdaptiveVoltage,NpuVoltageOffset
69 <b>Revision 14</b>: - Added TurboThermalProtection
70 <b>Revision 15</b>: - Added RingTurboThermalProtectionand,NclkTurboThermalProtection
71
72 **/
73 typedef struct {
74 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
75 /**
76 Overclocking support. This controls whether OC mailbox transactions are sent.
77 If disabled, all policies in this config block besides OcSupport and OcLock will be ignored.
78 <b>0: Disable</b>;
79 1: Enable.
80 @note If PcdOverclockEnable is disabled, this should also be disabled.
81 **/
82 UINT32 OcSupport : 1;
83 /**
84 Core voltage mode, specifies which voltage mode the processor will be operating.
85 <b>0: Adaptive Mode</b> allows the processor to interpolate a voltage curve when beyond fused P0 range;
86 1: Override, sets one voltage for the entire frequency range, Pn-P0.
87 **/
88 UINT32 CoreVoltageMode : 1;
89 /**
90 Selects Core Voltage & Frequency Offset between Legacy and Selection modes.
91 Need Reset System after enabling OverClocking Feature to initialize the default value.
92 <b>0: In Legacy Mode, setting a global offset for the entire VF curve.</b>
93 1: In Selection Mode, setting a selected VF point.
94 **/
95 UINT32 CoreVfPointOffsetMode : 1;
96 /**
97 Core VF Configuration Scope.
98 Alows both all-core VF curve or per-core VF curve configuration.
99 <b>0: All-core Scope, setting the VF curve for all cores.</b>
100 1: Per-core Scope, setting the VF curve per-core.
101 **/
102 UINT32 CoreVfConfigScope : 1;
103 UINT32 PerCoreRatioOverride : 1; ///< Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new favored core ratio to each Core. <b>0: Disable</b>, 1: enable
104 UINT32 CoreRatioExtensionMode :1; ///< Enable or disable Core Ratio above 85 Extension Mode by writing BIOS MB 0x37 to enable FULL_RANGE_MULTIPLIER_UNLOCK_EN. <b>0: Disable</b>, 1: enable
105 /**
106 Ring Downbin enable/disable.
107 When enabled, the CPU will force the ring ratio to be lower than the core ratio.
108 Disabling will allow the ring and core ratios to run at the same frequency.
109 Uses OC Mailbox command 0x19.
110 0: Disables Ring Downbin feature. <b>1: Enables Ring downbin feature.</b>
111 **/
112 UINT32 RingDownBin : 1;
113 /**
114 Ring voltage mode, specifies which voltage mode the processor will be operating.
115 <b>0: Adaptive Mode</b> allows the processor to interpolate a voltage curve when beyond fused P0 range;
116 1: Override, sets one voltage for the entire frequency range, Pn-P0.
117 **/
118 UINT32 RingVoltageMode : 1;
119 UINT32 GtVoltageMode : 1; ///< Specifies whether GT voltage is operating in Adaptive or Override mode: <b>0=Adaptive</b>, 1=Override
120 /**
121 SA/Uncore voltage mode, specifies which voltage mode the processor will be operating.
122 <b>0: Adaptive Mode</b> allows the processor to interpolate a voltage curve when beyond fused P0 range;
123 1: Override, sets one voltage for the entire frequency range, Pn-P0.
124 **/
125 UINT32 SaVoltageMode : 1;
126 /**
127 This service controls Core frequency reduction caused by high package temperatures for processors that
128 implement the Intel Thermal Velocity Boost (TVB) feature. It is required to be disabled for supporting
129 overclocking at frequencies higher than the default max turbo frequency.
130 0: Disables TVB ratio clipping. <b>1: Enables TVB ratio clipping</b>.
131 **/
132 UINT32 TvbRatioClipping : 1;
133 /**
134 This service controls thermal based voltage optimizations for processors that implement the Intel
135 Thermal Velocity Boost (TVB) feature.
136 0: Disables TVB voltage optimization. <b>1: Enables TVB voltage optimization.</b>
137 **/
138 UINT32 TvbVoltageOptimization : 1;
139 UINT32 IaIccUnlimitedMode : 1; ///< Support IA Unlimited ICCMAX up to maximum value 512A., <b>0: Disable</b>. 1: Enable.
140 UINT32 GtIccUnlimitedMode : 1; ///< Support GT Unlimited ICCMAX up to maximum value 512A., <b>0: Disable</b>. 1: Enable.
141 /**
142 This service controls VCCSA Boot Voltage by programming the EPOC2 bits (strap).
143 <b> Default: 0: Nominal </b> 1: High Voltage(up to 1.2/1.3V)
144 **/
145 UINT32 VccsaBootVoltageSel : 1;
146 /**
147 This service controls CPU Bandgap bypass or not by programming the CPU EPOC2 bits (strap).
148 <b> Default: 0: Normal </b> 1: Bandgap Bypassed
149 **/
150 UINT32 CpuBandgapRefMode : 1;
151 /**
152 This service controls VCCIA boot voltage by programming SOC-North soft straps.
153 <b> Default: 0: Nominal </b> 1: High Voltage (support VCCIA boot voltage higher than 1.65v (max 2.01v))
154 **/
155 UINT32 VcciaBootVoltageSel : 1;
156 UINT32 BclkAdaptiveVoltage : 1; ///< Bclk Adaptive Voltage enable/disable. <b>0: Disabled</b>, 1: Enabled. When enabled, the CPU V/F curves are aware of BCLK frequency when calculated.
157 UINT32 RealtimeMemoryTiming : 1; ///< Enable/Disable the message sent to the CPU to allow realtime memory timing changes after MRC_DONE. <b>0=Disable</b>, 1=Enable
158 UINT32 Avx2RatioOffset : 5; ///< AVX2 Ratio Offset. <b>0: No offset</b>. Range is 0-31. Used to lower the AVX ratio to maximize possible ratio for SSE workload.
159 UINT32 Avx3RatioOffset : 5; ///< Deprecated from Revision 10
160 UINT32 GranularRatioOverride : 1; ///< Enable or disable OC Granular Ratio Override. <b>0: Disable</b>, 1: enable
161 /**
162 Memory Subsystem voltage mode, specifies which voltage mode the processor will be operating.
163 <b>0: Adaptive Mode</b> allows the processor to interpolate a voltage curve when beyond fused P0 range;
164 1: Override, sets one voltage for the entire frequency range, Pn-P0.
165 **/
166 UINT32 MemSSVoltageMode : 1;
167 /*
168 NGU voltage mode, specifies which voltage mode the processor will be operating.
169 <b>0: Adaptive Mode</b> allows the processor to interpolate a voltage curve when beyond fused P0 range;
170 1: Override, sets one voltage for the entire frequency range, Pn-P0.
171 **/
172 UINT32 NguVoltageMode : 1;
173 /**
174 Avx2 Voltage Guardband Scale Factor
175 This controls the AVX2 Voltage Guardband Scale factor applied to AVX2 workloads.
176 Valid range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor.
177 A value of 0 means no scale factor applied (no change to voltage on AVX commands)
178 A value of 100 applies the default voltage guardband values (1.0 factor).
179 A value > 100 will increase the voltage guardband on AVX2 workloads.
180 A value < 100 will decrease the voltage guardband on AVX2 workloads.
181 <b>0. No scale factor applied</b>
182 **/
183 UINT8 Avx2VoltageScaleFactor;
184 /**
185 Avx512 Voltage Guardband Scale Factor
186 This controls the AVX512 Voltage Guardband Scale factor applied to AVX512 workloads.
187 Valid range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor.
188 A value of 0 means no scale factor applied (no change to voltage on AVX commands)
189 A value of 100 applies the default voltage guardband values (1.0 factor).
190 A value > 100 will increase the voltage guardband on AVX512 workloads.
191 A value < 100 will decrease the voltage guardband on AVX512 workloads.
192 <b>0. No scale factor applied</b>
193 **/
194 UINT8 Avx512VoltageScaleFactor; // Deprecated from Revision 10
195
196 /**
197 Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit (P0).
198 <b>0. no override/HW defaults.</b>. Range non-turbo max - 120 (Previously max turbo is 83).
199 **/
200 UINT8 CoreMaxOcRatio;
201 UINT8 GtMaxOcRatio; ///< Maximum GT turbo ratio override: 0=Minimal, 60=Maximum, <b>0=AUTO</b>
202 /**
203 Maximum ring ratio override allows to increase CPU ring frequency beyond the fused max ring ratio limit.
204 <b>0. no override/HW defaults.</b>. Range non-turbo max - 85.
205 **/
206 UINT8 RingMaxOcRatio;
207 /**
208 TjMax Offset. Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius.
209 <b> Default: 0 Hardware Defaults </b> Range 10 to 63. 0 = No offset / Keep HW default.
210 **/
211 UINT8 TjMaxOffset;
212 /**
213 The core voltage override which is applied to the entire range of cpu core frequencies.
214 Used when CoreVoltageMode = Override.
215 <b>0. no override</b>. Range 0-2000 mV.
216 **/
217 UINT16 CoreVoltageOverride;
218 /**
219 Adaptive voltage target used to define the interpolation voltage point when the cpu is operating in adaptive mode range.
220 Used when CoreVoltageMode = Adaptive.
221 <b>0. no override</b>. Range 0-2000mV.
222 **/
223 UINT16 CoreAdaptiveVoltage;
224 /**
225 The core voltage offset applied on top of all other voltage modes. This offset is applied over the entire frequency range.
226 This is a 2's complement number in mV units. <b>Default: 0</b> Range: -1000 to 1000.
227 **/
228 INT16 CoreVoltageOffset;
229 /**
230 The ring voltage override which is applied to the entire range of cpu ring frequencies.
231 Used when RingVoltageMode = Override.
232 <b>0. no override</b>. Range 0-2000 mV.
233 **/
234 UINT16 RingVoltageOverride;
235 /**
236 Adaptive voltage target used to define the interpolation voltage point when the ring is operating in adaptive mode range.
237 Used when RingVoltageMode = Adaptive.
238 <b>0. no override</b>. Range 0-2000mV.
239 **/
240 UINT16 RingAdaptiveVoltage;
241 /**
242 The ring voltage offset applied on top of all other voltage modes. This offset is applied over the entire frequency range.
243 This is a 2's complement number in mV units. <b>Default: 0</b> Range: -1000 to 1000.
244 **/
245 INT16 RingVoltageOffset;
246 /**
247 The SA/Uncore voltage override which is applied to the entire range of uncore frequencies.
248 Used when SaVoltageMode = Override.
249 <b>0. no override</b>. Range 0-2000 mV.
250 **/
251 UINT16 SaVoltageOverride;
252 /**
253 Adaptive voltage target used to define the interpolation voltage point when the SA/Uncore is operating in adaptive mode range.
254 Used when SaVoltageMode = Adaptive.
255 <b>0. no override</b>. Range 0-2000mV.
256 **/
257 UINT16 SaAdaptiveVoltage;
258 /**
259 Voltage Regulator Current Limit (Icc Max) for IA, GT and SA. This value represents the Maximum instantaneous current allowed at any given time.
260 The value is represented in 1/4 A increments. A value of 400 = 100A. <b>0 (HW default)</b>. Range is 4-2047.
261 **/
262 UINT16 IaIccMax;
263 UINT16 GtIccMax;
264 UINT16 SaIccMax;
265 INT16 GtVoltageOffset; ///< The voltage offset applied to GT slice. Valid range from -1000mv to 1000mv: <b>0=Minimal</b>, 1000=Maximum
266 UINT16 GtVoltageOverride; ///< The GT voltage override which is applied to the entire range of GT frequencies <b>0=Default</b>
267 UINT16 GtAdaptiveVoltage; ///< The adaptive voltage applied during turbo frequencies. Valid range from 0 to 2000mV: <b>0=Minimal</b>, 2000=Maximum
268 /**
269 Selects GT Voltage & Frequency Point Offset between Legacy and Selection modes.
270 Need Reset System after enabling OverClocking Feature to initialize the default value.
271 <b>0: In Legacy Mode, setting a global offset for the entire VF curve.</b>
272 1: In Selection modes, setting a selected VF point.
273 **/
274 UINT8 GtVfPointOffsetMode;
275 UINT8 GtVfPointCount; ///< Number of supported GR Voltage & Frequency Point.
276 /**
277 Array used to specifies the GT Voltage Offset applied to the each selected VF Point.
278 This voltage is specified in millivolts. <b>Default: 0</b> Range: 0 to 1000
279 **/
280 INT16 GtVfPointOffset[CPU_OC_MAX_VF_POINTS];
281 UINT8 GtVfPointRatio[CPU_OC_MAX_VF_POINTS]; ///< Array for the each selected VF Point to display the GT Ration.
282 UINT8 GtRsvd[1];
283 INT16 SaVoltageOffset; ///< The voltage offset applied to the SA. Valid range from -1000mv to 1000mv: <b>0=Default</b>
284 UINT32 CorePllVoltageOffset : 4; ///< Core PLL voltage offset. <b>0: No offset</b>. Range 0-15 in 17.5mv units.
285 UINT32 RingPllVoltageOffset : 4; ///< Ring PLL voltage offset. <b>0: No offset</b>. Range 0-15 in 17.5mv units.
286 UINT32 SaPllVoltageOffset : 4; ///< SOC System Agent PLL voltage offset. <b>0: No offset</b>. Range 0-15 in 17.5mv units.
287 UINT32 IaAtomPllVoltageOffset : 4; ///< IA Atom PLL voltage offset. <b>0: No offset</b>. Range 0-15 in 17.5mv units.
288 UINT32 McPllVoltageOffset : 4; ///< Memory Controller PLL voltage offset. <b>0: No offset</b>. Range 0-15 in 17.5mv units.
289 UINT32 CpuSaPllVoltageOffset : 4; ///< Cpu SA PLL voltage offset. <b>0: No offset</b>. Range 0-15 in 17.5mv units.
290 UINT32 CpuDlvrMode : 1; ///< Select Core(s) and RING DLVR Mode, <b>0: Regulation Mode</b>. 1: Power Gate Mode.
291 UINT32 SaPllFreqOverride : 1; ///< Sa PLL Frequecy Override. <b>0: 2400MHz</b>. 1: 1600MHz.
292 UINT32 TscDisableHwFixup : 1; ///< Core HW Fixup disable during TSC copy from PMA to APIC, <b>0: Enable</b>. 1: Disable.
293 UINT32 SaIccUnlimitedMode : 1; ///< Support SA Unlimited ICCMAX up to maximum value 512A., <b>0: Disable</b>. 1: Enable.
294 UINT32 RsvdBits1 : 4; ///< Reserved bits
295 /**
296 Core disable mask is a bitwise indication of which core should be disabled, while ActiveCoreCount is to set the number of active cores.
297 Each bit represents physical core id for both P-core and E-core
298 1 - Disable
299 0 - Ignored
300 Default is 0, means no Core disable mask setting.
301 **/
302 UINT64 DisablePerCoreMask;
303 /**
304 Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, 0 - is ignored.
305 Input is in HEX and each bit maps to a logical core. Ex. A value of '1F' would disable HT for cores 4,3,2,1 and 0.
306 <b>Default is 0</b>, all cores have HT enabled. Range is 0 - 0x1FF. You can only disable up to MAX_CORE_COUNT - 1.
307 **/
308 UINT16 PerCoreHtDisable;
309
310 UINT8 CoreVfPointCount; ///< Number of supported Core Voltage & Frequency Point.
311 UINT8 CoreVfPointRatio[CPU_OC_MAX_VF_POINTS]; ///< Array for the each selected VF Point to display the Core Ration. It's only for read command and not for write.
312 /**
313 Array used to specifies the Core Voltage Offset applied to the each selected VF Point.
314 This voltage is specified in millivolts. <b>Default: 0</b> Range: 0 to 1000
315 **/
316 INT16 CoreVfPointOffset[CPU_OC_MAX_VF_POINTS];
317 /**
318 Selects Ring Voltage & Frequency Point Offset between Legacy and Selection modes.
319 Need Reset System after enabling OverClocking Feature to initialize the default value.
320 <b>0: In Legacy Mode, setting a global offset for the entire VF curve.</b>
321 1: In Selection modes, setting a selected VF point.
322 **/
323 UINT8 RingVfPointOffsetMode;
324 UINT8 RingVfPointCount; ///< Number of supported Ring Voltage & Frequency Point.
325 /**
326 Array used to specifies the Ring Voltage Offset applied to the each selected VF Point.
327 This voltage is specified in millivolts. <b>Default: 0</b> Range: 0 to 1000
328 **/
329 INT16 RingVfPointOffset[CPU_OC_MAX_VF_POINTS];
330 UINT8 RingVfPointRatio[CPU_OC_MAX_VF_POINTS]; ///< Array for the each selected VF Point to display the Ring Ration. It's only for read command and not for write.
331 UINT8 MemSSVfPointCount; ///< Number of supported Memory Subsystem Voltage & Frequency Point.
332 /**
333 Array used to specifies the Memory Subsystem Voltage Offset applied to the each selected VF Point.
334 This voltage is specified in millivolts. <b>Default: 0</b> Range: 0 to 1000
335 **/
336 INT16 MemSSVfPointOffset[CPU_OC_MAX_VF_POINTS];
337 UINT8 MemSSVfPointRatio[CPU_OC_MAX_VF_POINTS]; ///< Array for the each selected VF Point to display the Memory Subsystem Ration. It's only for read command and not for write.
338 /**
339 FLL_OVERCLOCK_MODE: 0x0 = no overclocking,
340 0x1 = ratio overclocking with nominal (0.5-1x) reference clock frequency,
341 0x2 = BCLK overclocking with elevated (1-3x) reference clock frequency,
342 0x3 = BCLK overclocking with extreme elevated (3-5x) reference clock frequency and ratio limited to 63.
343 **/
344 UINT8 FllOverclockMode;
345 /**
346 Set CPU D2D Ratio from Range 15 to 40. Default 0 indicates no setting.
347 **/
348 UINT8 CpuD2dRatio;
349 /**
350 When UnderVolt Protection is enabled, user will be not be able to program under voltage in OS runtime.
351 0: protection is disabled, <b> 1:protection is enabled </b>.
352 **/
353 UINT8 UnderVoltProtection;
354 /**
355 Array used to specifies the selected Core Offset Voltage.
356 This voltage is specified in millivolts.
357 **/
358 INT16 PerCoreVoltageOffset[CPU_MAX_BIG_CORES];
359 UINT8 PerCoreRatio[CPU_MAX_BIG_CORES];
360 UINT8 PerCoreVoltageMode[CPU_MAX_BIG_CORES]; ///< Array used to specifies the selected Core Voltage Mode.
361 UINT16 PerCoreVoltageOverride[CPU_MAX_BIG_CORES]; ///< Array used to specifies the selected Core Voltage Override.
362 UINT16 PerCoreAdaptiveVoltage[CPU_MAX_BIG_CORES]; ///< Array used to specifies the selected Core Adaptive Voltage.
363 UINT8 PerAtomClusterVoltageMode[CPU_MAX_ATOM_CLUSTERS]; ///< Array used to specifies the selected Atom Core Voltage Mode.
364 UINT16 PerAtomClusterVoltageOverride[CPU_MAX_ATOM_CLUSTERS]; ///< Array used to specifies the selected Atom Core Voltage Override.
365 UINT16 PerAtomClusterAdaptiveVoltage[CPU_MAX_ATOM_CLUSTERS]; ///< Array used to specifies the selected Atom Core Adaptive Voltage.
366 /**
367 The Atom cluster max ratio overrides.
368 <b>Default: 0</b> Range: 0 to 120.
369 **/
370 UINT8 AtomClusterRatio[CPU_MAX_ATOM_CLUSTERS];
371 INT16 PerAtomClusterVoltageOffset[CPU_MAX_ATOM_CLUSTERS];
372
373 UINT32 CpuBclkOcFrequency; ///< CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz <b>0 - Auto</b>. Range is 8000-50000 (10KHz)
374 UINT32 SocBclkOcFrequency; ///< SOC BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz <b>0 - Auto</b>. Range is 4000-100000 (10KHz)
375 /**
376 The Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio (P0 to Pn) to select the multiplier
377 so that the output is within the DCO frequency range. This threshold is applied to SA and MC/CMI PLL for SOC die and SA, Ring and Atom PLL when CPU die is selected.
378 Range 0-63. When the threshold is 0, static PVD ratio is selected based on the PVD Mode for SOC. <b>0: Default</b>.
379 **/
380 UINT8 PvdRatioThreshold[2];
381 /**
382 PVD Mode selects Static PVD ratio for SOC/CPU (when PVD THRESHOLD value is 0).
383 0x0 = div-1 (VCO = Output clock), 0x1 = div-2 (VCO = 2x Output clock)
384 0x2 = div-4 (VCO = 4x Output clock), 0x3 = div-8 (VCO = 8x Output clock)
385 **/
386 UINT8 PvdMode[2];
387 /**
388 Percore & PerAtomCluster Granularity Bins Override.
389 Array used to specifies the selected Core & AtomCluster Granularity Bins.
390 It's a negative offset to current resolved P0 ratio, programming Granularity Bins will always reduce the core frequency.
391 value is how many bins of 'Granularity Units' should be subtracted from the otherwise-configured P0 frequency.
392 <b>value = 0 (default)</b> Range 0-255.
393 **/
394 UINT8 PerCoreGranularityBins[CPU_MAX_BIG_CORES];
395 UINT8 PerAtomClusterGranularityBins[CPU_MAX_ATOM_CLUSTERS];
396 /**
397 Adaptive voltage target used to define the interpolation voltage point when the cpu is operating in adaptive mode range.
398 Used when MemSSVoltageMode = Adaptive.
399 <b>0. no override</b>. Range 0-2000mV.
400 **/
401 UINT16 MemSSAdaptiveVoltage;
402 /**
403 The Memory Subsystem voltage override which is applied to the entire range of uncore frequencies.
404 Used when MemSSVoltageMode = Override.
405 <b>0. no override</b>. Range 0-2000 mV.
406 **/
407 UINT16 MemSSVoltageOverride;
408 /**
409 Selects Memory Subsystem Voltage & Frequency Point Offset between Legacy and Selection modes.
410 Need Reset System after enabling OverClocking Feature to Initialize the default value.
411 <b>0: In Legacy Mode, setting a global offset for the entire VF curve.</b>
412 1: In Selection modes, setting a selected VF point.
413 **/
414 UINT8 MemSSVfPointOffsetMode;
415 /**
416 Maximum Memory Subsystem ratio override allows to increase memory frequency beyond the fused max ring ratio limit.
417 <b>0. no override/HW defaults.</b>. Range non-turbo max - 109.
418 **/
419 UINT8 MemSSMaxOcRatio;
420 /**
421 The Memory Subsystem voltage offset applied on top of all other voltage modes. This offset is applied over the entire frequency range.
422 This is a 2's complement number in mV units. <b>Default: 0</b> Range: -1000 to 1000.
423 **/
424 INT16 MemSSVoltageOffset;
425 UINT8 Rsvd1[4];
426 /**
427 OC TVB Enable/Disable. This control will come into picture only when TVB Ratio clipping
428 is enabled from OCMB 0x18/0x19 (bit 2). When disabled, BIOS will not send OC TVB parameter
429 commands 0x24/0x25. When OcTvb is enabled, BIOS will allow user to modify and program
430 new parameters for temperature thresholds T0, T1 and delta DownBins for T0 and T1.
431 <b>0: Disable</b>, 1: Enable.
432 */
433 UINT8 OcTvb;
434 /**
435 Temperature Threshold 0 for all Pcores (in degrees C). Running ABOVE this temperature will clip delta
436 Down Bins for T0 from the resolved OC Ratio, when TVB ratio clipping is enabled from OCMB 0x18 Bit 2 = 0 (Enabled).
437 <b>70 </b>. Range 0-100.
438 **/
439 UINT8 PcoreTvbTempThreshold0;
440 /**
441 Temperature Threshold 1 for all Pcores (in degrees C). Running ABOVE this temperature will clip delta
442 Down Bins for T1 from the resolved OC Ratio, when TVB ratio clipping is enabled from OCMB 0x18 Bit 2 = 0 (Enabled).
443 <b>100 </b>. Range 0-100.
444 **/
445 UINT8 PcoreTvbTempThreshold1;
446 /**
447 Temperature Threshold 0 for all Ecores (in degrees C). Running ABOVE this temperature will clip delta
448 Down Bins for T0 from the resolved OC Ratio, when TVB ratio clipping is enabled from OCMB 0x18 Bit 2 = 0 (Enabled).
449 <b>70 </b>. Range 0-100.
450 **/
451 UINT8 EcoreTvbTempThreshold0;
452 /**
453 Temperature Threshold 1 for all Ecores (in degrees C). Running ABOVE this temperature will clip delta
454 Down Bins for T1 from the resolved OC Ratio, when TVB ratio clipping is enabled from OCMB 0x18 Bit 2 = 0 (Enabled).
455 <b>100 </b>. Range 0-100.
456 **/
457 UINT8 EcoreTvbTempThreshold1;
458 /**
459 Limits Select,
460 0 - Per CCP (Module), Command Param2 = CCP ID, CCP ID can range from 0-15.
461 1 - Per Pcore group number, Command Param2 = Pcore Group Number (0-7), a Pcore active group has number of active cores as present in MSR 0x1AE.
462 <b> 0 </b>.
463 **/
464 UINT8 TvbConfigLimitSelect;
465 /**
466 Down Bins (delta) for Temperature Threshold 0. When running above T0, the ratio of Per Pcore module will be clipped by
467 MAX_RATIO[n]-this value, when TVB ratio clipping is enabled from OCMB 0x18 Bit 2 = 0 (Enabled).
468 <b>1 </b>. Range 0-10.
469 **/
470 UINT8 PerPcoreRatioDownBinAboveT0[CPU_MAX_BIG_CORES];
471 /**
472 Down Bins (delta) for Temperature Threshold 1. When running above T1, the ratio of Per Pcore module will be clipped by
473 MAX_RATIO[n]-this value, when TVB ratio clipping is enabled from OCMB 0x18 Bit 2 = 0 (Enabled).
474 <b>2 </b>. Range 0-10.
475 **/
476 UINT8 PerPcoreRatioDownBinAboveT1[CPU_MAX_BIG_CORES];
477 /**
478 Down Bins (delta) for Temperature Threshold 0. When running above T0, the ratio of Per Ecore module will be clipped by
479 MAX_RATIO[n]-this value, when TVB ratio clipping is enabled from OCMB 0x18 Bit 2 = 0 (Enabled).
480 <b>0 </b>. Range 0-10.
481 **/
482 UINT8 PerEcoreCcpRatioDownBinAboveT0[CPU_MAX_ATOM_CLUSTERS];
483 /**
484 Down Bins (delta) for Temperature Threshold 1. When running above T1, the ratio of Per Ecore module will be clipped by
485 MAX_RATIO[n]-this value, when TVB ratio clipping is enabled from OCMB 0x18 Bit 2 = 0 (Enabled).
486 <b>0 </b>. Range 0-10.
487 **/
488 UINT8 PerEcoreCcpRatioDownBinAboveT1[CPU_MAX_ATOM_CLUSTERS];
489 /**
490 Down Bins (delta) for Temperature Threshold 0. When running above T0, the ratio of Per Pcore group will be clipped by
491 MAX_RATIO[n]-this value, when TVB ratio clipping is enabled from OCMB 0x18 Bit 2 = 0 (Enabled).
492 <b>1 </b>. Range 0-10.
493 **/
494 UINT8 PerPcoreGrRatioDownBinAboveT0[CPU_MAX_BIG_CORE_TRL_GROUPS];
495 /**
496 Down Bins (delta) for Temperature Threshold 1. When running above T1, the ratio of Per Pcore group will be clipped by
497 MAX_RATIO[n]-this value, when TVB ratio clipping is enabled from OCMB 0x18 Bit 2 = 0 (Enabled).
498 <b>2 </b>. Range 0-10.
499 **/
500 UINT8 PerPcoreGrRatioDownBinAboveT1[CPU_MAX_BIG_CORE_TRL_GROUPS];
501
502 /**
503 Ring Turbo Thermal Protection (TTP) control which allows user to disable Turbo Thermal Protection for Ring.
504 This is a sticky bit, Once set, will remain set until cold or warm reset is performed. 0: Disable; <b>1: Enable</b>
505 **/
506 UINT8 RingTurboThermalProtection;
507
508 /**
509 NCLK Turbo Thermal Protection (TTP) control which allows user to disable Turbo Thermal Protection for SA.
510 This is a sticky bit, Once set, will remain set until cold or warm reset is performed. 0: Disable; <b>1: Enable</b>
511 **/
512 UINT8 NclkTurboThermalProtection;
513
514 /**
515 Enable or Disable Compute Die SSC configuration.
516 - <b>0: Disable</b>
517 - 1: Enable
518 **/
519 UINT8 ComputeDieSscEnable;
520
521 /**
522 Enable or Disable Soc Die SSC configuration.
523 - <b>0: Disable</b>
524 - 1: Enable
525 **/
526 UINT8 SocDieSscEnable;
527
528 UINT8 Rsvd3[6];
529
530 UINT8 PerCoreMaxRatio[CPU_MAX_BIG_CORES]; ///< Array used to specifies the selected Core Max Ratio.
531 UINT8 PerAtomClusterMaxRatio[CPU_MAX_ATOM_CLUSTERS]; ///< Array used to specifies the selected Atom Cluster Max Ratio.
532 /**
533 Maximum NGU ratio override allows to increase CPU NGU frequency beyond the fused max NGU ratio limit.
534 <b>0. no override/HW defaults.</b>. Range 0-34.
535 **/
536 UINT8 NguMaxOcRatio;
537 /**
538 Sets the Ratio for NGU using SAVG B2P Mailbox cmd 0x22 and subcommand 0x1.
539 When this value is zero, dynamic mode is selected and NGU ratio can be modified using OCMB cmd 0x11.
540 When valid ratio value is set, static mode is selected with the fixed ratio specified by this value.
541 **/
542 UINT8 NguRatio;
543 /**
544 The NGU voltage override which is applied to the entire range of cpu NGU frequencies.
545 Used when NguVoltageMode = Override.
546 <b>0. no override</b>. Range 0-2000 mV.
547 **/
548 UINT16 NguVoltageOverride;
549 UINT16 NguAdaptiveVoltage; ///< The adaptive voltage applied during turbo frequencies. Valid range from 0 to 2000mV: <b>0=Minimal</b>, 2000=Maximum
550 /**
551 The NGU voltage offset applied on top of all other voltage modes. This offset is applied over the entire frequency range.
552 This is a 2's complement number in mV units. <b>Default: 0</b> Range: -1000 to 1000.
553 **/
554 INT16 NguVoltageOffset;
555 /**
556 Selects NGU Voltage & Frequency Point Offset between Legacy and Selection modes.
557 Need Reset System after enabling OverClocking Feature to initialize the default value.
558 <b>0: In Legacy Mode, setting a global offset for the entire VF curve.</b>
559 1: In Selection modes, setting a selected VF point.
560 **/
561 UINT8 NguVfPointOffsetMode;
562 UINT8 NguVfPointCount; ///< Number of supported NGU Voltage & Frequency Point.
563 /**
564 Array used to specifies the NGU Voltage Offset applied to the each selected VF Point.
565 This voltage is specified in millivolts. <b>Default: 0</b> Range: 0 to 1000
566 **/
567 INT16 NguVfPointOffset[CPU_OC_MAX_VF_POINTS];
568 UINT8 NguVfPointRatio[CPU_OC_MAX_VF_POINTS]; ///< Array for the each selected VF Point to display the NGU Ration. It's only for read command and not for write.
569 /**
570 Disabling Process Vmax Limit will allow user to set any voltage. If this limit is not disabled then, request above factory set limits will be rejected.
571 This is a sticky bit, BIOS can only set this bit, it cannot be cleared by mailbox command. This setting persists over warm reset, and cleared on cold reset.
572 MailBox control is to disable the ProcessVmaxLimit (reverse encoding is used). 0: Disable;<b>1: Enable</b>;
573 Note: Disabling the voltage limit checks may cause permanent damage to processor.
574 Note: This bit cannot be set after BIOS_RST_CPL.
575 */
576 UINT8 ProcessVmaxLimit;
577 /**
578 Pcore Power Density Throttle control allows user to disable P-core throttling for power density protection.
579 This is a sticky bit, Once set, will remain set until cold or warm reset is performed.
580 MailBox control is to disable the Pcore Power Density Throttling (reverse encoding is used). 0: Disable;<b>1: Enable</b>;
581 **/
582 UINT8 PcorePowerDensityThrottle;
583 UINT8 Rsvd5[1];
584 UINT16 MaxVoltageLimit[MAX_OC_DOMAINS]; ///< Array for the each Domain to set OC Max Voltage limits <b>Default: 0 </b> Range: 0 to 2000
585 UINT8 Rsvd6[1];
586 UINT8 CorePllCurrentRefTuningOffset; ///< Core PLL Current Reference Tuning Offset. <b>0: No offset</b>. Range 0-15
587 UINT8 RingPllCurrentRefTuningOffset; ///< Deprecated from Revision 11
588 UINT8 IaAtomPllCurrentRefTuningOffset; ///< IaAtom PLL Current Reference Tuning Offset. <b>0: No offset</b>. Range 0-15
589 /**
590 Request Core Min Ratio. Limit Core minimum ratio for extreme overclocking. Default 0 indicates no request.
591 **/
592 UINT8 CoreMinRatio;
593 /**
594 This configuration allows OC user to either use legacy num of cores option or the OC specific per core disable configuration. <b>0: Disable</b>, 1: Enable
595 **/
596 UINT8 PerCoreDisableConfiguration;
597
598 UINT8 NpuMaxOcRatio; ///< Deprecated from Revision 13
599 UINT8 NpuVoltageMode; ///< Deprecated from Revision 13
600 UINT16 NpuVoltageOverride; ///< Deprecated from Revision 13
601 UINT16 NpuAdaptiveVoltage; ///< Deprecated from Revision 13
602 INT16 NpuVoltageOffset; ///< Deprecated from Revision 13
603
604 UINT8 ForcePcoreResidency; ///< Enable or disable Force Pcore Residency. <b>0: Disable</b>, 1: enable
605 UINT8 VrLimitBypass; ///< Enable or disable VR Limit Bypass. <b>0: Disable</b>, 1: enable
606
607 /**
608 Turbo Thermal Protection (TTP) control allows user to disable Turbo Thermal Protection.
609 This is a sticky bit, Once set, will remain set until cold or warm reset is performed. 0: Disable; <b>1: Enable</b>
610 **/
611 UINT8 TurboThermalProtection;
612 UINT8 Rsvd7[27];
613 } OVERCLOCKING_PREMEM_CONFIG;
614
615 #pragma pack (pop)
616
617 #endif // _CPU_OVERCLOCKING_CONFIG_H_
OVERCLOCKING_PREMEM_CONFIG::MemSSVfPointCount
UINT8 MemSSVfPointCount
Number of supported Memory Subsystem Voltage & Frequency Point.
Definition: OverclockingConfig.h:331
OVERCLOCKING_PREMEM_CONFIG::RingVoltageOffset
INT16 RingVoltageOffset
The ring voltage offset applied on top of all other voltage modes.
Definition: OverclockingConfig.h:245
OVERCLOCKING_PREMEM_CONFIG::GtVoltageOverride
UINT16 GtVoltageOverride
The GT voltage override which is applied to the entire range of GT frequencies 0=Default
Definition: OverclockingConfig.h:266
OVERCLOCKING_PREMEM_CONFIG::Avx512VoltageScaleFactor
UINT8 Avx512VoltageScaleFactor
Avx512 Voltage Guardband Scale Factor This controls the AVX512 Voltage Guardband Scale factor applied...
Definition: OverclockingConfig.h:194
OVERCLOCKING_PREMEM_CONFIG::NclkTurboThermalProtection
UINT8 NclkTurboThermalProtection
NCLK Turbo Thermal Protection (TTP) control which allows user to disable Turbo Thermal Protection for...
Definition: OverclockingConfig.h:512
OVERCLOCKING_PREMEM_CONFIG::GtVoltageOffset
INT16 GtVoltageOffset
The voltage offset applied to GT slice. Valid range from -1000mv to 1000mv: 0=Minimal,...
Definition: OverclockingConfig.h:265
OVERCLOCKING_PREMEM_CONFIG::PcoreTvbTempThreshold0
UINT8 PcoreTvbTempThreshold0
Temperature Threshold 0 for all Pcores (in degrees C).
Definition: OverclockingConfig.h:439
OVERCLOCKING_PREMEM_CONFIG::CorePllCurrentRefTuningOffset
UINT8 CorePllCurrentRefTuningOffset
Core PLL Current Reference Tuning Offset. 0: No offset. Range 0-15.
Definition: OverclockingConfig.h:586
OVERCLOCKING_PREMEM_CONFIG::NpuVoltageOverride
UINT16 NpuVoltageOverride
Deprecated from Revision 13.
Definition: OverclockingConfig.h:600
OVERCLOCKING_PREMEM_CONFIG::UnderVoltProtection
UINT8 UnderVoltProtection
When UnderVolt Protection is enabled, user will be not be able to program under voltage in OS runtime...
Definition: OverclockingConfig.h:353
OVERCLOCKING_PREMEM_CONFIG::GtAdaptiveVoltage
UINT16 GtAdaptiveVoltage
The adaptive voltage applied during turbo frequencies. Valid range from 0 to 2000mV: 0=Minimal,...
Definition: OverclockingConfig.h:267
OVERCLOCKING_PREMEM_CONFIG::FllOverclockMode
UINT8 FllOverclockMode
FLL_OVERCLOCK_MODE: 0x0 = no overclocking, 0x1 = ratio overclocking with nominal (0....
Definition: OverclockingConfig.h:344
OVERCLOCKING_PREMEM_CONFIG::NpuMaxOcRatio
UINT8 NpuMaxOcRatio
Deprecated from Revision 13.
Definition: OverclockingConfig.h:598
OVERCLOCKING_PREMEM_CONFIG::IaIccMax
UINT16 IaIccMax
Voltage Regulator Current Limit (Icc Max) for IA, GT and SA.
Definition: OverclockingConfig.h:262
OVERCLOCKING_PREMEM_CONFIG::IaAtomPllCurrentRefTuningOffset
UINT8 IaAtomPllCurrentRefTuningOffset
IaAtom PLL Current Reference Tuning Offset. 0: No offset. Range 0-15.
Definition: OverclockingConfig.h:588
OVERCLOCKING_PREMEM_CONFIG::CoreVfPointOffsetMode
UINT32 CoreVfPointOffsetMode
Selects Core Voltage & Frequency Offset between Legacy and Selection modes.
Definition: OverclockingConfig.h:95
OVERCLOCKING_PREMEM_CONFIG::RealtimeMemoryTiming
UINT32 RealtimeMemoryTiming
Enable/Disable the message sent to the CPU to allow realtime memory timing changes after MRC_DONE....
Definition: OverclockingConfig.h:157
OVERCLOCKING_PREMEM_CONFIG::SocBclkOcFrequency
UINT32 SocBclkOcFrequency
SOC BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz 0 - Auto....
Definition: OverclockingConfig.h:374
OVERCLOCKING_PREMEM_CONFIG::Avx2VoltageScaleFactor
UINT8 Avx2VoltageScaleFactor
Avx2 Voltage Guardband Scale Factor This controls the AVX2 Voltage Guardband Scale factor applied to ...
Definition: OverclockingConfig.h:183
OVERCLOCKING_PREMEM_CONFIG::RsvdBits1
UINT32 RsvdBits1
Reserved bits.
Definition: OverclockingConfig.h:294
OVERCLOCKING_PREMEM_CONFIG::RingAdaptiveVoltage
UINT16 RingAdaptiveVoltage
Adaptive voltage target used to define the interpolation voltage point when the ring is operating in ...
Definition: OverclockingConfig.h:240
OVERCLOCKING_PREMEM_CONFIG::NguMaxOcRatio
UINT8 NguMaxOcRatio
Maximum NGU ratio override allows to increase CPU NGU frequency beyond the fused max NGU ratio limit.
Definition: OverclockingConfig.h:536
OVERCLOCKING_PREMEM_CONFIG::RingDownBin
UINT32 RingDownBin
Ring Downbin enable/disable.
Definition: OverclockingConfig.h:112
OVERCLOCKING_PREMEM_CONFIG::CpuSaPllVoltageOffset
UINT32 CpuSaPllVoltageOffset
Cpu SA PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
Definition: OverclockingConfig.h:289
OVERCLOCKING_PREMEM_CONFIG::CoreAdaptiveVoltage
UINT16 CoreAdaptiveVoltage
Adaptive voltage target used to define the interpolation voltage point when the cpu is operating in a...
Definition: OverclockingConfig.h:223
OVERCLOCKING_PREMEM_CONFIG::VcciaBootVoltageSel
UINT32 VcciaBootVoltageSel
This service controls VCCIA boot voltage by programming SOC-North soft straps.
Definition: OverclockingConfig.h:155
OVERCLOCKING_PREMEM_CONFIG::NguAdaptiveVoltage
UINT16 NguAdaptiveVoltage
The adaptive voltage applied during turbo frequencies. Valid range from 0 to 2000mV: 0=Minimal,...
Definition: OverclockingConfig.h:549
OVERCLOCKING_PREMEM_CONFIG::SaAdaptiveVoltage
UINT16 SaAdaptiveVoltage
Adaptive voltage target used to define the interpolation voltage point when the SA/Uncore is operatin...
Definition: OverclockingConfig.h:257
OVERCLOCKING_PREMEM_CONFIG::PcoreTvbTempThreshold1
UINT8 PcoreTvbTempThreshold1
Temperature Threshold 1 for all Pcores (in degrees C).
Definition: OverclockingConfig.h:445
OVERCLOCKING_PREMEM_CONFIG::CpuBandgapRefMode
UINT32 CpuBandgapRefMode
This service controls CPU Bandgap bypass or not by programming the CPU EPOC2 bits (strap).
Definition: OverclockingConfig.h:150
OVERCLOCKING_PREMEM_CONFIG::CpuD2dRatio
UINT8 CpuD2dRatio
Set CPU D2D Ratio from Range 15 to 40.
Definition: OverclockingConfig.h:348
OVERCLOCKING_PREMEM_CONFIG::Avx2RatioOffset
UINT32 Avx2RatioOffset
AVX2 Ratio Offset. 0: No offset. Range is 0-31. Used to lower the AVX ratio to maximize possible rati...
Definition: OverclockingConfig.h:158
OVERCLOCKING_PREMEM_CONFIG::GranularRatioOverride
UINT32 GranularRatioOverride
Enable or disable OC Granular Ratio Override. 0: Disable, 1: enable.
Definition: OverclockingConfig.h:160
OVERCLOCKING_PREMEM_CONFIG::CoreVfPointCount
UINT8 CoreVfPointCount
Number of supported Core Voltage & Frequency Point.
Definition: OverclockingConfig.h:310
OVERCLOCKING_PREMEM_CONFIG::EcoreTvbTempThreshold0
UINT8 EcoreTvbTempThreshold0
Temperature Threshold 0 for all Ecores (in degrees C).
Definition: OverclockingConfig.h:451
OVERCLOCKING_PREMEM_CONFIG::PerCoreHtDisable
UINT16 PerCoreHtDisable
Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, 0 - is ignored.
Definition: OverclockingConfig.h:308
OVERCLOCKING_PREMEM_CONFIG::SaPllFreqOverride
UINT32 SaPllFreqOverride
Sa PLL Frequecy Override. 0: 2400MHz. 1: 1600MHz.
Definition: OverclockingConfig.h:291
OVERCLOCKING_PREMEM_CONFIG::NguVfPointOffsetMode
UINT8 NguVfPointOffsetMode
Selects NGU Voltage & Frequency Point Offset between Legacy and Selection modes.
Definition: OverclockingConfig.h:561
OVERCLOCKING_PREMEM_CONFIG::RingVfPointCount
UINT8 RingVfPointCount
Number of supported Ring Voltage & Frequency Point.
Definition: OverclockingConfig.h:324
OVERCLOCKING_PREMEM_CONFIG::GtVfPointOffsetMode
UINT8 GtVfPointOffsetMode
Selects GT Voltage & Frequency Point Offset between Legacy and Selection modes.
Definition: OverclockingConfig.h:274
OVERCLOCKING_PREMEM_CONFIG
Overclocking Configuration Structure.
Definition: OverclockingConfig.h:73
OVERCLOCKING_PREMEM_CONFIG::MemSSMaxOcRatio
UINT8 MemSSMaxOcRatio
Maximum Memory Subsystem ratio override allows to increase memory frequency beyond the fused max ring...
Definition: OverclockingConfig.h:419
OVERCLOCKING_PREMEM_CONFIG::GtMaxOcRatio
UINT8 GtMaxOcRatio
Maximum GT turbo ratio override: 0=Minimal, 60=Maximum, 0=AUTO
Definition: OverclockingConfig.h:201
OVERCLOCKING_PREMEM_CONFIG::VccsaBootVoltageSel
UINT32 VccsaBootVoltageSel
This service controls VCCSA Boot Voltage by programming the EPOC2 bits (strap).
Definition: OverclockingConfig.h:145
OVERCLOCKING_PREMEM_CONFIG::TurboThermalProtection
UINT8 TurboThermalProtection
Turbo Thermal Protection (TTP) control allows user to disable Turbo Thermal Protection.
Definition: OverclockingConfig.h:611
OVERCLOCKING_PREMEM_CONFIG::MemSSVoltageMode
UINT32 MemSSVoltageMode
Memory Subsystem voltage mode, specifies which voltage mode the processor will be operating.
Definition: OverclockingConfig.h:166
OVERCLOCKING_PREMEM_CONFIG::RingVoltageOverride
UINT16 RingVoltageOverride
The ring voltage override which is applied to the entire range of cpu ring frequencies.
Definition: OverclockingConfig.h:234
OVERCLOCKING_PREMEM_CONFIG::OcSupport
UINT32 OcSupport
Overclocking support.
Definition: OverclockingConfig.h:82
OVERCLOCKING_PREMEM_CONFIG::NpuVoltageMode
UINT8 NpuVoltageMode
Deprecated from Revision 13.
Definition: OverclockingConfig.h:599
OVERCLOCKING_PREMEM_CONFIG::IaIccUnlimitedMode
UINT32 IaIccUnlimitedMode
Support IA Unlimited ICCMAX up to maximum value 512A., 0: Disable. 1: Enable.
Definition: OverclockingConfig.h:139
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
OVERCLOCKING_PREMEM_CONFIG::CoreMinRatio
UINT8 CoreMinRatio
Request Core Min Ratio.
Definition: OverclockingConfig.h:592
OVERCLOCKING_PREMEM_CONFIG::CoreRatioExtensionMode
UINT32 CoreRatioExtensionMode
Enable or disable Core Ratio above 85 Extension Mode by writing BIOS MB 0x37 to enable FULL_RANGE_MUL...
Definition: OverclockingConfig.h:104
OVERCLOCKING_PREMEM_CONFIG::ForcePcoreResidency
UINT8 ForcePcoreResidency
Enable or disable Force Pcore Residency. 0: Disable, 1: enable.
Definition: OverclockingConfig.h:604
OVERCLOCKING_PREMEM_CONFIG::SaVoltageMode
UINT32 SaVoltageMode
SA/Uncore voltage mode, specifies which voltage mode the processor will be operating.
Definition: OverclockingConfig.h:125
OVERCLOCKING_PREMEM_CONFIG::NguVoltageOverride
UINT16 NguVoltageOverride
The NGU voltage override which is applied to the entire range of cpu NGU frequencies.
Definition: OverclockingConfig.h:548
OVERCLOCKING_PREMEM_CONFIG::SaIccUnlimitedMode
UINT32 SaIccUnlimitedMode
Support SA Unlimited ICCMAX up to maximum value 512A., 0: Disable. 1: Enable.
Definition: OverclockingConfig.h:293
OVERCLOCKING_PREMEM_CONFIG::ProcessVmaxLimit
UINT8 ProcessVmaxLimit
Disabling Process Vmax Limit will allow user to set any voltage.
Definition: OverclockingConfig.h:576
OVERCLOCKING_PREMEM_CONFIG::IaAtomPllVoltageOffset
UINT32 IaAtomPllVoltageOffset
IA Atom PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
Definition: OverclockingConfig.h:287
OVERCLOCKING_PREMEM_CONFIG::CpuBclkOcFrequency
UINT32 CpuBclkOcFrequency
CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz 0 - Auto....
Definition: OverclockingConfig.h:373
OVERCLOCKING_PREMEM_CONFIG::RingMaxOcRatio
UINT8 RingMaxOcRatio
Maximum ring ratio override allows to increase CPU ring frequency beyond the fused max ring ratio lim...
Definition: OverclockingConfig.h:206
OVERCLOCKING_PREMEM_CONFIG::Avx3RatioOffset
UINT32 Avx3RatioOffset
Deprecated from Revision 10.
Definition: OverclockingConfig.h:159
OVERCLOCKING_PREMEM_CONFIG::MemSSVoltageOffset
INT16 MemSSVoltageOffset
The Memory Subsystem voltage offset applied on top of all other voltage modes.
Definition: OverclockingConfig.h:424
OVERCLOCKING_PREMEM_CONFIG::SaVoltageOverride
UINT16 SaVoltageOverride
The SA/Uncore voltage override which is applied to the entire range of uncore frequencies.
Definition: OverclockingConfig.h:251
OVERCLOCKING_PREMEM_CONFIG::NpuAdaptiveVoltage
UINT16 NpuAdaptiveVoltage
Deprecated from Revision 13.
Definition: OverclockingConfig.h:601
OVERCLOCKING_PREMEM_CONFIG::CoreVoltageOverride
UINT16 CoreVoltageOverride
The core voltage override which is applied to the entire range of cpu core frequencies.
Definition: OverclockingConfig.h:217
OVERCLOCKING_PREMEM_CONFIG::SocDieSscEnable
UINT8 SocDieSscEnable
Enable or Disable Soc Die SSC configuration.
Definition: OverclockingConfig.h:526
OVERCLOCKING_PREMEM_CONFIG::NpuVoltageOffset
INT16 NpuVoltageOffset
Deprecated from Revision 13.
Definition: OverclockingConfig.h:602
OVERCLOCKING_PREMEM_CONFIG::CoreVoltageMode
UINT32 CoreVoltageMode
Core voltage mode, specifies which voltage mode the processor will be operating.
Definition: OverclockingConfig.h:88
OVERCLOCKING_PREMEM_CONFIG::CoreVfConfigScope
UINT32 CoreVfConfigScope
Core VF Configuration Scope.
Definition: OverclockingConfig.h:102
OVERCLOCKING_PREMEM_CONFIG::MemSSAdaptiveVoltage
UINT16 MemSSAdaptiveVoltage
Adaptive voltage target used to define the interpolation voltage point when the cpu is operating in a...
Definition: OverclockingConfig.h:401
OVERCLOCKING_PREMEM_CONFIG::MemSSVfPointOffsetMode
UINT8 MemSSVfPointOffsetMode
Selects Memory Subsystem Voltage & Frequency Point Offset between Legacy and Selection modes.
Definition: OverclockingConfig.h:414
OVERCLOCKING_PREMEM_CONFIG::NguRatio
UINT8 NguRatio
Sets the Ratio for NGU using SAVG B2P Mailbox cmd 0x22 and subcommand 0x1.
Definition: OverclockingConfig.h:542
OVERCLOCKING_PREMEM_CONFIG::EcoreTvbTempThreshold1
UINT8 EcoreTvbTempThreshold1
Temperature Threshold 1 for all Ecores (in degrees C).
Definition: OverclockingConfig.h:457
OVERCLOCKING_PREMEM_CONFIG::BclkAdaptiveVoltage
UINT32 BclkAdaptiveVoltage
Bclk Adaptive Voltage enable/disable. 0: Disabled, 1: Enabled. When enabled, the CPU V/F curves are a...
Definition: OverclockingConfig.h:156
OVERCLOCKING_PREMEM_CONFIG::McPllVoltageOffset
UINT32 McPllVoltageOffset
Memory Controller PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
Definition: OverclockingConfig.h:288
OVERCLOCKING_PREMEM_CONFIG::PcorePowerDensityThrottle
UINT8 PcorePowerDensityThrottle
Pcore Power Density Throttle control allows user to disable P-core throttling for power density prote...
Definition: OverclockingConfig.h:582
OVERCLOCKING_PREMEM_CONFIG::TvbVoltageOptimization
UINT32 TvbVoltageOptimization
This service controls thermal based voltage optimizations for processors that implement the Intel The...
Definition: OverclockingConfig.h:138
OVERCLOCKING_PREMEM_CONFIG::DisablePerCoreMask
UINT64 DisablePerCoreMask
Core disable mask is a bitwise indication of which core should be disabled, while ActiveCoreCount is ...
Definition: OverclockingConfig.h:302
OVERCLOCKING_PREMEM_CONFIG::RingPllCurrentRefTuningOffset
UINT8 RingPllCurrentRefTuningOffset
Deprecated from Revision 11.
Definition: OverclockingConfig.h:587
OVERCLOCKING_PREMEM_CONFIG::TvbConfigLimitSelect
UINT8 TvbConfigLimitSelect
Limits Select, 0 - Per CCP (Module), Command Param2 = CCP ID, CCP ID can range from 0-15.
Definition: OverclockingConfig.h:464
OVERCLOCKING_PREMEM_CONFIG::SaVoltageOffset
INT16 SaVoltageOffset
The voltage offset applied to the SA. Valid range from -1000mv to 1000mv: 0=Default
Definition: OverclockingConfig.h:283
OVERCLOCKING_PREMEM_CONFIG::NguVfPointCount
UINT8 NguVfPointCount
Number of supported NGU Voltage & Frequency Point.
Definition: OverclockingConfig.h:562
OVERCLOCKING_PREMEM_CONFIG::ComputeDieSscEnable
UINT8 ComputeDieSscEnable
Enable or Disable Compute Die SSC configuration.
Definition: OverclockingConfig.h:519
OVERCLOCKING_PREMEM_CONFIG::GtVoltageMode
UINT32 GtVoltageMode
Specifies whether GT voltage is operating in Adaptive or Override mode: 0=Adaptive,...
Definition: OverclockingConfig.h:119
OVERCLOCKING_PREMEM_CONFIG::NguVoltageOffset
INT16 NguVoltageOffset
The NGU voltage offset applied on top of all other voltage modes.
Definition: OverclockingConfig.h:554
OVERCLOCKING_PREMEM_CONFIG::CorePllVoltageOffset
UINT32 CorePllVoltageOffset
Core PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
Definition: OverclockingConfig.h:284
OVERCLOCKING_PREMEM_CONFIG::TscDisableHwFixup
UINT32 TscDisableHwFixup
Core HW Fixup disable during TSC copy from PMA to APIC, 0: Enable. 1: Disable.
Definition: OverclockingConfig.h:292
OVERCLOCKING_PREMEM_CONFIG::VrLimitBypass
UINT8 VrLimitBypass
Enable or disable VR Limit Bypass. 0: Disable, 1: enable.
Definition: OverclockingConfig.h:605
OVERCLOCKING_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: OverclockingConfig.h:74
OVERCLOCKING_PREMEM_CONFIG::RingVfPointOffsetMode
UINT8 RingVfPointOffsetMode
Selects Ring Voltage & Frequency Point Offset between Legacy and Selection modes.
Definition: OverclockingConfig.h:323
OVERCLOCKING_PREMEM_CONFIG::RingTurboThermalProtection
UINT8 RingTurboThermalProtection
Ring Turbo Thermal Protection (TTP) control which allows user to disable Turbo Thermal Protection for...
Definition: OverclockingConfig.h:506
OVERCLOCKING_PREMEM_CONFIG::SaPllVoltageOffset
UINT32 SaPllVoltageOffset
SOC System Agent PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
Definition: OverclockingConfig.h:286
OVERCLOCKING_PREMEM_CONFIG::CoreVoltageOffset
INT16 CoreVoltageOffset
The core voltage offset applied on top of all other voltage modes.
Definition: OverclockingConfig.h:228
OVERCLOCKING_PREMEM_CONFIG::PerCoreRatioOverride
UINT32 PerCoreRatioOverride
Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new favored core ratio...
Definition: OverclockingConfig.h:103
OVERCLOCKING_PREMEM_CONFIG::PerCoreDisableConfiguration
UINT8 PerCoreDisableConfiguration
This configuration allows OC user to either use legacy num of cores option or the OC specific per cor...
Definition: OverclockingConfig.h:596
OVERCLOCKING_PREMEM_CONFIG::RingVoltageMode
UINT32 RingVoltageMode
Ring voltage mode, specifies which voltage mode the processor will be operating.
Definition: OverclockingConfig.h:118
OVERCLOCKING_PREMEM_CONFIG::GtVfPointCount
UINT8 GtVfPointCount
Number of supported GR Voltage & Frequency Point.
Definition: OverclockingConfig.h:275
OVERCLOCKING_PREMEM_CONFIG::CpuDlvrMode
UINT32 CpuDlvrMode
Select Core(s) and RING DLVR Mode, 0: Regulation Mode. 1: Power Gate Mode.
Definition: OverclockingConfig.h:290
OVERCLOCKING_PREMEM_CONFIG::RingPllVoltageOffset
UINT32 RingPllVoltageOffset
Ring PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
Definition: OverclockingConfig.h:285
OVERCLOCKING_PREMEM_CONFIG::GtIccUnlimitedMode
UINT32 GtIccUnlimitedMode
Support GT Unlimited ICCMAX up to maximum value 512A., 0: Disable. 1: Enable.
Definition: OverclockingConfig.h:140
OVERCLOCKING_PREMEM_CONFIG::MemSSVoltageOverride
UINT16 MemSSVoltageOverride
The Memory Subsystem voltage override which is applied to the entire range of uncore frequencies.
Definition: OverclockingConfig.h:407
OVERCLOCKING_PREMEM_CONFIG::CoreMaxOcRatio
UINT8 CoreMaxOcRatio
Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ra...
Definition: OverclockingConfig.h:200
OVERCLOCKING_PREMEM_CONFIG::TvbRatioClipping
UINT32 TvbRatioClipping
This service controls Core frequency reduction caused by high package temperatures for processors tha...
Definition: OverclockingConfig.h:132
OVERCLOCKING_PREMEM_CONFIG::TjMaxOffset
UINT8 TjMaxOffset
TjMax Offset.
Definition: OverclockingConfig.h:211
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
OVERCLOCKING_PREMEM_CONFIG::OcTvb
UINT8 OcTvb
OC TVB Enable/Disable.
Definition: OverclockingConfig.h:433
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: P2sbConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • P2sb
Classes
P2sbConfig.h File Reference

P2sb policy. More...

Go to the source code of this file.

Classes

struct PCH_P2SB_CONFIG
This structure contains the policies which are related to P2SB device. More...

Detailed Description

P2sb policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file P2sbConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: P2sbConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • P2sb
P2sbConfig.h
Go to the documentation of this file.
1 /** @file
2 P2sb policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _P2SB_CONFIG_H_
36 #define _P2SB_CONFIG_H_
37
38 #define PCH_P2SB_CONFIG_REVISION 1
39 extern EFI_GUID gP2sbConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 This structure contains the policies which are related to P2SB device.
45 **/
46 typedef struct {
47 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
48 /**
49 <b>(Test)</b>
50 The sideband MMIO register access to specific ports will be locked
51 before 3rd party code execution. Currently it disables PSFx access.
52 This policy unlocks the sideband MMIO space for those IPs.
53 <b>0: Lock sideband access </b>; 1: Unlock sideband access.
54 NOTE: Do not set this policy "SbAccessUnlock" unless its necessary.
55 **/
56 UINT32 SbAccessUnlock : 1;
57 UINT32 Rsvdbits : 31; ///< Reserved bits
58 } PCH_P2SB_CONFIG;
59
60 #pragma pack (pop)
61
62 #endif // _P2SB_CONFIG_H_
PCH_P2SB_CONFIG
This structure contains the policies which are related to P2SB device.
Definition: P2sbConfig.h:46
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_P2SB_CONFIG::Rsvdbits
UINT32 Rsvdbits
Reserved bits.
Definition: P2sbConfig.h:57
PCH_P2SB_CONFIG::SbAccessUnlock
UINT32 SbAccessUnlock
(Test) The sideband MMIO register access to specific ports will be locked before 3rd party code execu...
Definition: P2sbConfig.h:56
PCH_P2SB_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: P2sbConfig.h:47
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PchDmiConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PchDmi
Classes
PchDmiConfig.h File Reference

DMI policy. More...

Go to the source code of this file.

Classes

struct PCH_DMI_CONFIG
The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI. More...

Detailed Description

DMI policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchDmiConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PchDmiConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PchDmi
PchDmiConfig.h
Go to the documentation of this file.
1 /** @file
2 DMI policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_DMI_CONFIG_H_
36 #define _PCH_DMI_CONFIG_H_
37
38 #define PCH_DMI_CONFIG_REVISION 1
39 extern EFI_GUID gPchDmiConfigGuid;
40
41
42 #pragma pack (push,1)
43
44
45 /**
46 The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI.
47 <b>Revision 1</b>:
48 - Initial version.
49 **/
50 typedef struct {
51 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
52
53 UINT32 PwrOptEnable : 1; ///< <b>0: Disable</b>; 1: Enable DMI Power Optimizer on PCH side.
54 UINT32 DmiAspmCtrl : 8; ///< ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
55 UINT32 CwbEnable : 1; ///< 0: Disable; <b>1: Enable</b> Central Write Buffer feature configurable and enabled by default
56 UINT32 L1RpCtl : 1; ///< 0: Disable; <b>1: Enable</b> Allow DMI enter L1 when all root ports are in L1, L0s or link down. Disabled by default.
57 /**
58 When set to TRUE turns on:
59 - L1 State Controller Power Gating
60 - L1 State PHY Data Lane Power Gating
61 - PHY Common Lane Power Gating
62 - Hardware Autonomous Enable
63 - PMC Request Enable and Sleep Enable
64 **/
65 UINT32 DmiPowerReduction : 1;
66 UINT32 ClockGating : 1; ///< 0: Disable; 1: Enable clock gating.
67 UINT32 Rsvdbits : 19; ///< Reserved bits
68 } PCH_DMI_CONFIG;
69
70 #pragma pack (pop)
71
72 #endif // _PCH_DMI_CONFIG_H_
PCH_DMI_CONFIG::PwrOptEnable
UINT32 PwrOptEnable
0: Disable; 1: Enable DMI Power Optimizer on PCH side.
Definition: PchDmiConfig.h:53
PCH_DMI_CONFIG::DmiAspmCtrl
UINT32 DmiAspmCtrl
ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig
Definition: PchDmiConfig.h:54
PCH_DMI_CONFIG
The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI.
Definition: PchDmiConfig.h:50
PCH_DMI_CONFIG::Rsvdbits
UINT32 Rsvdbits
Reserved bits.
Definition: PchDmiConfig.h:67
PCH_DMI_CONFIG::DmiPowerReduction
UINT32 DmiPowerReduction
When set to TRUE turns on:
Definition: PchDmiConfig.h:65
PCH_DMI_CONFIG::CwbEnable
UINT32 CwbEnable
0: Disable; 1: Enable Central Write Buffer feature configurable and enabled by default
Definition: PchDmiConfig.h:55
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_DMI_CONFIG::ClockGating
UINT32 ClockGating
0: Disable; 1: Enable clock gating.
Definition: PchDmiConfig.h:66
PCH_DMI_CONFIG::L1RpCtl
UINT32 L1RpCtl
0: Disable; 1: Enable Allow DMI enter L1 when all root ports are in L1, L0s or link down....
Definition: PchDmiConfig.h:56
PCH_DMI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PchDmiConfig.h:51
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PchGeneralConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • ConfigBlock
Classes | Macros | Enumerations
PchGeneralConfig.h File Reference

PCH General policy. More...

Go to the source code of this file.

Classes

struct PCH_GENERAL_CONFIG
PCH General Configuration Revision 2: - Add VtdEnabled field. More...

Macros

#define | PCH_GENERAL_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.
#define | PCH_GENERAL_PREMEM_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Enumerations

enum PCH_RESERVED_PAGE_ROUTE

Detailed Description

PCH General policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchGeneralConfig.h.

Enumeration Type Documentation

◆ PCH_RESERVED_PAGE_ROUTE

enum PCH_RESERVED_PAGE_ROUTE
Enumerator
PchReservedPageToLpc | Port 80h cycles are sent to LPC.
PchReservedPageToPcie | Port 80h cycles are sent to PCIe.

Definition at line 58 of file PchGeneralConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PchGeneralConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • ConfigBlock
PchGeneralConfig.h
Go to the documentation of this file.
1 /** @file
2 PCH General policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_GENERAL_CONFIG_H_
36 #define _PCH_GENERAL_CONFIG_H_
37
38 /**
39 Making any structure change after API Lock
40 will need to maintain backward compatibility, bump up
41 structure revision and update below history table\n
42 <b>Revision 1</b>: - Initial version.
43 **/
44 #define PCH_GENERAL_CONFIG_REVISION 1
45 /**
46 Making any structure change after API Lock
47 will need to maintain backward compatibility, bump up
48 structure revision and update below history table\n
49 <b>Revision 1</b>: - Initial version.
50 **/
51 #define PCH_GENERAL_PREMEM_CONFIG_REVISION 1
52
53 extern EFI_GUID gPchGeneralConfigGuid;
54 extern EFI_GUID gPchGeneralPreMemConfigGuid;
55
56 #pragma pack (push,1)
57
58 enum PCH_RESERVED_PAGE_ROUTE {
59 PchReservedPageToLpc, ///< Port 80h cycles are sent to LPC.
60 PchReservedPageToPcie ///< Port 80h cycles are sent to PCIe.
61 };
62
63 /**
64 PCH General Configuration
65 <b>Revision 2</b>: - Add VtdEnabled field.
66 **/
67 typedef struct {
68 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
69 /**
70 This member describes whether or not the Compatibility Revision ID (CRID) feature
71 of PCH should be enabled. <b>0: Disable</b>; 1: Enable
72 **/
73 UINT32 Crid : 1;
74 /**
75 Set to enable low latency of legacy IO.
76 Some systems require lower IO latency irrespective of power.
77 This is a tradeoff between power and IO latency.
78 @note: Once this is enabled, DmiAspm, Pcie DmiAspm in SystemAgent
79 and ITSS Clock Gating are forced to disabled.
80 <b>0: Disable</b>, 1: Enable
81 **/
82 UINT32 LegacyIoLowLatency : 1;
83 /**
84 This member describes whether or not the VTD feature
85 should be enabled in PCH. <b>0: Disable</b>; 1: Enable
86 **/
87 UINT32 VtdEnabled : 1;
88 UINT32 RsvdBits0 : 29; ///< Reserved bits
89 } PCH_GENERAL_CONFIG;
90
91 typedef struct {
92 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
93 /**
94 Control where the Port 80h cycles are sent, <b>0: LPC</b>; 1: PCI.
95 **/
96 UINT32 Port80Route : 1;
97 UINT32 IotgPllSscEn : 1; ///< Need to disable CPU Side SSC for A0 PO
98 /**
99 Gpio override Level
100 -- <b>0: Disable</b>;
101 - 1: Override Level 1 - Skips GPIO configuration in PEI/FSPM/FSPT phase
102 - 2: Override Level 2 - Reserved for future use
103 **/
104 UINT32 GpioOverride : 3;
105 /**
106 Enable/Disable IOE Debug. When enabled, IOE D2D Dfx link and clock will keep up for debug
107 <b>0: Disable</b>; 1: Enable
108 **/
109 UINT32 IoeDebugEn : 1;
110 /**
111 Enable/Disable PMODE clock. When enabled, Pmode clock will toggle for XDP use
112 <b>0: Disable</b>; 1: Enable
113 **/
114 UINT32 PmodeClkEn : 1;
115 UINT32 RsvdBits0 : 25; ///< Reserved bits
116 } PCH_GENERAL_PREMEM_CONFIG;
117
118 #pragma pack (pop)
119
120 #endif // _PCH_GENERAL_CONFIG_H_
PCH_RESERVED_PAGE_ROUTE
PCH_RESERVED_PAGE_ROUTE
Definition: PchGeneralConfig.h:58
PCH_GENERAL_CONFIG::LegacyIoLowLatency
UINT32 LegacyIoLowLatency
Set to enable low latency of legacy IO.
Definition: PchGeneralConfig.h:82
PCH_GENERAL_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PchGeneralConfig.h:68
PCH_GENERAL_CONFIG::Crid
UINT32 Crid
This member describes whether or not the Compatibility Revision ID (CRID) feature of PCH should be en...
Definition: PchGeneralConfig.h:73
PchReservedPageToPcie
@ PchReservedPageToPcie
Port 80h cycles are sent to PCIe.
Definition: PchGeneralConfig.h:60
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_GENERAL_CONFIG::VtdEnabled
UINT32 VtdEnabled
This member describes whether or not the VTD feature should be enabled in PCH.
Definition: PchGeneralConfig.h:87
PchReservedPageToLpc
@ PchReservedPageToLpc
Port 80h cycles are sent to LPC.
Definition: PchGeneralConfig.h:59
PCH_GENERAL_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: PchGeneralConfig.h:88
PCH_GENERAL_CONFIG
PCH General Configuration Revision 2: - Add VtdEnabled field.
Definition: PchGeneralConfig.h:67
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PchPcieRpConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PcieRp
  • PchPcieRp
Classes | Macros | Enumerations
PchPcieRpConfig.h File Reference

PCH Pcie root port policy. More...

#include <PchLimits.h>
#include <PcieConfig.h>
#include <ConfigBlock.h>
Include dependency graph for PchPcieRpConfig.h:

Go to the source code of this file.

Classes

struct | PCH_PCIE_CLOCK
PCH_PCIE_CLOCK describes PCIe source clock generated by PCH. More...
struct | DMI_LANE_CONFIG
The PCH_DMI_LANE_CONFIG block describes specific lane configuration. More...
struct | PCH_PCIE_ROOT_PORT_CONFIG
The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port. More...
struct | PCH_PCIE_CONFIG
The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers Revision 1: More...
struct | PCH_PCIE_RP_PREMEM_CONFIG
The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers Revision 1: More...
struct | PCIE_RP_DXE_CONFIG
The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers in DXE phase. More...

Macros

#define | PCH_PCIE_CONFIG_REVISION 2
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version. More...
#define | PCH_PCIE_RP_PREMEM_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.
#define | PCIE_RP_DXE_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Enumerations

enum | PCH_PCIE_ASPM_CONTROL
The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature.
enum | PCH_PCIE_L1SUBSTATES_CONTROL
Refer to PCH EDS for the PCH implementation values corresponding to below PCI-E spec defined ranges.
enum | PCH_PCIE_CLOCK_USAGE

Detailed Description

PCH Pcie root port policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchPcieRpConfig.h.

Macro Definition Documentation

◆ PCH_PCIE_CONFIG_REVISION

#define PCH_PCIE_CONFIG_REVISION 2

Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Revision 2:

  • Moved EnablePort8xhDecode policy to PCIE_COMMON_CONFIG
  • Add DmiPowerGatingDis

Definition at line 51 of file PchPcieRpConfig.h.

Enumeration Type Documentation

◆ PCH_PCIE_CLOCK_USAGE

enum PCH_PCIE_CLOCK_USAGE
Enumerator
PchClockUsageCpuPcie0

Quantity of PCH and CPU PCIe ports, as well as their encoding in this enum, may change between silicon generations and series.

Do not assume that PCH port 0 will be always encoded by 0. Instead, it is recommended to use (PchClockUsagePchPcie0 + PchPortIndex) style to be forward-compatible

PchClockUsageUnspecified

In use for a purpose not listed above.

Definition at line 116 of file PchPcieRpConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PchPcieRpConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PcieRp
  • PchPcieRp
PchPcieRpConfig.h
Go to the documentation of this file.
1 /** @file
2 PCH Pcie root port policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_PCIERP_CONFIG_H_
36 #define _PCH_PCIERP_CONFIG_H_
37
38 #include <PchLimits.h>
39 #include <PcieConfig.h>
40 #include <ConfigBlock.h>
41
42 /**
43 Making any structure change after API Lock
44 will need to maintain backward compatibility, bump up
45 structure revision and update below history table\n
46 <b>Revision 1</b>: - Initial version.
47 <b>Revision 2</b>:
48 - Moved EnablePort8xhDecode policy to PCIE_COMMON_CONFIG
49 - Add DmiPowerGatingDis
50 **/
51 #define PCH_PCIE_CONFIG_REVISION 2
52
53 /**
54 Making any structure change after API Lock
55 will need to maintain backward compatibility, bump up
56 structure revision and update below history table\n
57 <b>Revision 1</b>: - Initial version.
58 **/
59 #define PCH_PCIE_RP_PREMEM_CONFIG_REVISION 1
60
61 /**
62 Making any structure change after API Lock
63 will need to maintain backward compatibility, bump up
64 structure revision and update below history table\n
65 <b>Revision 1</b>: - Initial version.
66 **/
67 #define PCIE_RP_DXE_CONFIG_REVISION 1
68
69 extern EFI_GUID gPchPcieConfigGuid;
70 extern EFI_GUID gPcieRpPreMemConfigGuid;
71
72 #pragma pack (push,1)
73
74 typedef enum {
75 PchPcieOverrideDisabled = 0,
76 PchPcieL1L2Override = 0x01,
77 PchPcieL1SubstatesOverride = 0x02,
78 PchPcieL1L2AndL1SubstatesOverride = 0x03,
79 PchPcieLtrOverride = 0x04
80 } PCH_PCIE_OVERRIDE_CONFIG;
81
82 ///
83 /// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
84 ///
85 typedef enum {
86 PchPcieAspmDisabled,
87 PchPcieAspmL0s,
88 PchPcieAspmL1,
89 PchPcieAspmL0sL1,
90 PchPcieAspmAutoConfig,
91 PchPcieAspmMax
92 } PCH_PCIE_ASPM_CONTROL;
93
94 /**
95 Refer to PCH EDS for the PCH implementation values corresponding
96 to below PCI-E spec defined ranges
97 **/
98 typedef enum {
99 PchPcieL1SubstatesDisabled,
100 PchPcieL1SubstatesL1_1,
101 PchPcieL1SubstatesL1_1_2,
102 PchPcieL1SubstatesMax
103 } PCH_PCIE_L1SUBSTATES_CONTROL;
104
105 enum PCH_PCIE_MAX_PAYLOAD {
106 PchPcieMaxPayload128 = 0,
107 PchPcieMaxPayload256,
108 PchPcieMaxPayload512,
109 PchPcieMaxPayload64 = 7,
110 PchPcieMaxPayloadMax
111 };
112
113 #define PCH_PCIE_NO_SUCH_CLOCK 0xFF
114 #define PCH_PCIE_NO_GPIO_MUXING 0x00
115
116 typedef enum {
117 PchClockUsagePchPcie0 = 0,
118 PchClockUsagePchPcie1 = 1,
119 PchClockUsagePchPcie2 = 2,
120 PchClockUsagePchPcie3 = 3,
121 PchClockUsagePchPcie4 = 4,
122 PchClockUsagePchPcie5 = 5,
123 PchClockUsagePchPcie6 = 6,
124 PchClockUsagePchPcie7 = 7,
125 PchClockUsagePchPcie8 = 8,
126 PchClockUsagePchPcie9 = 9,
127 PchClockUsagePchPcie10 = 10,
128 PchClockUsagePchPcie11 = 11,
129 PchClockUsagePchPcie12 = 12,
130 PchClockUsagePchPcie13 = 13,
131 PchClockUsagePchPcie14 = 14,
132 PchClockUsagePchPcie15 = 15,
133 PchClockUsagePchPcie16 = 16,
134 PchClockUsagePchPcie17 = 17,
135 PchClockUsagePchPcie18 = 18,
136 PchClockUsagePchPcie19 = 19,
137 PchClockUsagePchPcie20 = 20,
138 PchClockUsagePchPcie21 = 21,
139 PchClockUsagePchPcie22 = 22,
140 PchClockUsagePchPcie23 = 23,
141 /**
142 Quantity of PCH and CPU PCIe ports, as well as their encoding in this enum, may change between
143 silicon generations and series. Do not assume that PCH port 0 will be always encoded by 0.
144 Instead, it is recommended to use (PchClockUsagePchPcie0 + PchPortIndex) style to be forward-compatible
145 **/
146 PchClockUsageCpuPcie0 = 0x40,
147 PchClockUsageCpuPcie1 = 0x41,
148 PchClockUsageCpuPcie2 = 0x42,
149 PchClockUsageCpuPcie3 = 0x43,
150
151 PchClockUsageLan = 0x70,
152 PchClockUsageUnspecified = 0x80, ///< In use for a purpose not listed above
153 PchClockUsageNotUsed = 0xFF
154 } PCH_PCIE_CLOCK_USAGE;
155
156 /**
157 PCH_PCIE_CLOCK describes PCIe source clock generated by PCH.
158 **/
159 typedef struct {
160 UINT8 Usage; ///< Purpose of given clock (see PCH_PCIE_CLOCK_USAGE). Default: Unused, 0xFF
161 UINT8 ClkReq; ///< ClkSrc - ClkReq mapping. Default: 1:1 mapping with Clock numbers
162 UINT8 RsvdBytes[2]; ///< Reserved byte
163 UINT32 ClkReqGpioPinMux; /// Muxed GPIO details. Refer GPIO_*_MUXING_SRC_CLKREQ_x*
164 } PCH_PCIE_CLOCK;
165
166 ///
167 /// The PCH_DMI_LANE_CONFIG block describes specific lane configuration
168 ///
169 typedef struct {
170 UINT32 DmiTranCoOverEn : 2; ///< Enable/Disable Lane Transmitter Coefficient
171 UINT32 Rsvd1 : 6; ///< Reserved
172 UINT32 DmiTranCoOverPostCur : 6; ///< Lane Transmitter Post-Cursor Coefficient Override
173 UINT32 Rsvd2 : 2; ///< Reserved
174 UINT32 DmiTranCoOverPreCur : 6; ///< Lane Transmitter Pre-Cursor Coefficient Override
175 UINT32 Rsvd3 : 2; ///< Reserved
176 UINT32 DmiUpPortTranPreset : 4; ///< Upstream Port Lane Transmitter Preset
177 UINT32 Rsvd4 : 4; ///< Reserved
178 } DMI_LANE_CONFIG;
179
180 typedef struct {
181 DMI_LANE_CONFIG Lane[PCH_MAX_DMI_LANES]; ///< DMI Lanes configuration
182 DMI_LANE_CONFIG LaneGen4[PCH_MAX_DMI_LANES]; ///< DMI Lanes configuration
183 UINT32 DmiUpPortTranPresetEn : 2; ///< 0: POR setting, 1: force enable, 2: force disable.
184 UINT32 DmiRtlepceb : 2; ///< DMI Remote Transmit Link Equalization Preset/Coefficient Evaluation Bypass (RTLEPCEB)
185 /**
186 When CNP is paired with SKL CPU, TX SAI Filtering Check performed for cycles
187 targeting MEUMA (ie. VCm upstream). As part of this check,
188 IOSF Root Space attribute is check to ensure that it is RS3.
189 Setting valid only when DMI VCm is enabled.
190 0: POR setting, 1: force enable, 2: force disable.
191 */
192 UINT32 TestDmiMeUmaRootSpaceCheck : 2;
193 UINT32 Rsvdbits : 26;
194 UINT8 MvcEnabled; ///< Enable/Disable MultiVC Option. 0: Disable; 1: Enable
195 UINT8 Reserved[3];
196 } DMI_PREMEM_CONFIG;
197
198 /**
199 The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port.
200 **/
201 typedef struct {
202 PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; ///an instance of Pcie Common Config
203 UINT8 ExtSync; ///< Indicate whether the extended synch is enabled. <b>0: Disable</b>; 1: Enable.
204 //
205 // Error handlings
206 //
207 UINT8 SystemErrorEnable; ///< Indicate whether the System Error is enabled. <b>0: Disable</b>; 1: Enable.
208 /**
209 The Multiple VC (MVC) supports hardware to avoid HoQ block for latency sensitive TC.
210 Currently it is only applicable to Root Ports with 2pX4 port configuration with 2 VCs,or
211 DMI port configuration with 3 VCs. For Root Ports 2pX4 configuration, two RPs (RP0,
212 RP2) shall support two PCIe VCs (VC0 & VC1) and the other RPs (RP1, RP3) shall be
213 disabled.
214 <b>0: Disable</b>; 1: Enable
215 **/
216 UINT8 MvcEnabled;
217 /**
218 Virtual Pin Port is industry standard introduced to PCIe Hot Plug support in systems
219 when GPIO pins expansion is needed. It is server specific feature.
220 <b>0x00: Default</b>; 0xFF: Disabled
221 **/
222 UINT8 VppPort;
223 UINT8 VppAddress; ///< PCIe Hot Plug VPP SMBus Address. Default is zero.
224 UINT8 MultiVc;
225 UINT8 Vc1Ctrl;
226 UINT8 VcMCtrl;
227 UINT8 MeUmaRootSpaceCheck;
228 UINT8 RsvdBytes0[3]; ///< Reserved bytes
229 } PCH_PCIE_ROOT_PORT_CONFIG;
230
231 /**
232 The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers
233 <b>Revision 1</b>:
234 - Initial version.
235 <b>Revision 2</b>:
236 - Moved EnablePort8xhDecode policy to PCIE_COMMON_CONFIG
237 <b>Revision 3</b>:
238 - Add DmiPowerGatingDis
239 **/
240 typedef struct {
241 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
242 ///
243 /// These members describe the configuration of each PCH PCIe root port.
244 ///
245 PCIE_COMMON_CONFIG PcieCommonConfig;
246 PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS];
247 PCH_PCIE_ROOT_PORT_CONFIG DmiPort;
248
249 ///
250 /// <b>(Test)</b> The Index of PCIe Port that is selected for Port8xh Decode (0 Based)
251 ///
252 UINT8 PchPciePort8xhDecodePortIndex;
253 UINT8 DmiPowerReduction;
254 UINT8 DmiPowerGatingDis;
255 UINT8 RsvdBytes0;
256 } PCH_PCIE_CONFIG;
257
258 /**
259 The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers
260 <b>Revision 1</b>:
261 - Initial version.
262 **/
263 typedef struct {
264 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
265 /**
266 Root Port enabling mask.
267 Bit0 presents RP1, Bit1 presents RP2, and so on.
268 0: Disable; <b>1: Enable</b>.
269 **/
270 UINT32 RpEnabledMask;
271 /// Configuration of PCIe source clocks
272 ///
273 PCH_PCIE_CLOCK PcieClock[PCH_MAX_PCIE_CLOCKS];
274
275 /**
276 Per Controller Bifurcation Configuration
277 <b>0: Disabled</b>; 1: 4x1; 2: 1x2_2x1; 3: 2x2; 4: 1x4; 5: 4x2; 6: 1x4_2x2; 7: 2x2_1x4; 8: 2x4; 9: 1x8 (see: PCIE_BIFURCATION_CONFIG)
278 **/
279 UINT8 Bifurcation[PCH_MAX_PCIE_CONTROLLERS];
280 UINT8 Rsvd[(4 - PCH_MAX_PCIE_CONTROLLERS % 4)];
281 DMI_PREMEM_CONFIG PchDmiPrememConfig;
282 } PCH_PCIE_RP_PREMEM_CONFIG;
283
284 /**
285 The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers in DXE phase
286
287 <b>Revision 1</b>:
288 - Init version
289 **/
290 typedef struct {
291 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
292
293 /**
294 PCIe device override table
295 The PCIe device table is being used to override PCIe device ASPM settings.
296 And it's only used in DXE phase.
297 Please refer to PCIE_DEVICE_OVERRIDE structure for the table.
298 Last entry VendorId must be 0.
299 **/
300 PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;
301 } PCIE_RP_DXE_CONFIG;
302
303 #pragma pack (pop)
304
305 #endif // _PCH_PCIERP_CONFIG_H_
PCH_PCIE_CLOCK::ClkReq
UINT8 ClkReq
ClkSrc - ClkReq mapping. Default: 1:1 mapping with Clock numbers.
Definition: PchPcieRpConfig.h:161
DMI_LANE_CONFIG::Rsvd2
UINT32 Rsvd2
Reserved.
Definition: PchPcieRpConfig.h:173
PCH_PCIE_CLOCK::Usage
UINT8 Usage
Purpose of given clock (see PCH_PCIE_CLOCK_USAGE). Default: Unused, 0xFF.
Definition: PchPcieRpConfig.h:160
PCIE_RP_DXE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PchPcieRpConfig.h:291
PCH_PCIE_CONFIG::PchPciePort8xhDecodePortIndex
UINT8 PchPciePort8xhDecodePortIndex
(Test) The Index of PCIe Port that is selected for Port8xh Decode (0 Based)
Definition: PchPcieRpConfig.h:252
ConfigBlock.h
Header file for Config Block Lib implementation.
DMI_LANE_CONFIG
The PCH_DMI_LANE_CONFIG block describes specific lane configuration.
Definition: PchPcieRpConfig.h:169
PCH_PCIE_CONFIG::PcieCommonConfig
PCIE_COMMON_CONFIG PcieCommonConfig
These members describe the configuration of each PCH PCIe root port.
Definition: PchPcieRpConfig.h:245
PCH_PCIE_ROOT_PORT_CONFIG::ExtSync
UINT8 ExtSync
an instance of Pcie Common Config
Definition: PchPcieRpConfig.h:203
PCH_PCIE_CLOCK
PCH_PCIE_CLOCK describes PCIe source clock generated by PCH.
Definition: PchPcieRpConfig.h:159
PCH_PCIE_L1SUBSTATES_CONTROL
PCH_PCIE_L1SUBSTATES_CONTROL
Refer to PCH EDS for the PCH implementation values corresponding to below PCI-E spec defined ranges.
Definition: PchPcieRpConfig.h:98
DMI_LANE_CONFIG::DmiTranCoOverPostCur
UINT32 DmiTranCoOverPostCur
Lane Transmitter Post-Cursor Coefficient Override.
Definition: PchPcieRpConfig.h:172
DMI_LANE_CONFIG::DmiUpPortTranPreset
UINT32 DmiUpPortTranPreset
Upstream Port Lane Transmitter Preset.
Definition: PchPcieRpConfig.h:176
PCH_PCIE_ASPM_CONTROL
PCH_PCIE_ASPM_CONTROL
The values before AutoConfig match the setting of PCI Express Base Specification 1....
Definition: PchPcieRpConfig.h:85
PchClockUsageUnspecified
@ PchClockUsageUnspecified
In use for a purpose not listed above.
Definition: PchPcieRpConfig.h:152
PCH_PCIE_ROOT_PORT_CONFIG::VppAddress
UINT8 VppAddress
PCIe Hot Plug VPP SMBus Address. Default is zero.
Definition: PchPcieRpConfig.h:223
DMI_LANE_CONFIG::Rsvd1
UINT32 Rsvd1
Reserved.
Definition: PchPcieRpConfig.h:171
DMI_LANE_CONFIG::DmiTranCoOverPreCur
UINT32 DmiTranCoOverPreCur
Lane Transmitter Pre-Cursor Coefficient Override.
Definition: PchPcieRpConfig.h:174
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
DMI_LANE_CONFIG::DmiTranCoOverEn
UINT32 DmiTranCoOverEn
Enable/Disable Lane Transmitter Coefficient.
Definition: PchPcieRpConfig.h:170
PchClockUsageCpuPcie0
@ PchClockUsageCpuPcie0
Quantity of PCH and CPU PCIe ports, as well as their encoding in this enum, may change between silico...
Definition: PchPcieRpConfig.h:146
PCH_PCIE_ROOT_PORT_CONFIG::SystemErrorEnable
UINT8 SystemErrorEnable
Indicate whether the System Error is enabled. 0: Disable; 1: Enable.
Definition: PchPcieRpConfig.h:207
PCH_PCIE_CONFIG
The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers Rev...
Definition: PchPcieRpConfig.h:240
PCIE_RP_DXE_CONFIG
The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers ...
Definition: PchPcieRpConfig.h:290
DMI_LANE_CONFIG::Rsvd4
UINT32 Rsvd4
Reserved.
Definition: PchPcieRpConfig.h:177
PCH_PCIE_ROOT_PORT_CONFIG
The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port.
Definition: PchPcieRpConfig.h:201
PCH_PCIE_RP_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PchPcieRpConfig.h:264
PCH_PCIE_ROOT_PORT_CONFIG::VppPort
UINT8 VppPort
Virtual Pin Port is industry standard introduced to PCIe Hot Plug support in systems when GPIO pins e...
Definition: PchPcieRpConfig.h:222
DMI_LANE_CONFIG::Rsvd3
UINT32 Rsvd3
Reserved.
Definition: PchPcieRpConfig.h:175
PCH_PCIE_ROOT_PORT_CONFIG::MvcEnabled
UINT8 MvcEnabled
The Multiple VC (MVC) supports hardware to avoid HoQ block for latency sensitive TC.
Definition: PchPcieRpConfig.h:216
PCH_PCIE_CLOCK_USAGE
PCH_PCIE_CLOCK_USAGE
Definition: PchPcieRpConfig.h:116
PCH_PCIE_RP_PREMEM_CONFIG
The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers ...
Definition: PchPcieRpConfig.h:263
PCIE_COMMON_CONFIG
PCIe Common Config.
Definition: PcieConfig.h:302
PcieConfig.h
PCIe Config Block.
PCH_PCIE_RP_PREMEM_CONFIG::RpEnabledMask
UINT32 RpEnabledMask
Root Port enabling mask.
Definition: PchPcieRpConfig.h:270
PCIE_RP_DXE_CONFIG::PcieDeviceOverrideTablePtr
PCIE_DEVICE_OVERRIDE * PcieDeviceOverrideTablePtr
PCIe device override table The PCIe device table is being used to override PCIe device ASPM settings.
Definition: PchPcieRpConfig.h:300
PCH_PCIE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PchPcieRpConfig.h:241
PCIE_DEVICE_OVERRIDE
PCIe device table entry entry.
Definition: PcieConfig.h:342
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PcieConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PcieRp
Classes | Enumerations
PcieConfig.h File Reference

PCIe Config Block. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | PCIE_EQ_PARAM
Represent lane specific PCIe Gen3 equalization parameters. More...
struct | PCIE_LINK_EQ_PLATFORM_SETTINGS
PCIe Link EQ Platform Settings. More...
struct | PCIE_COMMON_CONFIG
PCIe Common Config. More...
struct | PCIE_DEVICE_OVERRIDE
PCIe device table entry entry. More...

Enumerations

enum | PCIE_FORM_FACTOR
Specifies the form factor that the slot implements. More...
enum | PCIE_LINK_EQ_METHOD
enum | PCIE_LINK_EQ_MODE

Detailed Description

PCIe Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PcieConfig.h.

Enumeration Type Documentation

◆ PCIE_FORM_FACTOR

enum PCIE_FORM_FACTOR

Specifies the form factor that the slot implements.

For custom form factors that do not require any special handling please set PcieFormFactorOther.

Definition at line 102 of file PcieConfig.h.

◆ PCIE_LINK_EQ_METHOD

enum PCIE_LINK_EQ_METHOD
Enumerator
PcieLinkHardwareEq | Hardware is responsible for performing coefficient/preset search.
PcieLinkFixedEq | No coefficient/preset search is performed. Fixed values are used.

Definition at line 113 of file PcieConfig.h.

◆ PCIE_LINK_EQ_MODE

enum PCIE_LINK_EQ_MODE
Enumerator
PcieLinkEqPresetMode | Use presets during PCIe link equalization.
PcieLinkEqCoefficientMode | Use coefficients during PCIe link equalization.

Definition at line 118 of file PcieConfig.h.

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PcieConfig.h
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1 /** @file
2 PCIe Config Block
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCIE_CONFIG_H_
36 #define _PCIE_CONFIG_H_
37
38 #define PCIE_LINK_EQ_COEFFICIENTS_MAX 10
39 #define PCIE_LINK_EQ_PRESETS_MAX 11
40
41 #pragma pack (push,1)
42
43 enum PCIE_COMPLETION_TIMEOUT {
44 PcieCompletionTO_Default,
45 PcieCompletionTO_50_100us,
46 PcieCompletionTO_1_10ms,
47 PcieCompletionTO_16_55ms,
48 PcieCompletionTO_65_210ms,
49 PcieCompletionTO_260_900ms,
50 PcieCompletionTO_1_3P5s,
51 PcieCompletionTO_4_13s,
52 PcieCompletionTO_17_64s,
53 PcieCompletionTO_Disabled
54 };
55
56 typedef enum {
57 PcieAuto,
58 PcieGen1,
59 PcieGen2,
60 PcieGen3,
61 PcieGen4,
62 PcieGen5
63 } PCIE_SPEED;
64
65 typedef enum {
66 PcieDisabled,
67 PcieL1SUB_1,
68 PcieL1SUB_1_2
69 }L1_SUBSTATES;
70
71 /**
72 Represent lane specific PCIe Gen3 equalization parameters.
73 **/
74 typedef struct {
75 UINT8 Cm; ///< Coefficient C-1
76 UINT8 Cp; ///< Coefficient C+1
77 UINT8 Rsvd0[2]; ///< Reserved bytes
78 } PCIE_EQ_PARAM;
79
80 typedef struct {
81 UINT16 LtrMaxSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Snoop Latency.
82 UINT16 LtrMaxNoSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Non-Snoop Latency.
83 UINT8 SnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Mode.
84 UINT8 SnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Multiplier.
85 UINT16 SnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Value.
86 UINT8 NonSnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
87 UINT8 NonSnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
88 UINT16 NonSnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Value.
89 UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
90 UINT8 ForceLtrOverride;
91 UINT8 LtrOverrideSpecComplaint;
92 UINT8 RsvdByte1;
93 } PCIE_LTR_CONFIG;
94
95
96 /**
97 Specifies the form factor that the slot
98 implements. For custom form factors that
99 do not require any special handling please
100 set PcieFormFactorOther.
101 **/
102 typedef enum {
103 PcieFormFactorOther = 0,
104 PcieFormFactorCem,
105 PcieFormFactorMiniPci,
106 PcieFormFactorM2,
107 PcieFormFactorOcuLink,
108 PcieFormFactorExpressModule, // Also known as Server IO module(SIOM)
109 PcieFormFactorExpressCard,
110 PcieFormFactorU2 // Also known as SF-8639
111 } PCIE_FORM_FACTOR;
112
113 typedef enum {
114 PcieLinkHardwareEq = 0, ///< Hardware is responsible for performing coefficient/preset search.
115 PcieLinkFixedEq ///< No coefficient/preset search is performed. Fixed values are used.
116 } PCIE_LINK_EQ_METHOD;
117
118 typedef enum {
119 PcieLinkEqPresetMode = 0, ///< Use presets during PCIe link equalization
120 PcieLinkEqCoefficientMode ///< Use coefficients during PCIe link equalization
121 } PCIE_LINK_EQ_MODE;
122
123 typedef struct {
124 UINT32 PreCursor; ///< Pre-cursor coefficient
125 UINT32 PostCursor; ///< Post-cursor coefficient
126 } PCIE_LINK_EQ_COEFFICIENTS;
127
128 /**
129 PCIe Link EQ Platform Settings
130 **/
131 typedef struct {
132 UINT8 PcieLinkEqMethod; ///< Tells BIOS which link EQ method should be used for this port. Please refer to PCIE_LINK_EQ_METHOD for details of supported methods. Default: PcieLinkHardwareEq
133 UINT8 PcieLinkEqMode; ///< Tells BIOS which mode should be used for PCIe link EQ. Please refer to PCIE_LINK_EQ_MODE for details of supported modes. Default: depends on SoC
134 /**
135 Specifies if BIOS should perform local transmitter override during phase 2 of EQ process.
136 If enabled value in Ph2LocalTxOverridePreset must be valid.
137 <b>0: Disabled</b>; 1: Enabled
138 **/
139 UINT8 LocalTxOverrideEn;
140 UINT8 RemoteTransmitterOverrideEnable;
141 UINT8 DefaultPresetEnable[PCIE_LINK_EQ_PRESETS_MAX]; ///< Specifies if default settings should remain in use
142 UINT8 HapcsSearchEnable; ///< Specifies setting for Hardware Autonomous Preset/Coefficient Search mechanism
143 /**
144 Specifies the preset that should be used during local transmitter override during phase 2 of EQ process.
145 Used only if LocalTxOverrideEn is TRUE. Will be applied to all PCIe lanes of the root port.
146 Valid up to the PCIE_LINK_EQ_PRESET_MAX value. <b>Default: 0<\b>
147 **/
148 UINT32 Ph2LocalTxOverridePreset;
149 UINT32 PCETTimer; ///< PCET Timer value for single PCIe speed.
150 UINT8 RemotePresetCoeffoverride; ///< Remote Transmitter Preset Coefficient Override for single PCIe speed.
151 /**
152 PCIe Equalization Phase 3 Enable Control
153 - <b>Disabled</b> (0x0) : Disable phase 3 (Default)
154 - Enabled (0x1) : Enable phase 3
155 **/
156 UINT8 EqPh3Bypass;
157 /**
158 PCIe Equalization Phase 2-3 Enable Control
159 - <b>Disabled</b> (0x0) : Disable Phase 2 - Phase 3 (Default)
160 - Enabled (0x1) : Enable Phase 2 - Phase 3
161 **/
162 UINT8 EqPh23Bypass;
163 UINT8 TsLockTimer; ///< 8.0GT/s Training Sequence Wait Latency For Presets / Coefficients Evaluation - Gen3 TS Lock Timer
164 /**
165 PCIe Equalization Phase Enable Control
166 - <b>Disabled</b> (0x0) : Disable Phase (Default)
167 - Enabled (0x1) : Enable Phase
168 **/
169 UINT8 EqPhBypass;
170 UINT8 Rsvd[2];
171 /**
172 Tells BIOS how many presets/coefficients should be used during link EQ.
173 Entries in the Ph3CoefficientsList or Ph3PresetList(depending on chosen mode) need to be valid up to the number specified in this field.
174 **/
175 UINT8 Ph3NoOfPresetOrCoeff;
176 PCIE_LINK_EQ_COEFFICIENTS Ph3CoefficientsList[PCIE_LINK_EQ_COEFFICIENTS_MAX]; ///< List of the PCIe coefficients to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqCoefficientMode
177 UINT32 Ph3PresetList[PCIE_LINK_EQ_PRESETS_MAX]; ///< List of the PCIe preset values to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqPresetMode
178 UINT32 EndPointPresetList[PCIE_LINK_EQ_PRESETS_MAX]; ///< List of the PCIe preset values to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqPresetMode
179 UINT32 HintList[PCIE_LINK_EQ_PRESETS_MAX]; ///< List of the Hint values to be used during equalization process for preset calculation.
180 UINT32 Ph1DpTxPreset; ///< Specifies the value of the downstream port transmitter preset to be used during phase 1 of the equalization process. Will be applied to all lanes
181 UINT32 Ph1UpTxPreset; ///< Specifies the value of the upstream port transmitter preset to be used during phase 1 of the equalization process. Will be applied to all lanes
182 } PCIE_LINK_EQ_PLATFORM_SETTINGS;
183
184 //Note: This structure will be expanded to hold all common PCIe policies between SA and PCH RootPort
185 typedef struct {
186 UINT32 HotPlug : 1; ///< Indicate whether the root port is hot plug available. <b>0: Disable</b>; 1: Enable.
187 UINT32 PmSci : 1; ///< Indicate whether the root port power manager SCI is enabled. 0: Disable; <b>1: Enable</b>.
188 UINT32 TransmitterHalfSwing : 1; ///< Indicate whether the Transmitter Half Swing is enabled. <b>0: Disable</b>; 1: Enable.
189 UINT32 AcsEnabled : 1; ///< Indicate whether the ACS is enabled. 0: Disable; <b>1: Enable</b>.
190 //
191 // Error handlings
192 //
193 UINT32 AdvancedErrorReporting : 1; ///< Indicate whether the Advanced Error Reporting is enabled. <b>0: Disable</b>; 1: Enable.
194 UINT32 UnsupportedRequestReport : 1; ///< Indicate whether the Unsupported Request Report is enabled. <b>0: Disable</b>; 1: Enable.
195 UINT32 FatalErrorReport : 1; ///< Indicate whether the Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
196 UINT32 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
197 UINT32 CorrectableErrorReport : 1; ///< Indicate whether the Correctable Error Report is enabled. <b>0: Disable</b>; 1: Enable.
198 UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether the System Error on Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
199 UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether the System Error on Non Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
200 UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether the System Error on Correctable Error is enabled. <b>0: Disable</b>; 1: Enable.
201 /**
202 Max Payload Size supported, Default <b>128B</b>, see enum CPU_PCIE_MAX_PAYLOAD
203 Changes Max Payload Size Supported field in Device Capabilities of the root port.
204 **/
205 UINT32 MaxPayload : 3;
206 UINT32 DpcEnabled : 1; ///< Downstream Port Containment. 0: Disable; <b>1: Enable</b>
207 UINT32 RpDpcExtensionsEnabled : 1; ///< RP Extensions for Downstream Port Containment. 0: Disable; <b>1: Enable</b>
208 /**
209 Indicates how this root port is connected to endpoint. 0: built-in device; <b>1: slot</b>
210 Built-in is incompatible with hotplug-capable ports.
211 **/
212 UINT32 SlotImplemented : 1;
213 UINT32 PtmEnabled : 1; ///< Enables PTM capability
214 UINT32 RsvdBits0 : 13; ///< Reserved bits.
215 UINT32 SlotPowerLimitScale : 2; ///< <b>(Test)</b> Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is <b>zero</b>.
216 UINT32 SlotPowerLimitValue : 12; //< <b>(Test)</b> Specifies upper limit on power supplies by slot. Leave as 0 to set to default. Default is <b>zero</b>.
217 /**
218 Probe CLKREQ# signal before enabling CLKREQ# based power management.
219 Conforming device shall hold CLKREQ# low until CPM is enabled. This feature attempts
220 to verify CLKREQ# signal is connected by testing pad state before enabling CPM.
221 In particular this helps to avoid issues with open-ended PCIe slots.
222 This is only applicable to non hot-plug ports.
223 <b>0: Disable</b>; 1: Enable.
224 **/
225 UINT32 ClkReqDetect : 1;
226 /**
227 Set if the slot supports manually operated retention latch.
228 **/
229 UINT32 MrlSensorPresent : 1;
230 UINT32 RelaxedOrder : 1;
231 UINT32 NoSnoop : 1;
232 ///
233 /// This member describes whether Peer Memory Writes are enabled on the platform. <b>0: Disable</b>; 1: Enable.
234 ///
235 UINT32 EnablePeerMemoryWrite : 1;
236 ///
237 /// This member describes whether the PCI Express Clock Gating for each root port
238 /// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
239 ///
240 UINT32 ClockGating : 1;
241 ///
242 /// This member describes whether the PCI Express Power Gating for each root port
243 /// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
244 ///
245 UINT32 PowerGating : 1;
246 UINT32 PcieFomsCp : 3; ///< FOM Score Board Control Policy
247 UINT32 LedManagement : 1; ///< Indicate whether the VMD Led Management is enabled in root port. <b>0: Disable</b>; 1: Enable.
248 UINT32 RsvdBits1 : 7; ///< Reserved bits.
249 UINT16 PhysicalSlotNumber; ///< Indicates the slot number for the root port. Default is the value as root port index.
250 /**
251 PCIe Gen3 Equalization Phase 3 Method (see CPU_PCIE_EQ_METHOD).
252 0: DEPRECATED, hardware equalization; <b>1: hardware equalization</b>; 4: Fixed Coefficients
253 **/
254 UINT8 Gen3EqPh3Method;
255 UINT8 CompletionTimeout; ///< The completion timeout configuration of the root port (see: CPU_PCIE_COMPLETION_TIMEOUT). Default is <b>PchPcieCompletionTO_Default</b>.
256 /**
257 <b>(Test)</b>
258 Forces LTR override to be permanent
259 The default way LTR override works is:
260 rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
261 This settings allows force override of LTR mechanism. If it's enabled, then:
262 rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
263 **/
264 PCIE_LTR_CONFIG PcieRpLtrConfig; ///< <b>(Test)</b> Latency Tolerance Reporting Policies including LTR limit and Override
265 //
266 // Power Management
267 //
268 UINT8 Aspm; ///< The ASPM configuration of the root port (see: CPU_PCIE_ASPM_CONTROL). Default is <b>PchPcieAspmAutoConfig</b>.
269 UINT8 L1Substates; ///< The L1 Substates configuration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL). Default is <b>PchPcieL1SubstatesL1_1_2</b>.
270 UINT8 L1ExitLatency; ///< L1 Exit Latency
271 UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. <b>0: Disable</b>; 1: Enable.
272 UINT8 EnableCpm; ///< Enables Clock Power Management; even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism
273 UINT8 PcieSpeed; ///< Contains speed of PCIe bus (see: PCIE_SPEED)
274 /**
275 The number of milliseconds reference code will wait for link to exit Detect state for enabled ports
276 before assuming there is no device and potentially disabling the port.
277 It's assumed that the link will exit detect state before root port initialization (sufficient time
278 elapsed since PLTRST de-assertion) therefore default timeout is zero. However this might be useful
279 if device power-up seqence is controlled by BIOS or a specific device requires more time to detect.
280 In case of non-common clock enabled the default timout is 15ms.
281 <b>Default: 0</b>
282 **/
283 UINT16 DetectTimeoutMs;
284 UINT8 FormFactor; // Please check PCIE_FORM_FACTOR for supported values
285 UINT8 L1Low; ///< L1.LOW enable/disable. <b>0: Disable</b>; 1: Enable.
286 UINT8 LinkDownGpios;
287 ///
288 /// <b>0: Use project default equalization settings</b>; 1: Use equalization settings from PcieLinkEqPlatformSettings
289 ///
290 UINT8 OverrideEqualizationDefaults;
291 UINT8 PcieCfgDump;
292 UINT8 Rsvd[11];
293 PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen3LinkEqPlatformSettings; ///< Global PCIe Gen3 link EQ settings that BIOS will use during PCIe link EQ for every port.
294 PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen4LinkEqPlatformSettings; ///< Global PCIe Gen4 link EQ settings that BIOS will use during PCIe link EQ for every port.
295 PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen5LinkEqPlatformSettings; ///< Global PCIe Gen5 link EQ settings that BIOS will use during PCIe link EQ for every port.
296 } PCIE_ROOT_PORT_COMMON_CONFIG;
297
298 /**
299 PCIe Common Config
300 @note This structure will be expanded to hold all common PCIe policies between SA and PCH
301 **/
302 typedef struct {
303 /**
304 RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled.
305 A PCIE device can have higher functions only when Function0 exists. To satisfy this requirement,
306 BIOS will always enable Function0 of a device that contains more than 0 enabled root ports.
307 - <b>Enabled: One of enabled root ports get assigned to Function0.</b>
308 This offers no guarantee that any particular root port will be available at a specific DevNr:FuncNr location
309 - Disabled: Root port that corresponds to Function0 will be kept visible even though it might be not used.
310 That way rootport - to - DevNr:FuncNr assignment is constant. This option will impact ports 1, 9, 17.
311 NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage or disabled through policy
312 In other words, it only affects ports that would become hidden because they have no device connected.
313 NOTE: Disabling function swap may have adverse impact on power management. This option should ONLY
314 be used when each one of root ports 1, 9, 17:
315 - is configured as PCIe and has correctly configured ClkReq signal, or
316 - does not own any mPhy lanes (they are configured as SATA or USB)
317 **/
318 UINT32 RpFunctionSwap : 1;
319 /**
320 Compliance Test Mode shall be enabled when using Compliance Load Board.
321 <b>0: Disable</b>, 1: Enable
322 **/
323 UINT32 ComplianceTestMode : 1;
324 UINT32 SkipPresetToCoeff : 1;
325 UINT32 RsvdBits0 : 29; ///< Reserved bits
326 ///
327 /// <b>(Test)</b> This member describes whether PCIE root port Port 8xh Decode is enabled. <b>0: Disable</b>; 1: Enable.
328 ///
329 UINT8 EnablePort8xhDecode;
330 UINT8 RsvdBytes0[3];
331 } PCIE_COMMON_CONFIG;
332
333
334 /**
335 PCIe device table entry entry
336
337 The PCIe device table is being used to override PCIe device ASPM settings.
338 To take effect table consisting of such entries must be instelled as PPI
339 on gPchPcieDeviceTablePpiGuid.
340 Last entry VendorId must be 0.
341 **/
342 typedef struct {
343 UINT16 VendorId; ///< The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID
344 UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID
345 UINT8 RevId; ///< The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings
346 UINT8 BaseClassCode; ///< The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class
347 UINT8 SubClassCode; ///< The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class
348 UINT8 EndPointAspm; ///< Override device ASPM (see: PCH_PCIE_ASPM_CONTROL)
349 ///< Bit 1 must be set in OverrideConfig for this field to take effect
350 UINT16 OverrideConfig; ///< The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG).
351 /**
352 The L1Substates Capability Offset Override. (applicable if bit 2 is set in OverrideConfig)
353 This field can be zero if only the L1 Substate value is going to be override.
354 **/
355 UINT16 L1SubstatesCapOffset;
356 /**
357 L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideConfig)
358 Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s values are override.
359 Only bit [3:0] are applicable. Other bits are ignored.
360 **/
361 UINT8 L1SubstatesCapMask;
362 /**
363 L1 Substate Port Common Mode Restore Time Override. (applicable if bit 2 is set in OverrideConfig)
364 L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
365 If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
366 and only L1SubstatesCapOffset is override.
367 **/
368 UINT8 L1sCommonModeRestoreTime;
369 /**
370 L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set in OverrideConfig)
371 L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
372 If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
373 and only L1SubstatesCapOffset is override.
374 **/
375 UINT8 L1sTpowerOnScale;
376 /**
377 L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set in OverrideConfig)
378 L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
379 If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
380 and only L1SubstatesCapOffset is override.
381 **/
382 UINT8 L1sTpowerOnValue;
383
384 /**
385 SnoopLatency bit definition
386 Note: All Reserved bits must be set to 0
387
388 BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
389 When clear values in bits 9:0 will be ignored
390 BITS[14:13] - Reserved
391 BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
392 000b - 1 ns
393 001b - 32 ns
394 010b - 1024 ns
395 011b - 32,768 ns
396 100b - 1,048,576 ns
397 101b - 33,554,432 ns
398 110b - Reserved
399 111b - Reserved
400 BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with
401 the scale in bits 12:10
402
403 This field takes effect only if bit 3 is set in OverrideConfig.
404 **/
405 UINT16 SnoopLatency;
406 /**
407 NonSnoopLatency bit definition
408 Note: All Reserved bits must be set to 0
409
410 BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
411 When clear values in bits 9:0 will be ignored
412 BITS[14:13] - Reserved
413 BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
414 000b - 1 ns
415 001b - 32 ns
416 010b - 1024 ns
417 011b - 32,768 ns
418 100b - 1,048,576 ns
419 101b - 33,554,432 ns
420 110b - Reserved
421 111b - Reserved
422 BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with
423 the scale in bits 12:10
424
425 This field takes effect only if bit 3 is set in OverrideConfig.
426 **/
427 UINT16 NonSnoopLatency;
428
429 /**
430 Forces LTR override to be permanent
431 The default way LTR override works is:
432 rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
433 This settings allows force override of LTR mechanism. If it's enabled, then:
434 rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
435 **/
436 UINT8 ForceLtrOverride;
437 UINT8 Reserved[3];
438 } PCIE_DEVICE_OVERRIDE;
439
440 #pragma pack (pop)
441 #endif // _PCIE_CONFIG_H_
PCIE_DEVICE_OVERRIDE::BaseClassCode
UINT8 BaseClassCode
The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class.
Definition: PcieConfig.h:346
PCIE_LINK_EQ_MODE
PCIE_LINK_EQ_MODE
Definition: PcieConfig.h:118
PCIE_LINK_EQ_PLATFORM_SETTINGS::RemotePresetCoeffoverride
UINT8 RemotePresetCoeffoverride
Remote Transmitter Preset Coefficient Override for single PCIe speed.
Definition: PcieConfig.h:150
PcieLinkFixedEq
@ PcieLinkFixedEq
No coefficient/preset search is performed. Fixed values are used.
Definition: PcieConfig.h:115
PCIE_LINK_EQ_PLATFORM_SETTINGS::EqPh3Bypass
UINT8 EqPh3Bypass
PCIe Equalization Phase 3 Enable Control.
Definition: PcieConfig.h:156
PCIE_COMMON_CONFIG::ComplianceTestMode
UINT32 ComplianceTestMode
Compliance Test Mode shall be enabled when using Compliance Load Board.
Definition: PcieConfig.h:323
PCIE_DEVICE_OVERRIDE::SnoopLatency
UINT16 SnoopLatency
SnoopLatency bit definition Note: All Reserved bits must be set to 0.
Definition: PcieConfig.h:405
PCIE_DEVICE_OVERRIDE::DeviceId
UINT16 DeviceId
The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID.
Definition: PcieConfig.h:344
PCIE_DEVICE_OVERRIDE::L1sTpowerOnValue
UINT8 L1sTpowerOnValue
L1 Substate Port Tpower_on Value Override.
Definition: PcieConfig.h:382
PCIE_DEVICE_OVERRIDE::L1SubstatesCapOffset
UINT16 L1SubstatesCapOffset
The L1Substates Capability Offset Override.
Definition: PcieConfig.h:355
PCIE_LINK_EQ_PLATFORM_SETTINGS::PcieLinkEqMode
UINT8 PcieLinkEqMode
Tells BIOS which mode should be used for PCIe link EQ. Please refer to PCIE_LINK_EQ_MODE for details ...
Definition: PcieConfig.h:133
PCIE_DEVICE_OVERRIDE::L1SubstatesCapMask
UINT8 L1SubstatesCapMask
L1 Substate Capability Mask.
Definition: PcieConfig.h:361
PCIE_LINK_EQ_PLATFORM_SETTINGS::Ph3NoOfPresetOrCoeff
UINT8 Ph3NoOfPresetOrCoeff
Tells BIOS how many presets/coefficients should be used during link EQ.
Definition: PcieConfig.h:175
PCIE_EQ_PARAM
Represent lane specific PCIe Gen3 equalization parameters.
Definition: PcieConfig.h:74
PcieLinkEqPresetMode
@ PcieLinkEqPresetMode
Use presets during PCIe link equalization.
Definition: PcieConfig.h:119
PCIE_LINK_EQ_PLATFORM_SETTINGS::EqPh23Bypass
UINT8 EqPh23Bypass
PCIe Equalization Phase 2-3 Enable Control.
Definition: PcieConfig.h:162
PCIE_COMMON_CONFIG::RpFunctionSwap
UINT32 RpFunctionSwap
RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is ...
Definition: PcieConfig.h:318
PCIE_DEVICE_OVERRIDE::ForceLtrOverride
UINT8 ForceLtrOverride
Forces LTR override to be permanent The default way LTR override works is: rootport uses LTR override...
Definition: PcieConfig.h:436
PCIE_COMMON_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: PcieConfig.h:325
PCIE_EQ_PARAM::Cp
UINT8 Cp
Coefficient C+1.
Definition: PcieConfig.h:76
PCIE_LINK_EQ_PLATFORM_SETTINGS::PCETTimer
UINT32 PCETTimer
PCET Timer value for single PCIe speed.
Definition: PcieConfig.h:149
PCIE_DEVICE_OVERRIDE::SubClassCode
UINT8 SubClassCode
The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class.
Definition: PcieConfig.h:347
PCIE_LINK_EQ_PLATFORM_SETTINGS::Ph2LocalTxOverridePreset
UINT32 Ph2LocalTxOverridePreset
Specifies the preset that should be used during local transmitter override during phase 2 of EQ proce...
Definition: PcieConfig.h:148
PCIE_LINK_EQ_PLATFORM_SETTINGS::PcieLinkEqMethod
UINT8 PcieLinkEqMethod
Tells BIOS which link EQ method should be used for this port. Please refer to PCIE_LINK_EQ_METHOD for...
Definition: PcieConfig.h:132
PCIE_DEVICE_OVERRIDE::OverrideConfig
UINT16 OverrideConfig
The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG).
Definition: PcieConfig.h:350
PcieLinkHardwareEq
@ PcieLinkHardwareEq
Hardware is responsible for performing coefficient/preset search.
Definition: PcieConfig.h:114
PcieLinkEqCoefficientMode
@ PcieLinkEqCoefficientMode
Use coefficients during PCIe link equalization.
Definition: PcieConfig.h:120
PCIE_LINK_EQ_PLATFORM_SETTINGS::Ph1DpTxPreset
UINT32 Ph1DpTxPreset
Specifies the value of the downstream port transmitter preset to be used during phase 1 of the equali...
Definition: PcieConfig.h:180
PCIE_DEVICE_OVERRIDE::RevId
UINT8 RevId
The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings.
Definition: PcieConfig.h:345
PCIE_DEVICE_OVERRIDE::VendorId
UINT16 VendorId
The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID.
Definition: PcieConfig.h:343
PCIE_LINK_EQ_PLATFORM_SETTINGS::HapcsSearchEnable
UINT8 HapcsSearchEnable
Specifies setting for Hardware Autonomous Preset/Coefficient Search mechanism.
Definition: PcieConfig.h:142
PCIE_DEVICE_OVERRIDE::NonSnoopLatency
UINT16 NonSnoopLatency
NonSnoopLatency bit definition Note: All Reserved bits must be set to 0.
Definition: PcieConfig.h:427
PCIE_LINK_EQ_PLATFORM_SETTINGS::Ph1UpTxPreset
UINT32 Ph1UpTxPreset
Specifies the value of the upstream port transmitter preset to be used during phase 1 of the equaliza...
Definition: PcieConfig.h:181
PCIE_LINK_EQ_PLATFORM_SETTINGS::TsLockTimer
UINT8 TsLockTimer
8.0GT/s Training Sequence Wait Latency For Presets / Coefficients Evaluation - Gen3 TS Lock Timer
Definition: PcieConfig.h:163
PCIE_COMMON_CONFIG
PCIe Common Config.
Definition: PcieConfig.h:302
PCIE_LINK_EQ_METHOD
PCIE_LINK_EQ_METHOD
Definition: PcieConfig.h:113
PCIE_DEVICE_OVERRIDE::L1sTpowerOnScale
UINT8 L1sTpowerOnScale
L1 Substate Port Tpower_on Scale Override.
Definition: PcieConfig.h:375
PCIE_LINK_EQ_PLATFORM_SETTINGS
PCIe Link EQ Platform Settings.
Definition: PcieConfig.h:131
PCIE_LINK_EQ_PLATFORM_SETTINGS::EqPhBypass
UINT8 EqPhBypass
PCIe Equalization Phase Enable Control.
Definition: PcieConfig.h:169
PCIE_LINK_EQ_PLATFORM_SETTINGS::LocalTxOverrideEn
UINT8 LocalTxOverrideEn
Specifies if BIOS should perform local transmitter override during phase 2 of EQ process.
Definition: PcieConfig.h:139
PCIE_DEVICE_OVERRIDE::L1sCommonModeRestoreTime
UINT8 L1sCommonModeRestoreTime
L1 Substate Port Common Mode Restore Time Override.
Definition: PcieConfig.h:368
PCIE_COMMON_CONFIG::EnablePort8xhDecode
UINT8 EnablePort8xhDecode
(Test) This member describes whether PCIE root port Port 8xh Decode is enabled.
Definition: PcieConfig.h:329
PCIE_DEVICE_OVERRIDE
PCIe device table entry entry.
Definition: PcieConfig.h:342
PCIE_EQ_PARAM::Cm
UINT8 Cm
Coefficient C-1.
Definition: PcieConfig.h:75
PCIE_DEVICE_OVERRIDE::EndPointAspm
UINT8 EndPointAspm
Override device ASPM (see: PCH_PCIE_ASPM_CONTROL) Bit 1 must be set in OverrideConfig for this field ...
Definition: PcieConfig.h:348
PCIE_FORM_FACTOR
PCIE_FORM_FACTOR
Specifies the form factor that the slot implements.
Definition: PcieConfig.h:102
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PciePreMemConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PcieRp
Classes
PciePreMemConfig.h File Reference

PCIe Config Block PreMem. More...

Go to the source code of this file.

Classes

struct | PCIE_IMR_CONFIG
PCIe IMR Config. More...
struct | PCIE_PREMEM_CONFIG
PCIe Pre-Memory Configuration Revision 1: - Initial version. More...

Detailed Description

PCIe Config Block PreMem.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PciePreMemConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PciePreMemConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PcieRp
PciePreMemConfig.h
Go to the documentation of this file.
1 /** @file
2 PCIe Config Block PreMem
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCIE_PREMEM_CONFIG_H_
36 #define _PCIE_PREMEM_CONFIG_H_
37
38 #define PCIE_PREMEM_CONFIG_REVISION 1
39
40 extern EFI_GUID gPciePreMemConfigGuid;
41
42 typedef enum {
43 ImrRpLocationPch,
44 ImrRpLocationSa,
45 ImrRpLocationMax
46 } PCIE_IMR_ROOT_PORT_LOCATION;
47
48 #pragma pack (push,1)
49
50 /**
51 PCIe IMR Config
52 **/
53 typedef struct {
54 UINT8 ImrEnabled; ///< PCIe IMR. <b>0: Disable</b>; 1: Enable.
55 UINT8 ImrRpLocation; ///< 0: PCH_PCIe; 1: CPU_PCIe. If PCIeImrEnabled is TRUE then this will use to select the Root port location from PCH PCIe or CPU PCIe.Refer PCIE_IMR_ROOT_PORT_LOCATION above
56 UINT16 ImrSize; ///< PCIe IMR size in megabytes
57 UINT8 ImrRpSelection; ///< Index of root port that is selected for PCIe IMR (0 based)
58 UINT8 Rsvd0[3];
59 } PCIE_IMR_CONFIG;
60
61 /**
62 PCIe Pre-Memory Configuration
63 <b>Revision 1</b>: - Initial version.
64 **/
65 typedef struct {
66 CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
67 PCIE_IMR_CONFIG PcieImr; ///< IMR Configuration
68 } PCIE_PREMEM_CONFIG;
69
70 #pragma pack (pop)
71 #endif // _PCIE_PREMEM_CONFIG_H_
PCIE_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0 - 27 Config Block Header.
Definition: PciePreMemConfig.h:66
PCIE_IMR_CONFIG::ImrRpLocation
UINT8 ImrRpLocation
0: PCH_PCIe; 1: CPU_PCIe. If PCIeImrEnabled is TRUE then this will use to select the Root port locati...
Definition: PciePreMemConfig.h:55
PCIE_IMR_CONFIG
PCIe IMR Config.
Definition: PciePreMemConfig.h:53
PCIE_PREMEM_CONFIG
PCIe Pre-Memory Configuration Revision 1: - Initial version.
Definition: PciePreMemConfig.h:65
PCIE_IMR_CONFIG::ImrSize
UINT16 ImrSize
PCIe IMR size in megabytes.
Definition: PciePreMemConfig.h:56
PCIE_PREMEM_CONFIG::PcieImr
PCIE_IMR_CONFIG PcieImr
IMR Configuration.
Definition: PciePreMemConfig.h:67
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCIE_IMR_CONFIG::ImrRpSelection
UINT8 ImrRpSelection
Index of root port that is selected for PCIe IMR (0 based)
Definition: PciePreMemConfig.h:57
PCIE_IMR_CONFIG::ImrEnabled
UINT8 ImrEnabled
PCIe IMR. 0: Disable; 1: Enable.
Definition: PciePreMemConfig.h:54
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PeiITbtConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tbt
Macros
PeiITbtConfig.h File Reference

Header file for TBT PEI Policy. More...

#include <ConfigBlock.h>
#include <TcssInfo.h>
#include <PeiITbtGenericStructure.h>
Include dependency graph for PeiITbtConfig.h:

Go to the source code of this file.

Macros

#define PEI_ITBT_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Detailed Description

Header file for TBT PEI Policy.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiITbtConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PeiITbtConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tbt
PeiITbtConfig.h
Go to the documentation of this file.
1 /** @file
2 Header file for TBT PEI Policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _PEI_ITBT_CONFIG_H_
37 #define _PEI_ITBT_CONFIG_H_
38
39 #include <ConfigBlock.h>
40 #include <TcssInfo.h>
41 #include <PeiITbtGenericStructure.h>
42
43 //
44 // CM mode in Pre-boot - bit 2:0
45 //
46 #define USB4_CM_MODE_FW_CM 0x00
47 #define USB4_CM_MODE_SW_CM 0x01
48
49 #pragma pack(push, 1)
50 /**
51 Making any structure change after API Lock
52 will need to maintain backward compatibility, bump up
53 structure revision and update below history table\n
54 <b>Revision 1</b>: - Initial version.
55 **/
56 #define PEI_ITBT_CONFIG_REVISION 1
57
58 typedef struct _PEI_ITBT_CONFIG {
59 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
60 ITBT_GENERIC_CONFIG ITbtGenericConfig; ///< ITbt Common Configuration
61 ITBT_ROOTPORT_CONFIG ITbtRootPortConfig [MAX_ITBT_PCIE_PORT]; ///< iTbt Root Port Configuration
62 UINT16 ITbtDmaLtr [MAX_HOST_ITBT_DMA_NUMBER]; ///< iTbt Host controller DMA LTR value
63 UINT8 RsvdBytes[4]; ///< Reserved for future use
64 } PEI_ITBT_CONFIG;
65 #pragma pack(pop)
66
67 #endif
ConfigBlock.h
Header file for Config Block Lib implementation.
_ITBT_ROOTPORT_CONFIG
iTBT RootPort Data Structure
Definition: PeiITbtGenericStructure.h:44
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PeiITbtGenericStructure.h
ITBT Policy definition to be referred in both PEI and DXE phase.
_ITBT_GENERIC_CONFIG
ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and...
Definition: PeiITbtGenericStructure.h:52
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PeiITbtGenericStructure.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Typedefs
PeiITbtGenericStructure.h File Reference

ITBT Policy definition to be referred in both PEI and DXE phase. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | _ITBT_ROOTPORT_CONFIG
iTBT RootPort Data Structure More...
struct | _ITBT_GENERIC_CONFIG
ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and HOB. More...

Typedefs

typedef struct _ITBT_ROOTPORT_CONFIG | ITBT_ROOTPORT_CONFIG
iTBT RootPort Data Structure
typedef struct _ITBT_GENERIC_CONFIG | ITBT_GENERIC_CONFIG
ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and HOB.

Detailed Description

ITBT Policy definition to be referred in both PEI and DXE phase.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiITbtGenericStructure.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PeiITbtGenericStructure.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
PeiITbtGenericStructure.h
Go to the documentation of this file.
1 /** @file
2 ITBT Policy definition to be referred in both PEI and DXE phase.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _ITBT_POLICY_GENERIC_H_
37 #define _ITBT_POLICY_GENERIC_H_
38
39 #pragma pack(push, 1)
40
41 ///
42 /// iTBT RootPort Data Structure
43 ///
44 typedef struct _ITBT_ROOTPORT_CONFIG{
45 UINT8 ITbtPcieRootPortEn; ///< Disable/Enable iTBT PCIe Root Port
46 UINT8 Reserved[3]; ///< Reserved for DWORD alignment
47 } ITBT_ROOTPORT_CONFIG;
48
49 ///
50 /// ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and HOB
51 ///
52 typedef struct _ITBT_GENERIC_CONFIG{
53 /**
54 Timeout value for forcing power iTBT controller on every boot/reboot/Sx exit as a precondition for execution of following
55 mailbox communication.
56 After applying Force Power Thunderbolt BIOS shall poll for iTBT readiness for mailbox communication
57 If TBT cable is disconnected, iTBT microcontrollers are in lower power state.
58 To ensure successful mailbox execution, independently on presence of TBT cable, TBT BIOS shall bring iTBT
59 microcontrollers up by applying Force Power. iTBT microcontrollers will wake up either due to TBT cable presence or
60 Force Power event.
61 <b>(Test)</b>
62 <b> default is 500 ms </b>
63 **/
64 UINT16 ITbtForcePowerOnTimeoutInMs;
65 /**
66 Timeout value while sending connect topology mailbox command in order to bring all connected TBT devices are available
67 on PCIe before BIOS will enumerate them in BDS
68 <b>(Test)</b>
69 <b> default is 5000 ms </b>
70 **/
71 UINT16 ITbtConnectTopologyTimeoutInMs;
72 UINT8 Reserved2; ///<Reserved and previously used for iTbt Security Level
73 UINT8 ITbtPcieTunnelingForUsb4; ///< Disable/Enable PCIe tunneling for USB4. <b>default is enable</b>
74 UINT8 Usb4CmMode; ///< USB4 CM mode
75 UINT8 Reserved[1]; ///< Reserved for DWORD alignment
76 } ITBT_GENERIC_CONFIG;
77
78 #pragma pack(pop)
79
80 #endif
_ITBT_GENERIC_CONFIG::ITbtForcePowerOnTimeoutInMs
UINT16 ITbtForcePowerOnTimeoutInMs
Timeout value for forcing power iTBT controller on every boot/reboot/Sx exit as a precondition for ex...
Definition: PeiITbtGenericStructure.h:64
_ITBT_ROOTPORT_CONFIG::ITbtPcieRootPortEn
UINT8 ITbtPcieRootPortEn
Disable/Enable iTBT PCIe Root Port.
Definition: PeiITbtGenericStructure.h:45
_ITBT_GENERIC_CONFIG::Reserved2
UINT8 Reserved2
Reserved and previously used for iTbt Security Level.
Definition: PeiITbtGenericStructure.h:72
_ITBT_ROOTPORT_CONFIG::Reserved
UINT8 Reserved[3]
Reserved for DWORD alignment.
Definition: PeiITbtGenericStructure.h:46
_ITBT_ROOTPORT_CONFIG
iTBT RootPort Data Structure
Definition: PeiITbtGenericStructure.h:44
_ITBT_GENERIC_CONFIG::Usb4CmMode
UINT8 Usb4CmMode
USB4 CM mode.
Definition: PeiITbtGenericStructure.h:74
_ITBT_GENERIC_CONFIG::ITbtConnectTopologyTimeoutInMs
UINT16 ITbtConnectTopologyTimeoutInMs
Timeout value while sending connect topology mailbox command in order to bring all connected TBT devi...
Definition: PeiITbtGenericStructure.h:71
ITBT_GENERIC_CONFIG
struct _ITBT_GENERIC_CONFIG ITBT_GENERIC_CONFIG
ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and...
_ITBT_GENERIC_CONFIG::ITbtPcieTunnelingForUsb4
UINT8 ITbtPcieTunnelingForUsb4
Disable/Enable PCIe tunneling for USB4. default is enable
Definition: PeiITbtGenericStructure.h:73
_ITBT_GENERIC_CONFIG
ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and...
Definition: PeiITbtGenericStructure.h:52
ITBT_ROOTPORT_CONFIG
struct _ITBT_ROOTPORT_CONFIG ITBT_ROOTPORT_CONFIG
iTBT RootPort Data Structure
_ITBT_GENERIC_CONFIG::Reserved
UINT8 Reserved[1]
Reserved for DWORD alignment.
Definition: PeiITbtGenericStructure.h:75
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PeiPreMemSiDefaultPolicy.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Classes | Typedefs
PeiPreMemSiDefaultPolicy.h File Reference

This file defines the function to initialize default silicon policy PPI. More...

Go to the source code of this file.

Classes

struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI
This PPI provides function to install default silicon policy. More...

Typedefs

typedef EFI_STATUS(* PEI_PREMEM_POLICY_INIT) (VOID)
Initialize and install default silicon policy PPI.

Detailed Description

This file defines the function to initialize default silicon policy PPI.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiPreMemSiDefaultPolicy.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PeiPreMemSiDefaultPolicy.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
PeiPreMemSiDefaultPolicy.h
Go to the documentation of this file.
1 /** @file
2 This file defines the function to initialize default silicon policy PPI.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
36 #define _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
37
38 //
39 // Forward declaration for the PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI.
40 //
41 typedef struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI;
42
43 /**
44 Initialize and install default silicon policy PPI
45 **/
46 typedef
47 EFI_STATUS
48 (EFIAPI *PEI_PREMEM_POLICY_INIT) (
49 VOID
50 );
51
52 ///
53 /// This PPI provides function to install default silicon policy
54 ///
55 struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI {
56 PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit; ///< PeiPreMemPolicyInit()
57 };
58
59 extern EFI_GUID gSiPreMemDefaultPolicyInitPpiGuid;
60
61 #endif // _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
_PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI
This PPI provides function to install default silicon policy.
Definition: PeiPreMemSiDefaultPolicy.h:55
VOID
#define VOID
Undeclared type.
Definition: Base.h:269
EFI_STATUS
RETURN_STATUS EFI_STATUS
Function return status for EFI API.
Definition: UefiBaseType.h:29
_PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI::PeiPreMemPolicyInit
PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit
PeiPreMemPolicyInit()
Definition: PeiPreMemSiDefaultPolicy.h:56
PEI_PREMEM_POLICY_INIT
EFI_STATUS(* PEI_PREMEM_POLICY_INIT)(VOID)
Initialize and install default silicon policy PPI.
Definition: PeiPreMemSiDefaultPolicy.h:48
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PeiSiDefaultPolicy.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Classes | Typedefs
PeiSiDefaultPolicy.h File Reference

This file defines the function to initialize default silicon policy PPI. More...

Go to the source code of this file.

Classes

struct _PEI_SI_DEFAULT_POLICY_INIT_PPI
This PPI provides function to install default silicon policy. More...

Typedefs

typedef EFI_STATUS(* PEI_POLICY_INIT) (VOID)
Initialize and install default silicon policy PPI.

Detailed Description

This file defines the function to initialize default silicon policy PPI.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiSiDefaultPolicy.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PeiSiDefaultPolicy.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
PeiSiDefaultPolicy.h
Go to the documentation of this file.
1 /** @file
2 This file defines the function to initialize default silicon policy PPI.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
36 #define _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
37
38 //
39 // Forward declaration for the PEI_SI_DEFAULT_POLICY_INIT_PPI.
40 //
41 typedef struct _PEI_SI_DEFAULT_POLICY_INIT_PPI PEI_SI_DEFAULT_POLICY_INIT_PPI;
42
43 /**
44 Initialize and install default silicon policy PPI
45 **/
46 typedef
47 EFI_STATUS
48 (EFIAPI *PEI_POLICY_INIT) (
49 VOID
50 );
51
52 ///
53 /// This PPI provides function to install default silicon policy
54 ///
55 struct _PEI_SI_DEFAULT_POLICY_INIT_PPI {
56 PEI_POLICY_INIT PeiPolicyInit; ///< PeiPolicyInit()
57 };
58
59 extern EFI_GUID gSiDefaultPolicyInitPpiGuid;
60
61 #endif // _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
VOID
#define VOID
Undeclared type.
Definition: Base.h:269
_PEI_SI_DEFAULT_POLICY_INIT_PPI
This PPI provides function to install default silicon policy.
Definition: PeiSiDefaultPolicy.h:55
_PEI_SI_DEFAULT_POLICY_INIT_PPI::PeiPolicyInit
PEI_POLICY_INIT PeiPolicyInit
PeiPolicyInit()
Definition: PeiSiDefaultPolicy.h:56
EFI_STATUS
RETURN_STATUS EFI_STATUS
Function return status for EFI API.
Definition: UefiBaseType.h:29
PEI_POLICY_INIT
EFI_STATUS(* PEI_POLICY_INIT)(VOID)
Initialize and install default silicon policy PPI.
Definition: PeiSiDefaultPolicy.h:48
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PiHob.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Edk2
  • MdePkg
  • Include
  • Pi
Classes | Macros | Typedefs
PiHob.h File Reference

HOB related definitions in PI. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | EFI_HOB_GENERIC_HEADER
Describes the format and size of the data inside the HOB. More...
struct | EFI_HOB_HANDOFF_INFO_TABLE
Contains general state information used by the HOB producer phase. More...
struct | EFI_HOB_MEMORY_ALLOCATION_HEADER
EFI_HOB_MEMORY_ALLOCATION_HEADER describes the various attributes of the logical memory allocation. More...
struct | EFI_HOB_MEMORY_ALLOCATION
Describes all memory ranges used during the HOB producer phase that exist outside the HOB list. More...
struct | EFI_HOB_MEMORY_ALLOCATION_STACK
Describes the memory stack that is produced by the HOB producer phase and upon which all post-memory-installed executable content in the HOB producer phase is executing. More...
struct | EFI_HOB_MEMORY_ALLOCATION_BSP_STORE
Defines the location of the boot-strap processor (BSP) BSPStore ("Backing Store Pointer Store"). More...
struct | EFI_HOB_MEMORY_ALLOCATION_MODULE
Defines the location and entry point of the HOB consumer phase. More...
struct | EFI_HOB_RESOURCE_DESCRIPTOR
Describes the resource properties of all fixed, nonrelocatable resource ranges found on the processor host bus during the HOB producer phase. More...
struct | EFI_HOB_GUID_TYPE
Allows writers of executable content in the HOB producer phase to maintain and manage HOBs with specific GUID. More...
struct | EFI_HOB_FIRMWARE_VOLUME
Details the location of firmware volumes that contain firmware files. More...
struct | EFI_HOB_FIRMWARE_VOLUME2
Details the location of a firmware volume that was extracted from a file within another firmware volume. More...
struct | EFI_HOB_FIRMWARE_VOLUME3
Details the location of a firmware volume that was extracted from a file within another firmware volume. More...
struct | EFI_HOB_CPU
Describes processor information, such as address space and I/O space capabilities. More...
struct | EFI_HOB_MEMORY_POOL
Describes pool memory allocations. More...
struct | EFI_HOB_UEFI_CAPSULE
Each UEFI capsule HOB details the location of a UEFI capsule. More...
union | EFI_PEI_HOB_POINTERS
Union of all the possible HOB Types. More...

Macros

#define EFI_HOB_HANDOFF_TABLE_VERSION 0x0009
Value of version in EFI_HOB_HANDOFF_INFO_TABLE.

Typedefs

typedef UINT32 | EFI_RESOURCE_TYPE
The resource type.
typedef UINT32 | EFI_RESOURCE_ATTRIBUTE_TYPE
A type of recount attribute type.

Detailed Description

HOB related definitions in PI.

Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Revision Reference:
PI Version 1.6

Definition in file PiHob.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PiHob.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Edk2
  • MdePkg
  • Include
  • Pi
PiHob.h
Go to the documentation of this file.
1 /** @file
2 HOB related definitions in PI.
3
4 Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
6
7 @par Revision Reference:
8 PI Version 1.6
9
10 **/
11
12 #ifndef __PI_HOB_H__
13 #define __PI_HOB_H__
14
15 //
16 // HobType of EFI_HOB_GENERIC_HEADER.
17 //
18 #define EFI_HOB_TYPE_HANDOFF 0x0001
19 #define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
20 #define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
21 #define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
22 #define EFI_HOB_TYPE_FV 0x0005
23 #define EFI_HOB_TYPE_CPU 0x0006
24 #define EFI_HOB_TYPE_MEMORY_POOL 0x0007
25 #define EFI_HOB_TYPE_FV2 0x0009
26 #define EFI_HOB_TYPE_LOAD_PEIM_UNUSED 0x000A
27 #define EFI_HOB_TYPE_UEFI_CAPSULE 0x000B
28 #define EFI_HOB_TYPE_FV3 0x000C
29 #define EFI_HOB_TYPE_UNUSED 0xFFFE
30 #define EFI_HOB_TYPE_END_OF_HOB_LIST 0xFFFF
31
32 ///
33 /// Describes the format and size of the data inside the HOB.
34 /// All HOBs must contain this generic HOB header.
35 ///
36 typedef struct {
37 ///
38 /// Identifies the HOB data structure type.
39 ///
40 UINT16 HobType;
41 ///
42 /// The length in bytes of the HOB.
43 ///
44 UINT16 HobLength;
45 ///
46 /// This field must always be set to zero.
47 ///
48 UINT32 Reserved;
49 } EFI_HOB_GENERIC_HEADER;
50
51 ///
52 /// Value of version in EFI_HOB_HANDOFF_INFO_TABLE.
53 ///
54 #define EFI_HOB_HANDOFF_TABLE_VERSION 0x0009
55
56 ///
57 /// Contains general state information used by the HOB producer phase.
58 /// This HOB must be the first one in the HOB list.
59 ///
60 typedef struct {
61 ///
62 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_HANDOFF.
63 ///
64 EFI_HOB_GENERIC_HEADER Header;
65 ///
66 /// The version number pertaining to the PHIT HOB definition.
67 /// This value is four bytes in length to provide an 8-byte aligned entry
68 /// when it is combined with the 4-byte BootMode.
69 ///
70 UINT32 Version;
71 ///
72 /// The system boot mode as determined during the HOB producer phase.
73 ///
74 EFI_BOOT_MODE BootMode;
75 ///
76 /// The highest address location of memory that is allocated for use by the HOB producer
77 /// phase. This address must be 4-KB aligned to meet page restrictions of UEFI.
78 ///
79 EFI_PHYSICAL_ADDRESS EfiMemoryTop;
80 ///
81 /// The lowest address location of memory that is allocated for use by the HOB producer phase.
82 ///
83 EFI_PHYSICAL_ADDRESS EfiMemoryBottom;
84 ///
85 /// The highest address location of free memory that is currently available
86 /// for use by the HOB producer phase.
87 ///
88 EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop;
89 ///
90 /// The lowest address location of free memory that is available for use by the HOB producer phase.
91 ///
92 EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom;
93 ///
94 /// The end of the HOB list.
95 ///
96 EFI_PHYSICAL_ADDRESS EfiEndOfHobList;
97 } EFI_HOB_HANDOFF_INFO_TABLE;
98
99 ///
100 /// EFI_HOB_MEMORY_ALLOCATION_HEADER describes the
101 /// various attributes of the logical memory allocation. The type field will be used for
102 /// subsequent inclusion in the UEFI memory map.
103 ///
104 typedef struct {
105 ///
106 /// A GUID that defines the memory allocation region's type and purpose, as well as
107 /// other fields within the memory allocation HOB. This GUID is used to define the
108 /// additional data within the HOB that may be present for the memory allocation HOB.
109 /// Type EFI_GUID is defined in InstallProtocolInterface() in the UEFI 2.0
110 /// specification.
111 ///
112 EFI_GUID Name;
113
114 ///
115 /// The base address of memory allocated by this HOB. Type
116 /// EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in the UEFI 2.0
117 /// specification.
118 ///
119 EFI_PHYSICAL_ADDRESS MemoryBaseAddress;
120
121 ///
122 /// The length in bytes of memory allocated by this HOB.
123 ///
124 UINT64 MemoryLength;
125
126 ///
127 /// Defines the type of memory allocated by this HOB. The memory type definition
128 /// follows the EFI_MEMORY_TYPE definition. Type EFI_MEMORY_TYPE is defined
129 /// in AllocatePages() in the UEFI 2.0 specification.
130 ///
131 EFI_MEMORY_TYPE MemoryType;
132
133 ///
134 /// Padding for Itanium processor family
135 ///
136 UINT8 Reserved[4];
137 } EFI_HOB_MEMORY_ALLOCATION_HEADER;
138
139 ///
140 /// Describes all memory ranges used during the HOB producer
141 /// phase that exist outside the HOB list. This HOB type
142 /// describes how memory is used, not the physical attributes of memory.
143 ///
144 typedef struct {
145 ///
146 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.
147 ///
148 EFI_HOB_GENERIC_HEADER Header;
149 ///
150 /// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the
151 /// various attributes of the logical memory allocation.
152 ///
153 EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;
154 //
155 // Additional data pertaining to the "Name" Guid memory
156 // may go here.
157 //
158 } EFI_HOB_MEMORY_ALLOCATION;
159
160 ///
161 /// Describes the memory stack that is produced by the HOB producer
162 /// phase and upon which all post-memory-installed executable
163 /// content in the HOB producer phase is executing.
164 ///
165 typedef struct {
166 ///
167 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.
168 ///
169 EFI_HOB_GENERIC_HEADER Header;
170 ///
171 /// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the
172 /// various attributes of the logical memory allocation.
173 ///
174 EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;
175 } EFI_HOB_MEMORY_ALLOCATION_STACK;
176
177 ///
178 /// Defines the location of the boot-strap
179 /// processor (BSP) BSPStore ("Backing Store Pointer Store").
180 /// This HOB is valid for the Itanium processor family only
181 /// register overflow store.
182 ///
183 typedef struct {
184 ///
185 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.
186 ///
187 EFI_HOB_GENERIC_HEADER Header;
188 ///
189 /// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the
190 /// various attributes of the logical memory allocation.
191 ///
192 EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;
193 } EFI_HOB_MEMORY_ALLOCATION_BSP_STORE;
194
195 ///
196 /// Defines the location and entry point of the HOB consumer phase.
197 ///
198 typedef struct {
199 ///
200 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.
201 ///
202 EFI_HOB_GENERIC_HEADER Header;
203 ///
204 /// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the
205 /// various attributes of the logical memory allocation.
206 ///
207 EFI_HOB_MEMORY_ALLOCATION_HEADER MemoryAllocationHeader;
208 ///
209 /// The GUID specifying the values of the firmware file system name
210 /// that contains the HOB consumer phase component.
211 ///
212 EFI_GUID ModuleName;
213 ///
214 /// The address of the memory-mapped firmware volume
215 /// that contains the HOB consumer phase firmware file.
216 ///
217 EFI_PHYSICAL_ADDRESS EntryPoint;
218 } EFI_HOB_MEMORY_ALLOCATION_MODULE;
219
220 ///
221 /// The resource type.
222 ///
223 typedef UINT32 EFI_RESOURCE_TYPE;
224
225 //
226 // Value of ResourceType in EFI_HOB_RESOURCE_DESCRIPTOR.
227 //
228 #define EFI_RESOURCE_SYSTEM_MEMORY 0x00000000
229 #define EFI_RESOURCE_MEMORY_MAPPED_IO 0x00000001
230 #define EFI_RESOURCE_IO 0x00000002
231 #define EFI_RESOURCE_FIRMWARE_DEVICE 0x00000003
232 #define EFI_RESOURCE_MEMORY_MAPPED_IO_PORT 0x00000004
233 #define EFI_RESOURCE_MEMORY_RESERVED 0x00000005
234 #define EFI_RESOURCE_IO_RESERVED 0x00000006
235 //
236 // BZ3937_EFI_RESOURCE_MEMORY_UNACCEPTED is defined for unaccepted memory.
237 // But this defitinion has not been officially in the PI spec. Base
238 // on the code-first we define BZ3937_EFI_RESOURCE_MEMORY_UNACCEPTED at
239 // MdeModulePkg/Include/Pi/PrePiHob.h and update EFI_RESOURCE_MAX_MEMORY_TYPE
240 // to 8. After BZ3937_EFI_RESOURCE_MEMORY_UNACCEPTED is officially published
241 // in PI spec, we will re-visit here.
242 //
243 // #define BZ3937_EFI_RESOURCE_MEMORY_UNACCEPTED 0x00000007
244 #define EFI_RESOURCE_MAX_MEMORY_TYPE 0x00000008
245
246 ///
247 /// A type of recount attribute type.
248 ///
249 typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE;
250
251 //
252 // These types can be ORed together as needed.
253 //
254 // The following attributes are used to describe settings
255 //
256 #define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001
257 #define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002
258 #define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004
259 #define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED 0x00000080
260 //
261 // This is typically used as memory cacheability attribute today.
262 // NOTE: Since PI spec 1.4, please use EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTED
263 // as Physical write protected attribute, and EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED
264 // means Memory cacheability attribute: The memory supports being programmed with
265 // a writeprotected cacheable attribute.
266 //
267 #define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED 0x00000100
268 #define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED 0x00000200
269 #define EFI_RESOURCE_ATTRIBUTE_PERSISTENT 0x00800000
270 //
271 // The rest of the attributes are used to describe capabilities
272 //
273 #define EFI_RESOURCE_ATTRIBUTE_SINGLE_BIT_ECC 0x00000008
274 #define EFI_RESOURCE_ATTRIBUTE_MULTIPLE_BIT_ECC 0x00000010
275 #define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_1 0x00000020
276 #define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_2 0x00000040
277 #define EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE 0x00000400
278 #define EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE 0x00000800
279 #define EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE 0x00001000
280 #define EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE 0x00002000
281 #define EFI_RESOURCE_ATTRIBUTE_16_BIT_IO 0x00004000
282 #define EFI_RESOURCE_ATTRIBUTE_32_BIT_IO 0x00008000
283 #define EFI_RESOURCE_ATTRIBUTE_64_BIT_IO 0x00010000
284 #define EFI_RESOURCE_ATTRIBUTE_UNCACHED_EXPORTED 0x00020000
285 #define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTABLE 0x00100000
286 //
287 // This is typically used as memory cacheability attribute today.
288 // NOTE: Since PI spec 1.4, please use EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTABLE
289 // as Memory capability attribute: The memory supports being protected from processor
290 // writes, and EFI_RESOURCE_ATTRIBUTE_WRITE_PROTEC TABLE means Memory cacheability attribute:
291 // The memory supports being programmed with a writeprotected cacheable attribute.
292 //
293 #define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTABLE 0x00200000
294 #define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTABLE 0x00400000
295 #define EFI_RESOURCE_ATTRIBUTE_PERSISTABLE 0x01000000
296
297 #define EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTED 0x00040000
298 #define EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTABLE 0x00080000
299
300 //
301 // Physical memory relative reliability attribute. This
302 // memory provides higher reliability relative to other
303 // memory in the system. If all memory has the same
304 // reliability, then this bit is not used.
305 //
306 #define EFI_RESOURCE_ATTRIBUTE_MORE_RELIABLE 0x02000000
307
308 ///
309 /// Describes the resource properties of all fixed,
310 /// nonrelocatable resource ranges found on the processor
311 /// host bus during the HOB producer phase.
312 ///
313 typedef struct {
314 ///
315 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_RESOURCE_DESCRIPTOR.
316 ///
317 EFI_HOB_GENERIC_HEADER Header;
318 ///
319 /// A GUID representing the owner of the resource. This GUID is used by HOB
320 /// consumer phase components to correlate device ownership of a resource.
321 ///
322 EFI_GUID Owner;
323 ///
324 /// The resource type enumeration as defined by EFI_RESOURCE_TYPE.
325 ///
326 EFI_RESOURCE_TYPE ResourceType;
327 ///
328 /// Resource attributes as defined by EFI_RESOURCE_ATTRIBUTE_TYPE.
329 ///
330 EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
331 ///
332 /// The physical start address of the resource region.
333 ///
334 EFI_PHYSICAL_ADDRESS PhysicalStart;
335 ///
336 /// The number of bytes of the resource region.
337 ///
338 UINT64 ResourceLength;
339 } EFI_HOB_RESOURCE_DESCRIPTOR;
340
341 ///
342 /// Allows writers of executable content in the HOB producer phase to
343 /// maintain and manage HOBs with specific GUID.
344 ///
345 typedef struct {
346 ///
347 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_GUID_EXTENSION.
348 ///
349 EFI_HOB_GENERIC_HEADER Header;
350 ///
351 /// A GUID that defines the contents of this HOB.
352 ///
353 EFI_GUID Name;
354 //
355 // Guid specific data goes here
356 //
357 } EFI_HOB_GUID_TYPE;
358
359 ///
360 /// Details the location of firmware volumes that contain firmware files.
361 ///
362 typedef struct {
363 ///
364 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_FV.
365 ///
366 EFI_HOB_GENERIC_HEADER Header;
367 ///
368 /// The physical memory-mapped base address of the firmware volume.
369 ///
370 EFI_PHYSICAL_ADDRESS BaseAddress;
371 ///
372 /// The length in bytes of the firmware volume.
373 ///
374 UINT64 Length;
375 } EFI_HOB_FIRMWARE_VOLUME;
376
377 ///
378 /// Details the location of a firmware volume that was extracted
379 /// from a file within another firmware volume.
380 ///
381 typedef struct {
382 ///
383 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_FV2.
384 ///
385 EFI_HOB_GENERIC_HEADER Header;
386 ///
387 /// The physical memory-mapped base address of the firmware volume.
388 ///
389 EFI_PHYSICAL_ADDRESS BaseAddress;
390 ///
391 /// The length in bytes of the firmware volume.
392 ///
393 UINT64 Length;
394 ///
395 /// The name of the firmware volume.
396 ///
397 EFI_GUID FvName;
398 ///
399 /// The name of the firmware file that contained this firmware volume.
400 ///
401 EFI_GUID FileName;
402 } EFI_HOB_FIRMWARE_VOLUME2;
403
404 ///
405 /// Details the location of a firmware volume that was extracted
406 /// from a file within another firmware volume.
407 ///
408 typedef struct {
409 ///
410 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_FV3.
411 ///
412 EFI_HOB_GENERIC_HEADER Header;
413 ///
414 /// The physical memory-mapped base address of the firmware volume.
415 ///
416 EFI_PHYSICAL_ADDRESS BaseAddress;
417 ///
418 /// The length in bytes of the firmware volume.
419 ///
420 UINT64 Length;
421 ///
422 /// The authentication status.
423 ///
424 UINT32 AuthenticationStatus;
425 ///
426 /// TRUE if the FV was extracted as a file within another firmware volume.
427 /// FALSE otherwise.
428 ///
429 BOOLEAN ExtractedFv;
430 ///
431 /// The name of the firmware volume.
432 /// Valid only if IsExtractedFv is TRUE.
433 ///
434 EFI_GUID FvName;
435 ///
436 /// The name of the firmware file that contained this firmware volume.
437 /// Valid only if IsExtractedFv is TRUE.
438 ///
439 EFI_GUID FileName;
440 } EFI_HOB_FIRMWARE_VOLUME3;
441
442 ///
443 /// Describes processor information, such as address space and I/O space capabilities.
444 ///
445 typedef struct {
446 ///
447 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_CPU.
448 ///
449 EFI_HOB_GENERIC_HEADER Header;
450 ///
451 /// Identifies the maximum physical memory addressability of the processor.
452 ///
453 UINT8 SizeOfMemorySpace;
454 ///
455 /// Identifies the maximum physical I/O addressability of the processor.
456 ///
457 UINT8 SizeOfIoSpace;
458 ///
459 /// This field will always be set to zero.
460 ///
461 UINT8 Reserved[6];
462 } EFI_HOB_CPU;
463
464 ///
465 /// Describes pool memory allocations.
466 ///
467 typedef struct {
468 ///
469 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_POOL.
470 ///
471 EFI_HOB_GENERIC_HEADER Header;
472 } EFI_HOB_MEMORY_POOL;
473
474 ///
475 /// Each UEFI capsule HOB details the location of a UEFI capsule. It includes a base address and length
476 /// which is based upon memory blocks with a EFI_CAPSULE_HEADER and the associated
477 /// CapsuleImageSize-based payloads. These HOB's shall be created by the PEI PI firmware
478 /// sometime after the UEFI UpdateCapsule service invocation with the
479 /// CAPSULE_FLAGS_POPULATE_SYSTEM_TABLE flag set in the EFI_CAPSULE_HEADER.
480 ///
481 typedef struct {
482 ///
483 /// The HOB generic header where Header.HobType = EFI_HOB_TYPE_UEFI_CAPSULE.
484 ///
485 EFI_HOB_GENERIC_HEADER Header;
486
487 ///
488 /// The physical memory-mapped base address of an UEFI capsule. This value is set to
489 /// point to the base of the contiguous memory of the UEFI capsule.
490 /// The length of the contiguous memory in bytes.
491 ///
492 EFI_PHYSICAL_ADDRESS BaseAddress;
493 UINT64 Length;
494 } EFI_HOB_UEFI_CAPSULE;
495
496 ///
497 /// Union of all the possible HOB Types.
498 ///
499 typedef union {
500 EFI_HOB_GENERIC_HEADER *Header;
501 EFI_HOB_HANDOFF_INFO_TABLE *HandoffInformationTable;
502 EFI_HOB_MEMORY_ALLOCATION *MemoryAllocation;
503 EFI_HOB_MEMORY_ALLOCATION_BSP_STORE *MemoryAllocationBspStore;
504 EFI_HOB_MEMORY_ALLOCATION_STACK *MemoryAllocationStack;
505 EFI_HOB_MEMORY_ALLOCATION_MODULE *MemoryAllocationModule;
506 EFI_HOB_RESOURCE_DESCRIPTOR *ResourceDescriptor;
507 EFI_HOB_GUID_TYPE *Guid;
508 EFI_HOB_FIRMWARE_VOLUME *FirmwareVolume;
509 EFI_HOB_FIRMWARE_VOLUME2 *FirmwareVolume2;
510 EFI_HOB_FIRMWARE_VOLUME3 *FirmwareVolume3;
511 EFI_HOB_CPU *Cpu;
512 EFI_HOB_MEMORY_POOL *Pool;
513 EFI_HOB_UEFI_CAPSULE *Capsule;
514 UINT8 *Raw;
515 } EFI_PEI_HOB_POINTERS;
516
517 #endif
EFI_HOB_MEMORY_ALLOCATION::AllocDescriptor
EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor
An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the various attributes of the logi...
Definition: PiHob.h:153
EFI_HOB_FIRMWARE_VOLUME3::ExtractedFv
BOOLEAN ExtractedFv
TRUE if the FV was extracted as a file within another firmware volume.
Definition: PiHob.h:429
EFI_HOB_MEMORY_ALLOCATION_BSP_STORE::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:187
EFI_HOB_MEMORY_ALLOCATION_BSP_STORE::AllocDescriptor
EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor
An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the various attributes of the logi...
Definition: PiHob.h:192
EFI_RESOURCE_TYPE
UINT32 EFI_RESOURCE_TYPE
The resource type.
Definition: PiHob.h:223
EFI_HOB_FIRMWARE_VOLUME3::FvName
EFI_GUID FvName
The name of the firmware volume.
Definition: PiHob.h:434
EFI_HOB_HANDOFF_INFO_TABLE::Version
UINT32 Version
The version number pertaining to the PHIT HOB definition.
Definition: PiHob.h:70
EFI_HOB_CPU::SizeOfIoSpace
UINT8 SizeOfIoSpace
Identifies the maximum physical I/O addressability of the processor.
Definition: PiHob.h:457
EFI_HOB_RESOURCE_DESCRIPTOR::ResourceType
EFI_RESOURCE_TYPE ResourceType
The resource type enumeration as defined by EFI_RESOURCE_TYPE.
Definition: PiHob.h:326
EFI_HOB_UEFI_CAPSULE::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header where Header.HobType = EFI_HOB_TYPE_UEFI_CAPSULE.
Definition: PiHob.h:485
EFI_HOB_RESOURCE_DESCRIPTOR::PhysicalStart
EFI_PHYSICAL_ADDRESS PhysicalStart
The physical start address of the resource region.
Definition: PiHob.h:334
EFI_HOB_CPU::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:449
EFI_HOB_MEMORY_ALLOCATION_MODULE
Defines the location and entry point of the HOB consumer phase.
Definition: PiHob.h:198
EFI_HOB_FIRMWARE_VOLUME2::Length
UINT64 Length
The length in bytes of the firmware volume.
Definition: PiHob.h:393
EFI_HOB_FIRMWARE_VOLUME::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:366
EFI_HOB_FIRMWARE_VOLUME3::FileName
EFI_GUID FileName
The name of the firmware file that contained this firmware volume.
Definition: PiHob.h:439
EFI_HOB_FIRMWARE_VOLUME2::FileName
EFI_GUID FileName
The name of the firmware file that contained this firmware volume.
Definition: PiHob.h:401
EFI_HOB_MEMORY_ALLOCATION_STACK
Describes the memory stack that is produced by the HOB producer phase and upon which all post-memory-...
Definition: PiHob.h:165
EFI_HOB_FIRMWARE_VOLUME3::AuthenticationStatus
UINT32 AuthenticationStatus
The authentication status.
Definition: PiHob.h:424
EFI_HOB_HANDOFF_INFO_TABLE
Contains general state information used by the HOB producer phase.
Definition: PiHob.h:60
EFI_HOB_UEFI_CAPSULE
Each UEFI capsule HOB details the location of a UEFI capsule.
Definition: PiHob.h:481
EFI_HOB_FIRMWARE_VOLUME2
Details the location of a firmware volume that was extracted from a file within another firmware volu...
Definition: PiHob.h:381
EFI_HOB_FIRMWARE_VOLUME2::FvName
EFI_GUID FvName
The name of the firmware volume.
Definition: PiHob.h:397
EFI_HOB_MEMORY_ALLOCATION_STACK::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:169
EFI_HOB_MEMORY_POOL::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:471
EFI_HOB_CPU
Describes processor information, such as address space and I/O space capabilities.
Definition: PiHob.h:445
EFI_HOB_RESOURCE_DESCRIPTOR
Describes the resource properties of all fixed, nonrelocatable resource ranges found on the processor...
Definition: PiHob.h:313
EFI_HOB_FIRMWARE_VOLUME2::BaseAddress
EFI_PHYSICAL_ADDRESS BaseAddress
The physical memory-mapped base address of the firmware volume.
Definition: PiHob.h:389
EFI_HOB_RESOURCE_DESCRIPTOR::Owner
EFI_GUID Owner
A GUID representing the owner of the resource.
Definition: PiHob.h:322
EFI_HOB_MEMORY_ALLOCATION_MODULE::EntryPoint
EFI_PHYSICAL_ADDRESS EntryPoint
The address of the memory-mapped firmware volume that contains the HOB consumer phase firmware file.
Definition: PiHob.h:217
EFI_HOB_FIRMWARE_VOLUME3::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:412
EFI_HOB_MEMORY_ALLOCATION_MODULE::ModuleName
EFI_GUID ModuleName
The GUID specifying the values of the firmware file system name that contains the HOB consumer phase ...
Definition: PiHob.h:212
EFI_HOB_RESOURCE_DESCRIPTOR::ResourceLength
UINT64 ResourceLength
The number of bytes of the resource region.
Definition: PiHob.h:338
EFI_PEI_HOB_POINTERS
Union of all the possible HOB Types.
Definition: PiHob.h:499
EFI_HOB_UEFI_CAPSULE::BaseAddress
EFI_PHYSICAL_ADDRESS BaseAddress
The physical memory-mapped base address of an UEFI capsule.
Definition: PiHob.h:492
EFI_PHYSICAL_ADDRESS
UINT64 EFI_PHYSICAL_ADDRESS
64-bit physical memory address.
Definition: UefiBaseType.h:50
EFI_HOB_FIRMWARE_VOLUME3
Details the location of a firmware volume that was extracted from a file within another firmware volu...
Definition: PiHob.h:408
EFI_HOB_MEMORY_POOL
Describes pool memory allocations.
Definition: PiHob.h:467
EFI_HOB_MEMORY_ALLOCATION_HEADER::MemoryType
EFI_MEMORY_TYPE MemoryType
Defines the type of memory allocated by this HOB.
Definition: PiHob.h:131
EFI_HOB_GENERIC_HEADER::HobType
UINT16 HobType
Identifies the HOB data structure type.
Definition: PiHob.h:40
EFI_HOB_HANDOFF_INFO_TABLE::EfiEndOfHobList
EFI_PHYSICAL_ADDRESS EfiEndOfHobList
The end of the HOB list.
Definition: PiHob.h:96
EFI_HOB_HANDOFF_INFO_TABLE::EfiMemoryBottom
EFI_PHYSICAL_ADDRESS EfiMemoryBottom
The lowest address location of memory that is allocated for use by the HOB producer phase.
Definition: PiHob.h:83
EFI_HOB_FIRMWARE_VOLUME::BaseAddress
EFI_PHYSICAL_ADDRESS BaseAddress
The physical memory-mapped base address of the firmware volume.
Definition: PiHob.h:370
EFI_HOB_FIRMWARE_VOLUME3::BaseAddress
EFI_PHYSICAL_ADDRESS BaseAddress
The physical memory-mapped base address of the firmware volume.
Definition: PiHob.h:416
EFI_HOB_CPU::SizeOfMemorySpace
UINT8 SizeOfMemorySpace
Identifies the maximum physical memory addressability of the processor.
Definition: PiHob.h:453
EFI_HOB_FIRMWARE_VOLUME::Length
UINT64 Length
The length in bytes of the firmware volume.
Definition: PiHob.h:374
EFI_HOB_GUID_TYPE
Allows writers of executable content in the HOB producer phase to maintain and manage HOBs with speci...
Definition: PiHob.h:345
EFI_HOB_MEMORY_ALLOCATION_HEADER::MemoryBaseAddress
EFI_PHYSICAL_ADDRESS MemoryBaseAddress
The base address of memory allocated by this HOB.
Definition: PiHob.h:119
EFI_HOB_FIRMWARE_VOLUME3::Length
UINT64 Length
The length in bytes of the firmware volume.
Definition: PiHob.h:420
EFI_HOB_HANDOFF_INFO_TABLE::EfiFreeMemoryTop
EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop
The highest address location of free memory that is currently available for use by the HOB producer p...
Definition: PiHob.h:88
EFI_HOB_MEMORY_ALLOCATION_MODULE::MemoryAllocationHeader
EFI_HOB_MEMORY_ALLOCATION_HEADER MemoryAllocationHeader
An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the various attributes of the logi...
Definition: PiHob.h:207
EFI_HOB_HANDOFF_INFO_TABLE::BootMode
EFI_BOOT_MODE BootMode
The system boot mode as determined during the HOB producer phase.
Definition: PiHob.h:74
EFI_HOB_MEMORY_ALLOCATION_HEADER::MemoryLength
UINT64 MemoryLength
The length in bytes of memory allocated by this HOB.
Definition: PiHob.h:124
EFI_HOB_RESOURCE_DESCRIPTOR::ResourceAttribute
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute
Resource attributes as defined by EFI_RESOURCE_ATTRIBUTE_TYPE.
Definition: PiHob.h:330
EFI_HOB_GENERIC_HEADER
Describes the format and size of the data inside the HOB.
Definition: PiHob.h:36
EFI_HOB_FIRMWARE_VOLUME2::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:385
EFI_RESOURCE_ATTRIBUTE_TYPE
UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE
A type of recount attribute type.
Definition: PiHob.h:249
EFI_HOB_MEMORY_ALLOCATION_MODULE::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:202
EFI_HOB_GUID_TYPE::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:349
EFI_HOB_MEMORY_ALLOCATION_HEADER
EFI_HOB_MEMORY_ALLOCATION_HEADER describes the various attributes of the logical memory allocation.
Definition: PiHob.h:104
EFI_HOB_GENERIC_HEADER::HobLength
UINT16 HobLength
The length in bytes of the HOB.
Definition: PiHob.h:44
EFI_HOB_GENERIC_HEADER::Reserved
UINT32 Reserved
This field must always be set to zero.
Definition: PiHob.h:48
EFI_HOB_FIRMWARE_VOLUME
Details the location of firmware volumes that contain firmware files.
Definition: PiHob.h:362
EFI_HOB_MEMORY_ALLOCATION_BSP_STORE
Defines the location of the boot-strap processor (BSP) BSPStore ("Backing Store Pointer Store").
Definition: PiHob.h:183
EFI_HOB_MEMORY_ALLOCATION_HEADER::Name
EFI_GUID Name
A GUID that defines the memory allocation region's type and purpose, as well as other fields within t...
Definition: PiHob.h:112
EFI_HOB_HANDOFF_INFO_TABLE::EfiFreeMemoryBottom
EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom
The lowest address location of free memory that is available for use by the HOB producer phase.
Definition: PiHob.h:92
EFI_HOB_MEMORY_ALLOCATION_STACK::AllocDescriptor
EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor
An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the various attributes of the logi...
Definition: PiHob.h:174
EFI_HOB_HANDOFF_INFO_TABLE::EfiMemoryTop
EFI_PHYSICAL_ADDRESS EfiMemoryTop
The highest address location of memory that is allocated for use by the HOB producer phase.
Definition: PiHob.h:79
EFI_HOB_GUID_TYPE::Name
EFI_GUID Name
A GUID that defines the contents of this HOB.
Definition: PiHob.h:353
EFI_HOB_HANDOFF_INFO_TABLE::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:64
EFI_HOB_RESOURCE_DESCRIPTOR::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:317
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
EFI_HOB_MEMORY_ALLOCATION
Describes all memory ranges used during the HOB producer phase that exist outside the HOB list.
Definition: PiHob.h:144
EFI_HOB_MEMORY_ALLOCATION::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:148
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PiMultiPhase.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Edk2
  • MdePkg
  • Include
  • Pi
Classes | Macros | Typedefs
PiMultiPhase.h File Reference

Include file matches things in PI for multiple module types. More...

#include <Pi/PiFirmwareVolume.h>
#include <Pi/PiFirmwareFile.h>
#include <Pi/PiBootMode.h>
#include <Pi/PiHob.h>
#include <Pi/PiDependency.h>
#include <Pi/PiStatusCode.h>
#include <Pi/PiS3BootScript.h>
Include dependency graph for PiMultiPhase.h:

Go to the source code of this file.

Classes

struct | EFI_MMRAM_DESCRIPTOR
Structure describing a MMRAM region and its accessibility attributes. More...
struct | _EFI_MM_RESERVED_MMRAM_REGION
Structure describing a MMRAM region which cannot be used for the MMRAM heap. More...

Macros

#define | DXE_ERROR(StatusCode) (MAX_BIT | (MAX_BIT >> 2) | StatusCode)
Produces an error code in the range reserved for use by the Platform Initialization Architecture Specification. More...
#define | EFI_REQUEST_UNLOAD_IMAGE DXE_ERROR (1)
If this value is returned by an EFI image, then the image should be unloaded.
#define | EFI_NOT_AVAILABLE_YET DXE_ERROR (2)
If this value is returned by an API, it means the capability is not yet installed/available/ready to use.
#define | PI_ENCODE_WARNING(a) ((MAX_BIT >> 2) | (a))
Success and warning codes reserved for use by PI. More...
#define | PI_ENCODE_ERROR(a) (MAX_BIT | (MAX_BIT >> 2) | (a))
Error codes reserved for use by PI. More...
#define | EFI_INTERRUPT_PENDING PI_ENCODE_ERROR (0)
Return status codes defined in SMM CIS.
#define | EFI_MMRAM_OPEN 0x00000001
MMRAM states and capabilities.
#define | EFI_AUTH_STATUS_PLATFORM_OVERRIDE 0x01
Bitmask of values for Authentication Status. More...

Typedefs

typedef struct _EFI_MM_RESERVED_MMRAM_REGION | EFI_MM_RESERVED_MMRAM_REGION
Structure describing a MMRAM region which cannot be used for the MMRAM heap.
typedef VOID(* | EFI_AP_PROCEDURE) (IN OUT VOID *Buffer)
The function prototype for invoking a function on an Application Processor. More...
typedef EFI_STATUS(* | EFI_AP_PROCEDURE2) (IN VOID *ProcedureArgument)
The function prototype for invoking a function on an Application Processor. More...

Detailed Description

Include file matches things in PI for multiple module types.

Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Revision Reference:
These elements are defined in UEFI Platform Initialization Specification 1.2.

Definition in file PiMultiPhase.h.

Macro Definition Documentation

◆ DXE_ERROR

#define DXE_ERROR ( StatusCode ) (MAX_BIT | (MAX_BIT >> 2) | StatusCode)

Produces an error code in the range reserved for use by the Platform Initialization Architecture Specification.

The supported 32-bit range is 0xA0000000-0xBFFFFFFF The supported 64-bit range is 0xA000000000000000-0xBFFFFFFFFFFFFFFF

Parameters
StatusCode The status code value to convert into a warning code. StatusCode must be in the range 0x00000000..0x1FFFFFFF.
Returns
The value specified by StatusCode in the PI reserved range.

Definition at line 36 of file PiMultiPhase.h.

◆ EFI_AUTH_STATUS_PLATFORM_OVERRIDE

#define EFI_AUTH_STATUS_PLATFORM_OVERRIDE 0x01

Bitmask of values for Authentication Status.

Authentication Status is returned from EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL and the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI

xx00 Image was not signed. xxx1 Platform security policy override. Assumes the same meaning as 0010 (the image was signed, the signature was tested, and the signature passed authentication test). 0010 Image was signed, the signature was tested, and the signature passed authentication test. 0110 Image was signed and the signature was not tested. 1010 Image was signed, the signature was tested, and the signature failed the authentication test.

Definition at line 84 of file PiMultiPhase.h.

◆ PI_ENCODE_ERROR

#define PI_ENCODE_ERROR ( a ) (MAX_BIT | (MAX_BIT >> 2) | (a))

Error codes reserved for use by PI.

Supported 32-bit range is 0xa0000000-0xbfffffff. Supported 64-bit range is 0xa000000000000000-0xbfffffffffffffff.

Definition at line 61 of file PiMultiPhase.h.

◆ PI_ENCODE_WARNING

#define PI_ENCODE_WARNING ( a ) ((MAX_BIT >> 2) | (a))

Success and warning codes reserved for use by PI.

Supported 32-bit range is 0x20000000-0x3fffffff. Supported 64-bit range is 0x2000000000000000-0x3fffffffffffffff.

Definition at line 54 of file PiMultiPhase.h.

Typedef Documentation

◆ EFI_AP_PROCEDURE

typedef VOID( * EFI_AP_PROCEDURE) (IN OUT VOID *Buffer)

The function prototype for invoking a function on an Application Processor.

This definition is used by the UEFI MP Serices Protocol, and the PI SMM System Table.

Parameters
[in,out] Buffer The pointer to private data buffer.

Definition at line 190 of file PiMultiPhase.h.

◆ EFI_AP_PROCEDURE2

typedef EFI_STATUS( * EFI_AP_PROCEDURE2) (IN VOID *ProcedureArgument)

The function prototype for invoking a function on an Application Processor.

This definition is used by the UEFI MM MP Serices Protocol.

Parameters
[in] ProcedureArgument The pointer to private data buffer.
Return values
EFI_SUCCESS Excutive the procedure successfully

Definition at line 206 of file PiMultiPhase.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PiMultiPhase.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Edk2
  • MdePkg
  • Include
  • Pi
PiMultiPhase.h
Go to the documentation of this file.
1 /** @file
2 Include file matches things in PI for multiple module types.
3
4 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
6
7 @par Revision Reference:
8 These elements are defined in UEFI Platform Initialization Specification 1.2.
9
10 **/
11
12 #ifndef __PI_MULTIPHASE_H__
13 #define __PI_MULTIPHASE_H__
14
15 #include <Pi/PiFirmwareVolume.h>
16 #include <Pi/PiFirmwareFile.h>
17 #include <Pi/PiBootMode.h>
18 #include <Pi/PiHob.h>
19 #include <Pi/PiDependency.h>
20 #include <Pi/PiStatusCode.h>
21 #include <Pi/PiS3BootScript.h>
22
23 /**
24 Produces an error code in the range reserved for use by the Platform Initialization
25 Architecture Specification.
26
27 The supported 32-bit range is 0xA0000000-0xBFFFFFFF
28 The supported 64-bit range is 0xA000000000000000-0xBFFFFFFFFFFFFFFF
29
30 @param StatusCode The status code value to convert into a warning code.
31 StatusCode must be in the range 0x00000000..0x1FFFFFFF.
32
33 @return The value specified by StatusCode in the PI reserved range.
34
35 **/
36 #define DXE_ERROR(StatusCode) (MAX_BIT | (MAX_BIT >> 2) | StatusCode)
37
38 ///
39 /// If this value is returned by an EFI image, then the image should be unloaded.
40 ///
41 #define EFI_REQUEST_UNLOAD_IMAGE DXE_ERROR (1)
42
43 ///
44 /// If this value is returned by an API, it means the capability is not yet
45 /// installed/available/ready to use.
46 ///
47 #define EFI_NOT_AVAILABLE_YET DXE_ERROR (2)
48
49 ///
50 /// Success and warning codes reserved for use by PI.
51 /// Supported 32-bit range is 0x20000000-0x3fffffff.
52 /// Supported 64-bit range is 0x2000000000000000-0x3fffffffffffffff.
53 ///
54 #define PI_ENCODE_WARNING(a) ((MAX_BIT >> 2) | (a))
55
56 ///
57 /// Error codes reserved for use by PI.
58 /// Supported 32-bit range is 0xa0000000-0xbfffffff.
59 /// Supported 64-bit range is 0xa000000000000000-0xbfffffffffffffff.
60 ///
61 #define PI_ENCODE_ERROR(a) (MAX_BIT | (MAX_BIT >> 2) | (a))
62
63 ///
64 /// Return status codes defined in SMM CIS.
65 ///
66 #define EFI_INTERRUPT_PENDING PI_ENCODE_ERROR (0)
67
68 #define EFI_WARN_INTERRUPT_SOURCE_PENDING PI_ENCODE_WARNING (0)
69 #define EFI_WARN_INTERRUPT_SOURCE_QUIESCED PI_ENCODE_WARNING (1)
70
71 ///
72 /// Bitmask of values for Authentication Status.
73 /// Authentication Status is returned from EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL
74 /// and the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI
75 ///
76 /// xx00 Image was not signed.
77 /// xxx1 Platform security policy override. Assumes the same meaning as 0010 (the image was signed, the
78 /// signature was tested, and the signature passed authentication test).
79 /// 0010 Image was signed, the signature was tested, and the signature passed authentication test.
80 /// 0110 Image was signed and the signature was not tested.
81 /// 1010 Image was signed, the signature was tested, and the signature failed the authentication test.
82 ///
83 ///@{
84 #define EFI_AUTH_STATUS_PLATFORM_OVERRIDE 0x01
85 #define EFI_AUTH_STATUS_IMAGE_SIGNED 0x02
86 #define EFI_AUTH_STATUS_NOT_TESTED 0x04
87 #define EFI_AUTH_STATUS_TEST_FAILED 0x08
88 #define EFI_AUTH_STATUS_ALL 0x0f
89 ///@}
90
91 ///
92 /// MMRAM states and capabilities
93 ///
94 #define EFI_MMRAM_OPEN 0x00000001
95 #define EFI_MMRAM_CLOSED 0x00000002
96 #define EFI_MMRAM_LOCKED 0x00000004
97 #define EFI_CACHEABLE 0x00000008
98 #define EFI_ALLOCATED 0x00000010
99 #define EFI_NEEDS_TESTING 0x00000020
100 #define EFI_NEEDS_ECC_INITIALIZATION 0x00000040
101
102 #define EFI_SMRAM_OPEN EFI_MMRAM_OPEN
103 #define EFI_SMRAM_CLOSED EFI_MMRAM_CLOSED
104 #define EFI_SMRAM_LOCKED EFI_MMRAM_LOCKED
105
106 ///
107 /// Structure describing a MMRAM region and its accessibility attributes.
108 ///
109 typedef struct {
110 ///
111 /// Designates the physical address of the MMRAM in memory. This view of memory is
112 /// the same as seen by I/O-based agents, for example, but it may not be the address seen
113 /// by the processors.
114 ///
115 EFI_PHYSICAL_ADDRESS PhysicalStart;
116 ///
117 /// Designates the address of the MMRAM, as seen by software executing on the
118 /// processors. This address may or may not match PhysicalStart.
119 ///
120 EFI_PHYSICAL_ADDRESS CpuStart;
121 ///
122 /// Describes the number of bytes in the MMRAM region.
123 ///
124 UINT64 PhysicalSize;
125 ///
126 /// Describes the accessibility attributes of the MMRAM. These attributes include the
127 /// hardware state (e.g., Open/Closed/Locked), capability (e.g., cacheable), logical
128 /// allocation (e.g., allocated), and pre-use initialization (e.g., needs testing/ECC
129 /// initialization).
130 ///
131 UINT64 RegionState;
132 } EFI_MMRAM_DESCRIPTOR;
133
134 typedef EFI_MMRAM_DESCRIPTOR EFI_SMRAM_DESCRIPTOR;
135
136 ///
137 /// Structure describing a MMRAM region which cannot be used for the MMRAM heap.
138 ///
139 typedef struct _EFI_MM_RESERVED_MMRAM_REGION {
140 ///
141 /// Starting address of the reserved MMRAM area, as it appears while MMRAM is open.
142 /// Ignored if MmramReservedSize is 0.
143 ///
144 EFI_PHYSICAL_ADDRESS MmramReservedStart;
145 ///
146 /// Number of bytes occupied by the reserved MMRAM area. A size of zero indicates the
147 /// last MMRAM area.
148 ///
149 UINT64 MmramReservedSize;
150 } EFI_MM_RESERVED_MMRAM_REGION;
151
152 typedef enum {
153 EFI_PCD_TYPE_8,
154 EFI_PCD_TYPE_16,
155 EFI_PCD_TYPE_32,
156 EFI_PCD_TYPE_64,
157 EFI_PCD_TYPE_BOOL,
158 EFI_PCD_TYPE_PTR
159 } EFI_PCD_TYPE;
160
161 typedef struct {
162 ///
163 /// The returned information associated with the requested TokenNumber. If
164 /// TokenNumber is 0, then PcdType is set to EFI_PCD_TYPE_8.
165 ///
166 EFI_PCD_TYPE PcdType;
167 ///
168 /// The size of the data in bytes associated with the TokenNumber specified. If
169 /// TokenNumber is 0, then PcdSize is set 0.
170 ///
171 UINTN PcdSize;
172 ///
173 /// The null-terminated ASCII string associated with a given token. If the
174 /// TokenNumber specified was 0, then this field corresponds to the null-terminated
175 /// ASCII string associated with the token's namespace Guid. If NULL, there is no
176 /// name associated with this request.
177 ///
178 CHAR8 *PcdName;
179 } EFI_PCD_INFO;
180
181 /**
182 The function prototype for invoking a function on an Application Processor.
183
184 This definition is used by the UEFI MP Serices Protocol, and the
185 PI SMM System Table.
186
187 @param[in,out] Buffer The pointer to private data buffer.
188 **/
189 typedef
190 VOID
191 (EFIAPI *EFI_AP_PROCEDURE)(
192 IN OUT VOID *Buffer
193 );
194
195 /**
196 The function prototype for invoking a function on an Application Processor.
197
198 This definition is used by the UEFI MM MP Serices Protocol.
199
200 @param[in] ProcedureArgument The pointer to private data buffer.
201
202 @retval EFI_SUCCESS Excutive the procedure successfully
203
204 **/
205 typedef
206 EFI_STATUS
207 (EFIAPI *EFI_AP_PROCEDURE2)(
208 IN VOID *ProcedureArgument
209 );
210
211 #endif
EFI_MMRAM_DESCRIPTOR::RegionState
UINT64 RegionState
Describes the accessibility attributes of the MMRAM.
Definition: PiMultiPhase.h:131
IN
#define IN
Datum is passed to the function.
Definition: Base.h:279
EFI_MMRAM_DESCRIPTOR::PhysicalSize
UINT64 PhysicalSize
Describes the number of bytes in the MMRAM region.
Definition: PiMultiPhase.h:124
_EFI_MM_RESERVED_MMRAM_REGION::MmramReservedStart
EFI_PHYSICAL_ADDRESS MmramReservedStart
Starting address of the reserved MMRAM area, as it appears while MMRAM is open.
Definition: PiMultiPhase.h:144
VOID
#define VOID
Undeclared type.
Definition: Base.h:269
EFI_AP_PROCEDURE
VOID(* EFI_AP_PROCEDURE)(IN OUT VOID *Buffer)
The function prototype for invoking a function on an Application Processor.
Definition: PiMultiPhase.h:191
EFI_MM_RESERVED_MMRAM_REGION
struct _EFI_MM_RESERVED_MMRAM_REGION EFI_MM_RESERVED_MMRAM_REGION
Structure describing a MMRAM region which cannot be used for the MMRAM heap.
EFI_MMRAM_DESCRIPTOR
Structure describing a MMRAM region and its accessibility attributes.
Definition: PiMultiPhase.h:109
EFI_MMRAM_DESCRIPTOR::PhysicalStart
EFI_PHYSICAL_ADDRESS PhysicalStart
Designates the physical address of the MMRAM in memory.
Definition: PiMultiPhase.h:115
EFI_MMRAM_DESCRIPTOR::CpuStart
EFI_PHYSICAL_ADDRESS CpuStart
Designates the address of the MMRAM, as seen by software executing on the processors.
Definition: PiMultiPhase.h:120
EFI_PHYSICAL_ADDRESS
UINT64 EFI_PHYSICAL_ADDRESS
64-bit physical memory address.
Definition: UefiBaseType.h:50
OUT
#define OUT
Datum is returned from the function.
Definition: Base.h:284
EFI_STATUS
RETURN_STATUS EFI_STATUS
Function return status for EFI API.
Definition: UefiBaseType.h:29
EFI_AP_PROCEDURE2
EFI_STATUS(* EFI_AP_PROCEDURE2)(IN VOID *ProcedureArgument)
The function prototype for invoking a function on an Application Processor.
Definition: PiMultiPhase.h:207
_EFI_MM_RESERVED_MMRAM_REGION
Structure describing a MMRAM region which cannot be used for the MMRAM heap.
Definition: PiMultiPhase.h:139
_EFI_MM_RESERVED_MMRAM_REGION::MmramReservedSize
UINT64 MmramReservedSize
Number of bytes occupied by the reserved MMRAM area.
Definition: PiMultiPhase.h:149
PiHob.h
HOB related definitions in PI.
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PmConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Pmc
Classes | Macros | Enumerations
PmConfig.h File Reference

Power Management policy. More...

#include <ConfigBlock.h>
Include dependency graph for PmConfig.h:

Go to the source code of this file.

Classes

struct | PCH_WAKE_CONFIG
This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL, LAN, PCIE wake events. More...
union | PMC_LPM_S0IX_SUB_STATE_EN
Low Power Mode Enable config. More...
union | PMC_GLOBAL_RESET_MASK
Description of Global Reset Trigger/Event Mask register. More...
struct | PCH_PM_CONFIG
The PCH_PM_CONFIG block describes expected miscellaneous power management settings. More...
struct | BCLK_CONFIG
BCLK configuration. More...

Macros

#define | PCH_PM_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.
#define | BCLK_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Enumerations

enum PCH_SLP_S4_MIN_ASSERT

Detailed Description

Power Management policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PmConfig.h.

Enumeration Type Documentation

◆ PCH_SLP_S4_MIN_ASSERT

enum PCH_SLP_S4_MIN_ASSERT
Enumerator
PchSlpS4PchTime

The time defined in PCH EDS Power Sequencing and Reset Signal Timings table.

Definition at line 94 of file PmConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PmConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Pmc
PmConfig.h
Go to the documentation of this file.
1 /** @file
2 Power Management policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PM_CONFIG_H_
36 #define _PM_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 /**
41 Making any structure change after API Lock
42 will need to maintain backward compatibility, bump up
43 structure revision and update below history table\n
44 <b>Revision 1</b>: - Initial version.
45 **/
46 #define PCH_PM_CONFIG_REVISION 1
47 extern EFI_GUID gPmConfigGuid;
48 /**
49 Making any structure change after API Lock
50 will need to maintain backward compatibility, bump up
51 structure revision and update below history table\n
52 <b>Revision 1</b>: - Initial version.
53 **/
54 #define BCLK_CONFIG_REVISION 1
55 extern EFI_GUID gBclkConfigGuid;
56
57 #pragma pack (push,1)
58
59 /**
60 This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL, LAN, PCIE wake events.
61 **/
62 typedef struct {
63 /**
64 Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register.
65 When set to 1, this bit blocks wake events from PME_B0_STS in S5, regardless of the state of PME_B0_EN.
66 When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. <b>0: Disable</b>; 1: Enable.
67 **/
68 UINT32 PmeB0S5Dis : 1;
69 UINT32 WolEnableOverride : 1; ///< Corresponds to the "WOL Enable Override" bit in the General PM Configuration B (GEN_PMCON_B) register. 0: Disable; <b>1: Enable</b>.
70 UINT32 PcieWakeFromDeepSx : 1; ///< Determine if enable PCIe to wake from deep Sx. <b>0: Disable</b>; 1: Enable.
71 UINT32 WoWlanEnable : 1; ///< Determine if WLAN wake from Sx, corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register. <b>0: Disable</b>; 1: Enable.
72 UINT32 WoWlanDeepSxEnable : 1; ///< Determine if WLAN wake from DeepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3 register. <b>0: Disable</b>; 1: Enable.
73 UINT32 LanWakeFromDeepSx : 1; ///< Determine if enable LAN to wake from deep Sx. 0: Disable; <b>1: Enable</b>.
74 UINT32 RsvdBits0 : 26;
75 } PCH_WAKE_CONFIG;
76
77 typedef enum {
78 PchDeepSxPolDisable,
79 PchDpS5BatteryEn,
80 PchDpS5AlwaysEn,
81 PchDpS4S5BatteryEn,
82 PchDpS4S5AlwaysEn,
83 PchDpS3S4S5BatteryEn,
84 PchDpS3S4S5AlwaysEn
85 } PCH_DEEP_SX_CONFIG;
86
87 typedef enum {
88 PchSlpS360us = 1,
89 PchSlpS31ms,
90 PchSlpS350ms,
91 PchSlpS32s
92 } PCH_SLP_S3_MIN_ASSERT;
93
94 typedef enum {
95 PchSlpS4PchTime, ///< The time defined in PCH EDS Power Sequencing and Reset Signal Timings table
96 PchSlpS41s,
97 PchSlpS42s,
98 PchSlpS43s,
99 PchSlpS44s
100 } PCH_SLP_S4_MIN_ASSERT;
101
102 typedef enum {
103 PchSlpSus0ms = 1,
104 PchSlpSus500ms,
105 PchSlpSus1s,
106 PchSlpSus4s,
107 } PCH_SLP_SUS_MIN_ASSERT;
108
109 typedef enum {
110 PchSlpA0ms = 1,
111 PchSlpA4s,
112 PchSlpA98ms,
113 PchSlpA2s,
114 } PCH_SLP_A_MIN_ASSERT;
115
116 typedef enum {
117 S0ixDisQNoChange,
118 S0ixDisQDciOob,
119 S0ixDisQUsb2Dbc,
120 S0ixDisQMax,
121 } S0IX_DISQ_PROBE_TYPE;
122
123 /**
124 Low Power Mode Enable config.
125 Used to configure if respective S0i2/3 sub-states are to be supported
126 by the platform. Each bit corresponds to one LPM state - LPMx->BITx.
127 Some sub-states will require external FETs controlled by EXT_PWR_GATE#/EXT_PWR_GATE2# pins
128 to gate v1p05-PHY or v1p05-IS supplies
129 **/
130 typedef union {
131 struct {
132 UINT32 S0i2p0En : 1; ///< LPM0 - S0i2.0 Enable
133 UINT32 S0i2p1En : 1; ///< LPM1 - S0i2.1 Enable
134 /**
135 LPM2 - S0i2.2 Enable.
136 Requires EXT_PWR_GATE# controlled FET to gate v1p05 PHY.
137 Refer to V1p05PhyExtFetControlEn.
138 **/
139 UINT32 S0i2p2En : 1;
140 UINT32 S0i3p0En : 1; ///< LPM3 - S0i3.0 Enable
141 UINT32 S0i3p1En : 1; ///< LPM4 - S0i3.1 Enable
142 UINT32 S0i3p2En : 1; ///< LPM5 - S0i3.2 Enable
143 /**
144 LPM5 - S0i3.3 Enable.
145 Requires EXT_PWR_GATE# controlled FET to gate v1p05 PHY.
146 Refer to V1p05PhyExtFetControlEn.
147 **/
148 UINT32 S0i3p3En : 1;
149 /**
150 LPM7 - S0i3.4 Enable.
151 Requires EXT_PWR_GATE2# controlled FET to gate v1p05-SRAM/ISCLK.
152 Refer to V1p05IsExtFetControlEn.
153 **/
154 UINT32 S0i3p4En : 1;
155 UINT32 Reserved : 24; ///< Reserved
156 } Field;
157 UINT32 Val;
158 } PMC_LPM_S0IX_SUB_STATE_EN;
159
160 /**
161 Description of Global Reset Trigger/Event Mask register
162 **/
163 typedef union {
164 struct {
165 UINT32 Reserved1 : 1;
166 UINT32 Pbo : 1;
167 UINT32 PmcUncErr : 1;
168 UINT32 PchThrm : 1;
169 UINT32 MePbo : 1;
170 UINT32 CpuThrm : 1;
171 UINT32 Megbl : 1;
172 UINT32 LtReset : 1;
173 UINT32 PmcWdt : 1;
174 UINT32 MeWdt : 1;
175 UINT32 PmcFw : 1;
176 UINT32 PchpwrFlr : 1;
177 UINT32 SyspwrFlr : 1;
178 UINT32 Reserved2 : 1;
179 UINT32 MiaUxsErr : 1;
180 UINT32 MiaUxErr : 1;
181 UINT32 CpuThrmWdt : 1;
182 UINT32 MeUncErr : 1;
183 UINT32 AdrGpio : 1;
184 UINT32 OcwdtNoicc : 1;
185 UINT32 OcwdtIcc : 1;
186 UINT32 CseHecUncErr : 1;
187 UINT32 PmcSramUncErr : 1;
188 UINT32 PmcIromParity : 1;
189 UINT32 PmcRfFusaErr : 1;
190 UINT32 Reserved3 : 4;
191 UINT32 PpbrParityErr : 1;
192 UINT32 Reserved4 : 2;
193 } Field;
194 UINT32 Value;
195 } PMC_GLOBAL_RESET_MASK;
196
197 typedef union {
198 struct {
199 UINT32 HostResetTimeout : 1;
200 UINT32 SxEntryTimeout : 1;
201 UINT32 HostRstProm : 1;
202 UINT32 HsmbMsg : 1;
203 UINT32 Pmc3Strike : 1;
204 UINT32 FwGblrstScratch5 : 1;
205 UINT32 PmcDmaTimeout : 1;
206 UINT32 EspiType7 : 1;
207 UINT32 EspiType8 : 1;
208 UINT32 FwGblRstScratch10 : 1;
209 UINT32 FwGblRstScratch11 : 1;
210 UINT32 LpmFwErr : 1;
211 UINT32 BscanMode : 1;
212 UINT32 SlpLvlRspErr : 1;
213 UINT32 FwGblrstScratch15 : 1;
214 UINT32 FwGblrstScratch16 : 1;
215 UINT32 FwGblrstScratch17 : 1;
216 UINT32 FwGblrstScratch18 : 1;
217 UINT32 FwGblrstScratch19 : 1;
218 UINT32 FwGblrstScratch20 : 1;
219 UINT32 FwGblrstScratch21 : 1;
220 UINT32 FwGblrstScratch22 : 1;
221 UINT32 FwGblrstScratch23 : 1;
222 UINT32 Rsvd : 9;
223 } Field;
224 UINT32 Value;
225 } PMC_GLOBAL_RESET_MASK1;
226
227 /**
228 The PCH_PM_CONFIG block describes expected miscellaneous power management settings.
229 The PowerResetStatusClear field would clear the Power/Reset status bits, please
230 set the bits if you want PCH Init driver to clear it, if you want to check the
231 status later then clear the bits.
232
233 <b>Revision 1</b>:
234 - Initial version.
235 <b>Revision 2</b>
236 - Added C10DynamicThresholdAdjustment
237 <b>Revision 3</b>
238 - Added PlatformAtxTelemetryUnit
239 **/
240 typedef struct {
241 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
242
243 PCH_WAKE_CONFIG WakeConfig; ///< Specify Wake Policy
244 UINT32 PchDeepSxPol : 4; ///< Deep Sx Policy. Refer to PCH_DEEP_SX_CONFIG for each value. Default is <b>PchDeepSxPolDisable</b>.
245 UINT32 PchSlpS3MinAssert : 4; ///< SLP_S3 Minimum Assertion Width Policy. Refer to PCH_SLP_S3_MIN_ASSERT for each value. Default is <b>PchSlpS350ms</b>.
246 UINT32 PchSlpS4MinAssert : 4; ///< SLP_S4 Minimum Assertion Width Policy. Refer to PCH_SLP_S4_MIN_ASSERT for each value. Default is <b>PchSlpS44s</b>.
247 UINT32 PchSlpSusMinAssert : 4; ///< SLP_SUS Minimum Assertion Width Policy. Refer to PCH_SLP_SUS_MIN_ASSERT for each value. Default is <b>PchSlpSus4s</b>.
248 UINT32 PchSlpAMinAssert : 4; ///< SLP_A Minimum Assertion Width Policy. Refer to PCH_SLP_A_MIN_ASSERT for each value. Default is <b>PchSlpA2s</b>.
249 UINT32 RsvdBits0 : 12;
250 /**
251 This member describes whether or not the LPC ClockRun feature of PCH should
252 be enabled. <b>0: Disable</b>; 1: Enable
253 **/
254 UINT32 SlpStrchSusUp : 1; ///< <b>0: Disable</b>; 1: Enable SLP_X Stretching After SUS Well Power Up
255 /**
256 Enable/Disable SLP_LAN# Low on DC Power. 0: Disable; <b>1: Enable</b>.
257 Configure On DC PHY Power Diable according to policy SlpLanLowDc.
258 When this is enabled, SLP_LAN# will be driven low when ACPRESENT is low.
259 This indicates that LAN PHY should be powered off on battery mode.
260 This will override the DC_PP_DIS setting by WolEnableOverride.
261 **/
262 UINT32 SlpLanLowDc : 1;
263 /**
264 PCH power button override period.
265 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s
266 <b>Default is 0: 4s</b>
267 **/
268 UINT32 PwrBtnOverridePeriod : 3;
269 /**
270 <b>(Test)</b>
271 Disable/Enable PCH to CPU enery report feature. <b>0: Disable</b>; 1: Enable.
272 Enery Report is must have feature. Wihtout Energy Report, the performance report
273 by workloads/benchmarks will be unrealistic because PCH's energy is not being accounted
274 in power/performance management algorithm.
275 If for some reason PCH energy report is too high, which forces CPU to try to reduce
276 its power by throttling, then it could try to disable Energy Report to do first debug.
277 This might be due to energy scaling factors are not correct or the LPM settings are not
278 kicking in.
279 **/
280 UINT32 DisableEnergyReport : 1;
281 /**
282 When set to Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
283 When set to Enable, PCH will not pull down AC_PRESENT.
284 This setting is ignored when DeepSx is not supported.
285 Default is <b>0:Disable</b>
286 **/
287 UINT32 DisableDsxAcPresentPulldown : 1;
288 /**
289 Power button native mode disable.
290 While FALSE, the PMC's power button logic will act upon the input value from the GPIO unit, as normal.
291 While TRUE, this will result in the PMC logic constantly seeing the power button as de-asserted.
292 <b>Default is FALSE.</b>
293 **/
294 UINT32 DisableNativePowerButton : 1;
295 UINT32 MeWakeSts : 1; ///< Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; <b>1: Enable</b>.
296 UINT32 WolOvrWkSts : 1; ///< Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; <b>1: Enable</b>.
297 /*
298 Set true to enable TCO timer.
299 When FALSE, it disables PCH ACPI timer, and stops TCO timer.
300 @note: This will have significant power impact when it's enabled.
301 If TCO timer is disabled, uCode ACPI timer emulation must be enabled,
302 and WDAT table must not be exposed to the OS.
303 <b>0: Disable</b>, 1: Enable
304 */
305 UINT32 EnableTcoTimer : 1;
306 /*
307 When VRAlert# feature pin is enabled and its state is '0',
308 the PMC requests throttling to a T3 Tstate to the PCH throttling unit.
309 <b>0: Disable</b>; 1: Enable.
310 */
311 UINT32 VrAlert : 1;
312 /**
313 Decide if PS_ON is to be enabled. This is available on desktop only.
314 PS_ON is a new C10 state from the CPU on desktop SKUs that enables a
315 lower power target that will be required by the California Energy
316 Commission (CEC). When FALSE, PS_ON is to be disabled.}
317 <b>0: Disable</b>; 1: Enable.
318 **/
319 UINT32 PsOnEnable : 1;
320 /**
321 Decide if CPPM Force Alignment is to be enabled. When enabled, PMC allows
322 stalling of the backbone or blocking the DMI transmit arbiter.
323 0: Disable; <b>1: Enable</b>
324 **/
325 UINT32 CppmFaEn : 1;
326 /**
327 Enable/Disable platform support for CPU_C10_GATE# pin to control gating
328 of CPU VccIO and VccSTG rails instead of SLP_S0# pin. This policy needs
329 to be set if board design includes support for CPU_C10_GATE# pin.
330 0: Disable; <b>1: Enable</b>
331 **/
332 UINT32 CpuC10GatePinEnable : 1;
333 /**
334 Control whether to enable PMC debug messages to Trace Hub.
335 When Enabled, PMC HW will send debug messages to trace hub;
336 When Disabled, PMC HW will never send debug meesages to trace hub.
337 @note: When enabled, system may not enter S0ix
338 <b>0: Disable</b>; 1: Enable.
339 **/
340 UINT32 PmcDbgMsgEn : 1;
341 /**
342 Enable/Disable ModPHY SUS Power Domain Dynamic Gating.
343 EXT_PWR_GATE# signal (if supported on platform) can be used to
344 control external FET for power gating ModPHY
345 @note: This setting is not supported and ignored on PCH-H
346 0: Disable; <b>1: Enable</b>.
347 **/
348 UINT32 ModPhySusPgEnable : 1;
349 /**
350 <b>(Test)</b>
351 This policy option enables USB2 PHY SUS Well Power Gating functionality.
352 @note: This setting is not supported and ignored on PCH-H
353 0: disable USB2 PHY SUS Well Power Gating
354 <b>1: enable USB2 PHY SUS Well Power Gating</b>
355 **/
356 UINT32 Usb2PhySusPgEnable : 1;
357 /**
358 Enable Os Idle Mode.
359 0: Disable; <b>1: Enable</b>.
360 **/
361 UINT32 OsIdleEnable : 1;
362 /**
363 Enable control using EXT_PWR_GATE# pin of external FET
364 to power gate v1p05-PHY
365 <b>0: Disable</b>; 1: Enable.
366 **/
367 UINT32 V1p05PhyExtFetControlEn : 1;
368 /**
369 Enable control using EXT_PWR_GATE2# pin of external FET
370 to power gate v1p05-IS supply
371 <b>0: Disable</b>; 1: Enable.
372 **/
373 UINT32 V1p05IsExtFetControlEn : 1;
374 /**
375 Enable/Disable the Low Power Mode Host S0ix Auto-Demotion
376 feature. This feature enables the PMC to autonomously manage
377 the deepest allowed S0ix substate to combat thrashing between
378 power management states.
379 0: Disable; <b>1: Enable</b>.
380 **/
381 UINT32 S0ixAutoDemotion : 1;
382 /**
383 Enable/Disable Latch Events C10 Exit. When this bit is set to 1,
384 SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are captured
385 on C10 exit (instead of C10 entry which is default)
386 <b>0: Disable</b>; 1: Enable.
387 **/
388 UINT32 LatchEventsC10Exit : 1;
389 /**
390 Enable/Disable PMC Watch Dog Timer. When this bit is set to 1,
391 timers are enabled that can trigger a system reset.
392 0: Disable; <b>1: Enable</b>.
393 **/
394 UINT32 PmcWdtTimerEn : 1;
395 UINT32 RsvdBits1 : 8;
396 /*
397 Power button debounce configuration
398 Debounce time can be specified in microseconds. Only certain values according
399 to below formula are supported:
400 DebounceTime = (2 ^ PADCFG_DW2.DEBOUNCE)*(glitch filter clock period).
401 RTC clock with f = 32 KHz is used for glitch filter.
402 DebounceTime = (2 ^ PADCFG_DW2.DEBOUNCE)*(31.25 us).
403 Supported DebounceTime values are following:
404 DebounceTime = 0 -> Debounce feature disabled
405 DebounceTime > 0 && < 250us -> Not supported
406 DebounceTime = 250us - 1024000us -> Supported range (DebounceTime = 250us * 2^n)
407 For values not supported by HW, they will be rounded down to closest supported one
408 <b>Default is 0</b>
409 */
410 UINT32 PowerButtonDebounce;
411 /**
412 Reset Power Cycle Duration could be customized in the unit of second. Please refer to EDS
413 for all support settings. PCH HW default is 4 seconds, and range is 1~4 seconds, where
414 <b>0 is default</b>, 1 is 1 second, 2 is 2 seconds, ... 4 is 4 seconds.
415 And make sure the setting correct, which never less than the following register.
416 - GEN_PMCON_B.SLP_S3_MIN_ASST_WDTH
417 - GEN_PMCON_B.SLP_S4_MIN_ASST_WDTH
418 - PWRM_CFG.SLP_A_MIN_ASST_WDTH
419 - PWRM_CFG.SLP_LAN_MIN_ASST_WDTH
420 **/
421 UINT8 PchPwrCycDur;
422 /**
423 Specifies the Pcie Pll Spread Spectrum Percentage
424 The value of this policy is in 1/10th percent units.
425 Valid spread range is 0-20. A value of 0xFF is reserved for AUTO.
426 A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%
427 The default is <b>0xFF: AUTO - No BIOS override</b>.
428 **/
429 UINT8 PciePllSsc;
430 /**
431 Tells BIOS to enable C10 dynamic threshold adjustment mode.
432 BIOS will only attemt to enable it on PCH SKUs which support it.
433 **/
434 UINT8 C10DynamicThresholdAdjustment;
435 UINT8 Rsvd0[1]; ///< Reserved bytes
436 /**
437 <b>(Test)</b>
438 Low Power Mode Enable/Disable config.
439 Configure if respective S0i2/3 sub-states are to be supported
440 by the platform. By default all sub-states are enabled but
441 for test purpose respective states can be disabled.
442 <b>Default is 0xFF</b>
443 **/
444 PMC_LPM_S0IX_SUB_STATE_EN LpmS0ixSubStateEnable;
445 /*
446 Set true to enable Timed GPIO 0 timer.
447 <b>0: Disable</b>, 1: Enable
448 */
449 UINT32 EnableTimedGpio0 : 1;
450 /*
451 Set true to enable Timed GPIO 1 timer.
452 <b>0: Disable</b>, 1: Enable
453 */
454 UINT32 EnableTimedGpio1 : 1;
455 /*
456 Set true to enable Demoted (Dirty) Warm reset.
457 <b>0: Disable</b>, 1: Enable
458 */
459 UINT32 DirtyWarmResetEnable : 1;
460 /*
461 Set true to enable CF9h Global Reset Lockdown.
462 <b>0: Disable</b>, 1: Enable
463 */
464 UINT32 Cf9LockdownEnable : 1;
465 UINT32 Rsvdbits2 : 28;
466
467 /**
468 Set true to enable override of Global Reset Event/Trigger masks.
469 Values from GlobalResetTriggerMask and GlobalResetEventMask will
470 be used as override value.
471 <b>0: Disable</b>, 1: Enable
472 **/
473 UINT8 GlobalResetMasksOverride;
474 UINT8 Rsvd1[3]; ///< Reserved bytes
475 /*
476 Mask for enabling Global Reset Trigger prevention
477 */
478 PMC_GLOBAL_RESET_MASK GlobalResetTriggerMask;
479 /*
480 Mask for enabling Global Reset Event prevention
481 */
482 PMC_GLOBAL_RESET_MASK GlobalResetEventMask;
483 /**
484 PMC Therm Timer Delay Register (THERM_TIMER_DELAY). Unit in us(microseconds).
485 Adding delay time between CPU thermal trip propagating through PCH and PCH generating a Global Reset
486 <b>Default is 500</b>
487 **/
488 UINT32 ThermTimerDelay : 10;
489 UINT32 PmErDebugMode : 1; ///< Energy Reporting Debug Mode
490 UINT32 PlatformAtxTelemetryUnit : 1; ///< PMC_SUS_SPARE_GCR_0 bit 0, set by BIOS to indicate the telemetry type for Desktop Psys support. Set ATX Telemetry Unit in Watts or Percentage Default value is Watts; <b>0: Watts</b>; 1: Percent
491 UINT32 Rsvdbits3 : 20;
492 } PCH_PM_CONFIG;
493
494 /**
495 BCLK configuration. Only available on projects with SOC and CPU BCLK supported.
496 **/
497 typedef struct {
498 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
499
500 /**
501 Controls enable status of SOC BCLK.
502 <b>0: HW default</b>, 1: Force enable, 2: Force disable
503 **/
504 UINT8 SocBclkPllOn;
505 /**
506 Controls enable status of CPU BCLK.
507 <b>0: HW default</b>, 1: Force enable, 2: Force disable
508 **/
509 UINT8 CpuBclkPllOn;
510 UINT8 Rsvd[2];
511 } BCLK_CONFIG;
512
513 #pragma pack (pop)
514
515 #endif // _PM_CONFIG_H_
PCH_PM_CONFIG::PchPwrCycDur
UINT8 PchPwrCycDur
Reset Power Cycle Duration could be customized in the unit of second.
Definition: PmConfig.h:421
PCH_PM_CONFIG::C10DynamicThresholdAdjustment
UINT8 C10DynamicThresholdAdjustment
Tells BIOS to enable C10 dynamic threshold adjustment mode.
Definition: PmConfig.h:434
PCH_WAKE_CONFIG::LanWakeFromDeepSx
UINT32 LanWakeFromDeepSx
Determine if enable LAN to wake from deep Sx. 0: Disable; 1: Enable.
Definition: PmConfig.h:73
ConfigBlock.h
Header file for Config Block Lib implementation.
PMC_LPM_S0IX_SUB_STATE_EN::S0i3p1En
UINT32 S0i3p1En
LPM4 - S0i3.1 Enable.
Definition: PmConfig.h:141
PCH_PM_CONFIG::PchDeepSxPol
UINT32 PchDeepSxPol
Deep Sx Policy. Refer to PCH_DEEP_SX_CONFIG for each value. Default is PchDeepSxPolDisable.
Definition: PmConfig.h:244
PCH_WAKE_CONFIG
This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL,...
Definition: PmConfig.h:62
PMC_LPM_S0IX_SUB_STATE_EN::S0i3p4En
UINT32 S0i3p4En
LPM7 - S0i3.4 Enable.
Definition: PmConfig.h:154
PCH_PM_CONFIG::PmcWdtTimerEn
UINT32 PmcWdtTimerEn
Enable/Disable PMC Watch Dog Timer.
Definition: PmConfig.h:394
PCH_WAKE_CONFIG::PcieWakeFromDeepSx
UINT32 PcieWakeFromDeepSx
Determine if enable PCIe to wake from deep Sx. 0: Disable; 1: Enable.
Definition: PmConfig.h:70
PCH_PM_CONFIG::PmErDebugMode
UINT32 PmErDebugMode
Energy Reporting Debug Mode.
Definition: PmConfig.h:489
BCLK_CONFIG::CpuBclkPllOn
UINT8 CpuBclkPllOn
Controls enable status of CPU BCLK.
Definition: PmConfig.h:509
PMC_LPM_S0IX_SUB_STATE_EN::S0i2p2En
UINT32 S0i2p2En
LPM2 - S0i2.2 Enable.
Definition: PmConfig.h:139
PCH_PM_CONFIG::OsIdleEnable
UINT32 OsIdleEnable
Enable Os Idle Mode.
Definition: PmConfig.h:361
PCH_PM_CONFIG::PsOnEnable
UINT32 PsOnEnable
Decide if PS_ON is to be enabled.
Definition: PmConfig.h:319
PCH_PM_CONFIG::PchSlpS4MinAssert
UINT32 PchSlpS4MinAssert
SLP_S4 Minimum Assertion Width Policy. Refer to PCH_SLP_S4_MIN_ASSERT for each value....
Definition: PmConfig.h:246
PCH_PM_CONFIG::S0ixAutoDemotion
UINT32 S0ixAutoDemotion
Enable/Disable the Low Power Mode Host S0ix Auto-Demotion feature.
Definition: PmConfig.h:381
PCH_PM_CONFIG::DisableNativePowerButton
UINT32 DisableNativePowerButton
Power button native mode disable.
Definition: PmConfig.h:294
PMC_LPM_S0IX_SUB_STATE_EN::S0i3p3En
UINT32 S0i3p3En
LPM5 - S0i3.3 Enable.
Definition: PmConfig.h:148
PCH_PM_CONFIG::SlpStrchSusUp
UINT32 SlpStrchSusUp
This member describes whether or not the LPC ClockRun feature of PCH should be enabled.
Definition: PmConfig.h:254
PMC_GLOBAL_RESET_MASK
Description of Global Reset Trigger/Event Mask register.
Definition: PmConfig.h:163
PCH_PM_CONFIG::LpmS0ixSubStateEnable
PMC_LPM_S0IX_SUB_STATE_EN LpmS0ixSubStateEnable
(Test) Low Power Mode Enable/Disable config.
Definition: PmConfig.h:444
PCH_PM_CONFIG::Usb2PhySusPgEnable
UINT32 Usb2PhySusPgEnable
(Test) This policy option enables USB2 PHY SUS Well Power Gating functionality.
Definition: PmConfig.h:356
PCH_PM_CONFIG::PciePllSsc
UINT8 PciePllSsc
Specifies the Pcie Pll Spread Spectrum Percentage The value of this policy is in 1/10th percent units...
Definition: PmConfig.h:429
PCH_PM_CONFIG::PchSlpS3MinAssert
UINT32 PchSlpS3MinAssert
SLP_S3 Minimum Assertion Width Policy. Refer to PCH_SLP_S3_MIN_ASSERT for each value....
Definition: PmConfig.h:245
PCH_PM_CONFIG::SlpLanLowDc
UINT32 SlpLanLowDc
Enable/Disable SLP_LAN# Low on DC Power.
Definition: PmConfig.h:262
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_PM_CONFIG::ThermTimerDelay
UINT32 ThermTimerDelay
PMC Therm Timer Delay Register (THERM_TIMER_DELAY).
Definition: PmConfig.h:488
PCH_PM_CONFIG::WakeConfig
PCH_WAKE_CONFIG WakeConfig
Specify Wake Policy.
Definition: PmConfig.h:243
PCH_PM_CONFIG::WolOvrWkSts
UINT32 WolOvrWkSts
Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable.
Definition: PmConfig.h:296
PCH_SLP_S4_MIN_ASSERT
PCH_SLP_S4_MIN_ASSERT
Definition: PmConfig.h:94
BCLK_CONFIG
BCLK configuration.
Definition: PmConfig.h:497
PCH_PM_CONFIG::MeWakeSts
UINT32 MeWakeSts
Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable.
Definition: PmConfig.h:295
PCH_PM_CONFIG::PchSlpAMinAssert
UINT32 PchSlpAMinAssert
SLP_A Minimum Assertion Width Policy. Refer to PCH_SLP_A_MIN_ASSERT for each value....
Definition: PmConfig.h:248
PCH_WAKE_CONFIG::WoWlanDeepSxEnable
UINT32 WoWlanDeepSxEnable
Determine if WLAN wake from DeepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3 register...
Definition: PmConfig.h:72
PMC_LPM_S0IX_SUB_STATE_EN::S0i2p1En
UINT32 S0i2p1En
LPM1 - S0i2.1 Enable.
Definition: PmConfig.h:133
PCH_PM_CONFIG
The PCH_PM_CONFIG block describes expected miscellaneous power management settings.
Definition: PmConfig.h:240
PCH_PM_CONFIG::DisableDsxAcPresentPulldown
UINT32 DisableDsxAcPresentPulldown
When set to Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
Definition: PmConfig.h:287
PCH_PM_CONFIG::GlobalResetMasksOverride
UINT8 GlobalResetMasksOverride
Set true to enable override of Global Reset Event/Trigger masks.
Definition: PmConfig.h:473
PMC_LPM_S0IX_SUB_STATE_EN
Low Power Mode Enable config.
Definition: PmConfig.h:130
PCH_PM_CONFIG::V1p05IsExtFetControlEn
UINT32 V1p05IsExtFetControlEn
Enable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS supply 0: Disable; 1: ...
Definition: PmConfig.h:373
PMC_LPM_S0IX_SUB_STATE_EN::Reserved
UINT32 Reserved
Reserved.
Definition: PmConfig.h:155
PCH_PM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PmConfig.h:241
PCH_PM_CONFIG::LatchEventsC10Exit
UINT32 LatchEventsC10Exit
Enable/Disable Latch Events C10 Exit.
Definition: PmConfig.h:388
PchSlpS4PchTime
@ PchSlpS4PchTime
The time defined in PCH EDS Power Sequencing and Reset Signal Timings table.
Definition: PmConfig.h:95
PCH_WAKE_CONFIG::WolEnableOverride
UINT32 WolEnableOverride
Corresponds to the "WOL Enable Override" bit in the General PM Configuration B (GEN_PMCON_B) register...
Definition: PmConfig.h:69
PCH_PM_CONFIG::ModPhySusPgEnable
UINT32 ModPhySusPgEnable
Enable/Disable ModPHY SUS Power Domain Dynamic Gating.
Definition: PmConfig.h:348
BCLK_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PmConfig.h:498
PCH_WAKE_CONFIG::WoWlanEnable
UINT32 WoWlanEnable
Determine if WLAN wake from Sx, corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register....
Definition: PmConfig.h:71
PMC_LPM_S0IX_SUB_STATE_EN::S0i2p0En
UINT32 S0i2p0En
LPM0 - S0i2.0 Enable.
Definition: PmConfig.h:132
PCH_WAKE_CONFIG::PmeB0S5Dis
UINT32 PmeB0S5Dis
Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register.
Definition: PmConfig.h:68
BCLK_CONFIG::SocBclkPllOn
UINT8 SocBclkPllOn
Controls enable status of SOC BCLK.
Definition: PmConfig.h:504
PCH_PM_CONFIG::PlatformAtxTelemetryUnit
UINT32 PlatformAtxTelemetryUnit
PMC_SUS_SPARE_GCR_0 bit 0, set by BIOS to indicate the telemetry type for Desktop Psys support....
Definition: PmConfig.h:490
PCH_PM_CONFIG::DisableEnergyReport
UINT32 DisableEnergyReport
(Test) Disable/Enable PCH to CPU enery report feature.
Definition: PmConfig.h:280
PCH_PM_CONFIG::PmcDbgMsgEn
UINT32 PmcDbgMsgEn
Control whether to enable PMC debug messages to Trace Hub.
Definition: PmConfig.h:340
PCH_PM_CONFIG::PwrBtnOverridePeriod
UINT32 PwrBtnOverridePeriod
PCH power button override period.
Definition: PmConfig.h:268
PCH_PM_CONFIG::CppmFaEn
UINT32 CppmFaEn
Decide if CPPM Force Alignment is to be enabled.
Definition: PmConfig.h:325
PMC_LPM_S0IX_SUB_STATE_EN::S0i3p2En
UINT32 S0i3p2En
LPM5 - S0i3.2 Enable.
Definition: PmConfig.h:142
PCH_PM_CONFIG::PchSlpSusMinAssert
UINT32 PchSlpSusMinAssert
SLP_SUS Minimum Assertion Width Policy. Refer to PCH_SLP_SUS_MIN_ASSERT for each value....
Definition: PmConfig.h:247
PCH_PM_CONFIG::CpuC10GatePinEnable
UINT32 CpuC10GatePinEnable
Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails...
Definition: PmConfig.h:332
PCH_PM_CONFIG::V1p05PhyExtFetControlEn
UINT32 V1p05PhyExtFetControlEn
Enable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY 0: Disable; 1: Enable.
Definition: PmConfig.h:367
PMC_LPM_S0IX_SUB_STATE_EN::S0i3p0En
UINT32 S0i3p0En
LPM3 - S0i3.0 Enable.
Definition: PmConfig.h:140
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: RstConfig.h File Reference

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RstConfig.h File Reference

Rst policy. More...

#include <PchLimits.h>
#include <ConfigBlock.h>
Include dependency graph for RstConfig.h:

Go to the source code of this file.

Classes

struct | RST_HARDWARE_REMAPPED_STORAGE_CONFIG
This structure describes the details of Intel RST for PCIe Storage remapping Note: In order to use this feature, Intel RST Driver is required. More...
struct | RST_CONFIG
Rapid Storage Technology settings. More...

Detailed Description

Rst policy.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file RstConfig.h.

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MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: RstConfig.h Source File

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RstConfig.h
Go to the documentation of this file.
1 /** @file
2 Rst policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _RST_CONFIG_H_
36 #define _RST_CONFIG_H_
37 #include <PchLimits.h>
38 #include <ConfigBlock.h>
39
40 #define RST_CONFIG_REVISION 1
41 extern EFI_GUID gRstConfigGuid;
42
43 #pragma pack (push,1)
44
45 typedef enum {
46 SataOromDelay2sec,
47 SataOromDelay4sec,
48 SataOromDelay6sec,
49 SataOromDelay8sec
50 } SATA_OROM_DELAY;
51
52 /**
53 This structure describes the details of Intel RST for PCIe Storage remapping
54 Note: In order to use this feature, Intel RST Driver is required
55 **/
56 typedef struct {
57 /**
58 This member describes whether or not the Intel RST for PCIe Storage remapping should be enabled. <b>0: Disable</b>; 1: Enable.
59 Note 1: If Sata Controller is disabled, PCIe Storage Remapping should be disabled as well
60 Note 2: If PCIe Storage remapping is enabled, the PCH integrated AHCI controllers Class Code is configured as RAID
61 **/
62 UINT32 Enable : 1;
63 /**
64 Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, <b>0 = autodetect</b>)
65 The supported ports for PCIe Storage remapping is different depend on the platform and cycle router
66 **/
67 UINT32 RstPcieStoragePort : 5;
68 /**
69 PCIe Storage Device Reset Delay in milliseconds (ms), which it guarantees such delay gap is fulfilled
70 before PCIe Storage Device configuration space is accessed after an reset caused by the link disable and enable step.
71 Default value is <b>100ms</b>.
72 **/
73 UINT32 DeviceResetDelay : 8;
74 UINT32 RsvdBits0 : 18; ///< Reserved bits
75
76 } RST_HARDWARE_REMAPPED_STORAGE_CONFIG;
77
78 /**
79 Rapid Storage Technology settings.
80
81 <b>Revision 1</b>:
82 - Initial version.
83 **/
84 typedef struct {
85 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
86
87 UINT32 Raid0 : 1; ///< 0 : Disable; <b>1 : Enable</b> RAID0
88 UINT32 Raid1 : 1; ///< 0 : Disable; <b>1 : Enable</b> RAID1
89 UINT32 Raid10 : 1; ///< 0 : Disable; <b>1 : Enable</b> RAID10
90 UINT32 Raid5 : 1; ///< 0 : Disable; <b>1 : Enable</b> RAID5
91 UINT32 Irrt : 1; ///< 0 : Disable; <b>1 : Enable</b> Intel Rapid Recovery Technology
92 UINT32 OromUiBanner : 1; ///< 0 : Disable; <b>1 : Enable</b> OROM UI and BANNER
93 UINT32 OromUiDelay : 2; ///< <b>00b : 2 secs</b>; 01b : 4 secs; 10b : 6 secs; 11 : 8 secs (see : SATA_OROM_DELAY)
94 UINT32 HddUnlock : 1; ///< 0 : Disable; <b>1 : Enable</b>. Indicates that the HDD password unlock in the OS is enabled
95 UINT32 LedLocate : 1; ///< 0 : Disable; <b>1 : Enable</b>. Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS
96 UINT32 IrrtOnly : 1; ///< 0 : Disable; <b>1 : Enable</b>. Allow only IRRT drives to span internal and external ports
97 UINT32 SmartStorage : 1; ///< 0 : Disable; <b>1 : Enable</b> RST Smart Storage caching Bit
98 UINT32 LegacyOrom : 1; ///< <b>0 : Disable</b>; 1 : Enable RST Legacy OROM
99 UINT32 OptaneMemory : 1; ///< 0: Disable; <b>1: Enable</b> RST Optane(TM) Memory
100 UINT32 CpuAttachedStorage : 1; ///< 0: Disable; <b>1: Enable</b> CPU Attached Storage
101 UINT32 RsvdBits0 : 17; ///< Reserved Bits
102 /**
103 This member describes the details of implementation of Intel RST for PCIe Storage remapping (Intel RST Driver is required)
104 Note: RST for PCIe Sorage remapping is supported only for first SATA controller if more controllers are available
105 **/
106 RST_HARDWARE_REMAPPED_STORAGE_CONFIG HardwareRemappedStorageConfig[PCH_MAX_RST_PCIE_STORAGE_CR];
107 } RST_CONFIG;
108
109 #pragma pack (pop)
110 #endif
ConfigBlock.h
Header file for Config Block Lib implementation.
RST_CONFIG::OromUiBanner
UINT32 OromUiBanner
0 : Disable; 1 : Enable OROM UI and BANNER
Definition: RstConfig.h:92
RST_CONFIG::LegacyOrom
UINT32 LegacyOrom
0 : Disable; 1 : Enable RST Legacy OROM
Definition: RstConfig.h:98
RST_CONFIG::HddUnlock
UINT32 HddUnlock
0 : Disable; 1 : Enable. Indicates that the HDD password unlock in the OS is enabled
Definition: RstConfig.h:94
RST_CONFIG::SmartStorage
UINT32 SmartStorage
0 : Disable; 1 : Enable RST Smart Storage caching Bit
Definition: RstConfig.h:97
RST_HARDWARE_REMAPPED_STORAGE_CONFIG::DeviceResetDelay
UINT32 DeviceResetDelay
PCIe Storage Device Reset Delay in milliseconds (ms), which it guarantees such delay gap is fulfilled...
Definition: RstConfig.h:73
RST_CONFIG::CpuAttachedStorage
UINT32 CpuAttachedStorage
0: Disable; 1: Enable CPU Attached Storage
Definition: RstConfig.h:100
RST_HARDWARE_REMAPPED_STORAGE_CONFIG
This structure describes the details of Intel RST for PCIe Storage remapping Note: In order to use th...
Definition: RstConfig.h:56
RST_CONFIG::Raid10
UINT32 Raid10
0 : Disable; 1 : Enable RAID10
Definition: RstConfig.h:89
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
RST_CONFIG
Rapid Storage Technology settings.
Definition: RstConfig.h:84
RST_CONFIG::Raid0
UINT32 Raid0
0 : Disable; 1 : Enable RAID0
Definition: RstConfig.h:87
RST_CONFIG::LedLocate
UINT32 LedLocate
0 : Disable; 1 : Enable. Indicates that the LED/SGPIO hardware is attached and ping to locate feature...
Definition: RstConfig.h:95
RST_HARDWARE_REMAPPED_STORAGE_CONFIG::RstPcieStoragePort
UINT32 RstPcieStoragePort
Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect) The supported po...
Definition: RstConfig.h:67
RST_CONFIG::IrrtOnly
UINT32 IrrtOnly
0 : Disable; 1 : Enable. Allow only IRRT drives to span internal and external ports
Definition: RstConfig.h:96
RST_HARDWARE_REMAPPED_STORAGE_CONFIG::Enable
UINT32 Enable
This member describes whether or not the Intel RST for PCIe Storage remapping should be enabled.
Definition: RstConfig.h:62
RST_CONFIG::OptaneMemory
UINT32 OptaneMemory
0: Disable; 1: Enable RST Optane(TM) Memory
Definition: RstConfig.h:99
RST_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved Bits.
Definition: RstConfig.h:101
RST_CONFIG::Irrt
UINT32 Irrt
0 : Disable; 1 : Enable Intel Rapid Recovery Technology
Definition: RstConfig.h:91
RST_HARDWARE_REMAPPED_STORAGE_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: RstConfig.h:74
RST_CONFIG::OromUiDelay
UINT32 OromUiDelay
00b : 2 secs; 01b : 4 secs; 10b : 6 secs; 11 : 8 secs (see : SATA_OROM_DELAY)
Definition: RstConfig.h:93
RST_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: RstConfig.h:85
RST_CONFIG::Raid1
UINT32 Raid1
0 : Disable; 1 : Enable RAID1
Definition: RstConfig.h:88
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
RST_CONFIG::Raid5
UINT32 Raid5
0 : Disable; 1 : Enable RAID5
Definition: RstConfig.h:90
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: RtcConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Rtc
Classes
RtcConfig.h File Reference

RTC policy. More...

#include <ConfigBlock.h>
Include dependency graph for RtcConfig.h:

Go to the source code of this file.

Classes

struct RTC_CONFIG
The RTC_CONFIG block describes the expected configuration of RTC configuration. More...

Detailed Description

RTC policy.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file RtcConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: RtcConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Rtc
RtcConfig.h
Go to the documentation of this file.
1 /** @file
2 RTC policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _RTC_CONFIG_H_
36 #define _RTC_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 #define RTC_CONFIG_REVISION 1
41 extern EFI_GUID gRtcConfigGuid;
42
43 #pragma pack (push,1)
44
45 /**
46 The RTC_CONFIG block describes the expected configuration of RTC configuration.
47 **/
48 typedef struct {
49 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
50 /**
51 When set, prevents RTC TS (BUC.TS) from being changed.
52 This BILD bit has different function compared to LPC/eSPI, SPI.
53 0: Disabled; <b>1: Enabled</b>
54 **/
55 UINT32 BiosInterfaceLock : 1;
56 /**
57 When set, bytes 38h-3Fh in the upper 128bytes bank of RTC RAM are locked
58 and cannot be accessed.
59 Writes will be droipped and reads will not return any guaranteed data.
60 0: Disabled; <b>1: Enabled</b>
61 **/
62 UINT32 MemoryLock : 1;
63 UINT32 RsvdBits0 : 30;
64 } RTC_CONFIG;
65
66 #pragma pack (pop)
67
68 #endif // _RTC_CONFIG_H_
ConfigBlock.h
Header file for Config Block Lib implementation.
RTC_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: RtcConfig.h:49
RTC_CONFIG
The RTC_CONFIG block describes the expected configuration of RTC configuration.
Definition: RtcConfig.h:48
RTC_CONFIG::BiosInterfaceLock
UINT32 BiosInterfaceLock
When set, prevents RTC TS (BUC.TS) from being changed.
Definition: RtcConfig.h:55
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
RTC_CONFIG::MemoryLock
UINT32 MemoryLock
When set, bytes 38h-3Fh in the upper 128bytes bank of RTC RAM are locked and cannot be accessed.
Definition: RtcConfig.h:62
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SaMiscPeiPreMemConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • ConfigBlock
Classes
SaMiscPeiPreMemConfig.h File Reference

Policy details for miscellaneous configuration in System Agent. More...

This graph shows which files directly or indirectly include this file:

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Classes

struct SA_MISC_PEI_PREMEM_CONFIG
This configuration block is to configure SA Miscellaneous variables during PEI Pre-Mem phase like programming different System Agent BARs, TsegSize, MmioSize required etc. More...

Detailed Description

Policy details for miscellaneous configuration in System Agent.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SaMiscPeiPreMemConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SaMiscPeiPreMemConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • ConfigBlock
SaMiscPeiPreMemConfig.h
Go to the documentation of this file.
1 /** @file
2 Policy details for miscellaneous configuration in System Agent
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SA_MISC_PEI_PREMEM_CONFIG_H_
36 #define _SA_MISC_PEI_PREMEM_CONFIG_H_
37
38 #pragma pack(push, 1)
39
40 #ifndef MEM_CFG_MAX_SOCKETS
41 #define MEM_CFG_MAX_SOCKETS 16
42 #endif
43
44 #define SA_MISC_PEI_PREMEM_CONFIG_REVISION 3
45
46 /**
47 This configuration block is to configure SA Miscellaneous variables during PEI Pre-Mem phase like programming
48 different System Agent BARs, TsegSize, MmioSize required etc.
49 <b>Revision 1</b>:
50 - Initial version.
51 <b>Revision 2</b>:
52 - Add CkdAddress Table.
53 <b>Revision 3</b>:
54 - Add MrcMustStaticSpdData.
55 **/
56 typedef struct {
57 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
58 /**
59 Offset 28 Memory DIMMs' SPD address for reading SPD data.
60 TGL Mapping
61 0 - Controller 0 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5
62 1 - Controller 0 Channel 0 Dimm 1 - DDR4
63 2 - Controller 0 Channel 1 Dimm 0 -------- DDR5 - LPDDR4 - LPDDR5
64 3 - Controller 0 Channel 1 Dimm 1 -------- DDR5 2DPC
65 4 - Controller 0 Channel 2 Dimm 0 --------------- LPDDR4 - LPDDR5
66 6 - Controller 0 Channel 3 Dimm 0 --------------- LPDDR4 - LPDDR5
67 8 - Controller 1 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5
68 9 - Controller 1 Channel 0 Dimm 1 - DDR4
69 10 - Controller 1 Channel 1 Dimm 0 -------- DDR5 - LPDDR4 - LPDDR5
70 11 - Controller 1 Channel 1 Dimm 1 -------- DDR5 2DPC
71 12 - Controller 1 Channel 2 Dimm 0 --------------- LPDDR4 - LPDDR5
72 14 - Controller 1 Channel 3 Dimm 0 --------------- LPDDR4 - LPDDR5
73 **/
74 UINT8 SpdAddressTable[MEM_CFG_MAX_SOCKETS];
75 VOID *S3DataPtr; ///< Offset 44 Memory data save pointer for S3 resume. The memory space should be allocated and filled with proper S3 resume data on a resume path
76 UINT32 SmbusBar; ///< Offset 48 Address of System Agent SMBUS BAR: <b>0xEFA0</b>
77 /**
78 Offset 52 Size of TSEG in bytes. (Must be power of 2)
79 <b>0x400000</b>: 4MB for Release build
80 0x1000000 : 16MB for Debug build
81 **/
82 UINT32 TsegSize;
83 UINT32 SkipExtGfxScan:1; ///< <b>(Test)</b> Offset 56:0 :1=Skip External Gfx Device Scan; <b>0=Scan for external graphics devices</b>. Set this policy to skip External Graphics card scanning if the platform uses Internal Graphics only.
84 UINT32 BdatEnable:1; ///< Offset 56:1 :This field enables the generation of the BIOS DATA ACPI Tables: <b>0=FALSE</b>, 1=TRUE.
85 UINT32 TxtImplemented:1; ///< OFfset 56:2 :This field currently is used to tell MRC if it should run after TXT initializatoin completed: <b>0=Run without waiting for TXT</b>, 1=Run after TXT initialization by callback
86 /**
87 Offset 56:3 :
88 <b>(Test)</b> Scan External Discrete Graphics Devices for Legacy Only VGA OpROMs
89
90 When enabled, if the primary graphics device is an external discrete graphics device, Si will scan the
91 graphics device for legacy only VGA OpROMs.
92
93 This is intended to ease the implementation of a BIOS feature to automatically enable CSM if the Primary Gfx device
94 only supports Legacy VBIOS (No UEFI GOP Present). Otherwise disabling CSM won't result in no video being displayed.
95 This is useful for platforms that implement PCIe slots that allow the end user to install an arbitrary Gfx device.
96
97 This setting will only take effect if SkipExtGfxScan == 0. It is ignored otherwise.
98
99 - Disabled (0x0) : Don't Scan for Legacy Only VGA OpROMs (Default)
100 - <b>Enabled</b> (0x1) : Scan External Gfx for Legacy Only VGA OpROM
101 **/
102 UINT32 ScanExtGfxForLegacyOpRom:1;
103 UINT32 RsvdBits0 :28; ///< Offset 56:4 :Reserved for future use
104 UINT8 UserBd; ///< Offset 60 <b>0=Mobile/Mobile Halo</b>, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server
105 UINT8 LockPTMregs; ///< <b>(Test)</b> Offset 61 Lock PCU Thermal Management registers: 0=FALSE, <b>1=TRUE</b>
106 UINT8 BdatTestType; ///< Offset 62 When BdatEnable is set to TRUE, this option selects the type of data which will be populated in the BIOS Data ACPI Tables: <b>0=RMT</b>, 1=RMT Per Bit, 2=Margin 2D.
107 UINT8 Rsvd4; ///< Offset 63 Reserved for config block alignment.
108 UINT32 AcpiReservedMemorySize; ///< Offset 64 The Size of a Reserved memory buffer allocated in previous boot for S3 resume used. Originally it is retrieved from AcpiVariableCompatibility variable.
109 UINT32 OpRomScanTempMmioBar; ///< <b>(Test)</b> Offset 68 Temporary address to MMIO map OpROMs during VGA scanning. Used for ScanExtGfxForLegacyOpRom feature. MUST BE 16MB ALIGNED!
110 UINT32 OpRomScanTempMmioLimit; ///< <b>(Test)</b> Offset 72 Limit address for OpROM MMIO range. Used for ScanExtGfxForLegacyOpRom feature. (OpROMScanTempMmioLimit - OpRomScanTempMmioBar) MUST BE >= 16MB!
111 UINT32 Rsvd3; ///< Offset 76 Reserved for config block alignment.
112 UINT64 AcpiReservedMemoryBase; ///< Offset 80 The Base address of a Reserved memory buffer allocated in previous boot for S3 resume used. Originally it is retrieved from AcpiVariableCompatibility variable.
113 UINT64 SystemMemoryLength; ///< Offset 88 Total system memory length from previous boot, this is required for S3 resume. Originally it is retrieved from AcpiVariableCompatibility variable.
114
115 UINT8 DisableMrcRetrainingOnRtcPowerLoss; ///< Offset 96 Enable/Disable DisableMrcRetrainingOnRtcPowerLoss.
116 UINT8 Reserved1[3]; ///< Offset 97 Reserved for config block alignment.
117
118 UINT8 OfflineCrashDumpEnable; ///< Offset 100 OfflineCrashDump feature enable. If this is enabled, memory must be reserved for BIOS execution for when an OfflineCrashDump occurs.
119 UINT8 CpuCrashDumpFlag;
120 UINT8 Rsvd2[6];
121
122 // Since the biggest element is UINT64, this structure should be aligned with 64 bits.
123 UINT8 Rsvd[4]; ///< Reserved for config block alignment.
124 UINT8 PcieResizableBarSupport;
125
126 UINT8 Rsrvd1[7];
127 /**
128 Memory DIMMs' CKD address for read/write CKD data.
129 0 - Controller 0 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5
130 1 - Controller 0 Channel 0 Dimm 1 - DDR4
131 2 - Controller 0 Channel 1 Dimm 0 -------- DDR5 - LPDDR4 - LPDDR5
132 3 - Controller 0 Channel 1 Dimm 1 -------- DDR5 2DPC
133 4 - Controller 0 Channel 2 Dimm 0 --------------- LPDDR4 - LPDDR5
134 6 - Controller 0 Channel 3 Dimm 0 --------------- LPDDR4 - LPDDR5
135 8 - Controller 1 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5
136 9 - Controller 1 Channel 0 Dimm 1 - DDR4
137 10 - Controller 1 Channel 1 Dimm 0 -------- DDR5 - LPDDR4 - LPDDR5
138 11 - Controller 1 Channel 1 Dimm 1 -------- DDR5 2DPC
139 12 - Controller 1 Channel 2 Dimm 0 --------------- LPDDR4 - LPDDR5
140 14 - Controller 1 Channel 3 Dimm 0 --------------- LPDDR4 - LPDDR5
141 **/
142 UINT8 CkdAddressTable[MEM_CFG_MAX_SOCKETS];
143
144 /**
145 * Although BIOS provides spd address, MRC need use static spd data
146 * in VPD. Each bit maps to one dimm.
147 */
148 UINT16 MrcMustStaticSpdData;
149
150 UINT8 Rsrvd2[6];
151 } SA_MISC_PEI_PREMEM_CONFIG;
152 #pragma pack(pop)
153
154 #endif // _SA_MISC_PEI_PREMEM_CONFIG_H_
SA_MISC_PEI_PREMEM_CONFIG::BdatTestType
UINT8 BdatTestType
Offset 62 When BdatEnable is set to TRUE, this option selects the type of data which will be populate...
Definition: SaMiscPeiPreMemConfig.h:106
SA_MISC_PEI_PREMEM_CONFIG::OpRomScanTempMmioLimit
UINT32 OpRomScanTempMmioLimit
(Test) Offset 72 Limit address for OpROM MMIO range. Used for ScanExtGfxForLegacyOpRom feature....
Definition: SaMiscPeiPreMemConfig.h:110
SA_MISC_PEI_PREMEM_CONFIG::UserBd
UINT8 UserBd
Offset 60 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server.
Definition: SaMiscPeiPreMemConfig.h:104
SA_MISC_PEI_PREMEM_CONFIG::DisableMrcRetrainingOnRtcPowerLoss
UINT8 DisableMrcRetrainingOnRtcPowerLoss
Offset 96 Enable/Disable DisableMrcRetrainingOnRtcPowerLoss.
Definition: SaMiscPeiPreMemConfig.h:115
SA_MISC_PEI_PREMEM_CONFIG::SystemMemoryLength
UINT64 SystemMemoryLength
Offset 88 Total system memory length from previous boot, this is required for S3 resume....
Definition: SaMiscPeiPreMemConfig.h:113
SA_MISC_PEI_PREMEM_CONFIG::MrcMustStaticSpdData
UINT16 MrcMustStaticSpdData
Although BIOS provides spd address, MRC need use static spd data in VPD.
Definition: SaMiscPeiPreMemConfig.h:148
SA_MISC_PEI_PREMEM_CONFIG::LockPTMregs
UINT8 LockPTMregs
(Test) Offset 61 Lock PCU Thermal Management registers: 0=FALSE, 1=TRUE
Definition: SaMiscPeiPreMemConfig.h:105
SA_MISC_PEI_PREMEM_CONFIG::OpRomScanTempMmioBar
UINT32 OpRomScanTempMmioBar
(Test) Offset 68 Temporary address to MMIO map OpROMs during VGA scanning. Used for ScanExtGfxForLega...
Definition: SaMiscPeiPreMemConfig.h:109
SA_MISC_PEI_PREMEM_CONFIG::SmbusBar
UINT32 SmbusBar
Offset 48 Address of System Agent SMBUS BAR: 0xEFA0
Definition: SaMiscPeiPreMemConfig.h:76
VOID
#define VOID
Undeclared type.
Definition: Base.h:269
SA_MISC_PEI_PREMEM_CONFIG::S3DataPtr
VOID * S3DataPtr
Offset 44 Memory data save pointer for S3 resume. The memory space should be allocated and filled wit...
Definition: SaMiscPeiPreMemConfig.h:75
SA_MISC_PEI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: SaMiscPeiPreMemConfig.h:57
SA_MISC_PEI_PREMEM_CONFIG::OfflineCrashDumpEnable
UINT8 OfflineCrashDumpEnable
Offset 100 OfflineCrashDump feature enable. If this is enabled, memory must be reserved for BIOS exec...
Definition: SaMiscPeiPreMemConfig.h:118
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
SA_MISC_PEI_PREMEM_CONFIG::Rsvd4
UINT8 Rsvd4
Offset 63 Reserved for config block alignment.
Definition: SaMiscPeiPreMemConfig.h:107
SA_MISC_PEI_PREMEM_CONFIG::TsegSize
UINT32 TsegSize
Offset 52 Size of TSEG in bytes.
Definition: SaMiscPeiPreMemConfig.h:82
SA_MISC_PEI_PREMEM_CONFIG::BdatEnable
UINT32 BdatEnable
Offset 56:1 :This field enables the generation of the BIOS DATA ACPI Tables: 0=FALSE,...
Definition: SaMiscPeiPreMemConfig.h:84
SA_MISC_PEI_PREMEM_CONFIG::ScanExtGfxForLegacyOpRom
UINT32 ScanExtGfxForLegacyOpRom
Offset 56:3 : (Test) Scan External Discrete Graphics Devices for Legacy Only VGA OpROMs.
Definition: SaMiscPeiPreMemConfig.h:102
SA_MISC_PEI_PREMEM_CONFIG::AcpiReservedMemorySize
UINT32 AcpiReservedMemorySize
Offset 64 The Size of a Reserved memory buffer allocated in previous boot for S3 resume used....
Definition: SaMiscPeiPreMemConfig.h:108
SA_MISC_PEI_PREMEM_CONFIG
This configuration block is to configure SA Miscellaneous variables during PEI Pre-Mem phase like pro...
Definition: SaMiscPeiPreMemConfig.h:56
SA_MISC_PEI_PREMEM_CONFIG::AcpiReservedMemoryBase
UINT64 AcpiReservedMemoryBase
Offset 80 The Base address of a Reserved memory buffer allocated in previous boot for S3 resume used....
Definition: SaMiscPeiPreMemConfig.h:112
SA_MISC_PEI_PREMEM_CONFIG::TxtImplemented
UINT32 TxtImplemented
OFfset 56:2 :This field currently is used to tell MRC if it should run after TXT initializatoin compl...
Definition: SaMiscPeiPreMemConfig.h:85
SA_MISC_PEI_PREMEM_CONFIG::RsvdBits0
UINT32 RsvdBits0
Offset 56:4 :Reserved for future use.
Definition: SaMiscPeiPreMemConfig.h:103
SA_MISC_PEI_PREMEM_CONFIG::Rsvd3
UINT32 Rsvd3
Offset 76 Reserved for config block alignment.
Definition: SaMiscPeiPreMemConfig.h:111
SA_MISC_PEI_PREMEM_CONFIG::SkipExtGfxScan
UINT32 SkipExtGfxScan
(Test) Offset 56:0 :1=Skip External Gfx Device Scan; 0=Scan for external graphics devices....
Definition: SaMiscPeiPreMemConfig.h:83
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SataConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Sata
Classes
SataConfig.h File Reference

Sata policy. More...

#include <PchLimits.h>
#include <ConfigBlock.h>
#include <Library/GpioConfig.h>
Include dependency graph for SataConfig.h:

Go to the source code of this file.

Classes

struct | PCH_SATA_PORT_CONFIG
This structure configures the features, property, and capability for each SATA port. More...
struct | SATA_THERMAL_THROTTLING
This structure lists PCH supported SATA thermal throttling register setting for customization. More...
struct | SATA_CONFIG
The SATA_CONFIG block describes the expected configuration of the SATA controllers. More...

Detailed Description

Sata policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SataConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SataConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Sata
SataConfig.h
Go to the documentation of this file.
1 /** @file
2 Sata policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SATA_CONFIG_H_
36 #define _SATA_CONFIG_H_
37
38 #include <PchLimits.h>
39 #include <ConfigBlock.h>
40 #include <Library/GpioConfig.h>
41
42 #define SATA_CONFIG_REVISION 1
43 extern EFI_GUID gSataConfigGuid;
44
45 #pragma pack (push,1)
46
47 typedef enum {
48 SataModeAhci,
49 SataModeRaid,
50 SataModeMax
51 } SATA_MODE;
52
53 typedef enum {
54 SataSpeedDefault,
55 SataSpeedGen1,
56 SataSpeedGen2,
57 SataSpeedGen3
58 } SATA_SPEED;
59
60 typedef enum {
61 SataRstMsix,
62 SataRstMsi,
63 SataRstLegacy
64 } SATA_RST_INTERRUPT;
65
66 typedef enum {
67 SataRaidClient,
68 SataRaidAlternate,
69 SataRaidServer
70 } SATA_RAID_DEV_ID;
71
72 /**
73 This structure configures the features, property, and capability for each SATA port.
74 **/
75 typedef struct {
76 /**
77 Enable SATA port.
78 It is highly recommended to disable unused ports for power savings
79 **/
80 UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>
81 UINT32 HotPlug : 1; ///< <b>0: Disable</b>; 1: Enable
82 UINT32 InterlockSw : 1; ///< <b>0: Disable</b>; 1: Enable
83 UINT32 External : 1; ///< <b>0: Disable</b>; 1: Enable
84 UINT32 SpinUp : 1; ///< <b>0: Disable</b>; 1: Enable the COMRESET initialization Sequence to the device
85 UINT32 SolidStateDrive : 1; ///< <b>0: HDD</b>; 1: SSD
86 UINT32 DevSlp : 1; ///< <b>0: Disable</b>; 1: Enable DEVSLP on the port
87 UINT32 EnableDitoConfig : 1; ///< <b>0: Disable</b>; 1: Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)
88 UINT32 DmVal : 4; ///< DITO multiplier. Default is <b>15</b>.
89 UINT32 DitoVal : 10; ///< DEVSLP Idle Timeout (DITO), Default is <b>625</b>.
90 /**
91 Support zero power ODD <b>0: Disable</b>, 1: Enable.
92 This is also used to disable ModPHY dynamic power gate.
93 **/
94 UINT32 ZpOdd : 1;
95 UINT32 DevSlpResetConfig : 4; ///< 0: Hardware default; <b>0x01: GpioResumeReset</b>; 0x03: GpioHostDeepReset; 0x05: GpioPlatformReset; 0x07: GpioDswReset
96 UINT32 RxPolarity : 1; ///< <b>0: Disable</b>; 1: Enable; Rx Polarity
97 UINT32 RsvdBits0 : 4; ///< Reserved fields for future expansion w/o protocol change
98 UINT32 DevSlpGpioPinMux; /// Muxed GPIO details. Refer GPIO_*_MUXING_SATA_DEVSLP_x*
99 } PCH_SATA_PORT_CONFIG;
100
101 /**
102 This structure lists PCH supported SATA thermal throttling register setting for customization.
103 The settings is programmed through SATA Index/Data registers.
104 When the SuggestedSetting is enabled, the customized values are ignored.
105 **/
106 typedef struct {
107 UINT32 P0T1M : 2; ///< Port 0 T1 Multipler
108 UINT32 P0T2M : 2; ///< Port 0 T2 Multipler
109 UINT32 P0T3M : 2; ///< Port 0 T3 Multipler
110 UINT32 P0TDisp : 2; ///< Port 0 Tdispatch
111
112 UINT32 P1T1M : 2; ///< Port 1 T1 Multipler
113 UINT32 P1T2M : 2; ///< Port 1 T2 Multipler
114 UINT32 P1T3M : 2; ///< Port 1 T3 Multipler
115 UINT32 P1TDisp : 2; ///< Port 1 Tdispatch
116
117 UINT32 P0Tinact : 2; ///< Port 0 Tinactive
118 UINT32 P0TDispFinit : 1; ///< Port 0 Alternate Fast Init Tdispatch
119 UINT32 P1Tinact : 2; ///< Port 1 Tinactive
120 UINT32 P1TDispFinit : 1; ///< Port 1 Alternate Fast Init Tdispatch
121 UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values
122 UINT32 RsvdBits0 : 9; ///< Reserved bits
123 } SATA_THERMAL_THROTTLING;
124
125 /**
126 The SATA_CONFIG block describes the expected configuration of the SATA controllers.
127
128 <b>Revision 1</b>:
129 - Initial version.
130 <b>Revision 2</b>:
131 - Added DevSlpGpioPinMux.
132 **/
133 typedef struct {
134 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
135 ///
136 /// This member describes whether or not the SATA controllers should be enabled. 0: Disable; <b>1: Enable</b>.
137 ///
138 UINT8 Enable;
139 UINT8 TestMode; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Allow entrance to the PCH SATA test modes
140 UINT8 SalpSupport; ///< 0: Disable; <b>1: Enable</b> Aggressive Link Power Management
141 UINT8 PwrOptEnable; ///< 0: Disable; <b>1: Enable</b> SATA Power Optimizer on PCH side.
142 /**
143 EsataSpeedLimit
144 When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
145 Please be noted, this setting could be cleared by HBA reset, which might be issued
146 by EFI AHCI driver when POST time, or by SATA inbox driver/RST driver after POST.
147 To support the Speed Limitation when POST, the EFI AHCI driver should preserve the
148 setting before and after initialization. For support it after POST, it's dependent on
149 driver's behavior.
150 <b>0: Disable</b>; 1: Enable
151 **/
152 UINT8 EsataSpeedLimit;
153 UINT8 LedEnable; ///< SATA LED indicates SATA controller activity. 0: Disable; <b>1: Enable</b> SATA LED.
154 /**
155 This option allows to configure SATA controller device ID while in RAID mode.
156 Refer to SATA_RAID_DEV_ID enumeration for supported options.
157 Choosing Client will allow RST driver loading, RSTe driver will not be able to load
158 Choosing Alternate will not allow RST inbox driver loading in Windows
159 Choosing Server will allow RSTe driver loading, RST driver will not load
160 <b>0: Client</b>; 1: Alternate; 2: Server
161 **/
162 UINT8 RaidDeviceId;
163 /**
164 Controlls which interrupts will be linked to SATA controller CAP list
165 This option will take effect only if SATA controller is in RAID mode
166 Default: <b>PchSataMsix</b>
167 **/
168 UINT8 SataRstInterrupt;
169
170 /**
171 Determines the system will be configured to which SATA mode.
172 Refer to SATA_MODE enumeration for supported options. Default is <b>SataModeAhci</b>.
173 **/
174 UINT8 SataMode;
175 /**
176 Indicates the maximum speed the SATA controller can support.
177 Refer to SATA_SPEED enumeration for supported options.
178 <b>0h: SataSpeedDefault</b>; 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2); 3h: 6 Gb/s (Gen 1)
179 **/
180 UINT8 SpeedLimit;
181 UINT8 EnclosureSupport; ///< Enclosure Management Support. 0: Disable; 1: Enable
182 /**
183 Controlls whenever Serial GPIO support is enabled for controller
184 <b>0: Disable</b>; 1: Enable
185 **/
186 UINT8 SgpioSupport;
187 /**
188 This member configures the features, property, and capability for each SATA port.
189 **/
190 PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS];
191 /**
192 This field decides the settings of Sata thermal throttling. When the Suggested Setting
193 is enabled, PCH RC will use the suggested representative values.
194 **/
195 SATA_THERMAL_THROTTLING ThermalThrottling;
196 } SATA_CONFIG;
197
198 #pragma pack (pop)
199
200 #endif // _SATA_CONFIG_H_
SATA_THERMAL_THROTTLING::P1Tinact
UINT32 P1Tinact
Port 1 Tinactive.
Definition: SataConfig.h:119
PCH_SATA_PORT_CONFIG::HotPlug
UINT32 HotPlug
0: Disable; 1: Enable
Definition: SataConfig.h:81
SATA_CONFIG::SpeedLimit
UINT8 SpeedLimit
Indicates the maximum speed the SATA controller can support.
Definition: SataConfig.h:180
ConfigBlock.h
Header file for Config Block Lib implementation.
SATA_THERMAL_THROTTLING::P0Tinact
UINT32 P0Tinact
Port 0 Tinactive.
Definition: SataConfig.h:117
SATA_THERMAL_THROTTLING::P0T2M
UINT32 P0T2M
Port 0 T2 Multipler.
Definition: SataConfig.h:108
SATA_CONFIG::SataRstInterrupt
UINT8 SataRstInterrupt
Controlls which interrupts will be linked to SATA controller CAP list This option will take effect on...
Definition: SataConfig.h:168
PCH_SATA_PORT_CONFIG::RxPolarity
UINT32 RxPolarity
0: Disable; 1: Enable; Rx Polarity
Definition: SataConfig.h:96
SATA_CONFIG::PwrOptEnable
UINT8 PwrOptEnable
0: Disable; 1: Enable SATA Power Optimizer on PCH side.
Definition: SataConfig.h:141
SATA_THERMAL_THROTTLING::P0T3M
UINT32 P0T3M
Port 0 T3 Multipler.
Definition: SataConfig.h:109
SATA_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: SataConfig.h:134
PCH_SATA_PORT_CONFIG::External
UINT32 External
0: Disable; 1: Enable
Definition: SataConfig.h:83
SATA_THERMAL_THROTTLING::P1TDisp
UINT32 P1TDisp
Port 1 Tdispatch.
Definition: SataConfig.h:115
SATA_CONFIG::LedEnable
UINT8 LedEnable
SATA LED indicates SATA controller activity. 0: Disable; 1: Enable SATA LED.
Definition: SataConfig.h:153
SATA_CONFIG::SgpioSupport
UINT8 SgpioSupport
Controlls whenever Serial GPIO support is enabled for controller 0: Disable; 1: Enable.
Definition: SataConfig.h:186
SATA_THERMAL_THROTTLING::P0T1M
UINT32 P0T1M
Port 0 T1 Multipler.
Definition: SataConfig.h:107
SATA_THERMAL_THROTTLING::P1T1M
UINT32 P1T1M
Port 1 T1 Multipler.
Definition: SataConfig.h:112
SATA_CONFIG::EnclosureSupport
UINT8 EnclosureSupport
Enclosure Management Support. 0: Disable; 1: Enable.
Definition: SataConfig.h:181
SATA_CONFIG::Enable
UINT8 Enable
This member describes whether or not the SATA controllers should be enabled.
Definition: SataConfig.h:138
SATA_CONFIG
The SATA_CONFIG block describes the expected configuration of the SATA controllers.
Definition: SataConfig.h:133
SATA_THERMAL_THROTTLING::P0TDispFinit
UINT32 P0TDispFinit
Port 0 Alternate Fast Init Tdispatch.
Definition: SataConfig.h:118
PCH_SATA_PORT_CONFIG::InterlockSw
UINT32 InterlockSw
0: Disable; 1: Enable
Definition: SataConfig.h:82
PCH_SATA_PORT_CONFIG::Enable
UINT32 Enable
Enable SATA port.
Definition: SataConfig.h:80
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_SATA_PORT_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved fields for future expansion w/o protocol change.
Definition: SataConfig.h:97
PCH_SATA_PORT_CONFIG::ZpOdd
UINT32 ZpOdd
Support zero power ODD 0: Disable, 1: Enable.
Definition: SataConfig.h:94
PCH_SATA_PORT_CONFIG::SolidStateDrive
UINT32 SolidStateDrive
0: HDD; 1: SSD
Definition: SataConfig.h:85
PCH_SATA_PORT_CONFIG::DevSlp
UINT32 DevSlp
0: Disable; 1: Enable DEVSLP on the port
Definition: SataConfig.h:86
SATA_CONFIG::RaidDeviceId
UINT8 RaidDeviceId
This option allows to configure SATA controller device ID while in RAID mode.
Definition: SataConfig.h:162
PCH_SATA_PORT_CONFIG::DmVal
UINT32 DmVal
DITO multiplier. Default is 15.
Definition: SataConfig.h:88
SATA_CONFIG::TestMode
UINT8 TestMode
(Test) 0: Disable; 1: Allow entrance to the PCH SATA test modes
Definition: SataConfig.h:139
PCH_SATA_PORT_CONFIG
This structure configures the features, property, and capability for each SATA port.
Definition: SataConfig.h:75
SATA_CONFIG::EsataSpeedLimit
UINT8 EsataSpeedLimit
EsataSpeedLimit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
Definition: SataConfig.h:152
SATA_THERMAL_THROTTLING::SuggestedSetting
UINT32 SuggestedSetting
0: Disable; 1: Enable suggested representative values
Definition: SataConfig.h:121
SATA_THERMAL_THROTTLING::P1TDispFinit
UINT32 P1TDispFinit
Port 1 Alternate Fast Init Tdispatch.
Definition: SataConfig.h:120
SATA_THERMAL_THROTTLING
This structure lists PCH supported SATA thermal throttling register setting for customization.
Definition: SataConfig.h:106
SATA_CONFIG::SalpSupport
UINT8 SalpSupport
0: Disable; 1: Enable Aggressive Link Power Management
Definition: SataConfig.h:140
PCH_SATA_PORT_CONFIG::DitoVal
UINT32 DitoVal
DEVSLP Idle Timeout (DITO), Default is 625.
Definition: SataConfig.h:89
SATA_THERMAL_THROTTLING::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: SataConfig.h:122
SATA_CONFIG::ThermalThrottling
SATA_THERMAL_THROTTLING ThermalThrottling
This field decides the settings of Sata thermal throttling.
Definition: SataConfig.h:195
SATA_CONFIG::SataMode
UINT8 SataMode
Determines the system will be configured to which SATA mode.
Definition: SataConfig.h:174
SATA_THERMAL_THROTTLING::P1T2M
UINT32 P1T2M
Port 1 T2 Multipler.
Definition: SataConfig.h:113
PCH_SATA_PORT_CONFIG::EnableDitoConfig
UINT32 EnableDitoConfig
0: Disable; 1: Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)
Definition: SataConfig.h:87
SATA_THERMAL_THROTTLING::P0TDisp
UINT32 P0TDisp
Port 0 Tdispatch.
Definition: SataConfig.h:110
PCH_SATA_PORT_CONFIG::DevSlpResetConfig
UINT32 DevSlpResetConfig
0: Hardware default; 0x01: GpioResumeReset; 0x03: GpioHostDeepReset; 0x05: GpioPlatformReset; 0x07: G...
Definition: SataConfig.h:95
SATA_THERMAL_THROTTLING::P1T3M
UINT32 P1T3M
Port 1 T3 Multipler.
Definition: SataConfig.h:114
PCH_SATA_PORT_CONFIG::SpinUp
UINT32 SpinUp
0: Disable; 1: Enable the COMRESET initialization Sequence to the device
Definition: SataConfig.h:84
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SerialIoConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • SerialIo
Classes | Macros
SerialIoConfig.h File Reference

Serial IO policy. More...

#include <SerialIoDevices.h>
Include dependency graph for SerialIoConfig.h:

Go to the source code of this file.

Classes

struct SERIAL_IO_CONFIG
The SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers. More...

Macros

#define SERIAL_IO_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Detailed Description

Serial IO policy.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2022 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SerialIoConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SerialIoConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • SerialIo
SerialIoConfig.h
Go to the documentation of this file.
1 /** @file
2 Serial IO policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2022 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SERIAL_IO_CONFIG_H_
36 #define _SERIAL_IO_CONFIG_H_
37
38 /**
39 Making any structure change after API Lock
40 will need to maintain backward compatibility, bump up
41 structure revision and update below history table\n
42 <b>Revision 1</b>: - Initial version.
43 **/
44 #define SERIAL_IO_CONFIG_REVISION 1
45 extern EFI_GUID gSerialIoConfigGuid;
46
47 #include <SerialIoDevices.h>
48
49 #pragma pack (push,1)
50
51 /**
52 The SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers
53
54 <b>Revision 1:</b>
55 - Inital version.
56 <b>Revision 2:</b>
57 - Modified SPI Config to support pinmux functionality.
58 <b>Revision 3:</b>
59 - Modified I3C Config to support more controllers.
60 **/
61 typedef struct {
62 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
63 SERIAL_IO_SPI_CONFIG SpiDeviceConfig[PCH_MAX_SERIALIO_SPI_CONTROLLERS]; ///< SPI Configuration
64 SERIAL_IO_I2C_CONFIG I2cDeviceConfig[PCH_MAX_SERIALIO_I2C_CONTROLLERS]; ///< I2C Configuration
65 SERIAL_IO_I3C_CONFIG I3cDeviceConfig[PCH_MAX_SERIALIO_I3C_CONTROLLERS]; ///< I3C Configuration
66 SERIAL_IO_UART_CONFIG UartDeviceConfig[PCH_MAX_SERIALIO_UART_CONTROLLERS]; ///< UART Configuration
67 } SERIAL_IO_CONFIG;
68
69 #pragma pack (pop)
70
71 #endif // _SERIAL_IO_CONFIG_H_
SERIAL_IO_I3C_CONFIG
The SERIAL_IO_I3C_CONFIG provides the configurations for Serial IO I3C controller.
Definition: SerialIoDevices.h:269
SerialIoDevices.h
Serial IO policy.
SERIAL_IO_I2C_CONFIG
Serial IO I2C Controller Configuration.
Definition: SerialIoDevices.h:220
SERIAL_IO_SPI_CONFIG
The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller.
Definition: SerialIoDevices.h:86
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
SERIAL_IO_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: SerialIoConfig.h:62
SERIAL_IO_UART_CONFIG
Serial IO UART Controller Configuration.
Definition: SerialIoDevices.h:166
SERIAL_IO_CONFIG
The SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers.
Definition: SerialIoConfig.h:61
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SerialIoDevices.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Enumerations
SerialIoDevices.h File Reference

Serial IO policy. More...

#include <Protocol/SerialIo.h>
#include <PchLimits.h>
Include dependency graph for SerialIoDevices.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | SPI_PIN_MUX
SPI signals pin muxing settings. More...
struct | SERIAL_IO_SPI_CONFIG
The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller. More...
struct | SERIAL_IO_UART_ATTRIBUTES
UART Settings. More...
struct | UART_PIN_MUX
UART signals pin muxing settings. More...
struct | SERIAL_IO_UART_CONFIG
Serial IO UART Controller Configuration. More...
struct | I2C_PIN_MUX
I2C signals pin muxing settings. More...
struct | SERIAL_IO_I2C_CONFIG
Serial IO I2C Controller Configuration. More...
struct | MUX_GPIO_CONFIG
I3C GPIO settings. More...
struct | SERIAL_IO_I3C_CONFIG
The SERIAL_IO_I3C_CONFIG provides the configurations for Serial IO I3C controller. More...

Enumerations

enum | SERIAL_IO_SPI_MODE
Available working modes for SerialIo SPI Host Controller. More...
enum | SERIAL_IO_CS_POLARITY
Used to set Inactive/Idle polarity of Spi Chip Select.
enum | SERIAL_IO_UART_MODE
Available working modes for SerialIo UART Host Controller. More...
enum | SERIAL_IO_UART_PG
enum | SERIAL_IO_I2C_MODE
Available working modes for SerialIo I2C Host Controller. More...
enum | SERIAL_IO_I3C_MODE
Available working modes for SerialIo I3C Host Controller. More...

Detailed Description

Serial IO policy.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2022 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SerialIoDevices.h.

Enumeration Type Documentation

◆ SERIAL_IO_I2C_MODE

enum SERIAL_IO_I2C_MODE

Available working modes for SerialIo I2C Host Controller.

 0: SerialIoI2cDisabled;
    - Device is placed in D3
    - Gpio configuration is skipped
    - PSF:
    !important! If given device is Function 0 and other higher functions on given device
                are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
                This is needed to allow PCI enumerator access functions above 0 in a multifunction device.

1: SerialIoI2cPci;

  • Gpio pin configuration in native mode for each assigned pin
  • Device will be enabled in PSF
  • Only BAR0 will be enabled

Definition at line 202 of file SerialIoDevices.h.

◆ SERIAL_IO_I3C_MODE

enum SERIAL_IO_I3C_MODE

Available working modes for SerialIo I3C Host Controller.

 0: SerialIoI3cDisabled;
    - Device is placed in D3
    - Gpio configuration is skipped
    - Device will be disabled in PSF

1: SerialIoI3cPci;

  • Gpio pin configuration in native mode for each assigned pin SDA and SCL
  • Device will be enabled in PSF
  • Only Bar 0 will be enabled 2: SerialIoI3cPhantom;
  • Dedicated mode for I3C1, controls if GPIOs are enabled

Definition at line 252 of file SerialIoDevices.h.

◆ SERIAL_IO_SPI_MODE

enum SERIAL_IO_SPI_MODE

Available working modes for SerialIo SPI Host Controller.

 0: SerialIoSpiDisabled;
    - Device is placed in D3
    - Gpio configuration is skipped
    - PSF:
    !important! If given device is Function 0 and other higher functions on given device
                are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
                This is needed to allow PCI enumerator access functions above 0 in a multifunction device.

1: SerialIoSpiPci;

  • Gpio pin configuration in native mode for each assigned pin
  • Device will be enabled in PSF
  • Only BAR0 will be enabled

Definition at line 58 of file SerialIoDevices.h.

◆ SERIAL_IO_UART_MODE

enum SERIAL_IO_UART_MODE

Available working modes for SerialIo UART Host Controller.

 0: SerialIoUartDisabled;
    - Device is placed in D3
    - Gpio configuration is skipped
    - PSF:
    !important! If given device is Function 0 and other higher functions on given device
                are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
                This is needed to allow PCI enumerator access functions above 0 in a multifunction device.

1: SerialIoUartPci;

  • Designated for Serial IO UART OS driver usage
  • Gpio pin configuration in native mode for each assigned pin
  • Device will be enabled in PSF
  • Only BAR0 will be enabled 2: SerialIoUartHidden;
  • Designated for BIOS and/or DBG2 OS kernel debug
  • Gpio pin configuration in native mode for each assigned pin
  • Device disabled in the PSF
  • Both BARs are enabled, BAR1 becomes devices Pci Config Space
  • BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
    Note
    If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space. 3: SerialIoUartCom;
  • Designated for 16550/PNP0501 compatible COM device
  • Gpio pin configuration in native mode for each assigned pin
  • Device disabled in the PSF
  • Both BARs are enabled, BAR1 becomes devices Pci Config Space
  • BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC 4: SerialIoUartSkipInit;
  • Gpio configuration is skipped
  • PSF configuration is skipped
  • BAR assignemnt is skipped
  • D-satate setting is skipped

Definition at line 132 of file SerialIoDevices.h.

◆ SERIAL_IO_UART_PG

enum SERIAL_IO_UART_PG
Enumerator
SerialIoUartPgDisabled | No _PS0/_PS3 support, device left in D0, after initialization.
SerialIoUartPgEnabled | In mode: SerialIoUartCom; _PS0/_PS3 that supports getting device out of reset In mode: SerialIoUartPci Keeps UART in D0 and assigns Fixed MMIO for SEC/PEI usage only.
SerialIoUartPgAuto | _PS0 and _PS3, detection through ACPI if device was initialized prior to first PG. If it was used (DBG2) PG is disabled,

Definition at line 175 of file SerialIoDevices.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SerialIoDevices.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
SerialIoDevices.h
Go to the documentation of this file.
1 /** @file
2 Serial IO policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2022 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SERIAL_IO_DEVICES_H_
36 #define _SERIAL_IO_DEVICES_H_
37
38 #include <Protocol/SerialIo.h>
39 #include <PchLimits.h>
40
41 #pragma pack (push,1)
42
43 /**
44 Available working modes for SerialIo SPI Host Controller
45
46 0: SerialIoSpiDisabled;
47 - Device is placed in D3
48 - Gpio configuration is skipped
49 - PSF:
50 !important! If given device is Function 0 and other higher functions on given device
51 are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
52 This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
53 <b>1: SerialIoSpiPci;</b>
54 - Gpio pin configuration in native mode for each assigned pin
55 - Device will be enabled in PSF
56 - Only BAR0 will be enabled
57 **/
58 typedef enum {
59 SerialIoSpiDisabled,
60 SerialIoSpiPci
61 } SERIAL_IO_SPI_MODE;
62
63 /**
64 Used to set Inactive/Idle polarity of Spi Chip Select
65 **/
66 typedef enum {
67 SerialIoSpiCsActiveLow = 0,
68 SerialIoSpiCsActiveHigh = 1
69 } SERIAL_IO_CS_POLARITY;
70
71 /**
72 SPI signals pin muxing settings. If signal can be enable only on a single pin
73 then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_SPIx_* in GpioPins*.h
74 for supported settings on a given platform
75 **/
76 typedef struct {
77 UINT32 Cs[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< CS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS_*
78 UINT32 Clk; ///< CLK Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK_*
79 UINT32 Miso; ///< MISO Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO_*
80 UINT32 Mosi; ///< MOSI Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI_*
81 } SPI_PIN_MUX;
82
83 /**
84 The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller
85 **/
86 typedef struct {
87 UINT8 Mode; ///< <b>SerialIoSpiPci </b> see SERIAL_IO_SPI_MODE
88 UINT8 DefaultCsOutput; ///< <b>0 = CS0</b> CS1, CS2, CS3. Default CS used by the SPI HC
89 UINT8 CsPolarity[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< Selects SPI ChipSelect signal polarity, 0 = low <b>1 = High</b>
90 UINT8 CsEnable[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< <b>0 = Enable</b> 1 = Disable. Based on this setting GPIO for given SPIx CSx will be configured in Native mode
91 UINT8 CsMode; ///< <b>0 = HW Control</b> 1 = SW Control. Sets Chip Select Control mode Hardware or Software.
92 UINT8 CsState; ///< <b>0 = CS is set to low</b> 1 = CS is set to high
93 SPI_PIN_MUX PinMux; ///< SPI Pinmux configuration
94 } SERIAL_IO_SPI_CONFIG;
95
96 /**
97 Available working modes for SerialIo UART Host Controller
98
99 0: SerialIoUartDisabled;
100 - Device is placed in D3
101 - Gpio configuration is skipped
102 - PSF:
103 !important! If given device is Function 0 and other higher functions on given device
104 are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
105 This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
106 <b>1: SerialIoUartPci;</b>
107 - Designated for Serial IO UART OS driver usage
108 - Gpio pin configuration in native mode for each assigned pin
109 - Device will be enabled in PSF
110 - Only BAR0 will be enabled
111 2: SerialIoUartHidden;
112 - Designated for BIOS and/or DBG2 OS kernel debug
113 - Gpio pin configuration in native mode for each assigned pin
114 - Device disabled in the PSF
115 - Both BARs are enabled, BAR1 becomes devices Pci Config Space
116 - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
117 @note
118 If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
119 3: SerialIoUartCom;
120 - Designated for 16550/PNP0501 compatible COM device
121 - Gpio pin configuration in native mode for each assigned pin
122 - Device disabled in the PSF
123 - Both BARs are enabled, BAR1 becomes devices Pci Config Space
124 - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
125 4: SerialIoUartSkipInit;
126 - Gpio configuration is skipped
127 - PSF configuration is skipped
128 - BAR assignemnt is skipped
129 - D-satate setting is skipped
130
131 **/
132 typedef enum {
133 SerialIoUartDisabled,
134 SerialIoUartPci,
135 SerialIoUartHidden,
136 SerialIoUartCom,
137 SerialIoUartSkipInit
138 } SERIAL_IO_UART_MODE;
139
140 /**
141 UART Settings
142 **/
143 typedef struct {
144 UINT32 BaudRate; ///< <b> 115200 </b> Max 6000000 MdePkg.dec PcdUartDefaultBaudRate
145 UINT8 Parity; ///< <b> 1 - No Parity</b> see EFI_PARITY_TYPE MdePkg.dec PcdUartDefaultParity
146 UINT8 DataBits; ///< <b>8</b> MdePkg.dec PcdUartDefaultDataBits
147 UINT8 StopBits; ///< <b>1 - One Stop Bit</b> see EFI_STOP_BITS_TYPE MdePkg.dec PcdUartDefaultStopBits
148 UINT8 AutoFlow; ///< <b>FALSE</b> IntelFrameworkModulePkg.dsc PcdIsaBusSerialUseHalfHandshake
149 } SERIAL_IO_UART_ATTRIBUTES;
150
151 /**
152 UART signals pin muxing settings. If signal can be enable only on a single pin
153 then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_UARTx_* in GpioPins*.h
154 for supported settings on a given platform
155 **/
156 typedef struct {
157 UINT32 Rx; ///< RXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RXD_*
158 UINT32 Tx; ///< TXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TXD_*
159 UINT32 Rts; ///< RTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS_*
160 UINT32 Cts; ///< CTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS_*
161 } UART_PIN_MUX;
162
163 /**
164 Serial IO UART Controller Configuration
165 **/
166 typedef struct {
167 SERIAL_IO_UART_ATTRIBUTES Attributes; ///< see SERIAL_IO_UART_ATTRIBUTES
168 UART_PIN_MUX PinMux; ///< UART pin mux configuration
169 UINT8 Mode; ///< <b> SerialIoUartPci </b> see SERIAL_IO_UART_MODE
170 UINT8 DBG2; ///< <b> FALSE </b> If TRUE adds UART to DBG2 table and overrides UartPg to SerialIoUartPgDisabled
171 UINT8 PowerGating; ///< <b> SerialIoUartPgAuto </b> Applies to Hidden/COM/SkipInit see SERIAL_IO_UART_PG
172 UINT8 DmaEnable; ///< <b> TRUE </b> Applies to SerialIoUartPci only. Informs OS driver to use DMA, if false it will run in PIO mode
173 } SERIAL_IO_UART_CONFIG;
174
175 typedef enum {
176 SerialIoUartPgDisabled, ///< No _PS0/_PS3 support, device left in D0, after initialization
177 /**
178 In mode: SerialIoUartCom;
179 _PS0/_PS3 that supports getting device out of reset
180 In mode: SerialIoUartPci
181 Keeps UART in D0 and assigns Fixed MMIO for SEC/PEI usage only
182 **/
183 SerialIoUartPgEnabled,
184 SerialIoUartPgAuto ///< _PS0 and _PS3, detection through ACPI if device was initialized prior to first PG. If it was used (DBG2) PG is disabled,
185 } SERIAL_IO_UART_PG;
186
187 /**
188 Available working modes for SerialIo I2C Host Controller
189
190 0: SerialIoI2cDisabled;
191 - Device is placed in D3
192 - Gpio configuration is skipped
193 - PSF:
194 !important! If given device is Function 0 and other higher functions on given device
195 are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
196 This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
197 <b>1: SerialIoI2cPci;</b>
198 - Gpio pin configuration in native mode for each assigned pin
199 - Device will be enabled in PSF
200 - Only BAR0 will be enabled
201 **/
202 typedef enum {
203 SerialIoI2cDisabled,
204 SerialIoI2cPci
205 } SERIAL_IO_I2C_MODE;
206
207 /**
208 I2C signals pin muxing settings. If signal can be enable only on a single pin
209 then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_* in GpioPins*.h
210 for supported settings on a given platform
211 **/
212 typedef struct {
213 UINT32 Sda; ///< SDA Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA_*
214 UINT32 Scl; ///< SCL Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL_*
215 } I2C_PIN_MUX;
216
217 /**
218 Serial IO I2C Controller Configuration
219 **/
220 typedef struct {
221 UINT8 Mode; /// <b>SerialIoI2cPci <b> see SERIAL_IO_I2C_MODE
222 /**
223 I2C Pads Internal Termination.
224 For more information please see Platform Design Guide.
225 Supported values (check GPIO_ELECTRICAL_CONFIG for reference):
226 <b>GpioTermNone: No termination</b>,
227 GpioTermWpu1K: 1kOhm weak pull-up,
228 GpioTermWpu5K: 5kOhm weak pull-up,
229 GpioTermWpu20K: 20kOhm weak pull-up
230 **/
231 UINT8 PadTermination;
232 UINT8 Reserved[2];
233 I2C_PIN_MUX PinMux; ///< I2C pin mux configuration
234 } SERIAL_IO_I2C_CONFIG;
235
236
237 /**
238 Available working modes for SerialIo I3C Host Controller
239
240 0: SerialIoI3cDisabled;
241 - Device is placed in D3
242 - Gpio configuration is skipped
243 - Device will be disabled in PSF
244 <b>1: SerialIoI3cPci</b>;
245 - Gpio pin configuration in native mode for each assigned pin
246 SDA and SCL
247 - Device will be enabled in PSF
248 - Only Bar 0 will be enabled
249 2: SerialIoI3cPhantom;
250 - Dedicated mode for I3C1, controls if GPIOs are enabled
251 **/
252 typedef enum {
253 SerialIoI3cDisabled,
254 SerialIoI3cPci,
255 SerialIoI3cPhantom
256 } SERIAL_IO_I3C_MODE;
257
258 /**
259 I3C GPIO settings
260 **/
261 typedef struct {
262 UINT32 PinMux; /// GPIO signals pin muxing settings.
263 UINT32 PadTermination; /// GPIO Pads Internal Termination.
264 } MUX_GPIO_CONFIG;
265
266 /**
267 The SERIAL_IO_I3C_CONFIG provides the configurations for Serial IO I3C controller
268 **/
269 typedef struct {
270 UINT8 Mode; ///< <b<SerialIoI3cPci <b> see SERIAL_IO_I3C_MODE
271 UINT8 Reserved[3]; ///< Reserved bytes
272 MUX_GPIO_CONFIG Sda;
273 MUX_GPIO_CONFIG Scl;
274 MUX_GPIO_CONFIG SclFb;
275
276 } SERIAL_IO_I3C_CONFIG;
277
278 #pragma pack (pop)
279
280 #endif // _SERIAL_IO_DEVICES_H_
SERIAL_IO_UART_ATTRIBUTES::BaudRate
UINT32 BaudRate
115200 Max 6000000 MdePkg.dec PcdUartDefaultBaudRate
Definition: SerialIoDevices.h:144
SERIAL_IO_UART_CONFIG::Attributes
SERIAL_IO_UART_ATTRIBUTES Attributes
see SERIAL_IO_UART_ATTRIBUTES
Definition: SerialIoDevices.h:167
SERIAL_IO_I3C_MODE
SERIAL_IO_I3C_MODE
Available working modes for SerialIo I3C Host Controller.
Definition: SerialIoDevices.h:252
SERIAL_IO_I3C_CONFIG
The SERIAL_IO_I3C_CONFIG provides the configurations for Serial IO I3C controller.
Definition: SerialIoDevices.h:269
SERIAL_IO_I3C_CONFIG::Mode
UINT8 Mode
<b<SerialIoI3cPci see SERIAL_IO_I3C_MODE
Definition: SerialIoDevices.h:270
SERIAL_IO_SPI_CONFIG::DefaultCsOutput
UINT8 DefaultCsOutput
0 = CS0 CS1, CS2, CS3. Default CS used by the SPI HC
Definition: SerialIoDevices.h:88
SERIAL_IO_UART_MODE
SERIAL_IO_UART_MODE
Available working modes for SerialIo UART Host Controller.
Definition: SerialIoDevices.h:132
SPI_PIN_MUX::Mosi
UINT32 Mosi
MOSI Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI_*.
Definition: SerialIoDevices.h:80
SERIAL_IO_SPI_CONFIG::PinMux
SPI_PIN_MUX PinMux
SPI Pinmux configuration.
Definition: SerialIoDevices.h:93
SERIAL_IO_UART_CONFIG::Mode
UINT8 Mode
SerialIoUartPci see SERIAL_IO_UART_MODE
Definition: SerialIoDevices.h:169
SERIAL_IO_UART_ATTRIBUTES
UART Settings.
Definition: SerialIoDevices.h:143
SERIAL_IO_UART_ATTRIBUTES::StopBits
UINT8 StopBits
1 - One Stop Bit see EFI_STOP_BITS_TYPE MdePkg.dec PcdUartDefaultStopBits
Definition: SerialIoDevices.h:147
I2C_PIN_MUX
I2C signals pin muxing settings.
Definition: SerialIoDevices.h:212
SERIAL_IO_UART_CONFIG::PowerGating
UINT8 PowerGating
SerialIoUartPgAuto Applies to Hidden/COM/SkipInit see SERIAL_IO_UART_PG
Definition: SerialIoDevices.h:171
SERIAL_IO_I2C_CONFIG
Serial IO I2C Controller Configuration.
Definition: SerialIoDevices.h:220
SERIAL_IO_UART_PG
SERIAL_IO_UART_PG
Definition: SerialIoDevices.h:175
I2C_PIN_MUX::Scl
UINT32 Scl
SCL Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL_*.
Definition: SerialIoDevices.h:214
SERIAL_IO_UART_CONFIG::PinMux
UART_PIN_MUX PinMux
UART pin mux configuration.
Definition: SerialIoDevices.h:168
UART_PIN_MUX::Rx
UINT32 Rx
RXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RXD_*.
Definition: SerialIoDevices.h:157
SERIAL_IO_I2C_CONFIG::PadTermination
UINT8 PadTermination
SerialIoI2cPci see SERIAL_IO_I2C_MODE
Definition: SerialIoDevices.h:231
SERIAL_IO_UART_CONFIG::DBG2
UINT8 DBG2
FALSE If TRUE adds UART to DBG2 table and overrides UartPg to SerialIoUartPgDisabled
Definition: SerialIoDevices.h:170
SERIAL_IO_UART_CONFIG::DmaEnable
UINT8 DmaEnable
TRUE Applies to SerialIoUartPci only. Informs OS driver to use DMA, if false it will run in PIO mode
Definition: SerialIoDevices.h:172
UART_PIN_MUX::Rts
UINT32 Rts
RTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS_*.
Definition: SerialIoDevices.h:159
SERIAL_IO_SPI_CONFIG
The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller.
Definition: SerialIoDevices.h:86
I2C_PIN_MUX::Sda
UINT32 Sda
SDA Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA_*.
Definition: SerialIoDevices.h:213
SPI_PIN_MUX::Clk
UINT32 Clk
CLK Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK_*.
Definition: SerialIoDevices.h:78
SERIAL_IO_SPI_MODE
SERIAL_IO_SPI_MODE
Available working modes for SerialIo SPI Host Controller.
Definition: SerialIoDevices.h:58
UART_PIN_MUX
UART signals pin muxing settings.
Definition: SerialIoDevices.h:156
SPI_PIN_MUX
SPI signals pin muxing settings.
Definition: SerialIoDevices.h:76
SERIAL_IO_UART_CONFIG
Serial IO UART Controller Configuration.
Definition: SerialIoDevices.h:166
SERIAL_IO_CS_POLARITY
SERIAL_IO_CS_POLARITY
Used to set Inactive/Idle polarity of Spi Chip Select.
Definition: SerialIoDevices.h:66
SPI_PIN_MUX::Miso
UINT32 Miso
MISO Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO_*.
Definition: SerialIoDevices.h:79
MUX_GPIO_CONFIG
I3C GPIO settings.
Definition: SerialIoDevices.h:261
MUX_GPIO_CONFIG::PadTermination
UINT32 PadTermination
GPIO signals pin muxing settings.
Definition: SerialIoDevices.h:263
UART_PIN_MUX::Tx
UINT32 Tx
TXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TXD_*.
Definition: SerialIoDevices.h:158
SERIAL_IO_UART_ATTRIBUTES::DataBits
UINT8 DataBits
8 MdePkg.dec PcdUartDefaultDataBits
Definition: SerialIoDevices.h:146
SERIAL_IO_UART_ATTRIBUTES::Parity
UINT8 Parity
1 - No Parity see EFI_PARITY_TYPE MdePkg.dec PcdUartDefaultParity
Definition: SerialIoDevices.h:145
SERIAL_IO_I2C_MODE
SERIAL_IO_I2C_MODE
Available working modes for SerialIo I2C Host Controller.
Definition: SerialIoDevices.h:202
UART_PIN_MUX::Cts
UINT32 Cts
CTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS_*.
Definition: SerialIoDevices.h:160
SERIAL_IO_SPI_CONFIG::CsMode
UINT8 CsMode
0 = HW Control 1 = SW Control. Sets Chip Select Control mode Hardware or Software.
Definition: SerialIoDevices.h:91
SerialIoUartPgEnabled
@ SerialIoUartPgEnabled
In mode: SerialIoUartCom; _PS0/_PS3 that supports getting device out of reset In mode: SerialIoUartPc...
Definition: SerialIoDevices.h:183
SerialIoUartPgAuto
@ SerialIoUartPgAuto
_PS0 and _PS3, detection through ACPI if device was initialized prior to first PG....
Definition: SerialIoDevices.h:184
SerialIoUartPgDisabled
@ SerialIoUartPgDisabled
No _PS0/_PS3 support, device left in D0, after initialization.
Definition: SerialIoDevices.h:176
SERIAL_IO_UART_ATTRIBUTES::AutoFlow
UINT8 AutoFlow
FALSE IntelFrameworkModulePkg.dsc PcdIsaBusSerialUseHalfHandshake
Definition: SerialIoDevices.h:148
SERIAL_IO_SPI_CONFIG::Mode
UINT8 Mode
SerialIoSpiPci see SERIAL_IO_SPI_MODE
Definition: SerialIoDevices.h:87
SERIAL_IO_SPI_CONFIG::CsState
UINT8 CsState
0 = CS is set to low 1 = CS is set to high
Definition: SerialIoDevices.h:92
SERIAL_IO_I2C_CONFIG::PinMux
I2C_PIN_MUX PinMux
I2C pin mux configuration.
Definition: SerialIoDevices.h:233
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SiConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
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  • ClientOneSiliconPkg
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  • ConfigBlock
Classes
SiConfig.h File Reference

Si Config Block. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | SI_CONFIG
The Silicon Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware. More...
struct | SVID_SID_VALUE
Subsystem Vendor ID / Subsystem ID. More...

Detailed Description

Si Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SiConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SiConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
SiConfig.h
Go to the documentation of this file.
1 /** @file
2 Si Config Block
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SI_CONFIG_H_
36 #define _SI_CONFIG_H_
37
38 #define SI_CONFIG_REVISION 1
39
40 extern EFI_GUID gSiConfigGuid;
41
42
43 #pragma pack (push,1)
44
45 /**
46 The Silicon Policy allows the platform code to publish a set of configuration
47 information that the RC drivers will use to configure the silicon hardware.
48
49 <b>Revision 1</b>: - Initial version.
50 **/
51 typedef struct {
52 CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
53 //
54 // Platform specific common policies that used by several silicon components.
55 //
56 /**
57 This is used to skip the SSID programming in silicon code.
58 When set to TRUE, silicon code will not do any SSID programming and platform code
59 needs to handle that by itself properly.
60 <b>0: FALSE</b>, 1: TRUE
61 **/
62 UINT8 SkipSsidProgramming; ///< offset 28
63 UINT8 RsvdBytes0[3]; ///< offset 29 - 31
64 /**
65 When SkipSsidProgramming is FALSE, silicon code will use this as default value
66 to program the SVID for all internal devices.
67 <b>0: use silicon default SVID 0x8086 </b>, Non-zero: use customized SVID.
68 **/
69 UINT16 CustomizedSvid; ///< offset 32 - 33
70 /**
71 When SkipSsidProgramming is FALSE, silicon code will use this as default value
72 to program the Sid for all internal devices.
73 <b>0: use silicon default SSID 0x7270 </b>, Non-zero: use customized SSID.
74 **/
75 UINT16 CustomizedSsid; ///< offset 34 - 35
76 /**
77 SsidTablePtr contains the SVID_SID_INIT_ENTRY table.
78 This is valid when SkipSsidProgramming is FALSE;
79 It doesn't need to contain entries for all Intel internal devices.
80 It can only contains the SVID_SID_INIT_ENTRY entries for those Dev# Func# which needs
81 to be overridden.
82 In the enties, only Dev, Function, SubSystemVendorId, and SubSystemId are required.
83 <b>Default is NULL.</b>
84
85 E.g. Platform only needs to override BDF 0:31:5 to AAAA:BBBB and BDF 0:31:3 to CCCC:DDDD,
86 it can be done in platform like this:
87 STATIC SVID_SID_INIT_ENTRY mSsidTablePtr[SI_MAX_DEVICE_COUNT] = {0};
88
89 VOID SiPolicyUpdate () {
90 UINT32 EntryCount = 0;
91 SiPolicy->SkipSsidProgramming = FALSE;
92 SiPolicy->SsidTablePtr = mSsidTablePtr;
93
94 mSsidTablePtr[EntryCount].Address.Bits.Device = SpiDeviceNumber ();
95 mSsidTablePtr[EntryCount].Address.Bits.Function = SpiFunctionNumber ();
96 mSsidTablePtr[EntryCount].SvidSidValue.SubSystemVendorId = 0xAAAA;
97 mSsidTablePtr[EntryCount].SvidSidValue.SubSystemId = 0xBBBB;
98 EntryCount ++;
99 mSsidTablePtr[EntryCount].Address.Bits.Device = HdaDevNumber ();
100 mSsidTablePtr[EntryCount].Address.Bits.Function = HdaFuncNumber ();
101 mSsidTablePtr[EntryCount].SvidSidValue.SubSystemVendorId = 0xCCCC;
102 mSsidTablePtr[EntryCount].SvidSidValue.SubSystemId = 0xDDDD;
103 EntryCount ++;
104 ASSERT (EntryCount < SI_MAX_DEVICE_COUNT);
105 SiPolicy->NumberOfSsidTableEntry = EntryCount;
106 }
107 **/
108 UINT32 *SsidTablePtr; ///< offset 36 - 39
109 /**
110 Number of valid enties in SsidTablePtr.
111 This is valid when SkipSsidProgramming is FALSE;
112 <b>Default is 0.</b>
113 **/
114 UINT16 NumberOfSsidTableEntry; ///< offset 40 - 41
115 UINT8 RsvdBytes1[2]; ///< offset 42 - 43
116 /**
117 This is used to skip setting BIOS_DONE MSR during firmware update boot mode.
118 When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,
119 skip setting BIOS_DONE MSR at EndofPei.
120 <b>0: FALSE</b>, 1: TRUE
121 **/
122 UINT8 SkipBiosDoneWhenFwUpdate; ///< Offset 44
123 UINT8 RsvdBytes2[3]; ///< Offset 45 - 47
124 } SI_CONFIG;
125
126 #pragma pack (pop)
127
128 #define DEFAULT_SSVID 0x8086
129 #define DEFAULT_SSDID 0x7270
130 #define SI_MAX_DEVICE_COUNT 70
131
132 ///
133 /// Subsystem Vendor ID / Subsystem ID
134 ///
135 typedef struct {
136 UINT16 SubSystemVendorId;
137 UINT16 SubSystemId;
138 } SVID_SID_VALUE;
139
140 //
141 // Below is to match PCI_SEGMENT_LIB_ADDRESS () which can directly send to PciSegmentRead/Write functions.
142 //
143 typedef struct {
144 union {
145 struct {
146 UINT32 Register:12;
147 UINT32 Function:3;
148 UINT32 Device:5;
149 UINT32 Bus:8;
150 UINT32 Reserved1:4;
151 UINT32 Segment:16;
152 UINT32 Reserved2:16;
153 } Bits;
154 UINT64 SegBusDevFuncRegister;
155 } Address;
156 SVID_SID_VALUE SvidSidValue;
157 UINT32 Reserved;
158 } SVID_SID_INIT_ENTRY;
159
160
161 typedef struct {
162 UINT32 SkipBus;
163 UINT32 SkipDevice;
164 UINT32 SkipFunction;
165 } SVID_SID_SKIP_TABLE;
166
167 #endif // _SI_CONFIG_H_
SI_CONFIG::SkipBiosDoneWhenFwUpdate
UINT8 SkipBiosDoneWhenFwUpdate
This is used to skip setting BIOS_DONE MSR during firmware update boot mode.
Definition: SiConfig.h:122
SI_CONFIG::SsidTablePtr
UINT32 * SsidTablePtr
SsidTablePtr contains the SVID_SID_INIT_ENTRY table.
Definition: SiConfig.h:108
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
SI_CONFIG::CustomizedSsid
UINT16 CustomizedSsid
When SkipSsidProgramming is FALSE, silicon code will use this as default value to program the Sid for...
Definition: SiConfig.h:75
SI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0 - 27 Config Block Header.
Definition: SiConfig.h:52
SI_CONFIG
The Silicon Policy allows the platform code to publish a set of configuration information that the RC...
Definition: SiConfig.h:51
SVID_SID_VALUE
Subsystem Vendor ID / Subsystem ID.
Definition: SiConfig.h:135
SI_CONFIG::CustomizedSvid
UINT16 CustomizedSvid
When SkipSsidProgramming is FALSE, silicon code will use this as default value to program the SVID fo...
Definition: SiConfig.h:69
SI_CONFIG::NumberOfSsidTableEntry
UINT16 NumberOfSsidTableEntry
Number of valid enties in SsidTablePtr.
Definition: SiConfig.h:114
SI_CONFIG::SkipSsidProgramming
UINT8 SkipSsidProgramming
This is used to skip the SSID programming in silicon code.
Definition: SiConfig.h:62
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SiPolicy.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Product
  • MeteorLake
  • Include
  • Ppi
SiPolicy.h File Reference

Silicon Policy PPI is used for specifying platform related Intel silicon information and policy setting. More...

#include <SiPolicyStruct.h>
#include <PchPolicyCommon.h>
#include <PchPreMemPolicyCommon.h>
#include <MePeiConfig.h>
#include <AmtConfig.h>
#include <FusaConfig.h>
#include <Uefi.h>
#include <CpuPowerMgmt.h>
#include <CpuInitConfig.h>
#include <CpuPowerMgmtBasicConfig.h>
#include <CpuPowerMgmtCustomConfig.h>
#include <CpuPowerDeliveryConfig.h>
#include <CpuPowerMgmtTestConfig.h>
#include <CpuTestConfig.h>
#include <CpuInitPreMemConfig.h>
#include <CpuSecurityPreMemConfig.h>
#include <TxtConfig.h>
#include <BiosGuardConfig.h>
#include <ConfigBlock/VoltageRegulator/CpuPowerMgmtVrConfig.h>
#include <OverclockingConfig.h>
#include <FiaConfig.h>
#include <Defines/HostBridgeDefines.h>
#include <GraphicsConfig.h>
#include <VtdConfig.h>
#include <GnaConfig.h>
#include <HybridGraphicsConfig.h>
#include <MemoryConfig.h>
#include <ConfigBlock/SaMiscPeiPreMemConfig.h>
#include <TraceHubConfig.h>
#include <HostBridgeConfig.h>
#include <VpuConfig.h>
#include <PeiDmiConfig.h>
#include <DmiConfig.h>
#include <GpioV2PeiConfig.h>
Include dependency graph for SiPolicy.h:

Go to the source code of this file.

Detailed Description

Silicon Policy PPI is used for specifying platform related Intel silicon information and policy setting.

This PPI is consumed by the silicon PEI modules and carried over to silicon DXE modules.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2022 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SiPolicy.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SiPolicy.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Product
  • MeteorLake
  • Include
  • Ppi
SiPolicy.h
Go to the documentation of this file.
1 /** @file
2 Silicon Policy PPI is used for specifying platform
3 related Intel silicon information and policy setting.
4 This PPI is consumed by the silicon PEI modules and carried
5 over to silicon DXE modules.
6
7 @copyright
8 INTEL CONFIDENTIAL
9 Copyright 2014 - 2022 Intel Corporation.
10
11 The source code contained or described herein and all documents related to the
12 source code ("Material") are owned by Intel Corporation or its suppliers or
13 licensors. Title to the Material remains with Intel Corporation or its suppliers
14 and licensors. The Material may contain trade secrets and proprietary and
15 confidential information of Intel Corporation and its suppliers and licensors,
16 and is protected by worldwide copyright and trade secret laws and treaty
17 provisions. No part of the Material may be used, copied, reproduced, modified,
18 published, uploaded, posted, transmitted, distributed, or disclosed in any way
19 without Intel's prior express written permission.
20
21 No license under any patent, copyright, trade secret or other intellectual
22 property right is granted to or conferred upon you by disclosure or delivery
23 of the Materials, either expressly, by implication, inducement, estoppel or
24 otherwise. Any license under such intellectual property rights must be
25 express and approved by Intel in writing.
26
27 Unless otherwise agreed by Intel in writing, you may not remove or alter
28 this notice or any other notice embedded in Materials by Intel or
29 Intel's suppliers or licensors in any way.
30
31 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
32 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
33 the terms of your license agreement with Intel or your vendor. This file may
34 be modified by the user, subject to additional terms of the license agreement.
35
36 @par Specification Reference:
37 **/
38
39 #ifndef _SI_POLICY_PPI_H_
40 #define _SI_POLICY_PPI_H_
41
42 #include <SiPolicyStruct.h>
43 #include <PchPolicyCommon.h>
44 #include <PchPreMemPolicyCommon.h>
45 #include <MePeiConfig.h>
46 #include <AmtConfig.h>
47 #include <FusaConfig.h>
48 #include <Uefi.h>
49 #include <CpuPowerMgmt.h>
50 #include <CpuInitConfig.h>
51 #include <CpuPowerMgmtBasicConfig.h>
52 #include <CpuPowerMgmtCustomConfig.h>
53 #include <CpuPowerDeliveryConfig.h>
54 #include <CpuPowerMgmtTestConfig.h>
55 #include <CpuTestConfig.h>
56 #include <CpuInitPreMemConfig.h>
57 #include <CpuSecurityPreMemConfig.h>
58 #include <TxtConfig.h>
59 #include <BiosGuardConfig.h>
60 #include <ConfigBlock/VoltageRegulator/CpuPowerMgmtVrConfig.h>
61 #include <OverclockingConfig.h>
62 #include <FiaConfig.h>
63 #include <Defines/HostBridgeDefines.h>
64
65 #ifndef DISABLED
66 #define DISABLED 0
67 #endif
68 #ifndef ENABLED
69 #define ENABLED 1
70 #endif
71
72 extern EFI_GUID gSiPreMemPolicyPpiGuid;
73 extern EFI_GUID gSiPolicyPpiGuid;
74
75
76 #include <GraphicsConfig.h>
77 extern EFI_GUID gGraphicsPeiPreMemConfigGuid;
78 extern EFI_GUID gGraphicsPeiConfigGuid;
79
80 #include <VtdConfig.h>
81 extern EFI_GUID gVtdConfigGuid;
82
83 #include <GnaConfig.h>
84 extern EFI_GUID gGnaConfigGuid;
85
86
87 #include <HybridGraphicsConfig.h>
88 extern EFI_GUID gHybridGraphicsConfigGuid;
89
90 #include <MemoryConfig.h>
91 extern EFI_GUID gMemoryConfigGuid;
92 extern EFI_GUID gMemoryConfigNoCrcGuid;
93
94 #include <ConfigBlock/SaMiscPeiPreMemConfig.h>
95 extern EFI_GUID gSaMiscPeiPreMemConfigGuid;
96
97 #include <TraceHubConfig.h>
98
99 #include <HostBridgeConfig.h>
100 extern EFI_GUID gHostBridgePeiPreMemConfigGuid;
101 extern EFI_GUID gHostBridgePeiConfigGuid;
102
103 #include <VpuConfig.h>
104 extern EFI_GUID gVpuPeiConfigGuid;
105
106 #include <PeiDmiConfig.h>
107 extern EFI_GUID gPeiDmiConfigGuid;
108
109 #include <DmiConfig.h>
110
111 #include <GpioV2PeiConfig.h>
112 extern EFI_GUID gGpioV2PeiConfigGuid;
113
114 typedef struct _SI_PREMEM_POLICY_STRUCT SI_PREMEM_POLICY_PPI;
115 typedef struct _SI_POLICY_STRUCT SI_POLICY_PPI;
116
117 #endif // _SI_POLICY_PPI_H_
SiPolicyStruct.h
Intel reference code configuration policies.
VtdConfig.h
VT-d policy definitions.
TraceHubConfig.h
Configurations for TraceHub.
HybridGraphicsConfig.h
Hybrid Graphics policy definitions.
GnaConfig.h
Policy definition for GNA Config Block.
_SI_PREMEM_POLICY_STRUCT
SI Policy PPI in Pre-Mem All SI config block change history will be listed here .
Definition: SiPolicyStruct.h:71
SaMiscPeiPreMemConfig.h
Policy details for miscellaneous configuration in System Agent.
_SI_POLICY_STRUCT
SI Policy PPI All SI config block change history will be listed here .
Definition: SiPolicyStruct.h:85
OverclockingConfig.h
Overclocking Config Block.
CpuPowerMgmtVrConfig.h
CPU Power Management VR Config Block.
MePeiConfig.h
ME config block for PEI phase.
AmtConfig.h
AMT Config Block for PEI/DXE phase.
HostBridgeConfig.h
Configurations for HostBridge.
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SiPolicyStruct.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Macros
SiPolicyStruct.h File Reference

Intel reference code configuration policies. More...

#include <ConfigBlock.h>
#include <ConfigBlock/SiPreMemConfig.h>
#include <ConfigBlock/SiConfig.h>
Include dependency graph for SiPolicyStruct.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | _SI_PREMEM_POLICY_STRUCT
SI Policy PPI in Pre-Mem
All SI config block change history will be listed here

. More...
struct | _SI_POLICY_STRUCT
SI Policy PPI
All SI config block change history will be listed here

. More...

Macros

#define | SI_POLICY_REVISION 1
Silicon Policy revision number Any change to this structure will result in an update in the revision number. More...
#define | SI_PREMEM_POLICY_REVISION 1
Silicon pre-memory Policy revision number Any change to this structure will result in an update in the revision number. More...

Detailed Description

Intel reference code configuration policies.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SiPolicyStruct.h.

Macro Definition Documentation

◆ SI_POLICY_REVISION

#define SI_POLICY_REVISION 1

Silicon Policy revision number Any change to this structure will result in an update in the revision number.

This member specifies the revision of the Silicon Policy. This field is used to indicate change to the policy structure.

Revision 1:

  • Initial version.

Definition at line 52 of file SiPolicyStruct.h.

◆ SI_PREMEM_POLICY_REVISION

#define SI_PREMEM_POLICY_REVISION 1

Silicon pre-memory Policy revision number Any change to this structure will result in an update in the revision number.

Revision 1:

  • Initial version.

Definition at line 61 of file SiPolicyStruct.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SiPolicyStruct.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
SiPolicyStruct.h
Go to the documentation of this file.
1 /** @file
2 Intel reference code configuration policies.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SI_POLICY_STRUCT_H_
36 #define _SI_POLICY_STRUCT_H_
37
38 #include <ConfigBlock.h>
39 #include <ConfigBlock/SiPreMemConfig.h>
40 #include <ConfigBlock/SiConfig.h>
41
42 /**
43 Silicon Policy revision number
44 Any change to this structure will result in an update in the revision number
45
46 This member specifies the revision of the Silicon Policy. This field is used to indicate change
47 to the policy structure.
48
49 <b>Revision 1</b>:
50 - Initial version.
51 **/
52 #define SI_POLICY_REVISION 1
53
54 /**
55 Silicon pre-memory Policy revision number
56 Any change to this structure will result in an update in the revision number
57
58 <b>Revision 1</b>:
59 - Initial version.
60 **/
61 #define SI_PREMEM_POLICY_REVISION 1
62
63
64 /**
65 SI Policy PPI in Pre-Mem\n
66 All SI config block change history will be listed here\n\n
67
68 - <b>Revision 1</b>:
69 - Initial version.\n
70 **/
71 struct _SI_PREMEM_POLICY_STRUCT {
72 CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Config Block Table Header
73 /*
74 Individual Config Block Structures are added here in memory as part of AddConfigBlock()
75 */
76 };
77
78 /**
79 SI Policy PPI\n
80 All SI config block change history will be listed here\n\n
81
82 - <b>Revision 1</b>:
83 - Initial version.\n
84 **/
85 struct _SI_POLICY_STRUCT {
86 CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Config Block Table Header
87 /*
88 Individual Config Block Structures are added here in memory as part of AddConfigBlock()
89 */
90 };
91
92 #endif
_SI_PREMEM_POLICY_STRUCT::TableHeader
CONFIG_BLOCK_TABLE_HEADER TableHeader
Config Block Table Header.
Definition: SiPolicyStruct.h:72
ConfigBlock.h
Header file for Config Block Lib implementation.
SiPreMemConfig.h
Si Config Block PreMem.
_SI_PREMEM_POLICY_STRUCT
SI Policy PPI in Pre-Mem All SI config block change history will be listed here .
Definition: SiPolicyStruct.h:71
_SI_POLICY_STRUCT
SI Policy PPI All SI config block change history will be listed here .
Definition: SiPolicyStruct.h:85
SiConfig.h
Si Config Block.
_CONFIG_BLOCK_TABLE_STRUCT
Config Block Table Header.
Definition: ConfigBlock.h:50
_SI_POLICY_STRUCT::TableHeader
CONFIG_BLOCK_TABLE_HEADER TableHeader
Config Block Table Header.
Definition: SiPolicyStruct.h:86
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SiPreMemConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
Classes
SiPreMemConfig.h File Reference

Si Config Block PreMem. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct SI_PREMEM_CONFIG
The Silicon PreMem Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware. More...

Detailed Description

Si Config Block PreMem.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SiPreMemConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SiPreMemConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
SiPreMemConfig.h
Go to the documentation of this file.
1 /** @file
2 Si Config Block PreMem
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SI_PREMEM_CONFIG_H_
36 #define _SI_PREMEM_CONFIG_H_
37
38 #define SI_PREMEM_CONFIG_REVISION 1
39
40 extern EFI_GUID gSiPreMemConfigGuid;
41
42 typedef enum {
43 DisableDebug = 0x00,
44 EnabledTraceActive = 0x02,
45 EnabledTraceReady = 0x04,
46 EnabledTracePowerOff = 0x06,
47 Manual = 0x07
48 } PLATFORM_DEBUG_OPTION;
49
50 #pragma pack (push,1)
51 /**
52 The Silicon PreMem Policy allows the platform code to publish a set of configuration
53 information that the RC drivers will use to configure the silicon hardware.
54
55 <b>Revision 1</b>:
56 - Initial version.
57 **/
58 typedef struct {
59 CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
60 /**
61 Platform Debug Option
62 As a main switch to enable platform debug capability and relevant settings.
63 Manual: Do not use Platform Debug Option to override other debug-relevant policies, but the user must set each debug option manually, aimed at advanced users.
64
65 PlatformDebugOption related policies please refer to PLATFORM_DEBUG_OPTION
66 <b>0:Disabled</b>; 2:Enabled TraceHub active; 4:Enabled TraceHub ready; 6:Enabled TraceHub power off; 7:Manual
67 **/
68 UINT32 PlatformDebugOption : 4; /// offset 28 - 31
69 UINT32 RsvdBits : 28;
70 /**
71 This is used to skip override boot mode during firmware update boot mode.
72 When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,
73 skip setting boot mode to BOOT_WITH_FULL_CONFIGURATION in PEI memory init.
74 <b>0: FALSE</b>, 1: TRUE
75 **/
76 UINT8 SkipOverrideBootModeWhenFwUpdate; /// offset 32
77 UINT8 RsvdBytes[3]; /// offset 33 - 35
78 } SI_PREMEM_CONFIG;
79
80 #pragma pack (pop)
81 #endif // _SI_PREMEM_CONFIG_H_
SI_PREMEM_CONFIG::PlatformDebugOption
UINT32 PlatformDebugOption
Platform Debug Option As a main switch to enable platform debug capability and relevant settings.
Definition: SiPreMemConfig.h:68
SI_PREMEM_CONFIG::RsvdBits
UINT32 RsvdBits
offset 28 - 31
Definition: SiPreMemConfig.h:69
SI_PREMEM_CONFIG
The Silicon PreMem Policy allows the platform code to publish a set of configuration information that...
Definition: SiPreMemConfig.h:58
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
SI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0 - 27 Config Block Header.
Definition: SiPreMemConfig.h:59
SI_PREMEM_CONFIG::SkipOverrideBootModeWhenFwUpdate
UINT8 SkipOverrideBootModeWhenFwUpdate
This is used to skip override boot mode during firmware update boot mode.
Definition: SiPreMemConfig.h:76
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SmbusConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Smbus
Classes
SmbusConfig.h File Reference

Smbus policy. More...

Go to the source code of this file.

Classes

struct PCH_SMBUS_PREMEM_CONFIG
The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform. More...

Detailed Description

Smbus policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SmbusConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SmbusConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Smbus
SmbusConfig.h
Go to the documentation of this file.
1 /** @file
2 Smbus policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SMBUS_CONFIG_H_
36 #define _SMBUS_CONFIG_H_
37
38 #define PCH_SMBUS_PREMEM_CONFIG_REVISION 1
39 extern EFI_GUID gSmbusPreMemConfigGuid;
40
41 #pragma pack (push,1)
42
43 #define PCH_MAX_SMBUS_RESERVED_ADDRESS 128
44
45 ///
46 /// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform.
47 ///
48 typedef struct {
49 /**
50 Revision 1: Init version
51 **/
52 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
53 /**
54 This member describes whether or not the SMBus controller of PCH should be enabled.
55 0: Disable; <b>1: Enable</b>.
56 **/
57 UINT32 Enable : 1;
58 UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, <b>0: Disable</b>; 1: Enable.
59 UINT32 DynamicPowerGating : 1; ///< <b>(Test)</b> <b>Disable</b> or Enable Smbus dynamic power gating.
60 ///
61 /// <b>(Test)</b> SPD Write Disable, 0: leave SPD Write Disable bit; <b>1: set SPD Write Disable bit.</b>
62 /// For security recommendations, SPD write disable bit must be set.
63 ///
64 UINT32 SpdWriteDisable : 1;
65 UINT32 SmbAlertEnable : 1; ///< Enable SMBus Alert pin (SMBALERT#). 0: <b>Disabled<b>, 1: Enabled.
66 UINT32 RsvdBits0 : 27; ///< Reserved bits
67 UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space). Default is <b>0xEFA0</b>.
68 UINT8 Rsvd0; ///< Reserved bytes
69 UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the RsvdSmbusAddressTable.
70 /**
71 Array of addresses reserved for non-ARP-capable SMBus devices.
72 **/
73 UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS];
74 } PCH_SMBUS_PREMEM_CONFIG;
75
76 #pragma pack (pop)
77
78 #endif // _SMBUS_CONFIG_H_
PCH_SMBUS_PREMEM_CONFIG::SmbusIoBase
UINT16 SmbusIoBase
SMBUS Base Address (IO space). Default is 0xEFA0.
Definition: SmbusConfig.h:67
PCH_SMBUS_PREMEM_CONFIG
The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform.
Definition: SmbusConfig.h:48
PCH_SMBUS_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Revision 1: Init version.
Definition: SmbusConfig.h:52
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_SMBUS_PREMEM_CONFIG::SpdWriteDisable
UINT32 SpdWriteDisable
(Test) SPD Write Disable, 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit.
Definition: SmbusConfig.h:64
PCH_SMBUS_PREMEM_CONFIG::Rsvd0
UINT8 Rsvd0
Reserved bytes.
Definition: SmbusConfig.h:68
PCH_SMBUS_PREMEM_CONFIG::DynamicPowerGating
UINT32 DynamicPowerGating
(Test) Disable or Enable Smbus dynamic power gating.
Definition: SmbusConfig.h:59
PCH_SMBUS_PREMEM_CONFIG::SmbAlertEnable
UINT32 SmbAlertEnable
Enable SMBus Alert pin (SMBALERT#). 0: Disabled, 1: Enabled.
Definition: SmbusConfig.h:65
PCH_SMBUS_PREMEM_CONFIG::NumRsvdSmbusAddresses
UINT8 NumRsvdSmbusAddresses
The number of elements in the RsvdSmbusAddressTable.
Definition: SmbusConfig.h:69
PCH_SMBUS_PREMEM_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: SmbusConfig.h:66
PCH_SMBUS_PREMEM_CONFIG::Enable
UINT32 Enable
This member describes whether or not the SMBus controller of PCH should be enabled.
Definition: SmbusConfig.h:57
PCH_SMBUS_PREMEM_CONFIG::ArpEnable
UINT32 ArpEnable
Enable SMBus ARP support, 0: Disable; 1: Enable.
Definition: SmbusConfig.h:58
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TcssPeiConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tcss
Classes | Macros
TcssPeiConfig.h File Reference

TCSS PEI policy. More...

#include <ConfigBlock.h>
#include <UsbConfig.h>
#include <TcssInfo.h>
Include dependency graph for TcssPeiConfig.h:

Go to the source code of this file.

Classes

struct | IOM_AUX_ORI_PAD_CONFIG
The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin. More...
struct | IOM_INTERFACE_CONFIG
The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC. More...
struct | PMC_INTERFACE_CONFIG
The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC. More...
struct | SA_XDCI_IRQ_INT_CONFIG
The SA XDCI INT Pin and IRQ number. More...
struct | TCSS_PCIE_PORT_POLICY
The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS. More...
struct | TCSS_PCIE_PEI_POLICY
TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS. More...
struct | TCSS_IOM_ORI_OVERRIDE
The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS. More...
struct | TCSS_IOM_PEI_CONFIG
The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS. More...
struct | TCSS_MISC_PEI_CONFIG
The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS. More...
struct | TCSS_PEI_CONFIG
The TCSS_PEI_CONFIG block describes TCSS settings for SA. More...

Macros

#define TCSS_PEI_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Detailed Description

TCSS PEI policy.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TcssPeiConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TcssPeiConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tcss
TcssPeiConfig.h
Go to the documentation of this file.
1 /** @file
2 TCSS PEI policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _TCSS_PEI_CONFIG_H_
36 #define _TCSS_PEI_CONFIG_H_
37
38 #include <ConfigBlock.h>
39 #include <UsbConfig.h>
40 #include <TcssInfo.h>
41
42 /**
43 Making any structure change after API Lock
44 will need to maintain backward compatibility, bump up
45 structure revision and update below history table\n
46 <b>Revision 1</b>: - Initial version.
47 **/
48 #define TCSS_PEI_CONFIG_REVISION 1
49 extern EFI_GUID gTcssPeiConfigGuid;
50
51 #pragma pack (push,1)
52
53
54 #define MAX_IOM_AUX_BIAS_COUNT 4
55
56 ///
57 /// The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin.
58 /// Those GPIO setting for DP Aux Orientation Bias Control when the TypeC port didn't have re-timer.
59 /// IOM needs know Pull-Up and Pull-Down pin for Bias control
60 ///
61 typedef struct {
62 UINT32 GpioAuxBiasCtrlPuP; ///< GPIO Aux Bias Ctrl Pull Up Pin number that is for IOM indicate the pull up pin from TypeC port.
63 UINT32 GpioAuxBiasCtrlPdN; ///< GPIO Aux Bais Ctrl Pull Down Pin number that is for IOM indicate the pull down pin from TypeC port.
64 UINT32 GpioIsoCtrlPin; ///< GPIO ISO control pin GPIO number that is IOM indicate the AUX active from SOC.
65 } IOM_AUX_ORI_PAD_CONFIG;
66
67 ///
68 /// The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC.
69 ///
70
71 typedef struct {
72 UINT32 VccSt; ///< IOM VCCST request. (Not equal to actual VCCST value)
73 UINT32 UsbOverride; ///< IOM to override USB connection.
74 UINT32 D3ColdEnable; ///< Enable/disable D3 Cold support in TCSS
75 UINT32 D3HotEnable; ///< Enable/disable D3 Hot support in TCSS
76 } IOM_INTERFACE_CONFIG;
77
78 ///
79 /// The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC
80 ///
81 typedef struct {
82 UINT8 PmcPdEnable; ///< PMC PD Solution Enable
83 UINT8 Rsvd[3];
84 } PMC_INTERFACE_CONFIG;
85
86 ///
87 /// The SA XDCI INT Pin and IRQ number
88 ///
89 typedef struct {
90 UINT8 IntPing; ///< Int Pin Number
91 UINT8 Irq; ///< Irq Number
92 UINT16 Rsvd;
93 } SA_XDCI_IRQ_INT_CONFIG;
94
95 //
96 // TCSS Port Convert to TypeA.
97 // The Data is avtive when Enable field is '1'.
98 //
99 typedef union {
100 struct {
101 UINT8 MappingPchXhciUsbA:4; ///< PCH xhci port number for Type C Port x mapping
102 UINT8 Rsvd:2; ///< Reserved bytes for future use
103 UINT8 Orientational:1; ///< Enable / Disable Orientation bit. <b>0: Disable</b>; 1: Enable.
104 UINT8 Enable : 1; ///< Enable / Disable Type C Port X Convert to TypeA.
105 UINT8 Rsvd2[3];
106 } Field;
107 UINT8 Data8;
108 } TCSS_TYPEC_CONV_TYPEA;
109
110 ///
111 /// The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS.
112 ///
113 typedef struct {
114 UINT8 AcsEnabled; ///< Indicate whether the ACS is enabled. 0: Disable; <b>1: Enable</b>.
115 UINT8 Rsvd[2];
116 UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. <b>0: Disable</b>; 1: Enable.
117 UINT8 PtmEnabled; ///< Enables PTM capability
118
119 UINT8 Aspm; ///< The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is <b>
120 UINT8 SlotNumber; ///< Indicates the slot number for the root port. Default is the value as root port index.
121 UINT8 SlotPowerLimitScale; ///< <b>(Test)</b> Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is <b>zero</b>.
122 UINT16 SlotPowerLimitValue; ///< <b>(Test)</b> Specifies upper limit on power supplies by slot. Leave as 0 to set to default. Default is <b>zero</b>.
123
124 UINT8 AdvancedErrorReporting; ///< Indicate whether the Advanced Error Reporting is enabled. <b>0: Disable</b>; 1: Enable.
125 UINT8 UnsupportedRequestReport; ///< Indicate whether the Unsupported Request Report is enabled. <b>0: Disable</b>; 1: Enable.
126 UINT8 FatalErrorReport; ///< Indicate whether the Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
127 UINT8 NoFatalErrorReport; ///< Indicate whether the No Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
128 UINT8 CorrectableErrorReport; ///< Indicate whether the Correctable Error Report is enabled. <b>0: Disable</b>; 1: Enable.
129 UINT8 SystemErrorOnFatalError; ///< Indicate whether the System Error on Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
130 UINT8 SystemErrorOnNonFatalError; ///< Indicate whether the System Error on Non Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
131 UINT8 SystemErrorOnCorrectableError; ///< Indicate whether the System Error on Correctable Error is enabled. <b>0: Disable</b>; 1: Enable.
132
133 UINT16 LtrMaxSnoopLatency; ///< Latency Tolerance Reporting, Max Snoop Latency.
134 UINT16 LtrMaxNoSnoopLatency; ///< Latency Tolerance Reporting, Max Non-Snoop Latency.
135 UINT8 SnoopLatencyOverrideMode; ///< Latency Tolerance Reporting, Snoop Latency Override Mode.
136 UINT8 SnoopLatencyOverrideMultiplier; ///< Latency Tolerance Reporting, Snoop Latency Override Multiplier.
137 UINT16 SnoopLatencyOverrideValue; ///< Latency Tolerance Reporting, Snoop Latency Override Value.
138 UINT8 NonSnoopLatencyOverrideMode; ///< Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
139 UINT8 NonSnoopLatencyOverrideMultiplier; ///< Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
140 UINT16 NonSnoopLatencyOverrideValue; ///< Latency Tolerance Reporting, Non-Snoop Latency Override Value.
141 UINT8 ForceLtrOverride; ///< <b>0: Disable</b>; 1: Enable.
142 UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
143 } TCSS_PCIE_PORT_POLICY;
144
145 ///
146 /// TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS.
147 ///
148 typedef struct {
149 TCSS_PCIE_PORT_POLICY PciePortPolicy[MAX_ITBT_PCIE_PORT];
150 UINT8 Reserved[4]; ///< Reserved bytes for future use.
151 } TCSS_PCIE_PEI_POLICY;
152
153 ///
154 /// The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS.
155 ///
156 typedef struct {
157 UINT16 AuxOri; ///< Bits defining value for IOM Aux Orientation Register
158 UINT16 HslOri; ///< Bits defining value for IOM HSL Orientation Register
159 } TCSS_IOM_ORI_OVERRIDE;
160
161 ///
162 /// The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS.
163 ///
164 typedef struct {
165 IOM_AUX_ORI_PAD_CONFIG IomAuxPortPad[MAX_IOM_AUX_BIAS_COUNT]; ///< The IOM_AUX_ORI_BIAS_CTRL port config setting.
166 TCSS_IOM_ORI_OVERRIDE IomOverrides;
167 IOM_INTERFACE_CONFIG IomInterface; ///< Config settings are BIOS <-> IOM interface.
168 PMC_INTERFACE_CONFIG PmcInterface; ///< Config settings for BIOS <-> PMC interface
169 UINT8 TcStateLimit; ///< Tcss C-State deep stage
170 UINT8 TcNotifyIgd; ///< Wake iGfx from D3 on HPD_ASSERT or HPD_IRQ assocaited with the DP_ALT and DP tunneling connection.
171 UINT8 Reserved[2]; ///< Reserved bytes for future use
172 } TCSS_IOM_PEI_CONFIG;
173
174 ///
175 /// The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS.
176 ///
177 typedef struct {
178 SA_XDCI_IRQ_INT_CONFIG SaXdci; ///< System Agent Xdci Int Pin and Irq setting
179 TCSS_TYPEC_CONV_TYPEA TcssConvTypeA[MAX_TCSS_USB3_PORTS]; ///< TCSS Port Convert to TypeA
180 UINT8 Reserved[8]; ///< Reserved bytes for future use
181 } TCSS_MISC_PEI_CONFIG;
182
183 ///
184 /// The TCSS_PEI_CONFIG block describes TCSS settings for SA.
185 ///
186 typedef struct {
187 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
188 TCSS_PCIE_PEI_POLICY PciePolicy; ///< The PCIe Config
189 USB_CONFIG UsbConfig; ///< USB config is shared between PCH and SA.
190 TCSS_IOM_PEI_CONFIG IomConfig; ///< The Iom Config
191 TCSS_MISC_PEI_CONFIG MiscConfig; ///< The MISC Config
192 } TCSS_PEI_CONFIG;
193
194 #pragma pack (pop)
195
196 #endif /* _TCSS_PEI_CONFIG_H_ */
IOM_AUX_ORI_PAD_CONFIG
The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin.
Definition: TcssPeiConfig.h:61
TCSS_IOM_PEI_CONFIG::IomInterface
IOM_INTERFACE_CONFIG IomInterface
Config settings are BIOS <-> IOM interface.
Definition: TcssPeiConfig.h:167
ConfigBlock.h
Header file for Config Block Lib implementation.
IOM_AUX_ORI_PAD_CONFIG::GpioAuxBiasCtrlPdN
UINT32 GpioAuxBiasCtrlPdN
GPIO Aux Bais Ctrl Pull Down Pin number that is for IOM indicate the pull down pin from TypeC port.
Definition: TcssPeiConfig.h:63
TCSS_PCIE_PORT_POLICY::NonSnoopLatencyOverrideValue
UINT16 NonSnoopLatencyOverrideValue
Latency Tolerance Reporting, Non-Snoop Latency Override Value.
Definition: TcssPeiConfig.h:140
TCSS_IOM_PEI_CONFIG::PmcInterface
PMC_INTERFACE_CONFIG PmcInterface
Config settings for BIOS <-> PMC interface.
Definition: TcssPeiConfig.h:168
TCSS_PCIE_PORT_POLICY::SystemErrorOnNonFatalError
UINT8 SystemErrorOnNonFatalError
Indicate whether the System Error on Non Fatal Error is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:130
TCSS_PCIE_PORT_POLICY::SnoopLatencyOverrideMultiplier
UINT8 SnoopLatencyOverrideMultiplier
Latency Tolerance Reporting, Snoop Latency Override Multiplier.
Definition: TcssPeiConfig.h:136
IOM_INTERFACE_CONFIG::D3ColdEnable
UINT32 D3ColdEnable
Enable/disable D3 Cold support in TCSS.
Definition: TcssPeiConfig.h:74
PMC_INTERFACE_CONFIG::PmcPdEnable
UINT8 PmcPdEnable
PMC PD Solution Enable.
Definition: TcssPeiConfig.h:82
TCSS_PCIE_PORT_POLICY::SlotPowerLimitValue
UINT16 SlotPowerLimitValue
(Test) Specifies upper limit on power supplies by slot. Leave as 0 to set to default....
Definition: TcssPeiConfig.h:122
TCSS_IOM_PEI_CONFIG
The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS.
Definition: TcssPeiConfig.h:164
TCSS_PCIE_PORT_POLICY::LtrEnable
UINT8 LtrEnable
Latency Tolerance Reporting Mechanism. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:116
IOM_INTERFACE_CONFIG
The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC.
Definition: TcssPeiConfig.h:71
TCSS_PCIE_PORT_POLICY::AcsEnabled
UINT8 AcsEnabled
Indicate whether the ACS is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:114
TCSS_PCIE_PORT_POLICY::SnoopLatencyOverrideValue
UINT16 SnoopLatencyOverrideValue
Latency Tolerance Reporting, Snoop Latency Override Value.
Definition: TcssPeiConfig.h:137
TCSS_PCIE_PORT_POLICY::NoFatalErrorReport
UINT8 NoFatalErrorReport
Indicate whether the No Fatal Error Report is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:127
UsbConfig.h
Common USB policy shared between PCH and CPU Contains general features settings for xHCI and xDCI.
TCSS_PCIE_PORT_POLICY::UnsupportedRequestReport
UINT8 UnsupportedRequestReport
Indicate whether the Unsupported Request Report is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:125
TCSS_PCIE_PORT_POLICY::SystemErrorOnFatalError
UINT8 SystemErrorOnFatalError
Indicate whether the System Error on Fatal Error is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:129
PMC_INTERFACE_CONFIG
The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC.
Definition: TcssPeiConfig.h:81
TCSS_PCIE_PORT_POLICY::FatalErrorReport
UINT8 FatalErrorReport
Indicate whether the Fatal Error Report is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:126
TCSS_PEI_CONFIG::UsbConfig
USB_CONFIG UsbConfig
USB config is shared between PCH and SA.
Definition: TcssPeiConfig.h:189
TCSS_PCIE_PEI_POLICY
TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS.
Definition: TcssPeiConfig.h:148
TCSS_PCIE_PORT_POLICY::ForceLtrOverride
UINT8 ForceLtrOverride
0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:141
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
TCSS_PCIE_PORT_POLICY::SnoopLatencyOverrideMode
UINT8 SnoopLatencyOverrideMode
Latency Tolerance Reporting, Snoop Latency Override Mode.
Definition: TcssPeiConfig.h:135
TCSS_IOM_ORI_OVERRIDE::AuxOri
UINT16 AuxOri
Bits defining value for IOM Aux Orientation Register.
Definition: TcssPeiConfig.h:157
TCSS_PCIE_PORT_POLICY::SlotNumber
UINT8 SlotNumber
Indicates the slot number for the root port. Default is the value as root port index.
Definition: TcssPeiConfig.h:120
TCSS_PCIE_PORT_POLICY::SlotPowerLimitScale
UINT8 SlotPowerLimitScale
(Test) Specifies scale used for slot power limit value. Leave as 0 to set to default....
Definition: TcssPeiConfig.h:121
TCSS_PCIE_PORT_POLICY::SystemErrorOnCorrectableError
UINT8 SystemErrorOnCorrectableError
Indicate whether the System Error on Correctable Error is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:131
SA_XDCI_IRQ_INT_CONFIG
The SA XDCI INT Pin and IRQ number.
Definition: TcssPeiConfig.h:89
SA_XDCI_IRQ_INT_CONFIG::IntPing
UINT8 IntPing
Int Pin Number.
Definition: TcssPeiConfig.h:90
TCSS_PCIE_PORT_POLICY
The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS.
Definition: TcssPeiConfig.h:113
TCSS_PEI_CONFIG::PciePolicy
TCSS_PCIE_PEI_POLICY PciePolicy
The PCIe Config.
Definition: TcssPeiConfig.h:188
SA_XDCI_IRQ_INT_CONFIG::Irq
UINT8 Irq
Irq Number.
Definition: TcssPeiConfig.h:91
TCSS_PCIE_PORT_POLICY::LtrConfigLock
UINT8 LtrConfigLock
0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:142
IOM_INTERFACE_CONFIG::VccSt
UINT32 VccSt
IOM VCCST request. (Not equal to actual VCCST value)
Definition: TcssPeiConfig.h:72
TCSS_PEI_CONFIG::IomConfig
TCSS_IOM_PEI_CONFIG IomConfig
The Iom Config.
Definition: TcssPeiConfig.h:190
IOM_AUX_ORI_PAD_CONFIG::GpioAuxBiasCtrlPuP
UINT32 GpioAuxBiasCtrlPuP
GPIO Aux Bias Ctrl Pull Up Pin number that is for IOM indicate the pull up pin from TypeC port.
Definition: TcssPeiConfig.h:62
TCSS_PEI_CONFIG::MiscConfig
TCSS_MISC_PEI_CONFIG MiscConfig
The MISC Config.
Definition: TcssPeiConfig.h:191
IOM_AUX_ORI_PAD_CONFIG::GpioIsoCtrlPin
UINT32 GpioIsoCtrlPin
GPIO ISO control pin GPIO number that is IOM indicate the AUX active from SOC.
Definition: TcssPeiConfig.h:64
TCSS_PCIE_PORT_POLICY::CorrectableErrorReport
UINT8 CorrectableErrorReport
Indicate whether the Correctable Error Report is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:128
TCSS_PEI_CONFIG
The TCSS_PEI_CONFIG block describes TCSS settings for SA.
Definition: TcssPeiConfig.h:186
TCSS_PCIE_PORT_POLICY::NonSnoopLatencyOverrideMultiplier
UINT8 NonSnoopLatencyOverrideMultiplier
Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
Definition: TcssPeiConfig.h:139
TCSS_IOM_PEI_CONFIG::TcNotifyIgd
UINT8 TcNotifyIgd
Wake iGfx from D3 on HPD_ASSERT or HPD_IRQ assocaited with the DP_ALT and DP tunneling connection.
Definition: TcssPeiConfig.h:170
TCSS_PEI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: TcssPeiConfig.h:187
TCSS_PCIE_PORT_POLICY::PtmEnabled
UINT8 PtmEnabled
Enables PTM capability.
Definition: TcssPeiConfig.h:117
IOM_INTERFACE_CONFIG::UsbOverride
UINT32 UsbOverride
IOM to override USB connection.
Definition: TcssPeiConfig.h:73
TCSS_PCIE_PORT_POLICY::Aspm
UINT8 Aspm
The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
Definition: TcssPeiConfig.h:119
TCSS_PCIE_PORT_POLICY::LtrMaxNoSnoopLatency
UINT16 LtrMaxNoSnoopLatency
Latency Tolerance Reporting, Max Non-Snoop Latency.
Definition: TcssPeiConfig.h:134
TCSS_MISC_PEI_CONFIG::SaXdci
SA_XDCI_IRQ_INT_CONFIG SaXdci
System Agent Xdci Int Pin and Irq setting.
Definition: TcssPeiConfig.h:178
TCSS_IOM_ORI_OVERRIDE
The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS.
Definition: TcssPeiConfig.h:156
TCSS_MISC_PEI_CONFIG
The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS.
Definition: TcssPeiConfig.h:177
IOM_INTERFACE_CONFIG::D3HotEnable
UINT32 D3HotEnable
Enable/disable D3 Hot support in TCSS.
Definition: TcssPeiConfig.h:75
TCSS_PCIE_PORT_POLICY::NonSnoopLatencyOverrideMode
UINT8 NonSnoopLatencyOverrideMode
Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
Definition: TcssPeiConfig.h:138
TCSS_PCIE_PORT_POLICY::LtrMaxSnoopLatency
UINT16 LtrMaxSnoopLatency
Latency Tolerance Reporting, Max Snoop Latency.
Definition: TcssPeiConfig.h:133
TCSS_PCIE_PORT_POLICY::AdvancedErrorReporting
UINT8 AdvancedErrorReporting
Indicate whether the Advanced Error Reporting is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:124
TCSS_IOM_ORI_OVERRIDE::HslOri
UINT16 HslOri
Bits defining value for IOM HSL Orientation Register.
Definition: TcssPeiConfig.h:158
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
TCSS_IOM_PEI_CONFIG::TcStateLimit
UINT8 TcStateLimit
Tcss C-State deep stage.
Definition: TcssPeiConfig.h:169
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TcssPeiPreMemConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tcss
Classes
TcssPeiPreMemConfig.h File Reference

TCSS PEI PreMem policy. More...

#include <ConfigBlock.h>
Include dependency graph for TcssPeiPreMemConfig.h:

Go to the source code of this file.

Classes

union | TCSS_DEVEN_PEI_PREMEM_CONFIG
The TCSS_DEVEN_PEI_PREMEM_CONFIG block describes Device Enable settings for TCSS. More...
struct | TCSS_USBTC_PEI_PERMEM_CONFIG
The TCSS_USBTC_PEI_PERMEM_CONFIG block describes IOM settings for TCSS. More...
struct | TCSS_PEI_PREMEM_CONFIG
This configuration block describes TCSS settings. More...

Detailed Description

TCSS PEI PreMem policy.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TcssPeiPreMemConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TcssPeiPreMemConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tcss
TcssPeiPreMemConfig.h
Go to the documentation of this file.
1 /** @file
2 TCSS PEI PreMem policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _TCSS_PEI_PREMEM_CONFIG_H_
36 #define _TCSS_PEI_PREMEM_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 #define TCSS_PEI_PREMEM_CONFIG_REVISION 1
41 extern EFI_GUID gTcssPeiPreMemConfigGuid;
42
43 #pragma pack (push,1)
44
45 ///
46 /// The TCSS_DEVEN_PEI_PREMEM_CONFIG block describes Device Enable settings for TCSS.
47 ///
48 typedef union {
49 UINT32 TcssDevEn; ///< Maps to bits in TCSS_DEVEN_0_0_0_MCHBAR_IMPH
50 struct{
51 UINT32 TcssItbtPcie0En:1;
52 UINT32 TcssItbtPcie1En:1;
53 UINT32 TcssItbtPcie2En:1;
54 UINT32 TcssItbtPcie3En:1;
55 UINT32 :4;
56 UINT32 TcssXhciEn:1;
57 UINT32 TcssXdciEn:1;
58 UINT32 TcssDma0En:1;
59 UINT32 TcssDma1En:1;
60 UINT32 :20;
61 } TcssDevEnBit;
62 } TCSS_DEVEN_PEI_PREMEM_CONFIG;
63
64 ///
65 /// The TCSS_USBTC_PEI_PERMEM_CONFIG block describes IOM settings for TCSS.
66 ///
67 typedef struct {
68 UINT32 UsbTcPortEn : 4; ///< bitmap for USB Type C enabled ports
69 UINT32 Rsvd : 28; ///< Reserved bytes for future use
70 } TCSS_USBTC_PEI_PERMEM_CONFIG;
71
72 /**
73 This configuration block describes TCSS settings.\n
74 <b>Revision 1</b>:
75 - Initial version.
76 **/
77 typedef struct {
78 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
79 TCSS_DEVEN_PEI_PREMEM_CONFIG DevEnConfig;///< TCSS DEVEN
80 TCSS_USBTC_PEI_PERMEM_CONFIG UsbTcConfig;///< USB Type C Port Configuration
81 } TCSS_PEI_PREMEM_CONFIG;
82
83 #pragma pack (pop)
84
85 #endif /* _TCSS_PEI_PREMEM_CONFIG_H_ */
ConfigBlock.h
Header file for Config Block Lib implementation.
TCSS_USBTC_PEI_PERMEM_CONFIG::UsbTcPortEn
UINT32 UsbTcPortEn
bitmap for USB Type C enabled ports
Definition: TcssPeiPreMemConfig.h:68
TCSS_DEVEN_PEI_PREMEM_CONFIG::TcssDevEn
UINT32 TcssDevEn
Maps to bits in TCSS_DEVEN_0_0_0_MCHBAR_IMPH.
Definition: TcssPeiPreMemConfig.h:49
TCSS_PEI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: TcssPeiPreMemConfig.h:78
TCSS_DEVEN_PEI_PREMEM_CONFIG
The TCSS_DEVEN_PEI_PREMEM_CONFIG block describes Device Enable settings for TCSS.
Definition: TcssPeiPreMemConfig.h:48
TCSS_PEI_PREMEM_CONFIG
This configuration block describes TCSS settings.
Definition: TcssPeiPreMemConfig.h:77
TCSS_USBTC_PEI_PERMEM_CONFIG::Rsvd
UINT32 Rsvd
Reserved bytes for future use.
Definition: TcssPeiPreMemConfig.h:69
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
TCSS_PEI_PREMEM_CONFIG::DevEnConfig
TCSS_DEVEN_PEI_PREMEM_CONFIG DevEnConfig
TCSS DEVEN.
Definition: TcssPeiPreMemConfig.h:79
TCSS_PEI_PREMEM_CONFIG::UsbTcConfig
TCSS_USBTC_PEI_PERMEM_CONFIG UsbTcConfig
USB Type C Port Configuration.
Definition: TcssPeiPreMemConfig.h:80
TCSS_USBTC_PEI_PERMEM_CONFIG
The TCSS_USBTC_PEI_PERMEM_CONFIG block describes IOM settings for TCSS.
Definition: TcssPeiPreMemConfig.h:67
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TelemetryPeiConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Telemetry
Classes
TelemetryPeiConfig.h File Reference

Configurations for Telemetry. More...

#include <ConfigBlock.h>
Include dependency graph for TelemetryPeiConfig.h:

Go to the source code of this file.

Classes

struct | TELEMETRY_PEI_PREMEM_CONFIG
This configuration block describes Telemetry settings in PreMem. More...
struct | TELEMETRY_PEI_CONFIG
This configuration block describes Telemetry settings in PostMem. More...

Detailed Description

Configurations for Telemetry.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TelemetryPeiConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TelemetryPeiConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Telemetry
TelemetryPeiConfig.h
Go to the documentation of this file.
1 /** @file
2 Configurations for Telemetry
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _TELEMETRY_CONFIG_H_
36 #define _TELEMETRY_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 #pragma pack (push,1)
41
42 #define TELEMETRY_PEI_CONFIG_REVISION 1
43 #define TELEMETRY_PEI_PREMEM_CONFIG_REVISION 1
44
45 extern EFI_GUID gTelemetryPeiConfigGuid;
46 extern EFI_GUID gTelemetryPeiPreMemConfigGuid;
47
48 /**
49 This configuration block describes Telemetry settings in PreMem.\n
50 <b>Revision 1</b>:
51 - Initial version.
52 **/
53 typedef struct {
54 CONFIG_BLOCK_HEADER Header; /// Config Block Header
55 UINT32 CpuCrashLogDevice; /// Enable or Disable CrashLog/Telemetry Device 0- Disable, <b>1- Enable</b>
56 } TELEMETRY_PEI_PREMEM_CONFIG;
57
58 /**
59 This configuration block describes Telemetry settings in PostMem.\n
60 <b>Revision 1</b>:
61 - Initial version.
62 **/
63 typedef struct {
64 CONFIG_BLOCK_HEADER Header; /// Config Block Header
65 UINT32 CpuCrashLogEnable; /// Enable or Disable CrashLog feature 0- Disable, <b>1- Enable</b>
66 } TELEMETRY_PEI_CONFIG;
67
68 #pragma pack (pop)
69
70 #endif
ConfigBlock.h
Header file for Config Block Lib implementation.
TELEMETRY_PEI_PREMEM_CONFIG
This configuration block describes Telemetry settings in PreMem.
Definition: TelemetryPeiConfig.h:53
TELEMETRY_PEI_PREMEM_CONFIG::CpuCrashLogDevice
UINT32 CpuCrashLogDevice
Config Block Header.
Definition: TelemetryPeiConfig.h:55
TELEMETRY_PEI_CONFIG
This configuration block describes Telemetry settings in PostMem.
Definition: TelemetryPeiConfig.h:63
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
TELEMETRY_PEI_CONFIG::CpuCrashLogEnable
UINT32 CpuCrashLogEnable
Config Block Header.
Definition: TelemetryPeiConfig.h:65
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ThcConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Thc
Classes | Macros | Enumerations
ThcConfig.h File Reference

Touch Host Controller policy. More...

Go to the source code of this file.

Classes

struct | THC_HID_OVER_SPI
THC Hid Over SPI mode related settings. More...
struct | THC_RESET
THC Reset Pad related settings. More...
struct | THC_HID_OVER_I2C
THC Hid Over I2C mode related settings. More...
struct | THC_PORT
Port Configuration structure required for each Port that THC might use. More...
struct | THC_CONFIG
THC_CONFIG block provides the configurations forTouch Host Controllers. More...

Macros

#define THC_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Enumerations

enum | THC_PORT_ASSIGNMENT
Available Port Assignments. More...
enum | THC_MODE
Available modes. More...

Detailed Description

Touch Host Controller policy.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2022 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file ThcConfig.h.

Enumeration Type Documentation

◆ THC_MODE

enum THC_MODE

Available modes.

Enumerator
Thc | Intel THC protocol.
HidOverSpi | Hid Over SPI protocol.
HidOverI2c | Hid Over I2C protocol.

Definition at line 63 of file ThcConfig.h.

◆ THC_PORT_ASSIGNMENT

enum THC_PORT_ASSIGNMENT

Available Port Assignments.

Enumerator
ThcAssignmentNone | None of the avaialbe controllers assigned.
ThcAssignmentThc0 | Port assigned to THC0.
ThcAssignmentThc1 | Port assigned to THC1.

Definition at line 54 of file ThcConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ThcConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Thc
ThcConfig.h
Go to the documentation of this file.
1 /** @file
2 Touch Host Controller policy.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2022 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _THC_CONFIG_H_
37 #define _THC_CONFIG_H_
38
39 /**
40 Making any structure change after API Lock
41 will need to maintain backward compatibility, bump up
42 structure revision and update below history table\n
43 <b>Revision 1</b>: - Initial version.
44 **/
45 #define THC_CONFIG_REVISION 1
46 extern EFI_GUID gThcConfigGuid;
47
48 #pragma pack (push,1)
49
50 /**
51 Available Port Assignments
52
53 **/
54 typedef enum {
55 ThcAssignmentNone, ///< None of the avaialbe controllers assigned
56 ThcAssignmentThc0, ///< Port assigned to THC0
57 ThcAssignmentThc1 ///< Port assigned to THC1
58 } THC_PORT_ASSIGNMENT;
59
60 /**
61 Available modes
62 **/
63 typedef enum {
64 Thc, ///< Intel THC protocol
65 HidOverSpi, ///< Hid Over SPI protocol
66 HidOverI2c ///< Hid Over I2C protocol
67 } THC_MODE;
68
69
70 /**
71 THC Hid Over SPI mode related settings. Only applicable when HidOverSpi is enbled.
72 **/
73 typedef struct {
74 UINT32 Frequency; ///< Connection Speed - SPI Frequency in Hz
75 UINT32 InputReportHeaderAddress; ///< Input Report Header Address
76 UINT32 InputReportBodyAddress; ///< Input Report Body Address
77 UINT32 OutputReportAddress; ///< Output Report Address
78 UINT32 ReadOpcode; ///< Read Opcode
79 UINT32 WriteOpcode; ///< Write Opcode
80 UINT32 Flags; ///< Flags
81 UINT32 LimitPacketSize; ///< Limit Packet Size
82 } THC_HID_OVER_SPI;
83
84 /**
85 THC Reset Pad related settings.
86 **/
87 typedef struct {
88 UINT32 ResetPad; ///< Reset Pad - <b>0x0 = THC HW default</b> BIOS will pass Pad infromation to ACPI, this Pad is used in _RST function
89 UINT32 ResetPadTrigger; ///< Reset Pad Trigger
90 UINT32 ResetSequencingDelay; ///< Policy control for reset sequencing delay (_INI, _RST)
91 } THC_RESET;
92
93 /**
94 THC Hid Over I2C mode related settings. Only applicable when HidOverI2c is enbled.
95 **/
96 typedef struct {
97 UINT32 DeviceAddress; ///< Device Address
98 UINT32 ConnectionSpeed; ///< Connection Speed - Frequency [Hz]
99 /**
100 Addressing Mode
101 0x1: The connection uses 10-bit addressing.
102 0x0: The connection uses 7-bit addressing.
103 **/
104 UINT32 AddressingMode;
105 UINT32 StandardModeSerialClockLineHighPeriod; ///< Serial Clock Line High Period
106 UINT32 StandardModeSerialClockLineLowPeriod; ///< Standard Mode Serial Clock Line Low Period
107 UINT32 StandardModeSerialDataLineTransmitHoldPeriod; ///< Standard Mode Serial Data Line Transmit Hold Period
108 UINT32 StandardModeSerialDataLineReceiveHoldPeriod; ///< Standard Mode Serial Data Line Receive Hold Period
109 UINT32 FastModeSerialClockLineHighPeriod; ///< Fast Mode Serial Clock Line High Period
110 UINT32 FastModeSerialClockLineLowPeriod; ///< Fast Mode Serial Clock Line Low Period
111 UINT32 FastModeSerialDataLineTransmitHoldPeriod; ///< Fast Mode Serial Data Line Transmit Hold Period
112 UINT32 FastModeSerialDataLineReceiveHoldPeriod; ///< Fast Mode Serial Data Line Receive Hold Period
113 UINT32 MaxSuppressedSpikesSMFMFMP; ///< Maximum Length Of Suppressed Spikes In Std Mode Fast Mode And Fast Mode Plus
114 UINT32 FastModePlusSerialClockLineHighPeriod; ///< Fast Mode Plus Serial Clock Line High Period
115 UINT32 FastModePlusSerialClockLineLowPeriod; ///< Fast Mode Plus Serial Clock Line Low Period
116 UINT32 FastModePlusSerialDataLineTransmitHoldPeriod; ///< Fast Mode Plus Serial Data Line Transmit Hold Period
117 UINT32 FastModePlusSerialDataLineReceiveHoldPeriod; ///< Fast Mode Plus Serial Data Line Receive Hold Period
118 UINT32 HighSpeedModePlusSerialClockLineHighPeriod; ///< High Speed Mode Plus Serial Clock Line High Period
119 UINT32 HighSpeedModePlusSerialClockLineLowPeriod; ///< High Speed Mode Plus Serial Clock Line Low Period
120 UINT32 HighSpeedModePlusSerialDataLineTransmitHoldPeriod; ///< High Speed Mode Plus Serial Data Line Transmit Hold Period
121 UINT32 HighSpeedModePlusSerialDataLineReceiveHoldPeriod; ///< High Speed Mode Plus Serial Data Line Receive Hold Period
122 UINT32 MaximumLengthOfSuppressedSpikesInHighSpeedMode; ///< Maximum Length Of Suppressed Spikes In High Speed Mode
123 } THC_HID_OVER_I2C;
124
125 /**
126 Port Configuration structure required for each Port that THC might use.
127 **/
128 typedef struct {
129 UINT32 Assignment; ///< Sets THCx assignment see THC_PORT_ASSIGNMENT
130 UINT32 InterruptPinMuxing; ///< Each GPIO PORTx/SPIx INTB Pin has different muxing options refer to GPIO_*_MUXING_THC_SPIx_*
131 UINT8 WakeOnTouch; ///< 1 = Enable <b>0 = Disable</b>. Based on this setting vGPIO for given THC will be in native mode, and additional _CRS for wake will be exposed in ACPI
132 UINT8 Mode; ///< 1 = Hid over SPI <b>0 = THC</b>. Switch between Intel THC protcol and Industry standard HID Over SPI protocol.
133 /**
134 Timestamp timer behavior in D0i2
135 <b>1 = Timer resets to 0 when entering D0i2</b>
136 0 = Timer is paused instead of reset to 0 when entering D0i2
137 **/
138 UINT8 TimestampTimerMode;
139 UINT8 Reserved[1]; ///< Reserved
140 THC_HID_OVER_SPI HidOverSpi; ///< Hid Over Spi mode settings
141 UINT32 ActiveLtr; ///< <b>0xFFFFFFFF = Driver Default </b> Active Ltr
142 UINT32 IdleLtr; ///< <b>0xFFFFFFFF = Driver Default </b> Idle Ltr
143 UINT32 PerformanceLimitation; ///< Performance Limitation
144 /**
145 Period of the emulated display frame sync [ms]
146 The minimum period is 2ms, maximum period is 100ms
147 Default: <b>10</b>ms
148 **/
149 UINT32 DisplayFrameSyncPeriod;
150 THC_RESET Reset; ///< Reset Line settings
151 THC_HID_OVER_I2C HidOverI2c; ///< Hid Over I2c mode settings
152 } THC_PORT;
153
154 /**
155 THC_CONFIG block provides the configurations forTouch Host Controllers
156
157 Assignment field in each THC port controlls the THC behavior.
158
159 Available scenarios:
160 1: Single Port 0 used by THC0
161 - THC0 Enabled
162 - Port0 assigned to THC0
163 - Port1 unassigned
164 - THC1 will be automatically Disabled.
165 2: Both ports used by THC0
166 - THC0 Enabled
167 - Port0 assigned to THC0
168 - Port1 assigned to THC0
169 - THC1 will be automatically Disabled.
170 3: Port 0 used by THC0 and Port 1 used by THC1
171 - THC0 Enabled
172 - Port0 assigned to THC0
173 - THC1 Enabled
174 - Port1 assigned to THC1.
175 <b>4: Both Ports unassigned.</b>
176 Both THC Controllers will be disabled in that case.
177
178 @note
179 Invalid scenario that will cause ASSERT.
180 1. Same port Number assigned to THC0 or THC1.
181 2. Two Ports assigned to THC1.
182
183 <b>Revision 1:</b>
184 - Inital version.
185 <b>Revision 2:</b>
186 - Add HidOverSpi THC_MODE
187 <b>Revision 3:</b>
188 - Expand HidOverSpi support
189 <b>Revision 4:</b>
190 - Add ResetSequencingDelay in THC_HID_OVER_SPI
191 <b>Revision 5:</b>
192 - Moved out reset data from THC_HID_OVER_SPI
193 - Add THC_HID_OVER_I2C
194
195 **/
196 typedef struct {
197 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
198 THC_PORT ThcPort[2]; ///< Port Configuration
199 } THC_CONFIG;
200
201 #pragma pack (pop)
202
203 #endif // _THC_CONFIG_H_
THC_HID_OVER_I2C::HighSpeedModePlusSerialDataLineReceiveHoldPeriod
UINT32 HighSpeedModePlusSerialDataLineReceiveHoldPeriod
High Speed Mode Plus Serial Data Line Receive Hold Period.
Definition: ThcConfig.h:121
THC_HID_OVER_SPI::Frequency
UINT32 Frequency
Connection Speed - SPI Frequency in Hz.
Definition: ThcConfig.h:74
THC_HID_OVER_I2C::MaximumLengthOfSuppressedSpikesInHighSpeedMode
UINT32 MaximumLengthOfSuppressedSpikesInHighSpeedMode
Maximum Length Of Suppressed Spikes In High Speed Mode.
Definition: ThcConfig.h:122
THC_HID_OVER_SPI::ReadOpcode
UINT32 ReadOpcode
Read Opcode.
Definition: ThcConfig.h:78
THC_MODE
THC_MODE
Available modes.
Definition: ThcConfig.h:63
THC_HID_OVER_SPI::Flags
UINT32 Flags
Flags.
Definition: ThcConfig.h:80
ThcAssignmentNone
@ ThcAssignmentNone
None of the avaialbe controllers assigned.
Definition: ThcConfig.h:55
HidOverSpi
@ HidOverSpi
Hid Over SPI protocol.
Definition: ThcConfig.h:65
THC_HID_OVER_I2C
THC Hid Over I2C mode related settings.
Definition: ThcConfig.h:96
THC_RESET::ResetPadTrigger
UINT32 ResetPadTrigger
Reset Pad Trigger.
Definition: ThcConfig.h:89
ThcAssignmentThc1
@ ThcAssignmentThc1
Port assigned to THC1.
Definition: ThcConfig.h:57
THC_PORT::InterruptPinMuxing
UINT32 InterruptPinMuxing
Each GPIO PORTx/SPIx INTB Pin has different muxing options refer to GPIO_*_MUXING_THC_SPIx_*.
Definition: ThcConfig.h:130
THC_PORT
Port Configuration structure required for each Port that THC might use.
Definition: ThcConfig.h:128
THC_RESET
THC Reset Pad related settings.
Definition: ThcConfig.h:87
THC_RESET::ResetPad
UINT32 ResetPad
Reset Pad - 0x0 = THC HW default BIOS will pass Pad infromation to ACPI, this Pad is used in _RST fun...
Definition: ThcConfig.h:88
THC_HID_OVER_I2C::AddressingMode
UINT32 AddressingMode
Addressing Mode 0x1: The connection uses 10-bit addressing.
Definition: ThcConfig.h:104
THC_HID_OVER_I2C::MaxSuppressedSpikesSMFMFMP
UINT32 MaxSuppressedSpikesSMFMFMP
Maximum Length Of Suppressed Spikes In Std Mode Fast Mode And Fast Mode Plus.
Definition: ThcConfig.h:113
THC_PORT::Assignment
UINT32 Assignment
Sets THCx assignment see THC_PORT_ASSIGNMENT.
Definition: ThcConfig.h:129
THC_HID_OVER_I2C::FastModeSerialDataLineReceiveHoldPeriod
UINT32 FastModeSerialDataLineReceiveHoldPeriod
Fast Mode Serial Data Line Receive Hold Period.
Definition: ThcConfig.h:112
THC_HID_OVER_I2C::DeviceAddress
UINT32 DeviceAddress
Device Address.
Definition: ThcConfig.h:97
Thc
@ Thc
Intel THC protocol.
Definition: ThcConfig.h:64
THC_HID_OVER_I2C::StandardModeSerialClockLineLowPeriod
UINT32 StandardModeSerialClockLineLowPeriod
Standard Mode Serial Clock Line Low Period.
Definition: ThcConfig.h:106
THC_PORT::IdleLtr
UINT32 IdleLtr
0xFFFFFFFF = Driver Default Idle Ltr
Definition: ThcConfig.h:142
THC_HID_OVER_I2C::StandardModeSerialClockLineHighPeriod
UINT32 StandardModeSerialClockLineHighPeriod
Serial Clock Line High Period.
Definition: ThcConfig.h:105
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
THC_HID_OVER_I2C::HighSpeedModePlusSerialClockLineHighPeriod
UINT32 HighSpeedModePlusSerialClockLineHighPeriod
High Speed Mode Plus Serial Clock Line High Period.
Definition: ThcConfig.h:118
THC_HID_OVER_I2C::FastModePlusSerialDataLineTransmitHoldPeriod
UINT32 FastModePlusSerialDataLineTransmitHoldPeriod
Fast Mode Plus Serial Data Line Transmit Hold Period.
Definition: ThcConfig.h:116
THC_PORT::HidOverSpi
THC_HID_OVER_SPI HidOverSpi
Hid Over Spi mode settings.
Definition: ThcConfig.h:140
THC_HID_OVER_SPI
THC Hid Over SPI mode related settings.
Definition: ThcConfig.h:73
THC_HID_OVER_SPI::LimitPacketSize
UINT32 LimitPacketSize
Limit Packet Size.
Definition: ThcConfig.h:81
THC_HID_OVER_I2C::FastModeSerialClockLineHighPeriod
UINT32 FastModeSerialClockLineHighPeriod
Fast Mode Serial Clock Line High Period.
Definition: ThcConfig.h:109
THC_PORT::WakeOnTouch
UINT8 WakeOnTouch
1 = Enable 0 = Disable. Based on this setting vGPIO for given THC will be in native mode,...
Definition: ThcConfig.h:131
THC_HID_OVER_SPI::InputReportBodyAddress
UINT32 InputReportBodyAddress
Input Report Body Address.
Definition: ThcConfig.h:76
THC_PORT::PerformanceLimitation
UINT32 PerformanceLimitation
Performance Limitation.
Definition: ThcConfig.h:143
THC_PORT::Reset
THC_RESET Reset
Reset Line settings.
Definition: ThcConfig.h:150
THC_HID_OVER_I2C::StandardModeSerialDataLineReceiveHoldPeriod
UINT32 StandardModeSerialDataLineReceiveHoldPeriod
Standard Mode Serial Data Line Receive Hold Period.
Definition: ThcConfig.h:108
THC_PORT::TimestampTimerMode
UINT8 TimestampTimerMode
Timestamp timer behavior in D0i2 1 = Timer resets to 0 when entering D0i2 0 = Timer is paused instead...
Definition: ThcConfig.h:138
THC_HID_OVER_I2C::FastModePlusSerialDataLineReceiveHoldPeriod
UINT32 FastModePlusSerialDataLineReceiveHoldPeriod
Fast Mode Plus Serial Data Line Receive Hold Period.
Definition: ThcConfig.h:117
THC_PORT::HidOverI2c
THC_HID_OVER_I2C HidOverI2c
Hid Over I2c mode settings.
Definition: ThcConfig.h:151
HidOverI2c
@ HidOverI2c
Hid Over I2C protocol.
Definition: ThcConfig.h:66
THC_PORT::DisplayFrameSyncPeriod
UINT32 DisplayFrameSyncPeriod
Period of the emulated display frame sync [ms] The minimum period is 2ms, maximum period is 100ms Def...
Definition: ThcConfig.h:149
THC_HID_OVER_SPI::OutputReportAddress
UINT32 OutputReportAddress
Output Report Address.
Definition: ThcConfig.h:77
THC_RESET::ResetSequencingDelay
UINT32 ResetSequencingDelay
Policy control for reset sequencing delay (_INI, _RST)
Definition: ThcConfig.h:90
THC_HID_OVER_SPI::InputReportHeaderAddress
UINT32 InputReportHeaderAddress
Input Report Header Address.
Definition: ThcConfig.h:75
THC_PORT::ActiveLtr
UINT32 ActiveLtr
0xFFFFFFFF = Driver Default Active Ltr
Definition: ThcConfig.h:141
THC_PORT_ASSIGNMENT
THC_PORT_ASSIGNMENT
Available Port Assignments.
Definition: ThcConfig.h:54
THC_HID_OVER_I2C::StandardModeSerialDataLineTransmitHoldPeriod
UINT32 StandardModeSerialDataLineTransmitHoldPeriod
Standard Mode Serial Data Line Transmit Hold Period.
Definition: ThcConfig.h:107
THC_HID_OVER_I2C::HighSpeedModePlusSerialDataLineTransmitHoldPeriod
UINT32 HighSpeedModePlusSerialDataLineTransmitHoldPeriod
High Speed Mode Plus Serial Data Line Transmit Hold Period.
Definition: ThcConfig.h:120
THC_HID_OVER_I2C::FastModeSerialDataLineTransmitHoldPeriod
UINT32 FastModeSerialDataLineTransmitHoldPeriod
Fast Mode Serial Data Line Transmit Hold Period.
Definition: ThcConfig.h:111
THC_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: ThcConfig.h:197
THC_HID_OVER_I2C::FastModePlusSerialClockLineHighPeriod
UINT32 FastModePlusSerialClockLineHighPeriod
Fast Mode Plus Serial Clock Line High Period.
Definition: ThcConfig.h:114
ThcAssignmentThc0
@ ThcAssignmentThc0
Port assigned to THC0.
Definition: ThcConfig.h:56
THC_HID_OVER_I2C::ConnectionSpeed
UINT32 ConnectionSpeed
Connection Speed - Frequency [Hz].
Definition: ThcConfig.h:98
THC_HID_OVER_I2C::FastModePlusSerialClockLineLowPeriod
UINT32 FastModePlusSerialClockLineLowPeriod
Fast Mode Plus Serial Clock Line Low Period.
Definition: ThcConfig.h:115
THC_PORT::Mode
UINT8 Mode
1 = Hid over SPI 0 = THC. Switch between Intel THC protcol and Industry standard HID Over SPI protoco...
Definition: ThcConfig.h:132
THC_CONFIG
THC_CONFIG block provides the configurations forTouch Host Controllers.
Definition: ThcConfig.h:196
THC_HID_OVER_SPI::WriteOpcode
UINT32 WriteOpcode
Write Opcode.
Definition: ThcConfig.h:79
THC_HID_OVER_I2C::HighSpeedModePlusSerialClockLineLowPeriod
UINT32 HighSpeedModePlusSerialClockLineLowPeriod
High Speed Mode Plus Serial Clock Line Low Period.
Definition: ThcConfig.h:119
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
THC_HID_OVER_I2C::FastModeSerialClockLineLowPeriod
UINT32 FastModeSerialClockLineLowPeriod
Fast Mode Serial Clock Line Low Period.
Definition: ThcConfig.h:110
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ThermalConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Thermal
Classes
ThermalConfig.h File Reference

Thermal policy. More...

Go to the source code of this file.

Classes

struct | THERMAL_THROTTLE_LEVELS
This structure lists PCH supported throttling register setting for custimization. More...
struct | DMI_HW_WIDTH_CONTROL
This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec design. More...
struct | THERMAL_CONFIG
The THERMAL_CONFIG block describes the expected configuration of the Thermal IP block. More...

Detailed Description

Thermal policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2022 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file ThermalConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ThermalConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Thermal
ThermalConfig.h
Go to the documentation of this file.
1 /** @file
2 Thermal policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2022 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _THERMAL_CONFIG_H_
36 #define _THERMAL_CONFIG_H_
37
38 #define THERMAL_CONFIG_REVISION 1
39 extern EFI_GUID gThermalConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 This structure lists PCH supported throttling register setting for custimization.
45 When the SuggestedSetting is enabled, the customized values are ignored.
46 **/
47 typedef struct {
48 UINT32 T0Level : 9; ///< Custimized T0Level value. If SuggestedSetting is used, this setting is ignored.
49 UINT32 T1Level : 9; ///< Custimized T1Level value. If SuggestedSetting is used, this setting is ignored.
50 UINT32 T2Level : 9; ///< Custimized T2Level value. If SuggestedSetting is used, this setting is ignored.
51 UINT32 TTEnable : 1; ///< Enable the thermal throttle function. If SuggestedSetting is used, this settings is ignored.
52 /**
53 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state.
54 If SuggestedSetting is used, this setting is ignored.
55 **/
56 UINT32 TTState13Enable : 1;
57 /**
58 When set to 1, this entire register (TL) is locked and remains locked until the next platform reset.
59 If SuggestedSetting is used, this setting is ignored.
60 **/
61 UINT32 TTLock : 1;
62 UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values.
63 UINT32 RsvdBits0 : 1; ///< Reserved bits.
64 UINT32 Rsvd0; ///< Reserved bytes
65 } THERMAL_THROTTLE_LEVELS;
66
67 //
68 // Supported Thermal Sensor Target Width
69 //
70 typedef enum {
71 DmiThermSensWidthX1 = 0,
72 DmiThermSensWidthX2 = 1,
73 DmiThermSensWidthX4 = 2,
74 DmiThermSensWidthX8 = 3,
75 DmiThermSensWidthX16 = 4
76 } DMI_THERMAL_SENSOR_TARGET_WIDTH;
77
78 /**
79 This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec design.
80 When the SuggestedSetting is enabled, the customized values are ignored.
81 Look at DMI_THERMAL_SENSOR_TARGET_WIDTH for possible values
82 **/
83 typedef struct {
84 UINT32 DmiTsawEn : 1; ///< DMI Thermal Sensor Autonomous Width Enable
85 UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values
86 UINT32 RsvdBits0 : 6; ///< Reserved bits
87 UINT32 TS0TW : 3; ///< Thermal Sensor 0 Target Width (<b>DmiThermSensWidthx8</b>)
88 UINT32 TS1TW : 3; ///< Thermal Sensor 1 Target Width (<b>DmiThermSensWidthx4</b>)
89 UINT32 TS2TW : 3; ///< Thermal Sensor 2 Target Width (<b>DmiThermSensWidthx2</b>)
90 UINT32 TS3TW : 3; ///< Thermal Sensor 3 Target Width (<b>DmiThermSensWidthx1</b>)
91 UINT32 RsvdBits1 : 12; ///< Reserved bits
92 } DMI_HW_WIDTH_CONTROL;
93
94 /**
95 The THERMAL_CONFIG block describes the expected configuration of the Thermal IP block.
96 **/
97 typedef struct {
98 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
99 UINT32 PchHotEnable : 1; ///< Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: <b>Disabled<b>, 1: Enabled.
100 UINT32 RsvdBits0 : 31;
101 /**
102 This field decides the settings of Thermal throttling. When the Suggested Setting
103 is enabled, PCH RC will use the suggested representative values.
104 **/
105 THERMAL_THROTTLE_LEVELS TTLevels;
106 /**
107 This field decides the settings of DMI throttling. When the Suggested Setting
108 is enabled, PCH RC will use the suggested representative values.
109 **/
110 DMI_HW_WIDTH_CONTROL DmiHaAWC;
111 /**
112 The recommendation is the same as Cat Trip point.
113 This field decides the temperature, default is <b>120</b>.
114 Temperature value used for PCHHOT# pin assertion based on 2s complement format
115 - 0x001 positive 1'C
116 - 0x000 0'C
117 - 0x1FF negative 1'C
118 - 0x1D8 negative 40'C
119 - and so on
120 **/
121 UINT16 PchHotLevel;
122 UINT8 Rsvd0[6];
123 } THERMAL_CONFIG;
124
125 #pragma pack (pop)
126
127 #endif // _THERMAL_CONFIG_H_
DMI_HW_WIDTH_CONTROL::DmiTsawEn
UINT32 DmiTsawEn
DMI Thermal Sensor Autonomous Width Enable.
Definition: ThermalConfig.h:84
THERMAL_THROTTLE_LEVELS::T0Level
UINT32 T0Level
Custimized T0Level value. If SuggestedSetting is used, this setting is ignored.
Definition: ThermalConfig.h:48
THERMAL_THROTTLE_LEVELS::TTEnable
UINT32 TTEnable
Enable the thermal throttle function. If SuggestedSetting is used, this settings is ignored.
Definition: ThermalConfig.h:51
THERMAL_THROTTLE_LEVELS::TTLock
UINT32 TTLock
When set to 1, this entire register (TL) is locked and remains locked until the next platform reset.
Definition: ThermalConfig.h:61
DMI_HW_WIDTH_CONTROL::TS0TW
UINT32 TS0TW
Thermal Sensor 0 Target Width (DmiThermSensWidthx8)
Definition: ThermalConfig.h:87
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
DMI_HW_WIDTH_CONTROL::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: ThermalConfig.h:86
THERMAL_THROTTLE_LEVELS
This structure lists PCH supported throttling register setting for custimization.
Definition: ThermalConfig.h:47
DMI_HW_WIDTH_CONTROL::TS2TW
UINT32 TS2TW
Thermal Sensor 2 Target Width (DmiThermSensWidthx2)
Definition: ThermalConfig.h:89
THERMAL_THROTTLE_LEVELS::Rsvd0
UINT32 Rsvd0
Reserved bytes.
Definition: ThermalConfig.h:64
THERMAL_CONFIG::TTLevels
THERMAL_THROTTLE_LEVELS TTLevels
This field decides the settings of Thermal throttling.
Definition: ThermalConfig.h:105
DMI_HW_WIDTH_CONTROL::TS1TW
UINT32 TS1TW
Thermal Sensor 1 Target Width (DmiThermSensWidthx4)
Definition: ThermalConfig.h:88
THERMAL_THROTTLE_LEVELS::SuggestedSetting
UINT32 SuggestedSetting
0: Disable; 1: Enable suggested representative values.
Definition: ThermalConfig.h:62
THERMAL_CONFIG::PchHotEnable
UINT32 PchHotEnable
Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: Disabled,...
Definition: ThermalConfig.h:99
THERMAL_CONFIG::DmiHaAWC
DMI_HW_WIDTH_CONTROL DmiHaAWC
This field decides the settings of DMI throttling.
Definition: ThermalConfig.h:110
THERMAL_THROTTLE_LEVELS::TTState13Enable
UINT32 TTState13Enable
When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state.
Definition: ThermalConfig.h:56
THERMAL_THROTTLE_LEVELS::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: ThermalConfig.h:63
THERMAL_CONFIG
The THERMAL_CONFIG block describes the expected configuration of the Thermal IP block.
Definition: ThermalConfig.h:97
DMI_HW_WIDTH_CONTROL::SuggestedSetting
UINT32 SuggestedSetting
0: Disable; 1: Enable suggested representative values
Definition: ThermalConfig.h:85
THERMAL_CONFIG::PchHotLevel
UINT16 PchHotLevel
The recommendation is the same as Cat Trip point.
Definition: ThermalConfig.h:121
DMI_HW_WIDTH_CONTROL::TS3TW
UINT32 TS3TW
Thermal Sensor 3 Target Width (DmiThermSensWidthx1)
Definition: ThermalConfig.h:90
DMI_HW_WIDTH_CONTROL::RsvdBits1
UINT32 RsvdBits1
Reserved bits.
Definition: ThermalConfig.h:91
THERMAL_THROTTLE_LEVELS::T1Level
UINT32 T1Level
Custimized T1Level value. If SuggestedSetting is used, this setting is ignored.
Definition: ThermalConfig.h:49
DMI_HW_WIDTH_CONTROL
This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec de...
Definition: ThermalConfig.h:83
THERMAL_THROTTLE_LEVELS::T2Level
UINT32 T2Level
Custimized T2Level value. If SuggestedSetting is used, this setting is ignored.
Definition: ThermalConfig.h:50
THERMAL_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: ThermalConfig.h:98
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TraceHubConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • TraceHub
Classes | Enumerations
TraceHubConfig.h File Reference

Configurations for TraceHub. More...

#include <ConfigBlock.h>
Include dependency graph for TraceHubConfig.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | TRACE_HUB_CONFIG
TRACE_HUB_CONFIG block describes TraceHub settings. More...
struct | PCH_TRACE_HUB_PREMEM_CONFIG
PCH Trace Hub PreMem Configuration Contains Trace Hub settings for PCH side tracing Revision 1: - Initial version. More...
struct | TRACE_HUB_PREMEM_CONFIG
Trace Hub PreMem Configuration Contains Trace Hub settings Revision 1: - Initial version. More...

Enumerations

enum | TRACE_HUB_ENABLE_MODE
The TRACE_HUB_ENABLE_MODE describes TraceHub mode of operation.
enum | TRACE_BUFFER_SIZE
The TRACE_BUFFER_SIZE describes the desired TraceHub buffer size.

Detailed Description

Configurations for TraceHub.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TraceHubConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TraceHubConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • TraceHub
TraceHubConfig.h
Go to the documentation of this file.
1 /** @file
2 Configurations for TraceHub
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _TRACE_HUB_CONFIG_H_
36 #define _TRACE_HUB_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 #define PCH_TRACE_HUB_PREMEM_CONFIG_REVISION 1
41 #define TRACE_HUB_PREMEM_CONFIG_REVISION 1
42 #define TRACEHUB_MEM_SIZE(TRACE_BUFFER_SIZE) (((TRACE_BUFFER_SIZE) == TraceBufferNone) ? ((UINT64) (0x0)) : (LShiftU64 ((UINT64) (1), (TRACE_BUFFER_SIZE + 20))))
43
44 extern EFI_GUID gPchTraceHubPreMemConfigGuid;
45 extern EFI_GUID gTraceHubPreMemConfigGuid;
46
47 typedef enum {
48 SocTraceHub,
49 PchTraceHub,
50 CpuTraceHub,
51 MaxTraceHub
52 } TRACE_HUB_DEVICE;
53 ///
54 /// The TRACE_HUB_ENABLE_MODE describes TraceHub mode of operation
55 ///
56 typedef enum {
57 TraceHubModeDisabled = 0,
58 TraceHubModeEnabled = 1,
59 TraceHubModeHostDebugger = 2,
60 TraceHubModeMax
61 } TRACE_HUB_ENABLE_MODE;
62
63 ///
64 /// The TRACE_BUFFER_SIZE describes the desired TraceHub buffer size
65 ///
66 typedef enum {
67 TraceBuffer1M = 0x00,
68 TraceBuffer8M = 0x03,
69 TraceBuffer64M = 0x06,
70 TraceBuffer128M = 0x07,
71 TraceBuffer256M = 0x08,
72 TraceBuffer512M = 0x09,
73 TraceBuffer1G = 0x0A,
74 TraceBuffer2G = 0x0B,
75 TraceBuffer4G = 0x0C,
76 TraceBuffer8G = 0x0D,
77 TraceBufferNone = 0x0E
78 } TRACE_BUFFER_SIZE;
79
80 #pragma pack (push,1)
81 ///
82 /// TRACE_HUB_CONFIG block describes TraceHub settings
83 ///
84 typedef struct {
85
86 /**
87 Trace hub memory buffer region size value.
88 Supported size refer to TRACE_BUFFER_SIZE
89 **/
90 UINT64 MemReg0Size;
91 UINT64 MemReg1Size;
92 /**
93 Trace hub mode. Default is disabled.
94 <b>0 = Disable</b>; 1 = Enabled
95 Refer to TRACE_HUB_ENABLE_MODE
96 **/
97 UINT8 EnableMode;
98 /**
99 AET is one of FW trace agents which is exclusively rounted to one TraceHub.
100 i.e. when one TraceHub device enableds it, the other one must disable it.
101 <b>0 = Disable</b>; 1 = Enabled
102 **/
103 UINT8 AetEnabled;
104 /**
105 Indicate if BIOS trace is sent to this TraceHub instance
106 <b>0 = Disable</b>; 1 = Enabled
107 **/
108 UINT8 BiosTraceSink;
109 /**
110 Filling reserved for future use & Config block DW alignment
111 **/
112 UINT8 Reserved[5];
113 } TRACE_HUB_CONFIG;
114
115 /**
116 PCH Trace Hub PreMem Configuration
117 Contains Trace Hub settings for PCH side tracing
118 <b>Revision 1</b>: - Initial version.
119 **/
120 typedef struct {
121 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
122 UINT8 Reserved[4];
123 TRACE_HUB_CONFIG TraceHub; ///< Trace Hub Config
124 } PCH_TRACE_HUB_PREMEM_CONFIG;
125
126 /**
127 Trace Hub PreMem Configuration
128 Contains Trace Hub settings
129 <b>Revision 1</b>: - Initial version.
130 **/
131 typedef struct {
132 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
133 UINT8 Reserved[4];
134 TRACE_HUB_CONFIG TraceHub[MaxTraceHub]; ///< Trace Hub Config
135 } TRACE_HUB_PREMEM_CONFIG;
136
137 #pragma pack (pop)
138
139 #endif
TRACE_HUB_CONFIG::AetEnabled
UINT8 AetEnabled
AET is one of FW trace agents which is exclusively rounted to one TraceHub.
Definition: TraceHubConfig.h:103
ConfigBlock.h
Header file for Config Block Lib implementation.
TRACE_HUB_CONFIG
TRACE_HUB_CONFIG block describes TraceHub settings.
Definition: TraceHubConfig.h:84
TRACE_HUB_PREMEM_CONFIG
Trace Hub PreMem Configuration Contains Trace Hub settings Revision 1: - Initial version.
Definition: TraceHubConfig.h:131
TRACE_BUFFER_SIZE
TRACE_BUFFER_SIZE
The TRACE_BUFFER_SIZE describes the desired TraceHub buffer size.
Definition: TraceHubConfig.h:66
TRACE_HUB_CONFIG::EnableMode
UINT8 EnableMode
Trace hub mode.
Definition: TraceHubConfig.h:97
PCH_TRACE_HUB_PREMEM_CONFIG
PCH Trace Hub PreMem Configuration Contains Trace Hub settings for PCH side tracing Revision 1: - Ini...
Definition: TraceHubConfig.h:120
TRACE_HUB_CONFIG::BiosTraceSink
UINT8 BiosTraceSink
Indicate if BIOS trace is sent to this TraceHub instance 0 = Disable; 1 = Enabled.
Definition: TraceHubConfig.h:108
TRACE_HUB_CONFIG::MemReg0Size
UINT64 MemReg0Size
Trace hub memory buffer region size value.
Definition: TraceHubConfig.h:90
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
TRACE_HUB_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: TraceHubConfig.h:132
TRACE_HUB_ENABLE_MODE
TRACE_HUB_ENABLE_MODE
The TRACE_HUB_ENABLE_MODE describes TraceHub mode of operation.
Definition: TraceHubConfig.h:56
PCH_TRACE_HUB_PREMEM_CONFIG::TraceHub
TRACE_HUB_CONFIG TraceHub
Trace Hub Config.
Definition: TraceHubConfig.h:123
PCH_TRACE_HUB_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: TraceHubConfig.h:121
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TsnConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tsn
Macros
TsnConfig.h File Reference

TSN Config policy. More...

#include <ConfigBlock.h>
Include dependency graph for TsnConfig.h:

Go to the source code of this file.

Macros

#define TSN_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Detailed Description

TSN Config policy.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2022 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TsnConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TsnConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tsn
TsnConfig.h
Go to the documentation of this file.
1 /** @file
2 TSN Config policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2022 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _TSN_CONFIG_H_
37 #define _TSN_CONFIG_H_
38
39 #include <ConfigBlock.h>
40
41 /**
42 Making any structure change after API Lock
43 will need to maintain backward compatibility, bump up
44 structure revision and update below history table\n
45 <b>Revision 1</b>: - Initial version.
46 **/
47 #define TSN_CONFIG_REVISION 1
48 extern EFI_GUID gTsnConfigGuid;
49
50 #pragma pack (push,1)
51
52 typedef struct {
53 UINT32 MacAddr[2]; ///< MAC Address
54 } TSN_MAC_ADDR_PORT;
55
56 typedef struct {
57 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
58 /**
59 Determines if enable PCH internal TSN, 0: Disable; <b>1: Enable</b>.
60 **/
61 UINT8 Enable;
62 UINT8 TsnLinkSpeed; ///< Refer to "TSN_LINK_SPEED_OPTIONS". Default is <b> TSN_LINK_SPEED_2_5G_34MHZ</b>
63 UINT8 MultiVcEnable; ///< Enable Multi-Vc via Tc to DMA mapping. Deafult is </b> 0:disable</b>
64 UINT8 Rsvd0; ///< Reserved bytes, align to multiple 4.
65 TSN_MAC_ADDR_PORT Port[2]; ///< MAC Address
66 } TSN_CONFIG;
67
68 #pragma pack (pop)
69
70 typedef enum {
71 TSN_LINK_SPEED_2_5G_24MHZ = 0,
72 TSN_LINK_SPEED_1G_24MHZ,
73 TSN_LINK_SPEED_2_5G_34MHZ,
74 TSN_LINK_SPEED_1G_34MHZ
75 } TSN_LINK_SPEED_OPTIONS;
76
77 #endif
ConfigBlock.h
Header file for Config Block Lib implementation.
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: UefiBaseType.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Edk2
  • MdePkg
  • Include
  • Uefi
Classes | Macros | Typedefs
UefiBaseType.h File Reference

Defines data types and constants introduced in UEFI. More...

#include <Base.h>
Include dependency graph for UefiBaseType.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | EFI_TIME
EFI Time Abstraction: Year: 1900 - 9999 Month: 1 - 12 Day: 1 - 31 Hour: 0 - 23 Minute: 0 - 59 Second: 0 - 59 Nanosecond: 0 - 999,999,999 TimeZone: -1440 to 1440 or 2047. More...
struct | EFI_MAC_ADDRESS
32-byte buffer containing a network Media Access Control address. More...
union | EFI_IP_ADDRESS
16-byte buffer aligned on a 4-byte boundary. More...

Macros

#define | EFIERR(_a) ENCODE_ERROR(_a)
Define macro to encode the status code.
#define | EFI_SIZE_TO_PAGES(Size) (((Size) >> EFI_PAGE_SHIFT) + (((Size) & EFI_PAGE_MASK) ? 1 : 0))
Macro that converts a size, in bytes, to a number of EFI_PAGESs. More...
#define | EFI_PAGES_TO_SIZE(Pages) ((Pages) << EFI_PAGE_SHIFT)
Macro that converts a number of EFI_PAGEs to a size in bytes. More...
#define | EFI_IMAGE_MACHINE_IA32 0x014C
PE32+ Machine type for IA32 UEFI images.
#define | EFI_IMAGE_MACHINE_IA64 0x0200
PE32+ Machine type for IA64 UEFI images.
#define | EFI_IMAGE_MACHINE_EBC 0x0EBC
PE32+ Machine type for EBC UEFI images.
#define | EFI_IMAGE_MACHINE_X64 0x8664
PE32+ Machine type for X64 UEFI images.
#define | EFI_IMAGE_MACHINE_ARMTHUMB_MIXED 0x01C2
PE32+ Machine type for ARM mixed ARM and Thumb/Thumb2 images.
#define | EFI_IMAGE_MACHINE_AARCH64 0xAA64
PE32+ Machine type for AARCH64 A64 images.
#define | EFI_IMAGE_MACHINE_RISCV32 0x5032
PE32+ Machine type for RISC-V 32/64/128.
#define | EFI_IMAGE_MACHINE_LOONGARCH32 0x6232
PE32+ Machine type for LoongArch 32/64 images.
#define | EFI_SUCCESS RETURN_SUCCESS
Enumeration of EFI_STATUS.
#define | EFI_NETWORK_UNREACHABLE EFIERR(100)
ICMP error definitions.
#define | EFI_CONNECTION_FIN EFIERR(104)
Tcp connection status definitions.

Typedefs

typedef GUID | EFI_GUID
128-bit buffer containing a unique identifier value.
typedef RETURN_STATUS | EFI_STATUS
Function return status for EFI API.
typedef VOID * | EFI_HANDLE
A collection of related interfaces.
typedef VOID * | EFI_EVENT
Handle to an event structure.
typedef UINTN | EFI_TPL
Task priority level.
typedef UINT64 | EFI_LBA
Logical block address.
typedef UINT64 | EFI_PHYSICAL_ADDRESS
64-bit physical memory address.
typedef UINT64 | EFI_VIRTUAL_ADDRESS
64-bit virtual memory address.
typedef IPv4_ADDRESS | EFI_IPv4_ADDRESS
4-byte buffer. More...
typedef IPv6_ADDRESS | EFI_IPv6_ADDRESS
16-byte buffer. More...

Detailed Description

Defines data types and constants introduced in UEFI.

Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
Portions copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.
Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.

SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file UefiBaseType.h.

Macro Definition Documentation

◆ EFI_PAGES_TO_SIZE

#define EFI_PAGES_TO_SIZE ( Pages ) ((Pages) << EFI_PAGE_SHIFT)

Macro that converts a number of EFI_PAGEs to a size in bytes.

Parameters
Pages The number of EFI_PAGES. This parameter is assumed to be type UINTN. Passing in a parameter that is larger than UINTN may produce unexpected results.
Returns
The number of bytes associated with the number of EFI_PAGEs specified by Pages.

Definition at line 211 of file UefiBaseType.h.

◆ EFI_SIZE_TO_PAGES

#define EFI_SIZE_TO_PAGES ( Size ) (((Size) >> EFI_PAGE_SHIFT) + (((Size) & EFI_PAGE_MASK) ? 1 : 0))

Macro that converts a size, in bytes, to a number of EFI_PAGESs.

Parameters
Size A size in bytes. This parameter is assumed to be type UINTN. Passing in a parameter that is larger than UINTN may produce unexpected results.
Returns
The number of EFI_PAGESs associated with the number of bytes specified by Size.

Definition at line 198 of file UefiBaseType.h.

Typedef Documentation

◆ EFI_IPv4_ADDRESS

typedef IPv4_ADDRESS EFI_IPv4_ADDRESS

4-byte buffer.

An IPv4 internet protocol address.

Definition at line 85 of file UefiBaseType.h.

◆ EFI_IPv6_ADDRESS

typedef IPv6_ADDRESS EFI_IPv6_ADDRESS

16-byte buffer.

An IPv6 internet protocol address.

Definition at line 90 of file UefiBaseType.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: UefiBaseType.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Edk2
  • MdePkg
  • Include
  • Uefi
UefiBaseType.h
Go to the documentation of this file.
1 /** @file
2 Defines data types and constants introduced in UEFI.
3
4 Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
5 Portions copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
6 Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
7 Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
8
9 SPDX-License-Identifier: BSD-2-Clause-Patent
10
11 **/
12
13 #ifndef __UEFI_BASETYPE_H__
14 #define __UEFI_BASETYPE_H__
15
16 #include <Base.h>
17
18 //
19 // Basic data type definitions introduced in UEFI.
20 //
21
22 ///
23 /// 128-bit buffer containing a unique identifier value.
24 ///
25 typedef GUID EFI_GUID;
26 ///
27 /// Function return status for EFI API.
28 ///
29 typedef RETURN_STATUS EFI_STATUS;
30 ///
31 /// A collection of related interfaces.
32 ///
33 typedef VOID *EFI_HANDLE;
34 ///
35 /// Handle to an event structure.
36 ///
37 typedef VOID *EFI_EVENT;
38 ///
39 /// Task priority level.
40 ///
41 typedef UINTN EFI_TPL;
42 ///
43 /// Logical block address.
44 ///
45 typedef UINT64 EFI_LBA;
46
47 ///
48 /// 64-bit physical memory address.
49 ///
50 typedef UINT64 EFI_PHYSICAL_ADDRESS;
51
52 ///
53 /// 64-bit virtual memory address.
54 ///
55 typedef UINT64 EFI_VIRTUAL_ADDRESS;
56
57 ///
58 /// EFI Time Abstraction:
59 /// Year: 1900 - 9999
60 /// Month: 1 - 12
61 /// Day: 1 - 31
62 /// Hour: 0 - 23
63 /// Minute: 0 - 59
64 /// Second: 0 - 59
65 /// Nanosecond: 0 - 999,999,999
66 /// TimeZone: -1440 to 1440 or 2047
67 ///
68 typedef struct {
69 UINT16 Year;
70 UINT8 Month;
71 UINT8 Day;
72 UINT8 Hour;
73 UINT8 Minute;
74 UINT8 Second;
75 UINT8 Pad1;
76 UINT32 Nanosecond;
77 INT16 TimeZone;
78 UINT8 Daylight;
79 UINT8 Pad2;
80 } EFI_TIME;
81
82 ///
83 /// 4-byte buffer. An IPv4 internet protocol address.
84 ///
85 typedef IPv4_ADDRESS EFI_IPv4_ADDRESS;
86
87 ///
88 /// 16-byte buffer. An IPv6 internet protocol address.
89 ///
90 typedef IPv6_ADDRESS EFI_IPv6_ADDRESS;
91
92 ///
93 /// 32-byte buffer containing a network Media Access Control address.
94 ///
95 typedef struct {
96 UINT8 Addr[32];
97 } EFI_MAC_ADDRESS;
98
99 ///
100 /// 16-byte buffer aligned on a 4-byte boundary.
101 /// An IPv4 or IPv6 internet protocol address.
102 ///
103 typedef union {
104 UINT32 Addr[4];
105 EFI_IPv4_ADDRESS v4;
106 EFI_IPv6_ADDRESS v6;
107 } EFI_IP_ADDRESS;
108
109 ///
110 /// Enumeration of EFI_STATUS.
111 ///@{
112 #define EFI_SUCCESS RETURN_SUCCESS
113 #define EFI_LOAD_ERROR RETURN_LOAD_ERROR
114 #define EFI_INVALID_PARAMETER RETURN_INVALID_PARAMETER
115 #define EFI_UNSUPPORTED RETURN_UNSUPPORTED
116 #define EFI_BAD_BUFFER_SIZE RETURN_BAD_BUFFER_SIZE
117 #define EFI_BUFFER_TOO_SMALL RETURN_BUFFER_TOO_SMALL
118 #define EFI_NOT_READY RETURN_NOT_READY
119 #define EFI_DEVICE_ERROR RETURN_DEVICE_ERROR
120 #define EFI_WRITE_PROTECTED RETURN_WRITE_PROTECTED
121 #define EFI_OUT_OF_RESOURCES RETURN_OUT_OF_RESOURCES
122 #define EFI_VOLUME_CORRUPTED RETURN_VOLUME_CORRUPTED
123 #define EFI_VOLUME_FULL RETURN_VOLUME_FULL
124 #define EFI_NO_MEDIA RETURN_NO_MEDIA
125 #define EFI_MEDIA_CHANGED RETURN_MEDIA_CHANGED
126 #define EFI_NOT_FOUND RETURN_NOT_FOUND
127 #define EFI_ACCESS_DENIED RETURN_ACCESS_DENIED
128 #define EFI_NO_RESPONSE RETURN_NO_RESPONSE
129 #define EFI_NO_MAPPING RETURN_NO_MAPPING
130 #define EFI_TIMEOUT RETURN_TIMEOUT
131 #define EFI_NOT_STARTED RETURN_NOT_STARTED
132 #define EFI_ALREADY_STARTED RETURN_ALREADY_STARTED
133 #define EFI_ABORTED RETURN_ABORTED
134 #define EFI_ICMP_ERROR RETURN_ICMP_ERROR
135 #define EFI_TFTP_ERROR RETURN_TFTP_ERROR
136 #define EFI_PROTOCOL_ERROR RETURN_PROTOCOL_ERROR
137 #define EFI_INCOMPATIBLE_VERSION RETURN_INCOMPATIBLE_VERSION
138 #define EFI_SECURITY_VIOLATION RETURN_SECURITY_VIOLATION
139 #define EFI_CRC_ERROR RETURN_CRC_ERROR
140 #define EFI_END_OF_MEDIA RETURN_END_OF_MEDIA
141 #define EFI_END_OF_FILE RETURN_END_OF_FILE
142 #define EFI_INVALID_LANGUAGE RETURN_INVALID_LANGUAGE
143 #define EFI_COMPROMISED_DATA RETURN_COMPROMISED_DATA
144 #define EFI_HTTP_ERROR RETURN_HTTP_ERROR
145
146 #define EFI_WARN_UNKNOWN_GLYPH RETURN_WARN_UNKNOWN_GLYPH
147 #define EFI_WARN_DELETE_FAILURE RETURN_WARN_DELETE_FAILURE
148 #define EFI_WARN_WRITE_FAILURE RETURN_WARN_WRITE_FAILURE
149 #define EFI_WARN_BUFFER_TOO_SMALL RETURN_WARN_BUFFER_TOO_SMALL
150 #define EFI_WARN_STALE_DATA RETURN_WARN_STALE_DATA
151 #define EFI_WARN_FILE_SYSTEM RETURN_WARN_FILE_SYSTEM
152 ///@}
153
154 ///
155 /// Define macro to encode the status code.
156 ///
157 #define EFIERR(_a) ENCODE_ERROR(_a)
158
159 #define EFI_ERROR(A) RETURN_ERROR(A)
160
161 ///
162 /// ICMP error definitions
163 ///@{
164 #define EFI_NETWORK_UNREACHABLE EFIERR(100)
165 #define EFI_HOST_UNREACHABLE EFIERR(101)
166 #define EFI_PROTOCOL_UNREACHABLE EFIERR(102)
167 #define EFI_PORT_UNREACHABLE EFIERR(103)
168 ///@}
169
170 ///
171 /// Tcp connection status definitions
172 ///@{
173 #define EFI_CONNECTION_FIN EFIERR(104)
174 #define EFI_CONNECTION_RESET EFIERR(105)
175 #define EFI_CONNECTION_REFUSED EFIERR(106)
176 ///@}
177
178 //
179 // The EFI memory allocation functions work in units of EFI_PAGEs that are
180 // 4KB. This should in no way be confused with the page size of the processor.
181 // An EFI_PAGE is just the quanta of memory in EFI.
182 //
183 #define EFI_PAGE_SIZE SIZE_4KB
184 #define EFI_PAGE_MASK 0xFFF
185 #define EFI_PAGE_SHIFT 12
186
187 /**
188 Macro that converts a size, in bytes, to a number of EFI_PAGESs.
189
190 @param Size A size in bytes. This parameter is assumed to be type UINTN.
191 Passing in a parameter that is larger than UINTN may produce
192 unexpected results.
193
194 @return The number of EFI_PAGESs associated with the number of bytes specified
195 by Size.
196
197 **/
198 #define EFI_SIZE_TO_PAGES(Size) (((Size) >> EFI_PAGE_SHIFT) + (((Size) & EFI_PAGE_MASK) ? 1 : 0))
199
200 /**
201 Macro that converts a number of EFI_PAGEs to a size in bytes.
202
203 @param Pages The number of EFI_PAGES. This parameter is assumed to be
204 type UINTN. Passing in a parameter that is larger than
205 UINTN may produce unexpected results.
206
207 @return The number of bytes associated with the number of EFI_PAGEs specified
208 by Pages.
209
210 **/
211 #define EFI_PAGES_TO_SIZE(Pages) ((Pages) << EFI_PAGE_SHIFT)
212
213 ///
214 /// PE32+ Machine type for IA32 UEFI images.
215 ///
216 #define EFI_IMAGE_MACHINE_IA32 0x014C
217
218 ///
219 /// PE32+ Machine type for IA64 UEFI images.
220 ///
221 #define EFI_IMAGE_MACHINE_IA64 0x0200
222
223 ///
224 /// PE32+ Machine type for EBC UEFI images.
225 ///
226 #define EFI_IMAGE_MACHINE_EBC 0x0EBC
227
228 ///
229 /// PE32+ Machine type for X64 UEFI images.
230 ///
231 #define EFI_IMAGE_MACHINE_X64 0x8664
232
233 ///
234 /// PE32+ Machine type for ARM mixed ARM and Thumb/Thumb2 images.
235 ///
236 #define EFI_IMAGE_MACHINE_ARMTHUMB_MIXED 0x01C2
237
238 ///
239 /// PE32+ Machine type for AARCH64 A64 images.
240 ///
241 #define EFI_IMAGE_MACHINE_AARCH64 0xAA64
242
243 ///
244 /// PE32+ Machine type for RISC-V 32/64/128
245 ///
246 #define EFI_IMAGE_MACHINE_RISCV32 0x5032
247 #define EFI_IMAGE_MACHINE_RISCV64 0x5064
248 #define EFI_IMAGE_MACHINE_RISCV128 0x5128
249
250 ///
251 /// PE32+ Machine type for LoongArch 32/64 images.
252 ///
253 #define EFI_IMAGE_MACHINE_LOONGARCH32 0x6232
254 #define EFI_IMAGE_MACHINE_LOONGARCH64 0x6264
255
256 #if !defined (EFI_IMAGE_MACHINE_TYPE_VALUE) && !defined (EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE)
257 #if defined (MDE_CPU_IA32)
258
259 #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
260 ((Machine) == EFI_IMAGE_MACHINE_IA32)
261
262 #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_X64)
263
264 #elif defined (MDE_CPU_X64)
265
266 #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
267 ((Machine) == EFI_IMAGE_MACHINE_X64)
268
269 #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_IA32)
270
271 #elif defined (MDE_CPU_ARM)
272
273 #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_ARMTHUMB_MIXED)
274
275 #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
276
277 #elif defined (MDE_CPU_AARCH64)
278
279 #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
280 ((Machine) == EFI_IMAGE_MACHINE_AARCH64)
281
282 #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
283
284 #elif defined (MDE_CPU_RISCV64)
285 #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
286 ((Machine) == EFI_IMAGE_MACHINE_RISCV64)
287
288 #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
289
290 #elif defined (MDE_CPU_LOONGARCH64)
291
292 #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
293 ((Machine) == EFI_IMAGE_MACHINE_LOONGARCH64)
294
295 #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
296
297 #elif defined (MDE_CPU_EBC)
298
299 ///
300 /// This is just to make sure you can cross compile with the EBC compiler.
301 /// It does not make sense to have a PE loader coded in EBC.
302 ///
303 #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_EBC)
304
305 #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
306
307 #else
308 #error Unknown Processor Type
309 #endif
310 #else
311 #if defined (EFI_IMAGE_MACHINE_TYPE_VALUE)
312 #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_TYPE_VALUE)
313 #else
314 #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) (FALSE)
315 #endif
316 #if defined (EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE)
317 #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE)
318 #else
319 #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
320 #endif
321 #endif
322
323 #endif
EFI_IPv4_ADDRESS
IPv4_ADDRESS EFI_IPv4_ADDRESS
4-byte buffer.
Definition: UefiBaseType.h:85
EFI_VIRTUAL_ADDRESS
UINT64 EFI_VIRTUAL_ADDRESS
64-bit virtual memory address.
Definition: UefiBaseType.h:55
IPv4_ADDRESS
4-byte buffer.
Definition: Base.h:223
EFI_TPL
UINTN EFI_TPL
Task priority level.
Definition: UefiBaseType.h:41
EFI_IPv6_ADDRESS
IPv6_ADDRESS EFI_IPv6_ADDRESS
16-byte buffer.
Definition: UefiBaseType.h:90
VOID
#define VOID
Undeclared type.
Definition: Base.h:269
IPv6_ADDRESS
16-byte buffer.
Definition: Base.h:230
EFI_PHYSICAL_ADDRESS
UINT64 EFI_PHYSICAL_ADDRESS
64-bit physical memory address.
Definition: UefiBaseType.h:50
Base.h
Root include file for Mde Package Base type modules.
EFI_HANDLE
VOID * EFI_HANDLE
A collection of related interfaces.
Definition: UefiBaseType.h:33
EFI_LBA
UINT64 EFI_LBA
Logical block address.
Definition: UefiBaseType.h:45
EFI_STATUS
RETURN_STATUS EFI_STATUS
Function return status for EFI API.
Definition: UefiBaseType.h:29
EFI_IP_ADDRESS
16-byte buffer aligned on a 4-byte boundary.
Definition: UefiBaseType.h:103
EFI_GUID
GUID EFI_GUID
128-bit buffer containing a unique identifier value.
Definition: UefiBaseType.h:25
EFI_EVENT
VOID * EFI_EVENT
Handle to an event structure.
Definition: UefiBaseType.h:37
EFI_MAC_ADDRESS
32-byte buffer containing a network Media Access Control address.
Definition: UefiBaseType.h:95
EFI_TIME
EFI Time Abstraction: Year: 1900 - 9999 Month: 1 - 12 Day: 1 - 31 Hour: 0 - 23 Minute: 0 - 59 Second:...
Definition: UefiBaseType.h:68
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Usb2PhyConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Usb
Classes
Usb2PhyConfig.h File Reference

USB2 PHY configuration policy. More...

#include <UsbConfig.h>
Include dependency graph for Usb2PhyConfig.h:

Go to the source code of this file.

Classes

struct | USB2_PHY_PARAMETERS
This structure configures per USB2 AFE settings. More...
struct | USB2_PHY_CONFIG
This structure holds info on how to tune electrical parameters of USB2 ports based on board layout. More...

Detailed Description

USB2 PHY configuration policy.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file Usb2PhyConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Usb2PhyConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Usb
Usb2PhyConfig.h
Go to the documentation of this file.
1 /** @file
2 USB2 PHY configuration policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _USB2_PHY_CONFIG_H_
36 #define _USB2_PHY_CONFIG_H_
37
38 #include <UsbConfig.h>
39
40 #define USB2_PHY_CONFIG_REVISION 1
41 extern EFI_GUID gUsb2PhyConfigGuid;
42
43 #pragma pack (push,1)
44
45 /**
46 This structure configures per USB2 AFE settings.
47 It allows to setup the port electrical parameters.
48 **/
49 typedef struct {
50 /** Per Port HS Preemphasis Bias (PERPORTPETXISET)
51 000b - 0mV
52 001b - 11.25mV
53 010b - 16.9mV
54 011b - 28.15mV
55 100b - 28.15mV
56 101b - 39.35mV
57 110b - 45mV
58 111b - 56.3mV
59 **/
60 UINT8 Petxiset;
61 /** Per Port HS Transmitter Bias (PERPORTTXISET)
62 000b - 0mV
63 001b - 11.25mV
64 010b - 16.9mV
65 011b - 28.15mV
66 100b - 28.15mV
67 101b - 39.35mV
68 110b - 45mV
69 111b - 56.3mV
70 **/
71 UINT8 Txiset;
72 /**
73 Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN)
74 00b - Emphasis OFF
75 01b - De-emphasis ON
76 10b - Pre-emphasis ON
77 11b - Pre-emphasis & De-emphasis ON
78 **/
79 UINT8 Predeemp;
80 /**
81 Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF)
82 1b - half-bit pre-emphasis
83 0b - full-bit pre-emphasis
84 **/
85 UINT8 Pehalfbit;
86 /**
87 Semi Flexi Pre/DE-emphasis (reg_predeemp_semiflexi_en):
88 1: Choose the predeemp setting (increase the DC amplitude)
89 0: Choose the predeemp setting (decrease the DC amplitude)
90 **/
91 UINT8 PredeempSemiflexEn;
92 UINT8 ReservedBytes0[3]; // Reserved bytes
93 } USB2_PHY_PARAMETERS;
94
95 /**
96 This structure holds info on how to tune electrical parameters of USB2 ports based on board layout
97
98 <b>Revision 1</b>:
99 - Initial version.
100
101 **/
102 typedef struct {
103 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
104 /**
105 This structure configures per USB2 port physical settings.
106 It allows to setup the port location and port length, and configures the port strength accordingly.
107 Changing this policy values from default ones may require disabling USB2 PHY Sus Well Power Gating
108 through Usb2PhySusPgEnable on PCH-LP
109 **/
110 USB2_PHY_PARAMETERS Port[MAX_USB2_PORTS];
111 } USB2_PHY_CONFIG;
112
113 #pragma pack (pop)
114
115 #endif // _USB2_PHY_CONFIG_H_
116
USB2_PHY_PARAMETERS::Pehalfbit
UINT8 Pehalfbit
Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF) 1b - half-bit pre-emphasis 0b - full-bit pre-emphasi...
Definition: Usb2PhyConfig.h:85
USB2_PHY_PARAMETERS::Predeemp
UINT8 Predeemp
Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN) 00b - Emphasis OFF 01b - De-emphasis ON 10b - Pre...
Definition: Usb2PhyConfig.h:79
USB2_PHY_PARAMETERS::PredeempSemiflexEn
UINT8 PredeempSemiflexEn
Semi Flexi Pre/DE-emphasis (reg_predeemp_semiflexi_en): 1: Choose the predeemp setting (increase the ...
Definition: Usb2PhyConfig.h:91
UsbConfig.h
Common USB policy shared between PCH and CPU Contains general features settings for xHCI and xDCI.
USB2_PHY_PARAMETERS::Petxiset
UINT8 Petxiset
Per Port HS Preemphasis Bias (PERPORTPETXISET) 000b - 0mV 001b - 11.25mV 010b - 16....
Definition: Usb2PhyConfig.h:60
USB2_PHY_PARAMETERS::Txiset
UINT8 Txiset
Per Port HS Transmitter Bias (PERPORTTXISET) 000b - 0mV 001b - 11.25mV 010b - 16.9mV 011b - 28....
Definition: Usb2PhyConfig.h:71
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
USB2_PHY_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: Usb2PhyConfig.h:103
USB2_PHY_PARAMETERS
This structure configures per USB2 AFE settings.
Definition: Usb2PhyConfig.h:49
USB2_PHY_CONFIG
This structure holds info on how to tune electrical parameters of USB2 ports based on board layout.
Definition: Usb2PhyConfig.h:102
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Usb3HsioConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Usb
Classes | Macros
Usb3HsioConfig.h File Reference

USB3 Mod PHY configuration policy. More...

#include <UsbConfig.h>
Include dependency graph for Usb3HsioConfig.h:

Go to the source code of this file.

Classes

struct HSIO_PARAMETERS
This structure describes USB3 Port N configuration parameters. More...

Macros

#define USB3_HSIO_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Detailed Description

USB3 Mod PHY configuration policy.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file Usb3HsioConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Usb3HsioConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Usb
Usb3HsioConfig.h
Go to the documentation of this file.
1 /** @file
2 USB3 Mod PHY configuration policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _USB3_HSIO_CONFIG_H_
37 #define _USB3_HSIO_CONFIG_H_
38
39 #include <UsbConfig.h>
40
41 /**
42 Making any structure change after API Lock
43 will need to maintain backward compatibility, bump up
44 structure revision and update below history table\n
45 <b>Revision 1</b>: - Initial version.
46 **/
47 #define USB3_HSIO_CONFIG_REVISION 1
48 extern EFI_GUID gUsb3HsioConfigGuid;
49
50 #pragma pack (push,1)
51
52 /**
53 This structure describes USB3 Port N configuration parameters
54 **/
55 typedef struct {
56 /**
57 USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin)
58 HSIO_TX_DWORD8[21:16]
59 <b>Default = 00h</b>
60 **/
61 UINT8 HsioTxDownscaleAmp;
62 /**
63 USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting (ow2tapgen2deemph3p5)
64 HSIO_TX_DWORD5[21:16]
65 <b>Default = 29h</b> (approximately -3.5dB De-Emphasis)
66 **/
67 UINT8 HsioTxDeEmph;
68 /**
69 Signed Magnatude number added to the CTLE code.(ctle_adapt_offset_cfg_4_0)
70 HSIO_RX_DWORD25 [20:16]
71 Ex: -1 -- 1_0001. +1: 0_0001
72 <b>Default = 0h</b>
73 **/
74 UINT8 HsioCtrlAdaptOffsetCfg;
75 /**
76 LFPS filter select for n (filter_sel_n_2_0)
77 HSIO_RX_DWORD51 [29:27]
78 0h:1.6ns
79 1h:2.4ns
80 2h:3.2ns
81 3h:4.0ns
82 4h:4.8ns
83 5h:5.6ns
84 6h:6.4ns
85 <b>Default = 0h</b>
86 **/
87 UINT8 HsioFilterSelN;
88 /**
89 LFPS filter select for p (filter_sel_p_2_0)
90 HSIO_RX_DWORD51 [26:24]
91 0h:1.6ns
92 1h:2.4ns
93 2h:3.2ns
94 3h:4.0ns
95 4h:4.8ns
96 5h:5.6ns
97 6h:6.4ns
98 <b>Default = 0h</b>
99 **/
100 UINT8 HsioFilterSelP;
101 /**
102 Controls the input offset (olfpscfgpullupdwnres_sus_usb_2_0)
103 HSIO_RX_DWORD51 [2:0]
104 000 Prohibited
105 001 45K
106 010 Prohibited
107 011 31K
108 100 36K
109 101 36K
110 110 36K
111 111 36K
112 <b>Default = 3h</b>
113 **/
114 UINT8 HsioOlfpsCfgPullUpDwnRes;
115
116 UINT8 HsioTxDeEmphEnable; ///< Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment, <b>0: Disable</b>; 1: Enable.
117 UINT8 HsioTxDownscaleAmpEnable; ///< Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, <b>0: Disable</b>; 1: Enable.
118 UINT8 HsioCtrlAdaptOffsetCfgEnable; ///< Enable the write to Signed Magnatude number added to the CTLE code, <b>0: Disable</b>; 1: Enable.
119 UINT8 HsioFilterSelNEnable; ///< Enable the write to LFPS filter select for n, <b>0: Disable</b>; 1: Enable.
120 UINT8 HsioFilterSelPEnable; ///< Enable the write to LFPS filter select for p, <b>0: Disable</b>; 1: Enable.
121 UINT8 HsioOlfpsCfgPullUpDwnResEnable; ///< Enable the write to olfpscfgpullupdwnres, <b>0: Disable</b>; 1: Enable.
122 /**
123 USB 3.0 TX Output - Unique Transition Bit Scale for rate 3 (rate3UniqTranScale)
124 HSIO_TX_DWORD9[6:0]
125 <b>Default = 4Ch</b>
126 **/
127 UINT8 HsioTxRate3UniqTran;
128 /**
129 USB 3.0 TX Output -Unique Transition Bit Scale for rate 2 (rate2UniqTranScale)
130 HSIO_TX_DWORD9[14:8]
131 <b>Default = 4Ch</b>
132 **/
133 UINT8 HsioTxRate2UniqTran;
134 /**
135 USB 3.0 TX Output - Unique Transition Bit Scale for rate 1 (rate1UniqTranScale)
136 HSIO_TX_DWORD9[22:16]
137 <b>Default = 4Ch</b>
138 **/
139 UINT8 HsioTxRate1UniqTran;
140 /**
141 USB 3.0 TX Output - Unique Transition Bit Scale for rate 0 (rate0UniqTranScale)
142 HSIO_TX_DWORD9[30:24]
143 <b>Default = 4Ch</b>
144 **/
145 UINT8 HsioTxRate0UniqTran;
146
147 UINT8 HsioTxRate3UniqTranEnable; ///< Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 3, <b>0: Disable</b>; 1: Enable.
148 UINT8 HsioTxRate2UniqTranEnable; ///< Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 2, <b>0: Disable</b>; 1: Enable.
149 UINT8 HsioTxRate1UniqTranEnable; ///< Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 1, <b>0: Disable</b>; 1: Enable.
150 UINT8 HsioTxRate0UniqTranEnable; ///< Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 0, <b>0: Disable</b>; 1: Enable.
151 } HSIO_PARAMETERS;
152
153 typedef struct {
154 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
155 /**
156 These members describe whether the USB3 Port N of PCH is enabled by platform modules.
157 **/
158 HSIO_PARAMETERS Port[MAX_USB3_PORTS];
159 } USB3_HSIO_CONFIG;
160
161 #pragma pack (pop)
162
163 #endif // _USB3_HSIO_CONFIG_H_
164
HSIO_PARAMETERS::HsioTxRate0UniqTranEnable
UINT8 HsioTxRate0UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 0, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:150
HSIO_PARAMETERS::HsioTxDownscaleAmp
UINT8 HsioTxDownscaleAmp
USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin) HSIO_TX_DWORD8[21:16] Default = 00h
Definition: Usb3HsioConfig.h:61
HSIO_PARAMETERS::HsioTxRate3UniqTran
UINT8 HsioTxRate3UniqTran
USB 3.0 TX Output - Unique Transition Bit Scale for rate 3 (rate3UniqTranScale) HSIO_TX_DWORD9[6:0] D...
Definition: Usb3HsioConfig.h:127
HSIO_PARAMETERS::HsioTxRate2UniqTranEnable
UINT8 HsioTxRate2UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 2, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:148
HSIO_PARAMETERS::HsioTxDeEmphEnable
UINT8 HsioTxDeEmphEnable
Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:116
HSIO_PARAMETERS::HsioFilterSelNEnable
UINT8 HsioFilterSelNEnable
Enable the write to LFPS filter select for n, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:119
HSIO_PARAMETERS::HsioFilterSelPEnable
UINT8 HsioFilterSelPEnable
Enable the write to LFPS filter select for p, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:120
UsbConfig.h
Common USB policy shared between PCH and CPU Contains general features settings for xHCI and xDCI.
HSIO_PARAMETERS::HsioTxRate3UniqTranEnable
UINT8 HsioTxRate3UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 3, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:147
HSIO_PARAMETERS::HsioTxRate1UniqTran
UINT8 HsioTxRate1UniqTran
USB 3.0 TX Output - Unique Transition Bit Scale for rate 1 (rate1UniqTranScale) HSIO_TX_DWORD9[22:16]...
Definition: Usb3HsioConfig.h:139
HSIO_PARAMETERS::HsioFilterSelN
UINT8 HsioFilterSelN
LFPS filter select for n (filter_sel_n_2_0) HSIO_RX_DWORD51 [29:27] 0h:1.6ns 1h:2....
Definition: Usb3HsioConfig.h:87
HSIO_PARAMETERS::HsioCtrlAdaptOffsetCfgEnable
UINT8 HsioCtrlAdaptOffsetCfgEnable
Enable the write to Signed Magnatude number added to the CTLE code, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:118
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
HSIO_PARAMETERS
This structure describes USB3 Port N configuration parameters.
Definition: Usb3HsioConfig.h:55
HSIO_PARAMETERS::HsioTxRate0UniqTran
UINT8 HsioTxRate0UniqTran
USB 3.0 TX Output - Unique Transition Bit Scale for rate 0 (rate0UniqTranScale) HSIO_TX_DWORD9[30:24]...
Definition: Usb3HsioConfig.h:145
HSIO_PARAMETERS::HsioOlfpsCfgPullUpDwnRes
UINT8 HsioOlfpsCfgPullUpDwnRes
Controls the input offset (olfpscfgpullupdwnres_sus_usb_2_0) HSIO_RX_DWORD51 [2:0] 000 Prohibited 001...
Definition: Usb3HsioConfig.h:114
HSIO_PARAMETERS::HsioTxRate1UniqTranEnable
UINT8 HsioTxRate1UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 1, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:149
HSIO_PARAMETERS::HsioFilterSelP
UINT8 HsioFilterSelP
LFPS filter select for p (filter_sel_p_2_0) HSIO_RX_DWORD51 [26:24] 0h:1.6ns 1h:2....
Definition: Usb3HsioConfig.h:100
HSIO_PARAMETERS::HsioOlfpsCfgPullUpDwnResEnable
UINT8 HsioOlfpsCfgPullUpDwnResEnable
Enable the write to olfpscfgpullupdwnres, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:121
HSIO_PARAMETERS::HsioTxDownscaleAmpEnable
UINT8 HsioTxDownscaleAmpEnable
Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:117
HSIO_PARAMETERS::HsioTxRate2UniqTran
UINT8 HsioTxRate2UniqTran
USB 3.0 TX Output -Unique Transition Bit Scale for rate 2 (rate2UniqTranScale) HSIO_TX_DWORD9[14:8] D...
Definition: Usb3HsioConfig.h:133
HSIO_PARAMETERS::HsioCtrlAdaptOffsetCfg
UINT8 HsioCtrlAdaptOffsetCfg
Signed Magnatude number added to the CTLE code.
Definition: Usb3HsioConfig.h:74
HSIO_PARAMETERS::HsioTxDeEmph
UINT8 HsioTxDeEmph
USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting (ow2tapgen2deemph3p5) HSIO_TX_DWORD5[21:16] D...
Definition: Usb3HsioConfig.h:67
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: UsbConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Usb
Classes | Macros
UsbConfig.h File Reference

Common USB policy shared between PCH and CPU Contains general features settings for xHCI and xDCI. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | USB2_PORT_CONFIG
This structure configures per USB2.0 port settings like enabling and overcurrent protection. More...
struct | USB3_PORT_CONFIG
This structure configures per USB3.x port settings like enabling and overcurrent protection. More...
struct | XDCI_CONFIG
The XDCI_CONFIG block describes the configurations of the xDCI Usb Device controller. More...

Macros

#define | USB_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.
#define | USB_OC_MAX_PINS 16
Total OC pins number (both physical and virtual)

Detailed Description

Common USB policy shared between PCH and CPU Contains general features settings for xHCI and xDCI.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2022 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file UsbConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: UsbConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Usb
UsbConfig.h
Go to the documentation of this file.
1 /** @file
2 Common USB policy shared between PCH and CPU
3 Contains general features settings for xHCI and xDCI
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2017 - 2022 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
30 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
31 the terms of your license agreement with Intel or your vendor. This file may
32 be modified by the user, subject to additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36 #ifndef _USB_CONFIG_H_
37 #define _USB_CONFIG_H_
38
39 /**
40 Making any structure change after API Lock
41 will need to maintain backward compatibility, bump up
42 structure revision and update below history table\n
43 <b>Revision 1</b>: - Initial version.
44 **/
45 #define USB_CONFIG_REVISION 1
46 extern EFI_GUID gUsbConfigGuid;
47
48 #define MAX_USB2_PORTS 16
49 #define MAX_USB3_PORTS 10
50
51 #pragma pack (push,1)
52
53 typedef UINT8 USB_OVERCURRENT_PIN;
54 #define USB_OC_SKIP 0xFF
55 #define USB_OC_MAX_PINS 16 ///< Total OC pins number (both physical and virtual)
56
57 /**
58 This structure configures per USB2.0 port settings like enabling and overcurrent protection
59 **/
60 typedef struct {
61 /**
62 These members describe the specific over current pin number of USB 2.0 Port N.
63 It is SW's responsibility to ensure that a given port's bit map is set only for
64 one OC pin Description. USB2 and USB3 on the same combo Port must use the same OC pin.
65 **/
66 UINT32 OverCurrentPin : 8;
67 UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
68 UINT32 PortResetMessageEnable : 1; ///< 0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message
69 UINT32 SwDeviceModeEnable : 1; ///< 0: Disable USB2 Port Device Mode; 1: Force USB2 Port Device Mode
70 UINT32 RsvdBits0 : 21; ///< Reserved bits
71 } USB2_PORT_CONFIG;
72
73 /**
74 This structure configures per USB3.x port settings like enabling and overcurrent protection
75 **/
76 typedef struct {
77 /**
78 These members describe the specific over current pin number of USB 3.x Port N.
79 It is SW's responsibility to ensure that a given port's bit map is set only for
80 one OC pin Description. USB2 and USB3 on the same combo Port must use the same OC pin.
81 **/
82 UINT32 OverCurrentPin : 8;
83 UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
84 UINT32 RsvdBits0 : 23; ///< Reserved bits
85 } USB3_PORT_CONFIG;
86
87 /**
88 The XDCI_CONFIG block describes the configurations
89 of the xDCI Usb Device controller.
90 **/
91 typedef struct {
92 /**
93 This member describes whether or not the xDCI controller should be enabled.
94 0: Disable; <b>1: Enable</b>.
95 **/
96 UINT32 Enable : 1;
97 UINT32 RsvdBits0 : 31; ///< Reserved bits
98 } XDCI_CONFIG;
99
100
101 typedef struct {
102 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
103 /**
104 This policy option when set will make BIOS program Port Disable Override register during PEI phase.
105 When disabled BIOS will not program the PDO during PEI phase and leave PDO register unlocked for later programming.
106 If this is disabled, platform code MUST set it before booting into OS.
107 <b>1: Enable</b>
108 0: Disable
109 **/
110 UINT32 PdoProgramming : 1;
111 /**
112 This option allows for control whether USB should program the Overcurrent Pins mapping into xHCI.
113 Disabling this feature will disable overcurrent detection functionality.
114 Overcurrent Pin mapping data is contained in respective port structures (i.e. USB30_PORT_CONFIG) in OverCurrentPin field.
115 By default this Overcurrent functionality should be enabled and disabled only for OBS debug usage.
116 <b>1: Will program USB OC pin mapping in respective xHCI controller registers</b>
117 0: Will clear OC pin mapping allow for OBS usage of OC pins
118 **/
119 UINT32 OverCurrentEnable : 1;
120 /**
121 <b>(Test)</b>
122 If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be
123 consumed by xHCI and OC mapping registers will be locked. OverCurrent mapping data is taken from respective port data
124 structure from OverCurrentPin field.
125 If EnableOverCurrent policy is enabled this also should be enabled, otherwise xHCI won't consume OC mapping data.
126 <b>1: Program OCCFDONE bit and make xHCI consume OverCurrent mapping data</b>
127 0: Do not program OCCFDONE bit making it possible to use OBS debug on OC pins.
128 **/
129 UINT32 XhciOcLock : 1;
130 /**
131 Enabling this feature will allow for overriding LTR values for xHCI controller.
132 Values used for programming will be taken from this config block and BIOS will disregard recommended ones.
133 <b>0: disable - do not override recommended LTR values</b>
134 1: enable - override recommended LTR values
135 **/
136 UINT32 LtrOverrideEnable : 1;
137 /**
138 Enable/disable option for USB Audio Offload feture. Disabling this will disable UAOL capability
139 in xHCI and UAOL ACPI definitions will be hidden.
140 0: disable UAOL
141 <b>1: enable UAOL</b>
142 **/
143 UINT32 UaolEnable : 1;
144 /**
145 Enable HS Interrupt IN Alarm
146 0: disable - Disable HSII
147 <b>1: enable - Enable HSII</b>
148 **/
149 UINT32 HsiiEnable : 1;
150 UINT32 RsvdBits0 : 26; ///< Reserved bits
151 /**
152 High Idle Time Control override value
153 This setting is used only if LtrOverrideEnable is enabled
154 **/
155 UINT32 LtrHighIdleTimeOverride;
156 /**
157 Medium Idle Time Control override value
158 This setting is used only if LtrOverrideEnable is enabled
159 **/
160 UINT32 LtrMediumIdleTimeOverride;
161 /**
162 Low Idle Time Control override value
163 This setting is used only if LtrOverrideEnable is enabled
164 **/
165 UINT32 LtrLowIdleTimeOverride;
166 /**
167 These members describe whether the USB2 Port N of PCH is enabled by platform modules.
168 **/
169 USB2_PORT_CONFIG PortUsb20[MAX_USB2_PORTS];
170 /**
171 These members describe whether the USB3 Port N of PCH is enabled by platform modules.
172 **/
173 USB3_PORT_CONFIG PortUsb30[MAX_USB3_PORTS];
174 /**
175 This member describes whether or not the xDCI controller should be enabled.
176 **/
177 XDCI_CONFIG XdciConfig;
178 /**
179 Adding USB3.1 Speeed selection
180 **/
181 UINT32 Usb31Speed;
182
183 } USB_CONFIG;
184
185 #pragma pack (pop)
186
187 #endif // _USB_CONFIG_H_
USB3_PORT_CONFIG::Enable
UINT32 Enable
0: Disable; 1: Enable.
Definition: UsbConfig.h:83
USB2_PORT_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: UsbConfig.h:70
USB2_PORT_CONFIG::SwDeviceModeEnable
UINT32 SwDeviceModeEnable
0: Disable USB2 Port Device Mode; 1: Force USB2 Port Device Mode
Definition: UsbConfig.h:69
USB2_PORT_CONFIG::Enable
UINT32 Enable
0: Disable; 1: Enable.
Definition: UsbConfig.h:67
XDCI_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: UsbConfig.h:97
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
USB3_PORT_CONFIG
This structure configures per USB3.x port settings like enabling and overcurrent protection.
Definition: UsbConfig.h:76
XDCI_CONFIG::Enable
UINT32 Enable
This member describes whether or not the xDCI controller should be enabled.
Definition: UsbConfig.h:96
XDCI_CONFIG
The XDCI_CONFIG block describes the configurations of the xDCI Usb Device controller.
Definition: UsbConfig.h:91
USB2_PORT_CONFIG::PortResetMessageEnable
UINT32 PortResetMessageEnable
0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message
Definition: UsbConfig.h:68
USB2_PORT_CONFIG::OverCurrentPin
UINT32 OverCurrentPin
These members describe the specific over current pin number of USB 2.0 Port N.
Definition: UsbConfig.h:66
USB3_PORT_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: UsbConfig.h:84
USB3_PORT_CONFIG::OverCurrentPin
UINT32 OverCurrentPin
These members describe the specific over current pin number of USB 3.x Port N.
Definition: UsbConfig.h:82
USB2_PORT_CONFIG
This structure configures per USB2.0 port settings like enabling and overcurrent protection.
Definition: UsbConfig.h:60
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: VmdPeiConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Vmd
Classes
VmdPeiConfig.h File Reference

VMD PEI policy VMD Config Block. More...

#include <ConfigBlock.h>
#include <Library/VmdInfoLib.h>
Include dependency graph for VmdPeiConfig.h:

Go to the source code of this file.

Classes

struct VMD_PEI_CONFIG
This configuration block is to configure VMD related variables used in PostMem PEI. More...

Detailed Description

VMD PEI policy VMD Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file VmdPeiConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: VmdPeiConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Vmd
VmdPeiConfig.h
Go to the documentation of this file.
1 /** @file
2 VMD PEI policy
3 VMD Config Block
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2017 - 2021 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
30 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
31 the terms of your license agreement with Intel or your vendor. This file may
32 be modified by the user, subject to additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36 #ifndef _VMD_PEI_CONFIG_H_
37 #define _VMD_PEI_CONFIG_H_
38
39 #include <ConfigBlock.h>
40 #include <Library/VmdInfoLib.h>
41
42 #define VMD_PEI_CONFIG_REVISION 1
43
44 #pragma pack (push,1)
45
46
47 typedef struct {
48 UINT8 RpBus;
49 UINT8 RpDevice;
50 UINT8 RpFunction;
51 UINT8 RpEnable;
52 } RP_BDF_DATA;
53
54 /**
55 This configuration block is to configure VMD related variables used in PostMem PEI.
56 If VMD Device is not supported, all policies can be ignored.
57 <b>Revision 1</b>:
58 - Initial version.
59 **/
60
61 typedef struct {
62 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
63 UINT8 VmdEnable; ///< Offset 28 This field used to enable VMD controller <b>1=Enable(default)</b> 0=Disable
64 UINT8 VmdGlobalMapping; ///< Offset 29 This field used to enable Global Mapping 1=Enable <b>0=Disable(default)</b>
65 UINT8 Rsvd[2]; ///< Offset 30-39 Reserved
66 RP_BDF_DATA VmdPortEnable[VMD_MAX_DEVICES]; ///< Offset 40 to 163 This field used to to store b/d/f for each root port along with enable Support 1=Enable <b>0=Disable (default)</b>
67 VOID *VmdVariablePtr; ///< This config block will be updated as per the EFI variable.
68 UINT32 VmdCfgBarBase; ///< Temp Address VMD CFG BAR Default is <b>0xA0000000</b>
69 UINT32 VmdMemBar1Base; ///< Temp Address VMD CFG BAR Default is <b>0xA2000000</b>
70 UINT32 VmdMemBar2Base; ///< Temp Address VMD CFG BAR Default is <b>0xA4000000</b>
71 } VMD_PEI_CONFIG;
72
73 #pragma pack (pop)
74
75 #endif /* _VMD_PEI_PREMEM_CONFIG_H_ */
VMD_PEI_CONFIG::VmdMemBar1Base
UINT32 VmdMemBar1Base
Temp Address VMD CFG BAR Default is 0xA2000000
Definition: VmdPeiConfig.h:69
ConfigBlock.h
Header file for Config Block Lib implementation.
VOID
#define VOID
Undeclared type.
Definition: Base.h:269
VMD_PEI_CONFIG::VmdVariablePtr
VOID * VmdVariablePtr
This config block will be updated as per the EFI variable.
Definition: VmdPeiConfig.h:67
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
VMD_PEI_CONFIG::VmdEnable
UINT8 VmdEnable
Offset 28 This field used to enable VMD controller 1=Enable(default) 0=Disable.
Definition: VmdPeiConfig.h:63
VMD_PEI_CONFIG::VmdGlobalMapping
UINT8 VmdGlobalMapping
Offset 29 This field used to enable Global Mapping 1=Enable 0=Disable(default)
Definition: VmdPeiConfig.h:64
VMD_PEI_CONFIG::VmdCfgBarBase
UINT32 VmdCfgBarBase
Temp Address VMD CFG BAR Default is 0xA0000000
Definition: VmdPeiConfig.h:68
VMD_PEI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: VmdPeiConfig.h:62
VMD_PEI_CONFIG
This configuration block is to configure VMD related variables used in PostMem PEI.
Definition: VmdPeiConfig.h:61
VMD_PEI_CONFIG::VmdMemBar2Base
UINT32 VmdMemBar2Base
Temp Address VMD CFG BAR Default is 0xA4000000
Definition: VmdPeiConfig.h:70
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: VtdConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Vtd
Classes | Macros | Typedefs
VtdConfig.h File Reference

VT-d policy definitions. More...

#include <VtdInfo.h>
Include dependency graph for VtdConfig.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct VTD_ENGINE_CONFIG
This structure describes each VT-d engine. More...

Macros

#define | VTD_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.
#define | VTD_DXE_CONFIG_REVISION 1
Making any structure change after API Lock will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Typedefs

typedef EFI_STATUS(* VTD_ENABLE_DMA_BUFFER) (IN VTD_ENGINE VtdEngineNumber)
Enable DMA buffer in VTd. More...

Detailed Description

VT-d policy definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2022 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file VtdConfig.h.

Typedef Documentation

◆ VTD_ENABLE_DMA_BUFFER

typedef EFI_STATUS( * VTD_ENABLE_DMA_BUFFER) (IN VTD_ENGINE VtdEngineNumber)

Enable DMA buffer in VTd.

Parameters
[in] VtdEngineNumber VTd engine number.
Return values
EFI_SUCCESS | Enable successfully.
EFI_INVALID_PARAMETER | Input parameters are invalid.
EFI_UNSUPPORTED | VTd base is zero.
EFI_OUT_OF_RESOURCES | There is no additional space in the PPI database.

Definition at line 72 of file VtdConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: VtdConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Vtd
VtdConfig.h
Go to the documentation of this file.
1 /** @file
2 VT-d policy definitions.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2022 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _VTD_CONFIG_H_
36 #define _VTD_CONFIG_H_
37
38 #include <VtdInfo.h>
39
40 #pragma pack(push, 1)
41
42 /**
43 Making any structure change after API Lock
44 will need to maintain backward compatibility, bump up
45 structure revision and update below history table\n
46 <b>Revision 1</b>: - Initial version.
47 **/
48 #define VTD_CONFIG_REVISION 1
49 /**
50 Making any structure change after API Lock
51 will need to maintain backward compatibility, bump up
52 structure revision and update below history table\n
53 <b>Revision 1</b>: - Initial version.
54 **/
55 #define VTD_DXE_CONFIG_REVISION 1
56
57 //
58 // Forward declaration for the VTd Enable DMA Buffer PPI.
59 //
60
61 /**
62 Enable DMA buffer in VTd
63
64 @param[in] VtdEngineNumber VTd engine number.
65
66 @retval EFI_SUCCESS Enable successfully.
67 @retval EFI_INVALID_PARAMETER Input parameters are invalid.
68 @retval EFI_UNSUPPORTED VTd base is zero.
69 @retval EFI_OUT_OF_RESOURCES There is no additional space in the PPI database.
70 **/
71 typedef
72 EFI_STATUS
73 (EFIAPI *VTD_ENABLE_DMA_BUFFER) (
74 IN VTD_ENGINE VtdEngineNumber
75 );
76
77 /**
78 This structure describes each VT-d engine.
79 **/
80 typedef struct {
81 UINT32 Reserved ;
82 } VTD_ENGINE_CONFIG;
83
84 typedef struct {
85 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
86 /**
87 Offset 28:
88 VT-D Support can be verified by reading CAP ID register as expalined in BIOS Spec.
89 This policy is for debug purpose only.
90 If VT-D is not supported, all other policies in this config block will be ignored.
91 <b>0 = To use Vt-d</b>;
92 1 = Avoids programming Vtd bars, Vtd overrides and DMAR table.
93 **/
94 UINT8 VtdDisable;
95 UINT8 X2ApicOptOut; ///< Offset 29: This field is used to enable the X2APIC_OPT_OUT bit in the DMAR table. 1=Enable/Set and <b>0=Disable/Clear</b>
96 UINT8 DmaControlGuarantee; ///< Offset 30: This field is used to enable the DMA_CONTROL_GUARANTEE bit in the DMAR table. 1=Enable/Set and <b>0=Disable/Clear</b>
97 UINT8 Reserved[3]; ///< Offset 31: Reserved
98 UINT8 PreBootDmaMask; ///< Offset 34: Convey PcdVTdPolicyPropertyMask value from EDK2 IntelSiliconPkg
99 UINT8 Reserved1; ///< Offset 35: Reserved
100 UINT32 DmaBufferSize; ///< Offset 36: Protect Memory Region (PMR) DMA buffer size
101 UINT8 Reserved40[8]; ///< Offset 40: Reserved
102 UINT32 BaseAddress[VTD_ENGINE_NUMBER]; ///< Offset 40: This field is used to describe the base addresses for VT-d function
103 } VTD_CONFIG;
104
105 typedef struct {
106 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
107 /**
108 This member configures the features, property, and capability for each VT-d engine.
109 **/
110 VTD_ENGINE_CONFIG VtdEngineConfig[VTD_ENGINE_NUMBER];
111 } VTD_DXE_CONFIG;
112 #pragma pack(pop)
113
114 #endif // _VTD_CONFIG_H_
IN
#define IN
Datum is passed to the function.
Definition: Base.h:279
VTD_ENGINE_CONFIG
This structure describes each VT-d engine.
Definition: VtdConfig.h:80
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
EFI_STATUS
RETURN_STATUS EFI_STATUS
Function return status for EFI API.
Definition: UefiBaseType.h:29
VTD_ENABLE_DMA_BUFFER
EFI_STATUS(* VTD_ENABLE_DMA_BUFFER)(IN VTD_ENGINE VtdEngineNumber)
Enable DMA buffer in VTd.
Definition: VtdConfig.h:73
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: WatchDogConfig.h File Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Wdt
Classes
WatchDogConfig.h File Reference

WatchDog policy. More...

Go to the source code of this file.

Classes

struct PCH_WDT_PREMEM_CONFIG
This policy clears status bits and disable watchdog, then lock the WDT registers. More...

Detailed Description

WatchDog policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file WatchDogConfig.h.

Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: WatchDogConfig.h Source File

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Wdt
WatchDogConfig.h
Go to the documentation of this file.
1 /** @file
2 WatchDog policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _WATCH_DOG_CONFIG_H_
36 #define _WATCH_DOG_CONFIG_H_
37
38 #define PCH_WDT_PREMEM_CONFIG_REVISION 1
39 extern EFI_GUID gWatchDogPreMemConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 This policy clears status bits and disable watchdog, then lock the
45 WDT registers.
46 while WDT is designed to be disabled and locked by Policy,
47 bios should not enable WDT by WDT PPI. In such case, bios shows the
48 warning message but not disable and lock WDT register to make sure
49 WDT event trigger correctly.
50 **/
51 typedef struct {
52 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
53 UINT32 DisableAndLock : 1; ///< <b>(Test)</b> Set 1 to clear WDT status, then disable and lock WDT registers. <b>0: Disable</b>; 1: Enable.
54 UINT32 RsvdBits : 31;
55 } PCH_WDT_PREMEM_CONFIG;
56
57 #pragma pack (pop)
58
59 #endif // _WATCH_DOG_CONFIG_H_
PCH_WDT_PREMEM_CONFIG::DisableAndLock
UINT32 DisableAndLock
(Test) Set 1 to clear WDT status, then disable and lock WDT registers. 0: Disable; 1: Enable.
Definition: WatchDogConfig.h:53
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_WDT_PREMEM_CONFIG
This policy clears status bits and disable watchdog, then lock the WDT registers.
Definition: WatchDogConfig.h:51
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:213
PCH_WDT_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: WatchDogConfig.h:52
Generated on Mon Dec 29 2025 02:15:47 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented file members with links to the documentation:

- _ -

  • _BASE_INT_SIZE_OF : Base.h
  • _CONCATENATE : Base.h
  • _INT_SIZE_OF : Base.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented file members with links to the documentation:

- a -

  • ABS : Base.h
  • AddConfigBlock() : ConfigBlockLib.h
  • ADDRESS_IS_ALIGNED : Base.h
  • ALIGN_POINTER : Base.h
  • ALIGN_VALUE : Base.h
  • ALIGN_VALUE_ADDEND : Base.h
  • ALIGN_VARIABLE : Base.h
  • ALIGNOF : Base.h
  • AMT_ERROR_MSG_ID : AmtConfig.h
  • AMT_REPORT_ERROR : AmtConfig.h
  • ANALYZER_NORETURN : Base.h
  • ANALYZER_UNREACHABLE : Base.h
  • ARRAY_SIZE : Base.h
  • ASM_PFX : Base.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented file members with links to the documentation:

- b -

  • B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK : GpioConfig.h
  • B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK : GpioConfig.h
  • B_GPIO_INT_CONFIG_INT_SOURCE_MASK : GpioConfig.h
  • B_GPIO_INT_CONFIG_INT_TYPE_MASK : GpioConfig.h
  • B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK : GpioConfig.h
  • B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK : GpioConfig.h
  • B_GPIO_OTHER_CONFIG_RXRAW_MASK : GpioConfig.h
  • BASE_ARG : Base.h
  • BASE_CR : Base.h
  • BASE_LIST : Base.h
  • BCLK_CONFIG_REVISION : PmConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented file members with links to the documentation:

- c -

  • CNVI_BT_INTERFACE : CnviConfig.h
  • CNVI_CONFIG_REVISION : CnviConfig.h
  • CNVI_MODE : CnviConfig.h
  • CNVI_PREMEM_CONFIG_REVISION : CnviConfig.h
  • CONFIG_BLOCK : ConfigBlock.h
  • CONFIG_BLOCK_HEADER : ConfigBlock.h
  • CONFIG_BLOCK_TABLE_HEADER : ConfigBlock.h
  • CONST : Base.h
  • CPU_POWER_MGMT_VR_CONFIG_REVISION : CpuPowerMgmtVrConfig.h
  • CreateConfigBlockTable() : ConfigBlockLib.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented file members with links to the documentation:

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  • DXE_ERROR : PiMultiPhase.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented file members with links to the documentation:

- e -

  • EFI_AP_PROCEDURE : PiMultiPhase.h
  • EFI_AP_PROCEDURE2 : PiMultiPhase.h
  • EFI_AUTH_STATUS_PLATFORM_OVERRIDE : PiMultiPhase.h
  • EFI_CONNECTION_FIN : UefiBaseType.h
  • EFI_EVENT : UefiBaseType.h
  • EFI_GUID : UefiBaseType.h
  • EFI_HANDLE : UefiBaseType.h
  • EFI_HOB_HANDOFF_TABLE_VERSION : PiHob.h
  • EFI_IMAGE_MACHINE_AARCH64 : UefiBaseType.h
  • EFI_IMAGE_MACHINE_ARMTHUMB_MIXED : UefiBaseType.h
  • EFI_IMAGE_MACHINE_EBC : UefiBaseType.h
  • EFI_IMAGE_MACHINE_IA32 : UefiBaseType.h
  • EFI_IMAGE_MACHINE_IA64 : UefiBaseType.h
  • EFI_IMAGE_MACHINE_LOONGARCH32 : UefiBaseType.h
  • EFI_IMAGE_MACHINE_RISCV32 : UefiBaseType.h
  • EFI_IMAGE_MACHINE_X64 : UefiBaseType.h
  • EFI_INTERRUPT_PENDING : PiMultiPhase.h
  • EFI_IPv4_ADDRESS : UefiBaseType.h
  • EFI_IPv6_ADDRESS : UefiBaseType.h
  • EFI_LBA : UefiBaseType.h
  • EFI_MM_RESERVED_MMRAM_REGION : PiMultiPhase.h
  • EFI_MMRAM_OPEN : PiMultiPhase.h
  • EFI_NETWORK_UNREACHABLE : UefiBaseType.h
  • EFI_NOT_AVAILABLE_YET : PiMultiPhase.h
  • EFI_PAGES_TO_SIZE : UefiBaseType.h
  • EFI_PEI_MP_SERVICES_ENABLEDISABLEAP : MpServices.h
  • EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS : MpServices.h
  • EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO : MpServices.h
  • EFI_PEI_MP_SERVICES_STARTUP_ALL_APS : MpServices.h
  • EFI_PEI_MP_SERVICES_STARTUP_THIS_AP : MpServices.h
  • EFI_PEI_MP_SERVICES_SWITCH_BSP : MpServices.h
  • EFI_PEI_MP_SERVICES_WHOAMI : MpServices.h
  • EFI_PHYSICAL_ADDRESS : UefiBaseType.h
  • EFI_REQUEST_UNLOAD_IMAGE : PiMultiPhase.h
  • EFI_RESOURCE_ATTRIBUTE_TYPE : PiHob.h
  • EFI_RESOURCE_TYPE : PiHob.h
  • EFI_SIZE_TO_PAGES : UefiBaseType.h
  • EFI_STATUS : UefiBaseType.h
  • EFI_SUCCESS : UefiBaseType.h
  • EFI_TPL : UefiBaseType.h
  • EFI_VIRTUAL_ADDRESS : UefiBaseType.h
  • EFIERR : UefiBaseType.h
  • ENCODE_ERROR : Base.h
  • ENCODE_WARNING : Base.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented file members with links to the documentation:

- f -

  • FALSE : Base.h
  • FIVR_RAIL_SX_STATE : FivrConfig.h
  • FSP_ERROR_INFO_HOB_GUID : FspErrorInfo.h
  • FSPM_ARCH_CONFIG_GUID : FspmArchConfigPpi.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented file members with links to the documentation:

- g -

  • GetConfigBlock() : ConfigBlockLib.h
  • GLOBAL_REMOVE_IF_UNREFERENCED : Base.h
  • GPIO_DIRECTION : GpioConfig.h
  • GPIO_ELECTRICAL_CONFIG : GpioConfig.h
  • GPIO_GROUP : GpioConfig.h
  • GPIO_HARDWARE_DEFAULT : GpioConfig.h
  • GPIO_HOSTSW_OWN : GpioConfig.h
  • GPIO_INT_CONFIG : GpioConfig.h
  • GPIO_LOCK_CONFIG : GpioConfig.h
  • GPIO_OTHER_CONFIG : GpioConfig.h
  • GPIO_OUTPUT_STATE : GpioConfig.h
  • GPIO_PAD : GpioConfig.h
  • GPIO_PAD_MODE : GpioConfig.h
  • GPIO_RESET_CONFIG : GpioConfig.h
  • GpioDirDefault : GpioConfig.h
  • GpioDirIn : GpioConfig.h
  • GpioDirInInv : GpioConfig.h
  • GpioDirInInvOut : GpioConfig.h
  • GpioDirInOut : GpioConfig.h
  • GpioDirNone : GpioConfig.h
  • GpioDirOut : GpioConfig.h
  • GpioDswReset : GpioConfig.h
  • GpioHardwareDefault : GpioConfig.h
  • GpioHostDeepReset : GpioConfig.h
  • GpioHostOwnAcpi : GpioConfig.h
  • GpioHostOwnDefault : GpioConfig.h
  • GpioHostOwnGpio : GpioConfig.h
  • GpioIntApic : GpioConfig.h
  • GpioIntBothEdge : GpioConfig.h
  • GpioIntDefault : GpioConfig.h
  • GpioIntDis : GpioConfig.h
  • GpioIntEdge : GpioConfig.h
  • GpioIntLevel : GpioConfig.h
  • GpioIntLvlEdgDis : GpioConfig.h
  • GpioIntNmi : GpioConfig.h
  • GpioIntSci : GpioConfig.h
  • GpioIntSmi : GpioConfig.h
  • GpioLockDefault : GpioConfig.h
  • GpioNoTolerance1v8 : GpioConfig.h
  • GpioOutDefault : GpioConfig.h
  • GpioOutHigh : GpioConfig.h
  • GpioOutLow : GpioConfig.h
  • GpioOutputStateLock : GpioConfig.h
  • GpioPadConfigLock : GpioConfig.h
  • GpioPlatformReset : GpioConfig.h
  • GpioResetDefault : GpioConfig.h
  • GpioResumeReset : GpioConfig.h
  • GpioRxRaw1Default : GpioConfig.h
  • GpioRxRaw1Dis : GpioConfig.h
  • GpioRxRaw1En : GpioConfig.h
  • GpioTermDefault : GpioConfig.h
  • GpioTermNative : GpioConfig.h
  • GpioTermNone : GpioConfig.h
  • GpioTermWpd20K : GpioConfig.h
  • GpioTermWpd5K : GpioConfig.h
  • GpioTermWpu1K : GpioConfig.h
  • GpioTermWpu1K2K : GpioConfig.h
  • GpioTermWpu20K : GpioConfig.h
  • GpioTermWpu2K : GpioConfig.h
  • GpioTermWpu5K : GpioConfig.h
  • GpioTolerance1v8 : GpioConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented file members with links to the documentation:

- h -

  • HDAUDIO_CONFIG_REVISION : HdAudioConfig.h
  • HDAUDIO_DXE_CONFIG_REVISION : HdAudioConfig.h
  • HDAUDIO_PREMEM_CONFIG_REVISION : HdAudioConfig.h
  • HDAUDIO_VERB_TABLE_INIT : HdAudioConfig.h
  • HDAUDIO_VERB_TABLE_VIDDID : HdAudioConfig.h
  • HidOverI2c : ThcConfig.h
  • HidOverSpi : ThcConfig.h
  • HOST_BRIDGE_PEI_CONFIG_REVISION : HostBridgeConfig.h
  • HOST_BRIDGE_PREMEM_CONFIG_REVISION : HostBridgeConfig.h
  • HYBRID_GRAPHICS_CONFIG_REVISION : HybridGraphicsConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented file members with links to the documentation:

- i -

  • IN : Base.h
  • IS_ALIGNED : Base.h
  • IS_POW2 : Base.h
  • ISH_CONFIG_REVISION : IshConfig.h
  • ISH_I3C_CONFIG_REVISION : IshConfig.h
  • ISH_PREMEM_CONFIG_REVISION : IshConfig.h
  • ITBT_GENERIC_CONFIG : PeiITbtGenericStructure.h
  • ITBT_ROOTPORT_CONFIG : PeiITbtGenericStructure.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented file members with links to the documentation:

- l -

  • LIST_ENTRY : Base.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented file members with links to the documentation:

- m -

  • MAX : Base.h
  • MAX_INT8 : Base.h
  • MAX_NUM_VRS : CpuPowerMgmtVrConfig.h
  • MIN : Base.h
  • MIN_INT8 : Base.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented file members with links to the documentation:

- n -

  • NORETURN : Base.h
  • NULL : Base.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented file members with links to the documentation:

- o -

  • OFFSET_OF : Base.h
  • OPTIONAL : Base.h
  • OUT : Base.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented file members with links to the documentation:

- p -

  • PcdFspAreaBaseAddress : FspFixedPcds.h
  • PcdFspImageIdString : FspFixedPcds.h
  • PcdFspReservedBufferSize : FspFixedPcds.h
  • PcdGlobalDataPointerAddress : FspFixedPcds.h
  • PcdSiliconInitVersionBuild : FspFixedPcds.h
  • PcdSiliconInitVersionMajor : FspFixedPcds.h
  • PcdSiliconInitVersionMinor : FspFixedPcds.h
  • PcdSiliconInitVersionRevision : FspFixedPcds.h
  • PcdTemporaryRamBase : FspFixedPcds.h
  • PcdTemporaryRamSize : FspFixedPcds.h
  • PCH_ESPI_CONFIG_REVISION : EspiConfig.h
  • PCH_GENERAL_CONFIG_REVISION : PchGeneralConfig.h
  • PCH_GENERAL_PREMEM_CONFIG_REVISION : PchGeneralConfig.h
  • PCH_HSIO_CONFIG_REVISION : HsioConfig.h
  • PCH_HSIO_PREMEM_CONFIG_REVISION : HsioConfig.h
  • PCH_INT_PIN : InterruptConfig.h
  • PCH_MAX_DEVICE_INTERRUPT_CONFIG : InterruptConfig.h
  • PCH_MAX_ITSS_IPC_REGS : InterruptConfig.h
  • PCH_MAX_ITSS_IRQ_NUM : InterruptConfig.h
  • PCH_MAX_PXRC_CONFIG : InterruptConfig.h
  • PCH_PCIE_ASPM_CONTROL : PchPcieRpConfig.h
  • PCH_PCIE_CLOCK_USAGE : PchPcieRpConfig.h
  • PCH_PCIE_CONFIG_REVISION : PchPcieRpConfig.h
  • PCH_PCIE_L1SUBSTATES_CONTROL : PchPcieRpConfig.h
  • PCH_PCIE_RP_PREMEM_CONFIG_REVISION : PchPcieRpConfig.h
  • PCH_PM_CONFIG_REVISION : PmConfig.h
  • PCH_RESERVED_PAGE_ROUTE : PchGeneralConfig.h
  • PCH_SLP_S4_MIN_ASSERT : PmConfig.h
  • PchClockUsageCpuPcie0 : PchPcieRpConfig.h
  • PchClockUsageUnspecified : PchPcieRpConfig.h
  • PchNoInt : InterruptConfig.h
  • PchReservedPageToLpc : PchGeneralConfig.h
  • PchReservedPageToPcie : PchGeneralConfig.h
  • PchSlpS4PchTime : PmConfig.h
  • PCIE_FORM_FACTOR : PcieConfig.h
  • PCIE_LINK_EQ_METHOD : PcieConfig.h
  • PCIE_LINK_EQ_MODE : PcieConfig.h
  • PCIE_RP_DXE_CONFIG_REVISION : PchPcieRpConfig.h
  • PcieLinkEqCoefficientMode : PcieConfig.h
  • PcieLinkEqPresetMode : PcieConfig.h
  • PcieLinkFixedEq : PcieConfig.h
  • PcieLinkHardwareEq : PcieConfig.h
  • PEI_ITBT_CONFIG_REVISION : PeiITbtConfig.h
  • PEI_POLICY_INIT : PeiSiDefaultPolicy.h
  • PEI_PREMEM_POLICY_INIT : PeiPreMemSiDefaultPolicy.h
  • PI_ENCODE_ERROR : PiMultiPhase.h
  • PI_ENCODE_WARNING : PiMultiPhase.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented file members with links to the documentation:

- r -

  • RETURN_ABORTED : Base.h
  • RETURN_ACCESS_DENIED : Base.h
  • RETURN_ADDRESS : Base.h
  • RETURN_ALREADY_STARTED : Base.h
  • RETURN_BAD_BUFFER_SIZE : Base.h
  • RETURN_BUFFER_TOO_SMALL : Base.h
  • RETURN_COMPROMISED_DATA : Base.h
  • RETURN_CRC_ERROR : Base.h
  • RETURN_DEVICE_ERROR : Base.h
  • RETURN_END_OF_FILE : Base.h
  • RETURN_END_OF_MEDIA : Base.h
  • RETURN_ERROR : Base.h
  • RETURN_HTTP_ERROR : Base.h
  • RETURN_ICMP_ERROR : Base.h
  • RETURN_INCOMPATIBLE_VERSION : Base.h
  • RETURN_INVALID_LANGUAGE : Base.h
  • RETURN_INVALID_PARAMETER : Base.h
  • RETURN_LOAD_ERROR : Base.h
  • RETURN_MEDIA_CHANGED : Base.h
  • RETURN_NO_MAPPING : Base.h
  • RETURN_NO_MEDIA : Base.h
  • RETURN_NO_RESPONSE : Base.h
  • RETURN_NOT_FOUND : Base.h
  • RETURN_NOT_READY : Base.h
  • RETURN_NOT_STARTED : Base.h
  • RETURN_OUT_OF_RESOURCES : Base.h
  • RETURN_PROTOCOL_ERROR : Base.h
  • RETURN_SECURITY_VIOLATION : Base.h
  • RETURN_SUCCESS : Base.h
  • RETURN_TFTP_ERROR : Base.h
  • RETURN_TIMEOUT : Base.h
  • RETURN_UNSUPPORTED : Base.h
  • RETURN_VOLUME_CORRUPTED : Base.h
  • RETURN_VOLUME_FULL : Base.h
  • RETURN_WARN_BUFFER_TOO_SMALL : Base.h
  • RETURN_WARN_DELETE_FAILURE : Base.h
  • RETURN_WARN_FILE_SYSTEM : Base.h
  • RETURN_WARN_STALE_DATA : Base.h
  • RETURN_WARN_UNKNOWN_GLYPH : Base.h
  • RETURN_WARN_WRITE_FAILURE : Base.h
  • RETURN_WRITE_PROTECTED : Base.h
  • RETURNS_TWICE : Base.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented file members with links to the documentation:

- s -

  • SERIAL_IO_CONFIG_REVISION : SerialIoConfig.h
  • SERIAL_IO_CS_POLARITY : SerialIoDevices.h
  • SERIAL_IO_I2C_MODE : SerialIoDevices.h
  • SERIAL_IO_I3C_MODE : SerialIoDevices.h
  • SERIAL_IO_SPI_MODE : SerialIoDevices.h
  • SERIAL_IO_UART_MODE : SerialIoDevices.h
  • SERIAL_IO_UART_PG : SerialIoDevices.h
  • SerialIoUartPgAuto : SerialIoDevices.h
  • SerialIoUartPgDisabled : SerialIoDevices.h
  • SerialIoUartPgEnabled : SerialIoDevices.h
  • SI_POLICY_REVISION : SiPolicyStruct.h
  • SI_PREMEM_POLICY_REVISION : SiPolicyStruct.h
  • SIGNATURE_16 : Base.h
  • SIGNATURE_32 : Base.h
  • SIGNATURE_64 : Base.h
  • STATIC : Base.h
  • STATIC_ASSERT : Base.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented file members with links to the documentation:

- t -

  • TCSS_PEI_CONFIG_REVISION : TcssPeiConfig.h
  • Thc : ThcConfig.h
  • THC_CONFIG_REVISION : ThcConfig.h
  • THC_MODE : ThcConfig.h
  • THC_PORT_ASSIGNMENT : ThcConfig.h
  • ThcAssignmentNone : ThcConfig.h
  • ThcAssignmentThc0 : ThcConfig.h
  • ThcAssignmentThc1 : ThcConfig.h
  • TRACE_BUFFER_SIZE : TraceHubConfig.h
  • TRACE_HUB_ENABLE_MODE : TraceHubConfig.h
  • TRUE : Base.h
  • TSN_CONFIG_REVISION : TsnConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented file members with links to the documentation:

- u -

  • UNREACHABLE : Base.h
  • USB3_HSIO_CONFIG_REVISION : Usb3HsioConfig.h
  • USB_CONFIG_REVISION : UsbConfig.h
  • USB_OC_MAX_PINS : UsbConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Here is a list of all documented file members with links to the documentation:

- v -

  • VA_ARG : Base.h
  • VA_COPY : Base.h
  • VA_END : Base.h
  • VA_LIST : Base.h
  • VA_START : Base.h
  • VOID : Base.h
  • VTD_CONFIG_REVISION : VtdConfig.h
  • VTD_DXE_CONFIG_REVISION : VtdConfig.h
  • VTD_ENABLE_DMA_BUFFER : VtdConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • AddConfigBlock() : ConfigBlockLib.h
  • CreateConfigBlockTable() : ConfigBlockLib.h
  • GetConfigBlock() : ConfigBlockLib.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- a -

  • AMT_REPORT_ERROR : AmtConfig.h

- b -

  • BASE_LIST : Base.h

- c -

  • CONFIG_BLOCK : ConfigBlock.h
  • CONFIG_BLOCK_HEADER : ConfigBlock.h
  • CONFIG_BLOCK_TABLE_HEADER : ConfigBlock.h

- e -

  • EFI_AP_PROCEDURE : PiMultiPhase.h
  • EFI_AP_PROCEDURE2 : PiMultiPhase.h
  • EFI_EVENT : UefiBaseType.h
  • EFI_GUID : UefiBaseType.h
  • EFI_HANDLE : UefiBaseType.h
  • EFI_IPv4_ADDRESS : UefiBaseType.h
  • EFI_IPv6_ADDRESS : UefiBaseType.h
  • EFI_LBA : UefiBaseType.h
  • EFI_MM_RESERVED_MMRAM_REGION : PiMultiPhase.h
  • EFI_PEI_MP_SERVICES_ENABLEDISABLEAP : MpServices.h
  • EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS : MpServices.h
  • EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO : MpServices.h
  • EFI_PEI_MP_SERVICES_STARTUP_ALL_APS : MpServices.h
  • EFI_PEI_MP_SERVICES_STARTUP_THIS_AP : MpServices.h
  • EFI_PEI_MP_SERVICES_SWITCH_BSP : MpServices.h
  • EFI_PEI_MP_SERVICES_WHOAMI : MpServices.h
  • EFI_PHYSICAL_ADDRESS : UefiBaseType.h
  • EFI_RESOURCE_ATTRIBUTE_TYPE : PiHob.h
  • EFI_RESOURCE_TYPE : PiHob.h
  • EFI_STATUS : UefiBaseType.h
  • EFI_TPL : UefiBaseType.h
  • EFI_VIRTUAL_ADDRESS : UefiBaseType.h

- g -

  • GPIO_GROUP : GpioConfig.h
  • GPIO_PAD : GpioConfig.h

- i -

  • ITBT_GENERIC_CONFIG : PeiITbtGenericStructure.h
  • ITBT_ROOTPORT_CONFIG : PeiITbtGenericStructure.h

- l -

  • LIST_ENTRY : Base.h

- p -

  • PEI_POLICY_INIT : PeiSiDefaultPolicy.h
  • PEI_PREMEM_POLICY_INIT : PeiPreMemSiDefaultPolicy.h

- v -

  • VA_LIST : Base.h
  • VTD_ENABLE_DMA_BUFFER : VtdConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- a -

  • AMT_ERROR_MSG_ID : AmtConfig.h

- c -

  • CNVI_BT_INTERFACE : CnviConfig.h
  • CNVI_MODE : CnviConfig.h

- f -

  • FIVR_RAIL_SX_STATE : FivrConfig.h

- g -

  • GPIO_DIRECTION : GpioConfig.h
  • GPIO_ELECTRICAL_CONFIG : GpioConfig.h
  • GPIO_HARDWARE_DEFAULT : GpioConfig.h
  • GPIO_HOSTSW_OWN : GpioConfig.h
  • GPIO_INT_CONFIG : GpioConfig.h
  • GPIO_LOCK_CONFIG : GpioConfig.h
  • GPIO_OTHER_CONFIG : GpioConfig.h
  • GPIO_OUTPUT_STATE : GpioConfig.h
  • GPIO_PAD_MODE : GpioConfig.h
  • GPIO_RESET_CONFIG : GpioConfig.h

- p -

  • PCH_INT_PIN : InterruptConfig.h
  • PCH_PCIE_ASPM_CONTROL : PchPcieRpConfig.h
  • PCH_PCIE_CLOCK_USAGE : PchPcieRpConfig.h
  • PCH_PCIE_L1SUBSTATES_CONTROL : PchPcieRpConfig.h
  • PCH_RESERVED_PAGE_ROUTE : PchGeneralConfig.h
  • PCH_SLP_S4_MIN_ASSERT : PmConfig.h
  • PCIE_FORM_FACTOR : PcieConfig.h
  • PCIE_LINK_EQ_METHOD : PcieConfig.h
  • PCIE_LINK_EQ_MODE : PcieConfig.h

- s -

  • SERIAL_IO_CS_POLARITY : SerialIoDevices.h
  • SERIAL_IO_I2C_MODE : SerialIoDevices.h
  • SERIAL_IO_I3C_MODE : SerialIoDevices.h
  • SERIAL_IO_SPI_MODE : SerialIoDevices.h
  • SERIAL_IO_UART_MODE : SerialIoDevices.h
  • SERIAL_IO_UART_PG : SerialIoDevices.h

- t -

  • THC_MODE : ThcConfig.h
  • THC_PORT_ASSIGNMENT : ThcConfig.h
  • TRACE_BUFFER_SIZE : TraceHubConfig.h
  • TRACE_HUB_ENABLE_MODE : TraceHubConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- g -

  • GpioDirDefault : GpioConfig.h
  • GpioDirIn : GpioConfig.h
  • GpioDirInInv : GpioConfig.h
  • GpioDirInInvOut : GpioConfig.h
  • GpioDirInOut : GpioConfig.h
  • GpioDirNone : GpioConfig.h
  • GpioDirOut : GpioConfig.h
  • GpioDswReset : GpioConfig.h
  • GpioHardwareDefault : GpioConfig.h
  • GpioHostDeepReset : GpioConfig.h
  • GpioHostOwnAcpi : GpioConfig.h
  • GpioHostOwnDefault : GpioConfig.h
  • GpioHostOwnGpio : GpioConfig.h
  • GpioIntApic : GpioConfig.h
  • GpioIntBothEdge : GpioConfig.h
  • GpioIntDefault : GpioConfig.h
  • GpioIntDis : GpioConfig.h
  • GpioIntEdge : GpioConfig.h
  • GpioIntLevel : GpioConfig.h
  • GpioIntLvlEdgDis : GpioConfig.h
  • GpioIntNmi : GpioConfig.h
  • GpioIntSci : GpioConfig.h
  • GpioIntSmi : GpioConfig.h
  • GpioLockDefault : GpioConfig.h
  • GpioNoTolerance1v8 : GpioConfig.h
  • GpioOutDefault : GpioConfig.h
  • GpioOutHigh : GpioConfig.h
  • GpioOutLow : GpioConfig.h
  • GpioOutputStateLock : GpioConfig.h
  • GpioPadConfigLock : GpioConfig.h
  • GpioPlatformReset : GpioConfig.h
  • GpioResetDefault : GpioConfig.h
  • GpioResumeReset : GpioConfig.h
  • GpioRxRaw1Default : GpioConfig.h
  • GpioRxRaw1Dis : GpioConfig.h
  • GpioRxRaw1En : GpioConfig.h
  • GpioTermDefault : GpioConfig.h
  • GpioTermNative : GpioConfig.h
  • GpioTermNone : GpioConfig.h
  • GpioTermWpd20K : GpioConfig.h
  • GpioTermWpd5K : GpioConfig.h
  • GpioTermWpu1K : GpioConfig.h
  • GpioTermWpu1K2K : GpioConfig.h
  • GpioTermWpu20K : GpioConfig.h
  • GpioTermWpu2K : GpioConfig.h
  • GpioTermWpu5K : GpioConfig.h
  • GpioTolerance1v8 : GpioConfig.h

- h -

  • HidOverI2c : ThcConfig.h
  • HidOverSpi : ThcConfig.h

- p -

  • PchClockUsageCpuPcie0 : PchPcieRpConfig.h
  • PchClockUsageUnspecified : PchPcieRpConfig.h
  • PchNoInt : InterruptConfig.h
  • PchReservedPageToLpc : PchGeneralConfig.h
  • PchReservedPageToPcie : PchGeneralConfig.h
  • PchSlpS4PchTime : PmConfig.h
  • PcieLinkEqCoefficientMode : PcieConfig.h
  • PcieLinkEqPresetMode : PcieConfig.h
  • PcieLinkFixedEq : PcieConfig.h
  • PcieLinkHardwareEq : PcieConfig.h

- s -

  • SerialIoUartPgAuto : SerialIoDevices.h
  • SerialIoUartPgDisabled : SerialIoDevices.h
  • SerialIoUartPgEnabled : SerialIoDevices.h

- t -

  • Thc : ThcConfig.h
  • ThcAssignmentNone : ThcConfig.h
  • ThcAssignmentThc0 : ThcConfig.h
  • ThcAssignmentThc1 : ThcConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide

- _ -

  • _BASE_INT_SIZE_OF : Base.h
  • _CONCATENATE : Base.h
  • _INT_SIZE_OF : Base.h

- a -

  • ABS : Base.h
  • ADDRESS_IS_ALIGNED : Base.h
  • ALIGN_POINTER : Base.h
  • ALIGN_VALUE : Base.h
  • ALIGN_VALUE_ADDEND : Base.h
  • ALIGN_VARIABLE : Base.h
  • ALIGNOF : Base.h
  • ANALYZER_NORETURN : Base.h
  • ANALYZER_UNREACHABLE : Base.h
  • ARRAY_SIZE : Base.h
  • ASM_PFX : Base.h

- b -

  • B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK : GpioConfig.h
  • B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK : GpioConfig.h
  • B_GPIO_INT_CONFIG_INT_SOURCE_MASK : GpioConfig.h
  • B_GPIO_INT_CONFIG_INT_TYPE_MASK : GpioConfig.h
  • B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK : GpioConfig.h
  • B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK : GpioConfig.h
  • B_GPIO_OTHER_CONFIG_RXRAW_MASK : GpioConfig.h
  • BASE_ARG : Base.h
  • BASE_CR : Base.h
  • BCLK_CONFIG_REVISION : PmConfig.h

- c -

  • CNVI_CONFIG_REVISION : CnviConfig.h
  • CNVI_PREMEM_CONFIG_REVISION : CnviConfig.h
  • CONST : Base.h
  • CPU_POWER_MGMT_VR_CONFIG_REVISION : CpuPowerMgmtVrConfig.h

- d -

  • DXE_ERROR : PiMultiPhase.h

- e -

  • EFI_AUTH_STATUS_PLATFORM_OVERRIDE : PiMultiPhase.h
  • EFI_CONNECTION_FIN : UefiBaseType.h
  • EFI_HOB_HANDOFF_TABLE_VERSION : PiHob.h
  • EFI_IMAGE_MACHINE_AARCH64 : UefiBaseType.h
  • EFI_IMAGE_MACHINE_ARMTHUMB_MIXED : UefiBaseType.h
  • EFI_IMAGE_MACHINE_EBC : UefiBaseType.h
  • EFI_IMAGE_MACHINE_IA32 : UefiBaseType.h
  • EFI_IMAGE_MACHINE_IA64 : UefiBaseType.h
  • EFI_IMAGE_MACHINE_LOONGARCH32 : UefiBaseType.h
  • EFI_IMAGE_MACHINE_RISCV32 : UefiBaseType.h
  • EFI_IMAGE_MACHINE_X64 : UefiBaseType.h
  • EFI_INTERRUPT_PENDING : PiMultiPhase.h
  • EFI_MMRAM_OPEN : PiMultiPhase.h
  • EFI_NETWORK_UNREACHABLE : UefiBaseType.h
  • EFI_NOT_AVAILABLE_YET : PiMultiPhase.h
  • EFI_PAGES_TO_SIZE : UefiBaseType.h
  • EFI_REQUEST_UNLOAD_IMAGE : PiMultiPhase.h
  • EFI_SIZE_TO_PAGES : UefiBaseType.h
  • EFI_SUCCESS : UefiBaseType.h
  • EFIERR : UefiBaseType.h
  • ENCODE_ERROR : Base.h
  • ENCODE_WARNING : Base.h

- f -

  • FALSE : Base.h
  • FSP_ERROR_INFO_HOB_GUID : FspErrorInfo.h
  • FSPM_ARCH_CONFIG_GUID : FspmArchConfigPpi.h

- g -

  • GLOBAL_REMOVE_IF_UNREFERENCED : Base.h

- h -

  • HDAUDIO_CONFIG_REVISION : HdAudioConfig.h
  • HDAUDIO_DXE_CONFIG_REVISION : HdAudioConfig.h
  • HDAUDIO_PREMEM_CONFIG_REVISION : HdAudioConfig.h
  • HDAUDIO_VERB_TABLE_INIT : HdAudioConfig.h
  • HDAUDIO_VERB_TABLE_VIDDID : HdAudioConfig.h
  • HOST_BRIDGE_PEI_CONFIG_REVISION : HostBridgeConfig.h
  • HOST_BRIDGE_PREMEM_CONFIG_REVISION : HostBridgeConfig.h
  • HYBRID_GRAPHICS_CONFIG_REVISION : HybridGraphicsConfig.h

- i -

  • IN : Base.h
  • IS_ALIGNED : Base.h
  • IS_POW2 : Base.h
  • ISH_CONFIG_REVISION : IshConfig.h
  • ISH_I3C_CONFIG_REVISION : IshConfig.h
  • ISH_PREMEM_CONFIG_REVISION : IshConfig.h

- m -

  • MAX : Base.h
  • MAX_INT8 : Base.h
  • MAX_NUM_VRS : CpuPowerMgmtVrConfig.h
  • MIN : Base.h
  • MIN_INT8 : Base.h

- n -

  • NORETURN : Base.h
  • NULL : Base.h

- o -

  • OFFSET_OF : Base.h
  • OPTIONAL : Base.h
  • OUT : Base.h

- p -

  • PcdFspAreaBaseAddress : FspFixedPcds.h
  • PcdFspImageIdString : FspFixedPcds.h
  • PcdFspReservedBufferSize : FspFixedPcds.h
  • PcdGlobalDataPointerAddress : FspFixedPcds.h
  • PcdSiliconInitVersionBuild : FspFixedPcds.h
  • PcdSiliconInitVersionMajor : FspFixedPcds.h
  • PcdSiliconInitVersionMinor : FspFixedPcds.h
  • PcdSiliconInitVersionRevision : FspFixedPcds.h
  • PcdTemporaryRamBase : FspFixedPcds.h
  • PcdTemporaryRamSize : FspFixedPcds.h
  • PCH_ESPI_CONFIG_REVISION : EspiConfig.h
  • PCH_GENERAL_CONFIG_REVISION : PchGeneralConfig.h
  • PCH_GENERAL_PREMEM_CONFIG_REVISION : PchGeneralConfig.h
  • PCH_HSIO_CONFIG_REVISION : HsioConfig.h
  • PCH_HSIO_PREMEM_CONFIG_REVISION : HsioConfig.h
  • PCH_MAX_DEVICE_INTERRUPT_CONFIG : InterruptConfig.h
  • PCH_MAX_ITSS_IPC_REGS : InterruptConfig.h
  • PCH_MAX_ITSS_IRQ_NUM : InterruptConfig.h
  • PCH_MAX_PXRC_CONFIG : InterruptConfig.h
  • PCH_PCIE_CONFIG_REVISION : PchPcieRpConfig.h
  • PCH_PCIE_RP_PREMEM_CONFIG_REVISION : PchPcieRpConfig.h
  • PCH_PM_CONFIG_REVISION : PmConfig.h
  • PCIE_RP_DXE_CONFIG_REVISION : PchPcieRpConfig.h
  • PEI_ITBT_CONFIG_REVISION : PeiITbtConfig.h
  • PI_ENCODE_ERROR : PiMultiPhase.h
  • PI_ENCODE_WARNING : PiMultiPhase.h

- r -

  • RETURN_ABORTED : Base.h
  • RETURN_ACCESS_DENIED : Base.h
  • RETURN_ADDRESS : Base.h
  • RETURN_ALREADY_STARTED : Base.h
  • RETURN_BAD_BUFFER_SIZE : Base.h
  • RETURN_BUFFER_TOO_SMALL : Base.h
  • RETURN_COMPROMISED_DATA : Base.h
  • RETURN_CRC_ERROR : Base.h
  • RETURN_DEVICE_ERROR : Base.h
  • RETURN_END_OF_FILE : Base.h
  • RETURN_END_OF_MEDIA : Base.h
  • RETURN_ERROR : Base.h
  • RETURN_HTTP_ERROR : Base.h
  • RETURN_ICMP_ERROR : Base.h
  • RETURN_INCOMPATIBLE_VERSION : Base.h
  • RETURN_INVALID_LANGUAGE : Base.h
  • RETURN_INVALID_PARAMETER : Base.h
  • RETURN_LOAD_ERROR : Base.h
  • RETURN_MEDIA_CHANGED : Base.h
  • RETURN_NO_MAPPING : Base.h
  • RETURN_NO_MEDIA : Base.h
  • RETURN_NO_RESPONSE : Base.h
  • RETURN_NOT_FOUND : Base.h
  • RETURN_NOT_READY : Base.h
  • RETURN_NOT_STARTED : Base.h
  • RETURN_OUT_OF_RESOURCES : Base.h
  • RETURN_PROTOCOL_ERROR : Base.h
  • RETURN_SECURITY_VIOLATION : Base.h
  • RETURN_SUCCESS : Base.h
  • RETURN_TFTP_ERROR : Base.h
  • RETURN_TIMEOUT : Base.h
  • RETURN_UNSUPPORTED : Base.h
  • RETURN_VOLUME_CORRUPTED : Base.h
  • RETURN_VOLUME_FULL : Base.h
  • RETURN_WARN_BUFFER_TOO_SMALL : Base.h
  • RETURN_WARN_DELETE_FAILURE : Base.h
  • RETURN_WARN_FILE_SYSTEM : Base.h
  • RETURN_WARN_STALE_DATA : Base.h
  • RETURN_WARN_UNKNOWN_GLYPH : Base.h
  • RETURN_WARN_WRITE_FAILURE : Base.h
  • RETURN_WRITE_PROTECTED : Base.h
  • RETURNS_TWICE : Base.h

- s -

  • SERIAL_IO_CONFIG_REVISION : SerialIoConfig.h
  • SI_POLICY_REVISION : SiPolicyStruct.h
  • SI_PREMEM_POLICY_REVISION : SiPolicyStruct.h
  • SIGNATURE_16 : Base.h
  • SIGNATURE_32 : Base.h
  • SIGNATURE_64 : Base.h
  • STATIC : Base.h
  • STATIC_ASSERT : Base.h

- t -

  • TCSS_PEI_CONFIG_REVISION : TcssPeiConfig.h
  • THC_CONFIG_REVISION : ThcConfig.h
  • TRUE : Base.h
  • TSN_CONFIG_REVISION : TsnConfig.h

- u -

  • UNREACHABLE : Base.h
  • USB3_HSIO_CONFIG_REVISION : Usb3HsioConfig.h
  • USB_CONFIG_REVISION : UsbConfig.h
  • USB_OC_MAX_PINS : UsbConfig.h

- v -

  • VA_ARG : Base.h
  • VA_COPY : Base.h
  • VA_END : Base.h
  • VA_START : Base.h
  • VOID : Base.h
  • VTD_CONFIG_REVISION : VtdConfig.h
  • VTD_DXE_CONFIG_REVISION : VtdConfig.h
Generated on Mon Dec 29 2025 02:15:53 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ClientOneSiliconPkg -> Edk2 Relation

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg

ClientOneSiliconPkg → Edk2 Relation

File in Intel/ClientOneSiliconPkg | Includes file in Edk2
Include / ConfigBlock.h | MdePkg / Include / Uefi / UefiBaseType.h
Include / ConfigBlock.h | MdePkg / Include / Pi / PiHob.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Gbe Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Gbe
Gbe Directory Reference

Files

file GbeConfig.h [code]
Gigabit Ethernet policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Rst Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Rst
Rst Directory Reference
Directory dependency graph for Rst:

Files

file RstConfig.h [code]
Rst policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Include -> ConfigBlock Relation

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include

Include → ConfigBlock Relation

File in Intel/ClientOneSiliconPkg/Include | Includes file in Intel/ClientOneSiliconPkg/Include/ConfigBlock
SiPolicyStruct.h | SiConfig.h
SiPolicyStruct.h | SiPreMemConfig.h
ConfigBlock / Tcss / TcssPeiConfig.h | Usb / UsbConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Include -> Edk2 Relation

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include

Include → Edk2 Relation

File in Intel/ClientOneSiliconPkg/Include | Includes file in Edk2
ConfigBlock.h | MdePkg / Include / Pi / PiHob.h
ConfigBlock.h | MdePkg / Include / Uefi / UefiBaseType.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Library Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Library Directory Reference

Files

file ConfigBlockLib.h [code]
Header file for Config Block Lib implementation.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ConfigBlock -> Library Relation

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock

ConfigBlock → Library Relation

File in Intel/ClientOneSiliconPkg/Include/ConfigBlock | Includes file in Intel/ClientOneSiliconPkg/Include/Library
Amt / AmtConfig.h | ConfigBlockLib.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Hda Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hda
Hda Directory Reference
Directory dependency graph for Hda:

Files

file HdAudioConfig.h [code]
HDAUDIO policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Fivr Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Fivr
Fivr Directory Reference

Files

file FivrConfig.h [code]
PCH FIVR policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PchPcieRp Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PcieRp
  • PchPcieRp
PchPcieRp Directory Reference
Directory dependency graph for PchPcieRp:

Files

file PchPcieRpConfig.h [code]
PCH Pcie root port policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SerialIo Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • SerialIo
SerialIo Directory Reference
Directory dependency graph for SerialIo:

Files

file SerialIoConfig.h [code]
Serial IO policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Rtc Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Rtc
Rtc Directory Reference
Directory dependency graph for Rtc:

Files

file RtcConfig.h [code]
RTC policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: SystemAgent Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
SystemAgent Directory Reference
Generated on Mon Dec 29 2025 02:15:52 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Uefi Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Edk2
  • MdePkg
  • Include
  • Uefi
Uefi Directory Reference
Directory dependency graph for Uefi:

Files

file UefiBaseType.h [code]
Defines data types and constants introduced in UEFI.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Amt -> Library Relation

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Amt

Amt → Library Relation

File in Intel/ClientOneSiliconPkg/Include/ConfigBlock/Amt | Includes file in Intel/ClientOneSiliconPkg/Include/Library
AmtConfig.h | ConfigBlockLib.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Thermal Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Thermal
Thermal Directory Reference

Files

file ThermalConfig.h [code]
Thermal policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ConfigBlock Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • ConfigBlock
ConfigBlock Directory Reference

Files

file PchGeneralConfig.h [code]
PCH General policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Spi Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Spi
Spi Directory Reference

Files

file FlashProtectionConfig.h [code]
FlashProtection policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Ish Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ish
Ish Directory Reference

Files

file IshConfig.h [code]
ISH policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ConfigBlock Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • ConfigBlock
ConfigBlock Directory Reference

Files

file SaMiscPeiPreMemConfig.h [code]
Policy details for miscellaneous configuration in System Agent.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: MeteorLakeFspBinPkg Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • MeteorLakeFspBinPkg
MeteorLakeFspBinPkg Directory Reference

Directories

Generated on Mon Dec 29 2025 02:15:52 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Sata Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Sata
Sata Directory Reference
Directory dependency graph for Sata:

Files

file SataConfig.h [code]
Sata policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Gna Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Gna
Gna Directory Reference

Files

file GnaConfig.h [code]
Policy definition for GNA Config Block.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Include Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
Include Directory Reference

Directories

Generated on Mon Dec 29 2025 02:15:52 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Thc Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Thc
Thc Directory Reference

Files

file ThcConfig.h [code]
Touch Host Controller policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Guid Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • Guid
Guid Directory Reference

Files

file FspErrorInfo.h [code]
FSP Error Information HOB to describe errors inside FSP that bootloader may take some actions to handle those error scenarios.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Me Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Me
Me Directory Reference
Directory dependency graph for Me:

Files

file MePeiConfig.h [code]
ME config block for PEI phase.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Dci Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Dci
Dci Directory Reference
Directory dependency graph for Dci:

Files

file DciConfig.h [code]
Dci policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Hsio Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hsio
Hsio Directory Reference

Files

file | HsioConfig.h [code]
HSIO policy.
file | HsioPcieConfig.h [code]
HSIO pcie policy.
file | HsioSataConfig.h [code]
Hsio Sata policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Ppi Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Product
  • MeteorLake
  • Include
  • Ppi
Ppi Directory Reference
Directory dependency graph for Ppi:

Files

file SiPolicy.h [code]
Silicon Policy PPI is used for specifying platform related Intel silicon information and policy setting.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Edk2 Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Edk2
Edk2 Directory Reference
Generated on Mon Dec 29 2025 02:15:52 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Ppi Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Edk2
  • MdePkg
  • Include
  • Ppi
Ppi Directory Reference

Files

file MpServices.h [code]
This file declares UEFI PI Multi-processor PPI.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Pi Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Edk2
  • MdePkg
  • Include
  • Pi
Pi Directory Reference

Files

file | PiHob.h [code]
HOB related definitions in PI.
file | PiMultiPhase.h [code]
Include file matches things in PI for multiple module types.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Product -> Include Relation

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Product

Product → Include Relation

File in Intel/ClientOneSiliconPkg/Product | Includes file in Intel/ClientOneSiliconPkg/Include
MeteorLake / Include / Ppi / SiPolicy.h | ConfigBlock / Amt / AmtConfig.h
MeteorLake / Include / Ppi / SiPolicy.h | ConfigBlock / VoltageRegulator / CpuPowerMgmtVrConfig.h
MeteorLake / Include / Ppi / SiPolicy.h | ConfigBlock / Gna / GnaConfig.h
MeteorLake / Include / Ppi / SiPolicy.h | ConfigBlock / HostBridge / Ver2 / HostBridgeConfig.h
MeteorLake / Include / Ppi / SiPolicy.h | ConfigBlock / HybridGraphics / HybridGraphicsConfig.h
MeteorLake / Include / Ppi / SiPolicy.h | ConfigBlock / Me / MePeiConfig.h
MeteorLake / Include / Ppi / SiPolicy.h | ConfigBlock / Overclocking / OverclockingConfig.h
MeteorLake / Include / Ppi / SiPolicy.h | SiPolicyStruct.h
MeteorLake / Include / Ppi / SiPolicy.h | ConfigBlock / TraceHub / TraceHubConfig.h
MeteorLake / Include / Ppi / SiPolicy.h | ConfigBlock / Vtd / VtdConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Product -> SystemAgent Relation

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Product

Product → SystemAgent Relation

File in Intel/ClientOneSiliconPkg/Product | Includes file in Intel/ClientOneSiliconPkg/SystemAgent
MeteorLake / Include / Ppi / SiPolicy.h | Include / ConfigBlock / SaMiscPeiPreMemConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: MeteorLake -> Include Relation

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Product
  • MeteorLake

MeteorLake → Include Relation

File in Intel/ClientOneSiliconPkg/Product/MeteorLake | Includes file in Intel/ClientOneSiliconPkg/Include
Include / Ppi / SiPolicy.h | SiPolicyStruct.h
Include / Ppi / SiPolicy.h | ConfigBlock / Me / MePeiConfig.h
Include / Ppi / SiPolicy.h | ConfigBlock / Amt / AmtConfig.h
Include / Ppi / SiPolicy.h | ConfigBlock / VoltageRegulator / CpuPowerMgmtVrConfig.h
Include / Ppi / SiPolicy.h | ConfigBlock / Overclocking / OverclockingConfig.h
Include / Ppi / SiPolicy.h | ConfigBlock / Vtd / VtdConfig.h
Include / Ppi / SiPolicy.h | ConfigBlock / Gna / GnaConfig.h
Include / Ppi / SiPolicy.h | ConfigBlock / HybridGraphics / HybridGraphicsConfig.h
Include / Ppi / SiPolicy.h | ConfigBlock / TraceHub / TraceHubConfig.h
Include / Ppi / SiPolicy.h | ConfigBlock / HostBridge / Ver2 / HostBridgeConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: MeteorLake -> SystemAgent Relation

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Product
  • MeteorLake

MeteorLake → SystemAgent Relation

File in Intel/ClientOneSiliconPkg/Product/MeteorLake | Includes file in Intel/ClientOneSiliconPkg/SystemAgent
Include / Ppi / SiPolicy.h | Include / ConfigBlock / SaMiscPeiPreMemConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Include -> Include Relation

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Product
  • MeteorLake
  • Include

Include → Include Relation

File in Intel/ClientOneSiliconPkg/Product/MeteorLake/Include | Includes file in Intel/ClientOneSiliconPkg/Include
Ppi / SiPolicy.h | SiPolicyStruct.h
Ppi / SiPolicy.h | ConfigBlock / Me / MePeiConfig.h
Ppi / SiPolicy.h | ConfigBlock / Amt / AmtConfig.h
Ppi / SiPolicy.h | ConfigBlock / VoltageRegulator / CpuPowerMgmtVrConfig.h
Ppi / SiPolicy.h | ConfigBlock / Overclocking / OverclockingConfig.h
Ppi / SiPolicy.h | ConfigBlock / Vtd / VtdConfig.h
Ppi / SiPolicy.h | ConfigBlock / Gna / GnaConfig.h
Ppi / SiPolicy.h | ConfigBlock / HybridGraphics / HybridGraphicsConfig.h
Ppi / SiPolicy.h | ConfigBlock / TraceHub / TraceHubConfig.h
Ppi / SiPolicy.h | ConfigBlock / HostBridge / Ver2 / HostBridgeConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Include -> SystemAgent Relation

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Product
  • MeteorLake
  • Include

Include → SystemAgent Relation

File in Intel/ClientOneSiliconPkg/Product/MeteorLake/Include | Includes file in Intel/ClientOneSiliconPkg/SystemAgent
Ppi / SiPolicy.h | Include / ConfigBlock / SaMiscPeiPreMemConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Ppi -> Include Relation

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Product
  • MeteorLake
  • Include
  • Ppi

Ppi → Include Relation

File in Intel/ClientOneSiliconPkg/Product/MeteorLake/Include/Ppi | Includes file in Intel/ClientOneSiliconPkg/Include
SiPolicy.h | ConfigBlock / Amt / AmtConfig.h
SiPolicy.h | ConfigBlock / VoltageRegulator / CpuPowerMgmtVrConfig.h
SiPolicy.h | ConfigBlock / Gna / GnaConfig.h
SiPolicy.h | ConfigBlock / HostBridge / Ver2 / HostBridgeConfig.h
SiPolicy.h | ConfigBlock / HybridGraphics / HybridGraphicsConfig.h
SiPolicy.h | ConfigBlock / Me / MePeiConfig.h
SiPolicy.h | ConfigBlock / Overclocking / OverclockingConfig.h
SiPolicy.h | SiPolicyStruct.h
SiPolicy.h | ConfigBlock / TraceHub / TraceHubConfig.h
SiPolicy.h | ConfigBlock / Vtd / VtdConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Ppi -> SystemAgent Relation

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Product
  • MeteorLake
  • Include
  • Ppi

Ppi → SystemAgent Relation

File in Intel/ClientOneSiliconPkg/Product/MeteorLake/Include/Ppi | Includes file in Intel/ClientOneSiliconPkg/SystemAgent
SiPolicy.h | Include / ConfigBlock / SaMiscPeiPreMemConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Tcss -> Usb Relation

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tcss

Tcss → Usb Relation

File in Intel/ClientOneSiliconPkg/Include/ConfigBlock/Tcss | Includes file in Intel/ClientOneSiliconPkg/Include/ConfigBlock/Usb
TcssPeiConfig.h | UsbConfig.h


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Tbt Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tbt
Tbt Directory Reference
Directory dependency graph for Tbt:

Files

file PeiITbtConfig.h [code]
Header file for TBT PEI Policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Amt Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Amt
Amt Directory Reference
Directory dependency graph for Amt:

Files

file AmtConfig.h [code]
AMT Config Block for PEI/DXE phase.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Smbus Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Smbus
Smbus Directory Reference

Files

file SmbusConfig.h [code]
Smbus policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ClientOneSiliconPkg Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
ClientOneSiliconPkg Directory Reference
Directory dependency graph for ClientOneSiliconPkg:

Directories

directory | Pch
directory | Product
directory | SystemAgent


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Include Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Product
  • MeteorLake
  • Include
Include Directory Reference
Directory dependency graph for Include:

Directories

Generated on Mon Dec 29 2025 02:15:52 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: MeteorLake Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Product
  • MeteorLake
MeteorLake Directory Reference
Directory dependency graph for MeteorLake:


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Tcss Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tcss
Tcss Directory Reference
Directory dependency graph for Tcss:

Files

file | TcssPeiConfig.h [code]
TCSS PEI policy.
file | TcssPeiPreMemConfig.h [code]
TCSS PEI PreMem policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Usb Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Usb
Usb Directory Reference

Files

file | Usb2PhyConfig.h [code]
USB2 PHY configuration policy.
file | Usb3HsioConfig.h [code]
USB3 Mod PHY configuration policy.
file | UsbConfig.h [code]
Common USB policy shared between PCH and CPU Contains general features settings for xHCI and xDCI.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Pch Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Pch
Pch Directory Reference
Generated on Mon Dec 29 2025 02:15:52 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Product Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Product
Product Directory Reference
Directory dependency graph for Product:


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Include Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
Include Directory Reference

Directories

Generated on Mon Dec 29 2025 02:15:52 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Telemetry Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Telemetry
Telemetry Directory Reference
Directory dependency graph for Telemetry:

Files

file TelemetryPeiConfig.h [code]
Configurations for Telemetry.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Intel Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
Intel Directory Reference
Directory dependency graph for Intel:


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PchDmi Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PchDmi
PchDmi Directory Reference

Files

file PchDmiConfig.h [code]
DMI policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Ieh Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ieh
Ieh Directory Reference
Directory dependency graph for Ieh:

Files

file IehConfig.h [code]
Integrated Error Handler policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: HostBridge Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HostBridge
HostBridge Directory Reference
Directory dependency graph for HostBridge:

Directories

Generated on Mon Dec 29 2025 02:15:52 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Include Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
Include Directory Reference
Directory dependency graph for Include:

Directories

Files

file | ConfigBlock.h [code]
Header file for Config Block Lib implementation.
file | PeiITbtGenericStructure.h [code]
ITBT Policy definition to be referred in both PEI and DXE phase.
file | SerialIoDevices.h [code]
Serial IO policy.
file | SiPolicyStruct.h [code]
Intel reference code configuration policies.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Ppi Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Ppi Directory Reference

Files

file | FspmArchConfigPpi.h [code]
Header file for FSP-M Arch Config PPI.
file | PeiPreMemSiDefaultPolicy.h [code]
This file defines the function to initialize default silicon policy PPI.
file | PeiSiDefaultPolicy.h [code]
This file defines the function to initialize default silicon policy PPI.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: P2sb Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • P2sb
P2sb Directory Reference

Files

file P2sbConfig.h [code]
P2sb policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: TraceHub Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • TraceHub
TraceHub Directory Reference
Directory dependency graph for TraceHub:

Files

file TraceHubConfig.h [code]
Configurations for TraceHub.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Ver2 Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HostBridge
  • Ver2
Ver2 Directory Reference
Directory dependency graph for Ver2:

Files

file HostBridgeConfig.h [code]
Configurations for HostBridge.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Cnvi Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Cnvi
Cnvi Directory Reference
Directory dependency graph for Cnvi:

Files

file CnviConfig.h [code]
CNVi policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Include Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • MeteorLakeFspBinPkg
  • Include
Include Directory Reference

Files

file | GpioConfig.h [code]
Header file for GpioConfig structure used by GPIO library.
file | GpioSampleDef.h [code]
Copyright (c) 2015 - 2017, Intel Corporation.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Vmd Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Vmd
Vmd Directory Reference
Directory dependency graph for Vmd:

Files

file VmdPeiConfig.h [code]
VMD PEI policy VMD Config Block.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: VoltageRegulator Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • VoltageRegulator
VoltageRegulator Directory Reference

Files

file CpuPowerMgmtVrConfig.h [code]
CPU Power Management VR Config Block.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: DoxygenInternalOnly Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • MeteorLakeFspBinPkg
  • DoxygenInternalOnly
DoxygenInternalOnly Directory Reference

Files

file FspFixedPcds.h [code]
This file lists all FixedAtBuild PCDs referenced in FSP integration guide.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Vtd Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Vtd
Vtd Directory Reference

Files

file VtdConfig.h [code]
VT-d policy definitions.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: PcieRp Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PcieRp
PcieRp Directory Reference
Directory dependency graph for PcieRp:

Directories

Files

file | PcieConfig.h [code]
PCIe Config Block.
file | PciePreMemConfig.h [code]
PCIe Config Block PreMem.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Tsn Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tsn
Tsn Directory Reference
Directory dependency graph for Tsn:

Files

file TsnConfig.h [code]
TSN Config policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: HybridGraphics Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HybridGraphics
HybridGraphics Directory Reference

Files

file HybridGraphicsConfig.h [code]
Hybrid Graphics policy definitions.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: ConfigBlock Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
ConfigBlock Directory Reference
Directory dependency graph for ConfigBlock:

Directories

directory HostBridge

Files

file | SiConfig.h [code]
Si Config Block.
file | SiPreMemConfig.h [code]
Si Config Block PreMem.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Pmc Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Pmc
Pmc Directory Reference
Directory dependency graph for Pmc:

Files

file | AdrConfig.h [code]
ADR policy.
file | PmConfig.h [code]
Power Management policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Overclocking Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Overclocking
Overclocking Directory Reference

Files

file OverclockingConfig.h [code]
Overclocking Config Block.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: MdePkg Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Edk2
  • MdePkg
MdePkg Directory Reference
Directory dependency graph for MdePkg:

Directories

Generated on Mon Dec 29 2025 02:15:52 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Espi Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Espi
Espi Directory Reference

Files

file | EspiConfig.h [code]
Espi policy.
file | LpcConfig.h [code]
Lpc policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Itss Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Itss
Itss Directory Reference
Directory dependency graph for Itss:

Files

file | InterruptConfig.h [code]
Interrupt policy.
file | IoApicConfig.h [code]
IoApic policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Include Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Edk2
  • MdePkg
  • Include
Include Directory Reference
Directory dependency graph for Include:

Directories

Files

file Base.h [code]
Root include file for Mde Package Base type modules.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Ipu Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ipu
Ipu Directory Reference
Directory dependency graph for Ipu:

Files

file IpuPreMemConfig.h [code]
IPU policy definitions.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Wdt Directory Reference

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Wdt
Wdt Directory Reference

Files

file WatchDogConfig.h [code]
WatchDog policy.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Graph Legend

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Graph Legend

This page explains how to interpret the graphs that are generated by doxygen.

Consider the following example:

/*! Invisible class because of truncation */
class Invisible { };
/*! Truncated class, inheritance relation is hidden */
class Truncated : public Invisible { };
/* Class not documented with doxygen comments */
class Undocumented { };
/*! Class that is inherited using public inheritance */
class PublicBase : public Truncated { };
/*! A template class */
template<class T> class Templ { };
/*! Class that is inherited using protected inheritance */
class ProtectedBase { };
/*! Class that is inherited using private inheritance */
class PrivateBase { };
/*! Class that is used by the Inherited class */
class Used { };
/*! Super class that inherits a number of other classes */
class Inherited : public PublicBase,
protected ProtectedBase,
private PrivateBase,
public Undocumented,
public Templ<int>
{
private:
Used *m_usedClass;
};

This will result in the following graph:

The boxes in the above graph have the following meaning:

  • A filled gray box represents the struct or class for which the graph is generated.
  • A box with a black border denotes a documented struct or class.
  • A box with a gray border denotes an undocumented struct or class.
  • A box with a red border denotes a documented struct or class forwhich not all inheritance/containment relations are shown. A graph is truncated if it does not fit within the specified boundaries.

The arrows have the following meaning:

  • A dark blue arrow is used to visualize a public inheritance relation between two classes.
  • A dark green arrow is used for protected inheritance.
  • A dark red arrow is used for private inheritance.
  • A purple dashed arrow is used if a class is contained or used by another class. The arrow is labelled with the variable(s) through which the pointed class or struct is accessible.
  • A yellow dashed arrow denotes a relation between a template instance and the template class it was instantiated from. The arrow is labelled with the template parameters of the instance.


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Related Pages

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
Related Pages
Here is a list of all related documentation pages:
[detail level 12]
2 Overview |
3 FSP Integration |
▼4 FSP Dispatch Mode |
4.1 Dispatch Mode Policy Init | For the plurality of platform designs, most of the policy options provided by FSP do not need to be modified by the bootloader
4.2 Config Blocks |
4.3 FSP Error Information | In the case of a fatal error occurring during the execution of the FSP, it may not be possible for the FSP to continue
4.4 Dispatch Mode Integration | Dispatch Mode Integration Notes:
▼5 FSP API Mode |
5.1 FSP APIs |
5.2 Reset Return Codes | As per FSP External Architecture Specification version 2.0/2.1/2.2, any reset required in the FSP flow will be reported by returning one of the FSP_STATUS_RESET_REQUIRED* return codes
5.3 UPD Porting Guide | Recommended values for UPDs:
6 Porting Recommendations | Here are some notes and recommendations for adapting an existing boot loader to FSP
7 FSP Output | The FSP builds a series of data structures called Hand-Off-Blocks (HOBs) as it progresses through initializing the silicon
8 POST Codes | The FSP outputs 16-bit POST codes to indicate which API and which module is currently executing
Todo List |


MeteorLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MeteorLake Intel® Firmware Support Package (FSP) Integration Guide
EFI_HOB_FIRMWARE_VOLUME Member List

This is the complete list of members for EFI_HOB_FIRMWARE_VOLUME, including all inherited members.

BaseAddress | EFI_HOB_FIRMWARE_VOLUME
Header | EFI_HOB_FIRMWARE_VOLUME
Length | EFI_HOB_FIRMWARE_VOLUME
Generated on Mon Dec 29 2025 02:15:51 for MeteorLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20