Comet Lake FSP 9.2.30.50

author: Nate DeSimone <nathaniel.l.desimone@intel.com> 2020-04-24 11:50:18 +0300
committer: Nate DeSimone <nathaniel.l.desimone@intel.com> 2020-04-24 12:54:06 +0300
commit: 5453e67a504dc6c2e682b0c20f10af0335f11049 (patch)
tree: 009e15f374cccf8160976d8ecf7b22b40b790307
parent: 5eccfa02a433e2c365d532be42d782d6bb41b427 (diff)
download: FSP-5453e67a504dc6c2e682b0c20f10af0335f11049.tar.xz
18 files changed, 24742 insertions, 0 deletions
diff --git a/CometLakeFspBinPkg/CometLake2/CometLakeFspBinPkg.dec b/CometLakeFspBinPkg/CometLake2/CometLakeFspBinPkg.dec
new file mode 100644
index 0000000..1c0b637
--- /dev/null
+++ b/CometLakeFspBinPkg/CometLake2/CometLakeFspBinPkg.dec
@@ -0,0 +1,29 @@
+## @file
+#  Component description file for CometLake Fsp Bin package.
+#
+# @copyright
+#  Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+# @par Specification
+##
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010005
+  PACKAGE_NAME                   = CometLakeFspBinPkg
+  PACKAGE_GUID                   = 5A536013-A46E-44AD-8B30-738235F77B06
+  PACKAGE_VERSION                = 1.02
+
+[Includes]
+  Include
+
+[Guids]
+  gFspInfoGuid                  = { 0x067e0f25, 0x374f, 0x47c2, { 0x17, 0x92, 0x86, 0xdc, 0xdb, 0xc4, 0x8a, 0xc9 }}
+
+[Ppis]
+  gEfiReadyToInstallPciEnumerationCompleteProtocolGuid    = { 0x84E3F112, 0x3C91, 0x476C, { 0xA0, 0x61, 0xE3, 0x3F, 0xA0, 0x8C, 0xCA, 0xF8 }}
+  gEfiReadyToInstallEventReadyToBootGuid                  = { 0xDB0F224F, 0x0D43, 0x4D77, { 0x86, 0x21, 0x96, 0xBB, 0xD4, 0xAD, 0x5C, 0x91 }}
+  gFspReadyToInstallEventEndOfFirmwareGuid                = { 0xD8D9A0E1, 0xC34E, 0x4FDB, { 0x8C, 0xCF, 0x10, 0x51, 0x5B, 0xE4, 0x76, 0x5D }}
+  gEndOfFspS3NotifyGuid                                   = { 0x4AF40FFA, 0x60CB, 0x4A9F, { 0xA0, 0xAA, 0x0A, 0x66, 0xC0, 0x13, 0xBA, 0xF0 }}
+  gFsptUpdLocationPpiGuid                                 = { 0xfc4dd4f2, 0x179e, 0x41f8, { 0x9d, 0x6d, 0xfa, 0xd6, 0xf9, 0xd7, 0xb8, 0xb9 }}
diff --git a/CometLakeFspBinPkg/CometLake2/FSP.fd b/CometLakeFspBinPkg/CometLake2/FSP.fd
new file mode 100644
index 0000000..a306180
--- /dev/null
+++ b/CometLakeFspBinPkg/CometLake2/FSP.fd
diff --git a/CometLakeFspBinPkg/CometLake2/Fsp.bsf b/CometLakeFspBinPkg/CometLake2/Fsp.bsf
new file mode 100644
index 0000000..b86b588
--- /dev/null
+++ b/CometLakeFspBinPkg/CometLake2/Fsp.bsf
@@ -0,0 +1,4862 @@
+/** @file
+
+  Boot Setting File for Platform Configuration.
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+
+
+GlobalDataDef
+    SKUID = 0, "DEFAULT"
+EndGlobalData
+
+
+StructDef
+
+    Find "CMLUPD_T"
+        $gPlatformFspPkgTokenSpaceGuid_Revision                        1 bytes    $_DEFAULT_ = 0x00
+        Skip 55 bytes
+        $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable      1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber           1 bytes    $_DEFAULT_ = 0x02
+        $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode             1 bytes    $_DEFAULT_ = 0x02
+        Skip 1 bytes
+        $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartBaudRate         4 bytes    $_DEFAULT_ = 115200
+        $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressBaseAddress        8 bytes    $_DEFAULT_ = 0xE0000000
+        $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressRegionLength       4 bytes    $_DEFAULT_ = 0x10000000
+        $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity           1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDataBits         1 bytes    $_DEFAULT_ = 0x08
+        $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits         1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow         1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartPinMux           1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable           1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags          1 bytes    $_DEFAULT_ = 0x012
+        $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel             1 bytes    $_DEFAULT_ = 0x03
+        $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase            1 bytes    $_DEFAULT_ = 0x00
+
+    Find "CMLUPD_M"
+        $gPlatformFspPkgTokenSpaceGuid_Revision                        1 bytes    $_DEFAULT_ = 0x00
+        Skip 55 bytes
+        $gPlatformFspPkgTokenSpaceGuid_PlatformMemorySize              8 bytes    $_DEFAULT_ = 0x400000
+        $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr00                  4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr01                  4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr10                  4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr11                  4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen                2 bytes    $_DEFAULT_ = 0x100
+        $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh0                   12 bytes    $_DEFAULT_ = 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh1                   12 bytes    $_DEFAULT_ = 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh0               8 bytes    $_DEFAULT_ = 2, 0, 1, 3, 6, 4, 7, 5
+        $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh1               8 bytes    $_DEFAULT_ = 1, 3, 2, 0, 5, 7, 6, 4
+        $gPlatformFspPkgTokenSpaceGuid_RcompResistor                   6 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_RcompTarget                    10 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_DqPinsInterleaved               1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_CaVrefConfig                    1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_SmramMask                       1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_MrcTimeMeasure                  1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_MrcFastBoot                     1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_RmtPerTask                      1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_TrainTrace                      1 bytes    $_DEFAULT_ = 0x0
+        Skip 3 bytes
+        $gPlatformFspPkgTokenSpaceGuid_IedSize                         4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_TsegSize                        4 bytes    $_DEFAULT_ = 0x0400000
+        $gPlatformFspPkgTokenSpaceGuid_MmioSize                        2 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_ProbelessTrace                  1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_GdxcIotSize                     1 bytes    $_DEFAULT_ = 0x04
+        $gPlatformFspPkgTokenSpaceGuid_GdxcMotSize                     1 bytes    $_DEFAULT_ = 0x0C
+        $gPlatformFspPkgTokenSpaceGuid_SpdAddressTable                 4 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc               1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_InternalGfx                     1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_ApertureSize                    1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_UserBd                          1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SaGv                            1 bytes    $_DEFAULT_ = 0x03
+        $gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit                    2 bytes    $_DEFAULT_ = 0
+        $gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow                     2 bytes    $_DEFAULT_ = 0
+        $gPlatformFspPkgTokenSpaceGuid_RMT                             1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_ScramblerSupport                1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_SkipMpInit                      1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RefClk                          1 bytes    $_DEFAULT_ = 0x00
+        Skip 1 bytes
+        $gPlatformFspPkgTokenSpaceGuid_VddVoltage                      2 bytes    $_DEFAULT_ = 0x0000
+        $gPlatformFspPkgTokenSpaceGuid_Ratio                           1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_OddRatioMode                    1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tCL                             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tCWL                            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tRCDtRP                         1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tRRD                            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tFAW                            2 bytes    $_DEFAULT_ = 0x0000
+        $gPlatformFspPkgTokenSpaceGuid_tRAS                            2 bytes    $_DEFAULT_ = 0x0000
+        $gPlatformFspPkgTokenSpaceGuid_tREFI                           2 bytes    $_DEFAULT_ = 0x0000
+        $gPlatformFspPkgTokenSpaceGuid_tRFC                            2 bytes    $_DEFAULT_ = 0x0000
+        $gPlatformFspPkgTokenSpaceGuid_tRTP                            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tWR                             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tWTR                            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_NModeSupport                    1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_DllBwEn0                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_DllBwEn1                        1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_DllBwEn2                        1 bytes    $_DEFAULT_ = 0x02
+        $gPlatformFspPkgTokenSpaceGuid_DllBwEn3                        1 bytes    $_DEFAULT_ = 0x02
+        $gPlatformFspPkgTokenSpaceGuid_IsvtIoPort                      1 bytes    $_DEFAULT_ = 0x99
+        $gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck                1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_MarginLimitL2                   2 bytes    $_DEFAULT_ = 100
+        $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode                 1 bytes    $_DEFAULT_ = 0
+        $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size          1 bytes    $_DEFAULT_ = 4
+        $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size          1 bytes    $_DEFAULT_ = 4
+        $gPlatformFspPkgTokenSpaceGuid_PeciC10Reset                    1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PeciSxReset                     1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_HeciTimeouts                    1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_Heci1BarAddress                 4 bytes    $_DEFAULT_ = 0xFED1A000
+        $gPlatformFspPkgTokenSpaceGuid_Heci2BarAddress                 4 bytes    $_DEFAULT_ = 0xFED1B000
+        $gPlatformFspPkgTokenSpaceGuid_Heci3BarAddress                 4 bytes    $_DEFAULT_ = 0xFED1C000
+        $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterPwrEn               2 bytes    $_DEFAULT_ = 300
+        $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterHoldReset           2 bytes    $_DEFAULT_ = 100
+        $gPlatformFspPkgTokenSpaceGuid_MmioSizeAdjustment              2 bytes    $_DEFAULT_ = 0
+        $gPlatformFspPkgTokenSpaceGuid_DmiGen3ProgramStaticEq          1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_Peg0Enable                      1 bytes    $_DEFAULT_ = 0x2
+        $gPlatformFspPkgTokenSpaceGuid_Peg1Enable                      1 bytes    $_DEFAULT_ = 0x2
+        $gPlatformFspPkgTokenSpaceGuid_Peg2Enable                      1 bytes    $_DEFAULT_ = 0x2
+        $gPlatformFspPkgTokenSpaceGuid_Peg3Enable                      1 bytes    $_DEFAULT_ = 0x2
+        $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed                1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed                1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed                1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed                1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth                1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth                1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth                1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth                1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes        1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes        1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes        1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes        1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom          1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking   1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_DmiGen3RootPortPreset           8 bytes    $_DEFAULT_ = 0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointPreset           8 bytes    $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointHint             8 bytes    $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_DmiGen3RxCtlePeaking            4 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping                1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization          1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtlePeaking           10 bytes    $_DEFAULT_ = 0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C
+        Skip 3 bytes
+        $gPlatformFspPkgTokenSpaceGuid_PegDataPtr                      4 bytes    $_DEFAULT_ = 0
+        $gPlatformFspPkgTokenSpaceGuid_PegGpioData                    28 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_PegRootPortHPE                  4 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis                   1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay                  1 bytes    $_DEFAULT_ = 0x3
+        $gPlatformFspPkgTokenSpaceGuid_GttSize                         2 bytes    $_DEFAULT_ = 0x3
+        $gPlatformFspPkgTokenSpaceGuid_GmAdr                           4 bytes    $_DEFAULT_ = 0xD0000000
+        $gPlatformFspPkgTokenSpaceGuid_GttMmAdr                        4 bytes    $_DEFAULT_ = 0xCF000000
+        $gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize                  1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie0Gpio                24 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie1Gpio                24 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie2Gpio                24 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie3Gpio                24 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_TxtImplemented                  1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_SaOcSupport                     1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_GtVoltageMode                   1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_GtMaxOcRatio                    1 bytes    $_DEFAULT_ = 0
+        Skip 1 bytes
+        $gPlatformFspPkgTokenSpaceGuid_GtVoltageOffset                 2 bytes    $_DEFAULT_ = 0
+        $gPlatformFspPkgTokenSpaceGuid_GtVoltageOverride               2 bytes    $_DEFAULT_ = 0
+        $gPlatformFspPkgTokenSpaceGuid_GtExtraTurboVoltage             2 bytes    $_DEFAULT_ = 0
+        $gPlatformFspPkgTokenSpaceGuid_SaVoltageOffset                 2 bytes    $_DEFAULT_ = 0
+        $gPlatformFspPkgTokenSpaceGuid_RootPortIndex                   1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming            1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_SaIpuEnable                     1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration           1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_GtPsmiSupport                   1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode                 1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOffset               2 bytes    $_DEFAULT_ = 0
+        $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOverride             2 bytes    $_DEFAULT_ = 0
+        $gPlatformFspPkgTokenSpaceGuid_GtusExtraTurboVoltage           2 bytes    $_DEFAULT_ = 0
+        $gPlatformFspPkgTokenSpaceGuid_GtusMaxOcRatio                  1 bytes    $_DEFAULT_ = 0
+        $gPlatformFspPkgTokenSpaceGuid_SaPreMemProductionRsvd          1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PerCoreHtDisable                2 bytes    $_DEFAULT_ = 0x0000
+        $gPlatformFspPkgTokenSpaceGuid_BistOnReset                     1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SkipStopPbet                    1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_EnableC6Dram                    1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_OcSupport                       1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_OcLock                          1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_CoreMaxOcRatio                  1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_CoreVoltageMode                 1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_DisableMtrrProgram              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RingMaxOcRatio                  1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_HyperThreading                  1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_CpuRatio                        1 bytes    $_DEFAULT_ = 0x1C
+        $gPlatformFspPkgTokenSpaceGuid_BootFrequency                   1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount                 1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_FClkFrequency                   1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable         1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_VmxEnable                       1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_Avx2RatioOffset                 1 bytes    $_DEFAULT_ = 0
+        $gPlatformFspPkgTokenSpaceGuid_Avx3RatioOffset                 1 bytes    $_DEFAULT_ = 0
+        $gPlatformFspPkgTokenSpaceGuid_BclkAdaptiveVoltage             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_CorePllVoltageOffset            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOverride             2 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_CoreVoltageAdaptive             2 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOffset               2 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RingDownBin                     1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_RingVoltageMode                 1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RingVoltageOverride             2 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RingVoltageAdaptive             2 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RingVoltageOffset               2 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_TjMaxOffset                     1 bytes    $_DEFAULT_ = 0x0A
+        $gPlatformFspPkgTokenSpaceGuid_BiosGuard                       1 bytes    $_DEFAULT_ = 0x00
+        Skip 1 bytes
+        $gPlatformFspPkgTokenSpaceGuid_EnableSgx                       1 bytes    $_DEFAULT_ = 0x02
+        $gPlatformFspPkgTokenSpaceGuid_Txt                             1 bytes    $_DEFAULT_ = 0x00
+        Skip 3 bytes
+        $gPlatformFspPkgTokenSpaceGuid_PrmrrSize                       4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_SinitMemorySize                 4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_TxtHeapMemorySize               4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_TxtDprMemorySize                4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_TxtDprMemoryBase                8 bytes    $_DEFAULT_ = 0x0000000000000000
+        $gPlatformFspPkgTokenSpaceGuid_BiosAcmBase                     4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_BiosAcmSize                     4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_ApStartupBase                   4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_TgaSize                         4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdBase                    8 bytes    $_DEFAULT_ = 0x0000000000000000
+        $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdSize                    8 bytes    $_DEFAULT_ = 0x0000000000000000
+        $gPlatformFspPkgTokenSpaceGuid_IsTPMPresence                   1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_AutoEasyOverclock               1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_ReservedSecurityPreMem          2 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddress                 12 bytes    $_DEFAULT_ = 0x00,0x00,0xD9,0xFE,0x00,0x20,0xD9,0xFE,0x00,0x10,0xD9,0xFE
+        $gPlatformFspPkgTokenSpaceGuid_SmbusEnable                     1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg              1 bytes    $_DEFAULT_ = 0x02
+        $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode                 1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size          1 bytes    $_DEFAULT_ = 0x03
+        $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size          1 bytes    $_DEFAULT_ = 0x03
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaEnable                    1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchIshEnable                    1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtleEnable     24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtle           24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmpEnable  24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmp  24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmpEnable  24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmp  24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmpEnable  24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmp  24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmphEnable  24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmph        24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5Enable  24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5     24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0Enable  24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0     24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMagEnable   8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMag     8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMagEnable   8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMag     8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMagEnable   8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMag     8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmpEnable   8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmp   8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmpEnable   8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmp   8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmpEnable   8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmp   8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmphEnable   8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmph         8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmphEnable   8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmph         8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmphEnable   8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmph         8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchLpcEnhancePort8xhDecoding    1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchPort80Route                  1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SmbusArpEnable                  1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchSmbusIoBase                  2 bytes    $_DEFAULT_ = 0xEFA0
+        $gPlatformFspPkgTokenSpaceGuid_PcieImrSize                     2 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RsvdSmbusAddressTablePtr        4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableMask                4 bytes    $_DEFAULT_ = 0x00FFFFFF
+        $gPlatformFspPkgTokenSpaceGuid_PcieImrEnabled                  1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_ImrRpSelection                  1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchSmbAlertEnable               1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags          1 bytes    $_DEFAULT_ = 0x012
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber   1 bytes    $_DEFAULT_ = 0x2
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugAutoFlow       1 bytes    $_DEFAULT_ = 0x0
+        Skip 2 bytes
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugBaudRate       4 bytes    $_DEFAULT_ = 115200
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity         1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits       1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugDataBits       1 bytes    $_DEFAULT_ = 0x8
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable                 1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType                    1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance          1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHda              1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic0            1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic1            1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp0             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp1             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp2             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw1            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw2            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw3            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw4            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwBufferRcomp           1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMem               2 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_GtPllVoltageOffset              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RingPllVoltageOffset            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SaPllVoltageOffset              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_McPllVoltageOffset              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_MrcSafeConfig                   1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate          1 bytes    $_DEFAULT_ = 0x07
+        $gPlatformFspPkgTokenSpaceGuid_HobBufferSize                   1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_ECT                             1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SOT                             1 bytes    $_DEFAULT_ = 0x001
+        $gPlatformFspPkgTokenSpaceGuid_ERDMPRTC2D                      1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_RDMPRT                          1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_RCVET                           1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_JWRL                            1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_EWRTC2D                         1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_ERDTC2D                         1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_WRTC1D                          1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_WRVC1D                          1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_RDTC1D                          1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_DIMMODTT                        1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_DIMMRONT                        1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_WRDSEQT                         1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_WRSRT                           1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_RDODTT                          1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_RDEQT                           1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_RDAPT                           1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_WRTC2D                          1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_RDTC2D                          1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_WRVC2D                          1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_RDVC2D                          1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_CMDVC                           1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_LCT                             1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_RTL                             1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_TAT                             1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_MEMTST                          1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_ALIASCHK                        1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_RCVENC1D                        1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_RMC                             1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_WRDSUDT                         1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_EccSupport                      1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_RemapEnable                     1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_RankInterleave                  1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_EnhancedInterleave              1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_MemoryTrace                     1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_ChHashEnable                    1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_EnableExtts                     1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_EnableCltm                      1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_EnableOltm                      1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_EnablePwrDn                     1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_EnablePwrDnLpddr                1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_UserPowerWeightsEn              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RaplLim2Lock                    1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RaplLim2Ena                     1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RaplLim1Ena                     1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SrefCfgEna                      1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeatLpddr           1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeat                1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RhPrevention                    1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_ExitOnFailure                   1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_DdrThermalSensor                1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedClock              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedZq                 1 bytes    $_DEFAULT_ = 0x00
+        Skip 1 bytes
+        $gPlatformFspPkgTokenSpaceGuid_ChHashMask                      2 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_BClkFrequency                   4 bytes    $_DEFAULT_ = 100000000
+        $gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit             1 bytes    $_DEFAULT_ = 0x02
+        $gPlatformFspPkgTokenSpaceGuid_EnergyScaleFact                 1 bytes    $_DEFAULT_ = 0x04
+        $gPlatformFspPkgTokenSpaceGuid_Idd3n                           2 bytes    $_DEFAULT_ = 0x1A
+        $gPlatformFspPkgTokenSpaceGuid_Idd3p                           2 bytes    $_DEFAULT_ = 0x0B
+        $gPlatformFspPkgTokenSpaceGuid_CMDSR                           1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_CMDDSEQ                         1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_CMDNORM                         1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_EWRDSEQ                         1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_RhActProbability                1 bytes    $_DEFAULT_ = 0xB
+        $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindX                   1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindY                   1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindX                   1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindY                   1 bytes    $_DEFAULT_ = 0x0
+        Skip 1 bytes
+        $gPlatformFspPkgTokenSpaceGuid_RaplLim2Pwr                     2 bytes    $_DEFAULT_ = 0xDE
+        $gPlatformFspPkgTokenSpaceGuid_RaplLim1Pwr                     2 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm0           1 bytes    $_DEFAULT_ = 0xFF
+        $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm1           1 bytes    $_DEFAULT_ = 0xFF
+        $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm0           1 bytes    $_DEFAULT_ = 0xFF
+        $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm1           1 bytes    $_DEFAULT_ = 0xFF
+        $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm0            1 bytes    $_DEFAULT_ = 0xFF
+        $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm1            1 bytes    $_DEFAULT_ = 0xFF
+        $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm0            1 bytes    $_DEFAULT_ = 0xFF
+        $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm1            1 bytes    $_DEFAULT_ = 0xFF
+        $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm0              1 bytes    $_DEFAULT_ = 0xFF
+        $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm1              1 bytes    $_DEFAULT_ = 0xFF
+        $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm0              1 bytes    $_DEFAULT_ = 0xFF
+        $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm1              1 bytes    $_DEFAULT_ = 0xFF
+        $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm0               1 bytes    $_DEFAULT_ = 0xFF
+        $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm1               1 bytes    $_DEFAULT_ = 0xFF
+        $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm0               1 bytes    $_DEFAULT_ = 0xFF
+        $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm1               1 bytes    $_DEFAULT_ = 0xFF
+        $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm0              1 bytes    $_DEFAULT_ = 0x0A
+        $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm1              1 bytes    $_DEFAULT_ = 0x0A
+        $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm0              1 bytes    $_DEFAULT_ = 0x0A
+        $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm1              1 bytes    $_DEFAULT_ = 0x0A
+        $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm0                1 bytes    $_DEFAULT_ = 0x06
+        $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm1                1 bytes    $_DEFAULT_ = 0x06
+        $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm0                1 bytes    $_DEFAULT_ = 0x06
+        $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm1                1 bytes    $_DEFAULT_ = 0x06
+        $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm0               1 bytes    $_DEFAULT_ = 0xAC
+        $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm1               1 bytes    $_DEFAULT_ = 0xAC
+        $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm0               1 bytes    $_DEFAULT_ = 0xAC
+        $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm1               1 bytes    $_DEFAULT_ = 0xAC
+        $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm0                1 bytes    $_DEFAULT_ = 0xD4
+        $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm1                1 bytes    $_DEFAULT_ = 0xD4
+        $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm0                1 bytes    $_DEFAULT_ = 0xD4
+        $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm1                1 bytes    $_DEFAULT_ = 0xD4
+        $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm0                1 bytes    $_DEFAULT_ = 0xDD
+        $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm1                1 bytes    $_DEFAULT_ = 0xDD
+        $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm0                1 bytes    $_DEFAULT_ = 0xDD
+        $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm1                1 bytes    $_DEFAULT_ = 0xDD
+        $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmr                   1 bytes    $_DEFAULT_ = 0x30
+        $gPlatformFspPkgTokenSpaceGuid_CkeRankMapping                  1 bytes    $_DEFAULT_ = 0xAA
+        $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh0                    1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh1                    1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_EnCmdRate                       1 bytes    $_DEFAULT_ = 0x03
+        $gPlatformFspPkgTokenSpaceGuid_Refresh2X                       1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_EpgEnable                       1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RhSolution                      1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_UserThresholdEnable             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_UserBudgetEnable                1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_TsodTcritMax                    1 bytes    $_DEFAULT_ = 0x69
+        $gPlatformFspPkgTokenSpaceGuid_TsodEventMode                   1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_TsodEventPolarity               1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_TsodCriticalEventOnly           1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_TsodEventOutputControl          1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_TsodAlarmwindowLockBit          1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_TsodCriticaltripLockBit         1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_TsodShutdownMode                1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_TsodThigMax                     1 bytes    $_DEFAULT_ = 0x5D
+        $gPlatformFspPkgTokenSpaceGuid_TsodManualEnable                1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_ForceOltmOrRefresh2x            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PwdwnIdleCounter                1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_CmdRanksTerminated              1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_GdxcEnable                      1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel             1 bytes    $_DEFAULT_ = 0x03
+        $gPlatformFspPkgTokenSpaceGuid_FivrFaults                      1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_FivrEfficiency                  1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SafeMode                        1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_CleanMemory                     1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_LpDdrDqDqsReTraining            1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PostCodeOutputPort              2 bytes    $_DEFAULT_ = 0x80
+        $gPlatformFspPkgTokenSpaceGuid_RMTLoopCount                    1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_EnBER                           1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType     1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Ddr4Mixed2DpcLimit              1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_FastBootRmt                     1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_ReservedFspmUpdCfl              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot               1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmrLpddr              1 bytes    $_DEFAULT_ = 0x40
+        $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOut                    1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_MrcTrainOnWarm                  1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt                    1 bytes    $_DEFAULT_ = 0x2
+        $gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn               1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel             1 bytes    $_DEFAULT_ = 0x03
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwLinkIoControlEnabled   4 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode           1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffset              30 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix        15 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_CoreVfPointRatio               15 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_CoreVfPointCount                1 bytes    $_DEFAULT_ = 0x00
+        Skip 9 bytes
+        $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan                  1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_BdatEnable                      1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_ScanExtGfxForLegacyOpRom        1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_LockPTMregs                     1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed                 1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable              1 bytes    $_DEFAULT_ = 0x02
+        $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method              1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable             1 bytes    $_DEFAULT_ = 0x2
+        $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable             1 bytes    $_DEFAULT_ = 0x2
+        $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable             1 bytes    $_DEFAULT_ = 0x2
+        $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable             1 bytes    $_DEFAULT_ = 0x2
+        $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method             1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method             1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method             1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method             1 bytes    $_DEFAULT_ = 0x2
+        $gPlatformFspPkgTokenSpaceGuid_PegGen3ProgramStaticEq          1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt           1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets         1 bytes    $_DEFAULT_ = 0x2
+        $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest           1 bytes    $_DEFAULT_ = 0x2
+        $gPlatformFspPkgTokenSpaceGuid_PegRxCemTestingMode             1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_PegRxCemLoopbackLane            1 bytes    $_DEFAULT_ = 0
+        $gPlatformFspPkgTokenSpaceGuid_PegGenerateBdatMarginTable      1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PegRxCemNonProtocolAwareness    1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtleOverride           1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PegGen3Rsvd                     1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PegGen3RootPortPreset          20 bytes    $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07
+        $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointPreset          20 bytes    $_DEFAULT_ = 0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07
+        $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointHint            20 bytes    $_DEFAULT_ = 0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02
+        Skip 1 bytes
+        $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterDwellTime         2 bytes    $_DEFAULT_ = 3000
+        $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterErrorTarget       2 bytes    $_DEFAULT_ = 2
+        $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocDwellTime            2 bytes    $_DEFAULT_ = 10000
+        $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocErrorTarget          2 bytes    $_DEFAULT_ = 2
+        $gPlatformFspPkgTokenSpaceGuid_PanelPowerEnable                1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_BdatTestType                    1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_VtdDisable                      1 bytes    $_DEFAULT_ = 0x1
+        Skip 1 bytes
+        $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem   2 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_OemT12DelayOverride             1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_SaPreMemTestRsvd                9 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_TotalFlashSize                  2 bytes    $_DEFAULT_ = 0x0000
+        $gPlatformFspPkgTokenSpaceGuid_BiosSize                        2 bytes    $_DEFAULT_ = 0x2800
+        $gPlatformFspPkgTokenSpaceGuid_TxtAcheckRequest                1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_SecurityTestRsvd                3 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SmbusDynamicPowerGating         1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_WdtDisableAndLock               1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SmbusSpdWriteDisable            1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMemTest          16 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_DidInitStat                     1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_DisableCpuReplacedPolling       1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_SendDidMsg                      1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_DisableMessageCheck             1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_SkipMbpHob                      1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_HeciCommunication2              1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_KtDeviceEnable                  1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_tRd2RdSG                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tRd2RdDG                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tRd2RdDR                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tRd2RdDD                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tWr2RdSG                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tWr2RdDG                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tWr2RdDR                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tWr2RdDD                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tWr2WrSG                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tWr2WrDG                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tWr2WrDR                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tWr2WrDD                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tRd2WrSG                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tRd2WrDG                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tRd2WrDR                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tRd2WrDD                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tRRD_L                          1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tRRD_S                          1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tWTR_L                          1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_tWTR_S                          1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SkipCpuReplacementCheck         1 bytes    $_DEFAULT_ = 0x00
+
+    Find "CMLUPD_S"
+        $gPlatformFspPkgTokenSpaceGuid_Revision                        1 bytes    $_DEFAULT_ = 0x01
+        Skip 23 bytes
+        $gPlatformFspPkgTokenSpaceGuid_LogoPtr                         4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_LogoSize                        4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_GraphicsConfigPtr               4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_Device4Enable                   1 bytes    $_DEFAULT_ = 0x00
+        Skip 3 bytes
+        $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionBase             4 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionSize             4 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_TurboMode                       1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_PchDmiCwbEnable                 1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Heci3Enabled                    1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_Heci1Disabled                   1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_AmtEnabled                      1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_WatchDogEnabled                 1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_ManageabilityMode               1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_FwProgress                      1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_AmtSolEnabled                   1 bytes    $_DEFAULT_ = 0x0
+        Skip 1 bytes
+        $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerOs                 2 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerBios               2 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_RemoteAssistance                1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_AmtKvmEnabled                   1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_ForcMebxSyncUp                  1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_CridEnable                      1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_DmiAspm                         1 bytes    $_DEFAULT_ = 0x3
+        $gPlatformFspPkgTokenSpaceGuid_PegDeEmphasis                   4 bytes    $_DEFAULT_ = 0x01,0x01,0x01,0x01
+        $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitValue          4 bytes    $_DEFAULT_ = 0x4B,0x4B,0x4B,0x4B
+        $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitScale          4 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00
+        Skip 1 bytes
+        $gPlatformFspPkgTokenSpaceGuid_PegPhysicalSlotNumber           8 bytes    $_DEFAULT_ = 0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00
+        $gPlatformFspPkgTokenSpaceGuid_PavpEnable                      1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_CdClock                         1 bytes    $_DEFAULT_ = 0x3
+        $gPlatformFspPkgTokenSpaceGuid_PeiGraphicsPeimInit             1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_GnaEnable                       1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOutDeprecated          1 bytes    $_DEFAULT_ = 0x0
+        Skip 3 bytes
+        $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddressDeprecated       12 bytes    $_DEFAULT_ = 0x00,0x00,0xD9,0xFE,0x00,0x20,0xD9,0xFE,0x00,0x10,0xD9,0xFE
+        $gPlatformFspPkgTokenSpaceGuid_DdiPortEdp                      1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_DdiPortBHpd                     1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_DdiPortCHpd                     1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_DdiPortDHpd                     1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_DdiPortFHpd                     1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_DdiPortBDdc                     1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_DdiPortCDdc                     1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_DdiPortDDdc                     1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_DdiPortFDdc                     1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_SkipS3CdClockInit               1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay         2 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_BltBufferAddress                4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_BltBufferSize                   4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_ProgramGtChickenBits            1 bytes    $_DEFAULT_ = 0xE
+        $gPlatformFspPkgTokenSpaceGuid_SaPostMemProductionRsvd        34 bytes    $_DEFAULT_ = 0x00
+        $gCannonLakeFspPkgTokenSpaceGuid_PcieRootPortGen2PllL1CgDisable  24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_AesEnable                       1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_Psi3Enable                      5 bytes    $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01
+        $gPlatformFspPkgTokenSpaceGuid_Psi4Enable                      5 bytes    $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01
+        $gPlatformFspPkgTokenSpaceGuid_ImonSlope                       5 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_ImonOffset                      5 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_VrConfigEnable                  5 bytes    $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01
+        $gPlatformFspPkgTokenSpaceGuid_TdcEnable                       5 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_TdcTimeWindow                   5 bytes    $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01
+        $gPlatformFspPkgTokenSpaceGuid_TdcLock                         5 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PsysSlope                       1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PsysOffset                      1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_AcousticNoiseMitigation         1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableIa           1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa               1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt               1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa               1 bytes    $_DEFAULT_ = 0x00
+        Skip 1 bytes
+        $gPlatformFspPkgTokenSpaceGuid_TdcPowerLimit                  10 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_AcLoadline                     10 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_DcLoadline                     10 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_Psi1Threshold                  10 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_Psi2Threshold                  10 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_Psi3Threshold                  10 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_IccMax                         10 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_VrVoltageLimit                 10 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableGt           1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableSa           1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SendVrMbxCmd                    1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Reserved2                       1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_TxtEnable                       1 bytes    $_DEFAULT_ = 0
+        $gPlatformFspPkgTokenSpaceGuid_SkipMpInitDeprecated            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyPrefix         1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyAdjust         1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_FivrRfiFrequency                2 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_McivrSpreadSpectrum             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_FivrSpreadSpectrum              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableFivr         1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr             1 bytes    $_DEFAULT_ = 0x00
+        Skip 2 bytes
+        $gPlatformFspPkgTokenSpaceGuid_CpuBistData                     4 bytes    $_DEFAULT_ = 0
+        $gPlatformFspPkgTokenSpaceGuid_IslVrCmd                        1 bytes    $_DEFAULT_ = 0x00
+        Skip 1 bytes
+        $gPlatformFspPkgTokenSpaceGuid_ImonSlope1                     10 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_VrPowerDeliveryDesign           4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_PreWake                         1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RampUp                          1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RampDown                        1 bytes    $_DEFAULT_ = 0x00
+        Skip 1 bytes
+        $gPlatformFspPkgTokenSpaceGuid_CpuMpPpi                        4 bytes    $_DEFAULT_ = 0
+        $gPlatformFspPkgTokenSpaceGuid_CpuMpHob                        4 bytes    $_DEFAULT_ = 0
+        $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable            1 bytes    $_DEFAULT_ = 0x02
+        Skip 1 bytes
+        $gPlatformFspPkgTokenSpaceGuid_ImonOffset1                    10 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemProduction    8 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable                 1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi0CsPolarity          2 bytes    $_DEFAULT_ = 0x01, 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi1CsPolarity          2 bytes    $_DEFAULT_ = 0x00, 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi2CsPolarity          2 bytes    $_DEFAULT_ = 0x01, 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi0CsEnable            2 bytes    $_DEFAULT_ = 0x01, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi1CsEnable            2 bytes    $_DEFAULT_ = 0x01, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi2CsEnable            2 bytes    $_DEFAULT_ = 0x01, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiMode                 3 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiDefaultCsOutput      3 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cPadsTermination   6 bytes    $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoI2cMode                 6 bytes    $_DEFAULT_ = 0x01, 0x01, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoUartMode                3 bytes    $_DEFAULT_ = 0x00, 0x00, 0x02
+        Skip 2 bytes
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoUartBaudRate           12 bytes    $_DEFAULT_ = 0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00,0x00,0xC2,0x01,0x00
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoUartParity              3 bytes    $_DEFAULT_ = 0x01, 0x01, 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDataBits            3 bytes    $_DEFAULT_ = 0x08, 0x08, 0x08
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoUartStopBits            3 bytes    $_DEFAULT_ = 0x01, 0x01, 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPowerGating         3 bytes    $_DEFAULT_ = 0x02, 0x02, 0x02
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDmaEnable           3 bytes    $_DEFAULT_ = 0x01, 0x01, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoUartAutoFlow            3 bytes    $_DEFAULT_ = 0x01, 0x01, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPinMux              3 bytes    $_DEFAULT_ = 0, 0, 0
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber         1 bytes    $_DEFAULT_ = 0x02
+        $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDbg2                3 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_ScsEmmcEnabled                  1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_ScsEmmcHs400Enabled             1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_ScsSdCardEnabled                1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_ShowSpiController               1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataSalpSupport                 1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SataPortsEnable                 8 bytes    $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlp                 8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PortUsb20Enable                16 bytes    $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PortUsb30Enable                10 bytes    $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
+        $gPlatformFspPkgTokenSpaceGuid_XdciEnable                      1 bytes    $_DEFAULT_ = 0x01
+        Skip 3 bytes
+        $gPlatformFspPkgTokenSpaceGuid_DevIntConfigPtr                 4 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_NumOfDevIntConfig               1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PxRcConfig                      8 bytes    $_DEFAULT_ = 0x0B, 0x0A, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B
+        $gPlatformFspPkgTokenSpaceGuid_GpioIrqRoute                    1 bytes    $_DEFAULT_ = 0x0E
+        $gPlatformFspPkgTokenSpaceGuid_SciIrqSelect                    1 bytes    $_DEFAULT_ = 0x09
+        $gPlatformFspPkgTokenSpaceGuid_TcoIrqSelect                    1 bytes    $_DEFAULT_ = 0x09
+        $gPlatformFspPkgTokenSpaceGuid_TcoIrqEnable                    1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTableEntryNum         1 bytes    $_DEFAULT_ = 0
+        Skip 2 bytes
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTablePtr              4 bytes    $_DEFAULT_ = 0
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaCodecSxWakeCapability     1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataEnable                      1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SataMode                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Usb2AfePetxiset                16 bytes    $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07
+        $gPlatformFspPkgTokenSpaceGuid_Usb2AfeTxiset                  16 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Usb2AfePredeemp                16 bytes    $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03
+        $gPlatformFspPkgTokenSpaceGuid_Usb2AfePehalfbit               16 bytes    $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmphEnable         10 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmph               10 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmpEnable   10 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmp         10 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrOverrideEnable         1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrHighIdleTimeOverride   4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrMediumIdleTimeOverride   4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrLowIdleTimeOverride    4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_PchLanEnable                    1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHda              1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic0            1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic1            1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp0             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp1             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp2             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw1            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw2            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw3            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw4            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwBufferRcomp           1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpPtmMask                   4 bytes    $_DEFAULT_ = 0x00FFFFFF
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpDpcMask                   4 bytes    $_DEFAULT_ = 0x00FFFFFF
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpDpcExtensionsMask         4 bytes    $_DEFAULT_ = 0x00FFFFFF
+        $gPlatformFspPkgTokenSpaceGuid_UsbPdoProgramming               1 bytes    $_DEFAULT_ = 0x01
+        Skip 3 bytes
+        $gPlatformFspPkgTokenSpaceGuid_PmcPowerButtonDebounce          4 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchEspiBmeMasterSlaveEnabled    1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SataRstLegacyOrom               1 bytes    $_DEFAULT_ = 0x00
+        Skip 2 bytes
+        $gPlatformFspPkgTokenSpaceGuid_TraceHubMemBase                 4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_PmcDbgMsgEn                     1 bytes    $_DEFAULT_ = 0x00
+        Skip 3 bytes
+        $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinPtr               4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinLen               4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_ScsUfsEnabled                   1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_CnviMode                        1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_CnviBtCore                      1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_CnviBtAudioOffload              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SdCardPowerEnableActiveHigh     1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchUsb2PhySusPgEnable           1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchUsbOverCurrentEnable         1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchEspiLgmrEnable               1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchHotEnable                    1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataLedEnable                   1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPmVrAlert                    1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0VmRuntimeControl      1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Vm070VSupport         1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Vm075VSupport         1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotImplemented          24 bytes    $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcUsage                16 bytes    $_DEFAULT_ = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
+        $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcClkReq               16 bytes    $_DEFAULT_ = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpAcsEnabled               24 bytes    $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableCpm                24 bytes    $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpDetectTimeoutMs          48 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_PmcModPhySusPgEnable            1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SlpS0WithGbeSupport             1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchPwrOptEnable                 1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchWriteProtectionEnable        5 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchReadProtectionEnable         5 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00
+        Skip 1 bytes
+        $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeLimit         10 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeBase          10 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaPme                       1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType                    1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency             1 bytes    $_DEFAULT_ = 0x02
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency        1 bytes    $_DEFAULT_ = 0x04
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance          1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispCodecDisconnect      1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioFilterSel            10 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchIoApicEntry24_119            1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchIoApicId                     1 bytes    $_DEFAULT_ = 0x02
+        $gPlatformFspPkgTokenSpaceGuid_PchIshSpiGpioAssign             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchIshUart0GpioAssign           1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchIshUart1GpioAssign           1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchIshI2c0GpioAssign            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchIshI2c1GpioAssign            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchIshI2c2GpioAssign            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchIshGp0GpioAssign             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchIshGp1GpioAssign             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchIshGp2GpioAssign             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchIshGp3GpioAssign             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchIshGp4GpioAssign             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchIshGp5GpioAssign             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchIshGp6GpioAssign             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchIshGp7GpioAssign             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchIshPdtUnlock                 1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchLanLtrEnable                 1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosLock             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchCrid                         1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchLockDownRtcMemoryLock        1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug                  24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpPmSci                    24 bytes    $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpExtSync                  24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpTransmitterHalfSwing     24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpClkReqDetect             24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpAdvancedErrorReporting   24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpUnsupportedRequestReport  24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpFatalErrorReport         24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpNoFatalErrorReport       24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpCorrectableErrorReport   24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnFatalError  24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnNonFatalError  24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnCorrectableError  24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpMaxPayload               24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioRxTuningParameters   10 bytes    $_DEFAULT_ = 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03
+        $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioRxTuningEnable       10 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpPcieSpeed                24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh3Method          24 bytes    $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpPhysicalSlotNumber       24 bytes    $_DEFAULT_ = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpCompletionTimeout        24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpAspm                     24 bytes    $_DEFAULT_ = 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpL1Substates              24 bytes    $_DEFAULT_ = 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrEnable                24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrConfigLock            24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCm           24 bytes    $_DEFAULT_ = 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06
+        $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCp           24 bytes    $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02
+        $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCm             5 bytes    $_DEFAULT_ = 0x06, 0x06, 0x08, 0x02, 0x0A
+        $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCp             5 bytes    $_DEFAULT_ = 0x08, 0x0C, 0x08, 0x02, 0x02
+        $gPlatformFspPkgTokenSpaceGuid_PcieDisableRootPortClockGating   1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieEnablePeerMemoryWrite       1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieComplianceTestMode          1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpFunctionSwap              1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_TetonGlacierCR                  1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPmPmeB0S5Dis                 1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpImrEnabled                1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpImrSelection              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_TetonGlacierMode                1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPmWolEnableOverride          1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchPmPcieWakeFromDeepSx         1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanEnable               1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanDeepSxEnable         1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPmLanWakeFromDeepSx          1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchPmDeepSxPol                  1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS3MinAssert             1 bytes    $_DEFAULT_ = 0x02
+        $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS4MinAssert             1 bytes    $_DEFAULT_ = 0x04
+        $gPlatformFspPkgTokenSpaceGuid_PchPmSlpSusMinAssert            1 bytes    $_DEFAULT_ = 0x03
+        $gPlatformFspPkgTokenSpaceGuid_PchPmSlpAMinAssert              1 bytes    $_DEFAULT_ = 0x03
+        $gPlatformFspPkgTokenSpaceGuid_SlpS0Override                   1 bytes    $_DEFAULT_ = 0x02
+        $gPlatformFspPkgTokenSpaceGuid_SlpS0DisQForDebug               1 bytes    $_DEFAULT_ = 0x03
+        $gPlatformFspPkgTokenSpaceGuid_PchEnableDbcObs                 1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchLegacyIoLowLatency           1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPmLpcClockRun                1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPmSlpStrchSusUp              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPmSlpLanLowDc                1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchPmPwrBtnOverridePeriod       1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPmDisableDsxAcPresentPulldown   1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPmDisableNativePowerButton   1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Enable                1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchPmMeWakeSts                  1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchPmWolOvrWkSts                1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchPmPwrCycDur                  1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPmPciePllSsc                 1 bytes    $_DEFAULT_ = 0xFF
+        $gPlatformFspPkgTokenSpaceGuid_SataPwrOptEnable                1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_EsataSpeedLimit                 1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataSpeedLimit                  1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataPortsHotPlug                8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataPortsInterlockSw            8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataPortsExternal               8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataPortsSpinUp                 8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataPortsSolidStateDrive        8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataPortsEnableDitoConfig       8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataPortsDmVal                  8 bytes    $_DEFAULT_ = 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F
+        Skip 1 bytes
+        $gPlatformFspPkgTokenSpaceGuid_SataPortsDitoVal               16 bytes    $_DEFAULT_ = 0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02,0x71,0x02
+        $gPlatformFspPkgTokenSpaceGuid_SataPortsZpOdd                  8 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId             1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SataRstRaid0                    1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SataRstRaid1                    1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SataRstRaid10                   1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SataRstRaid5                    1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SataRstIrrt                     1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiBanner             1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiDelay              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataRstHddUnlock                1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SataRstLedLocate                1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SataRstIrrtOnly                 1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SataRstSmartStorage             1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SataRstPcieEnable               3 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataRstPcieStoragePort          3 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataRstPcieDeviceResetDelay     3 bytes    $_DEFAULT_ = 100, 100, 100
+        $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400TuningRequired   1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DllDataValid     1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400RxStrobeDll1     1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400TxDataDll        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DriverStrength   1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchSirqEnable                   1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchSirqMode                     1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchStartFramePulse              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchEspiLockLinkConfiguration    1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchTsmicLock                    1 bytes    $_DEFAULT_ = 0x01
+        Skip 1 bytes
+        $gPlatformFspPkgTokenSpaceGuid_PchT0Level                      2 bytes    $_DEFAULT_ = 0x0000
+        $gPlatformFspPkgTokenSpaceGuid_PchT1Level                      2 bytes    $_DEFAULT_ = 0x0000
+        $gPlatformFspPkgTokenSpaceGuid_PchT2Level                      2 bytes    $_DEFAULT_ = 0x0000
+        $gPlatformFspPkgTokenSpaceGuid_PchTTEnable                     1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchTTState13Enable              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchTTLock                       1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_TTSuggestedSetting              1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_TTCrossThrottling               1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchDmiTsawEn                    1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_DmiSuggestedSetting             1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_DmiTS0TW                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_DmiTS1TW                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_DmiTS2TW                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_DmiTS3TW                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataP0T1M                       1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SataP0T2M                       1 bytes    $_DEFAULT_ = 0x02
+        $gPlatformFspPkgTokenSpaceGuid_SataP0T3M                       1 bytes    $_DEFAULT_ = 0x03
+        $gPlatformFspPkgTokenSpaceGuid_SataP0TDisp                     1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataP1T1M                       1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SataP1T2M                       1 bytes    $_DEFAULT_ = 0x02
+        $gPlatformFspPkgTokenSpaceGuid_SataP1T3M                       1 bytes    $_DEFAULT_ = 0x03
+        $gPlatformFspPkgTokenSpaceGuid_SataP1TDisp                     1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataP0Tinact                    1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataP0TDispFinit                1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataP1Tinact                    1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataP1TDispFinit                1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataThermalSuggestedSetting     1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchMemoryThrottlingEnable       1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchMemoryPmsyncEnable           2 bytes    $_DEFAULT_ = 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchMemoryC0TransmitEnable       2 bytes    $_DEFAULT_ = 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchMemoryPinSelection           2 bytes    $_DEFAULT_ = 0x00, 0x00
+        Skip 1 bytes
+        $gPlatformFspPkgTokenSpaceGuid_PchTemperatureHotLevel          2 bytes    $_DEFAULT_ = 0x0000
+        $gPlatformFspPkgTokenSpaceGuid_PchEnableComplianceMode         1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Usb2OverCurrentPin             16 bytes    $_DEFAULT_ = 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, 0x06, 0x06, 0x07, 0x07
+        $gPlatformFspPkgTokenSpaceGuid_Usb3OverCurrentPin             10 bytes    $_DEFAULT_ = 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04
+        $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGating           1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SataRstOptaneMemory             1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SataRstCpuAttachedStorage       1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGatingOnS3       1 bytes    $_DEFAULT_ = 0x01
+        Skip 3 bytes
+        $gPlatformFspPkgTokenSpaceGuid_PchPcieDeviceOverrideTablePtr   4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_EnableTcoTimer                  1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PsOnEnable                      1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PmcCpuC10GatePinEnable          1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl                  1 bytes    $_DEFAULT_ = 0x04
+        $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTranEnable  10 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTran        10 bytes    $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C
+        $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTranEnable  10 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTran        10 bytes    $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C
+        $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTranEnable  10 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTran        10 bytes    $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C
+        $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTranEnable  10 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTran        10 bytes    $_DEFAULT_ = 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C, 0x4C
+        $gPlatformFspPkgTokenSpaceGuid_PcieNumOfCoefficients           1 bytes    $_DEFAULT_ = 0x03
+        $gPlatformFspPkgTokenSpaceGuid_GpioPmRcompCommunityLocalClockGating   1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_ScsSdCardWpPinEnabled           1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlpResetConfig      8 bytes    $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
+        $gPlatformFspPkgTokenSpaceGuid_SpiFlashCfgLockDown             1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwLinkIoControlEnabled   4 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMem              3 bytes    $_DEFAULT_ = 0x00
+        Skip 1 bytes
+        $gPlatformFspPkgTokenSpaceGuid_BgpdtHash                      32 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_BiosGuardAttr                   4 bytes    $_DEFAULT_ = 0xFFFFFFFF
+        Skip 4 bytes
+        $gPlatformFspPkgTokenSpaceGuid_BiosGuardModulePtr              8 bytes    $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF
+        $gPlatformFspPkgTokenSpaceGuid_SendEcCmd                       8 bytes    $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF
+        $gPlatformFspPkgTokenSpaceGuid_EcCmdProvisionEav               1 bytes    $_DEFAULT_ = 0xFF
+        $gPlatformFspPkgTokenSpaceGuid_EcCmdLock                       1 bytes    $_DEFAULT_ = 0xFF
+        Skip 6 bytes
+        $gPlatformFspPkgTokenSpaceGuid_SgxEpoch0                       8 bytes    $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF
+        $gPlatformFspPkgTokenSpaceGuid_SgxEpoch1                       8 bytes    $_DEFAULT_ = 0xFFFFFFFFFFFFFFFF
+        $gPlatformFspPkgTokenSpaceGuid_SgxSinitNvsData                 1 bytes    $_DEFAULT_ = 0xFF
+        $gPlatformFspPkgTokenSpaceGuid_SiCsmFlag                       1 bytes    $_DEFAULT_ = 0x00
+        Skip 2 bytes
+        $gPlatformFspPkgTokenSpaceGuid_SiSsidTablePtr                  4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_SiNumberOfSsidTableEntry        2 bytes    $_DEFAULT_ = 0x0000
+        $gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt                1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear            1 bytes    $_DEFAULT_ = 0x01
+        Skip 8 bytes
+        $gPlatformFspPkgTokenSpaceGuid_ChapDeviceEnable                1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_SkipPamLock                     1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_EdramTestMode                   1 bytes    $_DEFAULT_ = 0x2
+        $gPlatformFspPkgTokenSpaceGuid_DmiExtSync                      1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_DmiIot                          1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_PegMaxPayload                   4 bytes    $_DEFAULT_ = 0xFF,0xFF,0xFF,0xFF
+        $gPlatformFspPkgTokenSpaceGuid_RenderStandby                   1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_PmSupport                       1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_CdynmaxClampEnable              1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_VtdDisableDeprecated            1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_GtFreqMax                       1 bytes    $_DEFAULT_ = 0xFF
+        $gPlatformFspPkgTokenSpaceGuid_DisableTurboGt                  1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_SaPostMemTestRsvd              11 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_OneCoreRatioLimit               1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_TwoCoreRatioLimit               1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_ThreeCoreRatioLimit             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_FourCoreRatioLimit              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Hwp                             1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_HdcControl                      1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PowerLimit1Time                 1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PowerLimit2                     1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_TurboPowerLimitLock             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Time                 1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PowerLimit3DutyCycle            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Lock                 1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PowerLimit4Lock                 1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_TccActivationOffset             1 bytes    $_DEFAULT_ = 0x0F
+        $gPlatformFspPkgTokenSpaceGuid_TccOffsetClamp                  1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_TccOffsetLock                   1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_NumberOfEntries                 1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1Time          1 bytes    $_DEFAULT_ = 0x1C
+        $gPlatformFspPkgTokenSpaceGuid_Custom1TurboActivationRatio     1 bytes    $_DEFAULT_ = 0x14
+        $gPlatformFspPkgTokenSpaceGuid_Custom1ConfigTdpControl         1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1Time          1 bytes    $_DEFAULT_ = 0x1C
+        $gPlatformFspPkgTokenSpaceGuid_Custom2TurboActivationRatio     1 bytes    $_DEFAULT_ = 0x14
+        $gPlatformFspPkgTokenSpaceGuid_Custom2ConfigTdpControl         1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1Time          1 bytes    $_DEFAULT_ = 0x1C
+        $gPlatformFspPkgTokenSpaceGuid_Custom3TurboActivationRatio     1 bytes    $_DEFAULT_ = 0x14
+        $gPlatformFspPkgTokenSpaceGuid_Custom3ConfigTdpControl         1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLock                   1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_ConfigTdpBios                   1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1                 1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Time             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2                 1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_MlcStreamerPrefetcher           1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_MlcSpatialPrefetcher            1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_MonitorMwaitEnable              1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_MachineCheckEnable              1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceLockEnable        1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_ApIdleManner                    1 bytes    $_DEFAULT_ = 0x02
+        $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme      1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceEnable            1 bytes    $_DEFAULT_ = 0x00
+        Skip 2 bytes
+        $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemBase           8 bytes    $_DEFAULT_ = 0x0000000000000000
+        $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemLength         4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_VoltageOptimization             1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_Eist                            1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientPState           1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo            1 bytes    $_DEFAULT_ = 0x02
+        $gPlatformFspPkgTokenSpaceGuid_TStates                         1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_BiProcHot                       1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_DisableProcHotOut               1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_ProcHotResponse                 1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_DisableVrThermalAlert           1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_AutoThermalReporting            1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_ThermalMonitor                  1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_Cx                              1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PmgCstCfgCtrlLock               1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_C1e                             1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PkgCStateDemotion               1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PkgCStateUnDemotion             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_CStatePreWake                   1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_TimedMwait                      1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_CstCfgCtrIoMwaitRedirection     1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PkgCStateLimit                  1 bytes    $_DEFAULT_ = 0x08
+        $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0TimeUnit   1 bytes    $_DEFAULT_ = 0x02
+        $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1TimeUnit   1 bytes    $_DEFAULT_ = 0x02
+        $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2TimeUnit   1 bytes    $_DEFAULT_ = 0x02
+        $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3TimeUnit   1 bytes    $_DEFAULT_ = 0x02
+        $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4TimeUnit   1 bytes    $_DEFAULT_ = 0x02
+        $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5TimeUnit   1 bytes    $_DEFAULT_ = 0x02
+        $gPlatformFspPkgTokenSpaceGuid_PpmIrmSetting                   1 bytes    $_DEFAULT_ = 0x04
+        $gPlatformFspPkgTokenSpaceGuid_ProcHotLock                     1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLevel                  1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RaceToHalt                      1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_MaxRatio                        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_StateRatio                     40 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_StateRatioMax16                16 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        Skip 1 bytes
+        $gPlatformFspPkgTokenSpaceGuid_PsysPmax                        2 bytes    $_DEFAULT_ = 0xAC
+        $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0Irtl       2 bytes    $_DEFAULT_ = 0x4B
+        $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1Irtl       2 bytes    $_DEFAULT_ = 0x76
+        $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2Irtl       2 bytes    $_DEFAULT_ = 0x94
+        $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3Irtl       2 bytes    $_DEFAULT_ = 0xFA
+        $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4Irtl       2 bytes    $_DEFAULT_ = 0x14C
+        $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5Irtl       2 bytes    $_DEFAULT_ = 0x3F2
+        Skip 2 bytes
+        $gPlatformFspPkgTokenSpaceGuid_PowerLimit1                     4 bytes    $_DEFAULT_ = 0x1B58
+        $gPlatformFspPkgTokenSpaceGuid_PowerLimit2Power                4 bytes    $_DEFAULT_ = 0x3A98
+        $gPlatformFspPkgTokenSpaceGuid_PowerLimit3                     4 bytes    $_DEFAULT_ = 0x3A98
+        $gPlatformFspPkgTokenSpaceGuid_PowerLimit4                     4 bytes    $_DEFAULT_ = 0x5208
+        $gPlatformFspPkgTokenSpaceGuid_TccOffsetTimeWindowForRatl      4 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1              4 bytes    $_DEFAULT_ = 0x9C40
+        $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit2              4 bytes    $_DEFAULT_ = 0xC350
+        $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1              4 bytes    $_DEFAULT_ = 0x9C40
+        $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit2              4 bytes    $_DEFAULT_ = 0xC350
+        $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1              4 bytes    $_DEFAULT_ = 0x9C40
+        $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit2              4 bytes    $_DEFAULT_ = 0xC350
+        $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Power            4 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2Power            4 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable       1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_HwpInterruptControl             1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit               1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit             1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_EnableItbm                      1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_EnableItbmDriver                1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_C1StateAutoDemotion             1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_C1StateUnDemotion               1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_CpuWakeUpTimer                  1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_MinRingRatioLimit               1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_MaxRingRatioLimit               1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_C3StateAutoDemotion             1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_C3StateUnDemotion               1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore0              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore1              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore2              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore3              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore4              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore5              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore6              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore7              1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_DualTauBoost                    1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_ItbmPeriodicSmmTimer            1 bytes    $_DEFAULT_ = 0x04
+        $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemTest          9 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SgxSinitDataFromTpm             1 bytes    $_DEFAULT_ = 0xFF
+        $gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage                1 bytes    $_DEFAULT_ = 0x1
+        $gPlatformFspPkgTokenSpaceGuid_DisableD0I3SettingForHeci       1 bytes    $_DEFAULT_ = 0x0
+        Skip 1 bytes
+        $gPlatformFspPkgTokenSpaceGuid_PchHdaResetWaitTimer            2 bytes    $_DEFAULT_ = 0x258
+        $gPlatformFspPkgTokenSpaceGuid_PchLockDownGlobalSmi            1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosInterface        1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_PchUnlockGpioPads               1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchSbAccessUnlock               1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxSnoopLatency       48 bytes    $_DEFAULT_ = 0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxNoSnoopLatency     48 bytes    $_DEFAULT_ = 0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10,0x03,0x10
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMode  24 bytes    $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMultiplier  24 bytes    $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideValue  48 bytes    $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMode  24 bytes    $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMultiplier  24 bytes    $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideValue  48 bytes    $_DEFAULT_ = 0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00,0x3C,0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitScale      24 bytes    $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitValue      48 bytes    $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpUptp                     24 bytes    $_DEFAULT_ = 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05
+        $gPlatformFspPkgTokenSpaceGuid_PcieRpDptp                     24 bytes    $_DEFAULT_ = 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07
+        $gPlatformFspPkgTokenSpaceGuid_PcieEnablePort8xhDecode         1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPciePort8xhDecodePortIndex   1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchPmDisableEnergyReport        1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_SataTestMode                    1 bytes    $_DEFAULT_ = 0x00
+        $gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock                   1 bytes    $_DEFAULT_ = 0x01
+        $gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMemTest         16 bytes    $_DEFAULT_ = 0x00
+        $gCannonLakeFspPkgTokenSpaceGuid_MctpBroadcastCycle            1 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_EmmcUseCustomDlls               1 bytes    $_DEFAULT_ = 0x0
+        Skip 1 bytes
+        $gPlatformFspPkgTokenSpaceGuid_EmmcTxCmdDelayRegValue          4 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_EmmcTxDataDelay1RegValue        4 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_EmmcTxDataDelay2RegValue        4 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_EmmcRxCmdDataDelay1RegValue     4 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_EmmcRxCmdDataDelay2RegValue     4 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_EmmcRxStrobeDelayRegValue       4 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_SdCardUseCustomDlls             1 bytes    $_DEFAULT_ = 0x0
+        Skip 3 bytes
+        $gPlatformFspPkgTokenSpaceGuid_SdCardTxCmdDelayRegValue        4 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_SdCardTxDataDelay1RegValue      4 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_SdCardTxDataDelay2RegValue      4 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_SdCardRxCmdDataDelay1RegValue   4 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_SdCardRxCmdDataDelay2RegValue   4 bytes    $_DEFAULT_ = 0x0
+        $gPlatformFspPkgTokenSpaceGuid_EnforceEDebugMode               1 bytes    $_DEFAULT_ = 0x0
+        Skip 3 bytes
+        $gPlatformFspPkgTokenSpaceGuid_LogoPixelHeight                 4 bytes    $_DEFAULT_ = 0x00000000
+        $gPlatformFspPkgTokenSpaceGuid_LogoPixelWidth                  4 bytes    $_DEFAULT_ = 0x00000000
+
+EndStruct
+
+
+List &EN_DIS
+    Selection 0x1 , "Enabled"
+    Selection 0x0 , "Disabled"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit
+    Selection 0x0 , "0xFF"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartPinMux
+    Selection 0 , " GPIO C8 to C11"
+    Selection 1 , " GPIO F5 - F7 (PCH LP) J5 - J7 (PCH H)"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase
+    Selection 0 , "0x3F8"
+    Selection 1 , "0x2F8"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow
+    Selection 1067 , "1067"
+    Selection 1333 , "1333"
+    Selection 1600 , "1600"
+    Selection 1867 , "1867"
+    Selection 2133 , "2133"
+    Selection 2400 , "2400"
+    Selection 2667 , "2667"
+    Selection 2933 , "2933"
+    Selection 0 , "Auto"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_RhSolution
+    Selection 0 , "Hardware RHP"
+    Selection 1 , "2x Refresh"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_TsegSize
+    Selection 0x0400000 , "4MB"
+    Selection 0x01000000 , "16MB"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel
+    Selection 0 , "Disable"
+    Selection 1 , "Error Only"
+    Selection 2 , "Error and Warnings"
+    Selection 3 , "Load Error Warnings and Info"
+    Selection 4 , "Load Error Warnings and Info & Event"
+    Selection 5 , "Load Error Warnings Info and Verbose"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber
+    Selection 0 , "SerialIoUart0"
+    Selection 1 , "SerialIoUart1"
+    Selection 2 , "SerialIoUart2"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_SmramMask
+    Selection 0 , " Neither"
+    Selection 1 , "AB-SEG"
+    Selection 2 , "H-SEG"
+    Selection 3 , " Both"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg2Enable
+    Selection 0 , "Disable"
+    Selection 1 , "Enable"
+    Selection 2 , "AUTO"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt
+    Selection 0 , "Disable"
+    Selection 1 , "Enable"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration
+    Selection 0 , "IPU Camera"
+    Selection 1 , "IPU Gen"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit
+    Selection 0 , "BIT6"
+    Selection 1 , "BIT7"
+    Selection 2 , "BIT8"
+    Selection 3 , "BIT9"
+    Selection 4 , "BIT10"
+    Selection 5 , "BIT11"
+    Selection 6 , "BIT12"
+    Selection 7 , "BIT13"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType
+    Selection 0 , "1DPC"
+    Selection 1 , "2DPC"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Ratio
+    Selection 0 , "Auto"
+    Selection 4 , "4"
+    Selection 5 , "5"
+    Selection 6 , "6"
+    Selection 7 , "7"
+    Selection 8 , "8"
+    Selection 9 , "9"
+    Selection 10 , "10"
+    Selection 11 , "11"
+    Selection 12 , "12"
+    Selection 13 , "13"
+    Selection 14 , "14"
+    Selection 15 , "15"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed
+    Selection 0 , "Auto"
+    Selection 1 , "Gen1"
+    Selection 2 , "Gen2"
+    Selection 3 , "Gen3"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl
+    Selection 0 , "Disabled"
+    Selection 1 , "L0s"
+    Selection 2 , "L1"
+    Selection 3 , "L0sL1"
+    Selection 4 , "Auto"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets
+    Selection 0 , "P7 P3 P5"
+    Selection 1 , "P0 to P9"
+    Selection 2 , "Auto"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom
+    Selection 0 , "Before"
+    Selection 1 , "After"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg3Enable
+    Selection 0 , "Disable"
+    Selection 1 , "Enable"
+    Selection 2 , "AUTO"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable
+    Selection 0 , "Disable"
+    Selection 1 , "Enable"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_DmiTS2TW
+    Selection 0 , "x1"
+    Selection 1 , "x2"
+    Selection 2 , "x4"
+    Selection 3 , "x8"
+    Selection 4 , "x16"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber
+    Selection 0 , "SerialIoUart0"
+    Selection 1 , "SerialIoUart1"
+    Selection 2 , "SerialIoUart2"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping
+    Selection 0 , " Disabled"
+    Selection 1 , " Enabled"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable
+    Selection 0 , "Disable phase2"
+    Selection 1 , "Enable phase2"
+    Selection 2 , "Auto"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes
+    Selection 0 , "No power saving"
+    Selection 1 , "Auto"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg1Enable
+    Selection 0 , "Disable"
+    Selection 1 , "Enable"
+    Selection 2 , "AUTO"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size
+    Selection 0 , "0"
+    Selection 1 , "1MB"
+    Selection 2 , "8MB"
+    Selection 3 , "64MB"
+    Selection 4 , "128MB"
+    Selection 5 , "256MB"
+    Selection 6 , "512MB"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth
+    Selection 0 , "Auto"
+    Selection 1 , "x1"
+    Selection 2 , "x2"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_VddVoltage
+    Selection 0 , "Default"
+    Selection 1200 , "1.20 Volts"
+    Selection 1250 , "1.25 Volts"
+    Selection 1300 , "1.30 Volts"
+    Selection 1350 , "1.35 Volts"
+    Selection 1400 , "1.40 Volts"
+    Selection 1450 , "1.45 Volts"
+    Selection 1500 , "1.50 Volts"
+    Selection 1550 , "1.55 Volts"
+    Selection 1600 , "1.60 Volts"
+    Selection 1650 , "1.65 Volts"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_ApIdleManner
+    Selection 1 , " HALT loop"
+    Selection 2 , " MWAIT loop"
+    Selection 3 , " RUN loop"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_DmiTS1TW
+    Selection 0 , "x1"
+    Selection 1 , "x2"
+    Selection 2 , "x4"
+    Selection 3 , "x8"
+    Selection 4 , "x16"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_SaGv
+    Selection 0 , "Disabled"
+    Selection 1 , "FixedLow"
+    Selection 2 , "FixedHigh"
+    Selection 3 , "Enabled"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_GtFreqMax
+    Selection 0xFF , " Auto(Default)"
+    Selection 2 , " 100 Mhz"
+    Selection 3 , " 150 Mhz"
+    Selection 4 , " 200 Mhz"
+    Selection 5 , " 250 Mhz"
+    Selection 6 , " 300 Mhz"
+    Selection 7 , " 350 Mhz"
+    Selection 8 , " 400 Mhz"
+    Selection 9 , " 450 Mhz"
+    Selection 0xA , " 500 Mhz"
+    Selection 0xB , " 550 Mhz"
+    Selection 0xC , " 600 Mhz"
+    Selection 0xD , " 650 Mhz"
+    Selection 0xE , " 700 Mhz"
+    Selection 0xF , " 750 Mhz"
+    Selection 0x10 , " 800 Mhz"
+    Selection 0x11 , " 850 Mhz"
+    Selection 0x12 , "900 Mhz"
+    Selection 0x13 , " 950 Mhz"
+    Selection 0x14 , " 1000 Mhz"
+    Selection 0x15 , " 1050 Mhz"
+    Selection 0x16 , " 1100 Mhz"
+    Selection 0x17 , " 1150 Mhz"
+    Selection 0x18 , " 1200 Mhz"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount
+    Selection 0 , "All"
+    Selection 1 , "1"
+    Selection 2 , "2"
+    Selection 3 , "3"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_SlpS0DisQForDebug
+    Selection 0 , "No Change"
+    Selection 1 , "DCI OOB"
+    Selection 2 , "USB2 DbC"
+    Selection 3 , "Auto"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem
+    Selection 0  , " No Delay"
+    Selection 0xFFFF  , " Auto Calulate T12 Delay"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode
+    Selection 0 , "SerialIoUartDisabled"
+    Selection 1 , "SerialIoUartPci"
+    Selection 2 , "SerialIoUartHidden"
+    Selection 3 , "SerialIoUartCom"
+    Selection 4 , "SerialIoUartSkipInit"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_IedSize
+    Selection 0  , " Disable"
+    Selection 0x400000  , " Enable"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode
+    Selection 0 , " Adaptive"
+    Selection 1 , " Override"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes
+    Selection 0 , "No power saving"
+    Selection 1 , "Auto"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable
+    Selection 0 , "Disable"
+    Selection 1 , "Enable"
+    Selection 2 , "Auto"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected
+    Selection 0 , "Default profile"
+    Selection 1 , "Custom profile"
+    Selection 2 , "XMP profile 1"
+    Selection 3 , "XMP profile 2"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method
+    Selection 0 , "Auto"
+    Selection 1 , "HwEq"
+    Selection 2 , "SwEq"
+    Selection 3 , "StaticEq"
+    Selection 4 , "BypassPhase3"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis
+    Selection 0 , " -6dB"
+    Selection 1 , " -3.5dB"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth
+    Selection 0 , "Auto"
+    Selection 1 , "x1"
+    Selection 2 , "x2"
+    Selection 3 , "x4"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode
+    Selection 0 , " 2T"
+    Selection 1 , " 1T"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PchHdaVcType
+    Selection 0 , " VC0"
+    Selection 1 , " VC1"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest
+    Selection 0 , "Disable"
+    Selection 1 , "Enable"
+    Selection 2 , "Auto"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth
+    Selection 0 , "Auto"
+    Selection 1 , "x1"
+    Selection 2 , "x2"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_SlpS0Override
+    Selection 0 , "Disabled"
+    Selection 1 , "Enabled"
+    Selection 2 , "Auto"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent
+    Selection 0 , "Disabled"
+    Selection 1 , "Enabled (DCI OOB+[DbC])"
+    Selection 2 , "Enabled (DCI OOB)"
+    Selection 3 , "Enabled (USB3 DbC)"
+    Selection 4 , "Enabled (XDP/MIPI60)"
+    Selection 5 , "Enabled (USB2 DbC)"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc
+    Selection 0x00 , "0 MB"
+    Selection 0x01 , "32 MB"
+    Selection 0x02 , "64 MB"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_BClkFrequency
+    Selection 100000000 , "100Hz"
+    Selection 125000000 , "125Hz"
+    Selection 167000000 , "167Hz"
+    Selection 250000000 , "250Hz"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay
+    Selection 0 , "iGFX"
+    Selection 1 , "PEG"
+    Selection 2 , "PCIe Graphics on PCH"
+    Selection 3 , "AUTO"
+    Selection 4 , "Switchable Graphics"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt
+    Selection 0 , " Fast/2"
+    Selection 1 , " Fast/4"
+    Selection 2 , " Fast/8"
+    Selection 3 , " Fast/16"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits
+    Selection 0 , " DefaultStopBits"
+    Selection 1 , " OneStopBit"
+    Selection 2 , " OneFiveStopBits"
+    Selection 3 , " TwoStopBits"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo
+    Selection 0 , " Disable"
+    Selection 1 , " Enable"
+    Selection 2 , " Auto"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable
+    Selection 0 , "Disable"
+    Selection 1 , "Enable and Initialize"
+    Selection 2 , "Enable without Initializing"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_DmiAspm
+    Selection 0 , "Disable"
+    Selection 1 , "L0s"
+    Selection 2 , "L1"
+    Selection 3 , "L0sL1"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_BootFrequency
+    Selection 0 , "0"
+    Selection 1 , "1"
+    Selection 2 , "2"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth
+    Selection 0 , "Auto"
+    Selection 1 , "x1"
+    Selection 2 , "x2"
+    Selection 3 , "x4"
+    Selection 4 , "x8"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes
+    Selection 0 , "No power saving"
+    Selection 1 , "Auto"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity
+    Selection 0 , " DefaultParity"
+    Selection 1 , " NoParity"
+    Selection 2 , " EvenParity"
+    Selection 3 , " OddParity"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes
+    Selection 0 , "No power saving"
+    Selection 1 , "Auto"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode
+    Selection 0 , " Disable"
+    Selection 1 , "Target Debugger Mode"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay
+    Selection 0  , " No Delay"
+    Selection 0xFFFF  , " Auto Calulate T12 Delay"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn
+    Selection 0 , "Disable"
+    Selection 1 , "Enable"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg
+    Selection 0 , "Disabled"
+    Selection 1 , "Enabled"
+    Selection 2 , "No Change"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_EdramTestMode
+    Selection 0 , " EDRAM SW disable"
+    Selection 1 , " EDRAM SW Enable"
+    Selection 2 , " EDRAM HW mode"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_BdatTestType
+    Selection 0 , "Rank Margin Tool"
+    Selection 1 , "Margin2D"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method
+    Selection 0 , "Auto"
+    Selection 1 , "HwEq"
+    Selection 2 , "SwEq"
+    Selection 3 , "StaticEq"
+    Selection 4 , "BypassPhase3"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable
+    Selection 0 , "Disable"
+    Selection 1 , "Enable"
+    Selection 2 , "Auto"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit
+    Selection 0x0 , "0xFF"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method
+    Selection 0 , "Auto"
+    Selection 1 , "HwEq"
+    Selection 2 , "SwEq"
+    Selection 3 , "StaticEq"
+    Selection 4 , "BypassPhase3"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_SataMode
+    Selection 0 , "AHCI"
+    Selection 1 , "RAID"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable
+    Selection 0 , " False"
+    Selection 1 , " True"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_tWR
+    Selection 0 , "Auto"
+    Selection 5 , "5"
+    Selection 6 , "6"
+    Selection 7 , "7"
+    Selection 8 , "8"
+    Selection 10 , "10"
+    Selection 12 , "12"
+    Selection 14 , "14"
+    Selection 16 , "16"
+    Selection 18 , "18"
+    Selection 20 , "20"
+    Selection 24 , "24"
+    Selection 30 , "30"
+    Selection 34 , "34"
+    Selection 40 , "40"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme
+    Selection 0 , " Single Range Output"
+    Selection 1 , " ToPA Output"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa
+    Selection 0 , " Fast/2"
+    Selection 1 , " Fast/4"
+    Selection 2 , " Fast/8"
+    Selection 3 , " Fast/16"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen
+    Selection 0x100 , "256 Bytes"
+    Selection 0x200 , "512 Bytes"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit
+    Selection 0x0 , "0xFF"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit
+    Selection 0x0 , "0xFF"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_EnCmdRate
+    Selection 0 , "Disable"
+    Selection 1 , "1 CMD"
+    Selection 2 , "2 CMDS"
+    Selection 3 , "3 CMDS"
+    Selection 4 , "4 CMDS"
+    Selection 5 , "5 CMDS"
+    Selection 6 , "6 CMDS"
+    Selection 7 , "7 CMDS"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt
+    Selection 0 , "Msix"
+    Selection 1 , "Msi"
+    Selection 2 , "Legacy"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_SdCardPowerEnableActiveHigh
+    Selection 0 , " Active low"
+    Selection 1 , " Active high"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed
+    Selection 0 , "Auto"
+    Selection 1 , "Gen1"
+    Selection 2 , "Gen2"
+    Selection 3 , "Gen3"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1
+    Selection 0 , "Enable both DIMMs"
+    Selection 1 , "Disable DIMM0"
+    Selection 2 , "Disable DIMM1"
+    Selection 3 , "Disable both DIMMs"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0
+    Selection 0 , "Enable both DIMMs"
+    Selection 1 , "Disable DIMM0"
+    Selection 2 , "Disable DIMM1"
+    Selection 3 , "Disable both DIMMs"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_CaVrefConfig
+    Selection 0 , "VREF_CA goes to both CH_A and CH_B"
+    Selection 1 , " VREF_CA to CH_A and VREF_DQ_A to CH_B"
+    Selection 2 , "VREF_CA to CH_A and VREF_DQ_B to CH_B"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed
+    Selection 0 , "Auto"
+    Selection 1 , "Gen1"
+    Selection 2 , "Gen2"
+    Selection 3 , "Gen3"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size
+    Selection 0 , "0"
+    Selection 1 , "1MB"
+    Selection 2 , "8MB"
+    Selection 3 , "64MB"
+    Selection 4 , "128MB"
+    Selection 5 , "256MB"
+    Selection 6 , "512MB"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot
+    Selection 0 , "Disable"
+    Selection 1 , "Enable"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization
+    Selection 0 , " Disabled"
+    Selection 1 , " Enabled"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize
+    Selection 0 , "32MB"
+    Selection 1 , "288MB"
+    Selection 2 , "544MB"
+    Selection 3 , "800MB"
+    Selection 4 , "1024MB"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking
+    Selection 0 , "Normal Operation"
+    Selection 1 , "Disable SSC"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_FClkFrequency
+    Selection 0 , "800 MHz"
+    Selection 1 , " 1 GHz"
+    Selection 2 , " 400 MHz"
+    Selection 3 , " Reserved"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable
+    Selection 0 , " False"
+    Selection 1 , " True"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed
+    Selection 0 , "Auto"
+    Selection 1 , "Gen1"
+    Selection 2 , "Gen2"
+    Selection 3 , "Gen3"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming
+    Selection 0 , " Disabled"
+    Selection 1 , " Enabled"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size
+    Selection 0 , "0"
+    Selection 1 , "1MB"
+    Selection 2 , "8MB"
+    Selection 3 , "64MB"
+    Selection 4 , "128MB"
+    Selection 5 , "256MB"
+    Selection 6 , "512MB"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method
+    Selection 0 , "Auto"
+    Selection 1 , "HwEq"
+    Selection 2 , "SwEq"
+    Selection 3 , "StaticEq"
+    Selection 4 , "BypassPhase3"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg0Enable
+    Selection 0 , "Disable"
+    Selection 1 , "Enable"
+    Selection 2 , "AUTO"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow
+    Selection 0 , " Disable"
+    Selection 1 , "Enable"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable
+    Selection 0 , "Disabled"
+    Selection 1 , "Enabled"
+    Selection 2 , "No Change"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency
+    Selection 0 , " 6MHz"
+    Selection 1 , " 12MHz"
+    Selection 2 , " 24MHz"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Refresh2X
+    Selection 0 , "Disable"
+    Selection 1 , "Enabled for WARM or HOT"
+    Selection 2 , "Enabled HOT only"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt
+    Selection 0 , "Disable"
+    Selection 1 , "Enable"
+    Selection 2 , "AUTO"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_DmiTS0TW
+    Selection 0 , "x1"
+    Selection 1 , "x2"
+    Selection 2 , "x4"
+    Selection 3 , "x8"
+    Selection 4 , "x16"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed
+    Selection 0 , "Auto"
+    Selection 1 , "Gen1"
+    Selection 2 , "Gen2"
+    Selection 3 , "Gen3"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits
+    Selection 0 , " DefaultStopBits"
+    Selection 1 , " OneStopBit"
+    Selection 2 , " OneFiveStopBits"
+    Selection 3 , " TwoStopBits"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_CnviMode
+    Selection 0 , "Disable"
+    Selection 1 , "Auto"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa
+    Selection 0 , " Fast/2"
+    Selection 1 , " Fast/4"
+    Selection 2 , " Fast/8"
+    Selection 3 , " Fast/16"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DriverStrength
+    Selection 0 , "33 Ohm"
+    Selection 1 , "40 Ohm"
+    Selection 2 , "50 Ohm"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size
+    Selection 0 , "0"
+    Selection 1 , "1MB"
+    Selection 2 , "8MB"
+    Selection 3 , "64MB"
+    Selection 4 , "128MB"
+    Selection 5 , "256MB"
+    Selection 6 , "512MB"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_TetonGlacierMode
+    Selection 0 , " Disabled"
+    Selection 1 , " Dynamic Configuration"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_RefClk
+    Selection 0 , "133MHz"
+    Selection 1 , "100MHz"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable
+    Selection 0 , "Disable"
+    Selection 1 , "Enable"
+    Selection 2 , "Auto"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_HobBufferSize
+    Selection 0 , "Default"
+    Selection 1 , " 1 Byte"
+    Selection 2 , " 1 KB"
+    Selection 3 , " Max value"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable
+    Selection 0 , "Disable"
+    Selection 1 , "Enable"
+    Selection 2 , "Auto"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_CdClock
+    Selection 0 , " 337.5 Mhz"
+    Selection 1 , " 450 Mhz"
+    Selection 2 , " 540 Mhz"
+    Selection 3 , " 675 Mhz"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_GttSize
+    Selection 1 , "2MB"
+    Selection 2 , "4MB"
+    Selection 3 , "8MB"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_EnableSgx
+    Selection 0 , " Disable"
+    Selection 1 , " Enable"
+    Selection 2 , " Software Control"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_DmiTS3TW
+    Selection 0 , "x1"
+    Selection 1 , "x2"
+    Selection 2 , "x4"
+    Selection 3 , "x8"
+    Selection 4 , "x16"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck
+    Selection 0 , "Disable"
+    Selection 1 , "L1"
+    Selection 2 , "L2"
+    Selection 3 , "Both"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_GtVoltageMode
+    Selection 0 , " Adaptive"
+    Selection 1 , " Override"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method
+    Selection 0 , "Auto"
+    Selection 1 , "HwEq"
+    Selection 2 , "SwEq"
+    Selection 3 , "StaticEq"
+    Selection 4 , "BypassPhase3"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber
+    Selection 0 , "UART0"
+    Selection 1 , "UART1"
+    Selection 2 , "UART2"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit
+    Selection 1067 , "1067"
+    Selection 1333 , "1333"
+    Selection 1400 , "1400"
+    Selection 1600 , "1600"
+    Selection 1800 , "1800"
+    Selection 1867 , "1867"
+    Selection 2000 , "2000"
+    Selection 2133 , "2133"
+    Selection 2200 , "2200"
+    Selection 2400 , "2400"
+    Selection 2600 , "2600"
+    Selection 2667 , "2667"
+    Selection 2800 , "2800"
+    Selection 2933 , "2933"
+    Selection 3000 , "3000"
+    Selection 3200 , "3200"
+    Selection 0 , "Auto"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix
+    Selection 0 , "Positive"
+    Selection 1 , "Negative"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear
+    Selection 0 , " Disable ME Unconfig On Rtc Clear"
+    Selection 1 , " Enable ME Unconfig On Rtc Clear"
+    Selection 2 , " Cmos is clear"
+    Selection 3 , " Reserved"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel
+    Selection 0 , "Disable"
+    Selection 1 , "Error Only"
+    Selection 2 , "Error and Warnings"
+    Selection 3 , "Load Error Warnings and Info"
+    Selection 4 , "Load Error Warnings and Info & Event"
+    Selection 5 , "Load Error Warnings Info and Verbose"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PchStartFramePulse
+    Selection 0 , " PchSfpw4Clk"
+    Selection 1 , " PchSfpw6Clk"
+    Selection 2 , " PchSfpw8Clk"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_ApertureSize
+    Selection 0 , "128 MB"
+    Selection 1 , "256 MB"
+    Selection 3 , "512 MB"
+    Selection 7 , "1024 MB"
+    Selection 15 , " 2048 MB"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId
+    Selection 0 , "Client"
+    Selection 1 , "Alternate"
+    Selection 2 , "Server"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate
+    Selection 3 , "9600"
+    Selection 4 , "19200"
+    Selection 6 , "56700"
+    Selection 7 , "115200"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr
+    Selection 0 , " Fast/2"
+    Selection 1 , " Fast/4"
+    Selection 2 , " Fast/8"
+    Selection 3 , " Fast/16"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_UserBd
+    Selection 0 , "Mobile/Mobile Halo"
+    Selection 1 , "Desktop/DT Halo"
+    Selection 5 , "ULT/ULX/Mobile Halo"
+    Selection 7 , "UP Server"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity
+    Selection 0 , " DefaultParity"
+    Selection 1 , " NoParity"
+    Selection 2 , " EvenParity"
+    Selection 3 , " OddParity"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency
+    Selection 4 , " 96MHz"
+    Selection 3 , " 48MHz"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode
+    Selection 0 , "Legacy"
+    Selection 1 , "Selection"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode
+    Selection 0 , " Disable"
+    Selection 1 , " Target Debugger Mode"
+    Selection 2 , " Host Debugger Mode"
+EndList
+
+BeginInfoBlock
+    PPVer       "0.1"
+    Description "Comet Lake Platform"
+EndInfoBlock
+
+Page "System Agent 1"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressBaseAddress, "Pci Express Base Address", HEX,
+        Help "Base address to be programmed for Pci Express"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcdPciExpressRegionLength, "Pci Express Region Length", HEX,
+        Help "Region Length to be programmed for Pci Express"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SpdAddressTable, "Spd Address Tabl", HEX,
+        Help "Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used if SPD Address is 00"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc, "Internal Graphics Pre-allocated Memory", &gPlatformFspPkgTokenSpaceGuid_IgdDvmt50PreAlloc,
+        Help "Size of memory preallocated for internal graphics."
+    Combo $gPlatformFspPkgTokenSpaceGuid_InternalGfx, "Internal Graphics", &EN_DIS,
+        Help "Enable/disable internal graphics."
+    Combo $gPlatformFspPkgTokenSpaceGuid_ApertureSize, "Aperture Size", &gPlatformFspPkgTokenSpaceGuid_ApertureSize,
+        Help "Select the Aperture Size."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SkipMpInit, "Skip Multi-Processor Initialization", &EN_DIS,
+        Help "When this is skipped, boot loader must initialize processors before SilicionInit API. </b>0: Initialize; <b>1: Skip"
+    Combo $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode, "CPU Trace Hub Mode", &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMode,
+        Help "Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality."
+    Combo $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size, "CPU Trace Hub Memory Region 0", &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg0Size,
+        Help "CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB."
+    Combo $gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size, "CPU Trace Hub Memory Region 1", &gPlatformFspPkgTokenSpaceGuid_CpuTraceHubMemReg1Size,
+        Help "CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PeciC10Reset, "Enable or Disable Peci C10 Reset command", &EN_DIS,
+        Help "Enable or Disable Peci C10 Reset command. If Enabled, BIOS will send the CPU message to disable peci reset on C10 exit. The default value is <b>0: Disable</b> for CNL, and <b>1: Enable</b> for all other CPU's"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PeciSxReset, "Enable or Disable Peci Sx Reset command", &EN_DIS,
+        Help "Enable or Disable Peci Sx Reset command; <b>0: Disable;</b> 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_HeciTimeouts, "HECI Timeouts", &EN_DIS,
+        Help "0: Disable, 1: Enable (Default) timeout check for HECI"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Heci1BarAddress, "HECI1 BAR address", HEX,
+        Help "BAR address of HECI1"
+             "Valid range: 0x00 ~ 0xFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Heci2BarAddress, "HECI2 BAR address", HEX,
+        Help "BAR address of HECI2"
+             "Valid range: 0x00 ~ 0xFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Heci3BarAddress, "HECI3 BAR address", HEX,
+        Help "BAR address of HECI3"
+             "Valid range: 0x00 ~ 0xFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterPwrEn, "SG dGPU Power Delay", HEX,
+        Help "SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is 300=300 microseconds"
+             "Valid range: 0x00 ~ 0x3E8"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SgDelayAfterHoldReset, "SG dGPU Reset Delay", HEX,
+        Help "SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 microseconds"
+             "Valid range: 0x00 ~ 0x3E8"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_MmioSizeAdjustment, "MMIO size adjustment for AUTO mode", HEX,
+        Help "Positive number means increasing MMIO size, Negative value means decreasing MMIO size: 0 (Default)=no change to AUTO mode MMIO size"
+             "Valid range: 0 ~ 0xFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3ProgramStaticEq, "Enable/Disable DMI GEN3 Static EQ Phase1 programming", &EN_DIS,
+        Help "Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable  EQ Phase1 Static Presets Programming"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg0Enable, "Enable/Disable PEG 0", &gPlatformFspPkgTokenSpaceGuid_Peg0Enable,
+        Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg1Enable, "Enable/Disable PEG 1", &gPlatformFspPkgTokenSpaceGuid_Peg1Enable,
+        Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg2Enable, "Enable/Disable PEG 2", &gPlatformFspPkgTokenSpaceGuid_Peg2Enable,
+        Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg3Enable, "Enable/Disable PEG 3", &gPlatformFspPkgTokenSpaceGuid_Peg3Enable,
+        Help "Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed, "PEG 0 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkSpeed,
+        Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed, "PEG 1 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkSpeed,
+        Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed, "PEG 2 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkSpeed,
+        Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed, "PEG 3 Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkSpeed,
+        Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth, "PEG 0 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg0MaxLinkWidth,
+        Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth, "PEG 1 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg1MaxLinkWidth,
+        Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth, "PEG 2 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg2MaxLinkWidth,
+        Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth, "PEG 3 Max Link Width", &gPlatformFspPkgTokenSpaceGuid_Peg3MaxLinkWidth,
+        Help "Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes, "Power down unused lanes on PEG 0", &gPlatformFspPkgTokenSpaceGuid_Peg0PowerDownUnusedLanes,
+        Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes, "Power down unused lanes on PEG 1", &gPlatformFspPkgTokenSpaceGuid_Peg1PowerDownUnusedLanes,
+        Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes, "Power down unused lanes on PEG 2", &gPlatformFspPkgTokenSpaceGuid_Peg2PowerDownUnusedLanes,
+        Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes, "Power down unused lanes on PEG 3", &gPlatformFspPkgTokenSpaceGuid_Peg3PowerDownUnusedLanes,
+        Help "(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width"
+    Combo $gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom, "PCIe ASPM programming will happen in relation to the Oprom", &gPlatformFspPkgTokenSpaceGuid_InitPcieAspmAfterOprom,
+        Help "Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking, "PCIe Disable Spread Spectrum Clocking", &gPlatformFspPkgTokenSpaceGuid_PegDisableSpreadSpectrumClocking,
+        Help "PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled, Disable SSC(0X1) - Disable SSC per platform design or for compliance testing"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3RootPortPreset, "DMI Gen3 Root port preset values per lane", HEX,
+        Help "Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointPreset, "DMI Gen3 End port preset values per lane", HEX,
+        Help "Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3EndPointHint, "DMI Gen3 End port Hint values per lane", HEX,
+        Help "Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_DmiGen3RxCtlePeaking, "DMI Gen3 RxCTLEp per-Bundle control", HEX,
+        Help "Range: 0-15, 0 is default for each bundle, must be specified based upon platform design"
+             "Valid range: 0x00 ~ 0xFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping, "Thermal Velocity Boost Ratio clipping", &gPlatformFspPkgTokenSpaceGuid_TvbRatioClipping,
+        Help "0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction caused by high package temperatures for processors that implement the Intel Thermal Velocity Boost (TVB) feature"
+    Combo $gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization, "Thermal Velocity Boost voltage optimization", &gPlatformFspPkgTokenSpaceGuid_TvbVoltageOptimization,
+        Help "0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations for processors that implement the Intel Thermal Velocity Boost (TVB) feature."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtlePeaking, "PEG Gen3 RxCTLEp per-Bundle control", HEX,
+        Help "Range: 0-15, 12 is default for each bundle, must be specified based upon platform design"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PegDataPtr, "Memory data pointer for saved preset search results", HEX,
+        Help "The reference code will store the Gen3 Preset Search results in the SaDataHob's PegData structure (SA_PEG_DATA) and platform code can save/restore this data to skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0"
+             "Valid range: 0 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PegGpioData, "PEG PERST# GPIO information", HEX,
+        Help "The reference code will use the information in this structure in order to reset PCIe Gen3 devices during equalization, if necessary"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PegRootPortHPE, "PCIe Hot Plug Enable/Disable per port", HEX,
+        Help "0(Default): Disable, 1: Enable"
+             "Valid range: 0x00 ~ 0xFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis, "DeEmphasis control for DMI", &gPlatformFspPkgTokenSpaceGuid_DmiDeEmphasis,
+        Help "DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay, "Selection of the primary display device", &gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay,
+        Help "0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics"
+    Combo $gPlatformFspPkgTokenSpaceGuid_GttSize, "Selection of iGFX GTT Memory size", &gPlatformFspPkgTokenSpaceGuid_GttSize,
+        Help "1=2MB, 2=4MB, 3=8MB, Default is 3"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_GmAdr, "Temporary MMIO address for GMADR", HEX,
+        Help "The reference code will use this as Temporary MMIO address space to access GMADR Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress - 0x1) (Where ApertureSize = 256MB)"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_GttMmAdr, "Temporary MMIO address for GTTMMADR", HEX,
+        Help "The reference code will use this as Temporary MMIO address space to access GTTMMADR Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize, "Selection of PSMI Region size", &gPlatformFspPkgTokenSpaceGuid_PsmiRegionSize,
+        Help "0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie0Gpio, "Switchable Graphics GPIO information for PEG 0", HEX,
+        Help "Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie1Gpio, "Switchable Graphics GPIO information for PEG 1", HEX,
+        Help "Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie2Gpio, "Switchable Graphics GPIO information for PEG 2", HEX,
+        Help "Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SaRtd3Pcie3Gpio, "Switchable Graphics GPIO information for PEG 3", HEX,
+        Help "Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_TxtImplemented, "Enable/Disable MRC TXT dependency", &EN_DIS,
+        Help "When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SaOcSupport, "Enable/Disable SA OcSupport", &EN_DIS,
+        Help "Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport"
+    Combo $gPlatformFspPkgTokenSpaceGuid_GtVoltageMode, "GT slice Voltage Mode", &gPlatformFspPkgTokenSpaceGuid_GtVoltageMode,
+        Help "0(Default): Adaptive, 1: Override"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_GtMaxOcRatio, "Maximum GTs turbo ratio override", HEX,
+        Help "0(Default)=Minimal/Auto, 60=Maximum"
+             "Valid range: 0x00 ~ 0x3C"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_GtVoltageOffset, "The voltage offset applied to GT slice", HEX,
+        Help "0(Default)=Minimal, 1000=Maximum"
+             "Valid range: 0x00 ~ 0x3E8"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_GtVoltageOverride, "The GT slice voltage override which is applied to the entire range of GT frequencies", HEX,
+        Help "0(Default)=Minimal, 2000=Maximum"
+             "Valid range: 0x00 ~ 0x7D0"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_GtExtraTurboVoltage, "adaptive voltage applied during turbo frequencies", HEX,
+        Help "0(Default)=Minimal, 2000=Maximum"
+             "Valid range: 0x00 ~ 0x7D0"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SaVoltageOffset, "voltage offset applied to the SA", HEX,
+        Help "0(Default)=Minimal, 1000=Maximum"
+             "Valid range: 0x00 ~ 0x3E8"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RootPortIndex, "PCIe root port Function number for Switchable Graphics dGPU", HEX,
+        Help "Root port Index number to indicate which PCIe root port has dGPU"
+             "Valid range: 0x00 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming, "Realtime Memory Timing", &gPlatformFspPkgTokenSpaceGuid_RealtimeMemoryTiming,
+        Help "0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform realtime memory timing changes after MRC_DONE."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SaIpuEnable, "Enable/Disable SA IPU", &EN_DIS,
+        Help "Enable(Default): Enable SA IPU, Disable: Disable SA IPU"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration, "IPU IMR Configuration", &gPlatformFspPkgTokenSpaceGuid_SaIpuImrConfiguration,
+        Help "0:IPU Camera, 1:IPU Gen Default is 0"
+    Combo $gPlatformFspPkgTokenSpaceGuid_GtPsmiSupport, "Selection of PSMI Support On/Off", &EN_DIS,
+        Help "0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support"
+    Combo $gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode, "GT unslice Voltage Mode", &gPlatformFspPkgTokenSpaceGuid_GtusVoltageMode,
+        Help "0(Default): Adaptive, 1: Override"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOffset, "voltage offset applied to GT unslice", HEX,
+        Help "0(Default)=Minimal, 2000=Maximum"
+             "Valid range: 0 ~ 1000"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_GtusVoltageOverride, "GT unslice voltage override which is applied to the entire range of GT frequencies", HEX,
+        Help "0(Default)=Minimal, 2000=Maximum"
+             "Valid range: 0 ~ 2000"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_GtusExtraTurboVoltage, "adaptive voltage applied during turbo frequencies", HEX,
+        Help "0(Default)=Minimal, 2000=Maximum"
+             "Valid range: 0 ~ 2000"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_GtusMaxOcRatio, "Maximum GTus turbo ratio override", HEX,
+        Help "0(Default)=Minimal, 60=Maximum"
+             "Valid range: 0 ~ 60"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SaPreMemProductionRsvd, "SaPreMemProductionRsvd", &EN_DIS,
+        Help "Reserved for SA Pre-Mem Production"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PerCoreHtDisable, "Per-core HT Disable", HEX,
+        Help "Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, 0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have HT enabled. Range is 0 - 0x1FF. You can only disable up to MAX_CORE_COUNT - 1."
+             "Valid range: 0x00 ~ 0x1FF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_BistOnReset, "BIST on Reset", &EN_DIS,
+        Help "Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SkipStopPbet, "Skip Stop PBET Timer Enable/Disable", &EN_DIS,
+        Help "Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_EnableC6Dram, "C6DRAM power gating feature", &EN_DIS,
+        Help "This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>."
+    Combo $gPlatformFspPkgTokenSpaceGuid_OcSupport, "Over clocking support", &EN_DIS,
+        Help "Over clocking support; <b>0: Disable</b>; 1: Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_OcLock, "Over clocking Lock", &EN_DIS,
+        Help "Over clocking Lock Enable/Disable; 0: Disable; <b>1: Enable</b>."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CoreMaxOcRatio, "Maximum Core Turbo Ratio Override", HEX,
+        Help "Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-255"
+             "Valid range: 0x00 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_CoreVoltageMode, "Core voltage mode", &EN_DIS,
+        Help "Core voltage mode; <b>0: Adaptive</b>; 1: Override."
+    Combo $gPlatformFspPkgTokenSpaceGuid_DisableMtrrProgram, "Program Cache Attributes", &EN_DIS,
+        Help "Program Cache Attributes; <b>0: Program</b>; 1: Disable Program."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RingMaxOcRatio, "Maximum clr turbo ratio override", HEX,
+        Help "Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the fused max turbo ratio limit. <b>0: Hardware defaults.</b>  Range: 0-255"
+             "Valid range: 0x00 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_HyperThreading, "Hyper Threading Enable/Disable", &EN_DIS,
+        Help "Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CpuRatio, "CPU ratio value", HEX,
+        Help "CPU ratio value. Valid Range 0 to 63. CPU Ratio is 0 when disabled."
+             "Valid range: 0x00 ~ 0x3F"
+    Combo $gPlatformFspPkgTokenSpaceGuid_BootFrequency, "Boot frequency", &gPlatformFspPkgTokenSpaceGuid_BootFrequency,
+        Help "Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.- <b>1: Maximum non-turbo performance</b>.- 2: Turbo performance. @note If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode."
+    Combo $gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount, "Number of active cores", &gPlatformFspPkgTokenSpaceGuid_ActiveCoreCount,
+        Help "Number of active cores(Depends on Number of cores). <b>0: All</b>;<b>1: 1 </b>;<b>2: 2 </b>;<b>3: 3 </b>"
+    Combo $gPlatformFspPkgTokenSpaceGuid_FClkFrequency, "Processor Early Power On Configuration FCLK setting", &gPlatformFspPkgTokenSpaceGuid_FClkFrequency,
+        Help " <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved"
+    Combo $gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable, "Set JTAG power in C10 and deeper power states", &gPlatformFspPkgTokenSpaceGuid_JtagC10PowerGateDisable,
+        Help "False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 and deeper power states for debug purpose. <b>0: False</b>; 1: True."
+    Combo $gPlatformFspPkgTokenSpaceGuid_VmxEnable, "Enable or Disable VMX", &EN_DIS,
+        Help "Enable or Disable VMX; 0: Disable; <b>1: Enable</b>."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Avx2RatioOffset, "AVX2 Ratio Offset", HEX,
+        Help "0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B."
+             "Valid range: 0x00 ~ 0x1F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Avx3RatioOffset, "AVX3 Ratio Offset", HEX,
+        Help "0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B."
+             "Valid range: 0x00 ~ 0x1F"
+    Combo $gPlatformFspPkgTokenSpaceGuid_BclkAdaptiveVoltage, "BCLK Adaptive Voltage Enable", &EN_DIS,
+        Help "When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0: Disable;<b> 1: Enable"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CorePllVoltageOffset, "Core PLL voltage offset", HEX,
+        Help "Core PLL voltage offset. <b>0: No offset</b>. Range 0-63"
+             "Valid range: 0x00 ~ 0x3F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOverride, "core voltage override", HEX,
+        Help "The core voltage override which is applied to the entire range of cpu core frequencies. Valid Range 0 to 2000"
+             "Valid range: 0x00 ~ 0x7D0"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageAdaptive, "Core Turbo voltage Adaptive", HEX,
+        Help "Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. Valid Range 0 to 2000"
+             "Valid range: 0x00 ~ 0x7D0"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVoltageOffset, "Core Turbo voltage Offset", HEX,
+        Help "The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000"
+             "Valid range: 0x00 ~ 0x3E8"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RingDownBin, "Ring Downbin", &EN_DIS,
+        Help "Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always lower than the core ratio.0: Disable; <b>1: Enable.</b>"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RingVoltageMode, "Ring voltage mode", &EN_DIS,
+        Help "Ring voltage mode; <b>0: Adaptive</b>; 1: Override."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageOverride, "Ring voltage override", HEX,
+        Help "The ring voltage override which is applied to the entire range of cpu ring frequencies. Valid Range 0 to 2000"
+             "Valid range: 0x00 ~ 0x7D0"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageAdaptive, "Ring Turbo voltage Adaptive", HEX,
+        Help "Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. Valid Range 0 to 2000"
+             "Valid range: 0x00 ~ 0x7D0"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RingVoltageOffset, "Ring Turbo voltage Offset", HEX,
+        Help "The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000"
+             "Valid range: 0x00 ~ 0x3E8"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_TjMaxOffset, "TjMax Offset", HEX,
+        Help "TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63"
+             "Valid range: 0x0A ~ 0x3F"
+    Combo $gPlatformFspPkgTokenSpaceGuid_BiosGuard, "BiosGuard", &EN_DIS,
+        Help "Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_EnableSgx, "EnableSgx", &gPlatformFspPkgTokenSpaceGuid_EnableSgx,
+        Help "Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Txt, "Txt", &EN_DIS,
+        Help "Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PrmrrSize, "PrmrrSize", HEX,
+        Help "0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SinitMemorySize, "SinitMemorySize", HEX,
+        Help "Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_TxtHeapMemorySize, "TxtHeapMemorySize", HEX,
+        Help "Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_TxtDprMemorySize, "TxtDprMemorySize", HEX,
+        Help "Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_TxtDprMemoryBase, "TxtDprMemoryBase", HEX,
+        Help "Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_BiosAcmBase, "BiosAcmBase", HEX,
+        Help "Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_BiosAcmSize, "BiosAcmSize", HEX,
+        Help "Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_ApStartupBase, "ApStartupBase", HEX,
+        Help "Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_TgaSize, "TgaSize", HEX,
+        Help "Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdBase, "TxtLcpPdBase", HEX,
+        Help "Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_TxtLcpPdSize, "TxtLcpPdSize", HEX,
+        Help "Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_IsTPMPresence, "IsTPMPresence", HEX,
+        Help "IsTPMPresence default values"
+             "Valid range: 0x00 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_AutoEasyOverclock, "Intel Speed Optimizer Enable", &EN_DIS,
+        Help "When enabled this feature automatically overclocks your processor. It changes the All Core Frequency along with PL1, PL2, and IccMax. </b>0: Disable;<b> 1: Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ReservedSecurityPreMem, "ReservedSecurityPreMem", &EN_DIS,
+        Help "Reserved for Security Pre-Mem"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddress, "Base addresses for VT-d function MMIO access", HEX,
+        Help "Base addresses for VT-d MMIO access per VT-d engine"
+             "Valid range: 0 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_GtPllVoltageOffset, "GT PLL voltage offset", HEX,
+        Help "Core PLL voltage offset. <b>0: No offset</b>. Range 0-63"
+             "Valid range: 0x00 ~ 0x3F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RingPllVoltageOffset, "Ring PLL voltage offset", HEX,
+        Help "Core PLL voltage offset. <b>0: No offset</b>. Range 0-63"
+             "Valid range: 0x00 ~ 0x3F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SaPllVoltageOffset, "System Agent PLL voltage offset", HEX,
+        Help "Core PLL voltage offset. <b>0: No offset</b>. Range 0-63"
+             "Valid range: 0x00 ~ 0x3F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_McPllVoltageOffset, "Memory Controller PLL voltage offset", HEX,
+        Help "Core PLL voltage offset. <b>0: No offset</b>. Range 0-63"
+             "Valid range: 0x00 ~ 0x3F"
+    Combo $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOut, "State of X2APIC_OPT_OUT bit in the DMAR table", &EN_DIS,
+        Help "0=Disable/Clear, 1=Enable/Set"
+    Combo $gPlatformFspPkgTokenSpaceGuid_VtdDisable, "Disable VT-d", &EN_DIS,
+        Help "0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem, "Delta T12 Power Cycle Delay required in ms", &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem,
+        Help "Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate T12 Delay to max 500ms"
+    Combo $gPlatformFspPkgTokenSpaceGuid_OemT12DelayOverride, "Oem T12 Dealy Override", &EN_DIS,
+        Help "Oem T12 Dealy Override. 0(Default)=Disable  1=Enable "
+EndPage
+
+Page "System Agent 2"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPtr, "Logo Pointer", HEX,
+        Help "Points to PEI Display Logo Image"
+             "Valid range: 0x0 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_LogoSize, "Logo Size", HEX,
+        Help "Size of PEI Display Logo Image"
+             "Valid range: 0x0 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_GraphicsConfigPtr, "Graphics Configuration Ptr", HEX,
+        Help "Points to VBT"
+             "Valid range: 0x0 ~ 0xFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Device4Enable, "Enable Device 4", &EN_DIS,
+        Help "Enable/disable Device 4"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionBase, "MicrocodeRegionBase", HEX,
+        Help "Memory Base of Microcode Updates"
+             "Valid range: 0x0 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_MicrocodeRegionSize, "MicrocodeRegionSize", HEX,
+        Help "Size of Microcode Updates"
+             "Valid range: 0x0 ~ 0xFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_TurboMode, "Turbo Mode", &EN_DIS,
+        Help "Enable/Disable Turbo mode. 0: disable, 1: enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiCwbEnable, "PchDmiCwbEnable", &EN_DIS,
+        Help "Central Write Buffer feature configurable and disabled by default"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Heci3Enabled, "HECI3 state", &EN_DIS,
+        Help "The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. 0: disable, 1: enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Heci1Disabled, "HECI1 state", &EN_DIS,
+        Help "Determine if HECI1 is hidden prior to boot to OS. <b>0: Disable</b>; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_AmtEnabled, "AMT Switch", &EN_DIS,
+        Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality."
+    Combo $gPlatformFspPkgTokenSpaceGuid_WatchDogEnabled, "WatchDog Timer Switch", &EN_DIS,
+        Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting is invalid if AmtEnabled is 0."
+    Combo $gPlatformFspPkgTokenSpaceGuid_ManageabilityMode, "Manageability Mode set by Mebx", &EN_DIS,
+        Help "Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode."
+    Combo $gPlatformFspPkgTokenSpaceGuid_FwProgress, "PET Progress", &EN_DIS,
+        Help "Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive PET Events. Setting is invalid if AmtEnabled is 0."
+    Combo $gPlatformFspPkgTokenSpaceGuid_AmtSolEnabled, "SOL Switch", &EN_DIS,
+        Help "Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. Setting is invalid if AmtEnabled is 0."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerOs, "OS Timer", HEX,
+        Help "16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0."
+             "Valid range: 0x00 ~ 0xFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_WatchDogTimerBios, "BIOS Timer", HEX,
+        Help "16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0."
+             "Valid range: 0x00 ~ 0xFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RemoteAssistance, "Remote Assistance Trigger Availablilty", &EN_DIS,
+        Help "Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx."
+    Combo $gPlatformFspPkgTokenSpaceGuid_AmtKvmEnabled, "KVM Switch", &EN_DIS,
+        Help "Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. Setting is invalid if AmtEnabled is 0."
+    Combo $gPlatformFspPkgTokenSpaceGuid_ForcMebxSyncUp, "MEBX execution", &EN_DIS,
+        Help "Enable/Disable. 0: Disable, 1: enable, Force MEBX execution."
+    Combo $gPlatformFspPkgTokenSpaceGuid_CridEnable, "Enable/Disable SA CRID", &EN_DIS,
+        Help "Enable: SA CRID, Disable (Default): SA CRID"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DmiAspm, "DMI ASPM", &gPlatformFspPkgTokenSpaceGuid_DmiAspm,
+        Help "0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PegDeEmphasis, "PCIe DeEmphasis control per root port", HEX,
+        Help "0: -6dB, 1(Default): -3.5dB"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitValue, "PCIe Slot Power Limit value per root port", HEX,
+        Help "Slot power limit value per root port"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PegSlotPowerLimitScale, "PCIe Slot Power Limit scale per root port", HEX,
+        Help "Slot power limit scale per root port"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PegPhysicalSlotNumber, "PCIe Physical Slot Number per root port", HEX,
+        Help "Physical Slot Number per root port"
+             "Valid range: 0 ~ 8191"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PavpEnable, "Enable/Disable PavpEnable", &EN_DIS,
+        Help "Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_CdClock, "CdClock Frequency selection", &gPlatformFspPkgTokenSpaceGuid_CdClock,
+        Help "0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PeiGraphicsPeimInit, "Enable/Disable PeiGraphicsPeimInit", &EN_DIS,
+        Help "Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit"
+    Combo $gPlatformFspPkgTokenSpaceGuid_GnaEnable, "Enable or disable GNA device", &EN_DIS,
+        Help "0=Disable, 1(Default)=Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOutDeprecated, "State of X2APIC_OPT_OUT bit in the DMAR table", &EN_DIS,
+        Help "0=Disable/Clear, 1=Enable/Set"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddressDeprecated, "Base addresses for VT-d function MMIO access", HEX,
+        Help "Base addresses for VT-d MMIO access per VT-d engine"
+             "Valid range: 0 ~ 0xFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortEdp, "Enable or disable eDP device", &EN_DIS,
+        Help "0=Disable, 1(Default)=Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortBHpd, "Enable or disable HPD of DDI port B", &EN_DIS,
+        Help "0=Disable, 1(Default)=Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortCHpd, "Enable or disable HPD of DDI port C", &EN_DIS,
+        Help "0=Disable, 1(Default)=Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortDHpd, "Enable or disable HPD of DDI port D", &EN_DIS,
+        Help "0=Disable, 1(Default)=Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortFHpd, "Enable or disable HPD of DDI port F", &EN_DIS,
+        Help "0=Disable, 1(Default)=Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortBDdc, "Enable or disable DDC of DDI port B", &EN_DIS,
+        Help "0=Disable, 1(Default)=Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortCDdc, "Enable or disable DDC of DDI port C", &EN_DIS,
+        Help "0=Disable, 1(Default)=Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortDDdc, "Enable or disable DDC of DDI port D", &EN_DIS,
+        Help "0=Disable, 1(Default)=Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DdiPortFDdc, "Enable or disable DDC of DDI port F", &EN_DIS,
+        Help "0(Default)=Disable, 1=Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SkipS3CdClockInit, "Enable/Disable SkipS3CdClockInit", &EN_DIS,
+        Help "Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full CD clock in S3 resume due to GOP absent"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay, "Delta T12 Power Cycle Delay required in ms", &gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelay,
+        Help "DEPRECATED"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_BltBufferAddress, "Blt Buffer Address", HEX,
+        Help "Address of Blt buffer"
+             "Valid range: 0x0 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_BltBufferSize, "Blt Buffer Size", HEX,
+        Help "Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL)"
+             "Valid range: 0x0 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_ProgramGtChickenBits, "Program GT Chicken bits", HEX,
+        Help "Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1]"
+             "Valid range: 0x0 ~ 0xFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SaPostMemProductionRsvd, "SaPostMemProductionRsvd", &EN_DIS,
+        Help "Reserved for SA Post-Mem Production"
+    Combo $gPlatformFspPkgTokenSpaceGuid_AesEnable, "Advanced Encryption Standard (AES) feature", &EN_DIS,
+        Help "Enable or Disable Advanced Encryption Standard (AES) feature; </b>0: Disable; <b>1: Enable"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Psi3Enable, "Power State 3 enable/disable", HEX,
+        Help "PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>. For all VR Indexes"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Psi4Enable, "Power State 4 enable/disable", HEX,
+        Help "PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.For all VR Indexes"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_ImonSlope, "Imon slope correction", HEX,
+        Help "PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_ImonOffset, "Imon offset correction", HEX,
+        Help "DEPRECATED"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_VrConfigEnable, "Enable/Disable BIOS configuration of VR", HEX,
+        Help "Enable/Disable BIOS configuration of VR; <b>0: Disable</b>; 1: Enable.For all VR Indexes"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_TdcEnable, "Thermal Design Current enable/disable", HEX,
+        Help "PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable.For all VR Indexes"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_TdcTimeWindow, "HECI3 state", HEX,
+        Help "PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms , 8 - 8ms , 10 - 10ms.For all VR Indexe"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_TdcLock, "Thermal Design Current Lock", HEX,
+        Help "PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.For all VR Indexes"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PsysSlope, "Platform Psys slope correction", HEX,
+        Help "PCODE MMIO Mailbox: Platform Psys slope correction. <b>0 - Auto</b> Specified in 1/100 increment values. Range is 0-200. 125 = 1.25"
+             "Valid range: 0x00 ~ 0xC8"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PsysOffset, "Platform Psys offset correction", HEX,
+        Help "PCODE MMIO Mailbox: Platform Psys offset correction. <b>0 - Auto</b> Units 1/4, Range 0-255. Value of 100 = 100/4 = 25 offset"
+             "Valid range: 0x00 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_AcousticNoiseMitigation, "Acoustic Noise Mitigation feature", &EN_DIS,
+        Help "Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.<b>0: Disabled</b>; 1: Enabled"
+    Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableIa, "Disable Fast Slew Rate for Deep Package C States for VR IA domain", &EN_DIS,
+        Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. <b>0: False</b>; 1: True"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa, "Slew Rate configuration for Deep Package C States for VR IA domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForIa,
+        Help "Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt, "Slew Rate configuration for Deep Package C States for VR GT domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForGt,
+        Help "Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa, "Slew Rate configuration for Deep Package C States for VR SA domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForSa,
+        Help "Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_TdcPowerLimit, "Thermal Design Current current limit", HEX,
+        Help "PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. Range is 0-4095. 1000 = 125A. <b>0: Auto</b>. For all VR Indexes"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_AcLoadline, "AcLoadline", HEX,
+        Help "PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249. <b>Intel Recommended Defaults vary by domain and SKU."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_DcLoadline, "DcLoadline", HEX,
+        Help "PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b>"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Psi1Threshold, "Power State 1 Threshold current", HEX,
+        Help "PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Psi2Threshold, "Power State 2 Threshold current", HEX,
+        Help "PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Psi3Threshold, "Power State 3 Threshold current", HEX,
+        Help "PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_IccMax, "Icc Max limit", HEX,
+        Help "PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_VrVoltageLimit, "VR Voltage Limit", HEX,
+        Help "PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableGt, "Disable Fast Slew Rate for Deep Package C States for VR GT domain", &EN_DIS,
+        Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. <b>0: False</b>; 1: True"
+    Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableSa, "Disable Fast Slew Rate for Deep Package C States for VR SA domain", &EN_DIS,
+        Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. <b>0: False</b>; 1: True"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SendVrMbxCmd, "Enable VR specific mailbox command", &EN_DIS,
+        Help "VR specific mailbox commands. <b>00b - no VR specific command sent.</b>  01b - A VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific command sent for PS4 exit issue. 11b - Reserved."
+    Combo $gPlatformFspPkgTokenSpaceGuid_TxtEnable, "Enable or Disable TXT", &EN_DIS,
+        Help "Enable or Disable TXT; 0: Disable; <b>1: Enable</b>."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SkipMpInitDeprecated, "Deprecated DO NOT USE Skip Multi-Processor Initialization", &EN_DIS,
+        Help "@deprecated SkipMpInit has been moved to FspmUpd"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyPrefix, "McIVR RFI Frequency Prefix", HEX,
+        Help "PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. <b>0: Plus (+)</b>; 1: Minus (-)."
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_McivrRfiFrequencyAdjust, "McIVR RFI Frequency Adjustment", HEX,
+        Help "PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. <b>0: Auto</b>."
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_FivrRfiFrequency, "FIVR RFI Frequency", HEX,
+        Help "PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. <b>0: Auto</b>. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; 0-1535 (Up to 153.5MHz) for 19MHz clock."
+             "Valid range: 0x0 ~ 0xFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_McivrSpreadSpectrum, "McIVR RFI Spread Spectrum", HEX,
+        Help "PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. <b>0: 0%</b>; 1: +/- 0.5%; 2: +/- 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%."
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_FivrSpreadSpectrum, "FIVR RFI Spread Spectrum", HEX,
+        Help "PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. <b>0: 0%</b>; Range: 0.0% to 10.0% (0-100)."
+             "Valid range: 0x0 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_FastPkgCRampDisableFivr, "Disable Fast Slew Rate for Deep Package C States for VR FIVR domain", &EN_DIS,
+        Help "Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. <b>0: False</b>; 1: True"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr, "Slew Rate configuration for Deep Package C States for VR FIVR domain", &gPlatformFspPkgTokenSpaceGuid_SlowSlewRateForFivr,
+        Help "Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CpuBistData, "CpuBistData", HEX,
+        Help "Pointer CPU BIST Data"
+             "Valid range: 0x0 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_IslVrCmd, "Activates VR mailbox command for Intersil VR C-state issues.", HEX,
+        Help "Intersil VR mailbox command. <b>0 - no mailbox command sent.</b>  1 - VR mailbox command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails."
+             "Valid range: 0x0 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_ImonSlope1, "Imon slope1 correction", HEX,
+        Help "PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_VrPowerDeliveryDesign, "CPU VR Power Delivery Design", HEX,
+        Help "Used to communicate the power delivery design capability of the board. This value is an enum of the available power delivery segments that are defined in the Platform Design Guide."
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PreWake, "Pre Wake Randomization time", HEX,
+        Help "PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled. Range 0-255 <b>0</b>."
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RampUp, "Ramp Up Randomization time", HEX,
+        Help "PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range 0-255 <b>0</b>."
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RampDown, "Ramp Down Randomization time", HEX,
+        Help "PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range 0-255 <b>0</b>."
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CpuMpPpi, "CpuMpPpi", HEX,
+        Help "Pointer for CpuMpPpi"
+             "Valid range: 0x0 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CpuMpHob, "CpuMpHob", HEX,
+        Help "Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage."
+             "Valid range: 0x0 ~ 0xFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable, "CPU Run Control", &gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable,
+        Help "Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; <b>2: No Change</b>"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_ImonOffset1, "Imon offset 1 correction", HEX,
+        Help "PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b>"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemProduction, "ReservedCpuPostMemProduction", &EN_DIS,
+        Help "Reserved for CPU Post-Mem Production"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_BgpdtHash, "BgpdtHash[4]", HEX,
+        Help "BgpdtHash values"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_BiosGuardAttr, "BiosGuardAttr", HEX,
+        Help "BiosGuardAttr default values"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_BiosGuardModulePtr, "BiosGuardModulePtr", HEX,
+        Help "BiosGuardModulePtr default values"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SendEcCmd, "SendEcCmd", HEX,
+        Help "SendEcCmd function pointer. \n @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE  EcCmdType, IN UINT8  EcCmd, IN UINT8  SendData, IN OUT UINT8  *ReceiveData); @endcode"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_EcCmdProvisionEav, "EcCmdProvisionEav", HEX,
+        Help "Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC"
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_EcCmdLock, "EcCmdLock", HEX,
+        Help "EcCmdLock default values. Locks Ephemeral Authorization Value sent previously"
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SgxEpoch0, "SgxEpoch0", HEX,
+        Help "SgxEpoch0 default values"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SgxEpoch1, "SgxEpoch1", HEX,
+        Help "SgxEpoch1 default values"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SgxSinitNvsData, "SgxSinitNvsData", HEX,
+        Help "SgxSinitNvsData default values"
+             "Valid range: 0x00 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SiCsmFlag, "Si Config CSM Flag.", &EN_DIS,
+        Help "Platform specific common policies that used by several silicon components. CSM status flag."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SiSsidTablePtr, "SVID SDID table Poniter.", HEX,
+        Help "The address of the table of SVID SDID to customize each SVID SDID entry."
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SiNumberOfSsidTableEntry, "Number of ssid table.", HEX,
+        Help "SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr."
+             "Valid range: 0x00 ~ 0xFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ChapDeviceEnable, "Enable/Disable Device 7", &EN_DIS,
+        Help "Enable: Device  7 enabled, Disable (Default): Device 7 disabled"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SkipPamLock, "Skip PAM register lock", &EN_DIS,
+        Help "Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC"
+    Combo $gPlatformFspPkgTokenSpaceGuid_EdramTestMode, "EDRAM Test Mode", &gPlatformFspPkgTokenSpaceGuid_EdramTestMode,
+        Help "Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DmiExtSync, "DMI Extended Sync Control", &EN_DIS,
+        Help "Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended Sync Control"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DmiIot, "DMI IOT Control", &EN_DIS,
+        Help "Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PegMaxPayload, "PEG Max Payload size per root port", HEX,
+        Help "0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RenderStandby, "Enable/Disable IGFX RenderStandby", &EN_DIS,
+        Help "Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PmSupport, "Enable/Disable IGFX PmSupport", &EN_DIS,
+        Help "Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport"
+    Combo $gPlatformFspPkgTokenSpaceGuid_CdynmaxClampEnable, "Enable/Disable CdynmaxClamp", &EN_DIS,
+        Help "Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp"
+    Combo $gPlatformFspPkgTokenSpaceGuid_VtdDisableDeprecated, "Disable VT-d", &EN_DIS,
+        Help "0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)"
+    Combo $gPlatformFspPkgTokenSpaceGuid_GtFreqMax, "GT Frequency Limit", &gPlatformFspPkgTokenSpaceGuid_GtFreqMax,
+        Help "0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, 0x18: 1200 Mhz"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DisableTurboGt, "Disable Turbo GT", &EN_DIS,
+        Help " 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SaPostMemTestRsvd, "SaPostMemTestRsvd", &EN_DIS,
+        Help "Reserved for SA Post-Mem Test"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_OneCoreRatioLimit, "1-Core Ratio Limit", HEX,
+        Help "1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, 8-Core Ratio Limit. Range is 0 to 255"
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_TwoCoreRatioLimit, "2-Core Ratio Limit", HEX,
+        Help "2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255"
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_ThreeCoreRatioLimit, "3-Core Ratio Limit", HEX,
+        Help "3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255"
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_FourCoreRatioLimit, "4-Core Ratio Limit", HEX,
+        Help "4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255"
+             "Valid range: 0x00 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Hwp, "Enable or Disable HWP", &EN_DIS,
+        Help "Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b> 2-3:Reserved"
+    Combo $gPlatformFspPkgTokenSpaceGuid_HdcControl, "Hardware Duty Cycle Control", &EN_DIS,
+        Help "Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit1Time, "Package Long duration turbo mode time", HEX,
+        Help "Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128"
+             "Valid range: 0x00 ~ 0x80"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit2, "Short Duration Turbo Mode", &EN_DIS,
+        Help "Enable or Disable short duration Turbo Mode. </b>0 : Disable; <b>1: Enable</b>"
+    Combo $gPlatformFspPkgTokenSpaceGuid_TurboPowerLimitLock, "Turbo settings Lock", &EN_DIS,
+        Help "Lock all Turbo settings Enable/Disable; <b>0: Disable , </b> 1: Enable"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Time, "Package PL3 time window", HEX,
+        Help "Package PL3 time window range for this policy from 0 to 64ms"
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3DutyCycle, "Package PL3 Duty Cycle", HEX,
+        Help "Package PL3 Duty Cycle; Valid Range is 0 to 100"
+             "Valid range: 0x00 ~ 0x64"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit3Lock, "Package PL3 Lock", &EN_DIS,
+        Help "Package PL3 Lock Enable/Disable; <b>0: Disable ; <b> 1: Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PowerLimit4Lock, "Package PL4 Lock", &EN_DIS,
+        Help "Package PL4 Lock Enable/Disable; <b>0: Disable ; <b>1: Enable"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_TccActivationOffset, "TCC Activation Offset", HEX,
+        Help "TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For Y SKU, the recommended default for this policy is  <b>15</b>, For all other SKUs the recommended default are <b>0</b>"
+             "Valid range: 0x00 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_TccOffsetClamp, "Tcc Offset Clamp Enable/Disable", &EN_DIS,
+        Help "Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.For Y SKU, the recommended default for this policy is <b>1: Enabled</b>, For all other SKUs the recommended default are  <b>0: Disabled</b>."
+    Combo $gPlatformFspPkgTokenSpaceGuid_TccOffsetLock, "Tcc Offset Lock", &EN_DIS,
+        Help "Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; <b>0: Disabled</b>; 1: Enabled."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_NumberOfEntries, "Custom Ratio State Entries", HEX,
+        Help "The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states. At least 2 states must be present"
+             "Valid range: 0x00 ~ 0x28"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1Time, "Custom Short term Power Limit time window", HEX,
+        Help "Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128, 0 = AUTO"
+             "Valid range: 0x00 ~ 0x80"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1TurboActivationRatio, "Custom Turbo Activation Ratio", HEX,
+        Help "Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255"
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1ConfigTdpControl, "Custom Config Tdp Control", HEX,
+        Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2"
+             "Valid range: 0x00 ~ 0x2"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1Time, "Custom Short term Power Limit time window", HEX,
+        Help "Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128, 0 = AUTO"
+             "Valid range: 0x00 ~ 0x80"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2TurboActivationRatio, "Custom Turbo Activation Ratio", HEX,
+        Help "Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255"
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2ConfigTdpControl, "Custom Config Tdp Control", HEX,
+        Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2"
+             "Valid range: 0x00 ~ 0x2"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1Time, "Custom Short term Power Limit time window", HEX,
+        Help "Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128, 0 = AUTO"
+             "Valid range: 0x00 ~ 0x80"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3TurboActivationRatio, "Custom Turbo Activation Ratio", HEX,
+        Help "Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255"
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3ConfigTdpControl, "Custom Config Tdp Control", HEX,
+        Help "Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2"
+             "Valid range: 0x00 ~ 0x2"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLock, "ConfigTdp mode settings Lock", &EN_DIS,
+        Help "Lock the ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1: Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ConfigTdpBios, "Load Configurable TDP SSDT", &EN_DIS,
+        Help "Configure whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1, "PL1 Enable value", &EN_DIS,
+        Help "PL1 Enable value to limit average platform power. <b>0: Disable</b>; 1: Enable."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Time, "PL1 timewindow", HEX,
+        Help "PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128"
+             "Valid range: 0x00 ~ 0x80"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2, "PL2 Enable Value", &EN_DIS,
+        Help "PL2 Enable activates the PL2 value to limit average platform power.<b>0: Disable</b>; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_MlcStreamerPrefetcher, "Enable or Disable MLC Streamer Prefetcher", &EN_DIS,
+        Help "Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>."
+    Combo $gPlatformFspPkgTokenSpaceGuid_MlcSpatialPrefetcher, "Enable or Disable MLC Spatial Prefetcher", &EN_DIS,
+        Help "Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>"
+    Combo $gPlatformFspPkgTokenSpaceGuid_MonitorMwaitEnable, "Enable or Disable Monitor /MWAIT instructions", &EN_DIS,
+        Help "Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>."
+    Combo $gPlatformFspPkgTokenSpaceGuid_MachineCheckEnable, "Enable or Disable initialization of machine check registers", &EN_DIS,
+        Help "Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>."
+    Combo $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceEnable, "Deprecated DO NOT USE Enable or Disable processor debug features", &EN_DIS,
+        Help "@deprecated Enable or Disable processor debug features; <b>0: Disable</b>; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_DebugInterfaceLockEnable, "Lock or Unlock debug interface features", &EN_DIS,
+        Help "Lock or Unlock debug interface features; 0: Disable; <b>1: Enable</b>."
+    Combo $gPlatformFspPkgTokenSpaceGuid_ApIdleManner, "AP Idle Manner of waiting for SIPI", &gPlatformFspPkgTokenSpaceGuid_ApIdleManner,
+        Help "AP Idle Manner of waiting for SIPI; 1: HALT loop; <b>2: MWAIT loop</b>; 3: RUN loop."
+    Combo $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme, "Control on Processor Trace output scheme", &gPlatformFspPkgTokenSpaceGuid_ProcessorTraceOutputScheme,
+        Help "Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output."
+    Combo $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceEnable, "Enable or Disable Processor Trace feature", &EN_DIS,
+        Help "Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemBase, "Base of memory region allocated for Processor Trace", HEX,
+        Help "Base address of memory region allocated for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_ProcessorTraceMemLength, "Memory region allocation for Processor Trace", HEX,
+        Help "Length in bytes of memory region allocated for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_VoltageOptimization, "Enable or Disable Voltage Optimization feature", &EN_DIS,
+        Help "Enable or Disable Voltage Optimization feature 0: Disable; <b>1: Enable</b>"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Eist, "Enable or Disable Intel SpeedStep Technology", &EN_DIS,
+        Help "Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b>"
+    Combo $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientPState, "Enable or Disable Energy Efficient P-state", &EN_DIS,
+        Help "Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; <b>1: Enable</b>"
+    Combo $gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo, "Enable or Disable Energy Efficient Turbo", &gPlatformFspPkgTokenSpaceGuid_EnergyEfficientTurbo,
+        Help "Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; 1: Enable, <b>2: Auto / Silicon default</b>"
+    Combo $gPlatformFspPkgTokenSpaceGuid_TStates, "Enable or Disable T states", &EN_DIS,
+        Help "Enable or Disable T states; <b>0: Disable</b>; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_BiProcHot, "Enable or Disable Bi-Directional PROCHOT#", &EN_DIS,
+        Help "Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b>"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DisableProcHotOut, "Enable or Disable PROCHOT# signal being driven externally", &EN_DIS,
+        Help "Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>."
+    Combo $gPlatformFspPkgTokenSpaceGuid_ProcHotResponse, "Enable or Disable PROCHOT# Response", &EN_DIS,
+        Help "Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_DisableVrThermalAlert, "Enable or Disable VR Thermal Alert", &EN_DIS,
+        Help "Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_AutoThermalReporting, "Enable or Disable Thermal Reporting", &EN_DIS,
+        Help "Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>."
+    Combo $gPlatformFspPkgTokenSpaceGuid_ThermalMonitor, "Enable or Disable Thermal Monitor", &EN_DIS,
+        Help "Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Cx, "Enable or Disable CPU power states (C-states)", &EN_DIS,
+        Help "Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PmgCstCfgCtrlLock, "Configure C-State Configuration Lock", &EN_DIS,
+        Help "Configure C-State Configuration Lock; 0: Disable; <b>1: Enable</b>."
+    Combo $gPlatformFspPkgTokenSpaceGuid_C1e, "Enable or Disable Enhanced C-states", &EN_DIS,
+        Help "Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b>"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PkgCStateDemotion, "Enable or Disable Package Cstate Demotion", &EN_DIS,
+        Help "Enable or Disable Package Cstate Demotion. <b>0: Disable</b>; 1: Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PkgCStateUnDemotion, "Enable or Disable Package Cstate UnDemotion", &EN_DIS,
+        Help "Enable or Disable Package Cstate UnDemotion. <b>0: Disable</b>; 1: Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_CStatePreWake, "Enable or Disable CState-Pre wake", &EN_DIS,
+        Help "Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b>"
+    Combo $gPlatformFspPkgTokenSpaceGuid_TimedMwait, "Enable or Disable TimedMwait Support.", &EN_DIS,
+        Help "Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_CstCfgCtrIoMwaitRedirection, "Enable or Disable IO to MWAIT redirection", &EN_DIS,
+        Help "Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PkgCStateLimit, "Set the Max Pkg Cstate", HEX,
+        Help "Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto"
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0TimeUnit, "TimeUnit for C-State Latency Control0", HEX,
+        Help "TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns"
+             "Valid range: 0x00 ~ 0x5"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1TimeUnit, "TimeUnit for C-State Latency Control1", HEX,
+        Help "TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns"
+             "Valid range: 0x00 ~ 0x5"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2TimeUnit, "TimeUnit for C-State Latency Control2", HEX,
+        Help "TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns"
+             "Valid range: 0x00 ~ 0x5"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3TimeUnit, "TimeUnit for C-State Latency Control3", HEX,
+        Help "TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns"
+             "Valid range: 0x00 ~ 0x5"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4TimeUnit, "TimeUnit for C-State Latency Control4", HEX,
+        Help "Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns"
+             "Valid range: 0x00 ~ 0x5"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5TimeUnit, "TimeUnit for C-State Latency Control5", HEX,
+        Help "TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns"
+             "Valid range: 0x00 ~ 0x5"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PpmIrmSetting, "Interrupt Redirection Mode Select", HEX,
+        Help "Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change."
+             "Valid range: 0x00 ~ 0x7"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ProcHotLock, "Lock prochot configuration", &EN_DIS,
+        Help "Lock prochot configuration Enable/Disable; <b>0: Disable</b>; 1: Enable"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_ConfigTdpLevel, "Configuration for boot TDP selection", HEX,
+        Help "Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP Up;0xFF : Deactivate"
+             "Valid range: 0x00 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RaceToHalt, "Race To Halt", &EN_DIS,
+        Help "Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)Disable; <b>1: Enable</b>"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_MaxRatio, "Max P-State Ratio", HEX,
+        Help "Max P-State Ratio, Valid Range 0 to 0x7F"
+             "Valid range: 0x00 ~ 0x7F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_StateRatio, "P-state ratios for custom P-state table", HEX,
+        Help "P-state ratios for custom P-state table. NumberOfEntries has valid range between 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] are configurable. Valid Range of each entry is 0 to 0x7F"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_StateRatioMax16, "P-state ratios for max 16 version of custom P-state table", HEX,
+        Help "P-state ratios for max 16 version of custom P-state table. This table is used for OS versions limited to a max of 16 P-States. If the first entry of this table is 0, or if Number of Entries is 16 or less, then this table will be ignored, and up to the top 16 values of the StateRatio table will be used instead. Valid Range of each entry is 0 to 0x7F"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPmax, "Platform Power Pmax", HEX,
+        Help "PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments. Range 0-1024 Watts. Value of 800 = 100W"
+             "Valid range: 0x00 ~ 0x400"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl0Irtl, "Interrupt Response Time Limit of C-State LatencyContol0", HEX,
+        Help "Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF"
+             "Valid range: 0x00 ~ 0x3FF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl1Irtl, "Interrupt Response Time Limit of C-State LatencyContol1", HEX,
+        Help "Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF"
+             "Valid range: 0x00 ~ 0x3FF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl2Irtl, "Interrupt Response Time Limit of C-State LatencyContol2", HEX,
+        Help "Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF"
+             "Valid range: 0x00 ~ 0x3FF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl3Irtl, "Interrupt Response Time Limit of C-State LatencyContol3", HEX,
+        Help "Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF"
+             "Valid range: 0x00 ~ 0x3FF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl4Irtl, "Interrupt Response Time Limit of C-State LatencyContol4", HEX,
+        Help "Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF"
+             "Valid range: 0x00 ~ 0x3FF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CstateLatencyControl5Irtl, "Interrupt Response Time Limit of C-State LatencyContol5", HEX,
+        Help "Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF"
+             "Valid range: 0x00 ~ 0x3FF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit1, "Package Long duration turbo mode power limit", HEX,
+        Help "Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 4095875 in Step size of 125"
+             "Valid range: 0x00 ~ 0x3E7F83"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit2Power, "Package Short duration turbo mode power limit", HEX,
+        Help "Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125"
+             "Valid range: 0x00 ~ 0x3E7F83"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit3, "Package PL3 power limit", HEX,
+        Help "Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125"
+             "Valid range: 0x00 ~ 0x3E7F83"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PowerLimit4, "Package PL4 power limit", HEX,
+        Help "Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125"
+             "Valid range: 0x00 ~ 0xF9F83"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_TccOffsetTimeWindowForRatl, "Tcc Offset Time Window for RATL", HEX,
+        Help "Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit1, "Short term Power Limit value for custom cTDP level 1", HEX,
+        Help "Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125"
+             "Valid range: 0x00 ~ 0x3E7F83"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Custom1PowerLimit2, "Long term Power Limit value for custom cTDP level 1", HEX,
+        Help "Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125"
+             "Valid range: 0x00 ~ 0x3E7F83"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit1, "Short term Power Limit value for custom cTDP level 2", HEX,
+        Help "Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125"
+             "Valid range: 0x00 ~ 0x3E7F83"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Custom2PowerLimit2, "Long term Power Limit value for custom cTDP level 2", HEX,
+        Help "Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125"
+             "Valid range: 0x00 ~ 0x3E7F83"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit1, "Short term Power Limit value for custom cTDP level 3", HEX,
+        Help "Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125"
+             "Valid range: 0x00 ~ 0x3E7F83"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Custom3PowerLimit2, "Long term Power Limit value for custom cTDP level 3", HEX,
+        Help "Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125"
+             "Valid range: 0x00 ~ 0x3E7F83"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit1Power, "Platform PL1 power", HEX,
+        Help "Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125"
+             "Valid range: 0x00 ~ 0x3E7F83"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PsysPowerLimit2Power, "Platform PL2 power", HEX,
+        Help "Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125"
+             "Valid range: 0x00 ~ 0x3E7F83"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable, "Set Three Strike Counter Disable", &gPlatformFspPkgTokenSpaceGuid_ThreeStrikeCounterDisable,
+        Help "False (default): Three Strike counter will be incremented and True: Prevents Three Strike counter from incrementing; <b>0: False</b>; 1: True."
+    Combo $gPlatformFspPkgTokenSpaceGuid_HwpInterruptControl, "Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT", &EN_DIS,
+        Help "Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit, "5-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_FiveCoreRatioLimit,
+        Help "5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit, "6-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_SixCoreRatioLimit,
+        Help "6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit, "7-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_SevenCoreRatioLimit,
+        Help "7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255"
+    Combo $gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit, "8-Core Ratio Limit", &gPlatformFspPkgTokenSpaceGuid_EightCoreRatioLimit,
+        Help "8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255"
+    Combo $gPlatformFspPkgTokenSpaceGuid_EnableItbm, "Intel Turbo Boost Max Technology 3.0", &EN_DIS,
+        Help "Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b>"
+    Combo $gPlatformFspPkgTokenSpaceGuid_EnableItbmDriver, "Intel Turbo Boost Max Technology 3.0 Driver", &EN_DIS,
+        Help "@deprecated Intel Turbo Boost Max Technology 3.0 Driver <b>0: Disabled</b>; 1: Enabled"
+    Combo $gPlatformFspPkgTokenSpaceGuid_C1StateAutoDemotion, "Enable or Disable C1 Cstate Demotion", &EN_DIS,
+        Help "Enable or Disable C1 Cstate Demotion. Disable; <b>1: Enable</b>"
+    Combo $gPlatformFspPkgTokenSpaceGuid_C1StateUnDemotion, "Enable or Disable C1 Cstate UnDemotion", &EN_DIS,
+        Help "Enable or Disable C1 Cstate UnDemotion. Disable; <b>1: Enable</b>"
+    Combo $gPlatformFspPkgTokenSpaceGuid_CpuWakeUpTimer, "CpuWakeUpTimer", &EN_DIS,
+        Help "Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased to 180 seconds. 0: Disable; <b>1: Enable</b>"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_MinRingRatioLimit, "Minimum Ring ratio limit override", HEX,
+        Help "Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo ratio limit"
+             "Valid range: 0x00 ~ 0x53"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_MaxRingRatioLimit, "Minimum Ring ratio limit override", HEX,
+        Help "Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo ratio limit"
+             "Valid range: 0x00 ~ 0x53"
+    Combo $gPlatformFspPkgTokenSpaceGuid_C3StateAutoDemotion, "Enable or Disable C3 Cstate Demotion", &EN_DIS,
+        Help "Enable or Disable C3 Cstate Demotion. Disable; <b>1: Enable</b>"
+    Combo $gPlatformFspPkgTokenSpaceGuid_C3StateUnDemotion, "Enable or Disable C3 Cstate UnDemotion", &EN_DIS,
+        Help "Enable or Disable C3 Cstate UnDemotion. Disable; <b>1: Enable</b>"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore0, "Ratio Limit Num Core 0", HEX,
+        Help "Ratio Limit Num Core0: This register defines the active core ranges for each frequency point"
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore1, "Ratio Limit Num Core 1", HEX,
+        Help "Ratio Limit Num Core1: This register defines the active core ranges for each frequency point"
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore2, "Ratio Limit Num Core 2", HEX,
+        Help "Ratio Limit Num Core2: This register defines the active core ranges for each frequency point"
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore3, "Ratio Limit Core 3", HEX,
+        Help "Ratio Limit Num Core3: This register defines the active core ranges for each frequency point"
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore4, "Ratio Limit Num Core 4", HEX,
+        Help "Ratio Limit Num Core4: This register defines the active core ranges for each frequency point"
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore5, "Ratio Limit Num Core 5", HEX,
+        Help "Ratio Limit Num Core5: This register defines the active core ranges for each frequency point"
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore6, "Ratio Limit Num Core 6", HEX,
+        Help "Ratio Limit Num Core6: This register defines the active core ranges for each frequency point"
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RatioLimitNumCore7, "Ratio Limit Num Core 7", HEX,
+        Help "Ratio Limit Num Core7: This register defines the active core ranges for each frequency point"
+             "Valid range: 0x00 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DualTauBoost, "Dual Tau Boost", &EN_DIS,
+        Help "Enable, Disable Dual Tau Boost feature. This is only applicable for CMLS; <b>0: Disable</b>; 1: Enable"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_ItbmPeriodicSmmTimer, "ITBMT 3.0 Runtime Periodic SMM timer", HEX,
+        Help "Periodic SMM Polling timer for ITBMT 3.0 <b>Default 4 - 8 Sec</b>. 0 = Diable periodic SMM, and Valid values 1 - 16ms , 2 - 32ms , 3 - 64ms , 4 - 8 sec , 5 - 16 sec, 6 - 32 sec, 7 - 64 sec."
+             "Valid range: 0x00 ~ 0x07"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ReservedCpuPostMemTest, "ReservedCpuPostMemTest", &EN_DIS,
+        Help "Reserved for CPU Post-Mem Test"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SgxSinitDataFromTpm, "SgxSinitDataFromTpm", HEX,
+        Help "SgxSinitDataFromTpm default values"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+EndPage
+
+Page "Memory Reference Code 1"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PlatformMemorySize, "Platform Reserved Memory Size", HEX,
+        Help "The minimum platform memory size required to pass control into DXE"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr00, "Memory SPD Pointer Channel 0 Dimm 0", HEX,
+        Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr01, "Memory SPD Pointer Channel 0 Dimm 1", HEX,
+        Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr10, "Memory SPD Pointer Channel 1 Dimm 0", HEX,
+        Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySpdPtr11, "Memory SPD Pointer Channel 1 Dimm 1", HEX,
+        Help "Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen, "SPD Data Length", &gPlatformFspPkgTokenSpaceGuid_MemorySpdDataLen,
+        Help "Length of SPD Data"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh0, "Dq Byte Map CH0", HEX,
+        Help "Dq byte mapping between CPU and DRAM, Channel 0: board-dependent"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_DqByteMapCh1, "Dq Byte Map CH1", HEX,
+        Help "Dq byte mapping between CPU and DRAM, Channel 1: board-dependent"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh0, "Dqs Map CPU to DRAM CH 0", HEX,
+        Help "Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_DqsMapCpu2DramCh1, "Dqs Map CPU to DRAM CH 1", HEX,
+        Help "Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RcompResistor, "RcompResistor settings", HEX,
+        Help "Indicates  RcompResistor settings: CML - 0's means MRC auto configured based on Design Guidelines, otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RcompTarget, "RcompTarget settings", HEX,
+        Help "RcompTarget settings: CML - 0's mean MRC auto configured based on Design Guidelines, otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DqPinsInterleaved, "Dqs Pins Interleaved Setting", &EN_DIS,
+        Help "Indicates DqPinsInterleaved setting: board-dependent"
+    Combo $gPlatformFspPkgTokenSpaceGuid_CaVrefConfig, "VREF_CA", &gPlatformFspPkgTokenSpaceGuid_CaVrefConfig,
+        Help "CA Vref routing: board-dependent"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SmramMask, "Smram Mask", &gPlatformFspPkgTokenSpaceGuid_SmramMask,
+        Help "The SMM Regions AB-SEG and/or H-SEG reserved"
+    Combo $gPlatformFspPkgTokenSpaceGuid_MrcTimeMeasure, "Time Measure", &EN_DIS,
+        Help "Time Measure: 0(Default)=Disable, 1=Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_MrcFastBoot, "MRC Fast Boot", &EN_DIS,
+        Help "Enables/Disable the MRC fast path thru the MRC"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RmtPerTask, "Rank Margin Tool per Task", &EN_DIS,
+        Help "This option enables the user to execute Rank Margin Tool per major training step in the MRC."
+    Combo $gPlatformFspPkgTokenSpaceGuid_TrainTrace, "Training Trace", &EN_DIS,
+        Help "This option enables the trained state tracing feature in MRC.  This feature will print out the key training parameters state across major training steps."
+    Combo $gPlatformFspPkgTokenSpaceGuid_IedSize, "Intel Enhanced Debug", &gPlatformFspPkgTokenSpaceGuid_IedSize,
+        Help "Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied"
+    Combo $gPlatformFspPkgTokenSpaceGuid_TsegSize, "Tseg Size", &gPlatformFspPkgTokenSpaceGuid_TsegSize,
+        Help "Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_MmioSize, "MMIO Size", HEX,
+        Help "Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB"
+             "Valid range: 0 ~ 0xC00"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ProbelessTrace, "Probeless Trace", &EN_DIS,
+        Help "Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. This also requires IED to be enabled."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_GdxcIotSize, "GDXC IOT SIZE", HEX,
+        Help "Size of IOT and MOT is in 8 MB chunks"
+             "Valid range: 0x00 ~ 0x80"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_GdxcMotSize, "GDXC MOT SIZE", HEX,
+        Help "Size of IOT and MOT is in 8 MB chunks"
+             "Valid range: 0x00 ~ 0x80"
+    Combo $gPlatformFspPkgTokenSpaceGuid_UserBd, "Board Type", &gPlatformFspPkgTokenSpaceGuid_UserBd,
+        Help "MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SaGv, "SA GV", &gPlatformFspPkgTokenSpaceGuid_SaGv,
+        Help "System Agent dynamic frequency support and when enabled memory will be training at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, 2=FixedHigh, and 3=Enabled."
+    Combo $gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit, "DDR Frequency Limit", &gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit,
+        Help "Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk, i.e. divide by 133 or 100"
+    Combo $gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow, "Low Frequency", &gPlatformFspPkgTokenSpaceGuid_FreqSaGvLow,
+        Help "SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933 and 0 for Auto."
+    Combo $gPlatformFspPkgTokenSpaceGuid_RMT, "Rank Margin Tool", &EN_DIS,
+        Help "Enable/disable Rank Margin Tool."
+    Combo $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0, "Channel A DIMM Control", &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel0,
+        Help "Channel A DIMM Control Support - Enable or Disable Dimms on Channel A."
+    Combo $gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1, "Channel B DIMM Control", &gPlatformFspPkgTokenSpaceGuid_DisableDimmChannel1,
+        Help "Channel B DIMM Control Support - Enable or Disable Dimms on Channel B."
+    Combo $gPlatformFspPkgTokenSpaceGuid_ScramblerSupport, "Scrambler Support", &EN_DIS,
+        Help "This option enables data scrambling in memory."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected, "SPD Profile Selected", &gPlatformFspPkgTokenSpaceGuid_SpdProfileSelected,
+        Help "Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP Profile 1, 3=XMP Profile 2"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RefClk, "Memory Reference Clock", &gPlatformFspPkgTokenSpaceGuid_RefClk,
+        Help "100MHz, 133MHz."
+    Combo $gPlatformFspPkgTokenSpaceGuid_VddVoltage, "Memory Voltage", &gPlatformFspPkgTokenSpaceGuid_VddVoltage,
+        Help "Memory Voltage Override (Vddq). Default = no override"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Ratio, "Memory Ratio", &gPlatformFspPkgTokenSpaceGuid_Ratio,
+        Help "Automatic or the frequency will equal ratio times reference clock. Set to Auto to recalculate memory timings listed below."
+    Combo $gPlatformFspPkgTokenSpaceGuid_OddRatioMode, "QCLK Odd Ratio", &EN_DIS,
+        Help "Adds 133 or 100 MHz to QCLK frequency, depending on RefClk"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tCL, "tCL", HEX,
+        Help "CAS Latency, 0: AUTO, max: 31"
+             "Valid range: 0x00 ~ 0x1F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tCWL, "tCWL", HEX,
+        Help "Min CAS Write Latency Delay Time, 0: AUTO, max: 34"
+             "Valid range: 0x00 ~ 0x22"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tRCDtRP, "tRCD/tRP", HEX,
+        Help "RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63"
+             "Valid range: 0x00 ~ 0x3F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD, "tRRD", HEX,
+        Help "Min Row Active to Row Active Delay Time, 0: AUTO, max: 15"
+             "Valid range: 0x00 ~ 0x0F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tFAW, "tFAW", HEX,
+        Help "Min Four Activate Window Delay Time, 0: AUTO, max: 63"
+             "Valid range: 0x00 ~ 0x3F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tRAS, "tRAS", HEX,
+        Help "RAS Active Time, 0: AUTO, max: 64"
+             "Valid range: 0x00 ~ 0x40"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tREFI, "tREFI", HEX,
+        Help "Refresh Interval, 0: AUTO, max: 65535"
+             "Valid range: 0x00 ~ 0xFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tRFC, "tRFC", HEX,
+        Help "Min Refresh Recovery Delay Time, 0: AUTO, max: 1023"
+             "Valid range: 0x00 ~ 0x3FF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tRTP, "tRTP", HEX,
+        Help "Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12"
+             "Valid range: 0x00 ~ 0x0F"
+    Combo $gPlatformFspPkgTokenSpaceGuid_tWR, "tWR", &gPlatformFspPkgTokenSpaceGuid_tWR,
+        Help "Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24, 30, 34, 40"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR, "tWTR", HEX,
+        Help "Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28"
+             "Valid range: 0x00 ~ 0x1C"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_NModeSupport, "NMode", HEX,
+        Help "System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N"
+             "Valid range: 0x00 ~ 0x02"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn0, "DllBwEn[0]", HEX,
+        Help "DllBwEn[0], for 1067 (0..7)"
+             "Valid range: 0x00 ~ 0x07"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn1, "DllBwEn[1]", HEX,
+        Help "DllBwEn[1], for 1333 (0..7)"
+             "Valid range: 0x00 ~ 0x07"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn2, "DllBwEn[2]", HEX,
+        Help "DllBwEn[2], for 1600 (0..7)"
+             "Valid range: 0x00 ~ 0x07"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_DllBwEn3, "DllBwEn[3]", HEX,
+        Help "DllBwEn[3], for 1867 and up (0..7)"
+             "Valid range: 0x00 ~ 0x07"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_IsvtIoPort, "ISVT IO Port Address", HEX,
+        Help "ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default"
+             "Valid range: 0x00 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck, "Margin Limit Check", &gPlatformFspPkgTokenSpaceGuid_MarginLimitCheck,
+        Help "Margin Limit Check. Choose level of margin check"
+    Combo $gPlatformFspPkgTokenSpaceGuid_MrcSafeConfig, "MRC Safe Config", &EN_DIS,
+        Help "Enables/Disable MRC Safe Config"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate, "PcdSerialDebugBaudRate", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugBaudRate,
+        Help "Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200."
+    Combo $gPlatformFspPkgTokenSpaceGuid_HobBufferSize, "HobBufferSize", &gPlatformFspPkgTokenSpaceGuid_HobBufferSize,
+        Help "Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB total HOB size)."
+    Combo $gPlatformFspPkgTokenSpaceGuid_ECT, "Early Command Training", &EN_DIS,
+        Help "Enables/Disable Early Command Training"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SOT, "SenseAmp Offset Training", &EN_DIS,
+        Help "Enables/Disable SenseAmp Offset Training"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ERDMPRTC2D, "Early ReadMPR Timing Centering 2D", &EN_DIS,
+        Help "Enables/Disable Early ReadMPR Timing Centering 2D"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RDMPRT, "Read MPR Training", &EN_DIS,
+        Help "Enables/Disable Read MPR Training"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RCVET, "Receive Enable Training", &EN_DIS,
+        Help "Enables/Disable Receive Enable Training"
+    Combo $gPlatformFspPkgTokenSpaceGuid_JWRL, "Jedec Write Leveling", &EN_DIS,
+        Help "Enables/Disable Jedec Write Leveling"
+    Combo $gPlatformFspPkgTokenSpaceGuid_EWRTC2D, "Early Write Time Centering 2D", &EN_DIS,
+        Help "Enables/Disable Early Write Time Centering 2D"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ERDTC2D, "Early Read Time Centering 2D", &EN_DIS,
+        Help "Enables/Disable Early Read Time Centering 2D"
+    Combo $gPlatformFspPkgTokenSpaceGuid_WRTC1D, "Write Timing Centering 1D", &EN_DIS,
+        Help "Enables/Disable Write Timing Centering 1D"
+    Combo $gPlatformFspPkgTokenSpaceGuid_WRVC1D, "Write Voltage Centering 1D", &EN_DIS,
+        Help "Enables/Disable Write Voltage Centering 1D"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RDTC1D, "Read Timing Centering 1D", &EN_DIS,
+        Help "Enables/Disable Read Timing Centering 1D"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DIMMODTT, "Dimm ODT Training", &EN_DIS,
+        Help "Enables/Disable Dimm ODT Training"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DIMMRONT, "DIMM RON Training", &EN_DIS,
+        Help "Enables/Disable DIMM RON Training"
+    Combo $gPlatformFspPkgTokenSpaceGuid_WRDSEQT, "Write Drive Strength/Equalization 2D", &EN_DIS,
+        Help "Enables/Disable Write Drive Strength/Equalization 2D"
+    Combo $gPlatformFspPkgTokenSpaceGuid_WRSRT, "Write Slew Rate Training", &EN_DIS,
+        Help "Enables/Disable Write Slew Rate Training"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RDODTT, "Read ODT Training", &EN_DIS,
+        Help "Enables/Disable Read ODT Training"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RDEQT, "Read Equalization Training", &EN_DIS,
+        Help "Enables/Disable Read Equalization Training"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RDAPT, "Read Amplifier Training", &EN_DIS,
+        Help "Enables/Disable Read Amplifier Training"
+    Combo $gPlatformFspPkgTokenSpaceGuid_WRTC2D, "Write Timing Centering 2D", &EN_DIS,
+        Help "Enables/Disable Write Timing Centering 2D"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RDTC2D, "Read Timing Centering 2D", &EN_DIS,
+        Help "Enables/Disable Read Timing Centering 2D"
+    Combo $gPlatformFspPkgTokenSpaceGuid_WRVC2D, "Write Voltage Centering 2D", &EN_DIS,
+        Help "Enables/Disable Write Voltage Centering 2D"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RDVC2D, "Read Voltage Centering 2D", &EN_DIS,
+        Help "Enables/Disable Read Voltage Centering 2D"
+    Combo $gPlatformFspPkgTokenSpaceGuid_CMDVC, "Command Voltage Centering", &EN_DIS,
+        Help "Enables/Disable Command Voltage Centering"
+    Combo $gPlatformFspPkgTokenSpaceGuid_LCT, "Late Command Training", &EN_DIS,
+        Help "Enables/Disable Late Command Training"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RTL, "Round Trip Latency Training", &EN_DIS,
+        Help "Enables/Disable Round Trip Latency Training"
+    Combo $gPlatformFspPkgTokenSpaceGuid_TAT, "Turn Around Timing Training", &EN_DIS,
+        Help "Enables/Disable Turn Around Timing Training"
+    Combo $gPlatformFspPkgTokenSpaceGuid_MEMTST, "Memory Test", &EN_DIS,
+        Help "Enables/Disable Memory Test"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ALIASCHK, "DIMM SPD Alias Test", &EN_DIS,
+        Help "Enables/Disable DIMM SPD Alias Test"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RCVENC1D, "Receive Enable Centering 1D", &EN_DIS,
+        Help "Enables/Disable Receive Enable Centering 1D"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RMC, "Retrain Margin Check", &EN_DIS,
+        Help "Enables/Disable Retrain Margin Check"
+    Combo $gPlatformFspPkgTokenSpaceGuid_WRDSUDT, "Write Drive Strength Up/Dn independently", &EN_DIS,
+        Help "Enables/Disable Write Drive Strength Up/Dn independently"
+    Combo $gPlatformFspPkgTokenSpaceGuid_EccSupport, "ECC Support", &EN_DIS,
+        Help "Enables/Disable ECC Support"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RemapEnable, "Memory Remap", &EN_DIS,
+        Help "Enables/Disable Memory Remap"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RankInterleave, "Rank Interleave support", &EN_DIS,
+        Help "Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at the same time."
+    Combo $gPlatformFspPkgTokenSpaceGuid_EnhancedInterleave, "Enhanced Interleave support", &EN_DIS,
+        Help "Enables/Disable Enhanced Interleave support"
+    Combo $gPlatformFspPkgTokenSpaceGuid_MemoryTrace, "Memory Trace", &EN_DIS,
+        Help "Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of equal size. This option may change TOLUD and REMAP values as needed."
+    Combo $gPlatformFspPkgTokenSpaceGuid_ChHashEnable, "Ch Hash Support", &EN_DIS,
+        Help "Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode"
+    Combo $gPlatformFspPkgTokenSpaceGuid_EnableExtts, "Extern Therm Status", &EN_DIS,
+        Help "Enables/Disable Extern Therm Status"
+    Combo $gPlatformFspPkgTokenSpaceGuid_EnableCltm, "Closed Loop Therm Manage", &EN_DIS,
+        Help "Enables/Disable Closed Loop Therm Manage"
+    Combo $gPlatformFspPkgTokenSpaceGuid_EnableOltm, "Open Loop Therm Manage", &EN_DIS,
+        Help "Enables/Disable Open Loop Therm Manage"
+    Combo $gPlatformFspPkgTokenSpaceGuid_EnablePwrDn, "DDR PowerDown and idle counter", &EN_DIS,
+        Help "Enables/Disable DDR PowerDown and idle counter"
+    Combo $gPlatformFspPkgTokenSpaceGuid_EnablePwrDnLpddr, "DDR PowerDown and idle counter - LPDDR", &EN_DIS,
+        Help "Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)"
+    Combo $gPlatformFspPkgTokenSpaceGuid_UserPowerWeightsEn, "Use user provided power weights, scale factor, and channel power floor values", &EN_DIS,
+        Help "Enables/Disable Use user provided power weights, scale factor, and channel power floor values"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RaplLim2Lock, "RAPL PL Lock", &EN_DIS,
+        Help "Enables/Disable RAPL PL Lock"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RaplLim2Ena, "RAPL PL 2 enable", &EN_DIS,
+        Help "Enables/Disable RAPL PL 2 enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RaplLim1Ena, "RAPL PL 1 enable", &EN_DIS,
+        Help "Enables/Disable RAPL PL 1 enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SrefCfgEna, "SelfRefresh Enable", &EN_DIS,
+        Help "Enables/Disable SelfRefresh Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeatLpddr, "Throttler CKEMin Defeature - LPDDR", &EN_DIS,
+        Help "Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinDefeat, "Throttler CKEMin Defeature", &EN_DIS,
+        Help "Enables/Disable Throttler CKEMin Defeature"
+    Combo $gPlatformFspPkgTokenSpaceGuid_RhPrevention, "Enable RH Prevention", &EN_DIS,
+        Help "Enables/Disable RH Prevention"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ExitOnFailure, "Exit On Failure (MRC)", &EN_DIS,
+        Help "Enables/Disable Exit On Failure (MRC)"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DdrThermalSensor, "LPDDR Thermal Sensor", &EN_DIS,
+        Help "Enables/Disable LPDDR Thermal Sensor"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedClock, "Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP", &EN_DIS,
+        Help "Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4DdpSharedZq, "Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP", &EN_DIS,
+        Help "ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_ChHashMask, "Ch Hash Mask", HEX,
+        Help "Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6"
+             "Valid range: 0x0000 ~ 0x3FFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_BClkFrequency, "Base reference clock value", &gPlatformFspPkgTokenSpaceGuid_BClkFrequency,
+        Help "Base reference clock value, in Hertz(Default is 125Hz)"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit, "Ch Hash Interleaved Bit", &gPlatformFspPkgTokenSpaceGuid_ChHashInterleaveBit,
+        Help "Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_EnergyScaleFact, "Energy Scale Factor", HEX,
+        Help "Energy Scale Factor, Default is 4"
+             "Valid range: 0x01 ~ 0x07"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Idd3n, "EPG DIMM Idd3N", HEX,
+        Help "Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 26"
+             "Valid range: 0x00 ~ 0x7D0"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Idd3p, "EPG DIMM Idd3P", HEX,
+        Help "Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 11"
+             "Valid range: 0x00 ~ 0x7D0"
+    Combo $gPlatformFspPkgTokenSpaceGuid_CMDSR, "CMD Slew Rate Training", &EN_DIS,
+        Help "Enable/Disable CMD Slew Rate Training"
+    Combo $gPlatformFspPkgTokenSpaceGuid_CMDDSEQ, "CMD Drive Strength and Tx Equalization", &EN_DIS,
+        Help "Enable/Disable CMD Drive Strength and Tx Equalization"
+    Combo $gPlatformFspPkgTokenSpaceGuid_CMDNORM, "CMD Normalization", &EN_DIS,
+        Help "Enable/Disable CMD Normalization"
+    Combo $gPlatformFspPkgTokenSpaceGuid_EWRDSEQ, "Early DQ Write Drive Strength and Equalization Training", &EN_DIS,
+        Help "Enable/Disable Early DQ Write Drive Strength and Equalization Training"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RhActProbability, "RH Activation Probability", HEX,
+        Help "RH Activation Probability, Probability value is 1/2^(inputvalue)"
+             "Valid range: 0x01 ~ 0xF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindX, "RAPL PL 2 WindowX", HEX,
+        Help "Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def)"
+             "Valid range: 0x01 ~ 0x03"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim2WindY, "RAPL PL 2 WindowY", HEX,
+        Help "Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def)"
+             "Valid range: 0x01 ~ 0x1F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindX, "RAPL PL 1 WindowX", HEX,
+        Help "Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)"
+             "Valid range: 0x01 ~ 0x03"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim1WindY, "RAPL PL 1 WindowY", HEX,
+        Help "Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)"
+             "Valid range: 0x01 ~ 0x1F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim2Pwr, "RAPL PL 2 Power", HEX,
+        Help "range[0;2^14-1]= [2047.875;0]in W, (222= Def)"
+             "Valid range: 0x0 ~ 0x3FFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RaplLim1Pwr, "RAPL PL 1 Power", HEX,
+        Help "range[0;2^14-1]= [2047.875;0]in W, (0= Def)"
+             "Valid range: 0x0 ~ 0x3FFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm0, "Warm Threshold Ch0 Dimm0", HEX,
+        Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh0Dimm1, "Warm Threshold Ch0 Dimm1", HEX,
+        Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm0, "Warm Threshold Ch1 Dimm0", HEX,
+        Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_WarmThresholdCh1Dimm1, "Warm Threshold Ch1 Dimm1", HEX,
+        Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm0, "Hot Threshold Ch0 Dimm0", HEX,
+        Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh0Dimm1, "Hot Threshold Ch0 Dimm1", HEX,
+        Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm0, "Hot Threshold Ch1 Dimm0", HEX,
+        Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_HotThresholdCh1Dimm1, "Hot Threshold Ch1 Dimm1", HEX,
+        Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm0, "Warm Budget Ch0 Dimm0", HEX,
+        Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh0Dimm1, "Warm Budget Ch0 Dimm1", HEX,
+        Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm0, "Warm Budget Ch1 Dimm0", HEX,
+        Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_WarmBudgetCh1Dimm1, "Warm Budget Ch1 Dimm1", HEX,
+        Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm0, "Hot Budget Ch0 Dimm0", HEX,
+        Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh0Dimm1, "Hot Budget Ch0 Dimm1", HEX,
+        Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm0, "Hot Budget Ch1 Dimm0", HEX,
+        Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_HotBudgetCh1Dimm1, "Hot Budget Ch1 Dimm1", HEX,
+        Help "range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm0, "Idle Energy Ch0Dimm0", HEX,
+        Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)"
+             "Valid range: 0x0 ~ 0x3F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh0Dimm1, "Idle Energy Ch0Dimm1", HEX,
+        Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)"
+             "Valid range: 0x0 ~ 0x3F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm0, "Idle Energy Ch1Dimm0", HEX,
+        Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)"
+             "Valid range: 0x0 ~ 0x3F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_IdleEnergyCh1Dimm1, "Idle Energy Ch1Dimm1", HEX,
+        Help "Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)"
+             "Valid range: 0x0 ~ 0x3F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm0, "PowerDown Energy Ch0Dimm0", HEX,
+        Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)"
+             "Valid range: 0x0 ~ 0x3F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh0Dimm1, "PowerDown Energy Ch0Dimm1", HEX,
+        Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)"
+             "Valid range: 0x0 ~ 0x3F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm0, "PowerDown Energy Ch1Dimm0", HEX,
+        Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)"
+             "Valid range: 0x0 ~ 0x3F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PdEnergyCh1Dimm1, "PowerDown Energy Ch1Dimm1", HEX,
+        Help "PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)"
+             "Valid range: 0x0 ~ 0x3F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm0, "Activate Energy Ch0Dimm0", HEX,
+        Help "Activate Energy Contribution, range[255;0],(172= Def)"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh0Dimm1, "Activate Energy Ch0Dimm1", HEX,
+        Help "Activate Energy Contribution, range[255;0],(172= Def)"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm0, "Activate Energy Ch1Dimm0", HEX,
+        Help "Activate Energy Contribution, range[255;0],(172= Def)"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_ActEnergyCh1Dimm1, "Activate Energy Ch1Dimm1", HEX,
+        Help "Activate Energy Contribution, range[255;0],(172= Def)"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm0, "Read Energy Ch0Dimm0", HEX,
+        Help "Read Energy Contribution, range[255;0],(212= Def)"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh0Dimm1, "Read Energy Ch0Dimm1", HEX,
+        Help "Read Energy Contribution, range[255;0],(212= Def)"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm0, "Read Energy Ch1Dimm0", HEX,
+        Help "Read Energy Contribution, range[255;0],(212= Def)"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RdEnergyCh1Dimm1, "Read Energy Ch1Dimm1", HEX,
+        Help "Read Energy Contribution, range[255;0],(212= Def)"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm0, "Write Energy Ch0Dimm0", HEX,
+        Help "Write Energy Contribution, range[255;0],(221= Def)"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh0Dimm1, "Write Energy Ch0Dimm1", HEX,
+        Help "Write Energy Contribution, range[255;0],(221= Def)"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm0, "Write Energy Ch1Dimm0", HEX,
+        Help "Write Energy Contribution, range[255;0],(221= Def)"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_WrEnergyCh1Dimm1, "Write Energy Ch1Dimm1", HEX,
+        Help "Write Energy Contribution, range[255;0],(221= Def)"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmr, "Throttler CKEMin Timer", HEX,
+        Help "Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Default is 0x30"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CkeRankMapping, "Cke Rank Mapping", HEX,
+        Help "Bits [7:4] - Channel 1, bits [3:0] - Channel 0. <b>0xAA=Default</b> Bit [i] specifies which rank CKE[i] goes to."
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh0, "Rapl Power Floor Ch0", HEX,
+        Help "Power budget ,range[255;0],(0= 5.3W Def)"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RaplPwrFlCh1, "Rapl Power Floor Ch1", HEX,
+        Help "Power budget ,range[255;0],(0= 5.3W Def)"
+             "Valid range: 0x0 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_EnCmdRate, "Command Rate Support", &gPlatformFspPkgTokenSpaceGuid_EnCmdRate,
+        Help "CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Refresh2X, "REFRESH_2X_MODE", &gPlatformFspPkgTokenSpaceGuid_Refresh2X,
+        Help "0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot"
+    Combo $gPlatformFspPkgTokenSpaceGuid_EpgEnable, "Energy Performance Gain", &EN_DIS,
+        Help "Enable/disable(default) Energy Performance Gain."
+    Combo $gPlatformFspPkgTokenSpaceGuid_RhSolution, "Row Hammer Solution", &gPlatformFspPkgTokenSpaceGuid_RhSolution,
+        Help "Type of method used to prevent Row Hammer. Default is Hardware RHP"
+    Combo $gPlatformFspPkgTokenSpaceGuid_UserThresholdEnable, "User Manual Threshold", &EN_DIS,
+        Help "Disabled: Predefined threshold will be used.\nEnabled: User Input will be used."
+    Combo $gPlatformFspPkgTokenSpaceGuid_UserBudgetEnable, "User Manual Budget", &EN_DIS,
+        Help "Disabled: Configuration of memories will defined the Budget value.\nEnabled: User Input will be used."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_TsodTcritMax, "  TcritMax", HEX,
+        Help "Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax has to be greater than THIGHMax .\n Critical temperature will be  TcritMax"
+             "Valid range: 0x0 ~ 0x7F"
+    Combo $gPlatformFspPkgTokenSpaceGuid_TsodEventMode, "Event mode", &EN_DIS,
+        Help "Disable:Comparator mode.\n Enable:Interrupt mode"
+    Combo $gPlatformFspPkgTokenSpaceGuid_TsodEventPolarity, "EVENT polarity", &EN_DIS,
+        Help "Disable:Active LOW.\nEnable:Active HIGH"
+    Combo $gPlatformFspPkgTokenSpaceGuid_TsodCriticalEventOnly, "Critical event only", &EN_DIS,
+        Help "Disable:Trips on alarm or critical.\nEnable:Trips only if criticaal temperature is reached"
+    Combo $gPlatformFspPkgTokenSpaceGuid_TsodEventOutputControl, "Event output control", &EN_DIS,
+        Help "Disable:Event output disable.\nEnable:Event output enabled"
+    Combo $gPlatformFspPkgTokenSpaceGuid_TsodAlarmwindowLockBit, "Alarm window lock bit", &EN_DIS,
+        Help "Disable:Alarm trips are not locked and can be changed.\nEnable:Alarm trips are locked and cannot be changed"
+    Combo $gPlatformFspPkgTokenSpaceGuid_TsodCriticaltripLockBit, "Critical trip lock bit", &EN_DIS,
+        Help "Disable:Critical trip is not locked and can be changed.\nEnable:Critical trip is locked and cannot be changed"
+    Combo $gPlatformFspPkgTokenSpaceGuid_TsodShutdownMode, "Shutdown mode", &EN_DIS,
+        Help "Disable:Temperature sensor enable.\nEnable:Temperature sensor disable"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_TsodThigMax, "ThighMax", HEX,
+        Help "Thigh = ThighMax (Default is 93)"
+             "Valid range: 0x0 ~ 0x80"
+    Combo $gPlatformFspPkgTokenSpaceGuid_TsodManualEnable, "User Manual Thig and Tcrit", &EN_DIS,
+        Help "Disabled(Default): Temperature will be given by the configuration of memories and 1x or 2xrefresh rate.\nEnabled: User Input will define for Thigh and Tcrit."
+    Combo $gPlatformFspPkgTokenSpaceGuid_ForceOltmOrRefresh2x, "Force OLTM or 2X Refresh when needed", &EN_DIS,
+        Help "Disabled(Default): = Force OLTM.\nEnabled: = Force 2x Refresh."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PwdwnIdleCounter, "Pwr Down Idle Timer", HEX,
+        Help "The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means AUTO: 64 for ULX/ULT, 128 for DT/Halo"
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CmdRanksTerminated, "Bitmask of ranks that have CA bus terminated", HEX,
+        Help "Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. <b>0x01=Default, Rank0 is terminating and Rank1 is non-terminating</b>"
+             "Valid range: 0x0 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_GdxcEnable, "GDXC  MOT enable", &EN_DIS,
+        Help "GDXC  MOT enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, "PcdSerialDebugLevel", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel,
+        Help "Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose."
+    Combo $gPlatformFspPkgTokenSpaceGuid_FivrFaults, "Fivr Faults", &EN_DIS,
+        Help "Fivr Faults; 0: Disabled; <b>1: Enabled.</b>"
+    Combo $gPlatformFspPkgTokenSpaceGuid_FivrEfficiency, "Fivr Efficiency", &EN_DIS,
+        Help "Fivr Efficiency Management; 0: Disabled; <b>1: Enabled.</b>"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SafeMode, "Safe Mode Support", &EN_DIS,
+        Help "This option configures the varous items in the IO and MC to be more conservative.(def=Disable)"
+    Combo $gPlatformFspPkgTokenSpaceGuid_CleanMemory, "Ask MRC to clear memory content", &EN_DIS,
+        Help "Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory."
+    Combo $gPlatformFspPkgTokenSpaceGuid_LpDdrDqDqsReTraining, "LpDdrDqDqsReTraining", &EN_DIS,
+        Help "Enables/Disable LpDdrDqDqsReTraining"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PostCodeOutputPort, "Post Code Output Port", HEX,
+        Help "This option configures Post Code Output Port"
+             "Valid range: 0x0 ~ 0xFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RMTLoopCount, "RMTLoopCount", HEX,
+        Help "Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO"
+             "Valid range: 0 ~ 0x20"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_EnBER, "BER Support", HEX,
+        Help "Enable/Disable the Rank Margin Tool interpolation/extrapolation."
+             "Valid range: 0 ~ 0x20"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType, "Dual Dimm Per-Channel Board Type", &gPlatformFspPkgTokenSpaceGuid_DualDimmPerChannelBoardType,
+        Help "Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used to limit maximum frequency for some SKUs."
+    Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4Mixed2DpcLimit, "DDR4 Mixed U-DIMM 2DPC Limitation", &EN_DIS,
+        Help "Enable/Disable Frequency Limitation for DDR4 Mixed Dimm 2DPC Memory Configurations. Disable=0, Enable(Default)=1"
+    Combo $gPlatformFspPkgTokenSpaceGuid_FastBootRmt, "RMT on Fast flow", &EN_DIS,
+        Help "Enable/Disable RMT on Fast flow. Default: Disabled"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ReservedFspmUpdCfl, "CFL Reserved", &EN_DIS,
+        Help "Reserved FspmConfig CFL"
+    Combo $gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot, "Memory Test on Warm Boot", &gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot,
+        Help "Run Base Memory Test on Warm Boot"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_ThrtCkeMinTmrLpddr, "Throttler CKEMin Timer - LPDDR", HEX,
+        Help "Timer value for CKEMin (For LPDDR Only), range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Default is 0x40"
+             "Valid range: 0x0 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_MrcTrainOnWarm, "MRC Force training on Warm", &EN_DIS,
+        Help "Enables/Disable the MRC training on warm boot"
+    Combo $gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt, "Lpddr Dram Odt", &gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt,
+        Help "Override Enable/Disable for the ODT logic for LPDDR3 memory. Default is 2 (AUTO)"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn, "DDR4 Skip Refresh Enable", &gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn,
+        Help "Enable/Disable of DDR4 Temperature Controlled Refresh on DRAM. Default is 1 (Enabled)"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel, "SerialDebugMrcLevel", &gPlatformFspPkgTokenSpaceGuid_SerialDebugMrcLevel,
+        Help "MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwLinkIoControlEnabled, "Enable HD Audio Sndw Link IO Control", HEX,
+        Help "deprecated"
+             "Valid range: 0x00 ~ 0x00"
+    Combo $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode, "Core VF Point Offset Mode", &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetMode,
+        Help "Selects Core Voltage & Frequency Point Offset between Legacy and Selection modes; <b>0: Legacy</b>; 1: Selection."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffset, "Core VF Point Offset", HEX,
+        Help "Array used to specifies the Offset Voltage applied to the each selected Core VF Point. This voltage is specified in millivolts."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix, "Core VF Point Offset Prefix", &gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix,
+        Help "Sets the CoreVfPointOffset value as positive or negative for corresponding core VF Point; <b>0: Positive </b>; 1: Negative."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVfPointRatio, "Core VF Point Ratio", HEX,
+        Help "Array for the each selected Core VF Point to display the ration."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVfPointCount, "Core VF Point Count", HEX,
+        Help "Number of supported Core Voltage & Frequency Point Offset"
+             "Valid range: 0x0 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan, "Skip external display device scanning", &EN_DIS,
+        Help "Enable: Do not scan for external display device, Disable (Default): Scan external display devices"
+    Combo $gPlatformFspPkgTokenSpaceGuid_BdatEnable, "Generate BIOS Data ACPI Table", &EN_DIS,
+        Help "Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ScanExtGfxForLegacyOpRom, "Detect External Graphics device for LegacyOpROM", &EN_DIS,
+        Help "Detect and report if external graphics device only support LegacyOpROM or not (to support CSM auto-enable). Enable(Default)=1, Disable=0"
+    Combo $gPlatformFspPkgTokenSpaceGuid_LockPTMregs, "Lock PCU Thermal Management registers", &EN_DIS,
+        Help "Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed, "DMI Max Link Speed", &gPlatformFspPkgTokenSpaceGuid_DmiMaxLinkSpeed,
+        Help "Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable, "DMI Equalization Phase 2", &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh2Enable,
+        Help "DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): AUTO - Use the current default method"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method, "DMI Gen3 Equalization Phase3", &gPlatformFspPkgTokenSpaceGuid_DmiGen3EqPh3Method,
+        Help "DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:0.", &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh2Enable,
+        Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:1.", &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh2Enable,
+        Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:2.", &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh2Enable,
+        Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable, "Phase2 EQ enable on the PEG 0:1:3.", &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh2Enable,
+        Help "Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:0.", &gPlatformFspPkgTokenSpaceGuid_Peg0Gen3EqPh3Method,
+        Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:1.", &gPlatformFspPkgTokenSpaceGuid_Peg1Gen3EqPh3Method,
+        Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:2.", &gPlatformFspPkgTokenSpaceGuid_Peg2Gen3EqPh3Method,
+        Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method, "Phase3 EQ method on the PEG 0:1:3.", &gPlatformFspPkgTokenSpaceGuid_Peg3Gen3EqPh3Method,
+        Help "PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PegGen3ProgramStaticEq, "Enable/Disable PEG GEN3 Static EQ Phase1 programming", &EN_DIS,
+        Help "Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable  EQ Phase1 Static Presets Programming"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt, "PEG Gen3 SwEq Always Attempt", &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqAlwaysAttempt,
+        Help "Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default): Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test and generate new EQ values every boot, not recommended"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets, "Select number of TxEq presets to test in the PCIe/DMI SwEq", &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqNumberOfPresets,
+        Help "Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the current default method (Default)Auto will test Presets 7, 3, and 5.  It is possible for this default to change over time;using Auto will ensure Reference Code always uses the latest default settings"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest, "Enable use of the Voltage Offset and Centering Test in the PCIe SwEq", &gPlatformFspPkgTokenSpaceGuid_Gen3SwEqEnableVocTest,
+        Help "Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): Use the current default"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PegRxCemTestingMode, "PCIe Rx Compliance Testing Mode", &EN_DIS,
+        Help "Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; it should only be set when doing PCIe compliance testing"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PegRxCemLoopbackLane, "PCIe Rx Compliance Loopback Lane  When PegRxCemTestingMode is Enabled", HEX,
+        Help "the specificied Lane (0 - 15) will be  used for RxCEMLoopback.  Default is Lane 0"
+             "Valid range: 0 ~ 0xF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PegGenerateBdatMarginTable, "Generate PCIe BDAT Margin Table", &EN_DIS,
+        Help "Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin data generation, Enable(0x1): Generate PCIe BDAT margin data"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PegRxCemNonProtocolAwareness, "PCIe Non-Protocol Awareness for Rx Compliance Testing", &EN_DIS,
+        Help "Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for compliance testing"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PegGen3RxCtleOverride, "PCIe Override RxCTLE", &EN_DIS,
+        Help "Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PegGen3Rsvd, "Rsvd", &EN_DIS,
+        Help "Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3RootPortPreset, "PEG Gen3 Root port preset values per lane", HEX,
+        Help "Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointPreset, "PEG Gen3 End port preset values per lane", HEX,
+        Help "Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PegGen3EndPointHint, "PEG Gen3 End port Hint values per lane", HEX,
+        Help "Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterDwellTime, "Jitter Dwell Time for PCIe Gen3 Software Equalization", HEX,
+        Help "Range: 0-65535, default is 1000. @warning Do not change from the default"
+             "Valid range: 0 ~ 0xFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqJitterErrorTarget, "Jitter Error Target for PCIe Gen3 Software Equalization", HEX,
+        Help "Range: 0-65535, default is 1. @warning Do not change from the default"
+             "Valid range: 0 ~ 0xFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocDwellTime, "VOC Dwell Time for PCIe Gen3 Software Equalization", HEX,
+        Help "Range: 0-65535, default is 10000. @warning Do not change from the default"
+             "Valid range: 0 ~ 0xFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Gen3SwEqVocErrorTarget, "VOC Error Target for PCIe Gen3 Software Equalization", HEX,
+        Help "Range: 0-65535, default is 2. @warning Do not change from the default"
+             "Valid range: 0 ~ 0xFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PanelPowerEnable, "Panel Power Enable", &EN_DIS,
+        Help "Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel). 0=Disable, 1(Default)=Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_BdatTestType, "BdatTestType", &gPlatformFspPkgTokenSpaceGuid_BdatTestType,
+        Help "Indicates the type of Memory Training data to populate into the BDAT ACPI table."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SaPreMemTestRsvd, "SaPreMemTestRsvd", &EN_DIS,
+        Help "Reserved for SA Pre-Mem Test"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdSG, "tRd2RdSG", HEX,
+        Help "Delay between Read-to-Read commands in the same Bank Group. 0-Auto, Range 4-54."
+             "Valid range: 0x00 ~ 0x36"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdDG, "tRd2RdDG", HEX,
+        Help "Delay between Read-to-Read commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54."
+             "Valid range: 0x00 ~ 0x36"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdDR, "tRd2RdDR", HEX,
+        Help "Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54."
+             "Valid range: 0x00 ~ 0x36"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2RdDD, "tRd2RdDD", HEX,
+        Help "Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54."
+             "Valid range: 0x00 ~ 0x36"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdSG, "tWr2RdSG", HEX,
+        Help "Delay between Write-to-Read commands in the same Bank Group. 0-Auto, Range 4-86."
+             "Valid range: 0x00 ~ 0x56"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdDG, "tWr2RdDG", HEX,
+        Help "Delay between Write-to-Read commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54."
+             "Valid range: 0x00 ~ 0x36"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdDR, "tWr2RdDR", HEX,
+        Help "Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54."
+             "Valid range: 0x00 ~ 0x36"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2RdDD, "tWr2RdDD", HEX,
+        Help "Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54."
+             "Valid range: 0x00 ~ 0x36"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrSG, "tWr2WrSG", HEX,
+        Help "Delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range 4-54."
+             "Valid range: 0x00 ~ 0x36"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrDG, "tWr2WrDG", HEX,
+        Help "Delay between Write-to-Write commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54."
+             "Valid range: 0x00 ~ 0x36"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrDR, "tWr2WrDR", HEX,
+        Help "Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54."
+             "Valid range: 0x00 ~ 0x36"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tWr2WrDD, "tWr2WrDD", HEX,
+        Help "Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54."
+             "Valid range: 0x00 ~ 0x36"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrSG, "tRd2WrSG", HEX,
+        Help "Delay between Read-to-Write commands in the same Bank Group. 0-Auto, Range 4-54."
+             "Valid range: 0x00 ~ 0x36"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrDG, "tRd2WrDG", HEX,
+        Help "Delay between Read-to-Write commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54."
+             "Valid range: 0x00 ~ 0x36"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrDR, "tRd2WrDR", HEX,
+        Help "Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54."
+             "Valid range: 0x00 ~ 0x36"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tRd2WrDD, "tRd2WrDD", HEX,
+        Help "Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54."
+             "Valid range: 0x00 ~ 0x36"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD_L, "tRRD_L", HEX,
+        Help "Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 31"
+             "Valid range: 0x00 ~ 0x1F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tRRD_S, "tRRD_S", HEX,
+        Help "Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. 0: AUTO, max: 31"
+             "Valid range: 0x00 ~ 0x1F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR_L, "tWTR_L", HEX,
+        Help "Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 60"
+             "Valid range: 0x00 ~ 0x3C"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_tWTR_S, "tWTR_S", HEX,
+        Help "Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only. 0: AUTO, max: 28"
+             "Valid range: 0x00 ~ 0x1C"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SkipCpuReplacementCheck, "Skip CPU replacement check", &EN_DIS,
+        Help "Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check"
+EndPage
+
+Page "PCH 1"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable, "PcdSerialIoUartDebugEnable", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable,
+        Help "Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber, "PcdSerialIoUartNumber - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber,
+        Help "Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode, "PcdSerialIoUartMode - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode,
+        Help "Select SerialIo Uart Controller mode"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartBaudRate, "PcdSerialIoUartBaudRate - FSPT", DEC,
+        Help "Set default BaudRate Supported from 0 - default to 6000000"
+             "Valid range: 0 ~ 6000000"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity, "PcdSerialIoUartParity - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartParity,
+        Help "Set default Parity."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDataBits, "PcdSerialIoUartDataBits - FSPT", HEX,
+        Help "Set default word length. 0: Default, 5,6,7,8"
+             "Valid range: 0x0 ~ 0x08"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits, "PcdSerialIoUartStopBits - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartStopBits,
+        Help "Set default stop bits."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow, "PcdSerialIoUartAutoFlow - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartAutoFlow,
+        Help "Enables UART hardware flow control, CTS and RTS lines."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartPinMux, "PcdSerialIoUartPinMux - FSPT", &gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartPinMux,
+        Help "Applies only to UART0 muxed with CNVI <b> 0 = GPIO C8 to C11 </b> 1 = GPIO F5 - F7 (PCH LP) J5 - J7 (PCH H)"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable, "PcdLpcUartDebugEnable", &gPlatformFspPkgTokenSpaceGuid_PcdLpcUartDebugEnable,
+        Help "Enable to initialize LPC Uart device in FSP."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags, "Debug Interfaces", HEX,
+        Help "Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used."
+             "Valid range: 0x00 ~ 0x3F"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel, "PcdSerialDebugLevel", &gPlatformFspPkgTokenSpaceGuid_PcdSerialDebugLevel,
+        Help "Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, "ISA Serial Base selection", &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase,
+        Help "Select ISA Serial Base address. Default is 0x3F8."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable, "Enable HD Audio DSP", &EN_DIS,
+        Help "Enable/disable HD Audio DSP feature."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi0CsPolarity, "SPI0 Chip Select Polarity", HEX,
+        Help "Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, 1:PchSerialIoCsActiveHigh"
+             "Valid range: 0x00 ~ 0xFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi1CsPolarity, "SPI1 Chip Select Polarity", HEX,
+        Help "Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, 1:PchSerialIoCsActiveHigh"
+             "Valid range: 0x00 ~ 0xFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi2CsPolarity, "SPI2 Chip Select Polarity", HEX,
+        Help "Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, 1:PchSerialIoCsActiveHigh"
+             "Valid range: 0x00 ~ 0xFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi0CsEnable, "SPI0 Chip Select Enable", HEX,
+        Help "0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled"
+             "Valid range: 0x00 ~ 0xFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi1CsEnable, "SPI1 Chip Select Enable", HEX,
+        Help "0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled"
+             "Valid range: 0x00 ~ 0xFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpi2CsEnable, "SPI2 Chip Select Enable", HEX,
+        Help "0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled"
+             "Valid range: 0x00 ~ 0xFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiMode, "SPIn Device Mode", HEX,
+        Help "Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden"
+             "Valid range: 0x00 ~ 0xFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiDefaultCsOutput, "SPIn Default Chip Select Output", HEX,
+        Help "Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available options: 0:CS0, 1:CS1"
+             "Valid range: 0x00 ~ 0xFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cPadsTermination, "PCH SerialIo I2C Pads Termination", HEX,
+        Help "0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoI2cMode, "I2Cn Device Mode", HEX,
+        Help "Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartMode, "UARTn Device Mode", HEX,
+        Help "Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit"
+             "Valid range: 0x00 ~ 0xFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartBaudRate, "Default BaudRate for each Serial IO UART", HEX,
+        Help "Set default BaudRate Supported from 0 - default to 6000000"
+             "Valid range: 0x0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartParity, "Default ParityType for each Serial IO UART", HEX,
+        Help "Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity"
+             "Valid range: 0x0 ~ 0xFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDataBits, "Default DataBits for each Serial IO UART", HEX,
+        Help "Set default word length. 0: Default, 5,6,7,8"
+             "Valid range: 0x0 ~ 0xFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartStopBits, "Default StopBits for each Serial IO UART", HEX,
+        Help "Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits"
+             "Valid range: 0x0 ~ 0xFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPowerGating, "Power Gating mode for each Serial IO UART that works in COM mode", HEX,
+        Help "Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto"
+             "Valid range: 0x0 ~ 0xFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDmaEnable, "Enable Dma for each Serial IO UART that supports it", HEX,
+        Help "Set DMA/PIO mode. 0: Disabled, 1: Enabled"
+             "Valid range: 0x0 ~ 0xFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartAutoFlow, "Enables UART hardware flow control, CTS and RTS lines", HEX,
+        Help "Enables UART hardware flow control, CTS and RTS lines."
+             "Valid range: 0x00 ~ 0xFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartPinMux, "Serial IO UART Pin Mux", HEX,
+        Help "Applies only to UART0 muxed with CNVI <b> 0 = GPIO C8 to C11 </b> 1 = GPIO F5 - F7 (PCH LP) J5 - J7 (PCH H)"
+             "Valid range: 0x00 ~ 0xFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber, "UART Number For Debug Purpose", &gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber,
+        Help "UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDbg2, "Serial IO UART DBG2 table", HEX,
+        Help "Enable or disable Serial Io UART DBG2 table, default is Disable; <b>0: Disable;</b> 1: Enable."
+             "Valid range: 0x00 ~ 0xFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ScsEmmcEnabled, "Enable eMMC Controller", &EN_DIS,
+        Help "Enable/disable eMMC Controller."
+    Combo $gPlatformFspPkgTokenSpaceGuid_ScsEmmcHs400Enabled, "Enable eMMC HS400 Mode", &EN_DIS,
+        Help "Enable eMMC HS400 Mode."
+    Combo $gPlatformFspPkgTokenSpaceGuid_ScsSdCardEnabled, "Enable SdCard Controller", &EN_DIS,
+        Help "Enable/disable SD Card Controller."
+    Combo $gPlatformFspPkgTokenSpaceGuid_ShowSpiController, "Show SPI controller", &EN_DIS,
+        Help "Enable/disable to show SPI controller."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataSalpSupport, "Enable SATA SALP Support", &EN_DIS,
+        Help "Enable/disable SATA Aggressive Link Power Management."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsEnable, "Enable SATA ports", HEX,
+        Help "Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlp, "Enable SATA DEVSLP Feature", HEX,
+        Help "Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PortUsb20Enable, "Enable USB2 ports", HEX,
+        Help "Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PortUsb30Enable, "Enable USB3 ports", HEX,
+        Help "Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_XdciEnable, "Enable xDCI controller", &EN_DIS,
+        Help "Enable/disable to xDCI controller."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_DevIntConfigPtr, "Address of PCH_DEVICE_INTERRUPT_CONFIG table.", HEX,
+        Help "The address of the table of PCH_DEVICE_INTERRUPT_CONFIG."
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_NumOfDevIntConfig, "Number of DevIntConfig Entry", HEX,
+        Help "Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr must not be NULL."
+             "Valid range: 0x00 ~ 0x40"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PxRcConfig, "PIRQx to IRQx Map Config", HEX,
+        Help "PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy 8259 PCI mode."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_GpioIrqRoute, "Select GPIO IRQ Route", HEX,
+        Help "GPIO IRQ Select. The valid value is 14 or 15."
+             "Valid range: 0x00 ~ 0x0F"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SciIrqSelect, "Select SciIrqSelect", HEX,
+        Help "SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only."
+             "Valid range: 0x00 ~ 0x17"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_TcoIrqSelect, "Select TcoIrqSelect", HEX,
+        Help "TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23."
+             "Valid range: 0x00 ~ 0x17"
+    Combo $gPlatformFspPkgTokenSpaceGuid_TcoIrqEnable, "Enable/Disable Tco IRQ", &EN_DIS,
+        Help "Enable/disable TCO IRQ"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTableEntryNum, "PCH HDA Verb Table Entry Number", HEX,
+        Help "Number of Entries in Verb Table."
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaVerbTablePtr, "PCH HDA Verb Table Pointer", HEX,
+        Help "Pointer to Array of pointers to Verb Table."
+             "Valid range: 0x0 ~ 0xFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataEnable, "Enable SATA", &EN_DIS,
+        Help "Enable/disable SATA controller."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataMode, "SATA Mode", &gPlatformFspPkgTokenSpaceGuid_SataMode,
+        Help "Select SATA controller working mode."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfePetxiset, "USB Per Port HS Preemphasis Bias", HEX,
+        Help "USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfeTxiset, "USB Per Port HS Transmitter Bias", HEX,
+        Help "USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfePredeemp, "USB Per Port HS Transmitter Emphasis", HEX,
+        Help "USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2AfePehalfbit, "USB Per Port Half Bit Pre-emphasis", HEX,
+        Help "USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SmbusEnable, "Enable SMBus", &EN_DIS,
+        Help "Enable/disable SMBus controller."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent, "Platform Debug Consent", &gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent,
+        Help "To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. Enabling this BIOS option may alter the default value of other debug-related BIOS options. Note: DCI OOB (aka BSSB) uses CCA probe; [DCI OOB+DbC] and [USB2 DbC] have the same setting"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg, "USB3 Type-C UFP2DFP Kernel/Platform Debug Support", &gPlatformFspPkgTokenSpaceGuid_DciUsb3TypecUfpDbg,
+        Help "This BIOS option enables kernel and platform debug for USB3 interface over a UFP Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode, "PCH Trace Hub Mode", &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMode,
+        Help "Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size, "PCH Trace Hub Memory Region 0 buffer Size", &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg0Size,
+        Help "Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size, "PCH Trace Hub Memory Region 1 buffer Size", &gPlatformFspPkgTokenSpaceGuid_PchTraceHubMemReg1Size,
+        Help "Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaEnable, "Enable Intel HD Audio (Azalia)", &EN_DIS,
+        Help "0: Disable, 1: Enable (Default) Azalia controller"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchIshEnable, "Enable PCH ISH Controller", &EN_DIS,
+        Help "0: Disable, 1: Enable (Default) ISH Controller"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtleEnable, "Enable PCH HSIO PCIE Rx Set Ctle", HEX,
+        Help "Enable PCH PCIe Gen 3 Set CTLE Value."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmphEnable, "Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment", HEX,
+        Help "Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port."
+             "Valid range: 0x00 ~ 0x01010101010101010101"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDeEmph, "USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting", HEX,
+        Help "USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioRxSetCtle, "PCH HSIO PCIE Rx Set Ctle Value", HEX,
+        Help "PCH PCIe Gen 3 Set CTLE Value."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmpEnable, "Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment", HEX,
+        Help "Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port."
+             "Valid range: 0x00 ~ 0x01010101010101010101"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxDownscaleAmp, "USB 3.0 TX Output Downscale Amplitude Adjustment", HEX,
+        Help "USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default = 00h</b>. One byte for each port."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrOverrideEnable, "Enable xHCI LTR override", &EN_DIS,
+        Help "Enables override of recommended LTR values for xHCI"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmpEnable, "Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override", HEX,
+        Help "0: Disable; 1: Enable."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrHighIdleTimeOverride, "xHCI High Idle Time LTR override", HEX,
+        Help "Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrMediumIdleTimeOverride, "xHCI Medium Idle Time LTR override", HEX,
+        Help "Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbLtrLowIdleTimeOverride, "xHCI Low Idle Time LTR override", HEX,
+        Help "Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchLanEnable, "Enable LAN", &EN_DIS,
+        Help "Enable/disable LAN controller."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHda, "Enable HD Audio Link", &EN_DIS,
+        Help "Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic0, "Enable HD Audio DMIC0 Link", &EN_DIS,
+        Help "Enable/disable HD Audio DMIC0 link. Muxed with SNDW4."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic1, "Enable HD Audio DMIC1 Link", &EN_DIS,
+        Help "Enable/disable HD Audio DMIC1 link. Muxed with SNDW3."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp0, "Enable HD Audio SSP0 Link", &EN_DIS,
+        Help "Enable/disable HD Audio SSP0/I2S link. Muxed with HDA."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp1, "Enable HD Audio SSP1 Link", &EN_DIS,
+        Help "Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp2, "Enable HD Audio SSP2 Link", &EN_DIS,
+        Help "Enable/disable HD Audio SSP2/I2S link."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw1, "Enable HD Audio SoundWire#1 Link", &EN_DIS,
+        Help "Enable/disable HD Audio SNDW1 link. Muxed with HDA."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw2, "Enable HD Audio SoundWire#2 Link", &EN_DIS,
+        Help "Enable/disable HD Audio SNDW2 link. Muxed with SSP1."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw3, "Enable HD Audio SoundWire#3 Link", &EN_DIS,
+        Help "Enable/disable HD Audio SNDW3 link. Muxed with DMIC1."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw4, "Enable HD Audio SoundWire#4 Link", &EN_DIS,
+        Help "Enable/disable HD Audio SNDW4 link. Muxed with DMIC0."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwBufferRcomp, "Soundwire Clock Buffer GPIO RCOMP Setting", &EN_DIS,
+        Help "0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DownscaleAmp, "PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value", HEX,
+        Help "PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPtmMask, "PTM for PCIE RP Mask", HEX,
+        Help "Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on."
+             "Valid range: 0x00 ~ 0x00FFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDpcMask, "DPC for PCIE RP Mask", HEX,
+        Help "Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on."
+             "Valid range: 0x00 ~ 0x00FFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDpcExtensionsMask, "DPC Extensions PCIE RP Mask", HEX,
+        Help "Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on."
+             "Valid range: 0x00 ~ 0x00FFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_UsbPdoProgramming, "USB PDO Programming", &EN_DIS,
+        Help "Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming during later phase. 1: enable, 0: disable"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PmcPowerButtonDebounce, "Power button debounce configuration", HEX,
+        Help "Debounce time for PWRBTN in microseconds. For values not supported by HW, they will be rounded down to closest supported on. 0: disable, 250-1024000us: supported range"
+             "Valid range: 0x00 ~ 0x009C4000"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiBmeMasterSlaveEnabled, "PCH eSPI Master and Slave BME enabled", &EN_DIS,
+        Help "PCH eSPI Master and Slave BME enabled"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataRstLegacyOrom, "PCH SATA use RST Legacy OROM", &EN_DIS,
+        Help "Use PCH SATA RST Legacy OROM when CSM is Enabled"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_TraceHubMemBase, "Trace Hub Memory Base", HEX,
+        Help "If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub memory is configured properly."
+             "Valid range: 0x0 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmpEnable, "Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override", HEX,
+        Help "0: Disable; 1: Enable."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PmcDbgMsgEn, "PMC Debug Message Enable", &EN_DIS,
+        Help "When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinPtr, "Pointer of ChipsetInit Binary", HEX,
+        Help "ChipsetInit Binary Pointer."
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_ChipsetInitBinLen, "Length of ChipsetInit Binary", HEX,
+        Help "ChipsetInit Binary Length."
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ScsUfsEnabled, "Enable Ufs Controller", &EN_DIS,
+        Help "Enable/disable Ufs 2.0 Controller."
+    Combo $gPlatformFspPkgTokenSpaceGuid_CnviMode, "CNVi Configuration", &gPlatformFspPkgTokenSpaceGuid_CnviMode,
+        Help "This option allows for automatic detection of Connectivity Solution. [Auto Detection] assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi."
+    Combo $gPlatformFspPkgTokenSpaceGuid_CnviBtCore, "CNVi BT Core", &EN_DIS,
+        Help "Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE"
+    Combo $gPlatformFspPkgTokenSpaceGuid_CnviBtAudioOffload, "CNVi BT Audio Offload", &EN_DIS,
+        Help "Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SdCardPowerEnableActiveHigh, "SdCard power enable polarity", &gPlatformFspPkgTokenSpaceGuid_SdCardPowerEnableActiveHigh,
+        Help "Choose SD_PWREN# polarity"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchUsb2PhySusPgEnable, "PCH USB2 PHY Power Gating enable", &EN_DIS,
+        Help "1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY Sus Well PG"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchUsbOverCurrentEnable, "PCH USB OverCurrent mapping enable", &EN_DIS,
+        Help "1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin mapping allow for NOA usage of OC pins"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiLgmrEnable, "Espi Lgmr Memory Range decode", &EN_DIS,
+        Help "This option enables or disables espi lgmr"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DownscaleAmp, "PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value", HEX,
+        Help "PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHotEnable, "PCHHOT# pin", &EN_DIS,
+        Help "Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataLedEnable, "SATA LED", &EN_DIS,
+        Help "SATA LED indicating SATA controller activity. 0: disable, 1: enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchPmVrAlert, "VRAlert# Pin", &EN_DIS,
+        Help "When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0VmRuntimeControl, "SLP_S0 VM Dynamic Control", &EN_DIS,
+        Help "SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Vm070VSupport, "SLP_S0 VM 0.70V Support", &EN_DIS,
+        Help "SLP_S0 Voltage Margining  0.70V Support Policy. 0: disable, 1: enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Vm075VSupport, "SLP_S0 VM 0.75V Support", &EN_DIS,
+        Help "SLP_S0 Voltage Margining  0.75V Support Policy. 0: disable, 1: enable"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotImplemented, "PCH PCIe root port connection type", HEX,
+        Help "0: built-in device, 1:slot"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmpEnable, "Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override", HEX,
+        Help "0: Disable; 1: Enable."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcUsage, "Usage type for ClkSrc", HEX,
+        Help "0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieClkSrcClkReq, "ClkReq-to-ClkSrc mapping", HEX,
+        Help "Number of ClkReq signal assigned to ClkSrc"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen3DownscaleAmp, "PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value", HEX,
+        Help "PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAcsEnabled, "PCIE RP Access Control Services Extended Capability", HEX,
+        Help "Enable/Disable PCIE RP Access Control Services Extended Capability"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmphEnable, "Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override", HEX,
+        Help "0: Disable; 1: Enable."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableCpm, "PCIE RP Clock Power Management", HEX,
+        Help "Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen1DeEmph, "PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value", HEX,
+        Help "PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDetectTimeoutMs, "PCIE RP Detect Timeout Ms", HEX,
+        Help "The number of milliseconds within 0~65535 in reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5Enable, "Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override", HEX,
+        Help "0: Disable; 1: Enable."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph3p5, "PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value", HEX,
+        Help "PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PmcModPhySusPgEnable, "ModPHY SUS Power Domain Dynamic Gating", &EN_DIS,
+        Help "Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on PCH-H. 0: disable, 1: enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SlpS0WithGbeSupport, "SlpS0WithGbeSupport", &EN_DIS,
+        Help "Enable/Disable SLP_S0 with GBE Support. Default is 0 for PCH-LP, WHL V0 Stepping CPU and 1 for PCH-H Series. 0: Disable, 1: Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchPwrOptEnable, "Enable Power Optimizer", &EN_DIS,
+        Help "Enable DMI Power Optimizer on PCH side."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchWriteProtectionEnable, "PCH Flash Protection Ranges Write Enble", HEX,
+        Help "Write or erase is blocked by hardware."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchReadProtectionEnable, "PCH Flash Protection Ranges Read Enble", HEX,
+        Help "Read is blocked by hardware."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0Enable, "Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override", HEX,
+        Help "0: Disable; 1: Enable."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeLimit, "PCH Protect Range Limit", HEX,
+        Help "Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchProtectedRangeBase, "PCH Protect Range Base", HEX,
+        Help "Left shifted address by 12 bits with address bits 11:0 are assumed to be 0."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieHsioTxGen2DeEmph6p0, "PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value", HEX,
+        Help "PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaPme, "Enable Pme", &EN_DIS,
+        Help "Enable Azalia wake-on-ring."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType, "VC Type", &gPlatformFspPkgTokenSpaceGuid_PchHdaVcType,
+        Help "Virtual Channel Type Select: 0: VC0, 1: VC1."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency, "HD Audio Link Frequency", &gPlatformFspPkgTokenSpaceGuid_PchHdaLinkFrequency,
+        Help "HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency, "iDisp-Link Frequency", &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkFrequency,
+        Help "iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode, "iDisp-Link T-mode", &gPlatformFspPkgTokenSpaceGuid_PchHdaIDispLinkTmode,
+        Help "iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance, "Universal Audio Architecture compliance for DSP enabled system", &EN_DIS,
+        Help "0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported)."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaIDispCodecDisconnect, "iDisplay Audio Codec disconnection", &EN_DIS,
+        Help "0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioFilterSel, "USB LFPS Filter selection", HEX,
+        Help "For each byte bits 2:0 are for p, bits 4:6 are for n. 0h:1.6ns, 1h:2.4ns, 2h:3.2ns, 3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchIoApicEntry24_119, "Enable PCH Io Apic Entry 24-119", &EN_DIS,
+        Help "0: Disable; 1: Enable."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchIoApicId, "PCH Io Apic ID", HEX,
+        Help "This member determines IOAPIC ID. Default is 0x02."
+             "Valid range: 0x0 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchIshSpiGpioAssign, "Enable PCH ISH SPI GPIO pins assigned", &EN_DIS,
+        Help "0: Disable; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchIshUart0GpioAssign, "Enable PCH ISH UART0 GPIO pins assigned", &EN_DIS,
+        Help "0: Disable; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchIshUart1GpioAssign, "Enable PCH ISH UART1 GPIO pins assigned", &EN_DIS,
+        Help "0: Disable; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchIshI2c0GpioAssign, "Enable PCH ISH I2C0 GPIO pins assigned", &EN_DIS,
+        Help "0: Disable; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchIshI2c1GpioAssign, "Enable PCH ISH I2C1 GPIO pins assigned", &EN_DIS,
+        Help "0: Disable; 1: Enable."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX,
+        Help "0: Disable; 1: Enable."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchIshI2c2GpioAssign, "Enable PCH ISH I2C2 GPIO pins assigned", &EN_DIS,
+        Help "0: Disable; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp0GpioAssign, "Enable PCH ISH GP_0 GPIO pin assigned", &EN_DIS,
+        Help "0: Disable; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp1GpioAssign, "Enable PCH ISH GP_1 GPIO pin assigned", &EN_DIS,
+        Help "0: Disable; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp2GpioAssign, "Enable PCH ISH GP_2 GPIO pin assigned", &EN_DIS,
+        Help "0: Disable; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp3GpioAssign, "Enable PCH ISH GP_3 GPIO pin assigned", &EN_DIS,
+        Help "0: Disable; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp4GpioAssign, "Enable PCH ISH GP_4 GPIO pin assigned", &EN_DIS,
+        Help "0: Disable; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp5GpioAssign, "Enable PCH ISH GP_5 GPIO pin assigned", &EN_DIS,
+        Help "0: Disable; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp6GpioAssign, "Enable PCH ISH GP_6 GPIO pin assigned", &EN_DIS,
+        Help "0: Disable; 1: Enable."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen1EqBoostMag, "PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX,
+        Help "PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchIshGp7GpioAssign, "Enable PCH ISH GP_7 GPIO pin assigned", &EN_DIS,
+        Help "0: Disable; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchIshPdtUnlock, "PCH ISH PDT Unlock Msg", &EN_DIS,
+        Help "0: False; 1: True."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchLanLtrEnable, "Enable PCH Lan LTR capabilty of PCH internal LAN", &EN_DIS,
+        Help "0: Disable; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosLock, "Enable LOCKDOWN BIOS LOCK", &EN_DIS,
+        Help "Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchCrid, "PCH Compatibility Revision ID", &EN_DIS,
+        Help "This member describes whether or not the CRID feature of PCH should be enabled."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownRtcMemoryLock, "RTC CMOS MEMORY LOCK", &EN_DIS,
+        Help "Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug, "Enable PCIE RP HotPlug", HEX,
+        Help "Indicate whether the root port is hot plug available."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX,
+        Help "0: Disable; 1: Enable."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMag, "PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX,
+        Help "PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX,
+        Help "0: Disable; 1: Enable."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPmSci, "Enable PCIE RP Pm Sci", HEX,
+        Help "Indicate whether the root port power manager SCI is enabled."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen3EqBoostMag, "PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value", HEX,
+        Help "PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmpEnable, "Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX,
+        Help "0: Disable; 1: Enable."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DownscaleAmp, "PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value", HEX,
+        Help "PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpExtSync, "Enable PCIE RP Ext Sync", HEX,
+        Help "Indicate whether the extended synch is enabled."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmpEnable, "Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX,
+        Help "0: Disable; 1: Enable."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DownscaleAmp, "PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value", HEX,
+        Help "PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmpEnable, "Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override", HEX,
+        Help "0: Disable; 1: Enable."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpTransmitterHalfSwing, "Enable PCIE RP Transmitter Half Swing", HEX,
+        Help "Indicate whether the Transmitter Half Swing is enabled."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DownscaleAmp, "PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value", HEX,
+        Help "PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmphEnable, "Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX,
+        Help "0: Disable; 1: Enable."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen1DeEmph, "PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting", HEX,
+        Help "PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpClkReqDetect, "Enable PCIE RP Clk Req Detect", HEX,
+        Help "Probe CLKREQ# signal before enabling CLKREQ# based power management."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmphEnable, "Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX,
+        Help "0: Disable; 1: Enable."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen2DeEmph, "PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting", HEX,
+        Help "PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmphEnable, "Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override", HEX,
+        Help "0: Disable; 1: Enable."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAdvancedErrorReporting, "PCIE RP Advanced Error Report", HEX,
+        Help "Indicate whether the Advanced Error Reporting is enabled."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioTxGen3DeEmph, "PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting", HEX,
+        Help "PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchLpcEnhancePort8xhDecoding, "PCH LPC Enhance the port 8xh decoding", &EN_DIS,
+        Help "Original LPC only decodes one byte of port 80h."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchPort80Route, "PCH Port80 Route", &EN_DIS,
+        Help "Control where the Port 80h cycles are sent, 0: LPC; 1: PCI."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SmbusArpEnable, "Enable SMBus ARP support", &EN_DIS,
+        Help "Enable SMBus ARP support."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchNumRsvdSmbusAddresses, "Number of RsvdSmbusAddressTable.", HEX,
+        Help "The number of elements in the RsvdSmbusAddressTable."
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchSmbusIoBase, "SMBUS Base Address", HEX,
+        Help "SMBUS Base Address (IO space)."
+             "Valid range: 0x00 ~ 0xFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieImrSize, "Size of PCIe IMR.", HEX,
+        Help "Size of PCIe IMR in megabytes"
+             "Valid range: 0x00 ~ 0xFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_RsvdSmbusAddressTablePtr, "Point of RsvdSmbusAddressTable", HEX,
+        Help "Array of addresses reserved for non-ARP-capable SMBus devices."
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpEnableMask, "Enable PCIE RP Mask", HEX,
+        Help "Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on."
+             "Valid range: 0x00 ~ 0x00FFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpUnsupportedRequestReport, "PCIE RP Unsupported Request Report", HEX,
+        Help "Indicate whether the Unsupported Request Report is enabled."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PcieImrEnabled, "Enable PCIe IMR", &EN_DIS,
+        Help "0:Disable, 1:Enable"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_ImrRpSelection, "Root port number for IMR.", HEX,
+        Help "Root port number for IMR."
+             "Valid range: 0x00 ~ 0x18"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchSmbAlertEnable, "Enable SMBus Alert Pin", &EN_DIS,
+        Help "Enable SMBus Alert Pin."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags, "Debug Interfaces", HEX,
+        Help "Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used."
+             "Valid range: 0x00 ~ 0x3F"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber, "Serial Io Uart Debug Controller Number", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber,
+        Help "Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugAutoFlow, "Serial Io Uart Debug Auto Flow", &EN_DIS,
+        Help "Enables UART hardware flow control, CTS and RTS lines."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugBaudRate, "Serial Io Uart Debug BaudRate", DEC,
+        Help "Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000"
+             "Valid range: 0 ~ 6000000"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity, "Serial Io Uart Debug Parity", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugParity,
+        Help "Set default Parity."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits, "Serial Io Uart Debug Stop Bits", &gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugStopBits,
+        Help "Set default stop bits."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugDataBits, "Serial Io Uart Debug Data Bits", HEX,
+        Help "Set default word length. 0: Default, 5,6,7,8"
+             "Valid range: 0x0 ~ 0x08"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspEnable, "Enable HD Audio DSP", &EN_DIS,
+        Help "Enable/disable HD Audio DSP feature."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaVcType, "VC Type", &gPlatformFspPkgTokenSpaceGuid_PchHdaVcType,
+        Help "Virtual Channel Type Select: 0: VC0, 1: VC1."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaDspUaaCompliance, "Universal Audio Architecture compliance for DSP enabled system", &EN_DIS,
+        Help "0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported)."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkHda, "Enable HD Audio Link", &EN_DIS,
+        Help "Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic0, "Enable HD Audio DMIC0 Link", &EN_DIS,
+        Help "Deprecated."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkDmic1, "Enable HD Audio DMIC1 Link", &EN_DIS,
+        Help "Deprecated."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp0, "Enable HD Audio SSP0 Link", &EN_DIS,
+        Help "Enable/disable HD Audio SSP0/I2S link. Muxed with HDA."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp1, "Enable HD Audio SSP1 Link", &EN_DIS,
+        Help "Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpFatalErrorReport, "PCIE RP Fatal Error Report", HEX,
+        Help "Indicate whether the Fatal Error Report is enabled."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSsp2, "Enable HD Audio SSP2 Link", &EN_DIS,
+        Help "Enable/disable HD Audio SSP2/I2S link."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw1, "Enable HD Audio SoundWire#1 Link", &EN_DIS,
+        Help "Enable/disable HD Audio SNDW1 link. Muxed with HDA."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw2, "Enable HD Audio SoundWire#2 Link", &EN_DIS,
+        Help "Enable/disable HD Audio SNDW2 link. Muxed with SSP1."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw3, "Enable HD Audio SoundWire#3 Link", &EN_DIS,
+        Help "Enable/disable HD Audio SNDW3 link. Muxed with DMIC1."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaAudioLinkSndw4, "Enable HD Audio SoundWire#4 Link", &EN_DIS,
+        Help "Enable/disable HD Audio SNDW4 link. Muxed with DMIC0."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwBufferRcomp, "Soundwire Clock Buffer GPIO RCOMP Setting", &EN_DIS,
+        Help "0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance."
+    Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMem, "ReservedPchPreMem", &EN_DIS,
+        Help "Reserved for Pch Pre-Mem"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase, "ISA Serial Base selection", &gPlatformFspPkgTokenSpaceGuid_PcdIsaSerialUartBase,
+        Help "Select ISA Serial Base address. Default is 0x3F8."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNoFatalErrorReport, "PCIE RP No Fatal Error Report", HEX,
+        Help "Indicate whether the No Fatal Error Report is enabled."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpCorrectableErrorReport, "PCIE RP Correctable Error Report", HEX,
+        Help "Indicate whether the Correctable Error Report is enabled."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnFatalError, "PCIE RP System Error On Fatal Error", HEX,
+        Help "Indicate whether the System Error on Fatal Error is enabled."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnNonFatalError, "PCIE RP System Error On Non Fatal Error", HEX,
+        Help "Indicate whether the System Error on Non Fatal Error is enabled."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSystemErrorOnCorrectableError, "PCIE RP System Error On Correctable Error", HEX,
+        Help "Indicate whether the System Error on Correctable Error is enabled."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpMaxPayload, "PCIE RP Max Payload", HEX,
+        Help "Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioRxTuningParameters, "PCH USB3 RX HSIO Tuning parameters", HEX,
+        Help "Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for controlling the input offset"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioRxTuningEnable, "PCH USB3 HSIO Rx Tuning Enable", HEX,
+        Help "Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable, 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPcieSpeed, "PCIE RP Pcie Speed", HEX,
+        Help "Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED)."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpGen3EqPh3Method, "PCIE RP Gen3 Equalization Phase Method", HEX,
+        Help "PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; 1: hardware equalization; 4: Fixed Coeficients."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPhysicalSlotNumber, "PCIE RP Physical Slot Number", HEX,
+        Help "Indicates the slot number for the root port. Default is the value as root port index."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpCompletionTimeout, "PCIE RP Completion Timeout", HEX,
+        Help "The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpAspm, "PCIE RP Aspm", HEX,
+        Help "The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpL1Substates, "PCIE RP L1 Substates", HEX,
+        Help "The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrEnable, "PCIE RP Ltr Enable", HEX,
+        Help "Latency Tolerance Reporting Mechanism."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrConfigLock, "PCIE RP Ltr Config Lock", HEX,
+        Help "0: Disable; 1: Enable."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_TotalFlashSize, "TotalFlashSize", HEX,
+        Help "Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable"
+             "Valid range: 0x00 ~ 0xFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_BiosSize, "BiosSize", HEX,
+        Help "Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable"
+             "Valid range: 0x00 ~ 0xFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_TxtAcheckRequest, "TxtAcheckRequest", &EN_DIS,
+        Help "Enable/Disable. When Enabled, it will forcing calling TXT Acheck once."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SecurityTestRsvd, "SecurityTestRsvd", &EN_DIS,
+        Help "Reserved for SA Pre-Mem Test"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SmbusDynamicPowerGating, "Smbus dynamic power gating", &EN_DIS,
+        Help "Disable or Enable Smbus dynamic power gating."
+    Combo $gPlatformFspPkgTokenSpaceGuid_WdtDisableAndLock, "Disable and Lock Watch Dog Register", &EN_DIS,
+        Help "Set 1 to clear WDT status, then disable and lock WDT registers."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SmbusSpdWriteDisable, "SMBUS SPD Write Disable", &EN_DIS,
+        Help "Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set."
+    Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMemTest, "ReservedPchPreMemTest", &EN_DIS,
+        Help "Reserved for Pch Pre-Mem Test"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCm, "PCIE Eq Ph3 Lane Param Cm", HEX,
+        Help "PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DidInitStat, "Force ME DID Init Status", &EN_DIS,
+        Help "Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set ME DID init stat value"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DisableCpuReplacedPolling, "CPU Replaced Polling Disable", &EN_DIS,
+        Help "Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SendDidMsg, "ME DID Message", &EN_DIS,
+        Help "Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent the DID message from being sent)"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DisableMessageCheck, "Check HECI message before send", &EN_DIS,
+        Help "Test, 0: disable, 1: enable, Enable/Disable message check."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SkipMbpHob, "Skip MBP HOB", &EN_DIS,
+        Help "Test, 0: disable, 1: enable, Enable/Disable MOB HOB."
+    Combo $gPlatformFspPkgTokenSpaceGuid_HeciCommunication2, "HECI2 Interface Communication", &EN_DIS,
+        Help "Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space."
+    Combo $gPlatformFspPkgTokenSpaceGuid_KtDeviceEnable, "Enable KT device", &EN_DIS,
+        Help "Test, 0: disable, 1: enable, Enable or Disable KT device."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCp, "PCIE Eq Ph3 Lane Param Cp", HEX,
+        Help "PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCm, "PCIE Sw Eq CoeffList Cm", HEX,
+        Help "PCH_PCIE_EQ_PARAM. Coefficient C-1. The values depend on PcieNumOfCoefficients, the default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCp, "PCIE Sw Eq CoeffList Cp", HEX,
+        Help "PCH_PCIE_EQ_PARAM. Coefficient C+1.The values depend on PcieNumOfCoefficients, the default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PcieDisableRootPortClockGating, "PCIE Disable RootPort Clock Gating", &EN_DIS,
+        Help "Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules. 0: Disable; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PcieEnablePeerMemoryWrite, "PCIE Enable Peer Memory Write", &EN_DIS,
+        Help "This member describes whether Peer Memory Writes are enabled on the platform."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PcieComplianceTestMode, "PCIE Compliance Test Mode", &EN_DIS,
+        Help "Compliance Test Mode shall be enabled when using Compliance Load Board."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpFunctionSwap, "PCIE Rp Function Swap", &EN_DIS,
+        Help "Allows BIOS to use root port function number swapping when root port of function 0 is disabled."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_TetonGlacierCR, "Teton Glacier Cycle Router", HEX,
+        Help "Specify to which cycle router Teton Glacier is connected, it is valid only when Teton Glacier support is enabled. Default is 0 for CNP-H system and 1 for CNP-LP system "
+             "Valid range: 0x0 ~ 0x02"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchPmPmeB0S5Dis, "PCH Pm PME_B0_S5_DIS", &EN_DIS,
+        Help "When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PcieRpImrEnabled, "PCIE IMR", &EN_DIS,
+        Help "Enables Isolated Memory Region for PCIe."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpImrSelection, "PCIE IMR port number", HEX,
+        Help "Selects PCIE root port number for IMR feature."
+             "Valid range: 0x0 ~ 23"
+    Combo $gPlatformFspPkgTokenSpaceGuid_TetonGlacierMode, "Teton Glacier Detection and Configuration Mode", &gPlatformFspPkgTokenSpaceGuid_TetonGlacierMode,
+        Help "Enables support for Teton Glacier hybrid storage device. 0: Disabled; 1: Dynamic Configuration. Default is 0: Disabled"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWolEnableOverride, "PCH Pm Wol Enable Override", &EN_DIS,
+        Help "Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchPmPcieWakeFromDeepSx, "PCH Pm Pcie Wake From DeepSx", &EN_DIS,
+        Help "Determine if enable PCIe to wake from deep Sx."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanEnable, "PCH Pm WoW lan Enable", &EN_DIS,
+        Help "Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWoWlanDeepSxEnable, "PCH Pm WoW lan DeepSx Enable", &EN_DIS,
+        Help "Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchPmLanWakeFromDeepSx, "PCH Pm Lan Wake From DeepSx", &EN_DIS,
+        Help "Determine if enable LAN to wake from deep Sx."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDeepSxPol, "PCH Pm Deep Sx Pol", &EN_DIS,
+        Help "Deep Sx Policy."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS3MinAssert, "PCH Pm Slp S3 Min Assert", HEX,
+        Help "SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms."
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS4MinAssert, "PCH Pm Slp S4 Min Assert", HEX,
+        Help "SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s."
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpSusMinAssert, "PCH Pm Slp Sus Min Assert", HEX,
+        Help "SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s."
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmSlpAMinAssert, "PCH Pm Slp A Min Assert", HEX,
+        Help "SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s."
+             "Valid range: 0x0 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SlpS0Override, "SLP_S0# Override", &gPlatformFspPkgTokenSpaceGuid_SlpS0Override,
+        Help "Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled' will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion when debug is enabled. \nNote: This BIOS option should keep 'Auto', other options are intended for advanced configuration only."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SlpS0DisQForDebug, "S0ix Override Settings", &gPlatformFspPkgTokenSpaceGuid_SlpS0DisQForDebug,
+        Help "Select 'Auto', it will be auto-configured according to probe type. 'No Change' will keep PMC default settings. Or select the desired debug probe type for S0ix Override settings.\nReminder: DCI OOB (aka BSSB) uses CCA probe.\nNote: This BIOS option should keep 'Auto', other options are intended for advanced configuration only."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchEnableDbcObs, "USB Overcurrent Override for DbC", &EN_DIS,
+        Help "This option overrides USB Over Current enablement state that USB OC will be disabled after enabling this option. Enable when DbC is used to avoid signaling conflicts."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchLegacyIoLowLatency, "PCH Legacy IO Low Latency Enable", &EN_DIS,
+        Help "Set to enable low latency of legacy IO. <b>0: Disable</b>, 1: Enable"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchPmLpcClockRun, "PCH Pm Lpc Clock Run", &EN_DIS,
+        Help "This member describes whether or not the LPC ClockRun feature of PCH should be enabled. Default value is Disabled"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpStrchSusUp, "PCH Pm Slp Strch Sus Up", &EN_DIS,
+        Help "Enable SLP_X Stretching After SUS Well Power Up."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpLanLowDc, "PCH Pm Slp Lan Low Dc", &EN_DIS,
+        Help "Enable/Disable SLP_LAN# Low on DC Power."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPwrBtnOverridePeriod, "PCH Pm Pwr Btn Override Period", HEX,
+        Help "PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s."
+             "Valid range: 0x0 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableDsxAcPresentPulldown, "PCH Pm Disable Dsx Ac Present Pulldown", &EN_DIS,
+        Help "When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableNativePowerButton, "PCH Pm Disable Native Power Button", &EN_DIS,
+        Help "Power button native mode disable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchPmSlpS0Enable, "PCH Pm Slp S0 Enable", &EN_DIS,
+        Help "Indicates whether SLP_S0# is to be asserted when PCH reaches idle state."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchPmMeWakeSts, "PCH Pm ME_WAKE_STS", &EN_DIS,
+        Help "Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchPmWolOvrWkSts, "PCH Pm WOL_OVR_WK_STS", &EN_DIS,
+        Help "Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPwrCycDur, "PCH Pm Reset Power Cycle Duration", HEX,
+        Help "Could be customized in the unit of second. Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ..."
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPmPciePllSsc, "PCH Pm Pcie Pll Ssc", HEX,
+        Help "Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No BIOS override."
+             "Valid range: 0x0 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataPwrOptEnable, "PCH Sata Pwr Opt Enable", &EN_DIS,
+        Help "SATA Power Optimizer on PCH side."
+    Combo $gPlatformFspPkgTokenSpaceGuid_EsataSpeedLimit, "PCH Sata eSATA Speed Limit", &EN_DIS,
+        Help "When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataSpeedLimit, "PCH Sata Speed Limit", HEX,
+        Help "Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault."
+             "Valid range: 0x0 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsHotPlug, "Enable SATA Port HotPlug", HEX,
+        Help "Enable SATA Port HotPlug."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsInterlockSw, "Enable SATA Port Interlock Sw", HEX,
+        Help "Enable SATA Port Interlock Sw."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsExternal, "Enable SATA Port External", HEX,
+        Help "Enable SATA Port External."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsSpinUp, "Enable SATA Port SpinUp", HEX,
+        Help "Enable the COMRESET initialization Sequence to the device."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsSolidStateDrive, "Enable SATA Port Solid State Drive", HEX,
+        Help "0: HDD; 1: SSD."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsEnableDitoConfig, "Enable SATA Port Enable Dito Config", HEX,
+        Help "Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDmVal, "Enable SATA Port DmVal", HEX,
+        Help "DITO multiplier. Default is 15."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDitoVal, "Enable SATA Port DmVal", HEX,
+        Help "DEVSLP Idle Timeout (DITO), Default is 625."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsZpOdd, "Enable SATA Port ZpOdd", HEX,
+        Help "Support zero power ODD."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId, "PCH Sata Rst Raid Device Id", &gPlatformFspPkgTokenSpaceGuid_SataRstRaidDeviceId,
+        Help "Enable RAID Alternate ID."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid0, "PCH Sata Rst Raid0", &EN_DIS,
+        Help "RAID0."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid1, "PCH Sata Rst Raid1", &EN_DIS,
+        Help "RAID1."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid10, "PCH Sata Rst Raid10", &EN_DIS,
+        Help "RAID10."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataRstRaid5, "PCH Sata Rst Raid5", &EN_DIS,
+        Help "RAID5."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataRstIrrt, "PCH Sata Rst Irrt", &EN_DIS,
+        Help "Intel Rapid Recovery Technology."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiBanner, "PCH Sata Rst Orom Ui Banner", &EN_DIS,
+        Help "OROM UI and BANNER."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstOromUiDelay, "PCH Sata Rst Orom Ui Delay", HEX,
+        Help "00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY)."
+             "Valid range: 0x00 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataRstHddUnlock, "PCH Sata Rst Hdd Unlock", &EN_DIS,
+        Help "Indicates that the HDD password unlock in the OS is enabled."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataRstLedLocate, "PCH Sata Rst Led Locate", &EN_DIS,
+        Help "Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataRstIrrtOnly, "PCH Sata Rst Irrt Only", &EN_DIS,
+        Help "Allow only IRRT drives to span internal and external ports."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataRstSmartStorage, "PCH Sata Rst Smart Storage", &EN_DIS,
+        Help "RST Smart Storage caching Bit."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieEnable, "PCH Sata Rst Pcie Storage Remap enable", HEX,
+        Help "Enable Intel RST for PCIe Storage remapping."
+             "Valid range: 0x00 ~ 0xFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieStoragePort, "PCH Sata Rst Pcie Storage Port", HEX,
+        Help "Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect)."
+             "Valid range: 0x00 ~ 0xFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataRstPcieDeviceResetDelay, "PCH Sata Rst Pcie Device Reset Delay", HEX,
+        Help "PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms"
+             "Valid range: 0x00 ~ 0xFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400TuningRequired, "Enable eMMC HS400 Training", &EN_DIS,
+        Help "Deprecated."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DllDataValid, "Set HS400 Tuning Data Valid", &EN_DIS,
+        Help "Deprecated"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400RxStrobeDll1, "Rx Strobe Delay Control", HEX,
+        Help "Deprecated"
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400TxDataDll, "Tx Data Delay Control", HEX,
+        Help "Deprecated"
+             "Valid range: 0x00 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DriverStrength, "I/O Driver Strength", &gPlatformFspPkgTokenSpaceGuid_PchScsEmmcHs400DriverStrength,
+        Help "Deprecated"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchSirqEnable, "Enable Serial IRQ", &EN_DIS,
+        Help "Determines if enable Serial IRQ."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchSirqMode, "Serial IRQ Mode Select", &EN_DIS,
+        Help "Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchStartFramePulse, "Start Frame Pulse Width", &gPlatformFspPkgTokenSpaceGuid_PchStartFramePulse,
+        Help "Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchEspiLockLinkConfiguration, "PCH eSPI Link Configuration Lock (SBLCL)", &EN_DIS,
+        Help "Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI slaves addresseses from range 0x0 - 0x7FF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchTsmicLock, "Thermal Device SMI Enable", &EN_DIS,
+        Help "This locks down SMI Enable on Alert Thermal Sensor Trip."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchT0Level, "Thermal Throttling Custimized T0Level Value", HEX,
+        Help "Custimized T0Level value."
+             "Valid range: 0x00 ~ 0xFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchT1Level, "Thermal Throttling Custimized T1Level Value", HEX,
+        Help "Custimized T1Level value."
+             "Valid range: 0x00 ~ 0xFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchT2Level, "Thermal Throttling Custimized T2Level Value", HEX,
+        Help "Custimized T2Level value."
+             "Valid range: 0x00 ~ 0xFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchTTEnable, "Enable The Thermal Throttle", &EN_DIS,
+        Help "Enable the thermal throttle function."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchTTState13Enable, "PMSync State 13", &EN_DIS,
+        Help "When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchTTLock, "Thermal Throttle Lock", &EN_DIS,
+        Help "Thermal Throttle Lock."
+    Combo $gPlatformFspPkgTokenSpaceGuid_TTSuggestedSetting, "Thermal Throttling Suggested Setting", &EN_DIS,
+        Help "Thermal Throttling Suggested Setting."
+    Combo $gPlatformFspPkgTokenSpaceGuid_TTCrossThrottling, "Enable PCH Cross Throttling", &EN_DIS,
+        Help "Enable/Disable PCH Cross Throttling"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiTsawEn, "DMI Thermal Sensor Autonomous Width Enable", &EN_DIS,
+        Help "DMI Thermal Sensor Autonomous Width Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_DmiSuggestedSetting, "DMI Thermal Sensor Suggested Setting", &EN_DIS,
+        Help "DMT thermal sensor suggested representative values."
+    Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS0TW, "Thermal Sensor 0 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS0TW,
+        Help "DMT thermal sensor suggested representative values."
+    Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS1TW, "Thermal Sensor 1 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS1TW,
+        Help "Thermal Sensor 1 Target Width."
+    Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS2TW, "Thermal Sensor 2 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS2TW,
+        Help "Thermal Sensor 2 Target Width."
+    Combo $gPlatformFspPkgTokenSpaceGuid_DmiTS3TW, "Thermal Sensor 3 Target Width", &gPlatformFspPkgTokenSpaceGuid_DmiTS3TW,
+        Help "Thermal Sensor 3 Target Width."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T1M, "Port 0 T1 Multipler", HEX,
+        Help "Port 0 T1 Multipler."
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T2M, "Port 0 T2 Multipler", HEX,
+        Help "Port 0 T2 Multipler."
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0T3M, "Port 0 T3 Multipler", HEX,
+        Help "Port 0 T3 Multipler."
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0TDisp, "Port 0 Tdispatch", HEX,
+        Help "Port 0 Tdispatch."
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T1M, "Port 1 T1 Multipler", HEX,
+        Help "Port 1 T1 Multipler."
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T2M, "Port 1 T2 Multipler", HEX,
+        Help "Port 1 T2 Multipler."
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1T3M, "Port 1 T3 Multipler", HEX,
+        Help "Port 1 T3 Multipler."
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1TDisp, "Port 1 Tdispatch", HEX,
+        Help "Port 1 Tdispatch."
+             "Valid range: 0x00 ~ 0xFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataP0Tinact, "Port 0 Tinactive", HEX,
+        Help "Port 0 Tinactive."
+             "Valid range: 0x00 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataP0TDispFinit, "Port 0 Alternate Fast Init Tdispatch", &EN_DIS,
+        Help "Port 0 Alternate Fast Init Tdispatch."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataP1Tinact, "Port 1 Tinactive", HEX,
+        Help "Port 1 Tinactive."
+             "Valid range: 0x00 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataP1TDispFinit, "Port 1 Alternate Fast Init Tdispatch", &EN_DIS,
+        Help "Port 1 Alternate Fast Init Tdispatch."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataThermalSuggestedSetting, "Sata Thermal Throttling Suggested Setting", &EN_DIS,
+        Help "Sata Thermal Throttling Suggested Setting."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchMemoryThrottlingEnable, "Enable Memory Thermal Throttling", &EN_DIS,
+        Help "Enable Memory Thermal Throttling."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchMemoryPmsyncEnable, "Memory Thermal Throttling", HEX,
+        Help "Enable Memory Thermal Throttling."
+             "Valid range: 0x00 ~ 0xFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchMemoryC0TransmitEnable, "Enable Memory Thermal Throttling", HEX,
+        Help "Enable Memory Thermal Throttling."
+             "Valid range: 0x00 ~ 0xFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchMemoryPinSelection, "Enable Memory Thermal Throttling", HEX,
+        Help "Enable Memory Thermal Throttling."
+             "Valid range: 0x00 ~ 0xFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchTemperatureHotLevel, "Thermal Device Temperature", HEX,
+        Help "Decides the temperature."
+             "Valid range: 0x00 ~ 0xFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchEnableComplianceMode, "Enable xHCI Compliance Mode", &EN_DIS,
+        Help "Compliance Mode can be enabled for testing through this option but this is disabled by default."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Usb2OverCurrentPin, "USB2 Port Over Current Pin", HEX,
+        Help "Describe the specific over current pin number of USB 2.0 Port N."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3OverCurrentPin, "USB3 Port Over Current Pin", HEX,
+        Help "Describe the specific over current pin number of USB 3.0 Port N."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGating, "Enable 8254 Static Clock Gating", &EN_DIS,
+        Help "Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support boot legacy OS using 8254 timer. Also enable this while S0ix is enabled."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataRstOptaneMemory, "PCH Sata Rst Optane Memory", &EN_DIS,
+        Help "Optane Memory"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataRstCpuAttachedStorage, "PCH Sata Rst CPU Attached Storage", &EN_DIS,
+        Help "CPU Attached Storage"
+    Combo $gPlatformFspPkgTokenSpaceGuid_Enable8254ClockGatingOnS3, "Enable 8254 Static Clock Gating On S3", &EN_DIS,
+        Help "This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPcieDeviceOverrideTablePtr, "Pch PCIE device override table pointer", HEX,
+        Help "The PCIe device table is being used to override PCIe device ASPM settings. This is a pointer points to a 32bit address. And it's only used in PostMem phase. Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId must be 0."
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_EnableTcoTimer, "Enable TCO timer.", &EN_DIS,
+        Help "When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PsOnEnable, "Enable PS_ON.", &EN_DIS,
+        Help "PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PmcCpuC10GatePinEnable, "Pmc Cpu C10 Gate Pin Enable", &EN_DIS,
+        Help "Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl, "Pch Dmi Aspm Ctrl", &gPlatformFspPkgTokenSpaceGuid_PchDmiAspmCtrl,
+        Help "ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3", HEX,
+        Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each value in array can be between 0-1. One byte for each port."
+             "Valid range: 0x00 ~ 0x01010101010101010101"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate3UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 3", HEX,
+        Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], <b>Default = 4Ch</b>. One byte for each port."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2", HEX,
+        Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each value in array can be between 0-1. One byte for each port."
+             "Valid range: 0x00 ~ 0x01010101010101010101"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate2UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 2", HEX,
+        Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], <b>Default = 4Ch</b>. One byte for each port."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1", HEX,
+        Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each value in array can be between 0-1. One byte for each port."
+             "Valid range: 0x00 ~ 0x01010101010101010101"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate1UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 1", HEX,
+        Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], <b>Default = 4Ch</b>. One byte for each port."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTranEnable, "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0", HEX,
+        Help "Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each value in array can be between 0-1. One byte for each port."
+             "Valid range: 0x00 ~ 0x01010101010101010101"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioTxRate0UniqTran, "USB 3.0 TX Output Unique Transition Bit Scale for rate 0", HEX,
+        Help "USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], <b>Default = 4Ch</b>. One byte for each port."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieNumOfCoefficients, "Number of Coefficients to be used", HEX,
+        Help "The number of coefficients to be used for equalization, default value is 3"
+             "Valid range: 0x0 ~ 0x5"
+    Combo $gPlatformFspPkgTokenSpaceGuid_GpioPmRcompCommunityLocalClockGating, "GPIO RCOMP Community Clock Gating", &EN_DIS,
+        Help "0 = Disable dynamic RCOMP clock local clock gating, 1 = Enable dynamic RCOMP clock local clock gating, default value is 1"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ScsSdCardWpPinEnabled, "Enable SD Card Write Protect Pin", &EN_DIS,
+        Help "Enable/disable SD Card Write Protect Pin."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SataPortsDevSlpResetConfig, "Set SATA DEVSLP GPIO Reset Config", HEX,
+        Help "Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset, 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte for each port, byte0 for port0, byte1 for port1, and so on."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SpiFlashCfgLockDown, "Flash Configuration Lock Down", &EN_DIS,
+        Help "Enable/disable flash lock down. If platform decides to skip this programming, it must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaSndwLinkIoControlEnabled, "Enable HD Audio Sndw Link IO Control", HEX,
+        Help "0:Disabled, 1:Enabled. Enables IO Control to Sndw link if it is Enabled"
+             "Valid range: 0x00 ~ 0x00"
+    Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMem, "ReservedPchPostMem", &EN_DIS,
+        Help "Reserved for Pch Post-Mem"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchHdaResetWaitTimer, "HD Audio Reset Wait Timer", HEX,
+        Help "The delay timer after Azalia reset, the value is number of microseconds. Default is 600."
+             "Valid range: 0x00 ~ 0xFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownGlobalSmi, "Enable LOCKDOWN SMI", &EN_DIS,
+        Help "Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownBiosInterface, "Enable LOCKDOWN BIOS Interface", &EN_DIS,
+        Help "Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchUnlockGpioPads, "Unlock all GPIO pads", &EN_DIS,
+        Help "Force all GPIO pads to be unlocked for debug purpose."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchSbAccessUnlock, "PCH Unlock SideBand access", &EN_DIS,
+        Help "The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxSnoopLatency, "PCIE RP Ltr Max Snoop Latency", HEX,
+        Help "Latency Tolerance Reporting, Max Snoop Latency."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpLtrMaxNoSnoopLatency, "PCIE RP Ltr Max No Snoop Latency", HEX,
+        Help "Latency Tolerance Reporting, Max Non-Snoop Latency."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMode, "PCIE RP Snoop Latency Override Mode", HEX,
+        Help "Latency Tolerance Reporting, Snoop Latency Override Mode."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideMultiplier, "PCIE RP Snoop Latency Override Multiplier", HEX,
+        Help "Latency Tolerance Reporting, Snoop Latency Override Multiplier."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSnoopLatencyOverrideValue, "PCIE RP Snoop Latency Override Value", HEX,
+        Help "Latency Tolerance Reporting, Snoop Latency Override Value."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMode, "PCIE RP Non Snoop Latency Override Mode", HEX,
+        Help "Latency Tolerance Reporting, Non-Snoop Latency Override Mode."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideMultiplier, "PCIE RP Non Snoop Latency Override Multiplier", HEX,
+        Help "Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpNonSnoopLatencyOverrideValue, "PCIE RP Non Snoop Latency Override Value", HEX,
+        Help "Latency Tolerance Reporting, Non-Snoop Latency Override Value."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitScale, "PCIE RP Slot Power Limit Scale", HEX,
+        Help "Specifies scale used for slot power limit value. Leave as 0 to set to default."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpSlotPowerLimitValue, "PCIE RP Slot Power Limit Value", HEX,
+        Help "Specifies upper limit on power supplie by slot. Leave as 0 to set to default."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpUptp, "PCIE RP Upstream Port Transmiter Preset", HEX,
+        Help "Used during Gen3 Link Equalization. Used for all lanes.  Default is 5."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpDptp, "PCIE RP Downstream Port Transmiter Preset", HEX,
+        Help "Used during Gen3 Link Equalization. Used for all lanes.  Default is 7."
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PcieEnablePort8xhDecode, "PCIE RP Enable Port8xh Decode", &EN_DIS,
+        Help "This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; 1: Enable."
+    EditNum $gPlatformFspPkgTokenSpaceGuid_PchPciePort8xhDecodePortIndex, "PCIE Port8xh Decode Port Index", HEX,
+        Help "The Index of PCIe Port that is selected for Port8xh Decode (0 Based)."
+             "Valid range: 0x0 ~ 0xFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchPmDisableEnergyReport, "PCH Energy Reporting", &EN_DIS,
+        Help "Disable/Enable PCH to CPU energy report feature."
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataTestMode, "PCH Sata Test Mode", &EN_DIS,
+        Help "Allow entrance to the PCH SATA test modes."
+    Combo $gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock, "PCH USB OverCurrent mapping lock enable", &EN_DIS,
+        Help "If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked."
+    Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMemTest, "ReservedPchPostMemTest", &EN_DIS,
+        Help "Reserved for Pch Post-Mem Test"
+    Combo $gCannonLakeFspPkgTokenSpaceGuid_MctpBroadcastCycle, "Mctp Broadcast Cycle", &EN_DIS,
+        Help "Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable."
+    Combo $gPlatformFspPkgTokenSpaceGuid_EmmcUseCustomDlls, "Use DLL values from policy", &EN_DIS,
+        Help "Set if FSP should use HS400 DLL values from policy"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcTxCmdDelayRegValue, "Emmc Tx CMD Delay control register value", HEX,
+        Help "Please see Tx CMD Delay Control register definition for help"
+             "Valid range: 0x0 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcTxDataDelay1RegValue, "Emmc Tx DATA Delay control 1 register value", HEX,
+        Help "Please see Tx DATA Delay control 1 register definition for help"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcTxDataDelay2RegValue, "Emmc Tx DATA Delay control 2 register value", HEX,
+        Help "Please see Tx DATA Delay control 2 register definition for help"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcRxCmdDataDelay1RegValue, "Emmc Rx CMD + DATA Delay control 1 register value", HEX,
+        Help "Please see Rx CMD + DATA Delay control 1 register definition for help"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcRxCmdDataDelay2RegValue, "Emmc Rx CMD + DATA Delay control 2 register value", HEX,
+        Help "Please see Rx CMD + DATA Delay control 2 register definition for help"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_EmmcRxStrobeDelayRegValue, "Emmc Rx Strobe Delay control register value", HEX,
+        Help "Please see Rx Strobe Delay control register definition for help"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SdCardUseCustomDlls, "Use tuned DLL values from policy", &EN_DIS,
+        Help "Set if FSP should use HS400 DLL values from policy"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SdCardTxCmdDelayRegValue, "SdCard Tx CMD Delay control register value", HEX,
+        Help "Please see Tx CMD Delay Control register definition for help"
+             "Valid range: 0x0 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SdCardTxDataDelay1RegValue, "SdCard Tx DATA Delay control 1 register value", HEX,
+        Help "Please see Tx DATA Delay control 1 register definition for help"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SdCardTxDataDelay2RegValue, "SdCard Tx DATA Delay control 2 register value", HEX,
+        Help "Please see Tx DATA Delay control 2 register definition for help"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SdCardRxCmdDataDelay1RegValue, "SdCard Rx CMD + DATA Delay control 1 register value", HEX,
+        Help "Please see Rx CMD + DATA Delay control 1 register definition for help"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_SdCardRxCmdDataDelay2RegValue, "SdCard Rx CMD + DATA Delay control 2 register value", HEX,
+        Help "Please see Rx CMD + DATA Delay control 2 register definition for help"
+             "Valid range: 0x00 ~ 0xFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_EnforceEDebugMode, "Enforce Enhanced Debug Mode", &EN_DIS,
+        Help "Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPixelHeight, "LogoPixelHeight Address", HEX,
+        Help "Address of LogoPixelHeight"
+             "Valid range: 0x0 ~ 0xFFFFFFFF"
+    EditNum $gPlatformFspPkgTokenSpaceGuid_LogoPixelWidth, "LogoPixelWidth Address", HEX,
+        Help "Address of LogoPixelWidth"
+             "Valid range: 0x0 ~ 0xFFFFFFFF"
+EndPage
+
+Page "PCH 2"
+    EditNum $gCannonLakeFspPkgTokenSpaceGuid_PcieRootPortGen2PllL1CgDisable, "PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable", HEX,
+        Help "PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for Alpine ridge"
+             "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
+    Combo $gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt, "SATA RST Interrupt Mode", &gPlatformFspPkgTokenSpaceGuid_SataRstInterrupt,
+        Help "Allowes to choose which interrupts will be implemented by SATA controller in RAID mode."
+    Combo $gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear, "ME Unconfig on RTC clear", &gPlatformFspPkgTokenSpaceGuid_MeUnconfigOnRtcClear,
+        Help "0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>. 2: Cmos is clear, status unkonwn. 3: Reserved"
+    Combo $gPlatformFspPkgTokenSpaceGuid_EndOfPostMessage, "End of Post message", &EN_DIS,
+        Help "Test, Send End of Post message. Disable(0x0): Disable EOP message, Enable(0x1)(Default): Enable EOP message"
+    Combo $gPlatformFspPkgTokenSpaceGuid_DisableD0I3SettingForHeci, "D0I3 Setting for HECI Disable", &EN_DIS,
+        Help "Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices"
+EndPage
+
diff --git a/CometLakeFspBinPkg/CometLake2/FspPcds.dsc b/CometLakeFspBinPkg/CometLake2/FspPcds.dsc
new file mode 100644
index 0000000..42c29d2
--- /dev/null
+++ b/CometLakeFspBinPkg/CometLake2/FspPcds.dsc
@@ -0,0 +1,40 @@
+## @file
+#  FSP description for DynamicEx PCDs.
+#
+# @copyright
+#  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+# @par Specification
+##
+
+  ## Specifies the AP target C-state for Mwait during POST phase.
+  #  The default value 0 means C1 state.
+  #  The value is defined as below.<BR><BR>
+  # @Prompt The specified AP target C-state for Mwait.
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0
+
+  ## Specifies max supported number of Logical Processors.
+  # @Prompt Configure max supported number of Logical Processorss
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber | 20
+
+  gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress           | 0xE0000000
+  gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength            | 0x10000000
+
+  ## Specifies the base address of the first microcode Patch in the microcode Region.
+  # @Prompt Microcode Region base address.
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0
+
+  ## Specifies the size of the microcode Region.
+  # @Prompt Microcode Region size.
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0
+
+  ## Specifies the AP wait loop state during POST phase.
+  #  The value is defined as below.
+  #  1: Place AP in the Hlt-Loop state.
+  #  2: Place AP in the Mwait-Loop state.
+  #  3: Place AP in the Run-Loop state.
+  # @Prompt The AP wait loop state.
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
+
diff --git a/CometLakeFspBinPkg/CometLake2/Include/FirmwareVersionInfoHob.h b/CometLakeFspBinPkg/CometLake2/Include/FirmwareVersionInfoHob.h
new file mode 100644
index 0000000..4d72102
--- /dev/null
+++ b/CometLakeFspBinPkg/CometLake2/Include/FirmwareVersionInfoHob.h
@@ -0,0 +1,62 @@
+/** @file
+  Header file for Firmware Version Information
+
+ @copyright
+  Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
+#define _FIRMWARE_VERSION_INFO_HOB_H_
+
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiHob.h>
+
+#pragma pack(1)
+///
+/// Firmware Version Structure
+///
+typedef struct {
+  UINT8                          MajorVersion;
+  UINT8                          MinorVersion;
+  UINT8                          Revision;
+  UINT16                         BuildNumber;
+} FIRMWARE_VERSION;
+
+///
+/// Firmware Version Information Structure
+///
+typedef struct {
+  UINT8                          ComponentNameIndex;        ///< Offset 0   Index of Component Name
+  UINT8                          VersionStringIndex;        ///< Offset 1   Index of Version String
+  FIRMWARE_VERSION               Version;                   ///< Offset 2-6 Firmware version
+} FIRMWARE_VERSION_INFO;
+
+#ifndef __SMBIOS_STANDARD_H__
+///
+/// The Smbios structure header.
+///
+typedef struct {
+  UINT8                          Type;
+  UINT8                          Length;
+  UINT16                         Handle;
+} SMBIOS_STRUCTURE;
+#endif
+
+///
+/// Firmware Version Information HOB Structure
+///
+typedef struct {
+  EFI_HOB_GUID_TYPE              Header;                    ///< Offset 0-23  The header of FVI HOB
+  SMBIOS_STRUCTURE               SmbiosData;                ///< Offset 24-27  The SMBIOS header of FVI HOB
+  UINT8                          Count;                     ///< Offset 28    Number of FVI elements included.
+///
+/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
+///
+} FIRMWARE_VERSION_INFO_HOB;
+#pragma pack()
+
+#endif // _FIRMWARE_VERSION_INFO_HOB_H_
diff --git a/CometLakeFspBinPkg/CometLake2/Include/FspInfoHob.h b/CometLakeFspBinPkg/CometLake2/Include/FspInfoHob.h
new file mode 100644
index 0000000..34283b8
--- /dev/null
+++ b/CometLakeFspBinPkg/CometLake2/Include/FspInfoHob.h
@@ -0,0 +1,32 @@
+/** @file
+  Header file for FSP Information HOB.
+
+ @copyright
+  Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@par Specification Reference:
+**/
+
+#ifndef _FSP_INFO_HOB_H_
+#define _FSP_INFO_HOB_H_
+
+extern EFI_GUID gFspInfoGuid;
+
+#pragma pack (push, 1)
+
+typedef struct {
+UINT8              SiliconInitVersionMajor;
+UINT8              SiliconInitVersionMinor;
+UINT8              SiliconInitVersionRevision;
+UINT8              SiliconInitVersionBuild;
+UINT8              FspVersionRevision;
+UINT8              FspVersionBuild;
+UINT8              TimeStamp [12];
+UINT8              FspVersionMinor;
+} FSP_INFO_HOB;
+
+#pragma pack (pop)
+
+#endif // _FSP_INFO_HOB_H_
diff --git a/CometLakeFspBinPkg/CometLake2/Include/FspUpd.h b/CometLakeFspBinPkg/CometLake2/Include/FspUpd.h
new file mode 100644
index 0000000..395a7a1
--- /dev/null
+++ b/CometLakeFspBinPkg/CometLake2/Include/FspUpd.h
@@ -0,0 +1,26 @@
+/** @file
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPUPD_H__
+#define __FSPUPD_H__
+
+#include <FspEas.h>
+
+#pragma pack(1)
+
+#define FSPT_UPD_SIGNATURE               0x545F4450554C4D43        /* 'CMLUPD_T' */
+
+#define FSPM_UPD_SIGNATURE               0x4D5F4450554C4D43        /* 'CMLUPD_M' */
+
+#define FSPS_UPD_SIGNATURE               0x535F4450554C4D43        /* 'CMLUPD_S' */
+
+#pragma pack()
+
+#endif
diff --git a/CometLakeFspBinPkg/CometLake2/Include/FspmUpd.h b/CometLakeFspBinPkg/CometLake2/Include/FspmUpd.h
new file mode 100644
index 0000000..cb58672
--- /dev/null
+++ b/CometLakeFspBinPkg/CometLake2/Include/FspmUpd.h
@@ -0,0 +1,3056 @@
+/** @file
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPMUPD_H__
+#define __FSPMUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+#include <MemInfoHob.h>
+
+///
+/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
+///
+typedef struct {
+  UINT8             Revision;         ///< Chipset Init Info Revision
+  UINT8             Rsvd[3];          ///< Reserved
+  UINT16            MeChipInitCrc;    ///< 16 bit CRC value of MeChipInit Table
+  UINT16            BiosChipInitCrc;  ///< 16 bit CRC value of PchChipInit Table
+} CHIPSET_INIT_INFO;
+
+
+/** Fsp M Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - Platform Reserved Memory Size
+  The minimum platform memory size required to pass control into DXE
+**/
+  UINT64                      PlatformMemorySize;
+
+/** Offset 0x0048 - Memory SPD Pointer Channel 0 Dimm 0
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+  UINT32                      MemorySpdPtr00;
+
+/** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 1
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+  UINT32                      MemorySpdPtr01;
+
+/** Offset 0x0050 - Memory SPD Pointer Channel 1 Dimm 0
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+  UINT32                      MemorySpdPtr10;
+
+/** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 1
+  Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+  UINT32                      MemorySpdPtr11;
+
+/** Offset 0x0058 - SPD Data Length
+  Length of SPD Data
+  0x100:256 Bytes, 0x200:512 Bytes
+**/
+  UINT16                      MemorySpdDataLen;
+
+/** Offset 0x005A - Dq Byte Map CH0
+  Dq byte mapping between CPU and DRAM, Channel 0: board-dependent
+**/
+  UINT8                       DqByteMapCh0[12];
+
+/** Offset 0x0066 - Dq Byte Map CH1
+  Dq byte mapping between CPU and DRAM, Channel 1: board-dependent
+**/
+  UINT8                       DqByteMapCh1[12];
+
+/** Offset 0x0072 - Dqs Map CPU to DRAM CH 0
+  Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent
+**/
+  UINT8                       DqsMapCpu2DramCh0[8];
+
+/** Offset 0x007A - Dqs Map CPU to DRAM CH 1
+  Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent
+**/
+  UINT8                       DqsMapCpu2DramCh1[8];
+
+/** Offset 0x0082 - RcompResistor settings
+  Indicates  RcompResistor settings: CML - 0's means MRC auto configured based on
+  Design Guidelines, otherwise input an Ohmic value per segment. CFL will need to
+  provide the appropriate values.
+**/
+  UINT16                      RcompResistor[3];
+
+/** Offset 0x0088 - RcompTarget settings
+  RcompTarget settings: CML - 0's mean MRC auto configured based on Design Guidelines,
+  otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values.
+**/
+  UINT16                      RcompTarget[5];
+
+/** Offset 0x0092 - Dqs Pins Interleaved Setting
+  Indicates DqPinsInterleaved setting: board-dependent
+  $EN_DIS
+**/
+  UINT8                       DqPinsInterleaved;
+
+/** Offset 0x0093 - VREF_CA
+  CA Vref routing: board-dependent
+  0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B,
+  2:VREF_CA to CH_A and VREF_DQ_B to CH_B
+**/
+  UINT8                       CaVrefConfig;
+
+/** Offset 0x0094 - Smram Mask
+  The SMM Regions AB-SEG and/or H-SEG reserved
+  0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both
+**/
+  UINT8                       SmramMask;
+
+/** Offset 0x0095 - Time Measure
+  Time Measure: 0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       MrcTimeMeasure;
+
+/** Offset 0x0096 - MRC Fast Boot
+  Enables/Disable the MRC fast path thru the MRC
+  $EN_DIS
+**/
+  UINT8                       MrcFastBoot;
+
+/** Offset 0x0097 - Rank Margin Tool per Task
+  This option enables the user to execute Rank Margin Tool per major training step
+  in the MRC.
+  $EN_DIS
+**/
+  UINT8                       RmtPerTask;
+
+/** Offset 0x0098 - Training Trace
+  This option enables the trained state tracing feature in MRC.  This feature will
+  print out the key training parameters state across major training steps.
+  $EN_DIS
+**/
+  UINT8                       TrainTrace;
+
+/** Offset 0x0099
+**/
+  UINT8                       UnusedUpdSpace0[3];
+
+/** Offset 0x009C - Intel Enhanced Debug
+  Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied
+  0 : Disable, 0x400000 : Enable
+**/
+  UINT32                      IedSize;
+
+/** Offset 0x00A0 - Tseg Size
+  Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
+  0x0400000:4MB, 0x01000000:16MB
+**/
+  UINT32                      TsegSize;
+
+/** Offset 0x00A4 - MMIO Size
+  Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
+**/
+  UINT16                      MmioSize;
+
+/** Offset 0x00A6 - Probeless Trace
+  Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB.
+  This also requires IED to be enabled.
+  $EN_DIS
+**/
+  UINT8                       ProbelessTrace;
+
+/** Offset 0x00A7 - GDXC IOT SIZE
+  Size of IOT and MOT is in 8 MB chunks
+**/
+  UINT8                       GdxcIotSize;
+
+/** Offset 0x00A8 - GDXC MOT SIZE
+  Size of IOT and MOT is in 8 MB chunks
+**/
+  UINT8                       GdxcMotSize;
+
+/** Offset 0x00A9 - Spd Address Tabl
+  Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used
+  if SPD Address is 00
+**/
+  UINT8                       SpdAddressTable[4];
+
+/** Offset 0x00AD - Internal Graphics Pre-allocated Memory
+  Size of memory preallocated for internal graphics.
+  0x00:0 MB, 0x01:32 MB, 0x02:64 MB
+**/
+  UINT8                       IgdDvmt50PreAlloc;
+
+/** Offset 0x00AE - Internal Graphics
+  Enable/disable internal graphics.
+  $EN_DIS
+**/
+  UINT8                       InternalGfx;
+
+/** Offset 0x00AF - Aperture Size
+  Select the Aperture Size.
+  0:128 MB, 1:256 MB, 3:512 MB, 7:1024 MB, 15: 2048 MB
+**/
+  UINT8                       ApertureSize;
+
+/** Offset 0x00B0 - Board Type
+  MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
+  Halo, 7=UP Server
+  0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
+**/
+  UINT8                       UserBd;
+
+/** Offset 0x00B1 - SA GV
+  System Agent dynamic frequency support and when enabled memory will be training
+  at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow,
+  2=FixedHigh, and 3=Enabled.
+  0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled
+**/
+  UINT8                       SaGv;
+
+/** Offset 0x00B2 - DDR Frequency Limit
+  Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk,
+  i.e. divide by 133 or 100
+  1067:1067, 1333:1333, 1400:1400, 1600:1600, 1800:1800, 1867:1867, 2000:2000, 2133:2133,
+  2200:2200, 2400:2400, 2600:2600, 2667:2667, 2800:2800, 2933:2933, 3000:3000, 3200:3200, 0:Auto
+**/
+  UINT16                      DdrFreqLimit;
+
+/** Offset 0x00B4 - Low Frequency
+  SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133,
+  2400, 2667, 2933 and 0 for Auto.
+  1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
+**/
+  UINT16                      FreqSaGvLow;
+
+/** Offset 0x00B6 - Rank Margin Tool
+  Enable/disable Rank Margin Tool.
+  $EN_DIS
+**/
+  UINT8                       RMT;
+
+/** Offset 0x00B7 - Channel A DIMM Control
+  Channel A DIMM Control Support - Enable or Disable Dimms on Channel A.
+  0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+**/
+  UINT8                       DisableDimmChannel0;
+
+/** Offset 0x00B8 - Channel B DIMM Control
+  Channel B DIMM Control Support - Enable or Disable Dimms on Channel B.
+  0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+**/
+  UINT8                       DisableDimmChannel1;
+
+/** Offset 0x00B9 - Scrambler Support
+  This option enables data scrambling in memory.
+  $EN_DIS
+**/
+  UINT8                       ScramblerSupport;
+
+/** Offset 0x00BA - Skip Multi-Processor Initialization
+  When this is skipped, boot loader must initialize processors before SilicionInit
+  API. </b>0: Initialize; <b>1: Skip
+  $EN_DIS
+**/
+  UINT8                       SkipMpInit;
+
+/** Offset 0x00BB - SPD Profile Selected
+  Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP
+  Profile 1, 3=XMP Profile 2
+  0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2
+**/
+  UINT8                       SpdProfileSelected;
+
+/** Offset 0x00BC - Memory Reference Clock
+  100MHz, 133MHz.
+  0:133MHz, 1:100MHz
+**/
+  UINT8                       RefClk;
+
+/** Offset 0x00BD
+**/
+  UINT8                       UnusedUpdSpace1;
+
+/** Offset 0x00BE - Memory Voltage
+  Memory Voltage Override (Vddq). Default = no override
+  0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40
+  Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts
+**/
+  UINT16                      VddVoltage;
+
+/** Offset 0x00C0 - Memory Ratio
+  Automatic or the frequency will equal ratio times reference clock. Set to Auto to
+  recalculate memory timings listed below.
+  0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15
+**/
+  UINT8                       Ratio;
+
+/** Offset 0x00C1 - QCLK Odd Ratio
+  Adds 133 or 100 MHz to QCLK frequency, depending on RefClk
+  $EN_DIS
+**/
+  UINT8                       OddRatioMode;
+
+/** Offset 0x00C2 - tCL
+  CAS Latency, 0: AUTO, max: 31
+**/
+  UINT8                       tCL;
+
+/** Offset 0x00C3 - tCWL
+  Min CAS Write Latency Delay Time, 0: AUTO, max: 34
+**/
+  UINT8                       tCWL;
+
+/** Offset 0x00C4 - tRCD/tRP
+  RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63
+**/
+  UINT8                       tRCDtRP;
+
+/** Offset 0x00C5 - tRRD
+  Min Row Active to Row Active Delay Time, 0: AUTO, max: 15
+**/
+  UINT8                       tRRD;
+
+/** Offset 0x00C6 - tFAW
+  Min Four Activate Window Delay Time, 0: AUTO, max: 63
+**/
+  UINT16                      tFAW;
+
+/** Offset 0x00C8 - tRAS
+  RAS Active Time, 0: AUTO, max: 64
+**/
+  UINT16                      tRAS;
+
+/** Offset 0x00CA - tREFI
+  Refresh Interval, 0: AUTO, max: 65535
+**/
+  UINT16                      tREFI;
+
+/** Offset 0x00CC - tRFC
+  Min Refresh Recovery Delay Time, 0: AUTO, max: 1023
+**/
+  UINT16                      tRFC;
+
+/** Offset 0x00CE - tRTP
+  Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal
+  values: 5, 6, 7, 8, 9, 10, 12
+**/
+  UINT8                       tRTP;
+
+/** Offset 0x00CF - tWR
+  Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18,
+  20, 24, 30, 34, 40
+  0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30,
+  34:34, 40:40
+**/
+  UINT8                       tWR;
+
+/** Offset 0x00D0 - tWTR
+  Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28
+**/
+  UINT8                       tWTR;
+
+/** Offset 0x00D1 - NMode
+  System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N
+**/
+  UINT8                       NModeSupport;
+
+/** Offset 0x00D2 - DllBwEn[0]
+  DllBwEn[0], for 1067 (0..7)
+**/
+  UINT8                       DllBwEn0;
+
+/** Offset 0x00D3 - DllBwEn[1]
+  DllBwEn[1], for 1333 (0..7)
+**/
+  UINT8                       DllBwEn1;
+
+/** Offset 0x00D4 - DllBwEn[2]
+  DllBwEn[2], for 1600 (0..7)
+**/
+  UINT8                       DllBwEn2;
+
+/** Offset 0x00D5 - DllBwEn[3]
+  DllBwEn[3], for 1867 and up (0..7)
+**/
+  UINT8                       DllBwEn3;
+
+/** Offset 0x00D6 - ISVT IO Port Address
+  ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default
+**/
+  UINT8                       IsvtIoPort;
+
+/** Offset 0x00D7 - Margin Limit Check
+  Margin Limit Check. Choose level of margin check
+  0:Disable, 1:L1, 2:L2, 3:Both
+**/
+  UINT8                       MarginLimitCheck;
+
+/** Offset 0x00D8 - Margin Limit L2
+  % of L1 check for margin limit check
+**/
+  UINT16                      MarginLimitL2;
+
+/** Offset 0x00DA - CPU Trace Hub Mode
+  Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable'
+  trace hub functionality.
+  0: Disable, 1:Target Debugger Mode
+**/
+  UINT8                       CpuTraceHubMode;
+
+/** Offset 0x00DB - CPU Trace Hub Memory Region 0
+  CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,
+  128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.
+  0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
+**/
+  UINT8                       CpuTraceHubMemReg0Size;
+
+/** Offset 0x00DC - CPU Trace Hub Memory Region 1
+  CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,
+  128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.
+  0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
+**/
+  UINT8                       CpuTraceHubMemReg1Size;
+
+/** Offset 0x00DD - Enable or Disable Peci C10 Reset command
+  Enable or Disable Peci C10 Reset command. If Enabled, BIOS will send the CPU message
+  to disable peci reset on C10 exit. The default value is <b>0: Disable</b> for CNL,
+  and <b>1: Enable</b> for all other CPU's
+  $EN_DIS
+**/
+  UINT8                       PeciC10Reset;
+
+/** Offset 0x00DE - Enable or Disable Peci Sx Reset command
+  Enable or Disable Peci Sx Reset command; <b>0: Disable;</b> 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PeciSxReset;
+
+/** Offset 0x00DF - HECI Timeouts
+  0: Disable, 1: Enable (Default) timeout check for HECI
+  $EN_DIS
+**/
+  UINT8                       HeciTimeouts;
+
+/** Offset 0x00E0 - HECI1 BAR address
+  BAR address of HECI1
+**/
+  UINT32                      Heci1BarAddress;
+
+/** Offset 0x00E4 - HECI2 BAR address
+  BAR address of HECI2
+**/
+  UINT32                      Heci2BarAddress;
+
+/** Offset 0x00E8 - HECI3 BAR address
+  BAR address of HECI3
+**/
+  UINT32                      Heci3BarAddress;
+
+/** Offset 0x00EC - SG dGPU Power Delay
+  SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is
+  300=300 microseconds
+**/
+  UINT16                      SgDelayAfterPwrEn;
+
+/** Offset 0x00EE - SG dGPU Reset Delay
+  SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100
+  microseconds
+**/
+  UINT16                      SgDelayAfterHoldReset;
+
+/** Offset 0x00F0 - MMIO size adjustment for AUTO mode
+  Positive number means increasing MMIO size, Negative value means decreasing MMIO
+  size: 0 (Default)=no change to AUTO mode MMIO size
+**/
+  UINT16                      MmioSizeAdjustment;
+
+/** Offset 0x00F2 - Enable/Disable DMI GEN3 Static EQ Phase1 programming
+  Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
+  Presets Programming, Enabled(0x1)(Default): Enable  EQ Phase1 Static Presets Programming
+  $EN_DIS
+**/
+  UINT8                       DmiGen3ProgramStaticEq;
+
+/** Offset 0x00F3 - Enable/Disable PEG 0
+  Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
+  it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
+  0:Disable, 1:Enable, 2:AUTO
+**/
+  UINT8                       Peg0Enable;
+
+/** Offset 0x00F4 - Enable/Disable PEG 1
+  Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
+  it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
+  0:Disable, 1:Enable, 2:AUTO
+**/
+  UINT8                       Peg1Enable;
+
+/** Offset 0x00F5 - Enable/Disable PEG 2
+  Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
+  it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
+  0:Disable, 1:Enable, 2:AUTO
+**/
+  UINT8                       Peg2Enable;
+
+/** Offset 0x00F6 - Enable/Disable PEG 3
+  Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
+  it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
+  0:Disable, 1:Enable, 2:AUTO
+**/
+  UINT8                       Peg3Enable;
+
+/** Offset 0x00F7 - PEG 0 Max Link Speed
+  Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
+  Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
+  0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
+**/
+  UINT8                       Peg0MaxLinkSpeed;
+
+/** Offset 0x00F8 - PEG 1 Max Link Speed
+  Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
+  Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
+  0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
+**/
+  UINT8                       Peg1MaxLinkSpeed;
+
+/** Offset 0x00F9 - PEG 2 Max Link Speed
+  Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
+  Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
+  0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
+**/
+  UINT8                       Peg2MaxLinkSpeed;
+
+/** Offset 0x00FA - PEG 3 Max Link Speed
+  Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
+  Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
+  0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
+**/
+  UINT8                       Peg3MaxLinkSpeed;
+
+/** Offset 0x00FB - PEG 0 Max Link Width
+  Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
+  Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8
+  0:Auto, 1:x1, 2:x2, 3:x4, 4:x8
+**/
+  UINT8                       Peg0MaxLinkWidth;
+
+/** Offset 0x00FC - PEG 1 Max Link Width
+  Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
+  Limit Link to x2, (0x3):Limit Link to x4
+  0:Auto, 1:x1, 2:x2, 3:x4
+**/
+  UINT8                       Peg1MaxLinkWidth;
+
+/** Offset 0x00FD - PEG 2 Max Link Width
+  Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
+  Limit Link to x2
+  0:Auto, 1:x1, 2:x2
+**/
+  UINT8                       Peg2MaxLinkWidth;
+
+/** Offset 0x00FE - PEG 3 Max Link Width
+  Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
+  Limit Link to x2
+  0:Auto, 1:x1, 2:x2
+**/
+  UINT8                       Peg3MaxLinkWidth;
+
+/** Offset 0x00FF - Power down unused lanes on PEG 0
+  (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
+  on the max possible link width
+  0:No power saving, 1:Auto
+**/
+  UINT8                       Peg0PowerDownUnusedLanes;
+
+/** Offset 0x0100 - Power down unused lanes on PEG 1
+  (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
+  on the max possible link width
+  0:No power saving, 1:Auto
+**/
+  UINT8                       Peg1PowerDownUnusedLanes;
+
+/** Offset 0x0101 - Power down unused lanes on PEG 2
+  (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
+  on the max possible link width
+  0:No power saving, 1:Auto
+**/
+  UINT8                       Peg2PowerDownUnusedLanes;
+
+/** Offset 0x0102 - Power down unused lanes on PEG 3
+  (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
+  on the max possible link width
+  0:No power saving, 1:Auto
+**/
+  UINT8                       Peg3PowerDownUnusedLanes;
+
+/** Offset 0x0103 - PCIe ASPM programming will happen in relation to the Oprom
+  Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default):
+  Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after
+  Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume
+  0:Before, 1:After
+**/
+  UINT8                       InitPcieAspmAfterOprom;
+
+/** Offset 0x0104 - PCIe Disable Spread Spectrum Clocking
+  PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled,
+  Disable SSC(0X1) - Disable SSC per platform design or for compliance testing
+  0:Normal Operation, 1:Disable SSC
+**/
+  UINT8                       PegDisableSpreadSpectrumClocking;
+
+/** Offset 0x0105 - DMI Gen3 Root port preset values per lane
+  Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
+**/
+  UINT8                       DmiGen3RootPortPreset[8];
+
+/** Offset 0x010D - DMI Gen3 End port preset values per lane
+  Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
+**/
+  UINT8                       DmiGen3EndPointPreset[8];
+
+/** Offset 0x0115 - DMI Gen3 End port Hint values per lane
+  Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
+**/
+  UINT8                       DmiGen3EndPointHint[8];
+
+/** Offset 0x011D - DMI Gen3 RxCTLEp per-Bundle control
+  Range: 0-15, 0 is default for each bundle, must be specified based upon platform design
+**/
+  UINT8                       DmiGen3RxCtlePeaking[4];
+
+/** Offset 0x0121 - Thermal Velocity Boost Ratio clipping
+  0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction
+  caused by high package temperatures for processors that implement the Intel Thermal
+  Velocity Boost (TVB) feature
+  0: Disabled, 1: Enabled
+**/
+  UINT8                       TvbRatioClipping;
+
+/** Offset 0x0122 - Thermal Velocity Boost voltage optimization
+  0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations
+  for processors that implement the Intel Thermal Velocity Boost (TVB) feature.
+  0: Disabled, 1: Enabled
+**/
+  UINT8                       TvbVoltageOptimization;
+
+/** Offset 0x0123 - PEG Gen3 RxCTLEp per-Bundle control
+  Range: 0-15, 12 is default for each bundle, must be specified based upon platform design
+**/
+  UINT8                       PegGen3RxCtlePeaking[10];
+
+/** Offset 0x012D
+**/
+  UINT8                       UnusedUpdSpace2[3];
+
+/** Offset 0x0130 - Memory data pointer for saved preset search results
+  The reference code will store the Gen3 Preset Search results in the SaDataHob's
+  PegData structure (SA_PEG_DATA) and platform code can save/restore this data to
+  skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0
+**/
+  UINT32                      PegDataPtr;
+
+/** Offset 0x0134 - PEG PERST# GPIO information
+  The reference code will use the information in this structure in order to reset
+  PCIe Gen3 devices during equalization, if necessary
+**/
+  UINT8                       PegGpioData[28];
+
+/** Offset 0x0150 - PCIe Hot Plug Enable/Disable per port
+  0(Default): Disable, 1: Enable
+**/
+  UINT8                       PegRootPortHPE[4];
+
+/** Offset 0x0154 - DeEmphasis control for DMI
+  DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB
+  0: -6dB, 1: -3.5dB
+**/
+  UINT8                       DmiDeEmphasis;
+
+/** Offset 0x0155 - Selection of the primary display device
+  0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics
+  0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics
+**/
+  UINT8                       PrimaryDisplay;
+
+/** Offset 0x0156 - Selection of iGFX GTT Memory size
+  1=2MB, 2=4MB, 3=8MB, Default is 3
+  1:2MB, 2:4MB, 3:8MB
+**/
+  UINT16                      GttSize;
+
+/** Offset 0x0158 - Temporary MMIO address for GMADR
+  The reference code will use this as Temporary MMIO address space to access GMADR
+  Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to
+  (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress
+  - 0x1) (Where ApertureSize = 256MB)
+**/
+  UINT32                      GmAdr;
+
+/** Offset 0x015C - Temporary MMIO address for GTTMMADR
+  The reference code will use this as Temporary MMIO address space to access GTTMMADR
+  Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr
+  to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO
+  + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)
+**/
+  UINT32                      GttMmAdr;
+
+/** Offset 0x0160 - Selection of PSMI Region size
+  0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0
+  0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB
+**/
+  UINT8                       PsmiRegionSize;
+
+/** Offset 0x0161 - Switchable Graphics GPIO information for PEG 0
+  Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs
+**/
+  UINT8                       SaRtd3Pcie0Gpio[24];
+
+/** Offset 0x0179 - Switchable Graphics GPIO information for PEG 1
+  Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs
+**/
+  UINT8                       SaRtd3Pcie1Gpio[24];
+
+/** Offset 0x0191 - Switchable Graphics GPIO information for PEG 2
+  Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs
+**/
+  UINT8                       SaRtd3Pcie2Gpio[24];
+
+/** Offset 0x01A9 - Switchable Graphics GPIO information for PEG 3
+  Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs
+**/
+  UINT8                       SaRtd3Pcie3Gpio[24];
+
+/** Offset 0x01C1 - Enable/Disable MRC TXT dependency
+  When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default):
+  MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization
+  $EN_DIS
+**/
+  UINT8                       TxtImplemented;
+
+/** Offset 0x01C2 - Enable/Disable SA OcSupport
+  Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport
+  $EN_DIS
+**/
+  UINT8                       SaOcSupport;
+
+/** Offset 0x01C3 - GT slice Voltage Mode
+  0(Default): Adaptive, 1: Override
+  0: Adaptive, 1: Override
+**/
+  UINT8                       GtVoltageMode;
+
+/** Offset 0x01C4 - Maximum GTs turbo ratio override
+  0(Default)=Minimal/Auto, 60=Maximum
+**/
+  UINT8                       GtMaxOcRatio;
+
+/** Offset 0x01C5
+**/
+  UINT8                       UnusedUpdSpace3;
+
+/** Offset 0x01C6 - The voltage offset applied to GT slice
+  0(Default)=Minimal, 1000=Maximum
+**/
+  UINT16                      GtVoltageOffset;
+
+/** Offset 0x01C8 - The GT slice voltage override which is applied to the entire range of GT frequencies
+  0(Default)=Minimal, 2000=Maximum
+**/
+  UINT16                      GtVoltageOverride;
+
+/** Offset 0x01CA - adaptive voltage applied during turbo frequencies
+  0(Default)=Minimal, 2000=Maximum
+**/
+  UINT16                      GtExtraTurboVoltage;
+
+/** Offset 0x01CC - voltage offset applied to the SA
+  0(Default)=Minimal, 1000=Maximum
+**/
+  UINT16                      SaVoltageOffset;
+
+/** Offset 0x01CE - PCIe root port Function number for Switchable Graphics dGPU
+  Root port Index number to indicate which PCIe root port has dGPU
+**/
+  UINT8                       RootPortIndex;
+
+/** Offset 0x01CF - Realtime Memory Timing
+  0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
+  realtime memory timing changes after MRC_DONE.
+  0: Disabled, 1: Enabled
+**/
+  UINT8                       RealtimeMemoryTiming;
+
+/** Offset 0x01D0 - Enable/Disable SA IPU
+  Enable(Default): Enable SA IPU, Disable: Disable SA IPU
+  $EN_DIS
+**/
+  UINT8                       SaIpuEnable;
+
+/** Offset 0x01D1 - IPU IMR Configuration
+  0:IPU Camera, 1:IPU Gen Default is 0
+  0:IPU Camera, 1:IPU Gen
+**/
+  UINT8                       SaIpuImrConfiguration;
+
+/** Offset 0x01D2 - Selection of PSMI Support On/Off
+  0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support
+  $EN_DIS
+**/
+  UINT8                       GtPsmiSupport;
+
+/** Offset 0x01D3 - GT unslice Voltage Mode
+  0(Default): Adaptive, 1: Override
+  0: Adaptive, 1: Override
+**/
+  UINT8                       GtusVoltageMode;
+
+/** Offset 0x01D4 - voltage offset applied to GT unslice
+  0(Default)=Minimal, 2000=Maximum
+**/
+  UINT16                      GtusVoltageOffset;
+
+/** Offset 0x01D6 - GT unslice voltage override which is applied to the entire range of GT frequencies
+  0(Default)=Minimal, 2000=Maximum
+**/
+  UINT16                      GtusVoltageOverride;
+
+/** Offset 0x01D8 - adaptive voltage applied during turbo frequencies
+  0(Default)=Minimal, 2000=Maximum
+**/
+  UINT16                      GtusExtraTurboVoltage;
+
+/** Offset 0x01DA - Maximum GTus turbo ratio override
+  0(Default)=Minimal, 60=Maximum
+**/
+  UINT8                       GtusMaxOcRatio;
+
+/** Offset 0x01DB - SaPreMemProductionRsvd
+  Reserved for SA Pre-Mem Production
+  $EN_DIS
+**/
+  UINT8                       SaPreMemProductionRsvd[1];
+
+/** Offset 0x01DC - Per-core HT Disable
+  Defines the per-core HT disable mask where: 1 - Disable selected logical core HT,
+  0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value
+  of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have
+  HT enabled. Range is 0 - 0x1FF. You can only disable up to MAX_CORE_COUNT - 1.
+**/
+  UINT16                      PerCoreHtDisable;
+
+/** Offset 0x01DE - BIST on Reset
+  Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       BistOnReset;
+
+/** Offset 0x01DF - Skip Stop PBET Timer Enable/Disable
+  Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable
+  $EN_DIS
+**/
+  UINT8                       SkipStopPbet;
+
+/** Offset 0x01E0 - C6DRAM power gating feature
+  This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM
+  power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating
+  feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>.
+  $EN_DIS
+**/
+  UINT8                       EnableC6Dram;
+
+/** Offset 0x01E1 - Over clocking support
+  Over clocking support; <b>0: Disable</b>; 1: Enable
+  $EN_DIS
+**/
+  UINT8                       OcSupport;
+
+/** Offset 0x01E2 - Over clocking Lock
+  Over clocking Lock Enable/Disable; 0: Disable; <b>1: Enable</b>.
+  $EN_DIS
+**/
+  UINT8                       OcLock;
+
+/** Offset 0x01E3 - Maximum Core Turbo Ratio Override
+  Maximum core turbo ratio override allows to increase CPU core frequency beyond the
+  fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-255
+**/
+  UINT8                       CoreMaxOcRatio;
+
+/** Offset 0x01E4 - Core voltage mode
+  Core voltage mode; <b>0: Adaptive</b>; 1: Override.
+  $EN_DIS
+**/
+  UINT8                       CoreVoltageMode;
+
+/** Offset 0x01E5 - Program Cache Attributes
+  Program Cache Attributes; <b>0: Program</b>; 1: Disable Program.
+  $EN_DIS
+**/
+  UINT8                       DisableMtrrProgram;
+
+/** Offset 0x01E6 - Maximum clr turbo ratio override
+  Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
+  fused max turbo ratio limit. <b>0: Hardware defaults.</b>  Range: 0-255
+**/
+  UINT8                       RingMaxOcRatio;
+
+/** Offset 0x01E7 - Hyper Threading Enable/Disable
+  Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       HyperThreading;
+
+/** Offset 0x01E8 - CPU ratio value
+  CPU ratio value. Valid Range 0 to 63. CPU Ratio is 0 when disabled.
+**/
+  UINT8                       CpuRatio;
+
+/** Offset 0x01E9 - Boot frequency
+  Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.-
+  <b>1: Maximum non-turbo performance</b>.- 2: Turbo performance. @note If Turbo
+  is selected BIOS will start in max non-turbo mode and switch to Turbo mode.
+  0:0, 1:1, 2:2
+**/
+  UINT8                       BootFrequency;
+
+/** Offset 0x01EA - Number of active cores
+  Number of active cores(Depends on Number of cores). <b>0: All</b>;<b>1: 1 </b>;<b>2:
+  2 </b>;<b>3: 3 </b>
+  0:All, 1:1, 2:2, 3:3
+**/
+  UINT8                       ActiveCoreCount;
+
+/** Offset 0x01EB - Processor Early Power On Configuration FCLK setting
+  <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.-
+  2: 400 MHz. - 3: Reserved
+  0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
+**/
+  UINT8                       FClkFrequency;
+
+/** Offset 0x01EC - Set JTAG power in C10 and deeper power states
+  False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10
+  and deeper power states for debug purpose. <b>0: False</b>; 1: True.
+  0: False, 1: True
+**/
+  UINT8                       JtagC10PowerGateDisable;
+
+/** Offset 0x01ED - Enable or Disable VMX
+  Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.
+  $EN_DIS
+**/
+  UINT8                       VmxEnable;
+
+/** Offset 0x01EE - AVX2 Ratio Offset
+  0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
+  vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
+**/
+  UINT8                       Avx2RatioOffset;
+
+/** Offset 0x01EF - AVX3 Ratio Offset
+  0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
+  vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
+**/
+  UINT8                       Avx3RatioOffset;
+
+/** Offset 0x01F0 - BCLK Adaptive Voltage Enable
+  When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:
+  Disable;<b> 1: Enable
+  $EN_DIS
+**/
+  UINT8                       BclkAdaptiveVoltage;
+
+/** Offset 0x01F1 - Core PLL voltage offset
+  Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
+**/
+  UINT8                       CorePllVoltageOffset;
+
+/** Offset 0x01F2 - core voltage override
+  The core voltage override which is applied to the entire range of cpu core frequencies.
+  Valid Range 0 to 2000
+**/
+  UINT16                      CoreVoltageOverride;
+
+/** Offset 0x01F4 - Core Turbo voltage Adaptive
+  Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode.
+  Valid Range 0 to 2000
+**/
+  UINT16                      CoreVoltageAdaptive;
+
+/** Offset 0x01F6 - Core Turbo voltage Offset
+  The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000
+**/
+  UINT16                      CoreVoltageOffset;
+
+/** Offset 0x01F8 - Ring Downbin
+  Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
+  lower than the core ratio.0: Disable; <b>1: Enable.</b>
+  $EN_DIS
+**/
+  UINT8                       RingDownBin;
+
+/** Offset 0x01F9 - Ring voltage mode
+  Ring voltage mode; <b>0: Adaptive</b>; 1: Override.
+  $EN_DIS
+**/
+  UINT8                       RingVoltageMode;
+
+/** Offset 0x01FA - Ring voltage override
+  The ring voltage override which is applied to the entire range of cpu ring frequencies.
+  Valid Range 0 to 2000
+**/
+  UINT16                      RingVoltageOverride;
+
+/** Offset 0x01FC - Ring Turbo voltage Adaptive
+  Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode.
+  Valid Range 0 to 2000
+**/
+  UINT16                      RingVoltageAdaptive;
+
+/** Offset 0x01FE - Ring Turbo voltage Offset
+  The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000
+**/
+  UINT16                      RingVoltageOffset;
+
+/** Offset 0x0200 - TjMax Offset
+  TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
+  TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63
+**/
+  UINT8                       TjMaxOffset;
+
+/** Offset 0x0201 - BiosGuard
+  Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
+  $EN_DIS
+**/
+  UINT8                       BiosGuard;
+
+/** Offset 0x0202
+**/
+  UINT8                       BiosGuardToolsInterface;
+
+/** Offset 0x0203 - EnableSgx
+  Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control
+  0: Disable, 1: Enable, 2: Software Control
+**/
+  UINT8                       EnableSgx;
+
+/** Offset 0x0204 - Txt
+  Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable
+  $EN_DIS
+**/
+  UINT8                       Txt;
+
+/** Offset 0x0205
+**/
+  UINT8                       UnusedUpdSpace4[3];
+
+/** Offset 0x0208 - PrmrrSize
+  0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000
+**/
+  UINT32                      PrmrrSize;
+
+/** Offset 0x020C - SinitMemorySize
+  Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
+**/
+  UINT32                      SinitMemorySize;
+
+/** Offset 0x0210 - TxtHeapMemorySize
+  Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
+**/
+  UINT32                      TxtHeapMemorySize;
+
+/** Offset 0x0214 - TxtDprMemorySize
+  Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable
+**/
+  UINT32                      TxtDprMemorySize;
+
+/** Offset 0x0218 - TxtDprMemoryBase
+  Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
+**/
+  UINT64                      TxtDprMemoryBase;
+
+/** Offset 0x0220 - BiosAcmBase
+  Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
+**/
+  UINT32                      BiosAcmBase;
+
+/** Offset 0x0224 - BiosAcmSize
+  Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable
+**/
+  UINT32                      BiosAcmSize;
+
+/** Offset 0x0228 - ApStartupBase
+  Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
+**/
+  UINT32                      ApStartupBase;
+
+/** Offset 0x022C - TgaSize
+  Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable
+**/
+  UINT32                      TgaSize;
+
+/** Offset 0x0230 - TxtLcpPdBase
+  Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable
+**/
+  UINT64                      TxtLcpPdBase;
+
+/** Offset 0x0238 - TxtLcpPdSize
+  Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable
+**/
+  UINT64                      TxtLcpPdSize;
+
+/** Offset 0x0240 - IsTPMPresence
+  IsTPMPresence default values
+**/
+  UINT8                       IsTPMPresence;
+
+/** Offset 0x0241 - Intel Speed Optimizer Enable
+  When enabled this feature automatically overclocks your processor. It changes the
+  All Core Frequency along with PL1, PL2, and IccMax. </b>0: Disable;<b> 1: Enable
+  $EN_DIS
+**/
+  UINT8                       AutoEasyOverclock;
+
+/** Offset 0x0242 - ReservedSecurityPreMem
+  Reserved for Security Pre-Mem
+  $EN_DIS
+**/
+  UINT8                       ReservedSecurityPreMem[2];
+
+/** Offset 0x0244 - Base addresses for VT-d function MMIO access
+  Base addresses for VT-d MMIO access per VT-d engine
+**/
+  UINT32                      VtdBaseAddress[3];
+
+/** Offset 0x0250 - Enable SMBus
+  Enable/disable SMBus controller.
+  $EN_DIS
+**/
+  UINT8                       SmbusEnable;
+
+/** Offset 0x0251 - Platform Debug Consent
+  To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type.
+  Enabling this BIOS option may alter the default value of other debug-related BIOS
+  options. Note: DCI OOB (aka BSSB) uses CCA probe; [DCI OOB+DbC] and [USB2 DbC]
+  have the same setting
+  0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC),
+  4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC)
+**/
+  UINT8                       PlatformDebugConsent;
+
+/** Offset 0x0252 - USB3 Type-C UFP2DFP Kernel/Platform Debug Support
+  This BIOS option enables kernel and platform debug for USB3 interface over a UFP
+  Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting.
+  0:Disabled, 1:Enabled, 2:No Change
+**/
+  UINT8                       DciUsb3TypecUfpDbg;
+
+/** Offset 0x0253 - PCH Trace Hub Mode
+  Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger'
+  if Trace Hub is used by target debugger software or 'Disable' trace hub functionality.
+  0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode
+**/
+  UINT8                       PchTraceHubMode;
+
+/** Offset 0x0254 - PCH Trace Hub Memory Region 0 buffer Size
+  Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB,
+  128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB.
+  0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
+**/
+  UINT8                       PchTraceHubMemReg0Size;
+
+/** Offset 0x0255 - PCH Trace Hub Memory Region 1 buffer Size
+  Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB,
+  128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB.
+  0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
+**/
+  UINT8                       PchTraceHubMemReg1Size;
+
+/** Offset 0x0256 - Enable Intel HD Audio (Azalia)
+  0: Disable, 1: Enable (Default) Azalia controller
+  $EN_DIS
+**/
+  UINT8                       PchHdaEnable;
+
+/** Offset 0x0257 - Enable PCH ISH Controller
+  0: Disable, 1: Enable (Default) ISH Controller
+  $EN_DIS
+**/
+  UINT8                       PchIshEnable;
+
+/** Offset 0x0258 - Enable PCH HSIO PCIE Rx Set Ctle
+  Enable PCH PCIe Gen 3 Set CTLE Value.
+**/
+  UINT8                       PchPcieHsioRxSetCtleEnable[24];
+
+/** Offset 0x0270 - PCH HSIO PCIE Rx Set Ctle Value
+  PCH PCIe Gen 3 Set CTLE Value.
+**/
+  UINT8                       PchPcieHsioRxSetCtle[24];
+
+/** Offset 0x0288 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchPcieHsioTxGen1DownscaleAmpEnable[24];
+
+/** Offset 0x02A0 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+  PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
+**/
+  UINT8                       PchPcieHsioTxGen1DownscaleAmp[24];
+
+/** Offset 0x02B8 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchPcieHsioTxGen2DownscaleAmpEnable[24];
+
+/** Offset 0x02D0 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+  PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
+**/
+  UINT8                       PchPcieHsioTxGen2DownscaleAmp[24];
+
+/** Offset 0x02E8 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchPcieHsioTxGen3DownscaleAmpEnable[24];
+
+/** Offset 0x0300 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
+  PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
+**/
+  UINT8                       PchPcieHsioTxGen3DownscaleAmp[24];
+
+/** Offset 0x0318 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchPcieHsioTxGen1DeEmphEnable[24];
+
+/** Offset 0x0330 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
+  PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
+**/
+  UINT8                       PchPcieHsioTxGen1DeEmph[24];
+
+/** Offset 0x0348 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchPcieHsioTxGen2DeEmph3p5Enable[24];
+
+/** Offset 0x0360 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
+  PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.
+**/
+  UINT8                       PchPcieHsioTxGen2DeEmph3p5[24];
+
+/** Offset 0x0378 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchPcieHsioTxGen2DeEmph6p0Enable[24];
+
+/** Offset 0x0390 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
+  PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.
+**/
+  UINT8                       PchPcieHsioTxGen2DeEmph6p0[24];
+
+/** Offset 0x03A8 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchSataHsioRxGen1EqBoostMagEnable[8];
+
+/** Offset 0x03B0 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+  PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
+**/
+  UINT8                       PchSataHsioRxGen1EqBoostMag[8];
+
+/** Offset 0x03B8 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchSataHsioRxGen2EqBoostMagEnable[8];
+
+/** Offset 0x03C0 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+  PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
+**/
+  UINT8                       PchSataHsioRxGen2EqBoostMag[8];
+
+/** Offset 0x03C8 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchSataHsioRxGen3EqBoostMagEnable[8];
+
+/** Offset 0x03D0 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+  PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
+**/
+  UINT8                       PchSataHsioRxGen3EqBoostMag[8];
+
+/** Offset 0x03D8 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchSataHsioTxGen1DownscaleAmpEnable[8];
+
+/** Offset 0x03E0 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
+  PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.
+**/
+  UINT8                       PchSataHsioTxGen1DownscaleAmp[8];
+
+/** Offset 0x03E8 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchSataHsioTxGen2DownscaleAmpEnable[8];
+
+/** Offset 0x03F0 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value
+  PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value.
+**/
+  UINT8                       PchSataHsioTxGen2DownscaleAmp[8];
+
+/** Offset 0x03F8 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchSataHsioTxGen3DownscaleAmpEnable[8];
+
+/** Offset 0x0400 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value
+  PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value.
+**/
+  UINT8                       PchSataHsioTxGen3DownscaleAmp[8];
+
+/** Offset 0x0408 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchSataHsioTxGen1DeEmphEnable[8];
+
+/** Offset 0x0410 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
+  PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.
+**/
+  UINT8                       PchSataHsioTxGen1DeEmph[8];
+
+/** Offset 0x0418 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchSataHsioTxGen2DeEmphEnable[8];
+
+/** Offset 0x0420 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
+  PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.
+**/
+  UINT8                       PchSataHsioTxGen2DeEmph[8];
+
+/** Offset 0x0428 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchSataHsioTxGen3DeEmphEnable[8];
+
+/** Offset 0x0430 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting
+  PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting.
+**/
+  UINT8                       PchSataHsioTxGen3DeEmph[8];
+
+/** Offset 0x0438 - PCH LPC Enhance the port 8xh decoding
+  Original LPC only decodes one byte of port 80h.
+  $EN_DIS
+**/
+  UINT8                       PchLpcEnhancePort8xhDecoding;
+
+/** Offset 0x0439 - PCH Port80 Route
+  Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
+  $EN_DIS
+**/
+  UINT8                       PchPort80Route;
+
+/** Offset 0x043A - Enable SMBus ARP support
+  Enable SMBus ARP support.
+  $EN_DIS
+**/
+  UINT8                       SmbusArpEnable;
+
+/** Offset 0x043B - Number of RsvdSmbusAddressTable.
+  The number of elements in the RsvdSmbusAddressTable.
+**/
+  UINT8                       PchNumRsvdSmbusAddresses;
+
+/** Offset 0x043C - SMBUS Base Address
+  SMBUS Base Address (IO space).
+**/
+  UINT16                      PchSmbusIoBase;
+
+/** Offset 0x043E - Size of PCIe IMR.
+  Size of PCIe IMR in megabytes
+**/
+  UINT16                      PcieImrSize;
+
+/** Offset 0x0440 - Point of RsvdSmbusAddressTable
+  Array of addresses reserved for non-ARP-capable SMBus devices.
+**/
+  UINT32                      RsvdSmbusAddressTablePtr;
+
+/** Offset 0x0444 - Enable PCIE RP Mask
+  Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
+  for port1, bit1 for port2, and so on.
+**/
+  UINT32                      PcieRpEnableMask;
+
+/** Offset 0x0448 - Enable PCIe IMR
+  0:Disable, 1:Enable
+  $EN_DIS
+**/
+  UINT8                       PcieImrEnabled;
+
+/** Offset 0x0449 - Root port number for IMR.
+  Root port number for IMR.
+**/
+  UINT8                       ImrRpSelection;
+
+/** Offset 0x044A - Enable SMBus Alert Pin
+  Enable SMBus Alert Pin.
+  $EN_DIS
+**/
+  UINT8                       PchSmbAlertEnable;
+
+/** Offset 0x044B - Debug Interfaces
+  Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
+  BIT2 - Not used.
+**/
+  UINT8                       PcdDebugInterfaceFlags;
+
+/** Offset 0x044C - Serial Io Uart Debug Controller Number
+  Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
+  Core interface, it cannot be used for debug purpose.
+  0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
+**/
+  UINT8                       SerialIoUartDebugControllerNumber;
+
+/** Offset 0x044D - Serial Io Uart Debug Auto Flow
+  Enables UART hardware flow control, CTS and RTS lines.
+  $EN_DIS
+**/
+  UINT8                       SerialIoUartDebugAutoFlow;
+
+/** Offset 0x044E
+**/
+  UINT8                       UnusedUpdSpace5[2];
+
+/** Offset 0x0450 - Serial Io Uart Debug BaudRate
+  Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
+  19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000
+**/
+  UINT32                      SerialIoUartDebugBaudRate;
+
+/** Offset 0x0454 - Serial Io Uart Debug Parity
+  Set default Parity.
+  0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
+**/
+  UINT8                       SerialIoUartDebugParity;
+
+/** Offset 0x0455 - Serial Io Uart Debug Stop Bits
+  Set default stop bits.
+  0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
+**/
+  UINT8                       SerialIoUartDebugStopBits;
+
+/** Offset 0x0456 - Serial Io Uart Debug Data Bits
+  Set default word length. 0: Default, 5,6,7,8
+  5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS
+**/
+  UINT8                       SerialIoUartDebugDataBits;
+
+/** Offset 0x0457 - Enable HD Audio DSP
+  Enable/disable HD Audio DSP feature.
+  $EN_DIS
+**/
+  UINT8                       PchHdaDspEnable;
+
+/** Offset 0x0458 - VC Type
+  Virtual Channel Type Select: 0: VC0, 1: VC1.
+  0: VC0, 1: VC1
+**/
+  UINT8                       PchHdaVcType;
+
+/** Offset 0x0459 - Universal Audio Architecture compliance for DSP enabled system
+  0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
+  driver or SST driver supported).
+  $EN_DIS
+**/
+  UINT8                       PchHdaDspUaaCompliance;
+
+/** Offset 0x045A - Enable HD Audio Link
+  Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
+  $EN_DIS
+**/
+  UINT8                       PchHdaAudioLinkHda;
+
+/** Offset 0x045B - Enable HD Audio DMIC0 Link
+  Deprecated.
+  $EN_DIS
+**/
+  UINT8                       PchHdaAudioLinkDmic0;
+
+/** Offset 0x045C - Enable HD Audio DMIC1 Link
+  Deprecated.
+  $EN_DIS
+**/
+  UINT8                       PchHdaAudioLinkDmic1;
+
+/** Offset 0x045D - Enable HD Audio SSP0 Link
+  Enable/disable HD Audio SSP0/I2S link. Muxed with HDA.
+  $EN_DIS
+**/
+  UINT8                       PchHdaAudioLinkSsp0;
+
+/** Offset 0x045E - Enable HD Audio SSP1 Link
+  Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2.
+  $EN_DIS
+**/
+  UINT8                       PchHdaAudioLinkSsp1;
+
+/** Offset 0x045F - Enable HD Audio SSP2 Link
+  Enable/disable HD Audio SSP2/I2S link.
+  $EN_DIS
+**/
+  UINT8                       PchHdaAudioLinkSsp2;
+
+/** Offset 0x0460 - Enable HD Audio SoundWire#1 Link
+  Enable/disable HD Audio SNDW1 link. Muxed with HDA.
+  $EN_DIS
+**/
+  UINT8                       PchHdaAudioLinkSndw1;
+
+/** Offset 0x0461 - Enable HD Audio SoundWire#2 Link
+  Enable/disable HD Audio SNDW2 link. Muxed with SSP1.
+  $EN_DIS
+**/
+  UINT8                       PchHdaAudioLinkSndw2;
+
+/** Offset 0x0462 - Enable HD Audio SoundWire#3 Link
+  Enable/disable HD Audio SNDW3 link. Muxed with DMIC1.
+  $EN_DIS
+**/
+  UINT8                       PchHdaAudioLinkSndw3;
+
+/** Offset 0x0463 - Enable HD Audio SoundWire#4 Link
+  Enable/disable HD Audio SNDW4 link. Muxed with DMIC0.
+  $EN_DIS
+**/
+  UINT8                       PchHdaAudioLinkSndw4;
+
+/** Offset 0x0464 - Soundwire Clock Buffer GPIO RCOMP Setting
+  0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance.
+  $EN_DIS
+**/
+  UINT8                       PchHdaSndwBufferRcomp;
+
+/** Offset 0x0465 - ReservedPchPreMem
+  Reserved for Pch Pre-Mem
+  $EN_DIS
+**/
+  UINT8                       ReservedPchPreMem[2];
+
+/** Offset 0x0467 - ISA Serial Base selection
+  Select ISA Serial Base address. Default is 0x3F8.
+  0:0x3F8, 1:0x2F8
+**/
+  UINT8                       PcdIsaSerialUartBase;
+
+/** Offset 0x0468 - GT PLL voltage offset
+  Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
+**/
+  UINT8                       GtPllVoltageOffset;
+
+/** Offset 0x0469 - Ring PLL voltage offset
+  Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
+**/
+  UINT8                       RingPllVoltageOffset;
+
+/** Offset 0x046A - System Agent PLL voltage offset
+  Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
+**/
+  UINT8                       SaPllVoltageOffset;
+
+/** Offset 0x046B - Memory Controller PLL voltage offset
+  Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
+**/
+  UINT8                       McPllVoltageOffset;
+
+/** Offset 0x046C - MRC Safe Config
+  Enables/Disable MRC Safe Config
+  $EN_DIS
+**/
+  UINT8                       MrcSafeConfig;
+
+/** Offset 0x046D - PcdSerialDebugBaudRate
+  Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
+  3:9600, 4:19200, 6:56700, 7:115200
+**/
+  UINT8                       PcdSerialDebugBaudRate;
+
+/** Offset 0x046E - HobBufferSize
+  Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB
+  total HOB size).
+  0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value
+**/
+  UINT8                       HobBufferSize;
+
+/** Offset 0x046F - Early Command Training
+  Enables/Disable Early Command Training
+  $EN_DIS
+**/
+  UINT8                       ECT;
+
+/** Offset 0x0470 - SenseAmp Offset Training
+  Enables/Disable SenseAmp Offset Training
+  $EN_DIS
+**/
+  UINT8                       SOT;
+
+/** Offset 0x0471 - Early ReadMPR Timing Centering 2D
+  Enables/Disable Early ReadMPR Timing Centering 2D
+  $EN_DIS
+**/
+  UINT8                       ERDMPRTC2D;
+
+/** Offset 0x0472 - Read MPR Training
+  Enables/Disable Read MPR Training
+  $EN_DIS
+**/
+  UINT8                       RDMPRT;
+
+/** Offset 0x0473 - Receive Enable Training
+  Enables/Disable Receive Enable Training
+  $EN_DIS
+**/
+  UINT8                       RCVET;
+
+/** Offset 0x0474 - Jedec Write Leveling
+  Enables/Disable Jedec Write Leveling
+  $EN_DIS
+**/
+  UINT8                       JWRL;
+
+/** Offset 0x0475 - Early Write Time Centering 2D
+  Enables/Disable Early Write Time Centering 2D
+  $EN_DIS
+**/
+  UINT8                       EWRTC2D;
+
+/** Offset 0x0476 - Early Read Time Centering 2D
+  Enables/Disable Early Read Time Centering 2D
+  $EN_DIS
+**/
+  UINT8                       ERDTC2D;
+
+/** Offset 0x0477 - Write Timing Centering 1D
+  Enables/Disable Write Timing Centering 1D
+  $EN_DIS
+**/
+  UINT8                       WRTC1D;
+
+/** Offset 0x0478 - Write Voltage Centering 1D
+  Enables/Disable Write Voltage Centering 1D
+  $EN_DIS
+**/
+  UINT8                       WRVC1D;
+
+/** Offset 0x0479 - Read Timing Centering 1D
+  Enables/Disable Read Timing Centering 1D
+  $EN_DIS
+**/
+  UINT8                       RDTC1D;
+
+/** Offset 0x047A - Dimm ODT Training
+  Enables/Disable Dimm ODT Training
+  $EN_DIS
+**/
+  UINT8                       DIMMODTT;
+
+/** Offset 0x047B - DIMM RON Training
+  Enables/Disable DIMM RON Training
+  $EN_DIS
+**/
+  UINT8                       DIMMRONT;
+
+/** Offset 0x047C - Write Drive Strength/Equalization 2D
+  Enables/Disable Write Drive Strength/Equalization 2D
+  $EN_DIS
+**/
+  UINT8                       WRDSEQT;
+
+/** Offset 0x047D - Write Slew Rate Training
+  Enables/Disable Write Slew Rate Training
+  $EN_DIS
+**/
+  UINT8                       WRSRT;
+
+/** Offset 0x047E - Read ODT Training
+  Enables/Disable Read ODT Training
+  $EN_DIS
+**/
+  UINT8                       RDODTT;
+
+/** Offset 0x047F - Read Equalization Training
+  Enables/Disable Read Equalization Training
+  $EN_DIS
+**/
+  UINT8                       RDEQT;
+
+/** Offset 0x0480 - Read Amplifier Training
+  Enables/Disable Read Amplifier Training
+  $EN_DIS
+**/
+  UINT8                       RDAPT;
+
+/** Offset 0x0481 - Write Timing Centering 2D
+  Enables/Disable Write Timing Centering 2D
+  $EN_DIS
+**/
+  UINT8                       WRTC2D;
+
+/** Offset 0x0482 - Read Timing Centering 2D
+  Enables/Disable Read Timing Centering 2D
+  $EN_DIS
+**/
+  UINT8                       RDTC2D;
+
+/** Offset 0x0483 - Write Voltage Centering 2D
+  Enables/Disable Write Voltage Centering 2D
+  $EN_DIS
+**/
+  UINT8                       WRVC2D;
+
+/** Offset 0x0484 - Read Voltage Centering 2D
+  Enables/Disable Read Voltage Centering 2D
+  $EN_DIS
+**/
+  UINT8                       RDVC2D;
+
+/** Offset 0x0485 - Command Voltage Centering
+  Enables/Disable Command Voltage Centering
+  $EN_DIS
+**/
+  UINT8                       CMDVC;
+
+/** Offset 0x0486 - Late Command Training
+  Enables/Disable Late Command Training
+  $EN_DIS
+**/
+  UINT8                       LCT;
+
+/** Offset 0x0487 - Round Trip Latency Training
+  Enables/Disable Round Trip Latency Training
+  $EN_DIS
+**/
+  UINT8                       RTL;
+
+/** Offset 0x0488 - Turn Around Timing Training
+  Enables/Disable Turn Around Timing Training
+  $EN_DIS
+**/
+  UINT8                       TAT;
+
+/** Offset 0x0489 - Memory Test
+  Enables/Disable Memory Test
+  $EN_DIS
+**/
+  UINT8                       MEMTST;
+
+/** Offset 0x048A - DIMM SPD Alias Test
+  Enables/Disable DIMM SPD Alias Test
+  $EN_DIS
+**/
+  UINT8                       ALIASCHK;
+
+/** Offset 0x048B - Receive Enable Centering 1D
+  Enables/Disable Receive Enable Centering 1D
+  $EN_DIS
+**/
+  UINT8                       RCVENC1D;
+
+/** Offset 0x048C - Retrain Margin Check
+  Enables/Disable Retrain Margin Check
+  $EN_DIS
+**/
+  UINT8                       RMC;
+
+/** Offset 0x048D - Write Drive Strength Up/Dn independently
+  Enables/Disable Write Drive Strength Up/Dn independently
+  $EN_DIS
+**/
+  UINT8                       WRDSUDT;
+
+/** Offset 0x048E - ECC Support
+  Enables/Disable ECC Support
+  $EN_DIS
+**/
+  UINT8                       EccSupport;
+
+/** Offset 0x048F - Memory Remap
+  Enables/Disable Memory Remap
+  $EN_DIS
+**/
+  UINT8                       RemapEnable;
+
+/** Offset 0x0490 - Rank Interleave support
+  Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at
+  the same time.
+  $EN_DIS
+**/
+  UINT8                       RankInterleave;
+
+/** Offset 0x0491 - Enhanced Interleave support
+  Enables/Disable Enhanced Interleave support
+  $EN_DIS
+**/
+  UINT8                       EnhancedInterleave;
+
+/** Offset 0x0492 - Memory Trace
+  Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of
+  equal size. This option may change TOLUD and REMAP values as needed.
+  $EN_DIS
+**/
+  UINT8                       MemoryTrace;
+
+/** Offset 0x0493 - Ch Hash Support
+  Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode
+  $EN_DIS
+**/
+  UINT8                       ChHashEnable;
+
+/** Offset 0x0494 - Extern Therm Status
+  Enables/Disable Extern Therm Status
+  $EN_DIS
+**/
+  UINT8                       EnableExtts;
+
+/** Offset 0x0495 - Closed Loop Therm Manage
+  Enables/Disable Closed Loop Therm Manage
+  $EN_DIS
+**/
+  UINT8                       EnableCltm;
+
+/** Offset 0x0496 - Open Loop Therm Manage
+  Enables/Disable Open Loop Therm Manage
+  $EN_DIS
+**/
+  UINT8                       EnableOltm;
+
+/** Offset 0x0497 - DDR PowerDown and idle counter
+  Enables/Disable DDR PowerDown and idle counter
+  $EN_DIS
+**/
+  UINT8                       EnablePwrDn;
+
+/** Offset 0x0498 - DDR PowerDown and idle counter - LPDDR
+  Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
+  $EN_DIS
+**/
+  UINT8                       EnablePwrDnLpddr;
+
+/** Offset 0x0499 - Use user provided power weights, scale factor, and channel power floor values
+  Enables/Disable Use user provided power weights, scale factor, and channel power
+  floor values
+  $EN_DIS
+**/
+  UINT8                       UserPowerWeightsEn;
+
+/** Offset 0x049A - RAPL PL Lock
+  Enables/Disable RAPL PL Lock
+  $EN_DIS
+**/
+  UINT8                       RaplLim2Lock;
+
+/** Offset 0x049B - RAPL PL 2 enable
+  Enables/Disable RAPL PL 2 enable
+  $EN_DIS
+**/
+  UINT8                       RaplLim2Ena;
+
+/** Offset 0x049C - RAPL PL 1 enable
+  Enables/Disable RAPL PL 1 enable
+  $EN_DIS
+**/
+  UINT8                       RaplLim1Ena;
+
+/** Offset 0x049D - SelfRefresh Enable
+  Enables/Disable SelfRefresh Enable
+  $EN_DIS
+**/
+  UINT8                       SrefCfgEna;
+
+/** Offset 0x049E - Throttler CKEMin Defeature - LPDDR
+  Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)
+  $EN_DIS
+**/
+  UINT8                       ThrtCkeMinDefeatLpddr;
+
+/** Offset 0x049F - Throttler CKEMin Defeature
+  Enables/Disable Throttler CKEMin Defeature
+  $EN_DIS
+**/
+  UINT8                       ThrtCkeMinDefeat;
+
+/** Offset 0x04A0 - Enable RH Prevention
+  Enables/Disable RH Prevention
+  $EN_DIS
+**/
+  UINT8                       RhPrevention;
+
+/** Offset 0x04A1 - Exit On Failure (MRC)
+  Enables/Disable Exit On Failure (MRC)
+  $EN_DIS
+**/
+  UINT8                       ExitOnFailure;
+
+/** Offset 0x04A2 - LPDDR Thermal Sensor
+  Enables/Disable LPDDR Thermal Sensor
+  $EN_DIS
+**/
+  UINT8                       DdrThermalSensor;
+
+/** Offset 0x04A3 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
+  Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
+  $EN_DIS
+**/
+  UINT8                       Ddr4DdpSharedClock;
+
+/** Offset 0x04A4 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
+  ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
+  $EN_DIS
+**/
+  UINT8                       Ddr4DdpSharedZq;
+
+/** Offset 0x04A5
+**/
+  UINT8                       UnusedUpdSpace6;
+
+/** Offset 0x04A6 - Ch Hash Mask
+  Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
+  BITS [19:6
+**/
+  UINT16                      ChHashMask;
+
+/** Offset 0x04A8 - Base reference clock value
+  Base reference clock value, in Hertz(Default is 125Hz)
+  100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz
+**/
+  UINT32                      BClkFrequency;
+
+/** Offset 0x04AC - Ch Hash Interleaved Bit
+  Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave
+  the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8
+  0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
+**/
+  UINT8                       ChHashInterleaveBit;
+
+/** Offset 0x04AD - Energy Scale Factor
+  Energy Scale Factor, Default is 4
+**/
+  UINT8                       EnergyScaleFact;
+
+/** Offset 0x04AE - EPG DIMM Idd3N
+  Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on
+  a per DIMM basis. Default is 26
+**/
+  UINT16                      Idd3n;
+
+/** Offset 0x04B0 - EPG DIMM Idd3P
+  Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated
+  on a per DIMM basis. Default is 11
+**/
+  UINT16                      Idd3p;
+
+/** Offset 0x04B2 - CMD Slew Rate Training
+  Enable/Disable CMD Slew Rate Training
+  $EN_DIS
+**/
+  UINT8                       CMDSR;
+
+/** Offset 0x04B3 - CMD Drive Strength and Tx Equalization
+  Enable/Disable CMD Drive Strength and Tx Equalization
+  $EN_DIS
+**/
+  UINT8                       CMDDSEQ;
+
+/** Offset 0x04B4 - CMD Normalization
+  Enable/Disable CMD Normalization
+  $EN_DIS
+**/
+  UINT8                       CMDNORM;
+
+/** Offset 0x04B5 - Early DQ Write Drive Strength and Equalization Training
+  Enable/Disable Early DQ Write Drive Strength and Equalization Training
+  $EN_DIS
+**/
+  UINT8                       EWRDSEQ;
+
+/** Offset 0x04B6 - RH Activation Probability
+  RH Activation Probability, Probability value is 1/2^(inputvalue)
+**/
+  UINT8                       RhActProbability;
+
+/** Offset 0x04B7 - RAPL PL 2 WindowX
+  Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def)
+**/
+  UINT8                       RaplLim2WindX;
+
+/** Offset 0x04B8 - RAPL PL 2 WindowY
+  Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def)
+**/
+  UINT8                       RaplLim2WindY;
+
+/** Offset 0x04B9 - RAPL PL 1 WindowX
+  Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
+**/
+  UINT8                       RaplLim1WindX;
+
+/** Offset 0x04BA - RAPL PL 1 WindowY
+  Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
+**/
+  UINT8                       RaplLim1WindY;
+
+/** Offset 0x04BB
+**/
+  UINT8                       UnusedUpdSpace7;
+
+/** Offset 0x04BC - RAPL PL 2 Power
+  range[0;2^14-1]= [2047.875;0]in W, (222= Def)
+**/
+  UINT16                      RaplLim2Pwr;
+
+/** Offset 0x04BE - RAPL PL 1 Power
+  range[0;2^14-1]= [2047.875;0]in W, (0= Def)
+**/
+  UINT16                      RaplLim1Pwr;
+
+/** Offset 0x04C0 - Warm Threshold Ch0 Dimm0
+  range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
+**/
+  UINT8                       WarmThresholdCh0Dimm0;
+
+/** Offset 0x04C1 - Warm Threshold Ch0 Dimm1
+  range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
+**/
+  UINT8                       WarmThresholdCh0Dimm1;
+
+/** Offset 0x04C2 - Warm Threshold Ch1 Dimm0
+  range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
+**/
+  UINT8                       WarmThresholdCh1Dimm0;
+
+/** Offset 0x04C3 - Warm Threshold Ch1 Dimm1
+  range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
+**/
+  UINT8                       WarmThresholdCh1Dimm1;
+
+/** Offset 0x04C4 - Hot Threshold Ch0 Dimm0
+  range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
+**/
+  UINT8                       HotThresholdCh0Dimm0;
+
+/** Offset 0x04C5 - Hot Threshold Ch0 Dimm1
+  range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
+**/
+  UINT8                       HotThresholdCh0Dimm1;
+
+/** Offset 0x04C6 - Hot Threshold Ch1 Dimm0
+  range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
+**/
+  UINT8                       HotThresholdCh1Dimm0;
+
+/** Offset 0x04C7 - Hot Threshold Ch1 Dimm1
+  range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
+**/
+  UINT8                       HotThresholdCh1Dimm1;
+
+/** Offset 0x04C8 - Warm Budget Ch0 Dimm0
+  range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
+**/
+  UINT8                       WarmBudgetCh0Dimm0;
+
+/** Offset 0x04C9 - Warm Budget Ch0 Dimm1
+  range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
+**/
+  UINT8                       WarmBudgetCh0Dimm1;
+
+/** Offset 0x04CA - Warm Budget Ch1 Dimm0
+  range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
+**/
+  UINT8                       WarmBudgetCh1Dimm0;
+
+/** Offset 0x04CB - Warm Budget Ch1 Dimm1
+  range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
+**/
+  UINT8                       WarmBudgetCh1Dimm1;
+
+/** Offset 0x04CC - Hot Budget Ch0 Dimm0
+  range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
+**/
+  UINT8                       HotBudgetCh0Dimm0;
+
+/** Offset 0x04CD - Hot Budget Ch0 Dimm1
+  range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
+**/
+  UINT8                       HotBudgetCh0Dimm1;
+
+/** Offset 0x04CE - Hot Budget Ch1 Dimm0
+  range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
+**/
+  UINT8                       HotBudgetCh1Dimm0;
+
+/** Offset 0x04CF - Hot Budget Ch1 Dimm1
+  range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
+**/
+  UINT8                       HotBudgetCh1Dimm1;
+
+/** Offset 0x04D0 - Idle Energy Ch0Dimm0
+  Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+  UINT8                       IdleEnergyCh0Dimm0;
+
+/** Offset 0x04D1 - Idle Energy Ch0Dimm1
+  Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+  UINT8                       IdleEnergyCh0Dimm1;
+
+/** Offset 0x04D2 - Idle Energy Ch1Dimm0
+  Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+  UINT8                       IdleEnergyCh1Dimm0;
+
+/** Offset 0x04D3 - Idle Energy Ch1Dimm1
+  Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+  UINT8                       IdleEnergyCh1Dimm1;
+
+/** Offset 0x04D4 - PowerDown Energy Ch0Dimm0
+  PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
+**/
+  UINT8                       PdEnergyCh0Dimm0;
+
+/** Offset 0x04D5 - PowerDown Energy Ch0Dimm1
+  PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
+**/
+  UINT8                       PdEnergyCh0Dimm1;
+
+/** Offset 0x04D6 - PowerDown Energy Ch1Dimm0
+  PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
+**/
+  UINT8                       PdEnergyCh1Dimm0;
+
+/** Offset 0x04D7 - PowerDown Energy Ch1Dimm1
+  PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
+**/
+  UINT8                       PdEnergyCh1Dimm1;
+
+/** Offset 0x04D8 - Activate Energy Ch0Dimm0
+  Activate Energy Contribution, range[255;0],(172= Def)
+**/
+  UINT8                       ActEnergyCh0Dimm0;
+
+/** Offset 0x04D9 - Activate Energy Ch0Dimm1
+  Activate Energy Contribution, range[255;0],(172= Def)
+**/
+  UINT8                       ActEnergyCh0Dimm1;
+
+/** Offset 0x04DA - Activate Energy Ch1Dimm0
+  Activate Energy Contribution, range[255;0],(172= Def)
+**/
+  UINT8                       ActEnergyCh1Dimm0;
+
+/** Offset 0x04DB - Activate Energy Ch1Dimm1
+  Activate Energy Contribution, range[255;0],(172= Def)
+**/
+  UINT8                       ActEnergyCh1Dimm1;
+
+/** Offset 0x04DC - Read Energy Ch0Dimm0
+  Read Energy Contribution, range[255;0],(212= Def)
+**/
+  UINT8                       RdEnergyCh0Dimm0;
+
+/** Offset 0x04DD - Read Energy Ch0Dimm1
+  Read Energy Contribution, range[255;0],(212= Def)
+**/
+  UINT8                       RdEnergyCh0Dimm1;
+
+/** Offset 0x04DE - Read Energy Ch1Dimm0
+  Read Energy Contribution, range[255;0],(212= Def)
+**/
+  UINT8                       RdEnergyCh1Dimm0;
+
+/** Offset 0x04DF - Read Energy Ch1Dimm1
+  Read Energy Contribution, range[255;0],(212= Def)
+**/
+  UINT8                       RdEnergyCh1Dimm1;
+
+/** Offset 0x04E0 - Write Energy Ch0Dimm0
+  Write Energy Contribution, range[255;0],(221= Def)
+**/
+  UINT8                       WrEnergyCh0Dimm0;
+
+/** Offset 0x04E1 - Write Energy Ch0Dimm1
+  Write Energy Contribution, range[255;0],(221= Def)
+**/
+  UINT8                       WrEnergyCh0Dimm1;
+
+/** Offset 0x04E2 - Write Energy Ch1Dimm0
+  Write Energy Contribution, range[255;0],(221= Def)
+**/
+  UINT8                       WrEnergyCh1Dimm0;
+
+/** Offset 0x04E3 - Write Energy Ch1Dimm1
+  Write Energy Contribution, range[255;0],(221= Def)
+**/
+  UINT8                       WrEnergyCh1Dimm1;
+
+/** Offset 0x04E4 - Throttler CKEMin Timer
+  Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
+  Default is 0x30
+**/
+  UINT8                       ThrtCkeMinTmr;
+
+/** Offset 0x04E5 - Cke Rank Mapping
+  Bits [7:4] - Channel 1, bits [3:0] - Channel 0. <b>0xAA=Default</b> Bit [i] specifies
+  which rank CKE[i] goes to.
+**/
+  UINT8                       CkeRankMapping;
+
+/** Offset 0x04E6 - Rapl Power Floor Ch0
+  Power budget ,range[255;0],(0= 5.3W Def)
+**/
+  UINT8                       RaplPwrFlCh0;
+
+/** Offset 0x04E7 - Rapl Power Floor Ch1
+  Power budget ,range[255;0],(0= 5.3W Def)
+**/
+  UINT8                       RaplPwrFlCh1;
+
+/** Offset 0x04E8 - Command Rate Support
+  CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs
+  0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS
+**/
+  UINT8                       EnCmdRate;
+
+/** Offset 0x04E9 - REFRESH_2X_MODE
+  0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot
+  0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only
+**/
+  UINT8                       Refresh2X;
+
+/** Offset 0x04EA - Energy Performance Gain
+  Enable/disable(default) Energy Performance Gain.
+  $EN_DIS
+**/
+  UINT8                       EpgEnable;
+
+/** Offset 0x04EB - Row Hammer Solution
+  Type of method used to prevent Row Hammer. Default is Hardware RHP
+  0:Hardware RHP, 1:2x Refresh
+**/
+  UINT8                       RhSolution;
+
+/** Offset 0x04EC - User Manual Threshold
+  Disabled: Predefined threshold will be used.\n
+  Enabled: User Input will be used.
+  $EN_DIS
+**/
+  UINT8                       UserThresholdEnable;
+
+/** Offset 0x04ED - User Manual Budget
+  Disabled: Configuration of memories will defined the Budget value.\n
+  Enabled: User Input will be used.
+  $EN_DIS
+**/
+  UINT8                       UserBudgetEnable;
+
+/** Offset 0x04EE -   TcritMax
+  Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax
+  has to be greater than THIGHMax .\n
+  Critical temperature will be  TcritMax
+**/
+  UINT8                       TsodTcritMax;
+
+/** Offset 0x04EF - Event mode
+  Disable:Comparator mode.\n
+  Enable:Interrupt mode
+  $EN_DIS
+**/
+  UINT8                       TsodEventMode;
+
+/** Offset 0x04F0 - EVENT polarity
+  Disable:Active LOW.\n
+  Enable:Active HIGH
+  $EN_DIS
+**/
+  UINT8                       TsodEventPolarity;
+
+/** Offset 0x04F1 - Critical event only
+  Disable:Trips on alarm or critical.\n
+  Enable:Trips only if criticaal temperature is reached
+  $EN_DIS
+**/
+  UINT8                       TsodCriticalEventOnly;
+
+/** Offset 0x04F2 - Event output control
+  Disable:Event output disable.\n
+  Enable:Event output enabled
+  $EN_DIS
+**/
+  UINT8                       TsodEventOutputControl;
+
+/** Offset 0x04F3 - Alarm window lock bit
+  Disable:Alarm trips are not locked and can be changed.\n
+  Enable:Alarm trips are locked and cannot be changed
+  $EN_DIS
+**/
+  UINT8                       TsodAlarmwindowLockBit;
+
+/** Offset 0x04F4 - Critical trip lock bit
+  Disable:Critical trip is not locked and can be changed.\n
+  Enable:Critical trip is locked and cannot be changed
+  $EN_DIS
+**/
+  UINT8                       TsodCriticaltripLockBit;
+
+/** Offset 0x04F5 - Shutdown mode
+  Disable:Temperature sensor enable.\n
+  Enable:Temperature sensor disable
+  $EN_DIS
+**/
+  UINT8                       TsodShutdownMode;
+
+/** Offset 0x04F6 - ThighMax
+  Thigh = ThighMax (Default is 93)
+**/
+  UINT8                       TsodThigMax;
+
+/** Offset 0x04F7 - User Manual Thig and Tcrit
+  Disabled(Default): Temperature will be given by the configuration of memories and
+  1x or 2xrefresh rate.\n
+  Enabled: User Input will define for Thigh and Tcrit.
+  $EN_DIS
+**/
+  UINT8                       TsodManualEnable;
+
+/** Offset 0x04F8 - Force OLTM or 2X Refresh when needed
+  Disabled(Default): = Force OLTM.\n
+  Enabled: = Force 2x Refresh.
+  $EN_DIS
+**/
+  UINT8                       ForceOltmOrRefresh2x;
+
+/** Offset 0x04F9 - Pwr Down Idle Timer
+  The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means
+  AUTO: 64 for ULX/ULT, 128 for DT/Halo
+**/
+  UINT8                       PwdwnIdleCounter;
+
+/** Offset 0x04FA - Bitmask of ranks that have CA bus terminated
+  Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. <b>0x01=Default,
+  Rank0 is terminating and Rank1 is non-terminating</b>
+**/
+  UINT8                       CmdRanksTerminated;
+
+/** Offset 0x04FB - GDXC  MOT enable
+  GDXC  MOT enable.
+  $EN_DIS
+**/
+  UINT8                       GdxcEnable;
+
+/** Offset 0x04FC - PcdSerialDebugLevel
+  Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+  Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+  Info & Verbose.
+  0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+  Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose
+**/
+  UINT8                       PcdSerialDebugLevel;
+
+/** Offset 0x04FD - Fivr Faults
+  Fivr Faults; 0: Disabled; <b>1: Enabled.</b>
+  $EN_DIS
+**/
+  UINT8                       FivrFaults;
+
+/** Offset 0x04FE - Fivr Efficiency
+  Fivr Efficiency Management; 0: Disabled; <b>1: Enabled.</b>
+  $EN_DIS
+**/
+  UINT8                       FivrEfficiency;
+
+/** Offset 0x04FF - Safe Mode Support
+  This option configures the varous items in the IO and MC to be more conservative.(def=Disable)
+  $EN_DIS
+**/
+  UINT8                       SafeMode;
+
+/** Offset 0x0500 - Ask MRC to clear memory content
+  Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
+  $EN_DIS
+**/
+  UINT8                       CleanMemory;
+
+/** Offset 0x0501 - LpDdrDqDqsReTraining
+  Enables/Disable LpDdrDqDqsReTraining
+  $EN_DIS
+**/
+  UINT8                       LpDdrDqDqsReTraining;
+
+/** Offset 0x0502 - Post Code Output Port
+  This option configures Post Code Output Port
+**/
+  UINT16                      PostCodeOutputPort;
+
+/** Offset 0x0504 - RMTLoopCount
+  Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
+**/
+  UINT8                       RMTLoopCount;
+
+/** Offset 0x0505 - BER Support
+  Enable/Disable the Rank Margin Tool interpolation/extrapolation.
+  0:Disable, 1:Enable
+**/
+  UINT8                       EnBER;
+
+/** Offset 0x0506 - Dual Dimm Per-Channel Board Type
+  Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used
+  to limit maximum frequency for some SKUs.
+  0:1DPC, 1:2DPC
+**/
+  UINT8                       DualDimmPerChannelBoardType;
+
+/** Offset 0x0507 - DDR4 Mixed U-DIMM 2DPC Limitation
+  Enable/Disable Frequency Limitation for DDR4 Mixed Dimm 2DPC Memory Configurations.
+  Disable=0, Enable(Default)=1
+  $EN_DIS
+**/
+  UINT8                       Ddr4Mixed2DpcLimit;
+
+/** Offset 0x0508 - RMT on Fast flow
+  Enable/Disable RMT on Fast flow. Default: Disabled
+  $EN_DIS
+**/
+  UINT8                       FastBootRmt;
+
+/** Offset 0x0509 - CFL Reserved
+  Reserved FspmConfig CFL
+  $EN_DIS
+**/
+  UINT8                       ReservedFspmUpdCfl;
+
+/** Offset 0x050A - Memory Test on Warm Boot
+  Run Base Memory Test on Warm Boot
+  0:Disable, 1:Enable
+**/
+  UINT8                       MemTestOnWarmBoot;
+
+/** Offset 0x050B - Throttler CKEMin Timer - LPDDR
+  Timer value for CKEMin (For LPDDR Only), range[255;0]. Req'd min of SC_ROUND_T +
+  BYTE_LENGTH (4). Default is 0x40
+**/
+  UINT8                       ThrtCkeMinTmrLpddr;
+
+/** Offset 0x050C - State of X2APIC_OPT_OUT bit in the DMAR table
+  0=Disable/Clear, 1=Enable/Set
+  $EN_DIS
+**/
+  UINT8                       X2ApicOptOut;
+
+/** Offset 0x050D - MRC Force training on Warm
+  Enables/Disable the MRC training on warm boot
+  $EN_DIS
+**/
+  UINT8                       MrcTrainOnWarm;
+
+/** Offset 0x050E - Lpddr Dram Odt
+  Override Enable/Disable for the ODT logic for LPDDR3 memory. Default is 2 (AUTO)
+  0:Disable, 1:Enable, 2:AUTO
+**/
+  UINT8                       LpddrDramOdt;
+
+/** Offset 0x050F - DDR4 Skip Refresh Enable
+  Enable/Disable of DDR4 Temperature Controlled Refresh on DRAM. Default is 1 (Enabled)
+  0:Disable, 1:Enable
+**/
+  UINT8                       Ddr4SkipRefreshEn;
+
+/** Offset 0x0510 - SerialDebugMrcLevel
+  MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+  Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+  Info & Verbose.
+  0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+  Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose
+**/
+  UINT8                       SerialDebugMrcLevel;
+
+/** Offset 0x0511 - Enable HD Audio Sndw Link IO Control
+  deprecated
+**/
+  UINT8                       PchHdaSndwLinkIoControlEnabled[4];
+
+/** Offset 0x0515 - Core VF Point Offset Mode
+  Selects Core Voltage & Frequency Point Offset between Legacy and Selection modes;
+  <b>0: Legacy</b>; 1: Selection.
+  0:Legacy, 1:Selection
+**/
+  UINT8                       CoreVfPointOffsetMode;
+
+/** Offset 0x0516 - Core VF Point Offset
+  Array used to specifies the Offset Voltage applied to the each selected Core VF
+  Point. This voltage is specified in millivolts.
+**/
+  UINT16                      CoreVfPointOffset[15];
+
+/** Offset 0x0534 - Core VF Point Offset Prefix
+  Sets the CoreVfPointOffset value as positive or negative for corresponding core
+  VF Point; <b>0: Positive </b>; 1: Negative.
+  0:Positive, 1:Negative
+**/
+  UINT8                       CoreVfPointOffsetPrefix[15];
+
+/** Offset 0x0543 - Core VF Point Ratio
+  Array for the each selected Core VF Point to display the ration.
+**/
+  UINT8                       CoreVfPointRatio[15];
+
+/** Offset 0x0552 - Core VF Point Count
+  Number of supported Core Voltage & Frequency Point Offset
+**/
+  UINT8                       CoreVfPointCount;
+
+/** Offset 0x0553
+**/
+  UINT8                       UnusedUpdSpace8[4];
+
+/** Offset 0x0557
+**/
+  UINT8                       ReservedFspmUpd[1];
+} FSP_M_CONFIG;
+
+/** Fsp M Test Configuration
+**/
+typedef struct {
+
+/** Offset 0x0558
+**/
+  UINT32                      Signature;
+
+/** Offset 0x055C - Skip external display device scanning
+  Enable: Do not scan for external display device, Disable (Default): Scan external
+  display devices
+  $EN_DIS
+**/
+  UINT8                       SkipExtGfxScan;
+
+/** Offset 0x055D - Generate BIOS Data ACPI Table
+  Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it
+  $EN_DIS
+**/
+  UINT8                       BdatEnable;
+
+/** Offset 0x055E - Detect External Graphics device for LegacyOpROM
+  Detect and report if external graphics device only support LegacyOpROM or not (to
+  support CSM auto-enable). Enable(Default)=1, Disable=0
+  $EN_DIS
+**/
+  UINT8                       ScanExtGfxForLegacyOpRom;
+
+/** Offset 0x055F - Lock PCU Thermal Management registers
+  Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
+  $EN_DIS
+**/
+  UINT8                       LockPTMregs;
+
+/** Offset 0x0560 - DMI Max Link Speed
+  Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
+  Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
+  0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
+**/
+  UINT8                       DmiMaxLinkSpeed;
+
+/** Offset 0x0561 - DMI Equalization Phase 2
+  DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default):
+  AUTO - Use the current default method
+  0:Disable phase2, 1:Enable phase2, 2:Auto
+**/
+  UINT8                       DmiGen3EqPh2Enable;
+
+/** Offset 0x0562 - DMI Gen3 Equalization Phase3
+  DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
+  HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
+  Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
+  EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
+  Phase1), Disabled(0x4): Bypass Equalization Phase 3
+  0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
+**/
+  UINT8                       DmiGen3EqPh3Method;
+
+/** Offset 0x0563 - Phase2 EQ enable on the PEG 0:1:0.
+  Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
+  Enable phase 2, Auto(0x2)(Default): Use the current default method
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       Peg0Gen3EqPh2Enable;
+
+/** Offset 0x0564 - Phase2 EQ enable on the PEG 0:1:1.
+  Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
+  Enable phase 2, Auto(0x2)(Default): Use the current default method
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       Peg1Gen3EqPh2Enable;
+
+/** Offset 0x0565 - Phase2 EQ enable on the PEG 0:1:2.
+  Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
+  Enable phase 2, Auto(0x2)(Default): Use the current default method
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       Peg2Gen3EqPh2Enable;
+
+/** Offset 0x0566 - Phase2 EQ enable on the PEG 0:1:3.
+  Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
+  Enable phase 2, Auto(0x2)(Default): Use the current default method
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       Peg3Gen3EqPh2Enable;
+
+/** Offset 0x0567 - Phase3 EQ method on the PEG 0:1:0.
+  PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
+  HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
+  Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
+  EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
+  Phase1), Disabled(0x4): Bypass Equalization Phase 3
+  0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
+**/
+  UINT8                       Peg0Gen3EqPh3Method;
+
+/** Offset 0x0568 - Phase3 EQ method on the PEG 0:1:1.
+  PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
+  HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
+  Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
+  EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
+  Phase1), Disabled(0x4): Bypass Equalization Phase 3
+  0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
+**/
+  UINT8                       Peg1Gen3EqPh3Method;
+
+/** Offset 0x0569 - Phase3 EQ method on the PEG 0:1:2.
+  PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
+  HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
+  Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
+  EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
+  Phase1), Disabled(0x4): Bypass Equalization Phase 3
+  0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
+**/
+  UINT8                       Peg2Gen3EqPh3Method;
+
+/** Offset 0x056A - Phase3 EQ method on the PEG 0:1:3.
+  PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
+  HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
+  Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
+  EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
+  Phase1), Disabled(0x4): Bypass Equalization Phase 3
+  0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
+**/
+  UINT8                       Peg3Gen3EqPh3Method;
+
+/** Offset 0x056B - Enable/Disable PEG GEN3 Static EQ Phase1 programming
+  Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
+  Presets Programming, Enabled(0x1)(Default): Enable  EQ Phase1 Static Presets Programming
+  $EN_DIS
+**/
+  UINT8                       PegGen3ProgramStaticEq;
+
+/** Offset 0x056C - PEG Gen3 SwEq Always Attempt
+  Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default):
+  Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test
+  and generate new EQ values every boot, not recommended
+  0:Disable, 1:Enable
+**/
+  UINT8                       Gen3SwEqAlwaysAttempt;
+
+/** Offset 0x056D - Select number of TxEq presets to test in the PCIe/DMI SwEq
+  Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test
+  Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the
+  current default method (Default)Auto will test Presets 7, 3, and 5.  It is possible
+  for this default to change over time;using Auto will ensure Reference Code always
+  uses the latest default settings
+  0:P7 P3 P5, 1:P0 to P9, 2:Auto
+**/
+  UINT8                       Gen3SwEqNumberOfPresets;
+
+/** Offset 0x056E - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq
+  Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization
+  Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default):
+  Use the current default
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       Gen3SwEqEnableVocTest;
+
+/** Offset 0x056F - PCIe Rx Compliance Testing Mode
+  Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1):
+  PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode;
+  it should only be set when doing PCIe compliance testing
+  $EN_DIS
+**/
+  UINT8                       PegRxCemTestingMode;
+
+/** Offset 0x0570 - PCIe Rx Compliance Loopback Lane  When PegRxCemTestingMode is Enabled
+  the specificied Lane (0 - 15) will be  used for RxCEMLoopback.  Default is Lane 0
+**/
+  UINT8                       PegRxCemLoopbackLane;
+
+/** Offset 0x0571 - Generate PCIe BDAT Margin Table
+  Set this policy to enable the generation and addition of PCIe margin data to the
+  BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin
+  data generation, Enable(0x1): Generate PCIe BDAT margin data
+  $EN_DIS
+**/
+  UINT8                       PegGenerateBdatMarginTable;
+
+/** Offset 0x0572 - PCIe Non-Protocol Awareness for Rx Compliance Testing
+  Set this policy to enable the generation and addition of PCIe margin data to the
+  BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness,
+  Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for
+  compliance testing
+  $EN_DIS
+**/
+  UINT8                       PegRxCemNonProtocolAwareness;
+
+/** Offset 0x0573 - PCIe Override RxCTLE
+  Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):
+  Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE
+  peak values unmodified
+  $EN_DIS
+**/
+  UINT8                       PegGen3RxCtleOverride;
+
+/** Offset 0x0574 - Rsvd
+  Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):
+  Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE
+  peak values unmodified
+  $EN_DIS
+**/
+  UINT8                       PegGen3Rsvd;
+
+/** Offset 0x0575 - PEG Gen3 Root port preset values per lane
+  Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
+**/
+  UINT8                       PegGen3RootPortPreset[20];
+
+/** Offset 0x0589 - PEG Gen3 End port preset values per lane
+  Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
+**/
+  UINT8                       PegGen3EndPointPreset[20];
+
+/** Offset 0x059D - PEG Gen3 End port Hint values per lane
+  Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
+**/
+  UINT8                       PegGen3EndPointHint[20];
+
+/** Offset 0x05B1
+**/
+  UINT8                       UnusedUpdSpace9;
+
+/** Offset 0x05B2 - Jitter Dwell Time for PCIe Gen3 Software Equalization
+  Range: 0-65535, default is 1000. @warning Do not change from the default
+**/
+  UINT16                      Gen3SwEqJitterDwellTime;
+
+/** Offset 0x05B4 - Jitter Error Target for PCIe Gen3 Software Equalization
+  Range: 0-65535, default is 1. @warning Do not change from the default
+**/
+  UINT16                      Gen3SwEqJitterErrorTarget;
+
+/** Offset 0x05B6 - VOC Dwell Time for PCIe Gen3 Software Equalization
+  Range: 0-65535, default is 10000. @warning Do not change from the default
+**/
+  UINT16                      Gen3SwEqVocDwellTime;
+
+/** Offset 0x05B8 - VOC Error Target for PCIe Gen3 Software Equalization
+  Range: 0-65535, default is 2. @warning Do not change from the default
+**/
+  UINT16                      Gen3SwEqVocErrorTarget;
+
+/** Offset 0x05BA - Panel Power Enable
+  Control for enabling/disabling VDD force bit (Required only for early enabling of
+  eDP panel). 0=Disable, 1(Default)=Enable
+  $EN_DIS
+**/
+  UINT8                       PanelPowerEnable;
+
+/** Offset 0x05BB - BdatTestType
+  Indicates the type of Memory Training data to populate into the BDAT ACPI table.
+  0:Rank Margin Tool, 1:Margin2D
+**/
+  UINT8                       BdatTestType;
+
+/** Offset 0x05BC - Disable VT-d
+  0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
+  $EN_DIS
+**/
+  UINT8                       VtdDisable;
+
+/** Offset 0x05BD
+**/
+  UINT8                       UnusedUpdSpace10;
+
+/** Offset 0x05BE - Delta T12 Power Cycle Delay required in ms
+  Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate
+  T12 Delay to max 500ms
+  0 : No Delay, 0xFFFF : Auto Calulate T12 Delay
+**/
+  UINT16                      DeltaT12PowerCycleDelayPreMem;
+
+/** Offset 0x05C0 - Oem T12 Dealy Override
+  Oem T12 Dealy Override. 0(Default)=Disable  1=Enable
+  $EN_DIS
+**/
+  UINT8                       OemT12DelayOverride;
+
+/** Offset 0x05C1 - SaPreMemTestRsvd
+  Reserved for SA Pre-Mem Test
+  $EN_DIS
+**/
+  UINT8                       SaPreMemTestRsvd[9];
+
+/** Offset 0x05CA - TotalFlashSize
+  Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
+**/
+  UINT16                      TotalFlashSize;
+
+/** Offset 0x05CC - BiosSize
+  Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable
+**/
+  UINT16                      BiosSize;
+
+/** Offset 0x05CE - TxtAcheckRequest
+  Enable/Disable. When Enabled, it will forcing calling TXT Acheck once.
+  $EN_DIS
+**/
+  UINT8                       TxtAcheckRequest;
+
+/** Offset 0x05CF - SecurityTestRsvd
+  Reserved for SA Pre-Mem Test
+  $EN_DIS
+**/
+  UINT8                       SecurityTestRsvd[3];
+
+/** Offset 0x05D2 - Smbus dynamic power gating
+  Disable or Enable Smbus dynamic power gating.
+  $EN_DIS
+**/
+  UINT8                       SmbusDynamicPowerGating;
+
+/** Offset 0x05D3 - Disable and Lock Watch Dog Register
+  Set 1 to clear WDT status, then disable and lock WDT registers.
+  $EN_DIS
+**/
+  UINT8                       WdtDisableAndLock;
+
+/** Offset 0x05D4 - SMBUS SPD Write Disable
+  Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
+  Disable bit. For security recommendations, SPD write disable bit must be set.
+  $EN_DIS
+**/
+  UINT8                       SmbusSpdWriteDisable;
+
+/** Offset 0x05D5 - ReservedPchPreMemTest
+  Reserved for Pch Pre-Mem Test
+  $EN_DIS
+**/
+  UINT8                       ReservedPchPreMemTest[16];
+
+/** Offset 0x05E5 - Force ME DID Init Status
+  Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set
+  ME DID init stat value
+  $EN_DIS
+**/
+  UINT8                       DidInitStat;
+
+/** Offset 0x05E6 - CPU Replaced Polling Disable
+  Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
+  $EN_DIS
+**/
+  UINT8                       DisableCpuReplacedPolling;
+
+/** Offset 0x05E7 - ME DID Message
+  Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent
+  the DID message from being sent)
+  $EN_DIS
+**/
+  UINT8                       SendDidMsg;
+
+/** Offset 0x05E8 - Check HECI message before send
+  Test, 0: disable, 1: enable, Enable/Disable message check.
+  $EN_DIS
+**/
+  UINT8                       DisableMessageCheck;
+
+/** Offset 0x05E9 - Skip MBP HOB
+  Test, 0: disable, 1: enable, Enable/Disable MOB HOB.
+  $EN_DIS
+**/
+  UINT8                       SkipMbpHob;
+
+/** Offset 0x05EA - HECI2 Interface Communication
+  Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
+  $EN_DIS
+**/
+  UINT8                       HeciCommunication2;
+
+/** Offset 0x05EB - Enable KT device
+  Test, 0: disable, 1: enable, Enable or Disable KT device.
+  $EN_DIS
+**/
+  UINT8                       KtDeviceEnable;
+
+/** Offset 0x05EC - tRd2RdSG
+  Delay between Read-to-Read commands in the same Bank Group. 0-Auto, Range 4-54.
+**/
+  UINT8                       tRd2RdSG;
+
+/** Offset 0x05ED - tRd2RdDG
+  Delay between Read-to-Read commands in different Bank Group for DDR4. All other
+  DDR technologies should set this equal to SG. 0-Auto, Range 4-54.
+**/
+  UINT8                       tRd2RdDG;
+
+/** Offset 0x05EE - tRd2RdDR
+  Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54.
+**/
+  UINT8                       tRd2RdDR;
+
+/** Offset 0x05EF - tRd2RdDD
+  Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54.
+**/
+  UINT8                       tRd2RdDD;
+
+/** Offset 0x05F0 - tWr2RdSG
+  Delay between Write-to-Read commands in the same Bank Group. 0-Auto, Range 4-86.
+**/
+  UINT8                       tWr2RdSG;
+
+/** Offset 0x05F1 - tWr2RdDG
+  Delay between Write-to-Read commands in different Bank Group for DDR4. All other
+  DDR technologies should set this equal to SG. 0-Auto, Range 4-54.
+**/
+  UINT8                       tWr2RdDG;
+
+/** Offset 0x05F2 - tWr2RdDR
+  Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54.
+**/
+  UINT8                       tWr2RdDR;
+
+/** Offset 0x05F3 - tWr2RdDD
+  Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54.
+**/
+  UINT8                       tWr2RdDD;
+
+/** Offset 0x05F4 - tWr2WrSG
+  Delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range 4-54.
+**/
+  UINT8                       tWr2WrSG;
+
+/** Offset 0x05F5 - tWr2WrDG
+  Delay between Write-to-Write commands in different Bank Group for DDR4. All other
+  DDR technologies should set this equal to SG. 0-Auto, Range 4-54.
+**/
+  UINT8                       tWr2WrDG;
+
+/** Offset 0x05F6 - tWr2WrDR
+  Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54.
+**/
+  UINT8                       tWr2WrDR;
+
+/** Offset 0x05F7 - tWr2WrDD
+  Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54.
+**/
+  UINT8                       tWr2WrDD;
+
+/** Offset 0x05F8 - tRd2WrSG
+  Delay between Read-to-Write commands in the same Bank Group. 0-Auto, Range 4-54.
+**/
+  UINT8                       tRd2WrSG;
+
+/** Offset 0x05F9 - tRd2WrDG
+  Delay between Read-to-Write commands in different Bank Group for DDR4. All other
+  DDR technologies should set this equal to SG. 0-Auto, Range 4-54.
+**/
+  UINT8                       tRd2WrDG;
+
+/** Offset 0x05FA - tRd2WrDR
+  Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54.
+**/
+  UINT8                       tRd2WrDR;
+
+/** Offset 0x05FB - tRd2WrDD
+  Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54.
+**/
+  UINT8                       tRd2WrDD;
+
+/** Offset 0x05FC - tRRD_L
+  Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 31
+**/
+  UINT8                       tRRD_L;
+
+/** Offset 0x05FD - tRRD_S
+  Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. 0:
+  AUTO, max: 31
+**/
+  UINT8                       tRRD_S;
+
+/** Offset 0x05FE - tWTR_L
+  Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. 0:
+  AUTO, max: 60
+**/
+  UINT8                       tWTR_L;
+
+/** Offset 0x05FF - tWTR_S
+  Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only.
+  0: AUTO, max: 28
+**/
+  UINT8                       tWTR_S;
+
+/** Offset 0x0600 - Skip CPU replacement check
+  Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
+  $EN_DIS
+**/
+  UINT8                       SkipCpuReplacementCheck;
+
+/** Offset 0x0601
+**/
+  UINT8                       ReservedFspmTestUpd[7];
+} FSP_M_TEST_CONFIG;
+
+/** Fsp M UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+  FSP_UPD_HEADER              FspUpdHeader;
+
+/** Offset 0x0020
+**/
+  FSPM_ARCH_UPD               FspmArchUpd;
+
+/** Offset 0x0040
+**/
+  FSP_M_CONFIG                FspmConfig;
+
+/** Offset 0x0558
+**/
+  FSP_M_TEST_CONFIG           FspmTestConfig;
+
+/** Offset 0x0608
+**/
+  UINT8                       UnusedUpdSpace11[6];
+
+/** Offset 0x060E
+**/
+  UINT16                      UpdTerminator;
+} FSPM_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/CometLakeFspBinPkg/CometLake2/Include/FspsUpd.h b/CometLakeFspBinPkg/CometLake2/Include/FspsUpd.h
new file mode 100644
index 0000000..ddfcb0c
--- /dev/null
+++ b/CometLakeFspBinPkg/CometLake2/Include/FspsUpd.h
@@ -0,0 +1,3675 @@
+/** @file
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPSUPD_H__
+#define __FSPSUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+///
+/// Azalia Header structure
+///
+typedef struct {
+  UINT16 VendorId;           ///< Codec Vendor ID
+  UINT16 DeviceId;           ///< Codec Device ID
+  UINT8  RevisionId;         ///< Revision ID of the codec. 0xFF matches any revision.
+  UINT8  SdiNum;             ///< SDI number, 0xFF matches any SDI.
+  UINT16 DataDwords;         ///< Number of data DWORDs pointed by the codec data buffer.
+  UINT32 Reserved;           ///< Reserved for future use. Must be set to 0.
+} AZALIA_HEADER;
+
+///
+/// Audio Azalia Verb Table structure
+///
+typedef struct {
+  AZALIA_HEADER Header;      ///< AZALIA PCH header
+  UINT32        *Data;       ///< Pointer to the data buffer. Its length is specified in the header
+} AUDIO_AZALIA_VERB_TABLE;
+
+///
+/// Refer to the definition of PCH_INT_PIN
+///
+typedef enum {
+  SiPchNoInt,        ///< No Interrupt Pin
+  SiPchIntA,
+  SiPchIntB,
+  SiPchIntC,
+  SiPchIntD
+} SI_PCH_INT_PIN;
+///
+/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
+///
+typedef struct {
+  UINT8        Device;                  ///< Device number
+  UINT8        Function;                ///< Device function
+  UINT8        IntX;                    ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
+  UINT8        Irq;                     ///< IRQ to be set for device.
+} SI_PCH_DEVICE_INTERRUPT_CONFIG;
+
+#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG  64       ///< Number of all PCH devices
+
+
+/** Fsp S Configuration
+**/
+typedef struct {
+
+/** Offset 0x0020 - Logo Pointer
+  Points to PEI Display Logo Image
+**/
+  UINT32                      LogoPtr;
+
+/** Offset 0x0024 - Logo Size
+  Size of PEI Display Logo Image
+**/
+  UINT32                      LogoSize;
+
+/** Offset 0x0028 - Graphics Configuration Ptr
+  Points to VBT
+**/
+  UINT32                      GraphicsConfigPtr;
+
+/** Offset 0x002C - Enable Device 4
+  Enable/disable Device 4
+  $EN_DIS
+**/
+  UINT8                       Device4Enable;
+
+/** Offset 0x002D
+**/
+  UINT8                       UnusedUpdSpace0[3];
+
+/** Offset 0x0030 - MicrocodeRegionBase
+  Memory Base of Microcode Updates
+**/
+  UINT32                      MicrocodeRegionBase;
+
+/** Offset 0x0034 - MicrocodeRegionSize
+  Size of Microcode Updates
+**/
+  UINT32                      MicrocodeRegionSize;
+
+/** Offset 0x0038 - Turbo Mode
+  Enable/Disable Turbo mode. 0: disable, 1: enable
+  $EN_DIS
+**/
+  UINT8                       TurboMode;
+
+/** Offset 0x0039 - PchDmiCwbEnable
+  Central Write Buffer feature configurable and disabled by default
+  $EN_DIS
+**/
+  UINT8                       PchDmiCwbEnable;
+
+/** Offset 0x003A - HECI3 state
+  The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed.
+  0: disable, 1: enable
+  $EN_DIS
+**/
+  UINT8                       Heci3Enabled;
+
+/** Offset 0x003B - HECI1 state
+  Determine if HECI1 is hidden prior to boot to OS. <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       Heci1Disabled;
+
+/** Offset 0x003C - AMT Switch
+  Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.
+  $EN_DIS
+**/
+  UINT8                       AmtEnabled;
+
+/** Offset 0x003D - WatchDog Timer Switch
+  Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting
+  is invalid if AmtEnabled is 0.
+  $EN_DIS
+**/
+  UINT8                       WatchDogEnabled;
+
+/** Offset 0x003E - Manageability Mode set by Mebx
+  Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode.
+  $EN_DIS
+**/
+  UINT8                       ManageabilityMode;
+
+/** Offset 0x003F - PET Progress
+  Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive
+  PET Events. Setting is invalid if AmtEnabled is 0.
+  $EN_DIS
+**/
+  UINT8                       FwProgress;
+
+/** Offset 0x0040 - SOL Switch
+  Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx.
+  Setting is invalid if AmtEnabled is 0.
+  $EN_DIS
+**/
+  UINT8                       AmtSolEnabled;
+
+/** Offset 0x0041
+**/
+  UINT8                       UnusedUpdSpace1;
+
+/** Offset 0x0042 - OS Timer
+  16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0.
+**/
+  UINT16                      WatchDogTimerOs;
+
+/** Offset 0x0044 - BIOS Timer
+  16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0.
+**/
+  UINT16                      WatchDogTimerBios;
+
+/** Offset 0x0046 - Remote Assistance Trigger Availablilty
+  Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx.
+  $EN_DIS
+**/
+  UINT8                       RemoteAssistance;
+
+/** Offset 0x0047 - KVM Switch
+  Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. Setting
+  is invalid if AmtEnabled is 0.
+  $EN_DIS
+**/
+  UINT8                       AmtKvmEnabled;
+
+/** Offset 0x0048 - MEBX execution
+  Enable/Disable. 0: Disable, 1: enable, Force MEBX execution.
+  $EN_DIS
+**/
+  UINT8                       ForcMebxSyncUp;
+
+/** Offset 0x0049 - Enable/Disable SA CRID
+  Enable: SA CRID, Disable (Default): SA CRID
+  $EN_DIS
+**/
+  UINT8                       CridEnable;
+
+/** Offset 0x004A - DMI ASPM
+  0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1
+  0:Disable, 1:L0s, 2:L1, 3:L0sL1
+**/
+  UINT8                       DmiAspm;
+
+/** Offset 0x004B - PCIe DeEmphasis control per root port
+  0: -6dB, 1(Default): -3.5dB
+  0:-6dB, 1:-3.5dB
+**/
+  UINT8                       PegDeEmphasis[4];
+
+/** Offset 0x004F - PCIe Slot Power Limit value per root port
+  Slot power limit value per root port
+**/
+  UINT8                       PegSlotPowerLimitValue[4];
+
+/** Offset 0x0053 - PCIe Slot Power Limit scale per root port
+  Slot power limit scale per root port
+  0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x
+**/
+  UINT8                       PegSlotPowerLimitScale[4];
+
+/** Offset 0x0057
+**/
+  UINT8                       UnusedUpdSpace2[1];
+
+/** Offset 0x0058 - PCIe Physical Slot Number per root port
+  Physical Slot Number per root port
+**/
+  UINT16                      PegPhysicalSlotNumber[4];
+
+/** Offset 0x0060 - Enable/Disable PavpEnable
+  Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
+  $EN_DIS
+**/
+  UINT8                       PavpEnable;
+
+/** Offset 0x0061 - CdClock Frequency selection
+  0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz
+  0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz
+**/
+  UINT8                       CdClock;
+
+/** Offset 0x0062 - Enable/Disable PeiGraphicsPeimInit
+  Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit
+  $EN_DIS
+**/
+  UINT8                       PeiGraphicsPeimInit;
+
+/** Offset 0x0063 - Enable or disable GNA device
+  0=Disable, 1(Default)=Enable
+  $EN_DIS
+**/
+  UINT8                       GnaEnable;
+
+/** Offset 0x0064 - State of X2APIC_OPT_OUT bit in the DMAR table
+  0=Disable/Clear, 1=Enable/Set
+  $EN_DIS
+**/
+  UINT8                       X2ApicOptOutDeprecated;
+
+/** Offset 0x0065
+**/
+  UINT8                       UnusedUpdSpace3[3];
+
+/** Offset 0x0068 - Base addresses for VT-d function MMIO access
+  Base addresses for VT-d MMIO access per VT-d engine
+**/
+  UINT32                      VtdBaseAddressDeprecated[3];
+
+/** Offset 0x0074 - Enable or disable eDP device
+  0=Disable, 1(Default)=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPortEdp;
+
+/** Offset 0x0075 - Enable or disable HPD of DDI port B
+  0=Disable, 1(Default)=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPortBHpd;
+
+/** Offset 0x0076 - Enable or disable HPD of DDI port C
+  0=Disable, 1(Default)=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPortCHpd;
+
+/** Offset 0x0077 - Enable or disable HPD of DDI port D
+  0=Disable, 1(Default)=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPortDHpd;
+
+/** Offset 0x0078 - Enable or disable HPD of DDI port F
+  0=Disable, 1(Default)=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPortFHpd;
+
+/** Offset 0x0079 - Enable or disable DDC of DDI port B
+  0=Disable, 1(Default)=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPortBDdc;
+
+/** Offset 0x007A - Enable or disable DDC of DDI port C
+  0=Disable, 1(Default)=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPortCDdc;
+
+/** Offset 0x007B - Enable or disable DDC of DDI port D
+  0=Disable, 1(Default)=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPortDDdc;
+
+/** Offset 0x007C - Enable or disable DDC of DDI port F
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPortFDdc;
+
+/** Offset 0x007D - Enable/Disable SkipS3CdClockInit
+  Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full
+  CD clock in S3 resume due to GOP absent
+  $EN_DIS
+**/
+  UINT8                       SkipS3CdClockInit;
+
+/** Offset 0x007E - Delta T12 Power Cycle Delay required in ms
+  DEPRECATED
+  0 : No Delay, 0xFFFF : Auto Calulate T12 Delay
+**/
+  UINT16                      DeltaT12PowerCycleDelay;
+
+/** Offset 0x0080 - Blt Buffer Address
+  Address of Blt buffer
+**/
+  UINT32                      BltBufferAddress;
+
+/** Offset 0x0084 - Blt Buffer Size
+  Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of
+  EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
+**/
+  UINT32                      BltBufferSize;
+
+/** Offset 0x0088 - Program GT Chicken bits
+  Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1]
+**/
+  UINT8                       ProgramGtChickenBits;
+
+/** Offset 0x0089 - SaPostMemProductionRsvd
+  Reserved for SA Post-Mem Production
+  $EN_DIS
+**/
+  UINT8                       SaPostMemProductionRsvd[34];
+
+/** Offset 0x00AB - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable
+  PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for
+  Alpine ridge
+**/
+  UINT8                       PcieRootPortGen2PllL1CgDisable[24];
+
+/** Offset 0x00C3 - Advanced Encryption Standard (AES) feature
+  Enable or Disable Advanced Encryption Standard (AES) feature; </b>0: Disable; <b>1: Enable
+  $EN_DIS
+**/
+  UINT8                       AesEnable;
+
+/** Offset 0x00C4 - Power State 3 enable/disable
+  PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.
+  For all VR Indexes
+**/
+  UINT8                       Psi3Enable[5];
+
+/** Offset 0x00C9 - Power State 4 enable/disable
+  PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.For
+  all VR Indexes
+**/
+  UINT8                       Psi4Enable[5];
+
+/** Offset 0x00CE - Imon slope correction
+  PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
+  Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes
+**/
+  UINT8                       ImonSlope[5];
+
+/** Offset 0x00D3 - Imon offset correction
+  DEPRECATED
+**/
+  UINT8                       ImonOffset[5];
+
+/** Offset 0x00D8 - Enable/Disable BIOS configuration of VR
+  Enable/Disable BIOS configuration of VR; <b>0: Disable</b>; 1: Enable.For all VR Indexes
+**/
+  UINT8                       VrConfigEnable[5];
+
+/** Offset 0x00DD - Thermal Design Current enable/disable
+  PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1:
+  Enable.For all VR Indexes
+**/
+  UINT8                       TdcEnable[5];
+
+/** Offset 0x00E2 - HECI3 state
+  PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
+  Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms
+  , 8 - 8ms , 10 - 10ms.For all VR Indexe
+**/
+  UINT8                       TdcTimeWindow[5];
+
+/** Offset 0x00E7 - Thermal Design Current Lock
+  PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.For
+  all VR Indexes
+**/
+  UINT8                       TdcLock[5];
+
+/** Offset 0x00EC - Platform Psys slope correction
+  PCODE MMIO Mailbox: Platform Psys slope correction. <b>0 - Auto</b> Specified in
+  1/100 increment values. Range is 0-200. 125 = 1.25
+**/
+  UINT8                       PsysSlope;
+
+/** Offset 0x00ED - Platform Psys offset correction
+  PCODE MMIO Mailbox: Platform Psys offset correction. <b>0 - Auto</b> Units 1/4,
+  Range 0-255. Value of 100 = 100/4 = 25 offset
+**/
+  UINT8                       PsysOffset;
+
+/** Offset 0x00EE - Acoustic Noise Mitigation feature
+  Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program
+  slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.<b>0:
+  Disabled</b>; 1: Enabled
+  $EN_DIS
+**/
+  UINT8                       AcousticNoiseMitigation;
+
+/** Offset 0x00EF - Disable Fast Slew Rate for Deep Package C States for VR IA domain
+  Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
+  feature enabled. <b>0: False</b>; 1: True
+  $EN_DIS
+**/
+  UINT8                       FastPkgCRampDisableIa;
+
+/** Offset 0x00F0 - Slew Rate configuration for Deep Package C States for VR IA domain
+  Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic
+  Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
+  0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
+**/
+  UINT8                       SlowSlewRateForIa;
+
+/** Offset 0x00F1 - Slew Rate configuration for Deep Package C States for VR GT domain
+  Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic
+  Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
+  0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
+**/
+  UINT8                       SlowSlewRateForGt;
+
+/** Offset 0x00F2 - Slew Rate configuration for Deep Package C States for VR SA domain
+  Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic
+  Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
+  0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
+**/
+  UINT8                       SlowSlewRateForSa;
+
+/** Offset 0x00F3
+**/
+  UINT8                       UnusedUpdSpace4[1];
+
+/** Offset 0x00F4 - Thermal Design Current current limit
+  PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.
+  Range is 0-4095. 1000 = 125A. <b>0: Auto</b>. For all VR Indexes
+**/
+  UINT16                      TdcPowerLimit[5];
+
+/** Offset 0x00FE - AcLoadline
+  PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
+  0-6249. <b>Intel Recommended Defaults vary by domain and SKU.
+**/
+  UINT16                      AcLoadline[5];
+
+/** Offset 0x0108 - DcLoadline
+  PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
+  0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b>
+**/
+  UINT16                      DcLoadline[5];
+
+/** Offset 0x0112 - Power State 1 Threshold current
+  PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A.
+**/
+  UINT16                      Psi1Threshold[5];
+
+/** Offset 0x011C - Power State 2 Threshold current
+  PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A.
+**/
+  UINT16                      Psi2Threshold[5];
+
+/** Offset 0x0126 - Power State 3 Threshold current
+  PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A.
+**/
+  UINT16                      Psi3Threshold[5];
+
+/** Offset 0x0130 - Icc Max limit
+  PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A
+**/
+  UINT16                      IccMax[5];
+
+/** Offset 0x013A - VR Voltage Limit
+  PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV.
+**/
+  UINT16                      VrVoltageLimit[5];
+
+/** Offset 0x0144 - Disable Fast Slew Rate for Deep Package C States for VR GT domain
+  Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
+  feature enabled. <b>0: False</b>; 1: True
+  $EN_DIS
+**/
+  UINT8                       FastPkgCRampDisableGt;
+
+/** Offset 0x0145 - Disable Fast Slew Rate for Deep Package C States for VR SA domain
+  Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
+  feature enabled. <b>0: False</b>; 1: True
+  $EN_DIS
+**/
+  UINT8                       FastPkgCRampDisableSa;
+
+/** Offset 0x0146 - Enable VR specific mailbox command
+  VR specific mailbox commands. <b>00b - no VR specific command sent.</b>  01b - A
+  VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific
+  command sent for PS4 exit issue. 11b - Reserved.
+  $EN_DIS
+**/
+  UINT8                       SendVrMbxCmd;
+
+/** Offset 0x0147 - Reserved
+  Reserved
+**/
+  UINT8                       Reserved2;
+
+/** Offset 0x0148 - Enable or Disable TXT
+  Enable or Disable TXT; 0: Disable; <b>1: Enable</b>.
+  $EN_DIS
+**/
+  UINT8                       TxtEnable;
+
+/** Offset 0x0149 - Deprecated DO NOT USE Skip Multi-Processor Initialization
+  @deprecated SkipMpInit has been moved to FspmUpd
+  $EN_DIS
+**/
+  UINT8                       SkipMpInitDeprecated;
+
+/** Offset 0x014A - McIVR RFI Frequency Prefix
+  PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. <b>0: Plus (+)</b>; 1:
+  Minus (-).
+**/
+  UINT8                       McivrRfiFrequencyPrefix;
+
+/** Offset 0x014B - McIVR RFI Frequency Adjustment
+  PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in
+  increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. <b>0: Auto</b>.
+**/
+  UINT8                       McivrRfiFrequencyAdjust;
+
+/** Offset 0x014C - FIVR RFI Frequency
+  PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. <b>0:
+  Auto</b>. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock;
+  0-1535 (Up to 153.5MHz) for 19MHz clock.
+**/
+  UINT16                      FivrRfiFrequency;
+
+/** Offset 0x014E - McIVR RFI Spread Spectrum
+  PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. <b>0: 0%</b>; 1: +/- 0.5%; 2: +/-
+  1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%.
+**/
+  UINT8                       McivrSpreadSpectrum;
+
+/** Offset 0x014F - FIVR RFI Spread Spectrum
+  PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. <b>0: 0%</b>;
+  Range: 0.0% to 10.0% (0-100).
+**/
+  UINT8                       FivrSpreadSpectrum;
+
+/** Offset 0x0150 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain
+  Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
+  feature enabled. <b>0: False</b>; 1: True
+  $EN_DIS
+**/
+  UINT8                       FastPkgCRampDisableFivr;
+
+/** Offset 0x0151 - Slew Rate configuration for Deep Package C States for VR FIVR domain
+  Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic
+  Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
+  0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
+**/
+  UINT8                       SlowSlewRateForFivr;
+
+/** Offset 0x0152
+**/
+  UINT8                       UnusedUpdSpace5[2];
+
+/** Offset 0x0154 - CpuBistData
+  Pointer CPU BIST Data
+**/
+  UINT32                      CpuBistData;
+
+/** Offset 0x0158 - Activates VR mailbox command for Intersil VR C-state issues.
+  Intersil VR mailbox command. <b>0 - no mailbox command sent.</b>  1 - VR mailbox
+  command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails.
+**/
+  UINT8                       IslVrCmd;
+
+/** Offset 0x0159
+**/
+  UINT8                       UnusedUpdSpace6[1];
+
+/** Offset 0x015A - Imon slope1 correction
+  PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
+  Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes
+**/
+  UINT16                      ImonSlope1[5];
+
+/** Offset 0x0164 - CPU VR Power Delivery Design
+  Used to communicate the power delivery design capability of the board. This value
+  is an enum of the available power delivery segments that are defined in the Platform
+  Design Guide.
+**/
+  UINT32                      VrPowerDeliveryDesign;
+
+/** Offset 0x0168 - Pre Wake Randomization time
+  PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization
+  time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.
+  Range 0-255 <b>0</b>.
+**/
+  UINT8                       PreWake;
+
+/** Offset 0x0169 - Ramp Up Randomization time
+  PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization
+  time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range
+  0-255 <b>0</b>.
+**/
+  UINT8                       RampUp;
+
+/** Offset 0x016A - Ramp Down Randomization time
+  PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization
+  time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range
+  0-255 <b>0</b>.
+**/
+  UINT8                       RampDown;
+
+/** Offset 0x016B
+**/
+  UINT8                       UnusedUpdSpace7;
+
+/** Offset 0x016C - CpuMpPpi
+  Pointer for CpuMpPpi
+**/
+  UINT32                      CpuMpPpi;
+
+/** Offset 0x0170 - CpuMpHob
+  Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage.
+**/
+  UINT32                      CpuMpHob;
+
+/** Offset 0x0174 - CPU Run Control
+  Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; <b>2:
+  No Change</b>
+  0:Disabled, 1:Enabled, 2:No Change
+**/
+  UINT8                       DebugInterfaceEnable;
+
+/** Offset 0x0175
+**/
+  UINT8                       UnusedUpdSpace8[1];
+
+/** Offset 0x0176 - Imon offset 1 correction
+  PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer.
+  Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b>
+**/
+  UINT16                      ImonOffset1[5];
+
+/** Offset 0x0180 - ReservedCpuPostMemProduction
+  Reserved for CPU Post-Mem Production
+  $EN_DIS
+**/
+  UINT8                       ReservedCpuPostMemProduction[8];
+
+/** Offset 0x0188 - Enable HD Audio DSP
+  Enable/disable HD Audio DSP feature.
+  $EN_DIS
+**/
+  UINT8                       PchHdaDspEnable;
+
+/** Offset 0x0189 - SPI0 Chip Select Polarity
+  Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow,
+  1:PchSerialIoCsActiveHigh
+**/
+  UINT8                       SerialIoSpi0CsPolarity[2];
+
+/** Offset 0x018B - SPI1 Chip Select Polarity
+  Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow,
+  1:PchSerialIoCsActiveHigh
+**/
+  UINT8                       SerialIoSpi1CsPolarity[2];
+
+/** Offset 0x018D - SPI2 Chip Select Polarity
+  Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow,
+  1:PchSerialIoCsActiveHigh
+**/
+  UINT8                       SerialIoSpi2CsPolarity[2];
+
+/** Offset 0x018F - SPI0 Chip Select Enable
+  0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled
+**/
+  UINT8                       SerialIoSpi0CsEnable[2];
+
+/** Offset 0x0191 - SPI1 Chip Select Enable
+  0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled
+**/
+  UINT8                       SerialIoSpi1CsEnable[2];
+
+/** Offset 0x0193 - SPI2 Chip Select Enable
+  0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled
+**/
+  UINT8                       SerialIoSpi2CsEnable[2];
+
+/** Offset 0x0195 - SPIn Device Mode
+  Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available
+  modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden
+**/
+  UINT8                       SerialIoSpiMode[3];
+
+/** Offset 0x0198 - SPIn Default Chip Select Output
+  Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available
+  options: 0:CS0, 1:CS1
+**/
+  UINT8                       SerialIoSpiDefaultCsOutput[3];
+
+/** Offset 0x019B - PCH SerialIo I2C Pads Termination
+  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5
+  pads termination respectively. One byte for each controller, byte0 for I2C0, byte1
+  for I2C1, and so on.
+**/
+  UINT8                       PchSerialIoI2cPadsTermination[6];
+
+/** Offset 0x01A1 - I2Cn Device Mode
+  Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available
+  modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden
+**/
+  UINT8                       SerialIoI2cMode[6];
+
+/** Offset 0x01A7 - UARTn Device Mode
+  Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available
+  modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
+  4:SerialIoUartSkipInit
+**/
+  UINT8                       SerialIoUartMode[3];
+
+/** Offset 0x01AA
+**/
+  UINT8                       UnusedUpdSpace9[2];
+
+/** Offset 0x01AC - Default BaudRate for each Serial IO UART
+  Set default BaudRate Supported from 0 - default to 6000000
+**/
+  UINT32                      SerialIoUartBaudRate[3];
+
+/** Offset 0x01B8 - Default ParityType for each Serial IO UART
+  Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
+**/
+  UINT8                       SerialIoUartParity[3];
+
+/** Offset 0x01BB - Default DataBits for each Serial IO UART
+  Set default word length. 0: Default, 5,6,7,8
+**/
+  UINT8                       SerialIoUartDataBits[3];
+
+/** Offset 0x01BE - Default StopBits for each Serial IO UART
+  Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3:
+  TwoStopBits
+**/
+  UINT8                       SerialIoUartStopBits[3];
+
+/** Offset 0x01C1 - Power Gating mode for each Serial IO UART that works in COM mode
+  Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto
+**/
+  UINT8                       SerialIoUartPowerGating[3];
+
+/** Offset 0x01C4 - Enable Dma for each Serial IO UART that supports it
+  Set DMA/PIO mode. 0: Disabled, 1: Enabled
+**/
+  UINT8                       SerialIoUartDmaEnable[3];
+
+/** Offset 0x01C7 - Enables UART hardware flow control, CTS and RTS lines
+  Enables UART hardware flow control, CTS and RTS lines.
+**/
+  UINT8                       SerialIoUartAutoFlow[3];
+
+/** Offset 0x01CA - Serial IO UART Pin Mux
+  Applies only to UART0 muxed with CNVI <b> 0 = GPIO C8 to C11 </b> 1 = GPIO F5 -
+  F7 (PCH LP) J5 - J7 (PCH H)
+**/
+  UINT8                       SerialIoUartPinMux[3];
+
+/** Offset 0x01CD - UART Number For Debug Purpose
+  UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected
+  as CNVi BT Core interface, it cannot be used for debug purpose.
+   0:UART0, 1:UART1, 2:UART2
+**/
+  UINT8                       SerialIoDebugUartNumber;
+
+/** Offset 0x01CE - Serial IO UART DBG2 table
+  Enable or disable Serial Io UART DBG2 table, default is Disable; <b>0: Disable;</b>
+  1: Enable.
+**/
+  UINT8                       SerialIoUartDbg2[3];
+
+/** Offset 0x01D1 - Enable eMMC Controller
+  Enable/disable eMMC Controller.
+  $EN_DIS
+**/
+  UINT8                       ScsEmmcEnabled;
+
+/** Offset 0x01D2 - Enable eMMC HS400 Mode
+  Enable eMMC HS400 Mode.
+  $EN_DIS
+**/
+  UINT8                       ScsEmmcHs400Enabled;
+
+/** Offset 0x01D3 - Enable SdCard Controller
+  Enable/disable SD Card Controller.
+  $EN_DIS
+**/
+  UINT8                       ScsSdCardEnabled;
+
+/** Offset 0x01D4 - Show SPI controller
+  Enable/disable to show SPI controller.
+  $EN_DIS
+**/
+  UINT8                       ShowSpiController;
+
+/** Offset 0x01D5 - Enable SATA SALP Support
+  Enable/disable SATA Aggressive Link Power Management.
+  $EN_DIS
+**/
+  UINT8                       SataSalpSupport;
+
+/** Offset 0x01D6 - Enable SATA ports
+  Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1,
+  and so on.
+**/
+  UINT8                       SataPortsEnable[8];
+
+/** Offset 0x01DE - Enable SATA DEVSLP Feature
+  Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each
+  port, byte0 for port0, byte1 for port1, and so on.
+**/
+  UINT8                       SataPortsDevSlp[8];
+
+/** Offset 0x01E6 - Enable USB2 ports
+  Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
+  port1, and so on.
+**/
+  UINT8                       PortUsb20Enable[16];
+
+/** Offset 0x01F6 - Enable USB3 ports
+  Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
+  port1, and so on.
+**/
+  UINT8                       PortUsb30Enable[10];
+
+/** Offset 0x0200 - Enable xDCI controller
+  Enable/disable to xDCI controller.
+  $EN_DIS
+**/
+  UINT8                       XdciEnable;
+
+/** Offset 0x0201
+**/
+  UINT8                       UnusedUpdSpace10[3];
+
+/** Offset 0x0204 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
+  The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
+**/
+  UINT32                      DevIntConfigPtr;
+
+/** Offset 0x0208 - Number of DevIntConfig Entry
+  Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
+  must not be NULL.
+**/
+  UINT8                       NumOfDevIntConfig;
+
+/** Offset 0x0209 - PIRQx to IRQx Map Config
+  PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for
+  PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy
+  8259 PCI mode.
+**/
+  UINT8                       PxRcConfig[8];
+
+/** Offset 0x0211 - Select GPIO IRQ Route
+  GPIO IRQ Select. The valid value is 14 or 15.
+**/
+  UINT8                       GpioIrqRoute;
+
+/** Offset 0x0212 - Select SciIrqSelect
+  SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.
+**/
+  UINT8                       SciIrqSelect;
+
+/** Offset 0x0213 - Select TcoIrqSelect
+  TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23.
+**/
+  UINT8                       TcoIrqSelect;
+
+/** Offset 0x0214 - Enable/Disable Tco IRQ
+  Enable/disable TCO IRQ
+  $EN_DIS
+**/
+  UINT8                       TcoIrqEnable;
+
+/** Offset 0x0215 - PCH HDA Verb Table Entry Number
+  Number of Entries in Verb Table.
+**/
+  UINT8                       PchHdaVerbTableEntryNum;
+
+/** Offset 0x0216
+**/
+  UINT8                       UnusedUpdSpace11[2];
+
+/** Offset 0x0218 - PCH HDA Verb Table Pointer
+  Pointer to Array of pointers to Verb Table.
+**/
+  UINT32                      PchHdaVerbTablePtr;
+
+/** Offset 0x021C - PCH HDA Codec Sx Wake Capability
+  Capability to detect wake initiated by a codec in Sx
+**/
+  UINT8                       PchHdaCodecSxWakeCapability;
+
+/** Offset 0x021D - Enable SATA
+  Enable/disable SATA controller.
+  $EN_DIS
+**/
+  UINT8                       SataEnable;
+
+/** Offset 0x021E - SATA Mode
+  Select SATA controller working mode.
+  0:AHCI, 1:RAID
+**/
+  UINT8                       SataMode;
+
+/** Offset 0x021F - USB Per Port HS Preemphasis Bias
+  USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
+  100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
+**/
+  UINT8                       Usb2AfePetxiset[16];
+
+/** Offset 0x022F - USB Per Port HS Transmitter Bias
+  USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
+  100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
+**/
+  UINT8                       Usb2AfeTxiset[16];
+
+/** Offset 0x023F - USB Per Port HS Transmitter Emphasis
+  USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
+  10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
+**/
+  UINT8                       Usb2AfePredeemp[16];
+
+/** Offset 0x024F - USB Per Port Half Bit Pre-emphasis
+  USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
+  One byte for each port.
+**/
+  UINT8                       Usb2AfePehalfbit[16];
+
+/** Offset 0x025F - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
+  Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
+  in arrary can be between 0-1. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxDeEmphEnable[10];
+
+/** Offset 0x0269 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
+  USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
+  <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.
+**/
+  UINT8                       Usb3HsioTxDeEmph[10];
+
+/** Offset 0x0273 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
+  Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
+  in arrary can be between 0-1. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxDownscaleAmpEnable[10];
+
+/** Offset 0x027D - USB 3.0 TX Output Downscale Amplitude Adjustment
+  USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default
+  = 00h</b>. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxDownscaleAmp[10];
+
+/** Offset 0x0287 - Enable xHCI LTR override
+  Enables override of recommended LTR values for xHCI
+  $EN_DIS
+**/
+  UINT8                       PchUsbLtrOverrideEnable;
+
+/** Offset 0x0288 - xHCI High Idle Time LTR override
+  Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
+**/
+  UINT32                      PchUsbLtrHighIdleTimeOverride;
+
+/** Offset 0x028C - xHCI Medium Idle Time LTR override
+  Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting
+**/
+  UINT32                      PchUsbLtrMediumIdleTimeOverride;
+
+/** Offset 0x0290 - xHCI Low Idle Time LTR override
+  Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting
+**/
+  UINT32                      PchUsbLtrLowIdleTimeOverride;
+
+/** Offset 0x0294 - Enable LAN
+  Enable/disable LAN controller.
+  $EN_DIS
+**/
+  UINT8                       PchLanEnable;
+
+/** Offset 0x0295 - Enable HD Audio Link
+  Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
+  $EN_DIS
+**/
+  UINT8                       PchHdaAudioLinkHda;
+
+/** Offset 0x0296 - Enable HD Audio DMIC0 Link
+  Enable/disable HD Audio DMIC0 link. Muxed with SNDW4.
+  $EN_DIS
+**/
+  UINT8                       PchHdaAudioLinkDmic0;
+
+/** Offset 0x0297 - Enable HD Audio DMIC1 Link
+  Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
+  $EN_DIS
+**/
+  UINT8                       PchHdaAudioLinkDmic1;
+
+/** Offset 0x0298 - Enable HD Audio SSP0 Link
+  Enable/disable HD Audio SSP0/I2S link. Muxed with HDA.
+  $EN_DIS
+**/
+  UINT8                       PchHdaAudioLinkSsp0;
+
+/** Offset 0x0299 - Enable HD Audio SSP1 Link
+  Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2.
+  $EN_DIS
+**/
+  UINT8                       PchHdaAudioLinkSsp1;
+
+/** Offset 0x029A - Enable HD Audio SSP2 Link
+  Enable/disable HD Audio SSP2/I2S link.
+  $EN_DIS
+**/
+  UINT8                       PchHdaAudioLinkSsp2;
+
+/** Offset 0x029B - Enable HD Audio SoundWire#1 Link
+  Enable/disable HD Audio SNDW1 link. Muxed with HDA.
+  $EN_DIS
+**/
+  UINT8                       PchHdaAudioLinkSndw1;
+
+/** Offset 0x029C - Enable HD Audio SoundWire#2 Link
+  Enable/disable HD Audio SNDW2 link. Muxed with SSP1.
+  $EN_DIS
+**/
+  UINT8                       PchHdaAudioLinkSndw2;
+
+/** Offset 0x029D - Enable HD Audio SoundWire#3 Link
+  Enable/disable HD Audio SNDW3 link. Muxed with DMIC1.
+  $EN_DIS
+**/
+  UINT8                       PchHdaAudioLinkSndw3;
+
+/** Offset 0x029E - Enable HD Audio SoundWire#4 Link
+  Enable/disable HD Audio SNDW4 link. Muxed with DMIC0.
+  $EN_DIS
+**/
+  UINT8                       PchHdaAudioLinkSndw4;
+
+/** Offset 0x029F - Soundwire Clock Buffer GPIO RCOMP Setting
+  0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance.
+  $EN_DIS
+**/
+  UINT8                       PchHdaSndwBufferRcomp;
+
+/** Offset 0x02A0 - PTM for PCIE RP Mask
+  Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable.
+  One bit for each port, bit0 for port1, bit1 for port2, and so on.
+**/
+  UINT32                      PcieRpPtmMask;
+
+/** Offset 0x02A4 - DPC for PCIE RP Mask
+  Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable.
+  One bit for each port, bit0 for port1, bit1 for port2, and so on.
+**/
+  UINT32                      PcieRpDpcMask;
+
+/** Offset 0x02A8 - DPC Extensions PCIE RP Mask
+  Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit
+  for each port, bit0 for port1, bit1 for port2, and so on.
+**/
+  UINT32                      PcieRpDpcExtensionsMask;
+
+/** Offset 0x02AC - USB PDO Programming
+  Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
+  during later phase. 1: enable, 0: disable
+  $EN_DIS
+**/
+  UINT8                       UsbPdoProgramming;
+
+/** Offset 0x02AD
+**/
+  UINT8                       UnusedUpdSpace12[3];
+
+/** Offset 0x02B0 - Power button debounce configuration
+  Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
+  be rounded down to closest supported on. 0: disable, 250-1024000us: supported range
+**/
+  UINT32                      PmcPowerButtonDebounce;
+
+/** Offset 0x02B4 - PCH eSPI Master and Slave BME enabled
+  PCH eSPI Master and Slave BME enabled
+  $EN_DIS
+**/
+  UINT8                       PchEspiBmeMasterSlaveEnabled;
+
+/** Offset 0x02B5 - PCH SATA use RST Legacy OROM
+  Use PCH SATA RST Legacy OROM when CSM is Enabled
+  $EN_DIS
+**/
+  UINT8                       SataRstLegacyOrom;
+
+/** Offset 0x02B6
+**/
+  UINT8                       UnusedUpdSpace13[2];
+
+/** Offset 0x02B8 - Trace Hub Memory Base
+  If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate
+  trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub
+  memory is configured properly.
+**/
+  UINT32                      TraceHubMemBase;
+
+/** Offset 0x02BC - PMC Debug Message Enable
+  When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW
+  will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix
+  $EN_DIS
+**/
+  UINT8                       PmcDbgMsgEn;
+
+/** Offset 0x02BD
+**/
+  UINT8                       UnusedUpdSpace14[3];
+
+/** Offset 0x02C0 - Pointer of ChipsetInit Binary
+  ChipsetInit Binary Pointer.
+**/
+  UINT32                      ChipsetInitBinPtr;
+
+/** Offset 0x02C4 - Length of ChipsetInit Binary
+  ChipsetInit Binary Length.
+**/
+  UINT32                      ChipsetInitBinLen;
+
+/** Offset 0x02C8 - Enable Ufs Controller
+  Enable/disable Ufs 2.0 Controller.
+  $EN_DIS
+**/
+  UINT8                       ScsUfsEnabled;
+
+/** Offset 0x02C9 - CNVi Configuration
+  This option allows for automatic detection of Connectivity Solution. [Auto Detection]
+  assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
+  0:Disable, 1:Auto
+**/
+  UINT8                       CnviMode;
+
+/** Offset 0x02CA - CNVi BT Core
+  Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
+  $EN_DIS
+**/
+  UINT8                       CnviBtCore;
+
+/** Offset 0x02CB - CNVi BT Audio Offload
+  Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE
+  $EN_DIS
+**/
+  UINT8                       CnviBtAudioOffload;
+
+/** Offset 0x02CC - SdCard power enable polarity
+  Choose SD_PWREN# polarity
+  0: Active low, 1: Active high
+**/
+  UINT8                       SdCardPowerEnableActiveHigh;
+
+/** Offset 0x02CD - PCH USB2 PHY Power Gating enable
+  1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY
+  Sus Well PG
+  $EN_DIS
+**/
+  UINT8                       PchUsb2PhySusPgEnable;
+
+/** Offset 0x02CE - PCH USB OverCurrent mapping enable
+  1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
+  mapping allow for NOA usage of OC pins
+  $EN_DIS
+**/
+  UINT8                       PchUsbOverCurrentEnable;
+
+/** Offset 0x02CF - Espi Lgmr Memory Range decode
+  This option enables or disables espi lgmr
+  $EN_DIS
+**/
+  UINT8                       PchEspiLgmrEnable;
+
+/** Offset 0x02D0 - PCHHOT# pin
+  Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
+  $EN_DIS
+**/
+  UINT8                       PchHotEnable;
+
+/** Offset 0x02D1 - SATA LED
+  SATA LED indicating SATA controller activity. 0: disable, 1: enable
+  $EN_DIS
+**/
+  UINT8                       SataLedEnable;
+
+/** Offset 0x02D2 - VRAlert# Pin
+  When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling
+  to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable
+  $EN_DIS
+**/
+  UINT8                       PchPmVrAlert;
+
+/** Offset 0x02D3 - SLP_S0 VM Dynamic Control
+  SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable
+  $EN_DIS
+**/
+  UINT8                       PchPmSlpS0VmRuntimeControl;
+
+/** Offset 0x02D4 - SLP_S0 VM 0.70V Support
+  SLP_S0 Voltage Margining  0.70V Support Policy. 0: disable, 1: enable
+  $EN_DIS
+**/
+  UINT8                       PchPmSlpS0Vm070VSupport;
+
+/** Offset 0x02D5 - SLP_S0 VM 0.75V Support
+  SLP_S0 Voltage Margining  0.75V Support Policy. 0: disable, 1: enable
+  $EN_DIS
+**/
+  UINT8                       PchPmSlpS0Vm075VSupport;
+
+/** Offset 0x02D6 - PCH PCIe root port connection type
+  0: built-in device, 1:slot
+**/
+  UINT8                       PcieRpSlotImplemented[24];
+
+/** Offset 0x02EE - Usage type for ClkSrc
+  0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
+  (free running), 0xFF: not used
+**/
+  UINT8                       PcieClkSrcUsage[16];
+
+/** Offset 0x02FE - ClkReq-to-ClkSrc mapping
+  Number of ClkReq signal assigned to ClkSrc
+**/
+  UINT8                       PcieClkSrcClkReq[16];
+
+/** Offset 0x030E - PCIE RP Access Control Services Extended Capability
+  Enable/Disable PCIE RP Access Control Services Extended Capability
+**/
+  UINT8                       PcieRpAcsEnabled[24];
+
+/** Offset 0x0326 - PCIE RP Clock Power Management
+  Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
+  can still be controlled by L1 PM substates mechanism
+**/
+  UINT8                       PcieRpEnableCpm[24];
+
+/** Offset 0x033E - PCIE RP Detect Timeout Ms
+  The number of milliseconds within 0~65535 in reference code will wait for link to
+  exit Detect state for enabled ports before assuming there is no device and potentially
+  disabling the port.
+**/
+  UINT16                      PcieRpDetectTimeoutMs[24];
+
+/** Offset 0x036E - ModPHY SUS Power Domain Dynamic Gating
+  Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on
+  PCH-H. 0: disable, 1: enable
+  $EN_DIS
+**/
+  UINT8                       PmcModPhySusPgEnable;
+
+/** Offset 0x036F - SlpS0WithGbeSupport
+  Enable/Disable SLP_S0 with GBE Support. Default is 0 for PCH-LP, WHL V0 Stepping
+  CPU and 1 for PCH-H Series. 0: Disable, 1: Enable
+  $EN_DIS
+**/
+  UINT8                       SlpS0WithGbeSupport;
+
+/** Offset 0x0370 - Enable Power Optimizer
+  Enable DMI Power Optimizer on PCH side.
+  $EN_DIS
+**/
+  UINT8                       PchPwrOptEnable;
+
+/** Offset 0x0371 - PCH Flash Protection Ranges Write Enble
+  Write or erase is blocked by hardware.
+**/
+  UINT8                       PchWriteProtectionEnable[5];
+
+/** Offset 0x0376 - PCH Flash Protection Ranges Read Enble
+  Read is blocked by hardware.
+**/
+  UINT8                       PchReadProtectionEnable[5];
+
+/** Offset 0x037B
+**/
+  UINT8                       UnusedUpdSpace15[1];
+
+/** Offset 0x037C - PCH Protect Range Limit
+  Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
+  limit comparison.
+**/
+  UINT16                      PchProtectedRangeLimit[5];
+
+/** Offset 0x0386 - PCH Protect Range Base
+  Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
+**/
+  UINT16                      PchProtectedRangeBase[5];
+
+/** Offset 0x0390 - Enable Pme
+  Enable Azalia wake-on-ring.
+  $EN_DIS
+**/
+  UINT8                       PchHdaPme;
+
+/** Offset 0x0391 - VC Type
+  Virtual Channel Type Select: 0: VC0, 1: VC1.
+  0: VC0, 1: VC1
+**/
+  UINT8                       PchHdaVcType;
+
+/** Offset 0x0392 - HD Audio Link Frequency
+  HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.
+  0: 6MHz, 1: 12MHz, 2: 24MHz
+**/
+  UINT8                       PchHdaLinkFrequency;
+
+/** Offset 0x0393 - iDisp-Link Frequency
+  iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
+  4: 96MHz, 3: 48MHz
+**/
+  UINT8                       PchHdaIDispLinkFrequency;
+
+/** Offset 0x0394 - iDisp-Link T-mode
+  iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T.
+  0: 2T, 1: 1T
+**/
+  UINT8                       PchHdaIDispLinkTmode;
+
+/** Offset 0x0395 - Universal Audio Architecture compliance for DSP enabled system
+  0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
+  driver or SST driver supported).
+  $EN_DIS
+**/
+  UINT8                       PchHdaDspUaaCompliance;
+
+/** Offset 0x0396 - iDisplay Audio Codec disconnection
+  0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
+  $EN_DIS
+**/
+  UINT8                       PchHdaIDispCodecDisconnect;
+
+/** Offset 0x0397 - USB LFPS Filter selection
+  For each byte bits 2:0 are for p, bits 4:6 are for n. 0h:1.6ns, 1h:2.4ns, 2h:3.2ns,
+  3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns.
+**/
+  UINT8                       PchUsbHsioFilterSel[10];
+
+/** Offset 0x03A1 - Enable PCH Io Apic Entry 24-119
+  0: Disable; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PchIoApicEntry24_119;
+
+/** Offset 0x03A2 - PCH Io Apic ID
+  This member determines IOAPIC ID. Default is 0x02.
+**/
+  UINT8                       PchIoApicId;
+
+/** Offset 0x03A3 - Enable PCH ISH SPI GPIO pins assigned
+  0: Disable; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PchIshSpiGpioAssign;
+
+/** Offset 0x03A4 - Enable PCH ISH UART0 GPIO pins assigned
+  0: Disable; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PchIshUart0GpioAssign;
+
+/** Offset 0x03A5 - Enable PCH ISH UART1 GPIO pins assigned
+  0: Disable; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PchIshUart1GpioAssign;
+
+/** Offset 0x03A6 - Enable PCH ISH I2C0 GPIO pins assigned
+  0: Disable; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PchIshI2c0GpioAssign;
+
+/** Offset 0x03A7 - Enable PCH ISH I2C1 GPIO pins assigned
+  0: Disable; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PchIshI2c1GpioAssign;
+
+/** Offset 0x03A8 - Enable PCH ISH I2C2 GPIO pins assigned
+  0: Disable; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PchIshI2c2GpioAssign;
+
+/** Offset 0x03A9 - Enable PCH ISH GP_0 GPIO pin assigned
+  0: Disable; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PchIshGp0GpioAssign;
+
+/** Offset 0x03AA - Enable PCH ISH GP_1 GPIO pin assigned
+  0: Disable; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PchIshGp1GpioAssign;
+
+/** Offset 0x03AB - Enable PCH ISH GP_2 GPIO pin assigned
+  0: Disable; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PchIshGp2GpioAssign;
+
+/** Offset 0x03AC - Enable PCH ISH GP_3 GPIO pin assigned
+  0: Disable; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PchIshGp3GpioAssign;
+
+/** Offset 0x03AD - Enable PCH ISH GP_4 GPIO pin assigned
+  0: Disable; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PchIshGp4GpioAssign;
+
+/** Offset 0x03AE - Enable PCH ISH GP_5 GPIO pin assigned
+  0: Disable; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PchIshGp5GpioAssign;
+
+/** Offset 0x03AF - Enable PCH ISH GP_6 GPIO pin assigned
+  0: Disable; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PchIshGp6GpioAssign;
+
+/** Offset 0x03B0 - Enable PCH ISH GP_7 GPIO pin assigned
+  0: Disable; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PchIshGp7GpioAssign;
+
+/** Offset 0x03B1 - PCH ISH PDT Unlock Msg
+  0: False; 1: True.
+  $EN_DIS
+**/
+  UINT8                       PchIshPdtUnlock;
+
+/** Offset 0x03B2 - Enable PCH Lan LTR capabilty of PCH internal LAN
+  0: Disable; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PchLanLtrEnable;
+
+/** Offset 0x03B3 - Enable LOCKDOWN BIOS LOCK
+  Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
+  protection.
+  $EN_DIS
+**/
+  UINT8                       PchLockDownBiosLock;
+
+/** Offset 0x03B4 - PCH Compatibility Revision ID
+  This member describes whether or not the CRID feature of PCH should be enabled.
+  $EN_DIS
+**/
+  UINT8                       PchCrid;
+
+/** Offset 0x03B5 - RTC CMOS MEMORY LOCK
+  Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
+  and and lower 128-byte bank of RTC RAM.
+  $EN_DIS
+**/
+  UINT8                       PchLockDownRtcMemoryLock;
+
+/** Offset 0x03B6 - Enable PCIE RP HotPlug
+  Indicate whether the root port is hot plug available.
+**/
+  UINT8                       PcieRpHotPlug[24];
+
+/** Offset 0x03CE - Enable PCIE RP Pm Sci
+  Indicate whether the root port power manager SCI is enabled.
+**/
+  UINT8                       PcieRpPmSci[24];
+
+/** Offset 0x03E6 - Enable PCIE RP Ext Sync
+  Indicate whether the extended synch is enabled.
+**/
+  UINT8                       PcieRpExtSync[24];
+
+/** Offset 0x03FE - Enable PCIE RP Transmitter Half Swing
+  Indicate whether the Transmitter Half Swing is enabled.
+**/
+  UINT8                       PcieRpTransmitterHalfSwing[24];
+
+/** Offset 0x0416 - Enable PCIE RP Clk Req Detect
+  Probe CLKREQ# signal before enabling CLKREQ# based power management.
+**/
+  UINT8                       PcieRpClkReqDetect[24];
+
+/** Offset 0x042E - PCIE RP Advanced Error Report
+  Indicate whether the Advanced Error Reporting is enabled.
+**/
+  UINT8                       PcieRpAdvancedErrorReporting[24];
+
+/** Offset 0x0446 - PCIE RP Unsupported Request Report
+  Indicate whether the Unsupported Request Report is enabled.
+**/
+  UINT8                       PcieRpUnsupportedRequestReport[24];
+
+/** Offset 0x045E - PCIE RP Fatal Error Report
+  Indicate whether the Fatal Error Report is enabled.
+**/
+  UINT8                       PcieRpFatalErrorReport[24];
+
+/** Offset 0x0476 - PCIE RP No Fatal Error Report
+  Indicate whether the No Fatal Error Report is enabled.
+**/
+  UINT8                       PcieRpNoFatalErrorReport[24];
+
+/** Offset 0x048E - PCIE RP Correctable Error Report
+  Indicate whether the Correctable Error Report is enabled.
+**/
+  UINT8                       PcieRpCorrectableErrorReport[24];
+
+/** Offset 0x04A6 - PCIE RP System Error On Fatal Error
+  Indicate whether the System Error on Fatal Error is enabled.
+**/
+  UINT8                       PcieRpSystemErrorOnFatalError[24];
+
+/** Offset 0x04BE - PCIE RP System Error On Non Fatal Error
+  Indicate whether the System Error on Non Fatal Error is enabled.
+**/
+  UINT8                       PcieRpSystemErrorOnNonFatalError[24];
+
+/** Offset 0x04D6 - PCIE RP System Error On Correctable Error
+  Indicate whether the System Error on Correctable Error is enabled.
+**/
+  UINT8                       PcieRpSystemErrorOnCorrectableError[24];
+
+/** Offset 0x04EE - PCIE RP Max Payload
+  Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
+**/
+  UINT8                       PcieRpMaxPayload[24];
+
+/** Offset 0x0506 - PCH USB3 RX HSIO Tuning parameters
+  Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for
+  controlling the input offset
+**/
+  UINT8                       PchUsbHsioRxTuningParameters[10];
+
+/** Offset 0x0510 - PCH USB3 HSIO Rx Tuning Enable
+  Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable,
+  1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable
+**/
+  UINT8                       PchUsbHsioRxTuningEnable[10];
+
+/** Offset 0x051A - PCIE RP Pcie Speed
+  Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
+  PCH_PCIE_SPEED).
+**/
+  UINT8                       PcieRpPcieSpeed[24];
+
+/** Offset 0x0532 - PCIE RP Gen3 Equalization Phase Method
+  PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization;
+  1: hardware equalization; 4: Fixed Coeficients.
+**/
+  UINT8                       PcieRpGen3EqPh3Method[24];
+
+/** Offset 0x054A - PCIE RP Physical Slot Number
+  Indicates the slot number for the root port. Default is the value as root port index.
+**/
+  UINT8                       PcieRpPhysicalSlotNumber[24];
+
+/** Offset 0x0562 - PCIE RP Completion Timeout
+  The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default.
+**/
+  UINT8                       PcieRpCompletionTimeout[24];
+
+/** Offset 0x057A - PCIE RP Aspm
+  The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
+  PchPcieAspmAutoConfig.
+**/
+  UINT8                       PcieRpAspm[24];
+
+/** Offset 0x0592 - PCIE RP L1 Substates
+  The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
+  Default is PchPcieL1SubstatesL1_1_2.
+**/
+  UINT8                       PcieRpL1Substates[24];
+
+/** Offset 0x05AA - PCIE RP Ltr Enable
+  Latency Tolerance Reporting Mechanism.
+**/
+  UINT8                       PcieRpLtrEnable[24];
+
+/** Offset 0x05C2 - PCIE RP Ltr Config Lock
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PcieRpLtrConfigLock[24];
+
+/** Offset 0x05DA - PCIE Eq Ph3 Lane Param Cm
+  PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1.
+**/
+  UINT8                       PcieEqPh3LaneParamCm[24];
+
+/** Offset 0x05F2 - PCIE Eq Ph3 Lane Param Cp
+  PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1.
+**/
+  UINT8                       PcieEqPh3LaneParamCp[24];
+
+/** Offset 0x060A - PCIE Sw Eq CoeffList Cm
+  PCH_PCIE_EQ_PARAM. Coefficient C-1. The values depend on PcieNumOfCoefficients,
+  the default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered.
+**/
+  UINT8                       PcieSwEqCoeffListCm[5];
+
+/** Offset 0x060F - PCIE Sw Eq CoeffList Cp
+  PCH_PCIE_EQ_PARAM. Coefficient C+1.The values depend on PcieNumOfCoefficients, the
+  default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered.
+**/
+  UINT8                       PcieSwEqCoeffListCp[5];
+
+/** Offset 0x0614 - PCIE Disable RootPort Clock Gating
+  Describes whether the PCI Express Clock Gating for each root port is enabled by
+  platform modules. 0: Disable; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PcieDisableRootPortClockGating;
+
+/** Offset 0x0615 - PCIE Enable Peer Memory Write
+  This member describes whether Peer Memory Writes are enabled on the platform.
+  $EN_DIS
+**/
+  UINT8                       PcieEnablePeerMemoryWrite;
+
+/** Offset 0x0616 - PCIE Compliance Test Mode
+  Compliance Test Mode shall be enabled when using Compliance Load Board.
+  $EN_DIS
+**/
+  UINT8                       PcieComplianceTestMode;
+
+/** Offset 0x0617 - PCIE Rp Function Swap
+  Allows BIOS to use root port function number swapping when root port of function
+  0 is disabled.
+  $EN_DIS
+**/
+  UINT8                       PcieRpFunctionSwap;
+
+/** Offset 0x0618 - Teton Glacier Cycle Router
+  Specify to which cycle router Teton Glacier is connected, it is valid only when
+  Teton Glacier support is enabled. Default is 0 for CNP-H system and 1 for CNP-LP system
+**/
+  UINT8                       TetonGlacierCR;
+
+/** Offset 0x0619 - PCH Pm PME_B0_S5_DIS
+  When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
+  $EN_DIS
+**/
+  UINT8                       PchPmPmeB0S5Dis;
+
+/** Offset 0x061A - PCIE IMR
+  Enables Isolated Memory Region for PCIe.
+  $EN_DIS
+**/
+  UINT8                       PcieRpImrEnabled;
+
+/** Offset 0x061B - PCIE IMR port number
+  Selects PCIE root port number for IMR feature.
+**/
+  UINT8                       PcieRpImrSelection;
+
+/** Offset 0x061C - Teton Glacier Detection and Configuration Mode
+  Enables support for Teton Glacier hybrid storage device. 0: Disabled; 1: Dynamic
+  Configuration. Default is 0: Disabled
+  0: Disabled, 1: Dynamic Configuration
+**/
+  UINT8                       TetonGlacierMode;
+
+/** Offset 0x061D - PCH Pm Wol Enable Override
+  Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
+  $EN_DIS
+**/
+  UINT8                       PchPmWolEnableOverride;
+
+/** Offset 0x061E - PCH Pm Pcie Wake From DeepSx
+  Determine if enable PCIe to wake from deep Sx.
+  $EN_DIS
+**/
+  UINT8                       PchPmPcieWakeFromDeepSx;
+
+/** Offset 0x061F - PCH Pm WoW lan Enable
+  Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
+  $EN_DIS
+**/
+  UINT8                       PchPmWoWlanEnable;
+
+/** Offset 0x0620 - PCH Pm WoW lan DeepSx Enable
+  Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the
+  PWRM_CFG3 register.
+  $EN_DIS
+**/
+  UINT8                       PchPmWoWlanDeepSxEnable;
+
+/** Offset 0x0621 - PCH Pm Lan Wake From DeepSx
+  Determine if enable LAN to wake from deep Sx.
+  $EN_DIS
+**/
+  UINT8                       PchPmLanWakeFromDeepSx;
+
+/** Offset 0x0622 - PCH Pm Deep Sx Pol
+  Deep Sx Policy.
+  $EN_DIS
+**/
+  UINT8                       PchPmDeepSxPol;
+
+/** Offset 0x0623 - PCH Pm Slp S3 Min Assert
+  SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
+**/
+  UINT8                       PchPmSlpS3MinAssert;
+
+/** Offset 0x0624 - PCH Pm Slp S4 Min Assert
+  SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.
+**/
+  UINT8                       PchPmSlpS4MinAssert;
+
+/** Offset 0x0625 - PCH Pm Slp Sus Min Assert
+  SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
+**/
+  UINT8                       PchPmSlpSusMinAssert;
+
+/** Offset 0x0626 - PCH Pm Slp A Min Assert
+  SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
+**/
+  UINT8                       PchPmSlpAMinAssert;
+
+/** Offset 0x0627 - SLP_S0# Override
+  Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled'
+  will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion
+  when debug is enabled. \n
+  Note: This BIOS option should keep 'Auto', other options are intended for advanced
+  configuration only.
+  0:Disabled, 1:Enabled, 2:Auto
+**/
+  UINT8                       SlpS0Override;
+
+/** Offset 0x0628 - S0ix Override Settings
+  Select 'Auto', it will be auto-configured according to probe type. 'No Change' will
+  keep PMC default settings. Or select the desired debug probe type for S0ix Override
+  settings.\n
+  Reminder: DCI OOB (aka BSSB) uses CCA probe.\n
+  Note: This BIOS option should keep 'Auto', other options are intended for advanced
+  configuration only.
+  0:No Change, 1:DCI OOB, 2:USB2 DbC, 3:Auto
+**/
+  UINT8                       SlpS0DisQForDebug;
+
+/** Offset 0x0629 - USB Overcurrent Override for DbC
+  This option overrides USB Over Current enablement state that USB OC will be disabled
+  after enabling this option. Enable when DbC is used to avoid signaling conflicts.
+  $EN_DIS
+**/
+  UINT8                       PchEnableDbcObs;
+
+/** Offset 0x062A - PCH Legacy IO Low Latency Enable
+  Set to enable low latency of legacy IO. <b>0: Disable</b>, 1: Enable
+  $EN_DIS
+**/
+  UINT8                       PchLegacyIoLowLatency;
+
+/** Offset 0x062B - PCH Pm Lpc Clock Run
+  This member describes whether or not the LPC ClockRun feature of PCH should be enabled.
+  Default value is Disabled
+  $EN_DIS
+**/
+  UINT8                       PchPmLpcClockRun;
+
+/** Offset 0x062C - PCH Pm Slp Strch Sus Up
+  Enable SLP_X Stretching After SUS Well Power Up.
+  $EN_DIS
+**/
+  UINT8                       PchPmSlpStrchSusUp;
+
+/** Offset 0x062D - PCH Pm Slp Lan Low Dc
+  Enable/Disable SLP_LAN# Low on DC Power.
+  $EN_DIS
+**/
+  UINT8                       PchPmSlpLanLowDc;
+
+/** Offset 0x062E - PCH Pm Pwr Btn Override Period
+  PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.
+**/
+  UINT8                       PchPmPwrBtnOverridePeriod;
+
+/** Offset 0x062F - PCH Pm Disable Dsx Ac Present Pulldown
+  When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
+  $EN_DIS
+**/
+  UINT8                       PchPmDisableDsxAcPresentPulldown;
+
+/** Offset 0x0630 - PCH Pm Disable Native Power Button
+  Power button native mode disable.
+  $EN_DIS
+**/
+  UINT8                       PchPmDisableNativePowerButton;
+
+/** Offset 0x0631 - PCH Pm Slp S0 Enable
+  Indicates whether SLP_S0# is to be asserted when PCH reaches idle state.
+  $EN_DIS
+**/
+  UINT8                       PchPmSlpS0Enable;
+
+/** Offset 0x0632 - PCH Pm ME_WAKE_STS
+  Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.
+  $EN_DIS
+**/
+  UINT8                       PchPmMeWakeSts;
+
+/** Offset 0x0633 - PCH Pm WOL_OVR_WK_STS
+  Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
+  $EN_DIS
+**/
+  UINT8                       PchPmWolOvrWkSts;
+
+/** Offset 0x0634 - PCH Pm Reset Power Cycle Duration
+  Could be customized in the unit of second. Please refer to EDS for all support settings.
+  0 is default, 1 is 1 second, 2 is 2 seconds, ...
+**/
+  UINT8                       PchPmPwrCycDur;
+
+/** Offset 0x0635 - PCH Pm Pcie Pll Ssc
+  Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
+  BIOS override.
+**/
+  UINT8                       PchPmPciePllSsc;
+
+/** Offset 0x0636 - PCH Sata Pwr Opt Enable
+  SATA Power Optimizer on PCH side.
+  $EN_DIS
+**/
+  UINT8                       SataPwrOptEnable;
+
+/** Offset 0x0637 - PCH Sata eSATA Speed Limit
+  When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
+  $EN_DIS
+**/
+  UINT8                       EsataSpeedLimit;
+
+/** Offset 0x0638 - PCH Sata Speed Limit
+  Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.
+**/
+  UINT8                       SataSpeedLimit;
+
+/** Offset 0x0639 - Enable SATA Port HotPlug
+  Enable SATA Port HotPlug.
+**/
+  UINT8                       SataPortsHotPlug[8];
+
+/** Offset 0x0641 - Enable SATA Port Interlock Sw
+  Enable SATA Port Interlock Sw.
+**/
+  UINT8                       SataPortsInterlockSw[8];
+
+/** Offset 0x0649 - Enable SATA Port External
+  Enable SATA Port External.
+**/
+  UINT8                       SataPortsExternal[8];
+
+/** Offset 0x0651 - Enable SATA Port SpinUp
+  Enable the COMRESET initialization Sequence to the device.
+**/
+  UINT8                       SataPortsSpinUp[8];
+
+/** Offset 0x0659 - Enable SATA Port Solid State Drive
+  0: HDD; 1: SSD.
+**/
+  UINT8                       SataPortsSolidStateDrive[8];
+
+/** Offset 0x0661 - Enable SATA Port Enable Dito Config
+  Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
+**/
+  UINT8                       SataPortsEnableDitoConfig[8];
+
+/** Offset 0x0669 - Enable SATA Port DmVal
+  DITO multiplier. Default is 15.
+**/
+  UINT8                       SataPortsDmVal[8];
+
+/** Offset 0x0671
+**/
+  UINT8                       UnusedUpdSpace16[1];
+
+/** Offset 0x0672 - Enable SATA Port DmVal
+  DEVSLP Idle Timeout (DITO), Default is 625.
+**/
+  UINT16                      SataPortsDitoVal[8];
+
+/** Offset 0x0682 - Enable SATA Port ZpOdd
+  Support zero power ODD.
+**/
+  UINT8                       SataPortsZpOdd[8];
+
+/** Offset 0x068A - PCH Sata Rst Raid Device Id
+  Enable RAID Alternate ID.
+  0:Client, 1:Alternate, 2:Server
+**/
+  UINT8                       SataRstRaidDeviceId;
+
+/** Offset 0x068B - PCH Sata Rst Raid0
+  RAID0.
+  $EN_DIS
+**/
+  UINT8                       SataRstRaid0;
+
+/** Offset 0x068C - PCH Sata Rst Raid1
+  RAID1.
+  $EN_DIS
+**/
+  UINT8                       SataRstRaid1;
+
+/** Offset 0x068D - PCH Sata Rst Raid10
+  RAID10.
+  $EN_DIS
+**/
+  UINT8                       SataRstRaid10;
+
+/** Offset 0x068E - PCH Sata Rst Raid5
+  RAID5.
+  $EN_DIS
+**/
+  UINT8                       SataRstRaid5;
+
+/** Offset 0x068F - PCH Sata Rst Irrt
+  Intel Rapid Recovery Technology.
+  $EN_DIS
+**/
+  UINT8                       SataRstIrrt;
+
+/** Offset 0x0690 - PCH Sata Rst Orom Ui Banner
+  OROM UI and BANNER.
+  $EN_DIS
+**/
+  UINT8                       SataRstOromUiBanner;
+
+/** Offset 0x0691 - PCH Sata Rst Orom Ui Delay
+  00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY).
+**/
+  UINT8                       SataRstOromUiDelay;
+
+/** Offset 0x0692 - PCH Sata Rst Hdd Unlock
+  Indicates that the HDD password unlock in the OS is enabled.
+  $EN_DIS
+**/
+  UINT8                       SataRstHddUnlock;
+
+/** Offset 0x0693 - PCH Sata Rst Led Locate
+  Indicates that the LED/SGPIO hardware is attached and ping to locate feature is
+  enabled on the OS.
+  $EN_DIS
+**/
+  UINT8                       SataRstLedLocate;
+
+/** Offset 0x0694 - PCH Sata Rst Irrt Only
+  Allow only IRRT drives to span internal and external ports.
+  $EN_DIS
+**/
+  UINT8                       SataRstIrrtOnly;
+
+/** Offset 0x0695 - PCH Sata Rst Smart Storage
+  RST Smart Storage caching Bit.
+  $EN_DIS
+**/
+  UINT8                       SataRstSmartStorage;
+
+/** Offset 0x0696 - PCH Sata Rst Pcie Storage Remap enable
+  Enable Intel RST for PCIe Storage remapping.
+**/
+  UINT8                       SataRstPcieEnable[3];
+
+/** Offset 0x0699 - PCH Sata Rst Pcie Storage Port
+  Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).
+**/
+  UINT8                       SataRstPcieStoragePort[3];
+
+/** Offset 0x069C - PCH Sata Rst Pcie Device Reset Delay
+  PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
+**/
+  UINT8                       SataRstPcieDeviceResetDelay[3];
+
+/** Offset 0x069F - Enable eMMC HS400 Training
+  Deprecated.
+  $EN_DIS
+**/
+  UINT8                       PchScsEmmcHs400TuningRequired;
+
+/** Offset 0x06A0 - Set HS400 Tuning Data Valid
+  Deprecated
+  $EN_DIS
+**/
+  UINT8                       PchScsEmmcHs400DllDataValid;
+
+/** Offset 0x06A1 - Rx Strobe Delay Control
+  Deprecated
+**/
+  UINT8                       PchScsEmmcHs400RxStrobeDll1;
+
+/** Offset 0x06A2 - Tx Data Delay Control
+  Deprecated
+**/
+  UINT8                       PchScsEmmcHs400TxDataDll;
+
+/** Offset 0x06A3 - I/O Driver Strength
+  Deprecated
+  0:33 Ohm, 1:40 Ohm, 2:50 Ohm
+**/
+  UINT8                       PchScsEmmcHs400DriverStrength;
+
+/** Offset 0x06A4 - Enable Serial IRQ
+  Determines if enable Serial IRQ.
+  $EN_DIS
+**/
+  UINT8                       PchSirqEnable;
+
+/** Offset 0x06A5 - Serial IRQ Mode Select
+  Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode.
+  $EN_DIS
+**/
+  UINT8                       PchSirqMode;
+
+/** Offset 0x06A6 - Start Frame Pulse Width
+  Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk.
+  0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk
+**/
+  UINT8                       PchStartFramePulse;
+
+/** Offset 0x06A7 - PCH eSPI Link Configuration Lock (SBLCL)
+  Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI slaves
+  addresseses from range 0x0 - 0x7FF
+  $EN_DIS
+**/
+  UINT8                       PchEspiLockLinkConfiguration;
+
+/** Offset 0x06A8 - Thermal Device SMI Enable
+  This locks down SMI Enable on Alert Thermal Sensor Trip.
+  $EN_DIS
+**/
+  UINT8                       PchTsmicLock;
+
+/** Offset 0x06A9
+**/
+  UINT8                       UnusedUpdSpace17;
+
+/** Offset 0x06AA - Thermal Throttling Custimized T0Level Value
+  Custimized T0Level value.
+**/
+  UINT16                      PchT0Level;
+
+/** Offset 0x06AC - Thermal Throttling Custimized T1Level Value
+  Custimized T1Level value.
+**/
+  UINT16                      PchT1Level;
+
+/** Offset 0x06AE - Thermal Throttling Custimized T2Level Value
+  Custimized T2Level value.
+**/
+  UINT16                      PchT2Level;
+
+/** Offset 0x06B0 - Enable The Thermal Throttle
+  Enable the thermal throttle function.
+  $EN_DIS
+**/
+  UINT8                       PchTTEnable;
+
+/** Offset 0x06B1 - PMSync State 13
+  When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
+  at least T2 state.
+  $EN_DIS
+**/
+  UINT8                       PchTTState13Enable;
+
+/** Offset 0x06B2 - Thermal Throttle Lock
+  Thermal Throttle Lock.
+  $EN_DIS
+**/
+  UINT8                       PchTTLock;
+
+/** Offset 0x06B3 - Thermal Throttling Suggested Setting
+  Thermal Throttling Suggested Setting.
+  $EN_DIS
+**/
+  UINT8                       TTSuggestedSetting;
+
+/** Offset 0x06B4 - Enable PCH Cross Throttling
+  Enable/Disable PCH Cross Throttling
+  $EN_DIS
+**/
+  UINT8                       TTCrossThrottling;
+
+/** Offset 0x06B5 - DMI Thermal Sensor Autonomous Width Enable
+  DMI Thermal Sensor Autonomous Width Enable.
+  $EN_DIS
+**/
+  UINT8                       PchDmiTsawEn;
+
+/** Offset 0x06B6 - DMI Thermal Sensor Suggested Setting
+  DMT thermal sensor suggested representative values.
+  $EN_DIS
+**/
+  UINT8                       DmiSuggestedSetting;
+
+/** Offset 0x06B7 - Thermal Sensor 0 Target Width
+  DMT thermal sensor suggested representative values.
+  0:x1, 1:x2, 2:x4, 3:x8, 4:x16
+**/
+  UINT8                       DmiTS0TW;
+
+/** Offset 0x06B8 - Thermal Sensor 1 Target Width
+  Thermal Sensor 1 Target Width.
+  0:x1, 1:x2, 2:x4, 3:x8, 4:x16
+**/
+  UINT8                       DmiTS1TW;
+
+/** Offset 0x06B9 - Thermal Sensor 2 Target Width
+  Thermal Sensor 2 Target Width.
+  0:x1, 1:x2, 2:x4, 3:x8, 4:x16
+**/
+  UINT8                       DmiTS2TW;
+
+/** Offset 0x06BA - Thermal Sensor 3 Target Width
+  Thermal Sensor 3 Target Width.
+  0:x1, 1:x2, 2:x4, 3:x8, 4:x16
+**/
+  UINT8                       DmiTS3TW;
+
+/** Offset 0x06BB - Port 0 T1 Multipler
+  Port 0 T1 Multipler.
+**/
+  UINT8                       SataP0T1M;
+
+/** Offset 0x06BC - Port 0 T2 Multipler
+  Port 0 T2 Multipler.
+**/
+  UINT8                       SataP0T2M;
+
+/** Offset 0x06BD - Port 0 T3 Multipler
+  Port 0 T3 Multipler.
+**/
+  UINT8                       SataP0T3M;
+
+/** Offset 0x06BE - Port 0 Tdispatch
+  Port 0 Tdispatch.
+**/
+  UINT8                       SataP0TDisp;
+
+/** Offset 0x06BF - Port 1 T1 Multipler
+  Port 1 T1 Multipler.
+**/
+  UINT8                       SataP1T1M;
+
+/** Offset 0x06C0 - Port 1 T2 Multipler
+  Port 1 T2 Multipler.
+**/
+  UINT8                       SataP1T2M;
+
+/** Offset 0x06C1 - Port 1 T3 Multipler
+  Port 1 T3 Multipler.
+**/
+  UINT8                       SataP1T3M;
+
+/** Offset 0x06C2 - Port 1 Tdispatch
+  Port 1 Tdispatch.
+**/
+  UINT8                       SataP1TDisp;
+
+/** Offset 0x06C3 - Port 0 Tinactive
+  Port 0 Tinactive.
+**/
+  UINT8                       SataP0Tinact;
+
+/** Offset 0x06C4 - Port 0 Alternate Fast Init Tdispatch
+  Port 0 Alternate Fast Init Tdispatch.
+  $EN_DIS
+**/
+  UINT8                       SataP0TDispFinit;
+
+/** Offset 0x06C5 - Port 1 Tinactive
+  Port 1 Tinactive.
+**/
+  UINT8                       SataP1Tinact;
+
+/** Offset 0x06C6 - Port 1 Alternate Fast Init Tdispatch
+  Port 1 Alternate Fast Init Tdispatch.
+  $EN_DIS
+**/
+  UINT8                       SataP1TDispFinit;
+
+/** Offset 0x06C7 - Sata Thermal Throttling Suggested Setting
+  Sata Thermal Throttling Suggested Setting.
+  $EN_DIS
+**/
+  UINT8                       SataThermalSuggestedSetting;
+
+/** Offset 0x06C8 - Enable Memory Thermal Throttling
+  Enable Memory Thermal Throttling.
+  $EN_DIS
+**/
+  UINT8                       PchMemoryThrottlingEnable;
+
+/** Offset 0x06C9 - Memory Thermal Throttling
+  Enable Memory Thermal Throttling.
+**/
+  UINT8                       PchMemoryPmsyncEnable[2];
+
+/** Offset 0x06CB - Enable Memory Thermal Throttling
+  Enable Memory Thermal Throttling.
+**/
+  UINT8                       PchMemoryC0TransmitEnable[2];
+
+/** Offset 0x06CD - Enable Memory Thermal Throttling
+  Enable Memory Thermal Throttling.
+**/
+  UINT8                       PchMemoryPinSelection[2];
+
+/** Offset 0x06CF
+**/
+  UINT8                       UnusedUpdSpace18;
+
+/** Offset 0x06D0 - Thermal Device Temperature
+  Decides the temperature.
+**/
+  UINT16                      PchTemperatureHotLevel;
+
+/** Offset 0x06D2 - Enable xHCI Compliance Mode
+  Compliance Mode can be enabled for testing through this option but this is disabled
+  by default.
+  $EN_DIS
+**/
+  UINT8                       PchEnableComplianceMode;
+
+/** Offset 0x06D3 - USB2 Port Over Current Pin
+  Describe the specific over current pin number of USB 2.0 Port N.
+**/
+  UINT8                       Usb2OverCurrentPin[16];
+
+/** Offset 0x06E3 - USB3 Port Over Current Pin
+  Describe the specific over current pin number of USB 3.0 Port N.
+**/
+  UINT8                       Usb3OverCurrentPin[10];
+
+/** Offset 0x06ED - Enable 8254 Static Clock Gating
+  Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
+  might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
+  boot legacy OS using 8254 timer. Also enable this while S0ix is enabled.
+  $EN_DIS
+**/
+  UINT8                       Enable8254ClockGating;
+
+/** Offset 0x06EE - PCH Sata Rst Optane Memory
+  Optane Memory
+  $EN_DIS
+**/
+  UINT8                       SataRstOptaneMemory;
+
+/** Offset 0x06EF - PCH Sata Rst CPU Attached Storage
+  CPU Attached Storage
+  $EN_DIS
+**/
+  UINT8                       SataRstCpuAttachedStorage;
+
+/** Offset 0x06F0 - Enable 8254 Static Clock Gating On S3
+  This is only applicable when Enable8254ClockGating is disabled. FSP will do the
+  8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
+  avoids the SMI requirement for the programming.
+  $EN_DIS
+**/
+  UINT8                       Enable8254ClockGatingOnS3;
+
+/** Offset 0x06F1
+**/
+  UINT8                       UnusedUpdSpace19[3];
+
+/** Offset 0x06F4 - Pch PCIE device override table pointer
+  The PCIe device table is being used to override PCIe device ASPM settings. This
+  is a pointer points to a 32bit address. And it's only used in PostMem phase. Please
+  refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId
+  must be 0.
+**/
+  UINT32                      PchPcieDeviceOverrideTablePtr;
+
+/** Offset 0x06F8 - Enable TCO timer.
+  When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have
+  huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer
+  emulation must be enabled, and WDAT table must not be exposed to the OS.
+  $EN_DIS
+**/
+  UINT8                       EnableTcoTimer;
+
+/** Offset 0x06F9 - Enable PS_ON.
+  PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
+  target that will be required by the California Energy Commission (CEC). When FALSE,
+  PS_ON is to be disabled.
+  $EN_DIS
+**/
+  UINT8                       PsOnEnable;
+
+/** Offset 0x06FA - Pmc Cpu C10 Gate Pin Enable
+  Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO
+  and VccSTG rails instead of SLP_S0# pin.
+  $EN_DIS
+**/
+  UINT8                       PmcCpuC10GatePinEnable;
+
+/** Offset 0x06FB - Pch Dmi Aspm Ctrl
+  ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
+  0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto
+**/
+  UINT8                       PchDmiAspmCtrl;
+
+/** Offset 0x06FC - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
+  Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each
+  value in array can be between 0-1. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxRate3UniqTranEnable[10];
+
+/** Offset 0x0706 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
+  USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], <b>Default
+  = 4Ch</b>. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxRate3UniqTran[10];
+
+/** Offset 0x0710 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
+  Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each
+  value in array can be between 0-1. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxRate2UniqTranEnable[10];
+
+/** Offset 0x071A - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
+  USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8],
+  <b>Default = 4Ch</b>. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxRate2UniqTran[10];
+
+/** Offset 0x0724 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
+  Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each
+  value in array can be between 0-1. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxRate1UniqTranEnable[10];
+
+/** Offset 0x072E - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
+  USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16],
+  <b>Default = 4Ch</b>. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxRate1UniqTran[10];
+
+/** Offset 0x0738 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
+  Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each
+  value in array can be between 0-1. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxRate0UniqTranEnable[10];
+
+/** Offset 0x0742 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
+  USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24],
+  <b>Default = 4Ch</b>. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxRate0UniqTran[10];
+
+/** Offset 0x074C - Number of Coefficients to be used
+  The number of coefficients to be used for equalization, default value is 3
+**/
+  UINT8                       PcieNumOfCoefficients;
+
+/** Offset 0x074D - GPIO RCOMP Community Clock Gating
+  0 = Disable dynamic RCOMP clock local clock gating, 1 = Enable dynamic RCOMP clock
+  local clock gating, default value is 1
+  $EN_DIS
+**/
+  UINT8                       GpioPmRcompCommunityLocalClockGating;
+
+/** Offset 0x074E - Enable SD Card Write Protect Pin
+  Enable/disable SD Card Write Protect Pin.
+  $EN_DIS
+**/
+  UINT8                       ScsSdCardWpPinEnabled;
+
+/** Offset 0x074F - Set SATA DEVSLP GPIO Reset Config
+  Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset,
+  0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte
+  for each port, byte0 for port0, byte1 for port1, and so on.
+**/
+  UINT8                       SataPortsDevSlpResetConfig[8];
+
+/** Offset 0x0757 - Flash Configuration Lock Down
+  Enable/disable flash lock down. If platform decides to skip this programming, it
+  must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post.
+  $EN_DIS
+**/
+  UINT8                       SpiFlashCfgLockDown;
+
+/** Offset 0x0758 - Enable HD Audio Sndw Link IO Control
+  0:Disabled, 1:Enabled. Enables IO Control to Sndw link if it is Enabled
+**/
+  UINT8                       PchHdaSndwLinkIoControlEnabled[4];
+
+/** Offset 0x075C - ReservedPchPostMem
+  Reserved for Pch Post-Mem
+  $EN_DIS
+**/
+  UINT8                       ReservedPchPostMem[3];
+
+/** Offset 0x075F
+**/
+  UINT8                       UnusedUpdSpace20[1];
+
+/** Offset 0x0760 - BgpdtHash[4]
+  BgpdtHash values
+**/
+  UINT64                      BgpdtHash[4];
+
+/** Offset 0x0780 - BiosGuardAttr
+  BiosGuardAttr default values
+**/
+  UINT32                      BiosGuardAttr;
+
+/** Offset 0x0784
+**/
+  UINT8                       UnusedUpdSpace21[4];
+
+/** Offset 0x0788 - BiosGuardModulePtr
+  BiosGuardModulePtr default values
+**/
+  UINT64                      BiosGuardModulePtr;
+
+/** Offset 0x0790 - SendEcCmd
+  SendEcCmd function pointer. \n
+  @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE
+  EcCmdType, IN UINT8  EcCmd, IN UINT8  SendData, IN OUT UINT8  *ReceiveData); @endcode
+**/
+  UINT64                      SendEcCmd;
+
+/** Offset 0x0798 - EcCmdProvisionEav
+  Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC
+**/
+  UINT8                       EcCmdProvisionEav;
+
+/** Offset 0x0799 - EcCmdLock
+  EcCmdLock default values. Locks Ephemeral Authorization Value sent previously
+**/
+  UINT8                       EcCmdLock;
+
+/** Offset 0x079A
+**/
+  UINT8                       UnusedUpdSpace22[6];
+
+/** Offset 0x07A0 - SgxEpoch0
+  SgxEpoch0 default values
+**/
+  UINT64                      SgxEpoch0;
+
+/** Offset 0x07A8 - SgxEpoch1
+  SgxEpoch1 default values
+**/
+  UINT64                      SgxEpoch1;
+
+/** Offset 0x07B0 - SgxSinitNvsData
+  SgxSinitNvsData default values
+**/
+  UINT8                       SgxSinitNvsData;
+
+/** Offset 0x07B1 - Si Config CSM Flag.
+  Platform specific common policies that used by several silicon components. CSM status flag.
+  $EN_DIS
+**/
+  UINT8                       SiCsmFlag;
+
+/** Offset 0x07B2
+**/
+  UINT8                       UnusedUpdSpace23[2];
+
+/** Offset 0x07B4 - SVID SDID table Poniter.
+  The address of the table of SVID SDID to customize each SVID SDID entry.
+**/
+  UINT32                      SiSsidTablePtr;
+
+/** Offset 0x07B8 - Number of ssid table.
+  SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr.
+**/
+  UINT16                      SiNumberOfSsidTableEntry;
+
+/** Offset 0x07BA - SATA RST Interrupt Mode
+  Allowes to choose which interrupts will be implemented by SATA controller in RAID mode.
+  0:Msix, 1:Msi, 2:Legacy
+**/
+  UINT8                       SataRstInterrupt;
+
+/** Offset 0x07BB - ME Unconfig on RTC clear
+  0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>.
+  2: Cmos is clear, status unkonwn. 3: Reserved
+  0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos
+  is clear, 3: Reserved
+**/
+  UINT8                       MeUnconfigOnRtcClear;
+
+/** Offset 0x07BC
+**/
+  UINT8                       UnusedUpdSpace24[3];
+
+/** Offset 0x07BF
+**/
+  UINT8                       ReservedFspsUpd[1];
+} FSP_S_CONFIG;
+
+/** Fsp S Test Configuration
+**/
+typedef struct {
+
+/** Offset 0x07C0
+**/
+  UINT32                      Signature;
+
+/** Offset 0x07C4 - Enable/Disable Device 7
+  Enable: Device  7 enabled, Disable (Default): Device 7 disabled
+  $EN_DIS
+**/
+  UINT8                       ChapDeviceEnable;
+
+/** Offset 0x07C5 - Skip PAM register lock
+  Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
+  PAM registers will be locked by RC
+  $EN_DIS
+**/
+  UINT8                       SkipPamLock;
+
+/** Offset 0x07C6 - EDRAM Test Mode
+  Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
+  PAM registers will be locked by RC
+  0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode
+**/
+  UINT8                       EdramTestMode;
+
+/** Offset 0x07C7 - DMI Extended Sync Control
+  Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended
+  Sync Control
+  $EN_DIS
+**/
+  UINT8                       DmiExtSync;
+
+/** Offset 0x07C8 - DMI IOT Control
+  Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control
+  $EN_DIS
+**/
+  UINT8                       DmiIot;
+
+/** Offset 0x07C9 - PEG Max Payload size per root port
+  0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B
+  0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B
+**/
+  UINT8                       PegMaxPayload[4];
+
+/** Offset 0x07CD - Enable/Disable IGFX RenderStandby
+  Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
+  $EN_DIS
+**/
+  UINT8                       RenderStandby;
+
+/** Offset 0x07CE - Enable/Disable IGFX PmSupport
+  Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
+  $EN_DIS
+**/
+  UINT8                       PmSupport;
+
+/** Offset 0x07CF - Enable/Disable CdynmaxClamp
+  Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp
+  $EN_DIS
+**/
+  UINT8                       CdynmaxClampEnable;
+
+/** Offset 0x07D0 - Disable VT-d
+  0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
+  $EN_DIS
+**/
+  UINT8                       VtdDisableDeprecated;
+
+/** Offset 0x07D1 - GT Frequency Limit
+  0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
+  7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
+  650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
+  0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
+  0x18: 1200 Mhz
+  0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
+  7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
+  650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
+  0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
+  0x18: 1200 Mhz
+**/
+  UINT8                       GtFreqMax;
+
+/** Offset 0x07D2 - Disable Turbo GT
+   0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency
+  $EN_DIS
+**/
+  UINT8                       DisableTurboGt;
+
+/** Offset 0x07D3 - SaPostMemTestRsvd
+  Reserved for SA Post-Mem Test
+  $EN_DIS
+**/
+  UINT8                       SaPostMemTestRsvd[11];
+
+/** Offset 0x07DE - 1-Core Ratio Limit
+  1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core
+  Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit,
+  4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit,
+  8-Core Ratio Limit. Range is 0 to 255
+**/
+  UINT8                       OneCoreRatioLimit;
+
+/** Offset 0x07DF - 2-Core Ratio Limit
+  2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core
+  Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
+**/
+  UINT8                       TwoCoreRatioLimit;
+
+/** Offset 0x07E0 - 3-Core Ratio Limit
+  3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core
+  Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
+**/
+  UINT8                       ThreeCoreRatioLimit;
+
+/** Offset 0x07E1 - 4-Core Ratio Limit
+  4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core
+  Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
+**/
+  UINT8                       FourCoreRatioLimit;
+
+/** Offset 0x07E2 - Enable or Disable HWP
+  Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
+  2-3:Reserved
+  $EN_DIS
+**/
+  UINT8                       Hwp;
+
+/** Offset 0x07E3 - Hardware Duty Cycle Control
+  Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved
+  $EN_DIS
+**/
+  UINT8                       HdcControl;
+
+/** Offset 0x07E4 - Package Long duration turbo mode time
+  Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds.
+  Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40
+  , 48 , 56 , 64 , 80 , 96 , 112 , 128
+**/
+  UINT8                       PowerLimit1Time;
+
+/** Offset 0x07E5 - Short Duration Turbo Mode
+  Enable or Disable short duration Turbo Mode. </b>0 : Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       PowerLimit2;
+
+/** Offset 0x07E6 - Turbo settings Lock
+  Lock all Turbo settings Enable/Disable; <b>0: Disable , </b> 1: Enable
+  $EN_DIS
+**/
+  UINT8                       TurboPowerLimitLock;
+
+/** Offset 0x07E7 - Package PL3 time window
+  Package PL3 time window range for this policy from 0 to 64ms
+**/
+  UINT8                       PowerLimit3Time;
+
+/** Offset 0x07E8 - Package PL3 Duty Cycle
+  Package PL3 Duty Cycle; Valid Range is 0 to 100
+**/
+  UINT8                       PowerLimit3DutyCycle;
+
+/** Offset 0x07E9 - Package PL3 Lock
+  Package PL3 Lock Enable/Disable; <b>0: Disable ; <b> 1: Enable
+  $EN_DIS
+**/
+  UINT8                       PowerLimit3Lock;
+
+/** Offset 0x07EA - Package PL4 Lock
+  Package PL4 Lock Enable/Disable; <b>0: Disable ; <b>1: Enable
+  $EN_DIS
+**/
+  UINT8                       PowerLimit4Lock;
+
+/** Offset 0x07EB - TCC Activation Offset
+  TCC Activation Offset. Offset from factory set TCC activation temperature at which
+  the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
+  Temperature, in volts.For Y SKU, the recommended default for this policy is  <b>15</b>,
+  For all other SKUs the recommended default are <b>0</b>
+**/
+  UINT8                       TccActivationOffset;
+
+/** Offset 0x07EC - Tcc Offset Clamp Enable/Disable
+  Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle
+  below P1.For Y SKU, the recommended default for this policy is <b>1: Enabled</b>,
+  For all other SKUs the recommended default are  <b>0: Disabled</b>.
+  $EN_DIS
+**/
+  UINT8                       TccOffsetClamp;
+
+/** Offset 0x07ED - Tcc Offset Lock
+  Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
+  target; <b>0: Disabled</b>; 1: Enabled.
+  $EN_DIS
+**/
+  UINT8                       TccOffsetLock;
+
+/** Offset 0x07EE - Custom Ratio State Entries
+  The number of custom ratio state entries, ranges from 0 to 40 for a valid custom
+  ratio table.Sets the number of custom P-states. At least 2 states must be present
+**/
+  UINT8                       NumberOfEntries;
+
+/** Offset 0x07EF - Custom Short term Power Limit time window
+  Short term Power Limit time window value for custom CTDP level 1. Valid Range 0
+  to 128, 0 = AUTO
+**/
+  UINT8                       Custom1PowerLimit1Time;
+
+/** Offset 0x07F0 - Custom Turbo Activation Ratio
+  Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255
+**/
+  UINT8                       Custom1TurboActivationRatio;
+
+/** Offset 0x07F1 - Custom Config Tdp Control
+  Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
+**/
+  UINT8                       Custom1ConfigTdpControl;
+
+/** Offset 0x07F2 - Custom Short term Power Limit time window
+  Short term Power Limit time window value for custom CTDP level 2. Valid Range 0
+  to 128, 0 = AUTO
+**/
+  UINT8                       Custom2PowerLimit1Time;
+
+/** Offset 0x07F3 - Custom Turbo Activation Ratio
+  Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255
+**/
+  UINT8                       Custom2TurboActivationRatio;
+
+/** Offset 0x07F4 - Custom Config Tdp Control
+  Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
+**/
+  UINT8                       Custom2ConfigTdpControl;
+
+/** Offset 0x07F5 - Custom Short term Power Limit time window
+  Short term Power Limit time window value for custom CTDP level 3. Valid Range 0
+  to 128, 0 = AUTO
+**/
+  UINT8                       Custom3PowerLimit1Time;
+
+/** Offset 0x07F6 - Custom Turbo Activation Ratio
+  Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255
+**/
+  UINT8                       Custom3TurboActivationRatio;
+
+/** Offset 0x07F7 - Custom Config Tdp Control
+  Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
+**/
+  UINT8                       Custom3ConfigTdpControl;
+
+/** Offset 0x07F8 - ConfigTdp mode settings Lock
+  Lock the ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1: Enable
+  $EN_DIS
+**/
+  UINT8                       ConfigTdpLock;
+
+/** Offset 0x07F9 - Load Configurable TDP SSDT
+  Configure whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       ConfigTdpBios;
+
+/** Offset 0x07FA - PL1 Enable value
+  PL1 Enable value to limit average platform power. <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PsysPowerLimit1;
+
+/** Offset 0x07FB - PL1 timewindow
+  PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds)
+  1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
+**/
+  UINT8                       PsysPowerLimit1Time;
+
+/** Offset 0x07FC - PL2 Enable Value
+  PL2 Enable activates the PL2 value to limit average platform power.<b>0: Disable</b>;
+  1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PsysPowerLimit2;
+
+/** Offset 0x07FD - Enable or Disable MLC Streamer Prefetcher
+  Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
+  $EN_DIS
+**/
+  UINT8                       MlcStreamerPrefetcher;
+
+/** Offset 0x07FE - Enable or Disable MLC Spatial Prefetcher
+  Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       MlcSpatialPrefetcher;
+
+/** Offset 0x07FF - Enable or Disable Monitor /MWAIT instructions
+  Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>.
+  $EN_DIS
+**/
+  UINT8                       MonitorMwaitEnable;
+
+/** Offset 0x0800 - Enable or Disable initialization of machine check registers
+  Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
+  $EN_DIS
+**/
+  UINT8                       MachineCheckEnable;
+
+/** Offset 0x0801 - Deprecated DO NOT USE Enable or Disable processor debug features
+  @deprecated Enable or Disable processor debug features; <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       DebugInterfaceEnable;
+
+/** Offset 0x0802 - Lock or Unlock debug interface features
+  Lock or Unlock debug interface features; 0: Disable; <b>1: Enable</b>.
+  $EN_DIS
+**/
+  UINT8                       DebugInterfaceLockEnable;
+
+/** Offset 0x0803 - AP Idle Manner of waiting for SIPI
+  AP Idle Manner of waiting for SIPI; 1: HALT loop; <b>2: MWAIT loop</b>; 3: RUN loop.
+  1: HALT loop, 2: MWAIT loop, 3: RUN loop
+**/
+  UINT8                       ApIdleManner;
+
+/** Offset 0x0804 - Control on Processor Trace output scheme
+  Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
+  0: Single Range Output, 1: ToPA Output
+**/
+  UINT8                       ProcessorTraceOutputScheme;
+
+/** Offset 0x0805 - Enable or Disable Processor Trace feature
+  Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       ProcessorTraceEnable;
+
+/** Offset 0x0806
+**/
+  UINT8                       UnusedUpdSpace25[2];
+
+/** Offset 0x0808 - Base of memory region allocated for Processor Trace
+  Base address of memory region allocated for Processor Trace. Processor Trace requires
+  2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>
+**/
+  UINT64                      ProcessorTraceMemBase;
+
+/** Offset 0x0810 - Memory region allocation for Processor Trace
+  Length in bytes of memory region allocated for Processor Trace. Processor Trace
+  requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>
+**/
+  UINT32                      ProcessorTraceMemLength;
+
+/** Offset 0x0814 - Enable or Disable Voltage Optimization feature
+  Enable or Disable Voltage Optimization feature 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       VoltageOptimization;
+
+/** Offset 0x0815 - Enable or Disable Intel SpeedStep Technology
+  Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       Eist;
+
+/** Offset 0x0816 - Enable or Disable Energy Efficient P-state
+  Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable;
+  <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       EnergyEfficientPState;
+
+/** Offset 0x0817 - Enable or Disable Energy Efficient Turbo
+  Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable;
+  1: Enable, <b>2: Auto / Silicon default</b>
+  0: Disable, 1: Enable, 2: Auto
+**/
+  UINT8                       EnergyEfficientTurbo;
+
+/** Offset 0x0818 - Enable or Disable T states
+  Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       TStates;
+
+/** Offset 0x0819 - Enable or Disable Bi-Directional PROCHOT#
+  Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       BiProcHot;
+
+/** Offset 0x081A - Enable or Disable PROCHOT# signal being driven externally
+  Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.
+  $EN_DIS
+**/
+  UINT8                       DisableProcHotOut;
+
+/** Offset 0x081B - Enable or Disable PROCHOT# Response
+  Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       ProcHotResponse;
+
+/** Offset 0x081C - Enable or Disable VR Thermal Alert
+  Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       DisableVrThermalAlert;
+
+/** Offset 0x081D - Enable or Disable Thermal Reporting
+  Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
+  $EN_DIS
+**/
+  UINT8                       AutoThermalReporting;
+
+/** Offset 0x081E - Enable or Disable Thermal Monitor
+  Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       ThermalMonitor;
+
+/** Offset 0x081F - Enable or Disable CPU power states (C-states)
+  Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       Cx;
+
+/** Offset 0x0820 - Configure C-State Configuration Lock
+  Configure C-State Configuration Lock; 0: Disable; <b>1: Enable</b>.
+  $EN_DIS
+**/
+  UINT8                       PmgCstCfgCtrlLock;
+
+/** Offset 0x0821 - Enable or Disable Enhanced C-states
+  Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       C1e;
+
+/** Offset 0x0822 - Enable or Disable Package Cstate Demotion
+  Enable or Disable Package Cstate Demotion. <b>0: Disable</b>; 1: Enable
+  $EN_DIS
+**/
+  UINT8                       PkgCStateDemotion;
+
+/** Offset 0x0823 - Enable or Disable Package Cstate UnDemotion
+  Enable or Disable Package Cstate UnDemotion. <b>0: Disable</b>; 1: Enable
+  $EN_DIS
+**/
+  UINT8                       PkgCStateUnDemotion;
+
+/** Offset 0x0824 - Enable or Disable CState-Pre wake
+  Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       CStatePreWake;
+
+/** Offset 0x0825 - Enable or Disable TimedMwait Support.
+  Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
+  $EN_DIS
+**/
+  UINT8                       TimedMwait;
+
+/** Offset 0x0826 - Enable or Disable IO to MWAIT redirection
+  Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       CstCfgCtrIoMwaitRedirection;
+
+/** Offset 0x0827 - Set the Max Pkg Cstate
+  Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep
+  C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S ,
+  6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto
+**/
+  UINT8                       PkgCStateLimit;
+
+/** Offset 0x0828 - TimeUnit for C-State Latency Control0
+  TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+  , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+  UINT8                       CstateLatencyControl0TimeUnit;
+
+/** Offset 0x0829 - TimeUnit for C-State Latency Control1
+  TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+  , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+  UINT8                       CstateLatencyControl1TimeUnit;
+
+/** Offset 0x082A - TimeUnit for C-State Latency Control2
+  TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+  , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+  UINT8                       CstateLatencyControl2TimeUnit;
+
+/** Offset 0x082B - TimeUnit for C-State Latency Control3
+  TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+  , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+  UINT8                       CstateLatencyControl3TimeUnit;
+
+/** Offset 0x082C - TimeUnit for C-State Latency Control4
+  Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+  UINT8                       CstateLatencyControl4TimeUnit;
+
+/** Offset 0x082D - TimeUnit for C-State Latency Control5
+  TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+  , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+  UINT8                       CstateLatencyControl5TimeUnit;
+
+/** Offset 0x082E - Interrupt Redirection Mode Select
+  Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4:
+  PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change.
+**/
+  UINT8                       PpmIrmSetting;
+
+/** Offset 0x082F - Lock prochot configuration
+  Lock prochot configuration Enable/Disable; <b>0: Disable</b>; 1: Enable
+  $EN_DIS
+**/
+  UINT8                       ProcHotLock;
+
+/** Offset 0x0830 - Configuration for boot TDP selection
+  Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP
+  Up;0xFF : Deactivate
+**/
+  UINT8                       ConfigTdpLevel;
+
+/** Offset 0x0831 - Race To Halt
+  Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
+  in order to enter pkg C-State faster to reduce overall power. (RTH is controlled
+  through MSR 1FC bit 20)Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       RaceToHalt;
+
+/** Offset 0x0832 - Max P-State Ratio
+  Max P-State Ratio, Valid Range 0 to 0x7F
+**/
+  UINT8                       MaxRatio;
+
+/** Offset 0x0833 - P-state ratios for custom P-state table
+  P-state ratios for custom P-state table. NumberOfEntries has valid range between
+  0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries]
+  are configurable. Valid Range of each entry is 0 to 0x7F
+**/
+  UINT8                       StateRatio[40];
+
+/** Offset 0x085B - P-state ratios for max 16 version of custom P-state table
+  P-state ratios for max 16 version of custom P-state table. This table is used for
+  OS versions limited to a max of 16 P-States. If the first entry of this table is
+  0, or if Number of Entries is 16 or less, then this table will be ignored, and
+  up to the top 16 values of the StateRatio table will be used instead. Valid Range
+  of each entry is 0 to 0x7F
+**/
+  UINT8                       StateRatioMax16[16];
+
+/** Offset 0x086B
+**/
+  UINT8                       UnusedUpdSpace26;
+
+/** Offset 0x086C - Platform Power Pmax
+  PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.
+  Range 0-1024 Watts. Value of 800 = 100W
+**/
+  UINT16                      PsysPmax;
+
+/** Offset 0x086E - Interrupt Response Time Limit of C-State LatencyContol0
+  Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF
+**/
+  UINT16                      CstateLatencyControl0Irtl;
+
+/** Offset 0x0870 - Interrupt Response Time Limit of C-State LatencyContol1
+  Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF
+**/
+  UINT16                      CstateLatencyControl1Irtl;
+
+/** Offset 0x0872 - Interrupt Response Time Limit of C-State LatencyContol2
+  Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF
+**/
+  UINT16                      CstateLatencyControl2Irtl;
+
+/** Offset 0x0874 - Interrupt Response Time Limit of C-State LatencyContol3
+  Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF
+**/
+  UINT16                      CstateLatencyControl3Irtl;
+
+/** Offset 0x0876 - Interrupt Response Time Limit of C-State LatencyContol4
+  Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF
+**/
+  UINT16                      CstateLatencyControl4Irtl;
+
+/** Offset 0x0878 - Interrupt Response Time Limit of C-State LatencyContol5
+  Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF
+**/
+  UINT16                      CstateLatencyControl5Irtl;
+
+/** Offset 0x087A
+**/
+  UINT8                       UnusedUpdSpace27[2];
+
+/** Offset 0x087C - Package Long duration turbo mode power limit
+  Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+  Valid Range 0 to 4095875 in Step size of 125
+**/
+  UINT32                      PowerLimit1;
+
+/** Offset 0x0880 - Package Short duration turbo mode power limit
+  Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+  Range 0 to 4095875 in Step size of 125
+**/
+  UINT32                      PowerLimit2Power;
+
+/** Offset 0x0884 - Package PL3 power limit
+  Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+  Range 0 to 4095875 in Step size of 125
+**/
+  UINT32                      PowerLimit3;
+
+/** Offset 0x0888 - Package PL4 power limit
+  Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+  Range 0 to 1023875 in Step size of 125
+**/
+  UINT32                      PowerLimit4;
+
+/** Offset 0x088C - Tcc Offset Time Window for RATL
+  Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+  Range 0 to 1023875 in Step size of 125
+**/
+  UINT32                      TccOffsetTimeWindowForRatl;
+
+/** Offset 0x0890 - Short term Power Limit value for custom cTDP level 1
+  Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+  Range 0 to 4095875 in Step size of 125
+**/
+  UINT32                      Custom1PowerLimit1;
+
+/** Offset 0x0894 - Long term Power Limit value for custom cTDP level 1
+  Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+  Range 0 to 4095875 in Step size of 125
+**/
+  UINT32                      Custom1PowerLimit2;
+
+/** Offset 0x0898 - Short term Power Limit value for custom cTDP level 2
+  Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+  Range 0 to 4095875 in Step size of 125
+**/
+  UINT32                      Custom2PowerLimit1;
+
+/** Offset 0x089C - Long term Power Limit value for custom cTDP level 2
+  Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+  Range 0 to 4095875 in Step size of 125
+**/
+  UINT32                      Custom2PowerLimit2;
+
+/** Offset 0x08A0 - Short term Power Limit value for custom cTDP level 3
+  Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+  Range 0 to 4095875 in Step size of 125
+**/
+  UINT32                      Custom3PowerLimit1;
+
+/** Offset 0x08A4 - Long term Power Limit value for custom cTDP level 3
+  Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+  Range 0 to 4095875 in Step size of 125
+**/
+  UINT32                      Custom3PowerLimit2;
+
+/** Offset 0x08A8 - Platform PL1 power
+  Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
+  0 to 4095875 in Step size of 125
+**/
+  UINT32                      PsysPowerLimit1Power;
+
+/** Offset 0x08AC - Platform PL2 power
+  Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
+  0 to 4095875 in Step size of 125
+**/
+  UINT32                      PsysPowerLimit2Power;
+
+/** Offset 0x08B0 - Set Three Strike Counter Disable
+  False (default): Three Strike counter will be incremented and True: Prevents Three
+  Strike counter from incrementing; <b>0: False</b>; 1: True.
+  0: False, 1: True
+**/
+  UINT8                       ThreeStrikeCounterDisable;
+
+/** Offset 0x08B1 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
+  Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       HwpInterruptControl;
+
+/** Offset 0x08B2 - 5-Core Ratio Limit
+  5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core
+  Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
+  0x0:0xFF
+**/
+  UINT8                       FiveCoreRatioLimit;
+
+/** Offset 0x08B3 - 6-Core Ratio Limit
+  6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core
+  Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
+  0x0:0xFF
+**/
+  UINT8                       SixCoreRatioLimit;
+
+/** Offset 0x08B4 - 7-Core Ratio Limit
+  7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core
+  Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
+  0x0:0xFF
+**/
+  UINT8                       SevenCoreRatioLimit;
+
+/** Offset 0x08B5 - 8-Core Ratio Limit
+  8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core
+  Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
+  0x0:0xFF
+**/
+  UINT8                       EightCoreRatioLimit;
+
+/** Offset 0x08B6 - Intel Turbo Boost Max Technology 3.0
+  Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b>
+  $EN_DIS
+**/
+  UINT8                       EnableItbm;
+
+/** Offset 0x08B7 - Intel Turbo Boost Max Technology 3.0 Driver
+  @deprecated Intel Turbo Boost Max Technology 3.0 Driver <b>0: Disabled</b>; 1: Enabled
+  $EN_DIS
+**/
+  UINT8                       EnableItbmDriver;
+
+/** Offset 0x08B8 - Enable or Disable C1 Cstate Demotion
+  Enable or Disable C1 Cstate Demotion. Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       C1StateAutoDemotion;
+
+/** Offset 0x08B9 - Enable or Disable C1 Cstate UnDemotion
+  Enable or Disable C1 Cstate UnDemotion. Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       C1StateUnDemotion;
+
+/** Offset 0x08BA - CpuWakeUpTimer
+  Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased
+  to 180 seconds. 0: Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       CpuWakeUpTimer;
+
+/** Offset 0x08BB - Minimum Ring ratio limit override
+  Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
+  ratio limit
+**/
+  UINT8                       MinRingRatioLimit;
+
+/** Offset 0x08BC - Minimum Ring ratio limit override
+  Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
+  ratio limit
+**/
+  UINT8                       MaxRingRatioLimit;
+
+/** Offset 0x08BD - Enable or Disable C3 Cstate Demotion
+  Enable or Disable C3 Cstate Demotion. Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       C3StateAutoDemotion;
+
+/** Offset 0x08BE - Enable or Disable C3 Cstate UnDemotion
+  Enable or Disable C3 Cstate UnDemotion. Disable; <b>1: Enable</b>
+  $EN_DIS
+**/
+  UINT8                       C3StateUnDemotion;
+
+/** Offset 0x08BF - Ratio Limit Num Core 0
+  Ratio Limit Num Core0: This register defines the active core ranges for each frequency point
+**/
+  UINT8                       RatioLimitNumCore0;
+
+/** Offset 0x08C0 - Ratio Limit Num Core 1
+  Ratio Limit Num Core1: This register defines the active core ranges for each frequency point
+**/
+  UINT8                       RatioLimitNumCore1;
+
+/** Offset 0x08C1 - Ratio Limit Num Core 2
+  Ratio Limit Num Core2: This register defines the active core ranges for each frequency point
+**/
+  UINT8                       RatioLimitNumCore2;
+
+/** Offset 0x08C2 - Ratio Limit Core 3
+  Ratio Limit Num Core3: This register defines the active core ranges for each frequency point
+**/
+  UINT8                       RatioLimitNumCore3;
+
+/** Offset 0x08C3 - Ratio Limit Num Core 4
+  Ratio Limit Num Core4: This register defines the active core ranges for each frequency point
+**/
+  UINT8                       RatioLimitNumCore4;
+
+/** Offset 0x08C4 - Ratio Limit Num Core 5
+  Ratio Limit Num Core5: This register defines the active core ranges for each frequency point
+**/
+  UINT8                       RatioLimitNumCore5;
+
+/** Offset 0x08C5 - Ratio Limit Num Core 6
+  Ratio Limit Num Core6: This register defines the active core ranges for each frequency point
+**/
+  UINT8                       RatioLimitNumCore6;
+
+/** Offset 0x08C6 - Ratio Limit Num Core 7
+  Ratio Limit Num Core7: This register defines the active core ranges for each frequency point
+**/
+  UINT8                       RatioLimitNumCore7;
+
+/** Offset 0x08C7 - Dual Tau Boost
+  Enable, Disable Dual Tau Boost feature. This is only applicable for CMLS; <b>0:
+  Disable</b>; 1: Enable
+  $EN_DIS
+**/
+  UINT8                       DualTauBoost;
+
+/** Offset 0x08C8 - ITBMT 3.0 Runtime Periodic SMM timer
+  Periodic SMM Polling timer for ITBMT 3.0 <b>Default 4 - 8 Sec</b>. 0 = Diable periodic
+  SMM, and Valid values 1 - 16ms , 2 - 32ms , 3 - 64ms , 4 - 8 sec , 5 - 16 sec,
+  6 - 32 sec, 7 - 64 sec.
+**/
+  UINT8                       ItbmPeriodicSmmTimer;
+
+/** Offset 0x08C9 - ReservedCpuPostMemTest
+  Reserved for CPU Post-Mem Test
+  $EN_DIS
+**/
+  UINT8                       ReservedCpuPostMemTest[9];
+
+/** Offset 0x08D2 - SgxSinitDataFromTpm
+  SgxSinitDataFromTpm default values
+**/
+  UINT8                       SgxSinitDataFromTpm;
+
+/** Offset 0x08D3 - End of Post message
+  Test, Send End of Post message. Disable(0x0): Disable EOP message, Enable(0x1)(Default):
+  Enable EOP message
+  $EN_DIS
+**/
+  UINT8                       EndOfPostMessage;
+
+/** Offset 0x08D4 - D0I3 Setting for HECI Disable
+  Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all
+  HECI devices
+  $EN_DIS
+**/
+  UINT8                       DisableD0I3SettingForHeci;
+
+/** Offset 0x08D5
+**/
+  UINT8                       UnusedUpdSpace28;
+
+/** Offset 0x08D6 - HD Audio Reset Wait Timer
+  The delay timer after Azalia reset, the value is number of microseconds. Default is 600.
+**/
+  UINT16                      PchHdaResetWaitTimer;
+
+/** Offset 0x08D8 - Enable LOCKDOWN SMI
+  Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
+  $EN_DIS
+**/
+  UINT8                       PchLockDownGlobalSmi;
+
+/** Offset 0x08D9 - Enable LOCKDOWN BIOS Interface
+  Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
+  $EN_DIS
+**/
+  UINT8                       PchLockDownBiosInterface;
+
+/** Offset 0x08DA - Unlock all GPIO pads
+  Force all GPIO pads to be unlocked for debug purpose.
+  $EN_DIS
+**/
+  UINT8                       PchUnlockGpioPads;
+
+/** Offset 0x08DB - PCH Unlock SideBand access
+  The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
+  3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.
+  $EN_DIS
+**/
+  UINT8                       PchSbAccessUnlock;
+
+/** Offset 0x08DC - PCIE RP Ltr Max Snoop Latency
+  Latency Tolerance Reporting, Max Snoop Latency.
+**/
+  UINT16                      PcieRpLtrMaxSnoopLatency[24];
+
+/** Offset 0x090C - PCIE RP Ltr Max No Snoop Latency
+  Latency Tolerance Reporting, Max Non-Snoop Latency.
+**/
+  UINT16                      PcieRpLtrMaxNoSnoopLatency[24];
+
+/** Offset 0x093C - PCIE RP Snoop Latency Override Mode
+  Latency Tolerance Reporting, Snoop Latency Override Mode.
+**/
+  UINT8                       PcieRpSnoopLatencyOverrideMode[24];
+
+/** Offset 0x0954 - PCIE RP Snoop Latency Override Multiplier
+  Latency Tolerance Reporting, Snoop Latency Override Multiplier.
+**/
+  UINT8                       PcieRpSnoopLatencyOverrideMultiplier[24];
+
+/** Offset 0x096C - PCIE RP Snoop Latency Override Value
+  Latency Tolerance Reporting, Snoop Latency Override Value.
+**/
+  UINT16                      PcieRpSnoopLatencyOverrideValue[24];
+
+/** Offset 0x099C - PCIE RP Non Snoop Latency Override Mode
+  Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
+**/
+  UINT8                       PcieRpNonSnoopLatencyOverrideMode[24];
+
+/** Offset 0x09B4 - PCIE RP Non Snoop Latency Override Multiplier
+  Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
+**/
+  UINT8                       PcieRpNonSnoopLatencyOverrideMultiplier[24];
+
+/** Offset 0x09CC - PCIE RP Non Snoop Latency Override Value
+  Latency Tolerance Reporting, Non-Snoop Latency Override Value.
+**/
+  UINT16                      PcieRpNonSnoopLatencyOverrideValue[24];
+
+/** Offset 0x09FC - PCIE RP Slot Power Limit Scale
+  Specifies scale used for slot power limit value. Leave as 0 to set to default.
+**/
+  UINT8                       PcieRpSlotPowerLimitScale[24];
+
+/** Offset 0x0A14 - PCIE RP Slot Power Limit Value
+  Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
+**/
+  UINT16                      PcieRpSlotPowerLimitValue[24];
+
+/** Offset 0x0A44 - PCIE RP Upstream Port Transmiter Preset
+  Used during Gen3 Link Equalization. Used for all lanes.  Default is 5.
+**/
+  UINT8                       PcieRpUptp[24];
+
+/** Offset 0x0A5C - PCIE RP Downstream Port Transmiter Preset
+  Used during Gen3 Link Equalization. Used for all lanes.  Default is 7.
+**/
+  UINT8                       PcieRpDptp[24];
+
+/** Offset 0x0A74 - PCIE RP Enable Port8xh Decode
+  This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;
+  1: Enable.
+  $EN_DIS
+**/
+  UINT8                       PcieEnablePort8xhDecode;
+
+/** Offset 0x0A75 - PCIE Port8xh Decode Port Index
+  The Index of PCIe Port that is selected for Port8xh Decode (0 Based).
+**/
+  UINT8                       PchPciePort8xhDecodePortIndex;
+
+/** Offset 0x0A76 - PCH Energy Reporting
+  Disable/Enable PCH to CPU energy report feature.
+  $EN_DIS
+**/
+  UINT8                       PchPmDisableEnergyReport;
+
+/** Offset 0x0A77 - PCH Sata Test Mode
+  Allow entrance to the PCH SATA test modes.
+  $EN_DIS
+**/
+  UINT8                       SataTestMode;
+
+/** Offset 0x0A78 - PCH USB OverCurrent mapping lock enable
+  If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning
+  that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.
+  $EN_DIS
+**/
+  UINT8                       PchXhciOcLock;
+
+/** Offset 0x0A79 - ReservedPchPostMemTest
+  Reserved for Pch Post-Mem Test
+  $EN_DIS
+**/
+  UINT8                       ReservedPchPostMemTest[16];
+
+/** Offset 0x0A89 - Mctp Broadcast Cycle
+  Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       MctpBroadcastCycle;
+
+/** Offset 0x0A8A - Use DLL values from policy
+  Set if FSP should use HS400 DLL values from policy
+  $EN_DIS
+**/
+  UINT8                       EmmcUseCustomDlls;
+
+/** Offset 0x0A8B
+**/
+  UINT8                       UnusedUpdSpace29;
+
+/** Offset 0x0A8C - Emmc Tx CMD Delay control register value
+  Please see Tx CMD Delay Control register definition for help
+**/
+  UINT32                      EmmcTxCmdDelayRegValue;
+
+/** Offset 0x0A90 - Emmc Tx DATA Delay control 1 register value
+  Please see Tx DATA Delay control 1 register definition for help
+**/
+  UINT32                      EmmcTxDataDelay1RegValue;
+
+/** Offset 0x0A94 - Emmc Tx DATA Delay control 2 register value
+  Please see Tx DATA Delay control 2 register definition for help
+**/
+  UINT32                      EmmcTxDataDelay2RegValue;
+
+/** Offset 0x0A98 - Emmc Rx CMD + DATA Delay control 1 register value
+  Please see Rx CMD + DATA Delay control 1 register definition for help
+**/
+  UINT32                      EmmcRxCmdDataDelay1RegValue;
+
+/** Offset 0x0A9C - Emmc Rx CMD + DATA Delay control 2 register value
+  Please see Rx CMD + DATA Delay control 2 register definition for help
+**/
+  UINT32                      EmmcRxCmdDataDelay2RegValue;
+
+/** Offset 0x0AA0 - Emmc Rx Strobe Delay control register value
+  Please see Rx Strobe Delay control register definition for help
+**/
+  UINT32                      EmmcRxStrobeDelayRegValue;
+
+/** Offset 0x0AA4 - Use tuned DLL values from policy
+  Set if FSP should use HS400 DLL values from policy
+  $EN_DIS
+**/
+  UINT8                       SdCardUseCustomDlls;
+
+/** Offset 0x0AA5
+**/
+  UINT8                       UnusedUpdSpace30[3];
+
+/** Offset 0x0AA8 - SdCard Tx CMD Delay control register value
+  Please see Tx CMD Delay Control register definition for help
+**/
+  UINT32                      SdCardTxCmdDelayRegValue;
+
+/** Offset 0x0AAC - SdCard Tx DATA Delay control 1 register value
+  Please see Tx DATA Delay control 1 register definition for help
+**/
+  UINT32                      SdCardTxDataDelay1RegValue;
+
+/** Offset 0x0AB0 - SdCard Tx DATA Delay control 2 register value
+  Please see Tx DATA Delay control 2 register definition for help
+**/
+  UINT32                      SdCardTxDataDelay2RegValue;
+
+/** Offset 0x0AB4 - SdCard Rx CMD + DATA Delay control 1 register value
+  Please see Rx CMD + DATA Delay control 1 register definition for help
+**/
+  UINT32                      SdCardRxCmdDataDelay1RegValue;
+
+/** Offset 0x0AB8 - SdCard Rx CMD + DATA Delay control 2 register value
+  Please see Rx CMD + DATA Delay control 2 register definition for help
+**/
+  UINT32                      SdCardRxCmdDataDelay2RegValue;
+
+/** Offset 0x0ABC - Enforce Enhanced Debug Mode
+  Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable
+  $EN_DIS
+**/
+  UINT8                       EnforceEDebugMode;
+
+/** Offset 0x0ABD
+**/
+  UINT8                       UnusedUpdSpace31[3];
+
+/** Offset 0x0AC0 - LogoPixelHeight Address
+  Address of LogoPixelHeight
+**/
+  UINT32                      LogoPixelHeight;
+
+/** Offset 0x0AC4 - LogoPixelWidth Address
+  Address of LogoPixelWidth
+**/
+  UINT32                      LogoPixelWidth;
+
+/** Offset 0x0AC8
+**/
+  UINT8                       UnusedUpdSpace32[4];
+
+/** Offset 0x0ACC
+**/
+  UINT8                       ReservedFspsTestUpd[4];
+} FSP_S_TEST_CONFIG;
+
+/** Fsp S UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+  FSP_UPD_HEADER              FspUpdHeader;
+
+/** Offset 0x0020
+**/
+  FSP_S_CONFIG                FspsConfig;
+
+/** Offset 0x07C0
+**/
+  FSP_S_TEST_CONFIG           FspsTestConfig;
+
+/** Offset 0x0AD0
+**/
+  UINT8                       UnusedUpdSpace33[6];
+
+/** Offset 0x0AD6
+**/
+  UINT16                      UpdTerminator;
+} FSPS_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/CometLakeFspBinPkg/CometLake2/Include/FsptUpd.h b/CometLakeFspBinPkg/CometLake2/Include/FsptUpd.h
new file mode 100644
index 0000000..9617105
--- /dev/null
+++ b/CometLakeFspBinPkg/CometLake2/Include/FsptUpd.h
@@ -0,0 +1,180 @@
+/** @file
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPTUPD_H__
+#define __FSPTUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+/** Fsp T Core UPD
+**/
+typedef struct {
+
+/** Offset 0x0020
+**/
+  UINT32                      MicrocodeRegionBase;
+
+/** Offset 0x0024
+**/
+  UINT32                      MicrocodeRegionSize;
+
+/** Offset 0x0028
+**/
+  UINT32                      CodeRegionBase;
+
+/** Offset 0x002C
+**/
+  UINT32                      CodeRegionSize;
+
+/** Offset 0x0030
+**/
+  UINT8                       Reserved[16];
+} FSPT_CORE_UPD;
+
+/** Fsp T Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - PcdSerialIoUartDebugEnable
+  Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
+  0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
+**/
+  UINT8                       PcdSerialIoUartDebugEnable;
+
+/** Offset 0x0041 - PcdSerialIoUartNumber - FSPT
+  Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
+  Core interface, it cannot be used for debug purpose.
+  0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
+**/
+  UINT8                       PcdSerialIoUartNumber;
+
+/** Offset 0x0042 - PcdSerialIoUartMode - FSPT
+  Select SerialIo Uart Controller mode
+  0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
+  4:SerialIoUartSkipInit
+**/
+  UINT8                       PcdSerialIoUartMode;
+
+/** Offset 0x0043
+**/
+  UINT8                       UnusedUpdSpace0;
+
+/** Offset 0x0044 - PcdSerialIoUartBaudRate - FSPT
+  Set default BaudRate Supported from 0 - default to 6000000
+**/
+  UINT32                      PcdSerialIoUartBaudRate;
+
+/** Offset 0x0048 - Pci Express Base Address
+  Base address to be programmed for Pci Express
+**/
+  UINT64                      PcdPciExpressBaseAddress;
+
+/** Offset 0x0050 - Pci Express Region Length
+  Region Length to be programmed for Pci Express
+**/
+  UINT32                      PcdPciExpressRegionLength;
+
+/** Offset 0x0054 - PcdSerialIoUartParity - FSPT
+  Set default Parity.
+  0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
+**/
+  UINT8                       PcdSerialIoUartParity;
+
+/** Offset 0x0055 - PcdSerialIoUartDataBits - FSPT
+  Set default word length. 0: Default, 5,6,7,8
+**/
+  UINT8                       PcdSerialIoUartDataBits;
+
+/** Offset 0x0056 - PcdSerialIoUartStopBits - FSPT
+  Set default stop bits.
+  0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
+**/
+  UINT8                       PcdSerialIoUartStopBits;
+
+/** Offset 0x0057 - PcdSerialIoUartAutoFlow - FSPT
+  Enables UART hardware flow control, CTS and RTS lines.
+  0: Disable, 1:Enable
+**/
+  UINT8                       PcdSerialIoUartAutoFlow;
+
+/** Offset 0x0058 - PcdSerialIoUartPinMux - FSPT
+  Applies only to UART0 muxed with CNVI <b> 0 = GPIO C8 to C11 </b> 1 = GPIO F5 -
+  F7 (PCH LP) J5 - J7 (PCH H)
+  0: GPIO C8 to C11, 1: GPIO F5 - F7 (PCH LP) J5 - J7 (PCH H)
+**/
+  UINT8                       PcdSerialIoUartPinMux;
+
+/** Offset 0x0059 - PcdLpcUartDebugEnable
+  Enable to initialize LPC Uart device in FSP.
+  0:Disable, 1:Enable
+**/
+  UINT8                       PcdLpcUartDebugEnable;
+
+/** Offset 0x005A - Debug Interfaces
+  Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
+  BIT2 - Not used.
+**/
+  UINT8                       PcdDebugInterfaceFlags;
+
+/** Offset 0x005B - PcdSerialDebugLevel
+  Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+  Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+  Info & Verbose.
+  0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+  Error Warnings and Info, 5:Load Error Warnings Info and Verbose
+**/
+  UINT8                       PcdSerialDebugLevel;
+
+/** Offset 0x005C - ISA Serial Base selection
+  Select ISA Serial Base address. Default is 0x3F8.
+  0:0x3F8, 1:0x2F8
+**/
+  UINT8                       PcdIsaSerialUartBase;
+
+/** Offset 0x005D
+**/
+  UINT8                       UnusedUpdSpace1[7];
+
+/** Offset 0x0064
+**/
+  UINT8                       ReservedFsptUpd1[20];
+} FSP_T_CONFIG;
+
+/** Fsp T UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+  FSP_UPD_HEADER              FspUpdHeader;
+
+/** Offset 0x0020
+**/
+  FSPT_CORE_UPD               FsptCoreUpd;
+
+/** Offset 0x0040
+**/
+  FSP_T_CONFIG                FsptConfig;
+
+/** Offset 0x0078
+**/
+  UINT8                       UnusedUpdSpace2[6];
+
+/** Offset 0x007E
+**/
+  UINT16                      UpdTerminator;
+} FSPT_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/CometLakeFspBinPkg/CometLake2/Include/GpioConfig.h b/CometLakeFspBinPkg/CometLake2/Include/GpioConfig.h
new file mode 100644
index 0000000..eed3cb2
--- /dev/null
+++ b/CometLakeFspBinPkg/CometLake2/Include/GpioConfig.h
@@ -0,0 +1,329 @@
+/** @file
+  Header file for GpioConfig structure used by GPIO library.
+
+@copyright
+  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@par Specification Reference:
+**/
+
+#ifndef _GPIO_CONFIG_H_
+#define _GPIO_CONFIG_H_
+
+#pragma pack(push, 1)
+
+///
+/// For any GpioPad usage in code use GPIO_PAD type
+///
+typedef UINT32 GPIO_PAD;
+
+
+///
+/// For any GpioGroup usage in code use GPIO_GROUP type
+///
+typedef UINT32 GPIO_GROUP;
+
+/**
+  GPIO configuration structure used for pin programming.
+  Structure contains fields that can be used to configure pad.
+**/
+typedef struct {
+  /**
+  Pad Mode
+  Pad can be set as GPIO or one of its native functions.
+  When in native mode setting Direction (except Inversion), OutputState,
+  InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary.
+  Refer to definition of GPIO_PAD_MODE.
+  Refer to EDS for each native mode according to the pad.
+  **/
+  UINT32 PadMode            : 5;
+  /**
+  Host Software Pad Ownership
+  Set pad to ACPI mode or GPIO Driver Mode.
+  Refer to definition of GPIO_HOSTSW_OWN.
+  **/
+  UINT32 HostSoftPadOwn     : 2;
+  /**
+  GPIO Direction
+  Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.
+  Refer to definition of GPIO_DIRECTION for supported settings.
+  **/
+  UINT32 Direction           : 6;
+  /**
+  Output State
+  Set Pad output value.
+  Refer to definition of GPIO_OUTPUT_STATE for supported settings.
+  This setting takes place when output is enabled.
+  **/
+  UINT32 OutputState         : 2;
+  /**
+  GPIO Interrupt Configuration
+  Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
+  This setting is applicable only if GPIO is in GpioMode with input enabled.
+  Refer to definition of GPIO_INT_CONFIG for supported settings.
+  **/
+  UINT32 InterruptConfig     : 9;
+  /**
+  GPIO Power Configuration.
+  This setting controls Pad Reset Configuration.
+  Refer to definition of GPIO_RESET_CONFIG for supported settings.
+  **/
+  UINT32 PowerConfig        : 8;
+  /**
+  GPIO Electrical Configuration
+  This setting controls pads termination.
+  Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
+  **/
+  UINT32 ElectricalConfig   : 9;
+  /**
+  GPIO Lock Configuration
+  This setting controls pads lock.
+  Refer to definition of GPIO_LOCK_CONFIG for supported settings.
+  **/
+  UINT32 LockConfig         : 4;
+  /**
+  Additional GPIO configuration
+  Refer to definition of GPIO_OTHER_CONFIG for supported settings.
+  **/
+  UINT32 OtherSettings     :  9;
+  UINT32 RsvdBits          : 10;    ///< Reserved bits for future extension
+} GPIO_CONFIG;
+
+
+typedef enum {
+  GpioHardwareDefault        = 0x0    ///< Leave setting unmodified
+} GPIO_HARDWARE_DEFAULT;
+
+/**
+  GPIO Pad Mode
+  Refer to GPIO documentation on native functions available for certain pad.
+  If GPIO is set to one of NativeX modes then following settings are not applicable
+  and can be skipped:
+  - Interrupt related settings
+  - Host Software Ownership
+  - Output/Input enabling/disabling
+  - Output lock
+**/
+typedef enum {
+  GpioPadModeGpio     = 0x1,
+  GpioPadModeNative1  = 0x3,
+  GpioPadModeNative2  = 0x5,
+  GpioPadModeNative3  = 0x7,
+  GpioPadModeNative4  = 0x9,
+  GpioPadModeNative5  = 0xB
+} GPIO_PAD_MODE;
+
+/**
+  Host Software Pad Ownership modes
+  This setting affects GPIO interrupt status registers. Depending on chosen ownership
+  some GPIO Interrupt status register get updated and other masked.
+  Please refer to EDS for HOSTSW_OWN register description.
+**/
+typedef enum {
+  GpioHostOwnDefault = 0x0,   ///< Leave ownership value unmodified
+  /**
+  Set HOST ownership to ACPI.
+  Use this setting if pad is not going to be used by GPIO OS driver.
+  If GPIO is configured to generate SCI/SMI/NMI then this setting must be
+  used for interrupts to work
+  **/
+  GpioHostOwnAcpi    = 0x1,
+  /**
+  Set HOST ownership to GPIO Driver mode.
+  Use this setting only if GPIO pad should be controlled by GPIO OS Driver.
+  GPIO OS Driver will be able to control the pad if appropriate entry in
+  ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)
+  **/
+  GpioHostOwnGpio    = 0x3
+} GPIO_HOSTSW_OWN;
+
+///
+/// GPIO Direction
+///
+typedef enum {
+  GpioDirDefault         = 0x0,                ///< Leave pad direction setting unmodified
+  GpioDirInOut           = (0x1 | (0x1 << 3)), ///< Set pad for both output and input
+  GpioDirInInvOut        = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion
+  GpioDirIn              = (0x3 | (0x1 << 3)), ///< Set pad for input only
+  GpioDirInInv           = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
+  GpioDirOut             = 0x5,                ///< Set pad for output only
+  GpioDirNone            = 0x7                 ///< Disable both output and input
+} GPIO_DIRECTION;
+
+/**
+  GPIO Output State
+  This field is relevant only if output is enabled
+**/
+typedef enum {
+  GpioOutDefault         = 0x0,  ///< Leave output value unmodified
+  GpioOutLow             = 0x1,  ///< Set output to low
+  GpioOutHigh            = 0x3   ///< Set output to high
+} GPIO_OUTPUT_STATE;
+
+/**
+  GPIO interrupt configuration
+  This setting is applicable only if pad is in GPIO mode and has input enabled.
+  GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI)
+  and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in
+  EDS for details on this settings.
+  Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge
+  to describe an interrupt e.g. GpioIntApic | GpioIntLevel
+  If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad.
+  If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad.
+  Not all GPIO are capable of generating an SMI or NMI interrupt.
+  When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this
+  interrupt cannot be shared and its IRQn number is not configurable.
+  Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel)
+  If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor
+  exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge).
+  This type of GPIO Driver interrupt doesn't have any additional routing setting
+  required to be set by BIOS. Interrupt is handled by GPIO OS Driver.
+**/
+
+typedef enum {
+  GpioIntDefault           = 0x0,  ///< Leave value of interrupt routing unmodified
+  GpioIntDis               = 0x1,  ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
+  GpioIntNmi               = 0x3,  ///< Enable NMI interrupt only
+  GpioIntSmi               = 0x5,  ///< Enable SMI interrupt only
+  GpioIntSci               = 0x9,  ///< Enable SCI interrupt only
+  GpioIntApic              = 0x11, ///< Enable IOxAPIC interrupt only
+  GpioIntLevel       = (0x1 << 5), ///< Set interrupt as level triggered
+  GpioIntEdge        = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion)
+  GpioIntLvlEdgDis   = (0x5 << 5), ///< Disable interrupt trigger
+  GpioIntBothEdge    = (0x7 << 5)  ///< Set interrupt as both edge triggered
+} GPIO_INT_CONFIG;
+
+#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK  0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source
+#define B_GPIO_INT_CONFIG_INT_TYPE_MASK    0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type
+
+/**
+  GPIO Power Configuration
+  GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will
+  be used to reset certain GPIO settings.
+  Refer to EDS for settings that are controllable by PadRstCfg.
+**/
+typedef enum {
+  GpioResetDefault   = 0x00,        ///< Leave value of pad reset unmodified
+  /**
+  Resume Reset (RSMRST)
+    GPP: PadRstCfg = 00b = "Powergood"
+    GPD: PadRstCfg = 11b = "Resume Reset"
+  Pad setting will reset on:
+  - DeepSx transition
+  - G3
+  Pad settings will not reset on:
+  - S3/S4/S5 transition
+  - Warm/Cold/Global reset
+  **/
+  GpioResumeReset      = 0x01,
+  /**
+  Host Deep Reset
+    PadRstCfg = 01b = "Deep GPIO Reset"
+  Pad settings will reset on:
+  - Warm/Cold/Global reset
+  - DeepSx transition
+  - G3
+  Pad settings will not reset on:
+  - S3/S4/S5 transition
+  **/
+  GpioHostDeepReset    = 0x03,
+  /**
+  Platform Reset (PLTRST)
+    PadRstCfg = 10b = "GPIO Reset"
+  Pad settings will reset on:
+  - S3/S4/S5 transition
+  - Warm/Cold/Global reset
+  - DeepSx transition
+  - G3
+  **/
+  GpioPlatformReset    = 0x05,
+  /**
+  Deep Sleep Well Reset (DSW_PWROK)
+    GPP: not applicable
+    GPD: PadRstCfg = 00b = "Powergood"
+  Pad settings will reset on:
+  - G3
+  Pad settings will not reset on:
+  - S3/S4/S5 transition
+  - Warm/Cold/Global reset
+  - DeepSx transition
+  **/
+  GpioDswReset         = 0x07
+} GPIO_RESET_CONFIG;
+
+/**
+  GPIO Electrical Configuration
+  Configuration options for GPIO termination setting
+**/
+typedef enum {
+  GpioTermDefault          = 0x0,  ///< Leave termination setting unmodified
+  GpioTermNone             = 0x1,  ///< none
+  GpioTermWpd5K            = 0x5,  ///< 5kOhm weak pull-down
+  GpioTermWpd20K           = 0x9,  ///< 20kOhm weak pull-down
+  GpioTermWpu1K            = 0x13, ///< 1kOhm weak pull-up
+  GpioTermWpu2K            = 0x17, ///< 2kOhm weak pull-up
+  GpioTermWpu5K            = 0x15, ///< 5kOhm weak pull-up
+  GpioTermWpu20K           = 0x19, ///< 20kOhm weak pull-up
+  GpioTermWpu1K2K          = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
+  /**
+  Native function controls pads termination
+  This setting is applicable only to some native modes.
+  Please check EDS to determine which native functionality
+  can control pads termination
+  **/
+  GpioTermNative           = 0x1F
+} GPIO_ELECTRICAL_CONFIG;
+
+#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK    0x1F   ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value
+
+/**
+  GPIO LockConfiguration
+  Set GPIO configuration lock and output state lock.
+  GpioPadConfigUnlock/Lock and GpioOutputStateUnlock can be OR'ed.
+  By default GPIO pads will be locked unless GPIO lib is explicitly
+  informed that certain pad is to be left unlocked.
+  Lock settings reset is in Powergood domain. Care must be taken when using this setting
+  as fields it locks may be reset by a different signal and can be controlled
+  by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides
+  functions which allow to unlock a GPIO pad. If possible each GPIO lib function will try to unlock
+  an already locked pad upon request for reconfiguration
+**/
+typedef enum {
+  /**
+  Perform default action
+   - if pad is an GPO, lock configuration but leave output unlocked
+   - if pad is an GPI, lock everything
+   - if pad is in native, lock everything
+**/
+  GpioLockDefault       = 0x0,
+  GpioPadConfigUnlock   = 0x3,  ///< Leave Pad configuration unlocked
+  GpioPadConfigLock     = 0x1,  ///< Lock Pad configuration
+  GpioOutputStateUnlock = 0xC,  ///< Leave Pad output control unlocked
+  GpioPadUnlock         = 0xF,  ///< Leave both Pad configuration and output control unlocked
+  GpioPadLock           = 0x5   ///< Lock both Pad configuration and output control
+} GPIO_LOCK_CONFIG;
+
+#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK  0x3  ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock
+#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK    0xC  ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock
+
+/**
+  Other GPIO Configuration
+  GPIO_OTHER_CONFIG is used for less often settings and for future extensions
+  Supported settings:
+   - RX raw override to '1' - allows to override input value to '1'
+      This setting is applicable only if in input mode (both in GPIO and native usage).
+      The override takes place at the internal pad state directly from buffer and before the RXINV.
+**/
+typedef enum {
+  GpioRxRaw1Default           = 0x0,  ///< Use default input override value
+  GpioRxRaw1Dis               = 0x1,  ///< Don't override input
+  GpioRxRaw1En                = 0x3   ///< Override input to '1'
+} GPIO_OTHER_CONFIG;
+
+#define B_GPIO_OTHER_CONFIG_RXRAW_MASK           0x3   ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting
+
+#pragma pack(pop)
+
+#endif //_GPIO_CONFIG_H_
diff --git a/CometLakeFspBinPkg/CometLake2/Include/GpioSampleDef.h b/CometLakeFspBinPkg/CometLake2/Include/GpioSampleDef.h
new file mode 100644
index 0000000..9cfc7c7
--- /dev/null
+++ b/CometLakeFspBinPkg/CometLake2/Include/GpioSampleDef.h
@@ -0,0 +1,361 @@
+/** @file
+  Sample enum definitions for GPIO table.
+
+ @copyright
+  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@par Specification Reference:
+**/
+
+#ifndef __GPIOCONFIG_H__
+#define __GPIOCONFIG_H__
+#include <FsptUpd.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+/*
+  SKL LP GPIO pins
+  Use below for functions from PCH GPIO Lib which
+  require GpioPad as argument. Encoding used here
+  has all information required by library functions
+*/
+#define GPIO_SKL_LP_GPP_A0      0x02000000
+#define GPIO_SKL_LP_GPP_A1      0x02000001
+#define GPIO_SKL_LP_GPP_A2      0x02000002
+#define GPIO_SKL_LP_GPP_A3      0x02000003
+#define GPIO_SKL_LP_GPP_A4      0x02000004
+#define GPIO_SKL_LP_GPP_A5      0x02000005
+#define GPIO_SKL_LP_GPP_A6      0x02000006
+#define GPIO_SKL_LP_GPP_A7      0x02000007
+#define GPIO_SKL_LP_GPP_A8      0x02000008
+#define GPIO_SKL_LP_GPP_A9      0x02000009
+#define GPIO_SKL_LP_GPP_A10     0x0200000A
+#define GPIO_SKL_LP_GPP_A11     0x0200000B
+#define GPIO_SKL_LP_GPP_A12     0x0200000C
+#define GPIO_SKL_LP_GPP_A13     0x0200000D
+#define GPIO_SKL_LP_GPP_A14     0x0200000E
+#define GPIO_SKL_LP_GPP_A15     0x0200000F
+#define GPIO_SKL_LP_GPP_A16     0x02000010
+#define GPIO_SKL_LP_GPP_A17     0x02000011
+#define GPIO_SKL_LP_GPP_A18     0x02000012
+#define GPIO_SKL_LP_GPP_A19     0x02000013
+#define GPIO_SKL_LP_GPP_A20     0x02000014
+#define GPIO_SKL_LP_GPP_A21     0x02000015
+#define GPIO_SKL_LP_GPP_A22     0x02000016
+#define GPIO_SKL_LP_GPP_A23     0x02000017
+#define GPIO_SKL_LP_GPP_B0      0x02010000
+#define GPIO_SKL_LP_GPP_B1      0x02010001
+#define GPIO_SKL_LP_GPP_B2      0x02010002
+#define GPIO_SKL_LP_GPP_B3      0x02010003
+#define GPIO_SKL_LP_GPP_B4      0x02010004
+#define GPIO_SKL_LP_GPP_B5      0x02010005
+#define GPIO_SKL_LP_GPP_B6      0x02010006
+#define GPIO_SKL_LP_GPP_B7      0x02010007
+#define GPIO_SKL_LP_GPP_B8      0x02010008
+#define GPIO_SKL_LP_GPP_B9      0x02010009
+#define GPIO_SKL_LP_GPP_B10     0x0201000A
+#define GPIO_SKL_LP_GPP_B11     0x0201000B
+#define GPIO_SKL_LP_GPP_B12     0x0201000C
+#define GPIO_SKL_LP_GPP_B13     0x0201000D
+#define GPIO_SKL_LP_GPP_B14     0x0201000E
+#define GPIO_SKL_LP_GPP_B15     0x0201000F
+#define GPIO_SKL_LP_GPP_B16     0x02010010
+#define GPIO_SKL_LP_GPP_B17     0x02010011
+#define GPIO_SKL_LP_GPP_B18     0x02010012
+#define GPIO_SKL_LP_GPP_B19     0x02010013
+#define GPIO_SKL_LP_GPP_B20     0x02010014
+#define GPIO_SKL_LP_GPP_B21     0x02010015
+#define GPIO_SKL_LP_GPP_B22     0x02010016
+#define GPIO_SKL_LP_GPP_B23     0x02010017
+#define GPIO_SKL_LP_GPP_C0      0x02020000
+#define GPIO_SKL_LP_GPP_C1      0x02020001
+#define GPIO_SKL_LP_GPP_C2      0x02020002
+#define GPIO_SKL_LP_GPP_C3      0x02020003
+#define GPIO_SKL_LP_GPP_C4      0x02020004
+#define GPIO_SKL_LP_GPP_C5      0x02020005
+#define GPIO_SKL_LP_GPP_C6      0x02020006
+#define GPIO_SKL_LP_GPP_C7      0x02020007
+#define GPIO_SKL_LP_GPP_C8      0x02020008
+#define GPIO_SKL_LP_GPP_C9      0x02020009
+#define GPIO_SKL_LP_GPP_C10     0x0202000A
+#define GPIO_SKL_LP_GPP_C11     0x0202000B
+#define GPIO_SKL_LP_GPP_C12     0x0202000C
+#define GPIO_SKL_LP_GPP_C13     0x0202000D
+#define GPIO_SKL_LP_GPP_C14     0x0202000E
+#define GPIO_SKL_LP_GPP_C15     0x0202000F
+#define GPIO_SKL_LP_GPP_C16     0x02020010
+#define GPIO_SKL_LP_GPP_C17     0x02020011
+#define GPIO_SKL_LP_GPP_C18     0x02020012
+#define GPIO_SKL_LP_GPP_C19     0x02020013
+#define GPIO_SKL_LP_GPP_C20     0x02020014
+#define GPIO_SKL_LP_GPP_C21     0x02020015
+#define GPIO_SKL_LP_GPP_C22     0x02020016
+#define GPIO_SKL_LP_GPP_C23     0x02020017
+#define GPIO_SKL_LP_GPP_D0      0x02030000
+#define GPIO_SKL_LP_GPP_D1      0x02030001
+#define GPIO_SKL_LP_GPP_D2      0x02030002
+#define GPIO_SKL_LP_GPP_D3      0x02030003
+#define GPIO_SKL_LP_GPP_D4      0x02030004
+#define GPIO_SKL_LP_GPP_D5      0x02030005
+#define GPIO_SKL_LP_GPP_D6      0x02030006
+#define GPIO_SKL_LP_GPP_D7      0x02030007
+#define GPIO_SKL_LP_GPP_D8      0x02030008
+#define GPIO_SKL_LP_GPP_D9      0x02030009
+#define GPIO_SKL_LP_GPP_D10     0x0203000A
+#define GPIO_SKL_LP_GPP_D11     0x0203000B
+#define GPIO_SKL_LP_GPP_D12     0x0203000C
+#define GPIO_SKL_LP_GPP_D13     0x0203000D
+#define GPIO_SKL_LP_GPP_D14     0x0203000E
+#define GPIO_SKL_LP_GPP_D15     0x0203000F
+#define GPIO_SKL_LP_GPP_D16     0x02030010
+#define GPIO_SKL_LP_GPP_D17     0x02030011
+#define GPIO_SKL_LP_GPP_D18     0x02030012
+#define GPIO_SKL_LP_GPP_D19     0x02030013
+#define GPIO_SKL_LP_GPP_D20     0x02030014
+#define GPIO_SKL_LP_GPP_D21     0x02030015
+#define GPIO_SKL_LP_GPP_D22     0x02030016
+#define GPIO_SKL_LP_GPP_D23     0x02030017
+#define GPIO_SKL_LP_GPP_E0      0x02040000
+#define GPIO_SKL_LP_GPP_E1      0x02040001
+#define GPIO_SKL_LP_GPP_E2      0x02040002
+#define GPIO_SKL_LP_GPP_E3      0x02040003
+#define GPIO_SKL_LP_GPP_E4      0x02040004
+#define GPIO_SKL_LP_GPP_E5      0x02040005
+#define GPIO_SKL_LP_GPP_E6      0x02040006
+#define GPIO_SKL_LP_GPP_E7      0x02040007
+#define GPIO_SKL_LP_GPP_E8      0x02040008
+#define GPIO_SKL_LP_GPP_E9      0x02040009
+#define GPIO_SKL_LP_GPP_E10     0x0204000A
+#define GPIO_SKL_LP_GPP_E11     0x0204000B
+#define GPIO_SKL_LP_GPP_E12     0x0204000C
+#define GPIO_SKL_LP_GPP_E13     0x0204000D
+#define GPIO_SKL_LP_GPP_E14     0x0204000E
+#define GPIO_SKL_LP_GPP_E15     0x0204000F
+#define GPIO_SKL_LP_GPP_E16     0x02040010
+#define GPIO_SKL_LP_GPP_E17     0x02040011
+#define GPIO_SKL_LP_GPP_E18     0x02040012
+#define GPIO_SKL_LP_GPP_E19     0x02040013
+#define GPIO_SKL_LP_GPP_E20     0x02040014
+#define GPIO_SKL_LP_GPP_E21     0x02040015
+#define GPIO_SKL_LP_GPP_E22     0x02040016
+#define GPIO_SKL_LP_GPP_E23     0x02040017
+#define GPIO_SKL_LP_GPP_F0      0x02050000
+#define GPIO_SKL_LP_GPP_F1      0x02050001
+#define GPIO_SKL_LP_GPP_F2      0x02050002
+#define GPIO_SKL_LP_GPP_F3      0x02050003
+#define GPIO_SKL_LP_GPP_F4      0x02050004
+#define GPIO_SKL_LP_GPP_F5      0x02050005
+#define GPIO_SKL_LP_GPP_F6      0x02050006
+#define GPIO_SKL_LP_GPP_F7      0x02050007
+#define GPIO_SKL_LP_GPP_F8      0x02050008
+#define GPIO_SKL_LP_GPP_F9      0x02050009
+#define GPIO_SKL_LP_GPP_F10     0x0205000A
+#define GPIO_SKL_LP_GPP_F11     0x0205000B
+#define GPIO_SKL_LP_GPP_F12     0x0205000C
+#define GPIO_SKL_LP_GPP_F13     0x0205000D
+#define GPIO_SKL_LP_GPP_F14     0x0205000E
+#define GPIO_SKL_LP_GPP_F15     0x0205000F
+#define GPIO_SKL_LP_GPP_F16     0x02050010
+#define GPIO_SKL_LP_GPP_F17     0x02050011
+#define GPIO_SKL_LP_GPP_F18     0x02050012
+#define GPIO_SKL_LP_GPP_F19     0x02050013
+#define GPIO_SKL_LP_GPP_F20     0x02050014
+#define GPIO_SKL_LP_GPP_F21     0x02050015
+#define GPIO_SKL_LP_GPP_F22     0x02050016
+#define GPIO_SKL_LP_GPP_F23     0x02050017
+#define GPIO_SKL_LP_GPP_G0      0x02060000
+#define GPIO_SKL_LP_GPP_G1      0x02060001
+#define GPIO_SKL_LP_GPP_G2      0x02060002
+#define GPIO_SKL_LP_GPP_G3      0x02060003
+#define GPIO_SKL_LP_GPP_G4      0x02060004
+#define GPIO_SKL_LP_GPP_G5      0x02060005
+#define GPIO_SKL_LP_GPP_G6      0x02060006
+#define GPIO_SKL_LP_GPP_G7      0x02060007
+#define GPIO_SKL_LP_GPD0        0x02070000
+#define GPIO_SKL_LP_GPD1        0x02070001
+#define GPIO_SKL_LP_GPD2        0x02070002
+#define GPIO_SKL_LP_GPD3        0x02070003
+#define GPIO_SKL_LP_GPD4        0x02070004
+#define GPIO_SKL_LP_GPD5        0x02070005
+#define GPIO_SKL_LP_GPD6        0x02070006
+#define GPIO_SKL_LP_GPD7        0x02070007
+#define GPIO_SKL_LP_GPD8        0x02070008
+#define GPIO_SKL_LP_GPD9        0x02070009
+#define GPIO_SKL_LP_GPD10       0x0207000A
+#define GPIO_SKL_LP_GPD11       0x0207000B
+
+#define END_OF_GPIO_TABLE   0xFFFFFFFF
+
+//Sample GPIO Table
+
+static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] =
+{
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//H_RCIN_N
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_AD0_ESPI_IO0
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_AD1_ESPI_IO1
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_AD2_ESPI_IO2
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_AD3_ESPI_IO3
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//LPC_FRAME_ESPI_CS_N
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//INT_SERIRQ
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A7,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PM_SLP_S0ix_R_N
+  {GPIO_SKL_LP_GPP_A8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PM_CLKRUN_N
+//skip for eSPI function    {GPIO_SKL_LP_GPP_A9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_CLK_ESPI_CLK
+  {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//PCH_CLK_PCI_TPM
+  {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//EC_HID_INTR
+  {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N
+  {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SUS_PWR_ACK_R
+//skip for eSPI function    {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N
+  {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//SUSACK_R_N
+  {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_1P8_SEL
+  {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_PWR_EN_N
+  {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_GP_0_SENSOR
+  {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_GP_1_SENSOR
+  {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_GP_2_SENSOR
+  {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//GNSS_CHUB_IRQ
+  {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//FPS_SLP_N
+  {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//FPS_DRDY
+  {GPIO_SKL_LP_GPP_B0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//V0.85A_VID0
+  {GPIO_SKL_LP_GPP_B1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//V0.85A_VID1
+  {GPIO_SKL_LP_GPP_B2,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//GP_VRALERTB
+  {GPIO_SKL_LP_GPP_B3,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset,  GpioTermNone}},//TCH_PAD_INTR_R_N
+  {GPIO_SKL_LP_GPP_B4,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//BT_RF_KILL_N
+  {GPIO_SKL_LP_GPP_B5,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//M.2_BT_UART_WAKE_N
+  // {GPIO_SKL_LP_GPP_B6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_SLOT1_N
+  // {GPIO_SKL_LP_GPP_B7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_SLOT2_LAN_N
+  // {GPIO_SKL_LP_GPP_B8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N
+  // {GPIO_SKL_LP_GPP_B9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_M.2_WIGIG_N
+  // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_M.2_WLAN_N
+  {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//MPHY_EXT_PWR_GATEB
+  {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_SLP_S0_N
+  {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PLT_RST_N
+  {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//TCH_PNL_PWREN
+  {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutLow,     GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_NFC_DFU
+  {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset,  GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N
+  {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset,  GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N
+  {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset,  GpioTermWpu20K}},//PCH_SLOT1_WAKE_N
+  {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,   GpioTermNone}},//FPS_GSPI1_CS_R1_N
+  {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//FPS_GSPI1_CLK_R1
+  {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//FPS_GSPI1_MISO_R1
+  {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1
+  {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N
+  {GPIO_SKL_LP_GPP_C0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SMB_CLK
+  {GPIO_SKL_LP_GPP_C1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//SMB_DATA
+  {GPIO_SKL_LP_GPP_C2,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N
+  {GPIO_SKL_LP_GPP_C3,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SML0_CLK
+  {GPIO_SKL_LP_GPP_C4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SML0_DATA
+  {GPIO_SKL_LP_GPP_C5,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N
+  {GPIO_SKL_LP_GPP_C6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SML1_CLK
+  {GPIO_SKL_LP_GPP_C7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//SML1_DATA
+  {GPIO_SKL_LP_GPP_C8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART0_RXD
+  {GPIO_SKL_LP_GPP_C9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART0_TXD
+  {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART0_RTS_N
+  {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART0_CTS_N
+  {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD
+  {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD
+  {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N
+  {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N
+  {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_I2C0_SDA
+  {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_I2C0_SCL
+  {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_I2C1_SDA
+  {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_I2C1_SCL
+  {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART2_RXD
+  {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART2_TXD
+  {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART2_RTS_N
+  {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART2_CTS_N
+  {GPIO_SKL_LP_GPP_D0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_CS_N
+  {GPIO_SKL_LP_GPP_D1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_CLK
+  {GPIO_SKL_LP_GPP_D2,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_MISO
+  {GPIO_SKL_LP_GPP_D3,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_MOSI
+  {GPIO_SKL_LP_GPP_D4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CSI2_FLASH_STROBE
+  {GPIO_SKL_LP_GPP_D5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_I2C0_SDA
+  {GPIO_SKL_LP_GPP_D6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_I2C0_SCL
+  {GPIO_SKL_LP_GPP_D7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_I2C1_SDA
+  {GPIO_SKL_LP_GPP_D8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_I2C1_SCL
+  {GPIO_SKL_LP_GPP_D9,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//HOME_BTN
+  {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SCREEN_LOCK_PCH
+  {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//VOL_UP_PCH
+  {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//VOL_DOWN_PCH
+  {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA
+  {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK
+  {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_UART0_RTS_N
+  {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N
+  {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DMIC_CLK_1
+  {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DMIC_DATA_1
+  {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DMIC_CLK_0
+  {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DMIC_DATA_0
+  {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_IO2
+  {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_IO3
+  {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP_MCLK
+  {GPIO_SKL_LP_GPP_E0,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//SPI_TPM_HDR_IRQ_N
+  {GPIO_SKL_LP_GPP_E1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SATA_ODD_PRSNT_N
+  {GPIO_SKL_LP_GPP_E2,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N
+  {GPIO_SKL_LP_GPP_E3,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioResumeReset,  GpioTermNone}},//EINK_SSR_DFU_N
+  {GPIO_SKL_LP_GPP_E4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_NFC_RESET
+  {GPIO_SKL_LP_GPP_E5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R
+  {GPIO_SKL_LP_GPP_E6,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutLow,     GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R
+  {GPIO_SKL_LP_GPP_E8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_SATA_LED_N
+  {GPIO_SKL_LP_GPP_E9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//USB_OC_0_WP1_OTG_N
+  {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//USB_OC_1_WP4_N
+  {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N
+  {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_NFC_IRQ
+  {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DDI1_HPD_Q
+  {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DDI2_HPD_Q
+  {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset,  GpioTermNone}},//SMC_EXTSMI_R_N
+  {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset,  GpioTermNone}},//SMC_RUNTIME_SCI_R_N
+  {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EDP_HPD
+  {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DDI1_CTRL_CLK
+  {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//DDI1_CTRL_DATA
+  {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DDI2_CTRL_CLK
+  {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//DDI2_CTRL_DATA
+  {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//PCH_CODEC_IRQ
+  {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//TCH_PNL_RST_N
+  {GPIO_SKL_LP_GPP_F0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP2_SCLK
+  {GPIO_SKL_LP_GPP_F1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP2_SFRM
+  {GPIO_SKL_LP_GPP_F2,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP2_TXD
+  {GPIO_SKL_LP_GPP_F3,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP2_RXD
+  {GPIO_SKL_LP_GPP_F4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA
+  {GPIO_SKL_LP_GPP_F5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL
+  {GPIO_SKL_LP_GPP_F6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA
+  {GPIO_SKL_LP_GPP_F7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL
+  {GPIO_SKL_LP_GPP_F8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA
+  {GPIO_SKL_LP_GPP_F9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL
+  {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA
+  {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL
+  {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_CMD
+  {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA0
+  {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA1
+  {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA2
+  {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA3
+  {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA4
+  {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA5
+  {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA6
+  {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA7
+  {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_RCLK
+  {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_CLK
+  {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET
+  {GPIO_SKL_LP_GPP_G0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_CMD
+  {GPIO_SKL_LP_GPP_G1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_DATA0
+  {GPIO_SKL_LP_GPP_G2,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_DATA1
+  {GPIO_SKL_LP_GPP_G3,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_DATA2
+  {GPIO_SKL_LP_GPP_G4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_DATA3
+  {GPIO_SKL_LP_GPP_G5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_CDB
+  {GPIO_SKL_LP_GPP_G6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_CLK
+  {GPIO_SKL_LP_GPP_G7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_WP
+  {GPIO_SKL_LP_GPD0,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//PM_BATLOW_R_N
+  {GPIO_SKL_LP_GPD1,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//AC_PRESENT_R
+  {GPIO_SKL_LP_GPD2,   {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset,  GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N
+  {GPIO_SKL_LP_GPD3,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermWpu20K}},//PM_PWRBTN_R_N
+  {GPIO_SKL_LP_GPD4,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SLP_S3_R_N
+  {GPIO_SKL_LP_GPD5,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SLP_S4_R_N
+  {GPIO_SKL_LP_GPD6,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SLP_M_R_N
+  {GPIO_SKL_LP_GPD7,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//USB_WAKEOUT_INTRUDET_N
+  {GPIO_SKL_LP_GPD8,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SUS_CLK
+  {GPIO_SKL_LP_GPD9,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//PCH_SLP_WLAN_N
+  {GPIO_SKL_LP_GPD10,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SLP_S5_R_N
+  {GPIO_SKL_LP_GPD11,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//PM_LANPHY_ENABLE
+  {END_OF_GPIO_TABLE,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//Marking End of Table
+};
+
+#endif   //_GPIO_CONFIG_H_
diff --git a/CometLakeFspBinPkg/CometLake2/Include/HobUsageDataHob.h b/CometLakeFspBinPkg/CometLake2/Include/HobUsageDataHob.h
new file mode 100644
index 0000000..2712130
--- /dev/null
+++ b/CometLakeFspBinPkg/CometLake2/Include/HobUsageDataHob.h
@@ -0,0 +1,35 @@
+/** @file
+  Definitions for Hob Usage data HOB
+
+  @copyright
+  Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@par Specification Reference:
+**/
+
+#ifndef _HOB_USAGE_DATA_HOB_H_
+#define _HOB_USAGE_DATA_HOB_H_
+
+extern EFI_GUID gHobUsageDataGuid;
+
+#pragma pack (push, 1)
+
+/**
+  Hob Usage Data Hob
+
+  <b>Revision 1:</b>
+  - Initial version.
+**/
+typedef struct {
+  EFI_PHYSICAL_ADDRESS EfiMemoryTop;
+  EFI_PHYSICAL_ADDRESS EfiMemoryBottom;
+  EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop;
+  EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom;
+  UINTN                FreeMemory;
+} HOB_USAGE_DATA_HOB;
+
+#pragma pack (pop)
+
+#endif // _HOB_USAGE_DATA_HOB_H_
diff --git a/CometLakeFspBinPkg/CometLake2/Include/MemInfoHob.h b/CometLakeFspBinPkg/CometLake2/Include/MemInfoHob.h
new file mode 100644
index 0000000..1c94e8e
--- /dev/null
+++ b/CometLakeFspBinPkg/CometLake2/Include/MemInfoHob.h
@@ -0,0 +1,263 @@
+/** @file
+  This file contains definitions required for creation of
+  Memory S3 Save data, Memory Info data and Memory Platform
+  data hobs.
+
+  @copyright
+  Copyright (c) 1999 - 2020, Intel Corporation. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@par Specification Reference:
+**/
+
+#ifndef _MEM_INFO_HOB_H_
+#define _MEM_INFO_HOB_H_
+
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiHob.h>
+
+#pragma pack (push, 1)
+
+extern EFI_GUID gSiMemoryS3DataGuid;
+extern EFI_GUID gSiMemoryInfoDataGuid;
+extern EFI_GUID gSiMemoryPlatformDataGuid;
+
+#define MAX_NODE        1
+#define MAX_CH          2
+#define MAX_DIMM        2
+
+///
+/// Host reset states from MRC.
+///
+#define  WARM_BOOT        2
+
+#define R_MC_CHNL_RANK_PRESENT  0x7C
+#define   B_RANK0_PRS           BIT0
+#define   B_RANK1_PRS           BIT1
+#define   B_RANK2_PRS           BIT4
+#define   B_RANK3_PRS           BIT5
+
+///
+/// Defines taken from MRC so avoid having to include MrcInterface.h
+///
+
+//
+// Matches MAX_SPD_SAVE define in MRC
+//
+#ifndef MAX_SPD_SAVE
+#define MAX_SPD_SAVE 29
+#endif
+
+//
+// MRC version description.
+//
+typedef struct {
+  UINT8  Major;     ///< Major version number
+  UINT8  Minor;     ///< Minor version number
+  UINT8  Rev;       ///< Revision number
+  UINT8  Build;     ///< Build number
+} SiMrcVersion;
+
+//
+// Matches MrcChannelSts enum in MRC
+//
+#ifndef CHANNEL_NOT_PRESENT
+#define CHANNEL_NOT_PRESENT     0  // There is no channel present on the controller.
+#endif
+#ifndef CHANNEL_DISABLED
+#define CHANNEL_DISABLED     1  // There is a channel present but it is disabled.
+#endif
+#ifndef CHANNEL_PRESENT
+#define CHANNEL_PRESENT     2  // There is a channel present and it is enabled.
+#endif
+
+//
+// Matches MrcDimmSts enum in MRC
+//
+#ifndef DIMM_ENABLED
+#define DIMM_ENABLED     0  // DIMM/rank Pair is enabled, presence will be detected.
+#endif
+#ifndef DIMM_DISABLED
+#define DIMM_DISABLED    1  // DIMM/rank Pair is disabled, regardless of presence.
+#endif
+#ifndef DIMM_PRESENT
+#define DIMM_PRESENT     2  // There is a DIMM present in the slot/rank pair and it will be used.
+#endif
+#ifndef DIMM_NOT_PRESENT
+#define DIMM_NOT_PRESENT 3  // There is no DIMM present in the slot/rank pair.
+#endif
+
+//
+// Matches MrcBootMode enum in MRC
+//
+#ifndef bmCold
+#define bmCold 0            // Cold boot
+#endif
+#ifndef bmWarm
+#define bmWarm 1            // Warm boot
+#endif
+#ifndef bmS3
+#define bmS3   2            // S3 resume
+#endif
+#ifndef bmFast
+#define bmFast 3            // Fast boot
+#endif
+
+//
+// Matches MrcDdrType enum in MRC
+//
+#ifndef MRC_DDR_TYPE_DDR4
+#define MRC_DDR_TYPE_DDR4     0
+#endif
+#ifndef MRC_DDR_TYPE_DDR3
+#define MRC_DDR_TYPE_DDR3     1
+#endif
+#ifndef MRC_DDR_TYPE_LPDDR3
+#define MRC_DDR_TYPE_LPDDR3   2
+#endif
+#ifndef MRC_DDR_TYPE_UNKNOWN
+#define MRC_DDR_TYPE_UNKNOWN  3
+#endif
+
+#define MAX_PROFILE_NUM     4 // number of memory profiles supported
+#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
+
+//
+// DIMM timings
+//
+typedef struct {
+  UINT32 tCK;       ///< Memory cycle time, in femtoseconds.
+  UINT16 NMode;     ///< Number of tCK cycles for the channel DIMM's command rate mode.
+  UINT16 tCL;       ///< Number of tCK cycles for the channel DIMM's CAS latency.
+  UINT16 tCWL;      ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
+  UINT16 tFAW;      ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
+  UINT16 tRAS;      ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
+  UINT16 tRCDtRP;   ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
+  UINT16 tREFI;     ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
+  UINT16 tRFC;      ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+  UINT16 tRFCpb;    ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
+  UINT16 tRFC2;     ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+  UINT16 tRFC4;     ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+  UINT16 tRPab;     ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
+  UINT16 tRRD;      ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
+  UINT16 tRRD_L;    ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
+  UINT16 tRRD_S;    ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
+  UINT16 tRTP;      ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
+  UINT16 tWR;       ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
+  UINT16 tWTR;      ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
+  UINT16 tWTR_L;    ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
+  UINT16 tWTR_S;    ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
+  UINT16 tCCD_L;  ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
+} MRC_CH_TIMING;
+
+typedef struct {
+  UINT8 SG;         ///< Number of tCK cycles between transactions in the same bank group.
+  UINT8 DG;         ///< Number of tCK cycles between transactions when switching bank groups.
+  UINT8 DR;         ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).
+  UINT8 DD;         ///< Number of tCK cycles between transactions when switching between DIMMs.
+} MRC_TA_TIMING;
+
+///
+/// Memory SMBIOS & OC Memory Data Hob
+///
+typedef struct {
+  UINT8            Status;                  ///< See MrcDimmStatus for the definition of this field.
+  UINT8            DimmId;
+  UINT32           DimmCapacity;            ///< DIMM size in MBytes.
+  UINT16           MfgId;
+  UINT8            ModulePartNum[20];       ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
+  UINT8            RankInDimm;              ///< The number of ranks in this DIMM.
+  UINT8            SpdDramDeviceType;       ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
+  UINT8            SpdModuleType;           ///< Save SPD ModuleType information needed for SMBIOS structure creation.
+  UINT8            SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
+  UINT8            SpdSave[MAX_SPD_SAVE];   ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
+  UINT16           Speed;                   ///< The maximum capable speed of the device, in MHz.
+} DIMM_INFO;
+
+typedef struct {
+  UINT8            Status;                  ///< Indicates whether this channel should be used.
+  UINT8            ChannelId;
+  UINT8            DimmCount;               ///< Number of valid DIMMs that exist in the channel.
+  MRC_CH_TIMING    Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
+  DIMM_INFO        DimmInfo[MAX_DIMM];      ///< Save the DIMM output characteristics.
+  MRC_TA_TIMING    tRd2Rd;                  ///< Read-to-Read   Turn Around Timings
+  MRC_TA_TIMING    tRd2Wr;                  ///< Read-to-Write  Turn Around Timings
+  MRC_TA_TIMING    tWr2Rd;                  ///< Write-to-Read  Turn Around Timings
+  MRC_TA_TIMING    tWr2Wr;                  ///< Write-to-Write Turn Around Timings
+} CHANNEL_INFO;
+
+typedef struct {
+  UINT8             Status;                  ///< Indicates whether this controller should be used.
+  UINT16            DeviceId;                ///< The PCI device id of this memory controller.
+  UINT8             RevisionId;              ///< The PCI revision id of this memory controller.
+  UINT8             ChannelCount;            ///< Number of valid channels that exist on the controller.
+  CHANNEL_INFO      ChannelInfo[MAX_CH];     ///< The following are channel level definitions.
+  MRC_TA_TIMING    tRd2Rd;                   ///< Deprecated and moved to CHANNEL_INFO. Read-to-Read   Turn Around Timings
+  MRC_TA_TIMING    tRd2Wr;                   ///< Deprecated and moved to CHANNEL_INFO. Read-to-Write  Turn Around Timings
+  MRC_TA_TIMING    tWr2Rd;                   ///< Deprecated and moved to CHANNEL_INFO. Write-to-Read  Turn Around Timings
+  MRC_TA_TIMING    tWr2Wr;                   ///< Deprecated and moved to CHANNEL_INFO. Write-to-Write Turn Around Timings
+} CONTROLLER_INFO;
+
+typedef struct {
+  UINT8             Revision;
+  UINT16            DataWidth;              ///< Data width, in bits, of this memory device
+  /** As defined in SMBIOS 3.0 spec
+    Section 7.18.2 and Table 75
+  **/
+  UINT8             MemoryType;             ///< DDR type: DDR3, DDR4, or LPDDR3
+  UINT16            MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
+  UINT16            ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
+  /** As defined in SMBIOS 3.0 spec
+    Section 7.17.3 and Table 72
+  **/
+  UINT8             ErrorCorrectionType;
+
+  SiMrcVersion      Version;
+  BOOLEAN           EccSupport;
+  UINT8             MemoryProfile;
+  UINT32            TotalPhysicalMemorySize;
+  UINT32            DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
+  UINT8             XmpProfileEnable;                  ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
+  UINT8             Ratio;
+  UINT8             RefClk;
+  UINT32            VddVoltage[MAX_PROFILE_NUM];
+  CONTROLLER_INFO   Controller[MAX_NODE];
+} MEMORY_INFO_DATA_HOB;
+
+/**
+  Memory Platform Data Hob
+
+  <b>Revision 1:</b>
+  - Initial version.
+  <b>Revision 2:</b>
+  - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
+**/
+typedef struct {
+  UINT8             Revision;
+  UINT8             Reserved[3];
+  UINT32            BootMode;
+  UINT32            TsegSize;
+  UINT32            TsegBase;
+  UINT32            PrmrrSize;
+  UINT32            PrmrrBase;
+  UINT32            GttBase;
+  UINT32            MmioSize;
+  UINT32            PciEBaseAddress;
+  UINT32            GdxcIotBase;
+  UINT32            GdxcIotSize;
+  UINT32            GdxcMotBase;
+  UINT32            GdxcMotSize;
+
+} MEMORY_PLATFORM_DATA;
+
+typedef struct {
+  EFI_HOB_GUID_TYPE    EfiHobGuidType;
+  MEMORY_PLATFORM_DATA Data;
+  UINT8                *Buffer;
+} MEMORY_PLATFORM_DATA_HOB;
+
+#pragma pack (pop)
+
+#endif // _MEM_INFO_HOB_H_
diff --git a/CometLakeFspBinPkg/CometLake2/Include/SmbiosCacheInfoHob.h b/CometLakeFspBinPkg/CometLake2/Include/SmbiosCacheInfoHob.h
new file mode 100644
index 0000000..87913d9
--- /dev/null
+++ b/CometLakeFspBinPkg/CometLake2/Include/SmbiosCacheInfoHob.h
@@ -0,0 +1,49 @@
+/** @file
+  Header file for SMBIOS Cache Info HOB
+
+ @copyright
+  Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  System Management BIOS (SMBIOS) Reference Specification v3.1.0
+  dated 2016-Nov-16 (DSP0134)
+  http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf
+**/
+
+#ifndef _SMBIOS_CACHE_INFO_HOB_H_
+#define _SMBIOS_CACHE_INFO_HOB_H_
+
+#include <Uefi.h>
+#include <Pi/PiHob.h>
+
+#pragma pack(1)
+///
+/// SMBIOS Cache Info HOB Structure
+///
+typedef struct {
+  UINT16     ProcessorSocketNumber;
+  UINT16     NumberOfCacheLevels;         ///< Based on Number of Cache Types L1/L2/L3
+  UINT8      SocketDesignationStrIndex;   ///< String Index in the string Buffer. Example "L1-CACHE"
+  UINT16     CacheConfiguration;          ///< Format defined in SMBIOS Spec v3.1 Section7.8 Table36
+  UINT16     MaxCacheSize;                ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
+  UINT16     InstalledSize;               ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
+  UINT16     SupportedSramType;           ///< Format defined in SMBIOS Spec v3.1 Section7.8.2
+  UINT16     CurrentSramType;             ///< Format defined in SMBIOS Spec v3.1 Section7.8.2
+  UINT8      CacheSpeed;                  ///< Cache Speed in nanoseconds. 0 if speed is unknown.
+  UINT8      ErrorCorrectionType;         ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.3
+  UINT8      SystemCacheType;             ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.4
+  UINT8      Associativity;               ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.5
+  //
+  // Add for smbios 3.1.0
+  //
+  UINT32     MaximumCacheSize2;           ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
+  UINT32     InstalledSize2;              ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
+  /**
+  String Buffer - each string terminated by NULL "0x00"
+  String buffer terminated by double NULL "0x0000"
+  **/
+} SMBIOS_CACHE_INFO;
+#pragma pack()
+
+#endif // _SMBIOS_CACHE_INFO_HOB_H_
diff --git a/CometLakeFspBinPkg/CometLake2/Include/SmbiosProcessorInfoHob.h b/CometLakeFspBinPkg/CometLake2/Include/SmbiosProcessorInfoHob.h
new file mode 100644
index 0000000..1fa6795
--- /dev/null
+++ b/CometLakeFspBinPkg/CometLake2/Include/SmbiosProcessorInfoHob.h
@@ -0,0 +1,60 @@
+/** @file
+  Header file for SMBIOS Processor Info HOB
+
+ @copyright
+  Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  System Management BIOS (SMBIOS) Reference Specification v3.1.0
+  dated 2016-Nov-16 (DSP0134)
+  http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf
+**/
+
+#ifndef _SMBIOS_PROCESSOR_INFO_HOB_H_
+#define _SMBIOS_PROCESSOR_INFO_HOB_H_
+
+#include <Uefi.h>
+#include <Pi/PiHob.h>
+
+#pragma pack(1)
+///
+/// SMBIOS Processor Info HOB Structure
+///
+typedef struct {
+  UINT16     TotalNumberOfSockets;
+  UINT16     CurrentSocketNumber;
+  UINT8      ProcessorType;                 ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.1
+  /** This info is used for both ProcessorFamily and ProcessorFamily2 fields
+      See ENUM defined in SMBIOS Spec v3.1 Section 7.5.2
+  **/
+  UINT16     ProcessorFamily;
+  UINT8      ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer
+  UINT64     ProcessorId;                   ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.3
+  UINT8      ProcessorVersionStrIndex;      ///< Index of the String in the String Buffer
+  UINT8      Voltage;                       ///< Format defined in SMBIOS Spec v3.1 Section 7.5.4
+  UINT16     ExternalClockInMHz;            ///< External Clock Frequency. Set to 0 if unknown.
+  UINT16     CurrentSpeedInMHz;             ///< Snapshot of current processor speed during boot
+  UINT8      Status;                        ///< Format defined in the SMBIOS Spec v3.1 Table 21
+  UINT8      ProcessorUpgrade;              ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.5
+  /** This info is used for both CoreCount & CoreCount2 fields
+      See detailed description in SMBIOS Spec v3.1 Section 7.5.6
+  **/
+  UINT16     CoreCount;
+  /** This info is used for both CoreEnabled & CoreEnabled2 fields
+      See detailed description in SMBIOS Spec v3.1 Section 7.5.7
+  **/
+  UINT16     EnabledCoreCount;
+  /** This info is used for both ThreadCount & ThreadCount2 fields
+      See detailed description in SMBIOS Spec v3.1 Section 7.5.8
+  **/
+  UINT16     ThreadCount;
+  UINT16     ProcessorCharacteristics;      ///< Format defined in SMBIOS Spec v3.1 Section 7.5.9
+  /**
+  String Buffer - each string terminated by NULL "0x00"
+  String buffer terminated by double NULL "0x0000"
+  **/
+} SMBIOS_PROCESSOR_INFO;
+#pragma pack()
+
+#endif // _SMBIOS_PROCESSOR_INFO_HOB_H_
diff --git a/CometLakeFspBinPkg/CometLake2/SampleCode/Vbt/Vbt.bin b/CometLakeFspBinPkg/CometLake2/SampleCode/Vbt/Vbt.bin
new file mode 100644
index 0000000..e801e45
--- /dev/null
+++ b/CometLakeFspBinPkg/CometLake2/SampleCode/Vbt/Vbt.bin
diff --git a/CometLakeFspBinPkg/CometLake2/SampleCode/Vbt/Vbt.bsf b/CometLakeFspBinPkg/CometLake2/SampleCode/Vbt/Vbt.bsf
new file mode 100644
index 0000000..30ec8b8
--- /dev/null
+++ b/CometLakeFspBinPkg/CometLake2/SampleCode/Vbt/Vbt.bsf
@@ -0,0 +1,11683 @@
+;   TITLE   BMP.bsf - BMP Script File for Video BIOS
+;==============================================================================
+; Advance Graphics ROM BIOS
+;------------------------------------------------------------------------------
+; Copyright (c) Intel Corporation (2000 - 2015).
+;
+; INTEL MAKES NO WARRANTY OF ANY KIND REGARDING THE CODE. THIS CODE IS
+; LICENSED ON AN "AS IS" BASIS AND INTEL WILL NOT PROVIDE ANY SUPPORT,
+; ASSISTANCE, INSTALLATION, TRAINING OR OTHER SERVICES.
+; INTEL DOES NOT PROVIDE ANY UPDATES, ENHANCEMENTS OR EXTENSIONS.
+; INTEL SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY,
+; NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY OTHER
+; WARRANTY.
+;
+; Intel disclaims all liability, including liability for infringement of
+; any proprietary rights, relating to use of the code. No license, express
+; or implied, by estoppel or otherwise, to any intellectual property rights
+; is granted herein.
+;
+; File Description:
+;   This file is the script file use by the BMP utility which will allow
+;   OEM's to edit data and select features on a binary file.
+;
+;------------------------------------------------------------------------------
+
+;==============================================================================
+; Header - Start of BMP Structure Definition
+;------------------------------------------------------------------------------
+StructDef
+
+Find                                      "BIOS_DATA_BLOCK "
+
+; The following block will determine the reference
+; pointer for all table pointer variables.
+Find_Ptr_Ref                              "BIOS_DATA_BLOCK" ; Reference to beginning of VB VBT data
+
+$BDB_Ver                                  2 bytes     ; BIOS Data Block version number (decimal, e.g.201 = 02.01)
+$BDB_Header_Size                          2 bytes     ; BIOS Data Block Header size
+$BDB_Size                                 2 bytes     ; BIOS Data Block size
+
+;==============================================================================
+; Block 254 - Signon Strings and Other General Data
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; Skip block ID and size
+
+$Bmp_BIOS_Size                            2 bytes
+$BIOS_Type                                1 byte      ; BIOS Type:
+
+$RelStage                                 1 byte      ; Release status
+
+$Chipset                                  1 byte      ; = 25 - Coffeelake
+
+SKIP                                      2 bit       ; Obsolete
+$Integrated_EFP                           1 bit       ; Integrated EFP Support:
+$eDP                                      1 bit       ; eDP:
+SKIP                                      4 bits
+ALIGN
+
+SKIP                                      4 bytes     ; Skip build number string
+
+$Signon                                   155 bytes   ; Signon string
+$Copyright                                61 bytes    ; Copyright string
+
+; General Byte Definitions
+$bmp_BIOS_CS                              2 bytes     ; BIOS code segment
+$bmp_VBIOS_Post_Mode                      1 byte      ; Mode number to set during V BIOS POST
+$bmp_BW_Percent                           1 byte      ; Set percentage of total memory BW
+SKIP                                      1 byte      ; Pop-up Memory Size
+$bmp_Resize_PCI_BIOS                      1 byte      ; BIOS size granularity in 0.5 KB
+SKIP                                      1 byte      ; Is the CRT already switched to DDC2
+
+; bmp_Allow_Config
+$Allow_Boot_DVI                           1 bit       ; Allow boot DVI even not attach
+$Allow_Aspect_Ratio                       1 bit       ; VBIOS aspect ratio for DOS
+SKIP                                      6 bits
+
+ALIGN
+
+;==============================================================================
+; Block 1 - General Bit Definitions
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; Skip block ID and size
+
+; bmp_Bits_1
+SKIP                                      1 byte      ; Skip bmp_bits_1 completely.
+ALIGN
+
+; bmp_Bits_2
+$Kvmr_Session_Enable                      1 bit       ; KVMR session enable/boot to fake DVI Display feature
+SKIP                                      5 bits
+$bmp_Dynamic_CdClock_Supported            1 bit       ; Enable/Disable Dynamic CD Clock select
+$Hotplug_Support_Enb                      1 bit       ; Hot Plug support in DOS
+ALIGN
+
+; bmp_Bits_3
+SKIP                                      2 bits      ; Skip 2 bits
+SKIP                                      1 bit       ; Obsolete.
+SKIP                                      5 bits      ; Skip remaining bits.
+ALIGN
+
+$bmp_Legacy_Monitor_Detect                1 bit       ; Reserved/Obsolete
+SKIP                                      7 bits      ; Reserved bits
+ALIGN
+
+; Int_Displays_Support
+SKIP                                      3 bits
+$DP_SSC_Enb                               1 bit       ; DP SSC Enable bit
+SKIP                                      1 bit       ; Obsolete/Reserved from CFL
+$DP_SSC_Dongle_Enb                        1 bit       ; DP SSC dongle Enable/Disable
+SKIP                                      2 bits      ; Reserved
+ALIGN
+
+;==============================================================================
+; Block 253 - PRD Boot Algorithm Table
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; Skip block ID and size
+
+SKIP                                      1 byte      ; Displays attached field is relevant in VBIOS only
+$ChildDevice1Primary                      1 byte      ; Primary
+$ChildDevice1Secondary                    1 byte      ; Secondary
+SKIP                                      1 byte
+$ChildDevice2Primary                      1 byte
+$ChildDevice2Secondary                    1 byte
+SKIP                                      1 byte
+$ChildDevice3Primary                      1 byte
+$ChildDevice3Secondary                    1 byte
+SKIP                                      1 byte
+$ChildDevice4Primary                      1 byte
+$ChildDevice4Secondary                    1 byte
+SKIP                                      1 byte
+$ChildDevice5Primary                      1 byte
+$ChildDevice5Secondary                    1 byte
+SKIP                                      1 byte
+$ChildDevice6Primary                      1 byte
+$ChildDevice6Secondary                    1 byte
+SKIP                                      1 byte
+$ChildDevice7Primary                      1 byte
+$ChildDevice7Secondary                    1 byte
+SKIP                                      1 byte
+$ChildDevice8Primary                      1 byte
+$ChildDevice8Secondary                    1 byte
+SKIP                                      1 byte
+$ChildDevice9Primary                      1 byte
+$ChildDevice9Secondary                    1 byte
+SKIP                                      1 byte
+$ChildDevice10Primary                     1 byte
+$ChildDevice10Secondary                   1 byte
+SKIP                                      1 byte
+$ChildDevice11Primary                     1 byte
+$ChildDevice11Secondary                   1 byte
+SKIP                                      1 byte
+$ChildDevice12Primary                     1 byte
+$ChildDevice12Secondary                   1 byte
+SKIP                                      1 byte
+$ChildDevice13Primary                     1 byte
+$ChildDevice13Secondary                   1 byte
+SKIP                                      1 byte
+$ChildDevice14Primary                     1 byte
+$ChildDevice14Secondary                   1 byte
+SKIP                                      1 byte
+$ChildDevice15Primary                     1 byte
+$ChildDevice15Secondary                   1 byte
+SKIP                                      1 byte
+$ChildDevice16Primary                     1 byte
+$ChildDevice16Secondary                   1 byte
+
+SKIP                                      2 bytes     ; No of entries
+
+;==============================================================================
+; Block 2 - General Data Definitions
+;------------------------------------------------------------------------------
+
+SKIP                                      3 bytes     ; Skip block ID and size
+
+; bmp_DDC_GPIO_Pins
+SKIP                                      1 byte      ; Obsolete: Was used for CRT DDC GMBUS pin pair
+
+; bmp_DPMS_Bits
+SKIP                                      1 byte      ; Skip bmp_dpms_bits completely.
+
+; bmp_Boot_Dev_Bits
+SKIP                                      2 bytes     ; Skip Boot display type
+
+$size_ChildStruc                          1 byte
+
+; Internal LFP Data structure
+SKIP                                      2 bytes     ; Skip Device Handle
+$LFP_Device_Class                         2 bytes     ; Device class
+SKIP                                      6 bytes     ; Skip till Flags 0 field
+SKIP                                      1 bit       ; Skip EDID less enable bit used for EFP's
+$Int_LFP_Compression_Enable               1 bit       ; Compression enable bit
+$Int_LFP_Compression_Method_Select        1 bit       ; Compression method select PPS/CPS
+$Int_LFP_Dual_Pipe_Ganged_Enable          1 bit       ; Dual pipe ganged support enable bit for LFP
+SKIP                                      4 bits      ; Skip remaining bits of Flags 0
+ALIGN
+
+$Int_LFP_Compression_Struct_Index         4 bits      ; Compression structure index in Block 55
+SKIP                                      4 bits      ; Skip remaining bits
+ALIGN
+
+$Int_LFP_Slave_Dvo_Port                   1 byte      ; Slave DVO port for LFP display.
+
+SKIP                                      3 bytes     ; Skip reserved_1 and add-in offset fields
+$Int_eDP_Port                             1 byte      ; eDP port select
+SKIP                                      6 bytes     ; Skip remaining Data structure
+SKIP                                      1 bit
+$LFP_Lane_Reversal                        1 bit       ; Port Reversal
+SKIP                                      1 bit       ; LSPCON bit skipped for LFP
+$LFP_IBoost_Enable                        1 bit       ; IBoost enable/disable for LFP.
+SKIP                                      1 bit       ; HPD inversion bit for BXT.
+SKIP                                      3 bits      ; Reserved
+SKIP                                      1 byte
+$Int_LFP_AUX_Channel                      1 byte      ; eDP AUX channel
+SKIP                                      11 bytes    ; Skip 11 bytes
+$Int_LFP_Dp_Boost_Magnitude               4 bits      ; eDP IBoost magnitude level
+SKIP                                      4 bits      ; Skip HDMI IBoost magnitude level field for LFP struct
+SKIP                                      1 byte      ; Skip DP Max link rate for EDP.
+
+; Internal EFP (HDMI/DP) Data structure
+; Device 1
+SKIP                                      2 bytes     ; Skip Device Handle
+$Int_EFP1_Type                            2 bytes     ; Device type
+SKIP                                      1 byte      ; I2C Speed
+$Int_EFP1_OnBoard_Pre_emphasis            3 bits      ; Set DisplayPort pre-emphasis level for onboard Redriver
+$Int_EFP1_OnBoard_Voltage_swing           3 bits      ; Set DisplayPort voltage swing level for onboard Redriver
+$Int_EFP1_OnBoard_Redriver_Present        1 bit       ; Set if onboard Redriver is present
+SKIP                                      1 bit       ; Reserved
+ALIGN
+$Int_EFP1_Dock_Pre_emphasis               3 bits      ; Set DisplayPort Redriver pre-emphasis level for dock Redriver
+$Int_EFP1_Dock_Voltage_swing              3 bits      ; Set DisplayPort Redriver voltage swing level for dock Redriver
+$Int_EFP1_Dock_Redriver_Present           1 bit       ; Set if dock Redriver is present
+SKIP                                      1 bit       ; Reserved
+ALIGN
+$Int_EFP1_HDMI_LS_Type                    5 bits      ; HDMI Level shifter configuration
+$Int_EFP1_HDMI_Maximum_Data_Rate          3 bits      ; HDMI maximum data rate
+ALIGN
+SKIP                                      2 bytes     ; Skip EDIDless DTD offset
+$EFP1_EDIDless_en                         1 bit       ; EDIDless enable bit
+$EFP1_Compression_Enable                  1 bit       ; Compression enable bit
+$EFP1_Compression_Method_Select           1 bit       ; Compression method select PPS/CPS
+$EFP1_Dual_Pipe_Ganged_Enable             1 bit       ; EFP1 dual pipe ganged display enable bit
+SKIP                                      4 bits      ; Skip remaining bits
+ALIGN
+$EFP1_Compression_Struct_Index            4 bits      ; Compression structure index in Block 55
+SKIP                                      4 bits      ; Reserved bits
+ALIGN
+$EFP1_Slave_Dvo_Port                      1 byte      ; Slave DVO port number for EFP 1
+SKIP                                      1 byte      ; Skip Reserved_1
+SKIP                                      2 bytes     ; skip Addin module table offset
+$Int_EFP1_Port                            1 byte      ; EFP1 port
+SKIP                                      2 bytes     ; Skip I2C bus and slave address
+$Int_EFP1_DDC_Pin                         1 byte      ; EFP1 DDC Pin
+SKIP                                      3 bytes     ; Skip Timing info pointer and DVO Config
+$Int_EFP1_Port_Dockable                   1 bit       ; HDMI/DP Docked Port
+$EFP1_Lane_Reversal                       1 bit       ; Port Reversal
+$LSPcon1_Options                          1 bit       ; Hdmi2.0 supported options
+$Int_EFP1_IBoost_Enable                   1 bit       ; IBoost enable/disable bit
+SKIP                                      1 bit       ; HPD inversion bit for BXT.
+SKIP                                      3 bits      ; Reserved
+ALIGN
+SKIP                                      1 byte      ; Obsolete: Was used for EFP compatibility field
+$Int_EFP1_AUX_Channel                     1 byte      ; DP AUX channel
+SKIP                                      1 byte      ; Obsolete: Was used for Dongle Detect
+SKIP                                      6 bytes     ; Skip to end of child structure
+$EFP1_USB_C_DongleFeature_Enabled         1 bit       ; USB type C dongle feature enabled
+$EFP1_Thunderbolt_Feature_Enabled         1 bit       ; Thunderbolt feature enabled
+SKIP                                      2 bits      ; Reserved
+$EFP1_DP_Port_Trace_Length                4 bits      ; DP port trace length for this port
+SKIP                                      3 bytes     ; GPIO resource ID and GPIO number
+$Int_EFP1_Dp_Boost_Magnitude              4 bits      ; DP IBoost magnitude level
+$Int_EFP1_Hdmi_Boost_Magnitude            4 bits      ; HDMI IBoost magnitude level
+SKIP                                      1 byte      ; Skip DP Max link rate
+
+; Device 2
+SKIP                                      2 bytes     ; Skip Device Handle
+$Int_EFP2_Type                            2 bytes     ; Device type
+SKIP                                      1 byte      ; I2C Speed
+$Int_EFP2_OnBoard_Pre_emphasis            3 bits      ; Set DisplayPort pre-emphasis level for onboard Redriver
+$Int_EFP2_OnBoard_Voltage_swing           3 bits      ; Set DisplayPort voltage swing level for onboard Redriver
+$Int_EFP2_OnBoard_Redriver_Present        1 bit       ; Set if onboard Redriver is present
+SKIP                                      1 bit       ; Reserved
+ALIGN
+$Int_EFP2_Dock_Pre_emphasis               3 bits      ; Set DisplayPort Redriver pre-emphasis level for dock Redriver
+$Int_EFP2_Dock_Voltage_swing              3 bits      ; Set DisplayPort Redriver voltage swing level for dock Redriver
+$Int_EFP2_Dock_Redriver_Present           1 bit       ; Set if dock Redriver is present
+SKIP                                      1 bit       ; Reserved
+ALIGN
+$Int_EFP2_HDMI_LS_Type                    5 bits      ; HDMI Level shifter configuration
+$Int_EFP2_HDMI_Maximum_Data_Rate          3 bits      ; HDMI maximum data rate
+ALIGN
+SKIP                                      2 bytes     ; Skip EDIDless DTD offset
+$EFP2_EDIDless_en                         1 bit       ; EDIDless enable bit
+$EFP2_Compression_Enable                  1 bit       ; Compression enable bit
+$EFP2_Compression_Method_Select           1 bit       ; Compression method select PPS/CPS
+$EFP2_Dual_Pipe_Ganged_Enable             1 bit       ; EFP2 dual pipe ganged display enable bit
+SKIP                                      4 bits      ; Skip remaining bits
+ALIGN
+$EFP2_Compression_Struct_Index            4 bits      ; Compression structure index in Block 55
+SKIP                                      4 bits      ; Reserved bits
+ALIGN
+$EFP2_Slave_Dvo_Port                      1 byte      ; Slave DVO port number for EFP 2
+SKIP                                      1 byte      ; Skip Reserved_1
+SKIP                                      2 bytes     ; skip add-in module table offset
+$Int_EFP2_Port                            1 byte      ; EFP1 port
+SKIP                                      2 bytes     ; Skip I2C bus and slave address
+$Int_EFP2_DDC_Pin                         1 byte      ; EFP1 DDC Pin
+SKIP                                      3 bytes     ; Timing info pointer and DVO Config
+$Int_EFP2_Port_Dockable                   1 bit       ; HDMI/DP Docked Port
+$EFP2_Lane_Reversal                       1 bit       ; Port Reversal
+$LSPcon2_Options                          1 bit       ; Hdmi2.0 support options
+$Int_EFP2_IBoost_Enable                   1 bit       ; IBoost enable/disable bit
+SKIP                                      1 bit       ; HPD inversion bit for BXT.
+SKIP                                      3 bits      ; Reserved
+ALIGN
+SKIP                                      1 byte      ; Obsolete: Was used for EFP compatibility field
+$Int_EFP2_AUX_Channel                     1 byte      ; DP AUX channel
+SKIP                                      1 byte      ; Obsolete: Was used for Dongle Detect
+SKIP                                      6 bytes     ; Skip to end of child structure
+$EFP2_USB_C_DongleFeature_Enabled         1 bit       ; USB type C dongle feature enabled
+$EFP2_Thunderbolt_Feature_Enabled         1 bit       ; Thunderbolt feature enabled
+SKIP                                      2 bits      ; Reserved
+$EFP2_DP_Port_Trace_Length                4 bits      ; DP port trace length for this port
+SKIP                                      3 bytes     ; GPIO resource ID and GPIO number
+$Int_EFP2_Dp_Boost_Magnitude              4 bits      ; DP IBoost magnitude level
+$Int_EFP2_Hdmi_Boost_Magnitude            4 bits      ; HDMI IBoost magnitude level
+SKIP                                      1 byte      ; Skip DP Max link rate.
+
+; Device 3
+SKIP                                      2 bytes     ; Skip Device Handle
+$Int_EFP3_Type                            2 bytes     ; Device type
+SKIP                                      1 byte      ; I2C Speed
+$Int_EFP3_OnBoard_Pre_emphasis            3 bits      ; Set DisplayPort pre-emphasis level for onboard Redriver
+$Int_EFP3_OnBoard_Voltage_swing           3 bits      ; Set DisplayPort voltage swing level for onboard Redriver
+$Int_EFP3_OnBoard_Redriver_Present        1 bit       ; Set if onboard Redriver is present
+SKIP                                      1 bit       ; Reserved
+ALIGN
+$Int_EFP3_Dock_Pre_emphasis               3 bits      ; Set DisplayPort Redriver pre-emphasis level for dock Redriver
+$Int_EFP3_Dock_Voltage_swing              3 bits      ; Set DisplayPort Redriver voltage swing level for dock Redriver
+$Int_EFP3_Dock_Redriver_Present           1 bit       ; Set if dock Redriver is present
+SKIP                                      1 bit       ; Reserved
+ALIGN
+$Int_EFP3_HDMI_LS_Type                    5 bits      ; HDMI Level shifter configuration
+$Int_EFP3_HDMI_Maximum_Data_Rate          3 bits      ; HDMI maximum data rate
+ALIGN
+SKIP                                      2 bytes     ; Skip EDIDless DTD offset
+$EFP3_EDIDless_en                         1 bit       ; EDIDless enable bit
+$EFP3_Compression_Enable                  1 bit       ; Compression enable bit
+$EFP3_Compression_Method_Select           1 bit       ; Compression method select PPS/CPS
+$EFP3_Dual_Pipe_Ganged_Enable             1 bit       ; EFP3 dual pipe ganged display enable bit
+SKIP                                      4 bits      ; Skip remaining bits
+ALIGN
+$EFP3_Compression_Struct_Index            4 bits      ; Compression structure index in Block 55
+SKIP                                      4 bits      ; Reserved bits
+ALIGN
+$EFP3_Slave_Dvo_Port                      1 byte      ; Slave DVO port number for EFP 3
+SKIP                                      1 byte      ; Skip Reserved_1
+SKIP                                      2 bytes     ; skip add-in module table offset
+$Int_EFP3_Port                            1 byte      ; EFP1 port
+SKIP                                      2 bytes     ; Skip I2C bus and slave address
+$Int_EFP3_DDC_Pin                         1 byte      ; EFP1 DDC Pin
+SKIP                                      3 bytes     ; Skip Timing Info Ptr and DVO Config
+$Int_EFP3_Port_Dockable                   1 bit       ; HDMI/DP Docked Port
+$EFP3_Lane_Reversal                       1 bit       ; Port Reversal
+$LSPcon3_Options                          1 bit       ; Hdmi2.0 supported options
+$Int_EFP3_IBoost_Enable                   1 bit       ; IBoost enable/disable bit
+SKIP                                      1 bit       ; HPD inversion bit for BXT.
+SKIP                                      3 bits      ; Reserved
+ALIGN
+SKIP                                      1 byte      ; Obsolete: Was used for EFP compatibility field
+$Int_EFP3_AUX_Channel                     1 byte      ; DP AUX channel
+SKIP                                      1 byte      ; Obsolete: Was used for Dongle Detect
+SKIP                                      6 bytes     ; Skip to end of child structure
+$EFP3_USB_C_DongleFeature_Enabled         1 bit       ; USB type C dongle feature enabled
+$EFP3_Thunderbolt_Feature_Enabled         1 bit       ; Thunderbolt feature enabled
+SKIP                                      2 bits      ; Reserved
+$EFP3_DP_Port_Trace_Length                4 bits      ; DP port trace length for this port
+SKIP                                      3 bytes     ; GPIO resource ID and GPIO number
+$Int_EFP3_Dp_Boost_Magnitude              4 bits      ; DP IBoost magnitude level
+$Int_EFP3_Hdmi_Boost_Magnitude            4 bits      ; HDMI IBoost magnitude level
+SKIP                                      1 byte      ; Skip DP Max link rate
+
+; Device 4
+SKIP                                      2 bytes     ; Skip Device Handle
+$Int_EFP4_Type                            2 bytes     ; Device type
+SKIP                                      1 byte      ; I2C Speed
+$Int_EFP4_OnBoard_Pre_emphasis            3 bits      ; Set DisplayPort pre-emphasis level for onboard Redriver
+$Int_EFP4_OnBoard_Voltage_swing           3 bits      ; Set DisplayPort voltage swing level for onboard Redriver
+$Int_EFP4_OnBoard_Redriver_Present        1 bit       ; Set if onboard Redriver is present
+SKIP                                      1 bit       ; Reserved
+ALIGN
+$Int_EFP4_Dock_Pre_emphasis               3 bits      ; Set DisplayPort Redriver pre-emphasis level for dock Redriver
+$Int_EFP4_Dock_Voltage_swing              3 bits      ; Set DisplayPort Redriver voltage swing level for dock Redriver
+$Int_EFP4_Dock_Redriver_Present           1 bit       ; Set if dock Redriver is present
+SKIP                                      1 bit       ; Reserved
+ALIGN
+$Int_EFP4_HDMI_LS_Type                    5 bits      ; HDMI Level shifter configuration
+$Int_EFP4_HDMI_Maximum_Data_Rate          3 bits      ; HDMI maximum data rate
+ALIGN
+SKIP                                      2 bytes     ; Skip EDIDless DTD offset
+$EFP4_EDIDless_en                         1 bit       ; EDIDless enable bit
+$EFP4_Compression_Enable                  1 bit       ; Compression enable bit
+$EFP4_Compression_Method_Select           1 bit       ; Compression method select PPS/CPS
+$EFP4_Dual_Pipe_Ganged_Enable             1 bit       ; EFP4 dual pipe ganged display enable bit
+SKIP                                      4 bits      ; Skip remaining bits
+ALIGN
+$EFP4_Compression_Struct_Index            4 bits      ; Compression structure index in Block 55
+SKIP                                      4 bits      ; Reserved bits
+ALIGN
+$EFP4_Slave_Dvo_Port                      1 byte      ; Slave DVO port number for EFP 4
+SKIP                                      1 byte      ; Skip Reserved_1
+SKIP                                      2 bytes     ; skip add-in module table offset
+$Int_EFP4_Port                            1 byte      ; EFP1 port
+SKIP                                      2 bytes     ; Skip I2C bus and slave address
+$Int_EFP4_DDC_Pin                         1 byte      ; EFP1 DDC Pin
+SKIP                                      3 bytes     ; Skip Timing Info Ptr and DVO Config
+$Int_EFP4_Port_Dockable                   1 bit       ; HDMI/DP Docked Port
+$EFP4_Lane_Reversal                       1 bit       ; Port Reversal
+$LSPcon4_Options                          1 bit       ; Hdmi2.0 supported options
+$Int_EFP4_IBoost_Enable                   1 bit       ; IBoost enable/disable bit
+SKIP                                      1 bit       ; HPD inversion bit for BXT.
+SKIP                                      3 bits      ; Reserved
+ALIGN
+SKIP                                      1 byte      ; Obsolete: Was used for EFP compatibility field
+$Int_EFP4_AUX_Channel                     1 byte      ; DP AUX channel
+SKIP                                      1 byte      ; Obsolete: Was used for Dongle Detect
+SKIP                                      6 bytes     ; Skip to end of child structure
+$EFP4_USB_C_DongleFeature_Enabled         1 bit       ; USB type C dongle feature enabled
+$EFP4_Thunderbolt_Feature_Enabled         1 bit       ; Thunderbolt feature enabled
+SKIP                                      2 bits      ; Reserved
+$EFP4_DP_Port_Trace_Length                4 bits      ; DP port trace length for this port
+SKIP                                      3 bytes     ; GPIO resource ID and GPIO number
+$Int_EFP4_Dp_Boost_Magnitude              4 bits      ; DP IBoost magnitude level
+$Int_EFP4_Hdmi_Boost_Magnitude            4 bits      ; HDMI IBoost magnitude level
+SKIP                                      1 byte      ; Skip DP Max link rate
+
+SKIP                                      39 bytes    ; Skip device data structure
+SKIP                                      39 bytes    ; Skip device data structure
+SKIP                                      39 bytes    ; Skip device data structure
+
+;==============================================================================
+; Block 3 - Original Display Toggle List
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; Skip block ID and size
+
+$bmp_Display_Detect                       1 byte      ; Obsolete
+
+;==============================================================================
+; Block 252 - Hook Defintions
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; Skip block ID and size
+
+SKIP                                      18 bytes    ; Skip 18 SBIOS hooks.
+
+; BMP - Pointer tables
+$Dev_Boot_Table_Ptr                       2 bytes     ; Start at BMP Boot table
+$Dev_Boot_Table_Size                      2 bytes
+$Dev_Boot_Table, $Dev_Boot_Table_Ptr, $Dev_Boot_Table_Size, Offset 0 byte
+
+$Dev_Removed_Table_Ptr                    2 bytes     ; Start at Display Configurations Removal table
+$Dev_Removed_Table_Size                   2 bytes
+$Dev_Removed_Table, $Dev_Removed_Table_Ptr, $Dev_Removed_Table_Size, Offset 0 byte
+
+$MMIO_Boot_Table_Ptr                      2 bytes     ; Start at BMP Boot table
+$MMIO_Boot_Table_Size                     2 bytes
+$MMIO_Boot_Table, $MMIO_Boot_Table_Ptr, $MMIO_Boot_Table_Size, Offset 0 byte
+
+$SWF_IO_Table_Ptr                         2 bytes     ; Start of IO SWF Table
+$SWF_IO_Table_Size                        2 bytes
+$SWF_IO_Table, $SWF_IO_Table_Ptr, $SWF_IO_Table_Size, Offset 3 bytes
+
+$SWF_MMIO_Table_Ptr                       2 bytes     ; Start of MMIO SWF Table
+$SWF_MMIO_Table_Size                      2 bytes
+$SWF_MMIO_Table, $SWF_MMIO_Table_Ptr, $SWF_MMIO_Table_Size, Offset 3 bytes
+
+$Mode_Rem_Table_Ptr                       2 bytes     ; Start at Mode Removal table
+$Mode_Rem_Table_Size                      2 bytes
+$Mode_Rem_Table, $Mode_Rem_Table_Ptr, $Mode_Rem_Table_Size, Offset 0 byte
+
+$Toggle_List1_Ptr                         2 bytes     ; Start at BMP Boot table
+$Toggle_List1_Size                        2 bytes
+$Toggle_List1, $Toggle_List1_Ptr, $Toggle_List1_Size, Offset 0 byte
+
+$Toggle_List2_Ptr                         2 bytes     ; Start at BMP Boot table
+$Toggle_List2_Size                        2 bytes
+$Toggle_List2, $Toggle_List2_Ptr, $Toggle_List2_Size, Offset 0 byte
+
+$Toggle_List3_Ptr                         2 bytes     ; Start at BMP Boot table
+$Toggle_List3_Size                        2 bytes
+$Toggle_List3, $Toggle_List3_Ptr, $Toggle_List3_Size, Offset 0 byte
+
+$Toggle_List4_Ptr                         2 bytes     ; Start at BMP Boot table
+$Toggle_List4_Size                        2 bytes
+$Toggle_List4, $Toggle_List4_Ptr, $Toggle_List4_Size, Offset 0 byte
+
+$eDP_Pwr_Seq_01_Ptr                       2 bytes
+$eDP_Pwr_Seq_01_Size                      2 bytes
+$eDP_Pwr_Seq_01, $eDP_Pwr_Seq_01_Ptr, $eDP_Pwr_Seq_01_Size, Offset 0 bytes
+$eDP_Pwr_Seq_02_Ptr                       2 bytes
+$eDP_Pwr_Seq_02_Size                      2 bytes
+$eDP_Pwr_Seq_02, $eDP_Pwr_Seq_02_Ptr, $eDP_Pwr_Seq_02_Size, Offset 0 bytes
+$eDP_Pwr_Seq_03_Ptr                       2 bytes
+$eDP_Pwr_Seq_03_Size                      2 bytes
+$eDP_Pwr_Seq_03, $eDP_Pwr_Seq_03_Ptr, $eDP_Pwr_Seq_03_Size, Offset 0 bytes
+$eDP_Pwr_Seq_04_Ptr                       2 bytes
+$eDP_Pwr_Seq_04_Size                      2 bytes
+$eDP_Pwr_Seq_04, $eDP_Pwr_Seq_04_Ptr, $eDP_Pwr_Seq_04_Size, Offset 0 bytes
+$eDP_Pwr_Seq_05_Ptr                       2 bytes
+$eDP_Pwr_Seq_05_Size                      2 bytes
+$eDP_Pwr_Seq_05, $eDP_Pwr_Seq_05_Ptr, $eDP_Pwr_Seq_05_Size, Offset 0 bytes
+$eDP_Pwr_Seq_06_Ptr                       2 bytes
+$eDP_Pwr_Seq_06_Size                      2 bytes
+$eDP_Pwr_Seq_06, $eDP_Pwr_Seq_06_Ptr, $eDP_Pwr_Seq_06_Size, Offset 0 bytes
+$eDP_Pwr_Seq_07_Ptr                       2 bytes
+$eDP_Pwr_Seq_07_Size                      2 bytes
+$eDP_Pwr_Seq_07, $eDP_Pwr_Seq_07_Ptr, $eDP_Pwr_Seq_07_Size, Offset 0 bytes
+$eDP_Pwr_Seq_08_Ptr                       2 bytes
+$eDP_Pwr_Seq_08_Size                      2 bytes
+$eDP_Pwr_Seq_08, $eDP_Pwr_Seq_08_Ptr, $eDP_Pwr_Seq_08_Size, Offset 0 bytes
+$eDP_Pwr_Seq_09_Ptr                       2 bytes
+$eDP_Pwr_Seq_09_Size                      2 bytes
+$eDP_Pwr_Seq_09, $eDP_Pwr_Seq_09_Ptr, $eDP_Pwr_Seq_09_Size, Offset 0 bytes
+$eDP_Pwr_Seq_10_Ptr                       2 bytes
+$eDP_Pwr_Seq_10_Size                      2 bytes
+$eDP_Pwr_Seq_10, $eDP_Pwr_Seq_10_Ptr, $eDP_Pwr_Seq_10_Size, Offset 0 bytes
+$eDP_Pwr_Seq_11_Ptr                       2 bytes
+$eDP_Pwr_Seq_11_Size                      2 bytes
+$eDP_Pwr_Seq_11, $eDP_Pwr_Seq_11_Ptr, $eDP_Pwr_Seq_11_Size, Offset 0 bytes
+$eDP_Pwr_Seq_12_Ptr                       2 bytes
+$eDP_Pwr_Seq_12_Size                      2 bytes
+$eDP_Pwr_Seq_12, $eDP_Pwr_Seq_12_Ptr, $eDP_Pwr_Seq_12_Size, Offset 0 bytes
+$eDP_Pwr_Seq_13_Ptr                       2 bytes
+$eDP_Pwr_Seq_13_Size                      2 bytes
+$eDP_Pwr_Seq_13, $eDP_Pwr_Seq_13_Ptr, $eDP_Pwr_Seq_13_Size, Offset 0 bytes
+$eDP_Pwr_Seq_14_Ptr                       2 bytes
+$eDP_Pwr_Seq_14_Size                      2 bytes
+$eDP_Pwr_Seq_14, $eDP_Pwr_Seq_14_Ptr, $eDP_Pwr_Seq_14_Size, Offset 0 bytes
+$eDP_Pwr_Seq_15_Ptr                       2 bytes
+$eDP_Pwr_Seq_15_Size                      2 bytes
+$eDP_Pwr_Seq_15, $eDP_Pwr_Seq_15_Ptr, $eDP_Pwr_Seq_15_Size, Offset 0 bytes
+$eDP_Pwr_Seq_16_Ptr                       2 bytes
+$eDP_Pwr_Seq_16_Size                      2 bytes
+$eDP_Pwr_Seq_16, $eDP_Pwr_Seq_16_Ptr, $eDP_Pwr_Seq_16_Size, Offset 0 bytes
+
+;==============================================================================
+; Block 6 - Extended MMIO Register tables
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; Skip block ID and size
+SKIP                                      117 bytes   ; Skip data
+
+;==============================================================================
+; Block 7 - IO Software flag register table for initialization
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; Skip block ID and size
+SKIP                                      7 bytes     ; Skip data
+
+;==============================================================================
+; Block 8 - MMIO Software flag register table for initialization
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; Skip block ID and size
+SKIP                                      61 bytes    ; Skip data
+
+;==============================================================================
+; Block 9 - PSR/SRD feature control block
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; Skip block ID and size
+
+; Panel #01
+$PSR_FullLink_Enable_01                   1 bit       ; Full link disable
+$PSR_Require_AUX2Wakeup_01                1 bit       ; Require AUX to wake up
+SKIP                                      6 bits      ; Reserved
+ALIGN
+
+$PSR_IdleFrames2Wait_01                   4 bits      ; Idle frames to wait for PSR enable
+$PSR_Lines2Wait_B4LinkS3_01               3 bits      ; Lines to wait before link standby
+SKIP                                      1 bit       ; Reserved
+ALIGN
+
+$PSR_TP1_WaitTime_01                      2 bytes     ; TP1 wake up time in multiples of 100
+$PSR_TP_2_3_WaitTime_01                   2 bytes     ; TP2/TP3 wake up time in multiples of 100
+ALIGN
+
+; Panel #02
+$PSR_FullLink_Enable_02                   1 bit       ; Full link disable
+$PSR_Require_AUX2Wakeup_02                1 bit       ; Require AUX to wake up
+SKIP                                      6 bits      ; Reserved
+ALIGN
+
+$PSR_IdleFrames2Wait_02                   4 bits      ; Idle frames to wait for PSR enable
+$PSR_Lines2Wait_B4LinkS3_02               3 bits      ; Lines to wait before link standby
+SKIP                                      1 bit       ; Reserved
+ALIGN
+
+$PSR_TP1_WaitTime_02                      2 bytes     ; TP1 wake up time in multiples of 100
+$PSR_TP_2_3_WaitTime_02                   2 bytes     ; TP2/TP3 wake up time in multiples of 100
+
+; Panel #03
+$PSR_FullLink_Enable_03                   1 bit       ; Full link disable
+$PSR_Require_AUX2Wakeup_03                1 bit       ; Require AUX to wake up
+SKIP                                      6 bits      ; Reserved
+ALIGN
+
+$PSR_IdleFrames2Wait_03                   4 bits      ; Idle frames to wait for PSR enable
+$PSR_Lines2Wait_B4LinkS3_03               3 bits      ; Lines to wait before link standby
+SKIP                                      1 bit       ; Reserved
+ALIGN
+
+$PSR_TP1_WaitTime_03                      2 bytes     ; TP1 wake up time in multiples of 100
+$PSR_TP_2_3_WaitTime_03                   2 bytes     ; TP2/TP3 wake up time in multiples of 100
+
+; Panel #04
+$PSR_FullLink_Enable_04                   1 bit       ; Full link disable
+$PSR_Require_AUX2Wakeup_04                1 bit       ; Require AUX to wake up
+SKIP                                      6 bits      ; Reserved
+ALIGN
+
+$PSR_IdleFrames2Wait_04                   4 bits      ; Idle frames to wait for PSR enable
+$PSR_Lines2Wait_B4LinkS3_04               3 bits      ; Lines to wait before link standby
+SKIP                                      1 bit       ; Reserved
+ALIGN
+
+$PSR_TP1_WaitTime_04                      2 bytes     ; TP1 wake up time in multiples of 100
+$PSR_TP_2_3_WaitTime_04                   2 bytes     ; TP2/TP3 wake up time in multiples of 100
+
+; Panel #05
+$PSR_FullLink_Enable_05                   1 bit       ; Full link disable
+$PSR_Require_AUX2Wakeup_05                1 bit       ; Require AUX to wake up
+SKIP                                      6 bits      ; Reserved
+ALIGN
+
+$PSR_IdleFrames2Wait_05                   4 bits      ; Idle frames to wait for PSR enable
+$PSR_Lines2Wait_B4LinkS3_05               3 bits      ; Lines to wait before link standby
+SKIP                                      1 bit       ; Reserved
+ALIGN
+
+$PSR_TP1_WaitTime_05                      2 bytes     ; TP1 wake up time in multiples of 100
+$PSR_TP_2_3_WaitTime_05                   2 bytes     ; TP2/TP3 wake up time in multiples of 100
+
+; Panel #06
+$PSR_FullLink_Enable_06                   1 bit       ; Full link disable
+$PSR_Require_AUX2Wakeup_06                1 bit       ; Require AUX to wake up
+SKIP                                      6 bits      ; Reserved
+ALIGN
+
+$PSR_IdleFrames2Wait_06                   4 bits      ; Idle frames to wait for PSR enable
+$PSR_Lines2Wait_B4LinkS3_06               3 bits      ; Lines to wait before link standby
+SKIP                                      1 bit       ; Reserved
+ALIGN
+
+$PSR_TP1_WaitTime_06                      2 bytes     ; TP1 wake up time in multiples of 100
+$PSR_TP_2_3_WaitTime_06                   2 bytes     ; TP2/TP3 wake up time in multiples of 100
+
+; Panel #07
+$PSR_FullLink_Enable_07                   1 bit       ; Full link disable
+$PSR_Require_AUX2Wakeup_07                1 bit       ; Require AUX to wake up
+SKIP                                      6 bits      ; Reserved
+ALIGN
+
+$PSR_IdleFrames2Wait_07                   4 bits      ; Idle frames to wait for PSR enable
+$PSR_Lines2Wait_B4LinkS3_07               3 bits      ; Lines to wait before link standby
+SKIP                                      1 bit       ; Reserved
+ALIGN
+
+$PSR_TP1_WaitTime_07                      2 bytes     ; TP1 wake up time in multiples of 100
+$PSR_TP_2_3_WaitTime_07                   2 bytes     ; TP2/TP3 wake up time in multiples of 100
+
+; Panel #08
+$PSR_FullLink_Enable_08                   1 bit       ; Full link disable
+$PSR_Require_AUX2Wakeup_08                1 bit       ; Require AUX to wake up
+SKIP                                      6 bits      ; Reserved
+ALIGN
+
+$PSR_IdleFrames2Wait_08                   4 bits      ; Idle frames to wait for PSR enable
+$PSR_Lines2Wait_B4LinkS3_08               3 bits      ; Lines to wait before link standby
+SKIP                                      1 bit       ; Reserved
+ALIGN
+
+$PSR_TP1_WaitTime_08                      2 bytes     ; TP1 wake up time in multiples of 100
+$PSR_TP_2_3_WaitTime_08                   2 bytes     ; TP2/TP3 wake up time in multiples of 100
+
+; Panel #09
+$PSR_FullLink_Enable_09                   1 bit       ; Full link disable
+$PSR_Require_AUX2Wakeup_09                1 bit       ; Require AUX to wake up
+SKIP                                      6 bits      ; Reserved
+ALIGN
+
+$PSR_IdleFrames2Wait_09                   4 bits      ; Idle frames to wait for PSR enable
+$PSR_Lines2Wait_B4LinkS3_09               3 bits      ; Lines to wait before link standby
+SKIP                                      1 bit       ; Reserved
+ALIGN
+
+$PSR_TP1_WaitTime_09                      2 bytes     ; TP1 wake up time in multiples of 100
+$PSR_TP_2_3_WaitTime_09                   2 bytes     ; TP2/TP3 wake up time in multiples of 100
+
+; Panel #10
+$PSR_FullLink_Enable_10                   1 bit       ; Full link disable
+$PSR_Require_AUX2Wakeup_10                1 bit       ; Require AUX to wake up
+SKIP                                      6 bits      ; Reserved
+ALIGN
+
+$PSR_IdleFrames2Wait_10                   4 bits      ; Idle frames to wait for PSR enable
+$PSR_Lines2Wait_B4LinkS3_10               3 bits      ; Lines to wait before link standby
+SKIP                                      1 bit
+ALIGN
+
+$PSR_TP1_WaitTime_10                      2 bytes     ; TP1 wake up time in multiples of 100
+$PSR_TP_2_3_WaitTime_10                   2 bytes     ; TP2/TP3 wake up time in multiples of 100
+
+; Panel #11
+$PSR_FullLink_Enable_11                   1 bit       ; Full link disable
+$PSR_Require_AUX2Wakeup_11                1 bit       ; Require AUX to wake up
+SKIP                                      6 bits      ; Reserved
+ALIGN
+
+$PSR_IdleFrames2Wait_11                   4 bits      ; Idle frames to wait for PSR enable
+$PSR_Lines2Wait_B4LinkS3_11               3 bits      ; Lines to wait before link standby
+SKIP                                      1 bit       ; Reserved
+ALIGN
+
+$PSR_TP1_WaitTime_11                      2 bytes     ; TP1 wake up time in multiples of 100
+$PSR_TP_2_3_WaitTime_11                   2 bytes     ; TP2/TP3 wake up time in multiples of 100
+
+; Panel #12
+$PSR_FullLink_Enable_12                   1 bit       ; Full link disable
+$PSR_Require_AUX2Wakeup_12                1 bit       ; Require AUX to wake up
+SKIP                                      6 bits      ; Reserved
+ALIGN
+
+$PSR_IdleFrames2Wait_12                   4 bits      ; Idle frames to wait for PSR enable
+$PSR_Lines2Wait_B4LinkS3_12               3 bits      ; Lines to wait before link standby
+SKIP                                      1 bit       ; Reserved
+ALIGN
+
+$PSR_TP1_WaitTime_12                      2 bytes     ; TP1 wake up time in multiples of 100
+$PSR_TP_2_3_WaitTime_12                   2 bytes     ; TP2/TP3 wake up time in multiples of 100
+
+; Panel #13
+$PSR_FullLink_Enable_13                   1 bit       ; Full link disable
+$PSR_Require_AUX2Wakeup_13                1 bit       ; Require AUX to wake up
+SKIP                                      6 bits      ; Reserved
+ALIGN
+
+$PSR_IdleFrames2Wait_13                   4 bits      ; Idle frames to wait for PSR enable
+$PSR_Lines2Wait_B4LinkS3_13               3 bits      ; Lines to wait before link standby
+SKIP                                      1 bit       ; Reserved
+ALIGN
+
+$PSR_TP1_WaitTime_13                      2 bytes     ; TP1 wake up time in multiples of 100
+$PSR_TP_2_3_WaitTime_13                   2 bytes     ; TP2/TP3 wake up time in multiples of 100
+
+; Panel #14
+$PSR_FullLink_Enable_14                   1 bit       ; Full link disable
+$PSR_Require_AUX2Wakeup_14                1 bit       ; Require AUX to wake up
+SKIP                                      6 bits      ; Reserved
+ALIGN
+
+$PSR_IdleFrames2Wait_14                   4 bits      ; Idle frames to wait for PSR enable
+$PSR_Lines2Wait_B4LinkS3_14               3 bits      ; Lines to wait before link standby
+SKIP                                      1 bit       ; Reserved
+ALIGN
+
+$PSR_TP1_WaitTime_14                      2 bytes     ; TP1 wake up time in multiples of 100
+$PSR_TP_2_3_WaitTime_14                   2 bytes     ; TP2/TP3 wake up time in multiples of 100
+
+; Panel #15
+$PSR_FullLink_Enable_15                   1 bit       ; Full link disable
+$PSR_Require_AUX2Wakeup_15                1 bit       ; Require AUX to wake up
+SKIP                                      6 bits      ; Reserved
+ALIGN
+
+$PSR_IdleFrames2Wait_15                   4 bits      ; Idle frames to wait for PSR enable
+$PSR_Lines2Wait_B4LinkS3_15               3 bits      ; Lines to wait before link standby
+SKIP                                      1 bit       ; Reserved
+ALIGN
+
+$PSR_TP1_WaitTime_15                      2 bytes     ; TP1 wake up time in multiples of 100
+$PSR_TP_2_3_WaitTime_15                   2 bytes     ; TP2/TP3 wake up time in multiples of 100
+
+; Panel #16
+$PSR_FullLink_Enable_16                   1 bit       ; Full link disable
+$PSR_Require_AUX2Wakeup_16                1 bit       ; Require AUX to wake up
+SKIP                                      6 bits      ; Reserved
+ALIGN
+
+$PSR_IdleFrames2Wait_16                   4 bits      ; Idle frames to wait for PSR enable
+$PSR_Lines2Wait_B4LinkS3_16               3 bits      ; Lines to wait before link standby
+SKIP                                      1 bit       ; Reserved
+ALIGN
+
+$PSR_TP1_WaitTime_16                      2 bytes     ; TP1 wake up time in multiples of 100
+$PSR_TP_2_3_WaitTime_16                   2 bytes     ; TP2/TP3 wake up time in multiples of 100
+
+;==============================================================================
+; Block 10 - Modes Removal Table.
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; Skip block ID and size
+SKIP                                      203 bytes   ; Skip data
+
+;==============================================================================
+; Block 12 - Driver default boot display
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; Skip block ID and size
+
+SKIP                                      1 bit
+SKIP                                      1 bit
+$Allow_FDOS_Disp_Switch                   1 bit       ; Obsolete
+$Hot_Plug_DVO                             1 bit
+SKIP                                      1 bit
+$Drv_Int15_hook                           1 bit
+$DVD_Sprite_Clone                         1 bit       ; Obsolete
+$Use_110h_for_LFP                         1 bit
+ALIGN
+
+$Driver_Boot_Mode_X                       2 bytes     ; Obsolete
+$Driver_Boot_Mode_Y                       2 bytes     ; Obsolete
+$Driver_Boot_Mode_BPP                     1 byte      ; Obsolete
+$Driver_Boot_Mode_RR                      1 byte      ; Obsolete
+
+; bmp_Ext_Driver_Bits_1
+$Enable_LFP_Primary                       1 bit       ; Obsolete
+$GTF_Mode_Pruning                         1 bit       ; Obsolete
+SKIP                                      4 bits
+$Sprite_Display_Assign                    1 bit       ; Sprite Display Assignment for when Overlay is Active in Clone Mode
+$CUI_Maintain_Aspect                      1 bit       ; Display "Maintain Aspect Ratio" via CUI
+$Preserve_Aspect_Ratio                    1 bit       ; Preserve Aspect Ratio
+$SDVO_Device_Power_Down                   1 bit       ; Obsolete
+SKIP                                      1 bit       ; Obsolete: Was used for CRT hot plug
+SKIP                                      2 bits      ; Obsolete: Was used for LVDS configuration
+SKIP                                      1 bit       ; Hot plug TV enable/disable
+SKIP                                      2 bits      ; Integrated HDMI Configuration
+ALIGN
+
+; bmp_Driver_Flags_1
+$CUIHotK_Static_Display                   1 bit
+$Embedded_Platform                        1 bit
+$Disable_DisplayEnum                      1 bit       ; Used in RCR 2262110
+SKIP                                      5 bits
+ALIGN
+
+$Legacy_Monitor_Max_X                     2 bytes
+$Legacy_Monitor_Max_Y                     2 bytes
+$Legacy_Monitor_Max_RR                    1 bytes
+
+; bmp_Ext2_Driver_Bits
+$Enable_Int_Src_Term                      1 bit       ; Enable Internal Source Termination for HDMI
+SKIP                                      7 bits      ; Reserved
+ALIGN
+
+$VBT_Customization_Version                1 byte      ; Customization VBT version number
+
+; bmp_Driver_Feature_Flags
+$PM_RMPM_Enable                           1 bit       ; Intel Rapid Memory Power Management (RMPM) Enable/Disable Flag.
+$PM_S2DDT_Enable                          1 bit       ; Intel Smart 2D Display Technology (S2DDT) Enable/Disable Flag.
+SKIP                                      1 bit       ; Obsolete.
+$PM_BLC_Enable                            1 bit       ; Backlight Control (BLC) Enable/Disable Flag.
+SKIP                                      1 bit       ; Obsolete.
+SKIP                                      1 bit       ; Obsolete.
+$PM_RS_Enable                             1 bit       ; Graphics Render Standby (RS) Enable/Disable Flag.
+$PM_GPMT_Enable                           1 bit       ; Obsolete
+$PM_Turbo_Enable                          1 bit       ; Intel Turbo Boost Technology Enable/Disable Flag.
+SKIP                                      1 bit       ; Obsolete.
+$Inter_Pixel_Storage                      1 bit       ; Hidden feature.
+$Dynamic_FPS_Enable                       1 bit       ; Dynamic Frames per second(DFPS) feature Enable/Disable Flag.
+SKIP                                      1 bit       ; Obsolete.
+SKIP                                      1 bit       ; Obsolete.
+$HPD_Wake                                 1 bit       ; HPD events routing to display driver when system is in S0ix/DC9, enable/disable
+$PC_Fields_Enable                         1 bit       ; PC Feature field's validity Flag.
+ALIGN
+
+;==============================================================================
+; Block 13 - Driver Persistence Algorithm
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; Skip block ID and size
+
+SKIP                                      3 bytes     ; Skip block data since it is obsolete.
+
+;==============================================================================
+; Block 17 - Test Feature
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; Skip block ID and size
+
+SKIP                                      8 bytes     ; Skip block data
+
+;==============================================================================
+; Block 18 - Driver Rotation Configuration
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; Skip block ID and size
+
+$Rot_Enable                               1 bit       ; Rotation Enable bit
+SKIP                                      7 bits
+SKIP                                      11 bytes    ; Reserved
+
+;==============================================================================
+; Block 20 - OEM Customizable Modes
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; Skip ID
+
+SKIP                                      2 bytes     ; Table Row/Size Data
+
+$OEM_Mode_Flags1                          1 byte
+$OEM_Display_Flags1                       1 byte
+$OEM_Mode_X1                              2 bytes
+$OEM_Mode_Y1                              2 bytes
+$OEM_Mode_Color1                          1 byte
+$OEM_Mode_RRate1                          1 byte
+$OEM_Mode_DTD1                            18 bytes
+
+$OEM_Mode_Flags2                          1 byte
+$OEM_Display_Flags2                       1 byte
+$OEM_Mode_X2                              2 bytes
+$OEM_Mode_Y2                              2 bytes
+$OEM_Mode_Color2                          1 byte
+$OEM_Mode_RRate2                          1 byte
+$OEM_Mode_DTD2                            18 bytes
+
+$OEM_Mode_Flags3                          1 byte
+$OEM_Display_Flags3                       1 byte
+$OEM_Mode_X3                              2 bytes
+$OEM_Mode_Y3                              2 bytes
+$OEM_Mode_Color3                          1 byte
+$OEM_Mode_RRate3                          1 byte
+$OEM_Mode_DTD3                            18 bytes
+
+$OEM_Mode_Flags4                          1 byte
+$OEM_Display_Flags4                       1 byte
+$OEM_Mode_X4                              2 bytes
+$OEM_Mode_Y4                              2 bytes
+$OEM_Mode_Color4                          1 byte
+$OEM_Mode_RRate4                          1 byte
+$OEM_Mode_DTD4                            18 bytes
+
+$OEM_Mode_Flags5                          1 byte
+$OEM_Display_Flags5                       1 byte
+$OEM_Mode_X5                              2 bytes
+$OEM_Mode_Y5                              2 bytes
+$OEM_Mode_Color5                          1 byte
+$OEM_Mode_RRate5                          1 byte
+$OEM_Mode_DTD5                            18 bytes
+
+$OEM_Mode_Flags6                          1 byte
+$OEM_Display_Flags6                       1 byte
+$OEM_Mode_X6                              2 bytes
+$OEM_Mode_Y6                              2 bytes
+$OEM_Mode_Color6                          1 byte
+$OEM_Mode_RRate6                          1 byte
+$OEM_Mode_DTD6                            18 bytes
+
+;==============================================================================
+; Block 26 - TV features
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; Skip ID and size
+
+$Under_Over_Scan_Via_YPrPb                2 bits      ; Obsolete
+SKIP                                      10 bits
+$Under_Over_Scan_Via_DVI                  2 bits      ; Obsolete
+$Add_Overscan_Mode                        1 bit       ; Obsolete
+$D_Connector                              1 bit       ; Obsolete
+ALIGN
+
+;==============================================================================
+; Block 27 - eDP Power Sequencing
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; Skip block ID and size
+
+; Panel #01 Power Sequencing
+$eDP_Vcc_To_Hpd_Delay_01                  2 bytes
+$eDP_DataOn_To_BkltEnable_Delay_01        2 bytes
+$eDP_BkltDisable_To_DataOff_Delay_01      2 bytes
+$eDP_DataOff_To_PowerOff_Delay_01         2 bytes
+$eDP_PowerCycle_Delay_01                  2 bytes
+
+; Panel #02 Power Sequencing
+$eDP_Vcc_To_Hpd_Delay_02                  2 bytes
+$eDP_DataOn_To_BkltEnable_Delay_02        2 bytes
+$eDP_BkltDisable_To_DataOff_Delay_02      2 bytes
+$eDP_DataOff_To_PowerOff_Delay_02         2 bytes
+$eDP_PowerCycle_Delay_02                  2 bytes
+
+; Panel #03 Power Sequencing
+$eDP_Vcc_To_Hpd_Delay_03                  2 bytes
+$eDP_DataOn_To_BkltEnable_Delay_03        2 bytes
+$eDP_BkltDisable_To_DataOff_Delay_03      2 bytes
+$eDP_DataOff_To_PowerOff_Delay_03         2 bytes
+$eDP_PowerCycle_Delay_03                  2 bytes
+
+; Panel #04 Power Sequencing
+$eDP_Vcc_To_Hpd_Delay_04                  2 bytes
+$eDP_DataOn_To_BkltEnable_Delay_04        2 bytes
+$eDP_BkltDisable_To_DataOff_Delay_04      2 bytes
+$eDP_DataOff_To_PowerOff_Delay_04         2 bytes
+$eDP_PowerCycle_Delay_04                  2 bytes
+
+; Panel #05 Power Sequencing
+$eDP_Vcc_To_Hpd_Delay_05                  2 bytes
+$eDP_DataOn_To_BkltEnable_Delay_05        2 bytes
+$eDP_BkltDisable_To_DataOff_Delay_05      2 bytes
+$eDP_DataOff_To_PowerOff_Delay_05         2 bytes
+$eDP_PowerCycle_Delay_05                  2 bytes
+
+; Panel #06 Power Sequencing
+$eDP_Vcc_To_Hpd_Delay_06                  2 bytes
+$eDP_DataOn_To_BkltEnable_Delay_06        2 bytes
+$eDP_BkltDisable_To_DataOff_Delay_06      2 bytes
+$eDP_DataOff_To_PowerOff_Delay_06         2 bytes
+$eDP_PowerCycle_Delay_06                  2 bytes
+
+; Panel #07 Power Sequencing
+$eDP_Vcc_To_Hpd_Delay_07                  2 bytes
+$eDP_DataOn_To_BkltEnable_Delay_07        2 bytes
+$eDP_BkltDisable_To_DataOff_Delay_07      2 bytes
+$eDP_DataOff_To_PowerOff_Delay_07         2 bytes
+$eDP_PowerCycle_Delay_07                  2 bytes
+
+; Panel #08 Power Sequencing
+$eDP_Vcc_To_Hpd_Delay_08                  2 bytes
+$eDP_DataOn_To_BkltEnable_Delay_08        2 bytes
+$eDP_BkltDisable_To_DataOff_Delay_08      2 bytes
+$eDP_DataOff_To_PowerOff_Delay_08         2 bytes
+$eDP_PowerCycle_Delay_08                  2 bytes
+
+; Panel #09 Power Sequencing
+$eDP_Vcc_To_Hpd_Delay_09                  2 bytes
+$eDP_DataOn_To_BkltEnable_Delay_09        2 bytes
+$eDP_BkltDisable_To_DataOff_Delay_09      2 bytes
+$eDP_DataOff_To_PowerOff_Delay_09         2 bytes
+$eDP_PowerCycle_Delay_09                  2 bytes
+
+; Panel #10 Power Sequencing
+$eDP_Vcc_To_Hpd_Delay_10                  2 bytes
+$eDP_DataOn_To_BkltEnable_Delay_10        2 bytes
+$eDP_BkltDisable_To_DataOff_Delay_10      2 bytes
+$eDP_DataOff_To_PowerOff_Delay_10         2 bytes
+$eDP_PowerCycle_Delay_10                  2 bytes
+
+; Panel #11 Power Sequencing
+$eDP_Vcc_To_Hpd_Delay_11                  2 bytes
+$eDP_DataOn_To_BkltEnable_Delay_11        2 bytes
+$eDP_BkltDisable_To_DataOff_Delay_11      2 bytes
+$eDP_DataOff_To_PowerOff_Delay_11         2 bytes
+$eDP_PowerCycle_Delay_11                  2 bytes
+
+; Panel #12 Power Sequencing
+$eDP_Vcc_To_Hpd_Delay_12                  2 bytes
+$eDP_DataOn_To_BkltEnable_Delay_12        2 bytes
+$eDP_BkltDisable_To_DataOff_Delay_12      2 bytes
+$eDP_DataOff_To_PowerOff_Delay_12         2 bytes
+$eDP_PowerCycle_Delay_12                  2 bytes
+
+; Panel #13 Power Sequencing
+$eDP_Vcc_To_Hpd_Delay_13                  2 bytes
+$eDP_DataOn_To_BkltEnable_Delay_13        2 bytes
+$eDP_BkltDisable_To_DataOff_Delay_13      2 bytes
+$eDP_DataOff_To_PowerOff_Delay_13         2 bytes
+$eDP_PowerCycle_Delay_13                  2 bytes
+
+; Panel #14 Power Sequencing
+$eDP_Vcc_To_Hpd_Delay_14                  2 bytes
+$eDP_DataOn_To_BkltEnable_Delay_14        2 bytes
+$eDP_BkltDisable_To_DataOff_Delay_14      2 bytes
+$eDP_DataOff_To_PowerOff_Delay_14         2 bytes
+$eDP_PowerCycle_Delay_14                  2 bytes
+
+; Panel #15 Power Sequencing
+$eDP_Vcc_To_Hpd_Delay_15                  2 bytes
+$eDP_DataOn_To_BkltEnable_Delay_15        2 bytes
+$eDP_BkltDisable_To_DataOff_Delay_15      2 bytes
+$eDP_DataOff_To_PowerOff_Delay_15         2 bytes
+$eDP_PowerCycle_Delay_15                  2 bytes
+
+; Panel #16 Power Sequencing
+$eDP_Vcc_To_Hpd_Delay_16                  2 bytes
+$eDP_DataOn_To_BkltEnable_Delay_16        2 bytes
+$eDP_BkltDisable_To_DataOff_Delay_16      2 bytes
+$eDP_DataOff_To_PowerOff_Delay_16         2 bytes
+$eDP_PowerCycle_Delay_16                  2 bytes
+
+$eDP_Panel_Color_Depth_01                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
+$eDP_Panel_Color_Depth_02                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
+$eDP_Panel_Color_Depth_03                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
+$eDP_Panel_Color_Depth_04                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
+$eDP_Panel_Color_Depth_05                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
+$eDP_Panel_Color_Depth_06                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
+$eDP_Panel_Color_Depth_07                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
+$eDP_Panel_Color_Depth_08                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
+$eDP_Panel_Color_Depth_09                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
+$eDP_Panel_Color_Depth_10                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
+$eDP_Panel_Color_Depth_11                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
+$eDP_Panel_Color_Depth_12                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
+$eDP_Panel_Color_Depth_13                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
+$eDP_Panel_Color_Depth_14                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
+$eDP_Panel_Color_Depth_15                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
+$eDP_Panel_Color_Depth_16                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
+
+SKIP                                      4 bits      ; Obsolete. Panel #01 Link Data Rate
+$eDP_Link_LaneCount_01                    4 bits      ; Panel #01 Link Lane Count
+$eDP_Link_PreEmp_01                       4 bits      ; Panel #01 Link Pre-emphasis
+$eDP_Link_Vswing_01                       4 bits      ; Panel #01 Link Voltage Swing
+
+SKIP                                      4 bits      ; Obsolete. Panel #02 Link Data Rate
+$eDP_Link_LaneCount_02                    4 bits      ; Panel #02 Link Lane Count
+$eDP_Link_PreEmp_02                       4 bits      ; Panel #02 Link Pre-emphasis
+$eDP_Link_Vswing_02                       4 bits      ; Panel #02 Link Voltage Swing
+
+SKIP                                      4 bits      ; Obsolete. Panel #03 Link Data Rate
+$eDP_Link_LaneCount_03                    4 bits      ; Panel #03 Link Lane Count
+$eDP_Link_PreEmp_03                       4 bits      ; Panel #03 Link Pre-emphasis
+$eDP_Link_Vswing_03                       4 bits      ; Panel #03 Link Voltage Swing
+
+SKIP                                      4 bits      ; Obsolete. Panel #04 Link Data Rate
+$eDP_Link_LaneCount_04                    4 bits      ; Panel #04 Link Lane Count
+$eDP_Link_PreEmp_04                       4 bits      ; Panel #04 Link Pre-emphasis
+$eDP_Link_Vswing_04                       4 bits      ; Panel #04 Link Voltage Swing
+
+SKIP                                      4 bits      ; Obsolete. Panel #05 Link Data Rate
+$eDP_Link_LaneCount_05                    4 bits      ; Panel #05 Link Lane Count
+$eDP_Link_PreEmp_05                       4 bits      ; Panel #05 Link Pre-emphasis
+$eDP_Link_Vswing_05                       4 bits      ; Panel #05 Link Voltage Swing
+
+SKIP                                      4 bits      ; Obsolete. Panel #06 Link Data Rate
+$eDP_Link_LaneCount_06                    4 bits      ; Panel #06 Link Lane Count
+$eDP_Link_PreEmp_06                       4 bits      ; Panel #06 Link Pre-emphasis
+$eDP_Link_Vswing_06                       4 bits      ; Panel #06 Link Voltage Swing
+
+SKIP                                      4 bits      ; Obsolete. Panel #07 Link Data Rate
+$eDP_Link_LaneCount_07                    4 bits      ; Panel #07 Link Lane Count
+$eDP_Link_PreEmp_07                       4 bits      ; Panel #07 Link Pre-emphasis
+$eDP_Link_Vswing_07                       4 bits      ; Panel #07 Link Voltage Swing
+
+SKIP                                      4 bits      ; Obsolete. Panel #08 Link Data Rate
+$eDP_Link_LaneCount_08                    4 bits      ; Panel #08 Link Lane Count
+$eDP_Link_PreEmp_08                       4 bits      ; Panel #08 Link Pre-emphasis
+$eDP_Link_Vswing_08                       4 bits      ; Panel #08 Link Voltage Swing
+
+SKIP                                      4 bits      ; Obsolete. Panel #09 Link Data Rate
+$eDP_Link_LaneCount_09                    4 bits      ; Panel #09 Link Lane Count
+$eDP_Link_PreEmp_09                       4 bits      ; Panel #09 Link Pre-emphasis
+$eDP_Link_Vswing_09                       4 bits      ; Panel #09 Link Voltage Swing
+
+SKIP                                      4 bits      ; Obsolete. Panel #10 Link Data Rate
+$eDP_Link_LaneCount_10                    4 bits      ; Panel #10 Link Lane Count
+$eDP_Link_PreEmp_10                       4 bits      ; Panel #10 Link Pre-emphasis
+$eDP_Link_Vswing_10                       4 bits      ; Panel #10 Link Voltage Swing
+
+SKIP                                      4 bits      ; Obsolete. Panel #11 Link Data Rate
+$eDP_Link_LaneCount_11                    4 bits      ; Panel #11 Link Lane Count
+$eDP_Link_PreEmp_11                       4 bits      ; Panel #11 Link Pre-emphasis
+$eDP_Link_Vswing_11                       4 bits      ; Panel #11 Link Voltage Swing
+
+SKIP                                      4 bits      ; Obsolete. Panel #12 Link Data Rate
+$eDP_Link_LaneCount_12                    4 bits      ; Panel #12 Link Lane Count
+$eDP_Link_PreEmp_12                       4 bits      ; Panel #12 Link Pre-emphasis
+$eDP_Link_Vswing_12                       4 bits      ; Panel #12 Link Voltage Swing
+
+SKIP                                      4 bits      ; Obsolete. Panel #13 Link Data Rate
+$eDP_Link_LaneCount_13                    4 bits      ; Panel #13 Link Lane Count
+$eDP_Link_PreEmp_13                       4 bits      ; Panel #13 Link Pre-emphasis
+$eDP_Link_Vswing_13                       4 bits      ; Panel #13 Link Voltage Swing
+
+SKIP                                      4 bits      ; Obsolete. Panel #14 Link Data Rate
+$eDP_Link_LaneCount_14                    4 bits      ; Panel #14 Link Lane Count
+$eDP_Link_PreEmp_14                       4 bits      ; Panel #14 Link Pre-emphasis
+$eDP_Link_Vswing_14                       4 bits      ; Panel #14 Link Voltage Swing
+
+SKIP                                      4 bits      ; Obsolete. Panel #15 Link Data Rate
+$eDP_Link_LaneCount_15                    4 bits      ; Panel #15 Link Lane Count
+$eDP_Link_PreEmp_15                       4 bits      ; Panel #15 Link Pre-emphasis
+$eDP_Link_Vswing_15                       4 bits      ; Panel #15 Link Voltage Swing
+
+SKIP                                      4 bits      ; Obsolete. Panel #16 Link Data Rate
+$eDP_Link_LaneCount_16                    4 bits      ; Panel #16 Link Lane Count
+$eDP_Link_PreEmp_16                       4 bits      ; Panel #16 Link Pre-emphasis
+$eDP_Link_Vswing_16                       4 bits      ; Panel #16 Link Voltage Swing
+
+SKIP                                      4 bytes     ; Obsolete: Was used for DRRS MSA Delay.
+
+SKIP                                      2 bytes     ; Obsolete: S3D enable disable VBT bit for 16 panels.
+
+$eDP_T3_Optimization_01                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #01
+$eDP_T3_Optimization_02                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #02
+$eDP_T3_Optimization_03                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #03
+$eDP_T3_Optimization_04                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #04
+$eDP_T3_Optimization_05                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #05
+$eDP_T3_Optimization_06                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #06
+$eDP_T3_Optimization_07                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #07
+$eDP_T3_Optimization_08                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #08
+$eDP_T3_Optimization_09                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #09
+$eDP_T3_Optimization_10                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #10
+$eDP_T3_Optimization_11                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #11
+$eDP_T3_Optimization_12                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #12
+$eDP_T3_Optimization_13                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #13
+$eDP_T3_Optimization_14                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #14
+$eDP_T3_Optimization_15                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #15
+$eDP_T3_Optimization_16                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #16
+
+$eDP_VSwingPreEmph_01                     4 bits      ; eDp selects VSwing Preemph table for panel #01
+$eDP_VSwingPreEmph_02                     4 bits      ; eDp selects VSwing Preemph table for panel #02
+$eDP_VSwingPreEmph_03                     4 bits      ; eDp selects VSwing Preemph table for panel #03
+$eDP_VSwingPreEmph_04                     4 bits      ; eDp selects VSwing Preemph table for panel #04
+$eDP_VSwingPreEmph_05                     4 bits      ; eDp selects VSwing Preemph table for panel #05
+$eDP_VSwingPreEmph_06                     4 bits      ; eDp selects VSwing Preemph table for panel #06
+$eDP_VSwingPreEmph_07                     4 bits      ; eDp selects VSwing Preemph table for panel #07
+$eDP_VSwingPreEmph_08                     4 bits      ; eDp selects VSwing Preemph table for panel #08
+$eDP_VSwingPreEmph_09                     4 bits      ; eDp selects VSwing Preemph table for panel #09
+$eDP_VSwingPreEmph_10                     4 bits      ; eDp selects VSwing Preemph table for panel #10
+$eDP_VSwingPreEmph_11                     4 bits      ; eDp selects VSwing Preemph table for panel #11
+$eDP_VSwingPreEmph_12                     4 bits      ; eDp selects VSwing Preemph table for panel #12
+$eDP_VSwingPreEmph_13                     4 bits      ; eDp selects VSwing Preemph table for panel #13
+$eDP_VSwingPreEmph_14                     4 bits      ; eDp selects VSwing Preemph table for panel #14
+$eDP_VSwingPreEmph_15                     4 bits      ; eDp selects VSwing Preemph table for panel #15
+$eDP_VSwingPreEmph_16                     4 bits      ; eDp selects VSwing Preemph table for panel #16
+
+$eDP_Fast_Link_Training_Supported_01      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #01
+$eDP_Fast_Link_Training_Supported_02      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #02
+$eDP_Fast_Link_Training_Supported_03      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #03
+$eDP_Fast_Link_Training_Supported_04      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #04
+$eDP_Fast_Link_Training_Supported_05      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #05
+$eDP_Fast_Link_Training_Supported_06      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #06
+$eDP_Fast_Link_Training_Supported_07      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #07
+$eDP_Fast_Link_Training_Supported_08      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #08
+$eDP_Fast_Link_Training_Supported_09      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #09
+$eDP_Fast_Link_Training_Supported_10      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #10
+$eDP_Fast_Link_Training_Supported_11      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #11
+$eDP_Fast_Link_Training_Supported_12      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #12
+$eDP_Fast_Link_Training_Supported_13      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #13
+$eDP_Fast_Link_Training_Supported_14      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #14
+$eDP_Fast_Link_Training_Supported_15      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #15
+$eDP_Fast_Link_Training_Supported_16      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #16
+
+SKIP                                      2 bytes     ; Skip Enable Power State at DPCD 600h
+
+$eDP_PwmOn_To_Bklt_Enable_Delay_01        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #01
+$eDP_Bklt_Disable_To_PwmOff_Delay_01      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #01
+
+$eDP_PwmOn_To_Bklt_Enable_Delay_02        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #02
+$eDP_Bklt_Disable_To_PwmOff_Delay_02      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #02
+
+$eDP_PwmOn_To_Bklt_Enable_Delay_03        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #03
+$eDP_Bklt_Disable_To_PwmOff_Delay_03      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #03
+
+$eDP_PwmOn_To_Bklt_Enable_Delay_04        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #04
+$eDP_Bklt_Disable_To_PwmOff_Delay_04      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #04
+
+$eDP_PwmOn_To_Bklt_Enable_Delay_05        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #05
+$eDP_Bklt_Disable_To_PwmOff_Delay_05      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #05
+
+$eDP_PwmOn_To_Bklt_Enable_Delay_06        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #06
+$eDP_Bklt_Disable_To_PwmOff_Delay_06      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #06
+
+$eDP_PwmOn_To_Bklt_Enable_Delay_07        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #07
+$eDP_Bklt_Disable_To_PwmOff_Delay_07      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #07
+
+$eDP_PwmOn_To_Bklt_Enable_Delay_08        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #08
+$eDP_Bklt_Disable_To_PwmOff_Delay_08      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #08
+
+$eDP_PwmOn_To_Bklt_Enable_Delay_09        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #09
+$eDP_Bklt_Disable_To_PwmOff_Delay_09      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #09
+
+$eDP_PwmOn_To_Bklt_Enable_Delay_10        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #10
+$eDP_Bklt_Disable_To_PwmOff_Delay_10      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #10
+
+$eDP_PwmOn_To_Bklt_Enable_Delay_11        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #11
+$eDP_Bklt_Disable_To_PwmOff_Delay_11      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #11
+
+$eDP_PwmOn_To_Bklt_Enable_Delay_12        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #12
+$eDP_Bklt_Disable_To_PwmOff_Delay_12      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #12
+
+$eDP_PwmOn_To_Bklt_Enable_Delay_13        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #13
+$eDP_Bklt_Disable_To_PwmOff_Delay_13      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #13
+
+$eDP_PwmOn_To_Bklt_Enable_Delay_14        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #14
+$eDP_Bklt_Disable_To_PwmOff_Delay_14      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #14
+
+$eDP_PwmOn_To_Bklt_Enable_Delay_15        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #15
+$eDP_Bklt_Disable_To_PwmOff_Delay_15      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #15
+
+$eDP_PwmOn_To_Bklt_Enable_Delay_16        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #16
+$eDP_Bklt_Disable_To_PwmOff_Delay_16      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #16
+
+$eDP_Full_Link_Training_Params_Enable_01  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #01
+$eDP_Full_Link_Training_Params_Enable_02  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #02
+$eDP_Full_Link_Training_Params_Enable_03  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #03
+$eDP_Full_Link_Training_Params_Enable_04  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #04
+$eDP_Full_Link_Training_Params_Enable_05  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #05
+$eDP_Full_Link_Training_Params_Enable_06  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #06
+$eDP_Full_Link_Training_Params_Enable_07  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #07
+$eDP_Full_Link_Training_Params_Enable_08  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #08
+$eDP_Full_Link_Training_Params_Enable_09  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #09
+$eDP_Full_Link_Training_Params_Enable_10  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #10
+$eDP_Full_Link_Training_Params_Enable_11  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #11
+$eDP_Full_Link_Training_Params_Enable_12  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #12
+$eDP_Full_Link_Training_Params_Enable_13  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #13
+$eDP_Full_Link_Training_Params_Enable_14  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #14
+$eDP_Full_Link_Training_Params_Enable_15  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #15
+$eDP_Full_Link_Training_Params_Enable_16  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #16
+
+$eDP_Full_Link_Train_PreEmp_01            4 bits      ; Panel #01 Full link training initial Pre-emphasis
+$eDP_Full_Link_Train_Vswing_01            4 bits      ; Panel #01 Full link training initial Voltage Swing
+
+$eDP_Full_Link_Train_PreEmp_02            4 bits      ; Panel #02 Full link training initial Pre-emphasis
+$eDP_Full_Link_Train_Vswing_02            4 bits      ; Panel #02 Full link training initial Voltage Swing
+
+$eDP_Full_Link_Train_PreEmp_03            4 bits      ; Panel #03 Full link training initial Pre-emphasis
+$eDP_Full_Link_Train_Vswing_03            4 bits      ; Panel #03 Full link training initial Voltage Swing
+
+$eDP_Full_Link_Train_PreEmp_04            4 bits      ; Panel #04 Full link training initial Pre-emphasis
+$eDP_Full_Link_Train_Vswing_04            4 bits      ; Panel #04 Full link training initial Voltage Swing
+
+$eDP_Full_Link_Train_PreEmp_05            4 bits      ; Panel #05 Full link training initial Pre-emphasis
+$eDP_Full_Link_Train_Vswing_05            4 bits      ; Panel #05 Full link training initial Voltage Swing
+
+$eDP_Full_Link_Train_PreEmp_06            4 bits      ; Panel #06 Full link training initial Pre-emphasis
+$eDP_Full_Link_Train_Vswing_06            4 bits      ; Panel #06 Full link training initial Voltage Swing
+
+$eDP_Full_Link_Train_PreEmp_07            4 bits      ; Panel #07 Full link training initial Pre-emphasis
+$eDP_Full_Link_Train_Vswing_07            4 bits      ; Panel #07 Full link training initial Voltage Swing
+
+$eDP_Full_Link_Train_PreEmp_08            4 bits      ; Panel #08 Full link training initial Pre-emphasis
+$eDP_Full_Link_Train_Vswing_08            4 bits      ; Panel #08 Full link training initial Voltage Swing
+
+$eDP_Full_Link_Train_PreEmp_09            4 bits      ; Panel #09 Full link training initial Pre-emphasis
+$eDP_Full_Link_Train_Vswing_09            4 bits      ; Panel #09 Full link training initial Voltage Swing
+
+$eDP_Full_Link_Train_PreEmp_10            4 bits      ; Panel #10 Full link training initial Pre-emphasis
+$eDP_Full_Link_Train_Vswing_10            4 bits      ; Panel #10 Full link training initial Voltage Swing
+
+$eDP_Full_Link_Train_PreEmp_11            4 bits      ; Panel #11 Full link training initial Pre-emphasis
+$eDP_Full_Link_Train_Vswing_11            4 bits      ; Panel #11 Full link training initial Voltage Swing
+
+$eDP_Full_Link_Train_PreEmp_12            4 bits      ; Panel #12 Full link training initial Pre-emphasis
+$eDP_Full_Link_Train_Vswing_12            4 bits      ; Panel #12 Full link training initial Voltage Swing
+
+$eDP_Full_Link_Train_PreEmp_13            4 bits      ; Panel #13 Full link training initial Pre-emphasis
+$eDP_Full_Link_Train_Vswing_13            4 bits      ; Panel #13 Full link training initial Voltage Swing
+
+$eDP_Full_Link_Train_PreEmp_14            4 bits      ; Panel #14 Full link training initial Pre-emphasis
+$eDP_Full_Link_Train_Vswing_14            4 bits      ; Panel #14 Full link training initial Voltage Swing
+
+$eDP_Full_Link_Train_PreEmp_15            4 bits      ; Panel #15 Full link training initial Pre-emphasis
+$eDP_Full_Link_Train_Vswing_15            4 bits      ; Panel #15 Full link training initial Voltage Swing
+
+$eDP_Full_Link_Train_PreEmp_16            4 bits      ; Panel #16 Full link training initial Pre-emphasis
+$eDP_Full_Link_Train_Vswing_16            4 bits      ; Panel #16 Full link training initial Voltage Swing
+
+$eDP_Apical_Display_Ip_Enable_01          1 bit       ; Panel #01 Apical Display IP Enable bit
+$eDP_Apical_Display_Ip_Enable_02          1 bit       ; Panel #02 Apical Display IP Enable bit
+$eDP_Apical_Display_Ip_Enable_03          1 bit       ; Panel #03 Apical Display IP Enable bit
+$eDP_Apical_Display_Ip_Enable_04          1 bit       ; Panel #04 Apical Display IP Enable bit
+$eDP_Apical_Display_Ip_Enable_05          1 bit       ; Panel #05 Apical Display IP Enable bit
+$eDP_Apical_Display_Ip_Enable_06          1 bit       ; Panel #06 Apical Display IP Enable bit
+$eDP_Apical_Display_Ip_Enable_07          1 bit       ; Panel #07 Apical Display IP Enable bit
+$eDP_Apical_Display_Ip_Enable_08          1 bit       ; Panel #08 Apical Display IP Enable bit
+$eDP_Apical_Display_Ip_Enable_09          1 bit       ; Panel #09 Apical Display IP Enable bit
+$eDP_Apical_Display_Ip_Enable_10          1 bit       ; Panel #10 Apical Display IP Enable bit
+$eDP_Apical_Display_Ip_Enable_11          1 bit       ; Panel #11 Apical Display IP Enable bit
+$eDP_Apical_Display_Ip_Enable_12          1 bit       ; Panel #12 Apical Display IP Enable bit
+$eDP_Apical_Display_Ip_Enable_13          1 bit       ; Panel #13 Apical Display IP Enable bit
+$eDP_Apical_Display_Ip_Enable_14          1 bit       ; Panel #14 Apical Display IP Enable bit
+$eDP_Apical_Display_Ip_Enable_15          1 bit       ; Panel #15 Apical Display IP Enable bit
+$eDP_Apical_Display_Ip_Enable_16          1 bit       ; Panel #16 Apical Display IP Enable bit
+
+; Panel #01 Apical Display IP parameters
+$eDP_Panel_Oui_01                         4 bytes     ; Panel #01 Apical specific Panel OUI
+$eDP_Dpcd_Base_Address_01                 4 bytes     ; Panel #01 Apical specific DPCD base address
+$eDP_Dpcd_Irdidix_Control0_01             4 bytes     ; Panel #01 Apical specific DPCD Idridix control 0
+$eDP_Dpcd_Option_Select_01                4 bytes     ; Panel #01 Apical specific DPCD option select
+$eDP_Dpcd_Backlight_01                    4 bytes     ; Panel #01 Apical specific DPCD backlight
+$eDP_Ambient_Light_01                     4 bytes     ; Panel #01 Apical specific Ambient light
+$eDP_Backlight_Scale_01                   4 bytes     ; Panel #01 Apical specific backlight scale value
+
+; Panel #02 Apical Display IP parameters
+$eDP_Panel_Oui_02                         4 bytes     ; Panel #02 Apical specific Panel OUI
+$eDP_Dpcd_Base_Address_02                 4 bytes     ; Panel #02 Apical specific DPCD base address
+$eDP_Dpcd_Irdidix_Control0_02             4 bytes     ; Panel #02 Apical specific DPCD Idridix control 0
+$eDP_Dpcd_Option_Select_02                4 bytes     ; Panel #02 Apical specific DPCD option select
+$eDP_Dpcd_Backlight_02                    4 bytes     ; Panel #02 Apical specific DPCD backlight
+$eDP_Ambient_Light_02                     4 bytes     ; Panel #02 Apical specific Ambient light
+$eDP_Backlight_Scale_02                   4 bytes     ; Panel #02 Apical specific backlight scale value
+
+; Panel #03 Apical Display IP parameters
+$eDP_Panel_Oui_03                         4 bytes     ; Panel #03 Apical specific Panel OUI
+$eDP_Dpcd_Base_Address_03                 4 bytes     ; Panel #03 Apical specific DPCD base address
+$eDP_Dpcd_Irdidix_Control0_03             4 bytes     ; Panel #03 Apical specific DPCD Idridix control 0
+$eDP_Dpcd_Option_Select_03                4 bytes     ; Panel #03 Apical specific DPCD option select
+$eDP_Dpcd_Backlight_03                    4 bytes     ; Panel #03 Apical specific DPCD backlight
+$eDP_Ambient_Light_03                     4 bytes     ; Panel #03 Apical specific Ambient light
+$eDP_Backlight_Scale_03                   4 bytes     ; Panel #03 Apical specific backlight scale value
+
+; Panel #04 Apical Display IP parameters
+$eDP_Panel_Oui_04                         4 bytes     ; Panel #04 Apical specific Panel OUI
+$eDP_Dpcd_Base_Address_04                 4 bytes     ; Panel #04 Apical specific DPCD base address
+$eDP_Dpcd_Irdidix_Control0_04             4 bytes     ; Panel #04 Apical specific DPCD Idridix control 0
+$eDP_Dpcd_Option_Select_04                4 bytes     ; Panel #04 Apical specific DPCD option select
+$eDP_Dpcd_Backlight_04                    4 bytes     ; Panel #04 Apical specific DPCD backlight
+$eDP_Ambient_Light_04                     4 bytes     ; Panel #04 Apical specific Ambient light
+$eDP_Backlight_Scale_04                   4 bytes     ; Panel #04 Apical specific backlight scale value
+
+; Panel #05 Apical Display IP parameters
+$eDP_Panel_Oui_05                         4 bytes     ; Panel #05 Apical specific Panel OUI
+$eDP_Dpcd_Base_Address_05                 4 bytes     ; Panel #05 Apical specific DPCD base address
+$eDP_Dpcd_Irdidix_Control0_05             4 bytes     ; Panel #05 Apical specific DPCD Idridix control 0
+$eDP_Dpcd_Option_Select_05                4 bytes     ; Panel #05 Apical specific DPCD option select
+$eDP_Dpcd_Backlight_05                    4 bytes     ; Panel #05 Apical specific DPCD backlight
+$eDP_Ambient_Light_05                     4 bytes     ; Panel #05 Apical specific Ambient light
+$eDP_Backlight_Scale_05                   4 bytes     ; Panel #05 Apical specific backlight scale value
+
+; Panel #06 Apical Display IP parameters
+$eDP_Panel_Oui_06                         4 bytes     ; Panel #06 Apical specific Panel OUI
+$eDP_Dpcd_Base_Address_06                 4 bytes     ; Panel #06 Apical specific DPCD base address
+$eDP_Dpcd_Irdidix_Control0_06             4 bytes     ; Panel #06 Apical specific DPCD Idridix control 0
+$eDP_Dpcd_Option_Select_06                4 bytes     ; Panel #06 Apical specific DPCD option select
+$eDP_Dpcd_Backlight_06                    4 bytes     ; Panel #06 Apical specific DPCD backlight
+$eDP_Ambient_Light_06                     4 bytes     ; Panel #06 Apical specific Ambient light
+$eDP_Backlight_Scale_06                   4 bytes     ; Panel #06 Apical specific backlight scale value
+
+; Panel #07 Apical Display IP parameters
+$eDP_Panel_Oui_07                         4 bytes     ; Panel #07 Apical specific Panel OUI
+$eDP_Dpcd_Base_Address_07                 4 bytes     ; Panel #07 Apical specific DPCD base address
+$eDP_Dpcd_Irdidix_Control0_07             4 bytes     ; Panel #07 Apical specific DPCD Idridix control 0
+$eDP_Dpcd_Option_Select_07                4 bytes     ; Panel #07 Apical specific DPCD option select
+$eDP_Dpcd_Backlight_07                    4 bytes     ; Panel #07 Apical specific DPCD backlight
+$eDP_Ambient_Light_07                     4 bytes     ; Panel #07 Apical specific Ambient light
+$eDP_Backlight_Scale_07                   4 bytes     ; Panel #07 Apical specific backlight scale value
+
+; Panel #08 Apical Display IP parameters
+$eDP_Panel_Oui_08                         4 bytes     ; Panel #08 Apical specific Panel OUI
+$eDP_Dpcd_Base_Address_08                 4 bytes     ; Panel #08 Apical specific DPCD base address
+$eDP_Dpcd_Irdidix_Control0_08             4 bytes     ; Panel #08 Apical specific DPCD Idridix control 0
+$eDP_Dpcd_Option_Select_08                4 bytes     ; Panel #08 Apical specific DPCD option select
+$eDP_Dpcd_Backlight_08                    4 bytes     ; Panel #08 Apical specific DPCD backlight
+$eDP_Ambient_Light_08                     4 bytes     ; Panel #08 Apical specific Ambient light
+$eDP_Backlight_Scale_08                   4 bytes     ; Panel #08 Apical specific backlight scale value
+
+; Panel #09 Apical Display IP parameters
+$eDP_Panel_Oui_09                         4 bytes     ; Panel #09 Apical specific Panel OUI
+$eDP_Dpcd_Base_Address_09                 4 bytes     ; Panel #09 Apical specific DPCD base address
+$eDP_Dpcd_Irdidix_Control0_09             4 bytes     ; Panel #09 Apical specific DPCD Idridix control 0
+$eDP_Dpcd_Option_Select_09                4 bytes     ; Panel #09 Apical specific DPCD option select
+$eDP_Dpcd_Backlight_09                    4 bytes     ; Panel #09 Apical specific DPCD backlight
+$eDP_Ambient_Light_09                     4 bytes     ; Panel #09 Apical specific Ambient light
+$eDP_Backlight_Scale_09                   4 bytes     ; Panel #09 Apical specific backlight scale value
+
+; Panel #10 Apical Display IP parameters
+$eDP_Panel_Oui_10                         4 bytes     ; Panel #10 Apical specific Panel OUI
+$eDP_Dpcd_Base_Address_10                 4 bytes     ; Panel #10 Apical specific DPCD base address
+$eDP_Dpcd_Irdidix_Control0_10             4 bytes     ; Panel #10 Apical specific DPCD Idridix control 0
+$eDP_Dpcd_Option_Select_10                4 bytes     ; Panel #10 Apical specific DPCD option select
+$eDP_Dpcd_Backlight_10                    4 bytes     ; Panel #10 Apical specific DPCD backlight
+$eDP_Ambient_Light_10                     4 bytes     ; Panel #10 Apical specific Ambient light
+$eDP_Backlight_Scale_10                   4 bytes     ; Panel #10 Apical specific backlight scale value
+
+; Panel #11 Apical Display IP parameters
+$eDP_Panel_Oui_11                         4 bytes     ; Panel #11 Apical specific Panel OUI
+$eDP_Dpcd_Base_Address_11                 4 bytes     ; Panel #11 Apical specific DPCD base address
+$eDP_Dpcd_Irdidix_Control0_11             4 bytes     ; Panel #11 Apical specific DPCD Idridix control 0
+$eDP_Dpcd_Option_Select_11                4 bytes     ; Panel #11 Apical specific DPCD option select
+$eDP_Dpcd_Backlight_11                    4 bytes     ; Panel #11 Apical specific DPCD backlight
+$eDP_Ambient_Light_11                     4 bytes     ; Panel #11 Apical specific Ambient light
+$eDP_Backlight_Scale_11                   4 bytes     ; Panel #11 Apical specific backlight scale value
+
+; Panel #12 Apical Display IP parameters
+$eDP_Panel_Oui_12                         4 bytes     ; Panel #12 Apical specific Panel OUI
+$eDP_Dpcd_Base_Address_12                 4 bytes     ; Panel #12 Apical specific DPCD base address
+$eDP_Dpcd_Irdidix_Control0_12             4 bytes     ; Panel #12 Apical specific DPCD Idridix control 0
+$eDP_Dpcd_Option_Select_12                4 bytes     ; Panel #12 Apical specific DPCD option select
+$eDP_Dpcd_Backlight_12                    4 bytes     ; Panel #12 Apical specific DPCD backlight
+$eDP_Ambient_Light_12                     4 bytes     ; Panel #12 Apical specific Ambient light
+$eDP_Backlight_Scale_12                   4 bytes     ; Panel #12 Apical specific backlight scale value
+
+; Panel #13 Apical Display IP parameters
+$eDP_Panel_Oui_13                         4 bytes     ; Panel #13 Apical specific Panel OUI
+$eDP_Dpcd_Base_Address_13                 4 bytes     ; Panel #13 Apical specific DPCD base address
+$eDP_Dpcd_Irdidix_Control0_13             4 bytes     ; Panel #13 Apical specific DPCD Idridix control 0
+$eDP_Dpcd_Option_Select_13                4 bytes     ; Panel #13 Apical specific DPCD option select
+$eDP_Dpcd_Backlight_13                    4 bytes     ; Panel #13 Apical specific DPCD backlight
+$eDP_Ambient_Light_13                     4 bytes     ; Panel #13 Apical specific Ambient light
+$eDP_Backlight_Scale_13                   4 bytes     ; Panel #13 Apical specific backlight scale value
+
+; Panel #14 Apical Display IP parameters
+$eDP_Panel_Oui_14                         4 bytes     ; Panel #14 Apical specific Panel OUI
+$eDP_Dpcd_Base_Address_14                 4 bytes     ; Panel #14 Apical specific DPCD base address
+$eDP_Dpcd_Irdidix_Control0_14             4 bytes     ; Panel #14 Apical specific DPCD Idridix control 0
+$eDP_Dpcd_Option_Select_14                4 bytes     ; Panel #14 Apical specific DPCD option select
+$eDP_Dpcd_Backlight_14                    4 bytes     ; Panel #14 Apical specific DPCD backlight
+$eDP_Ambient_Light_14                     4 bytes     ; Panel #14 Apical specific Ambient light
+$eDP_Backlight_Scale_14                   4 bytes     ; Panel #14 Apical specific backlight scale value
+
+; Panel #15 Apical Display IP parameters
+$eDP_Panel_Oui_15                         4 bytes     ; Panel #15 Apical specific Panel OUI
+$eDP_Dpcd_Base_Address_15                 4 bytes     ; Panel #15 Apical specific DPCD base address
+$eDP_Dpcd_Irdidix_Control0_15             4 bytes     ; Panel #15 Apical specific DPCD Idridix control 0
+$eDP_Dpcd_Option_Select_15                4 bytes     ; Panel #15 Apical specific DPCD option select
+$eDP_Dpcd_Backlight_15                    4 bytes     ; Panel #15 Apical specific DPCD backlight
+$eDP_Ambient_Light_15                     4 bytes     ; Panel #15 Apical specific Ambient light
+$eDP_Backlight_Scale_15                   4 bytes     ; Panel #15 Apical specific backlight scale value
+
+; Panel #16 Apical Display IP parameters
+$eDP_Panel_Oui_16                         4 bytes     ; Panel #16 Apical specific Panel OUI
+$eDP_Dpcd_Base_Address_16                 4 bytes     ; Panel #16 Apical specific DPCD base address
+$eDP_Dpcd_Irdidix_Control0_16             4 bytes     ; Panel #16 Apical specific DPCD Idridix control 0
+$eDP_Dpcd_Option_Select_16                4 bytes     ; Panel #16 Apical specific DPCD option select
+$eDP_Dpcd_Backlight_16                    4 bytes     ; Panel #16 Apical specific DPCD backlight
+$eDP_Ambient_Light_16                     4 bytes     ; Panel #16 Apical specific Ambient light
+$eDP_Backlight_Scale_16                   4 bytes     ; Panel #16 Apical specific backlight scale value
+
+$eDP_Fast_Link_Training_Data_Rate_01      2 bytes     ; Panel #01 Data Rate for Fast Link Training in unit of 200KHz
+$eDP_Fast_Link_Training_Data_Rate_02      2 bytes     ; Panel #02 Data Rate for Fast Link Training in unit of 200KHz
+$eDP_Fast_Link_Training_Data_Rate_03      2 bytes     ; Panel #03 Data Rate for Fast Link Training in unit of 200KHz
+$eDP_Fast_Link_Training_Data_Rate_04      2 bytes     ; Panel #04 Data Rate for Fast Link Training in unit of 200KHz
+$eDP_Fast_Link_Training_Data_Rate_05      2 bytes     ; Panel #05 Data Rate for Fast Link Training in unit of 200KHz
+$eDP_Fast_Link_Training_Data_Rate_06      2 bytes     ; Panel #06 Data Rate for Fast Link Training in unit of 200KHz
+$eDP_Fast_Link_Training_Data_Rate_07      2 bytes     ; Panel #07 Data Rate for Fast Link Training in unit of 200KHz
+$eDP_Fast_Link_Training_Data_Rate_08      2 bytes     ; Panel #08 Data Rate for Fast Link Training in unit of 200KHz
+$eDP_Fast_Link_Training_Data_Rate_09      2 bytes     ; Panel #09 Data Rate for Fast Link Training in unit of 200KHz
+$eDP_Fast_Link_Training_Data_Rate_10      2 bytes     ; Panel #10 Data Rate for Fast Link Training in unit of 200KHz
+$eDP_Fast_Link_Training_Data_Rate_11      2 bytes     ; Panel #11 Data Rate for Fast Link Training in unit of 200KHz
+$eDP_Fast_Link_Training_Data_Rate_12      2 bytes     ; Panel #12 Data Rate for Fast Link Training in unit of 200KHz
+$eDP_Fast_Link_Training_Data_Rate_13      2 bytes     ; Panel #13 Data Rate for Fast Link Training in unit of 200KHz
+$eDP_Fast_Link_Training_Data_Rate_14      2 bytes     ; Panel #14 Data Rate for Fast Link Training in unit of 200KHz
+$eDP_Fast_Link_Training_Data_Rate_15      2 bytes     ; Panel #15 Data Rate for Fast Link Training in unit of 200KHz
+$eDP_Fast_Link_Training_Data_Rate_16      2 bytes     ; Panel #16 Data Rate for Fast Link Training in unit of 200KHz
+
+;==============================================================================
+; Block 28 - EDID-less EFP support - Panel data
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; Skip block ID and size
+$EFP1_DTD                                 18 bytes    ; DTD for Device 1 DP/HDMI/DVI panel
+$EFP2_DTD                                 18 bytes    ; DTD for Device 2 DP/HDMI/DVI panel
+$EFP3_DTD                                 18 bytes    ; DTD for Device 3 DP/HDMI/DVI panel
+$EFP4_DTD                                 18 bytes    ; DTD for Device 4 DP/HDMI/DVI panel
+
+;==============================================================================
+; Block 31 - VBIOS/Driver Toggle list for CFL
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; Skip block ID and size
+SKIP                                      92 bytes    ; Skip Toggle lists
+ALIGN
+
+;==============================================================================
+; Block 32 - Display Removal Configurations for CFL
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; Skip block ID and size
+SKIP                                      2 bytes     ; Table Row/Size Data
+SKIP                                      30 bytes    ; Skip Removed displays table
+
+;==============================================================================
+; Block 40 - Start of LVDS BMP Structure Definition
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; Skip block ID and size
+
+$bmp_Panel_type                           1 byte      ; Flat panel type
+SKIP                                      1 byte      ; Obsolete
+SKIP                                      6 bits      ; Skip bits 0:5 of bmp_LVDS_Capabilities
+$bmp_Panel_EDID                           1 bit       ; LVDS panel EDID enable/disable bit
+SKIP                                      1 bit       ; Skip bit 7 of bmp_LVDS_Capabilities
+SKIP                                      1 byte      ; Skip bits 8:15 of bmp_LVDS_Capabilities
+
+; INT_LVDS_Panel_Channel_Bits
+SKIP                                      4 bytes     ; Obsolete: Was used for LVDS panel channel type.
+
+; LVDS Spread Spectrum Clock
+; Enable/Disable SSC
+$Enable_SSC01                             1 bit       ; Panel #01, 0=No, 1=Yes
+$Enable_SSC02                             1 bit       ; Panel #02, 0=No, 1=Yes
+$Enable_SSC03                             1 bit       ; Panel #03, 0=No, 1=Yes
+$Enable_SSC04                             1 bit       ; Panel #04, 0=No, 1=Yes
+$Enable_SSC05                             1 bit       ; Panel #05, 0=No, 1=Yes
+$Enable_SSC06                             1 bit       ; Panel #06, 0=No, 1=Yes
+$Enable_SSC07                             1 bit       ; Panel #07, 0=No, 1=Yes
+$Enable_SSC08                             1 bit       ; Panel #08, 0=No, 1=Yes
+$Enable_SSC09                             1 bit       ; Panel #09, 0=No, 1=Yes
+$Enable_SSC10                             1 bit       ; Panel #10, 0=No 1=Yes
+$Enable_SSC11                             1 bit       ; Panel #11, 0=No, 1=Yes
+$Enable_SSC12                             1 bit       ; Panel #12, 0=No, 1=Yes
+$Enable_SSC13                             1 bit       ; Panel #13, 0=No, 1=Yes
+$Enable_SSC14                             1 bit       ; Panel #14, 0=No, 1=Yes
+$Enable_SSC15                             1 bit       ; Panel #15, 0=No, 1=Yes
+$Enable_SSC16                             1 bit       ; Panel #16, 0=No, 1=Yes
+
+SKIP                                      2 bytes     ; Obsolete: Was used for SSC frequency for LVDS.
+
+SKIP                                      2 bytes     ; Obsolete: Was used for Disable SSC in DDT mode.
+
+SKIP                                      2 bytes     ; Obsolete: Was used for panel color depth for LVDS panels.
+
+$DPS_Panel_Type_01                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
+$DPS_Panel_Type_02                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
+$DPS_Panel_Type_03                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
+$DPS_Panel_Type_04                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
+$DPS_Panel_Type_05                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
+$DPS_Panel_Type_06                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
+$DPS_Panel_Type_07                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
+$DPS_Panel_Type_08                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
+$DPS_Panel_Type_09                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
+$DPS_Panel_Type_10                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
+$DPS_Panel_Type_11                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
+$DPS_Panel_Type_12                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
+$DPS_Panel_Type_13                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
+$DPS_Panel_Type_14                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
+$DPS_Panel_Type_15                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
+$DPS_Panel_Type_16                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
+
+$Blt_Control_01                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
+$Blt_Control_02                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
+$Blt_Control_03                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
+$Blt_Control_04                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
+$Blt_Control_05                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
+$Blt_Control_06                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
+$Blt_Control_07                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
+$Blt_Control_08                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
+$Blt_Control_09                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
+$Blt_Control_10                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
+$Blt_Control_11                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
+$Blt_Control_12                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
+$Blt_Control_13                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
+$Blt_Control_14                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
+$Blt_Control_15                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
+$Blt_Control_16                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
+
+$LcdVcc_On_During_S0_State_01             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #01
+$LcdVcc_On_During_S0_State_02             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #02
+$LcdVcc_On_During_S0_State_03             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #03
+$LcdVcc_On_During_S0_State_04             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #04
+$LcdVcc_On_During_S0_State_05             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #05
+$LcdVcc_On_During_S0_State_06             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #06
+$LcdVcc_On_During_S0_State_07             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #07
+$LcdVcc_On_During_S0_State_08             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #08
+$LcdVcc_On_During_S0_State_09             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #09
+$LcdVcc_On_During_S0_State_10             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #10
+$LcdVcc_On_During_S0_State_11             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #11
+$LcdVcc_On_During_S0_State_12             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #12
+$LcdVcc_On_During_S0_State_13             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #13
+$LcdVcc_On_During_S0_State_14             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #14
+$LcdVcc_On_During_S0_State_15             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #15
+$LcdVcc_On_During_S0_State_16             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #16
+
+$Panel_Rotation_01                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_02                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_03                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_04                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_05                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_06                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_07                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_08                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_09                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_10                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_11                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_12                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_13                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_14                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_15                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+$Panel_Rotation_16                        2 bits      ;  00 = 0 Degree, 01 = 90 Degree, 10 = 180 Degree, 11 = 270 Degree.
+
+;==============================================================================
+; Block 41 - Flat Panel Data Tables Pointers
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; SKIP block ID and size
+SKIP                                      1 byte      ; Skip entries number byte
+
+$LVDS_Tbl_Ptr_01                          2 bytes
+$LVDS_Tbl_Size_01                         1 byte
+$LVDS_Tbl_01, $LVDS_Tbl_Ptr_01, $LVDS_Tbl_Size_01, Offset 4 bytes
+$DVO_Tbl_Ptr_01                           2 bytes
+$DVO_Tbl_Size_01                          1 byte
+$DVO_Tbl_01, $DVO_Tbl_Ptr_01, $DVO_Tbl_Size_01, Offset 0 byte
+$LVDS_PnP_ID_Ptr_01                       2 bytes
+$LVDS_PnP_ID_Size_01                      1 byte
+$LVDS_PnP_ID_01, $LVDS_PnP_ID_Ptr_01, $LVDS_PnP_ID_Size_01, Offset 0 byte
+
+$LVDS_Tbl_Ptr_02                          2 bytes
+$LVDS_Tbl_Size_02                         1 byte
+$LVDS_Tbl_02, $LVDS_Tbl_Ptr_02, $LVDS_Tbl_Size_02, Offset 4 bytes
+$DVO_Tbl_Ptr_02                           2 bytes
+$DVO_Tbl_Size_02                          1 byte
+$DVO_Tbl_02, $DVO_Tbl_Ptr_02, $DVO_Tbl_Size_02, Offset 0 byte
+$LVDS_PnP_ID_Ptr_02                       2 bytes
+$LVDS_PnP_ID_Size_02                      1 byte
+$LVDS_PnP_ID_02, $LVDS_PnP_ID_Ptr_02, $LVDS_PnP_ID_Size_02, Offset 0 byte
+
+$LVDS_Tbl_Ptr_03                          2 bytes
+$LVDS_Tbl_Size_03                         1 byte
+$LVDS_Tbl_03, $LVDS_Tbl_Ptr_03, $LVDS_Tbl_Size_03, Offset 4 bytes
+$DVO_Tbl_Ptr_03                           2 bytes
+$DVO_Tbl_Size_03                          1 byte
+$DVO_Tbl_03, $DVO_Tbl_Ptr_03, $DVO_Tbl_Size_03, Offset 0 byte
+$LVDS_PnP_ID_Ptr_03                       2 bytes
+$LVDS_PnP_ID_Size_03                      1 byte
+$LVDS_PnP_ID_03, $LVDS_PnP_ID_Ptr_03, $LVDS_PnP_ID_Size_03, Offset 0 byte
+
+$LVDS_Tbl_Ptr_04                          2 bytes
+$LVDS_Tbl_Size_04                         1 byte
+$LVDS_Tbl_04, $LVDS_Tbl_Ptr_04, $LVDS_Tbl_Size_04, Offset 4 bytes
+$DVO_Tbl_Ptr_04                           2 bytes
+$DVO_Tbl_Size_04                          1 byte
+$DVO_Tbl_04, $DVO_Tbl_Ptr_04, $DVO_Tbl_Size_04, Offset 0 byte
+$LVDS_PnP_ID_Ptr_04                       2 bytes
+$LVDS_PnP_ID_Size_04                      1 byte
+$LVDS_PnP_ID_04, $LVDS_PnP_ID_Ptr_04, $LVDS_PnP_ID_Size_04, Offset 0 byte
+
+$LVDS_Tbl_Ptr_05                          2 bytes
+$LVDS_Tbl_Size_05                         1 byte
+$LVDS_Tbl_05, $LVDS_Tbl_Ptr_05, $LVDS_Tbl_Size_05, Offset 4 bytes
+$DVO_Tbl_Ptr_05                           2 bytes
+$DVO_Tbl_Size_05                          1 byte
+$DVO_Tbl_05, $DVO_Tbl_Ptr_05, $DVO_Tbl_Size_05, Offset 0 byte
+$LVDS_PnP_ID_Ptr_05                       2 bytes
+$LVDS_PnP_ID_Size_05                      1 byte
+$LVDS_PnP_ID_05, $LVDS_PnP_ID_Ptr_05, $LVDS_PnP_ID_Size_05, Offset 0 byte
+
+$LVDS_Tbl_Ptr_06                          2 bytes
+$LVDS_Tbl_Size_06                         1 byte
+$LVDS_Tbl_06, $LVDS_Tbl_Ptr_06, $LVDS_Tbl_Size_06, Offset 4 bytes
+$DVO_Tbl_Ptr_06                           2 bytes
+$DVO_Tbl_Size_06                          1 byte
+$DVO_Tbl_06, $DVO_Tbl_Ptr_06, $DVO_Tbl_Size_06, Offset 0 byte
+$LVDS_PnP_ID_Ptr_06                       2 bytes
+$LVDS_PnP_ID_Size_06                      1 byte
+$LVDS_PnP_ID_06, $LVDS_PnP_ID_Ptr_06, $LVDS_PnP_ID_Size_06, Offset 0 byte
+
+$LVDS_Tbl_Ptr_07                          2 bytes
+$LVDS_Tbl_Size_07                         1 byte
+$LVDS_Tbl_07, $LVDS_Tbl_Ptr_07, $LVDS_Tbl_Size_07, Offset 4 bytes
+$DVO_Tbl_Ptr_07                           2 bytes
+$DVO_Tbl_Size_07                          1 byte
+$DVO_Tbl_07, $DVO_Tbl_Ptr_07, $DVO_Tbl_Size_07, Offset 0 byte
+$LVDS_PnP_ID_Ptr_07                       2 bytes
+$LVDS_PnP_ID_Size_07                      1 byte
+$LVDS_PnP_ID_07, $LVDS_PnP_ID_Ptr_07, $LVDS_PnP_ID_Size_07, Offset 0 byte
+
+$LVDS_Tbl_Ptr_08                          2 bytes
+$LVDS_Tbl_Size_08                         1 byte
+$LVDS_Tbl_08, $LVDS_Tbl_Ptr_08, $LVDS_Tbl_Size_08, Offset 4 bytes
+$DVO_Tbl_Ptr_08                           2 bytes
+$DVO_Tbl_Size_08                          1 byte
+$DVO_Tbl_08, $DVO_Tbl_Ptr_08, $DVO_Tbl_Size_08, Offset 0 byte
+$LVDS_PnP_ID_Ptr_08                       2 bytes
+$LVDS_PnP_ID_Size_08                      1 byte
+$LVDS_PnP_ID_08, $LVDS_PnP_ID_Ptr_08, $LVDS_PnP_ID_Size_08, Offset 0 byte
+
+$LVDS_Tbl_Ptr_09                          2 bytes
+$LVDS_Tbl_Size_09                         1 byte
+$LVDS_Tbl_09, $LVDS_Tbl_Ptr_09, $LVDS_Tbl_Size_09, Offset 4 bytes
+$DVO_Tbl_Ptr_09                           2 bytes
+$DVO_Tbl_Size_09                          1 byte
+$DVO_Tbl_09, $DVO_Tbl_Ptr_09, $DVO_Tbl_Size_09, Offset 0 byte
+$LVDS_PnP_ID_Ptr_09                       2 bytes
+$LVDS_PnP_ID_Size_09                      1 byte
+$LVDS_PnP_ID_09, $LVDS_PnP_ID_Ptr_09, $LVDS_PnP_ID_Size_09, Offset 0 byte
+
+$LVDS_Tbl_Ptr_10                          2 bytes
+$LVDS_Tbl_Size_10                         1 byte
+$LVDS_Tbl_10, $LVDS_Tbl_Ptr_10, $LVDS_Tbl_Size_10, Offset 4 bytes
+$DVO_Tbl_Ptr_10                           2 bytes
+$DVO_Tbl_Size_10                          1 byte
+$DVO_Tbl_10, $DVO_Tbl_Ptr_10, $DVO_Tbl_Size_10, Offset 0 byte
+$LVDS_PnP_ID_Ptr_10                       2 bytes
+$LVDS_PnP_ID_Size_10                      1 byte
+$LVDS_PnP_ID_10, $LVDS_PnP_ID_Ptr_10, $LVDS_PnP_ID_Size_10, Offset 0 byte
+
+$LVDS_Tbl_Ptr_11                          2 bytes
+$LVDS_Tbl_Size_11                         1 byte
+$LVDS_Tbl_11, $LVDS_Tbl_Ptr_11, $LVDS_Tbl_Size_11, Offset 4 bytes
+$DVO_Tbl_Ptr_11                           2 bytes
+$DVO_Tbl_Size_11                          1 byte
+$DVO_Tbl_11, $DVO_Tbl_Ptr_11, $DVO_Tbl_Size_11, Offset 0 byte
+$LVDS_PnP_ID_Ptr_11                       2 bytes
+$LVDS_PnP_ID_Size_11                      1 byte
+$LVDS_PnP_ID_11, $LVDS_PnP_ID_Ptr_11, $LVDS_PnP_ID_Size_11, Offset 0 byte
+
+$LVDS_Tbl_Ptr_12                          2 bytes
+$LVDS_Tbl_Size_12                         1 byte
+$LVDS_Tbl_12, $LVDS_Tbl_Ptr_12, $LVDS_Tbl_Size_12, Offset 4 bytes
+$DVO_Tbl_Ptr_12                           2 bytes
+$DVO_Tbl_Size_12                          1 byte
+$DVO_Tbl_12, $DVO_Tbl_Ptr_12, $DVO_Tbl_Size_12, Offset 0 byte
+$LVDS_PnP_ID_Ptr_12                       2 bytes
+$LVDS_PnP_ID_Size_12                      1 byte
+$LVDS_PnP_ID_12, $LVDS_PnP_ID_Ptr_12, $LVDS_PnP_ID_Size_12, Offset 0 byte
+
+$LVDS_Tbl_Ptr_13                          2 bytes
+$LVDS_Tbl_Size_13                         1 byte
+$LVDS_Tbl_13, $LVDS_Tbl_Ptr_13, $LVDS_Tbl_Size_13, Offset 4 bytes
+$DVO_Tbl_Ptr_13                           2 bytes
+$DVO_Tbl_Size_13                          1 byte
+$DVO_Tbl_13, $DVO_Tbl_Ptr_13, $DVO_Tbl_Size_13, Offset 0 byte
+$LVDS_PnP_ID_Ptr_13                       2 bytes
+$LVDS_PnP_ID_Size_13                      1 byte
+$LVDS_PnP_ID_13, $LVDS_PnP_ID_Ptr_13, $LVDS_PnP_ID_Size_13, Offset 0 byte
+
+$LVDS_Tbl_Ptr_14                          2 bytes
+$LVDS_Tbl_Size_14                         1 byte
+$LVDS_Tbl_14, $LVDS_Tbl_Ptr_14, $LVDS_Tbl_Size_14, Offset 4 bytes
+$DVO_Tbl_Ptr_14                           2 bytes
+$DVO_Tbl_Size_14                          1 byte
+$DVO_Tbl_14, $DVO_Tbl_Ptr_14, $DVO_Tbl_Size_14, Offset 0 byte
+$LVDS_PnP_ID_Ptr_14                       2 bytes
+$LVDS_PnP_ID_Size_14                      1 byte
+$LVDS_PnP_ID_14, $LVDS_PnP_ID_Ptr_14, $LVDS_PnP_ID_Size_14, Offset 0 byte
+
+$LVDS_Tbl_Ptr_15                          2 bytes
+$LVDS_Tbl_Size_15                         1 byte
+$LVDS_Tbl_15, $LVDS_Tbl_Ptr_15, $LVDS_Tbl_Size_15, Offset 4 bytes
+$DVO_Tbl_Ptr_15                           2 bytes
+$DVO_Tbl_Size_15                          1 byte
+$DVO_Tbl_15, $DVO_Tbl_Ptr_15, $DVO_Tbl_Size_15, Offset 0 byte
+$LVDS_PnP_ID_Ptr_15                       2 bytes
+$LVDS_PnP_ID_Size_15                      1 byte
+$LVDS_PnP_ID_15, $LVDS_PnP_ID_Ptr_15, $LVDS_PnP_ID_Size_15, Offset 0 byte
+
+$LVDS_Tbl_Ptr_16                          2 bytes
+$LVDS_Tbl_Size_16                         1 byte
+$LVDS_Tbl_16, $LVDS_Tbl_Ptr_16, $LVDS_Tbl_Size_16, Offset 4 bytes
+$DVO_Tbl_Ptr_16                           2 bytes
+$DVO_Tbl_Size_16                          1 byte
+$DVO_Tbl_16, $DVO_Tbl_Ptr_16, $DVO_Tbl_Size_16, Offset 0 byte
+$LVDS_PnP_ID_Ptr_16                       2 bytes
+$LVDS_PnP_ID_Size_16                      1 byte
+$LVDS_PnP_ID_16, $LVDS_PnP_ID_Ptr_16, $LVDS_PnP_ID_Size_16, Offset 0 byte
+
+$LVDS_Name_Ptr                            2 bytes
+$LVDS_Name_Sz                             1 byte      ; Skip LFP_PanelName offset and panel name length
+
+;==============================================================================
+; Block 42 - Flat Panel Data Tables
+;------------------------------------------------------------------------------
+SKIP                                      3 bytes     ; Skip block ID and size
+
+; Flat Panel #01
+$Panel_Width_01                           2 bytes     ; Panel Width
+$Panel_Height_01                          2 bytes     ; Panel Height
+
+SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
+SKIP                                      18 bytes    ; DTD
+SKIP                                      10 bytes    ; PnP ID
+
+; Flat Panel #02
+$Panel_Width_02                           2 bytes     ; Panel Width
+$Panel_Height_02                          2 bytes     ; Panel Height
+
+SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
+SKIP                                      18 bytes    ; DTD
+SKIP                                      10 bytes    ; PnP ID
+
+; Flat Panel #03
+$Panel_Width_03                           2 bytes     ; Panel Width
+$Panel_Height_03                          2 bytes     ; Panel Height
+
+SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
+SKIP                                      18 bytes    ; DTD
+SKIP                                      10 bytes    ; PnP ID
+
+; Flat Panel #04
+$Panel_Width_04                           2 bytes     ; Panel Width
+$Panel_Height_04                          2 bytes     ; Panel Height
+
+SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
+SKIP                                      18 bytes    ; DTD
+SKIP                                      10 bytes    ; PnP ID
+
+; Flat Panel #05
+$Panel_Width_05                           2 bytes     ; Panel Width
+$Panel_Height_05                          2 bytes     ; Panel Height
+
+SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
+SKIP                                      18 bytes    ; DTD
+SKIP                                      10 bytes    ; PnP ID
+
+; Flat Panel #06
+$Panel_Width_06                           2 bytes     ; Panel Width
+$Panel_Height_06                          2 bytes     ; Panel Height
+
+SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
+SKIP                                      18 bytes    ; DTD
+SKIP                                      10 bytes    ; PnP ID
+
+; Flat Panel #07
+
+$Panel_Width_07                           2 bytes     ; Panel Width
+$Panel_Height_07                          2 bytes     ; Panel Height
+
+SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
+SKIP                                      18 bytes    ; DTD
+SKIP                                      10 bytes    ; PnP ID
+
+; Flat Panel #08
+
+$Panel_Width_08                           2 bytes     ; Panel Width
+$Panel_Height_08                          2 bytes     ; Panel Height
+
+SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
+SKIP                                      18 bytes    ; DTD
+SKIP                                      10 bytes    ; PnP ID
+
+; Flat Panel #09
+$Panel_Width_09                           2 bytes     ; Panel Width
+$Panel_Height_09                          2 bytes     ; Panel Height
+
+SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
+SKIP                                      18 bytes    ; DTD
+SKIP                                      10 bytes    ; PnP ID
+
+; Flat Panel #10
+$Panel_Width_10                           2 bytes     ; Panel Width
+$Panel_Height_10                          2 bytes     ; Panel Height
+
+SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
+SKIP                                      18 bytes    ; DTD
+SKIP                                      10 bytes    ; PnP ID
+
+; Flat Panel #11
+$Panel_Width_11                           2 bytes     ; Panel Width
+$Panel_Height_11                          2 bytes     ; Panel Height
+
+SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
+SKIP                                      18 bytes    ; DTD
+SKIP                                      10 bytes    ; PnP ID
+
+; Flat Panel #12
+$Panel_Width_12                           2 bytes     ; Panel Width
+$Panel_Height_12                          2 bytes     ; Panel Height
+
+SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
+SKIP                                      18 bytes    ; DTD
+SKIP                                      10 bytes    ; PnP ID
+
+; Flat Panel #13
+$Panel_Width_13                           2 bytes     ; Panel Width
+$Panel_Height_13                          2 bytes     ; Panel Height
+
+SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
+SKIP                                      18 bytes    ; DTD
+SKIP                                      10 bytes    ; PnP ID
+
+; Flat Panel #14
+$Panel_Width_14                           2 bytes     ; Panel Width
+$Panel_Height_14                          2 bytes     ; Panel Height
+
+SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
+SKIP                                      18 bytes    ; DTD
+SKIP                                      10 bytes    ; PnP ID
+
+; Flat Panel #15
+$Panel_Width_15                           2 bytes     ; Panel Width
+$Panel_Height_15                          2 bytes     ; Panel Height
+
+SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
+SKIP                                      18 bytes    ; DTD
+SKIP                                      10 bytes    ; PnP ID
+
+; Flat Panel #16
+$Panel_Width_16                           2 bytes     ; Panel Width
+$Panel_Height_16                          2 bytes     ; Panel Height
+
+SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
+SKIP                                      18 bytes    ; DTD
+SKIP                                      10 bytes    ; PnP ID
+
+$Panel_Name_01                            13 bytes    ; LFP Panel Name
+$Panel_Name_02                            13 bytes    ; LFP Panel Name
+$Panel_Name_03                            13 bytes    ; LFP Panel Name
+$Panel_Name_04                            13 bytes    ; LFP Panel Name
+$Panel_Name_05                            13 bytes    ; LFP Panel Name
+$Panel_Name_06                            13 bytes    ; LFP Panel Name
+$Panel_Name_07                            13 bytes    ; LFP Panel Name
+$Panel_Name_08                            13 bytes    ; LFP Panel Name
+$Panel_Name_09                            13 bytes    ; LFP Panel Name
+$Panel_Name_10                            13 bytes    ; LFP Panel Name
+$Panel_Name_11                            13 bytes    ; LFP Panel Name
+$Panel_Name_12                            13 bytes    ; LFP Panel Name
+$Panel_Name_13                            13 bytes    ; LFP Panel Name
+$Panel_Name_14                            13 bytes    ; LFP Panel Name
+$Panel_Name_15                            13 bytes    ; LFP Panel Name
+$Panel_Name_16                            13 bytes    ; LFP Panel Name
+
+SKIP                                      2 bytes     ; EnableScaling
+
+SKIP                                      16 bytes    ; Seamless_DRRS_Min_RR
+
+SKIP                                      16 bytes    ; Pixel overlap count field
+;==============================================================================
+; Block 43 - BLC (Backlight Control) Support
+;------------------------------------------------------------------------------
+
+SKIP                                      3 bytes     ; Skip block ID and size
+SKIP                                      1 byte      ; Skip row size
+
+; Flat Panel #01
+$BLC_Inv_Type_01                          2 bits      ; BLC inverter type
+$BLC_Inv_Polarity_01                      1 bit       ; BLC inverter polarity
+$BLC_GPIO_Pins_01                         3 bits      ; BLC inverter GPIO Pins
+$BLC_GMBus_Speed_01                       2 bits      ; BLC inverter GMBus speed
+$PWM_Frequency_01                         2 bytes     ; PWM inverter frequency
+$BLC_Min_Brightness_01                    1 byte      ; Minimum Brightness, 0 - 255
+$BLC_I2C_Addr_01                          1 byte      ; I2C inverter Slave address
+$BLC_Brightness_Cmd_01                    1 byte      ; I2C inverter command code
+
+; Flat Panel #02
+$BLC_Inv_Type_02                          2 bits      ; BLC inverter type
+$BLC_Inv_Polarity_02                      1 bit       ; BLC inverter polarity
+$BLC_GPIO_Pins_02                         3 bits      ; BLC inverter GPIO Pins
+$BLC_GMBus_Speed_02                       2 bits      ; BLC inverter GMBus speed
+$PWM_Frequency_02                         2 bytes     ; PWM inverter frequency
+$BLC_Min_Brightness_02                    1 byte      ; Minimum Brightness, 0 - 255
+$BLC_I2C_Addr_02                          1 byte      ; I2C inverter Slave address
+$BLC_Brightness_Cmd_02                    1 byte      ; I2C inverter command code
+
+; Flat Panel #03
+$BLC_Inv_Type_03                          2 bits      ; BLC inverter type
+$BLC_Inv_Polarity_03                      1 bit       ; BLC inverter polarity
+$BLC_GPIO_Pins_03                         3 bits      ; BLC inverter GPIO Pins
+$BLC_GMBus_Speed_03                       2 bits      ; BLC inverter GMBus speed
+$PWM_Frequency_03                         2 bytes     ; PWM inverter frequency
+$BLC_Min_Brightness_03                    1 byte      ; Minimum Brightness, 0 - 255
+$BLC_I2C_Addr_03                          1 byte      ; I2C inverter Slave address
+$BLC_Brightness_Cmd_03                    1 byte      ; I2C inverter command code
+
+; Flat Panel #04
+$BLC_Inv_Type_04                          2 bits      ; BLC inverter type
+$BLC_Inv_Polarity_04                      1 bit       ; BLC inverter polarity
+$BLC_GPIO_Pins_04                         3 bits      ; BLC inverter GPIO Pins
+$BLC_GMBus_Speed_04                       2 bits      ; BLC inverter GMBus speed
+$PWM_Frequency_04                         2 bytes     ; PWM inverter frequency
+$BLC_Min_Brightness_04                    1 byte      ; Minimum Brightness, 0 - 255
+$BLC_I2C_Addr_04                          1 byte      ; I2C inverter Slave address
+$BLC_Brightness_Cmd_04                    1 byte      ; I2C inverter command code
+
+; Flat Panel #05
+$BLC_Inv_Type_05                          2 bits      ; BLC inverter type
+$BLC_Inv_Polarity_05                      1 bit       ; BLC inverter polarity
+$BLC_GPIO_Pins_05                         3 bits      ; BLC inverter GPIO Pins
+$BLC_GMBus_Speed_05                       2 bits      ; BLC inverter GMBus speed
+$PWM_Frequency_05                         2 bytes     ; PWM inverter frequency
+$BLC_Min_Brightness_05                    1 byte      ; Minimum Brightness, 0 - 255
+$BLC_I2C_Addr_05                          1 byte      ; I2C inverter Slave address
+$BLC_Brightness_Cmd_05                    1 byte      ; I2C inverter command code
+
+; Flat Panel #06
+$BLC_Inv_Type_06                          2 bits      ; BLC inverter type
+$BLC_Inv_Polarity_06                      1 bit       ; BLC inverter polarity
+$BLC_GPIO_Pins_06                         3 bits      ; BLC inverter GPIO Pins
+$BLC_GMBus_Speed_06                       2 bits      ; BLC inverter GMBus speed
+$PWM_Frequency_06                         2 bytes     ; PWM inverter frequency
+$BLC_Min_Brightness_06                    1 byte      ; Minimum Brightness, 0 - 255
+$BLC_I2C_Addr_06                          1 byte      ; I2C inverter Slave address
+$BLC_Brightness_Cmd_06                    1 byte      ; I2C inverter command code
+
+; Flat Panel #07
+$BLC_Inv_Type_07                          2 bits      ; BLC inverter type
+$BLC_Inv_Polarity_07                      1 bit       ; BLC inverter polarity
+$BLC_GPIO_Pins_07                         3 bits      ; BLC inverter GPIO Pins
+$BLC_GMBus_Speed_07                       2 bits      ; BLC inverter GMBus speed
+$PWM_Frequency_07                         2 bytes     ; PWM inverter frequency
+$BLC_Min_Brightness_07                    1 byte      ; Minimum Brightness, 0 - 255
+$BLC_I2C_Addr_07                          1 byte      ; I2C inverter Slave address
+$BLC_Brightness_Cmd_07                    1 byte      ; I2C inverter command code
+
+; Flat Panel #08
+$BLC_Inv_Type_08                          2 bits      ; BLC inverter type
+$BLC_Inv_Polarity_08                      1 bit       ; BLC inverter polarity
+$BLC_GPIO_Pins_08                         3 bits      ; BLC inverter GPIO Pins
+$BLC_GMBus_Speed_08                       2 bits      ; BLC inverter GMBus speed
+$PWM_Frequency_08                         2 bytes     ; PWM inverter frequency
+$BLC_Min_Brightness_08                    1 byte      ; Minimum Brightness, 0 - 255
+$BLC_I2C_Addr_08                          1 byte      ; I2C inverter Slave address
+$BLC_Brightness_Cmd_08                    1 byte      ; I2C inverter command code
+
+; Flat Panel #09
+$BLC_Inv_Type_09                          2 bits      ; BLC inverter type
+$BLC_Inv_Polarity_09                      1 bit       ; BLC inverter polarity
+$BLC_GPIO_Pins_09                         3 bits      ; BLC inverter GPIO Pins
+$BLC_GMBus_Speed_09                       2 bits      ; BLC inverter GMBus speed
+$PWM_Frequency_09                         2 bytes     ; PWM inverter frequency
+$BLC_Min_Brightness_09                    1 byte      ; Minimum Brightness, 0 - 255
+$BLC_I2C_Addr_09                          1 byte      ; I2C inverter Slave address
+$BLC_Brightness_Cmd_09                    1 byte      ; I2C inverter command code
+
+; Flat Panel #10
+$BLC_Inv_Type_10                          2 bits      ; BLC inverter type
+$BLC_Inv_Polarity_10                      1 bit       ; BLC inverter polarity
+$BLC_GPIO_Pins_10                         3 bits      ; BLC inverter GPIO Pins
+$BLC_GMBus_Speed_10                       2 bits      ; BLC inverter GMBus speed
+$PWM_Frequency_10                         2 bytes     ; PWM inverter frequency
+$BLC_Min_Brightness_10                    1 byte      ; Minimum Brightness, 0 - 255
+$BLC_I2C_Addr_10                          1 byte      ; I2C inverter Slave address
+$BLC_Brightness_Cmd_10                    1 byte      ; I2C inverter command code
+
+; Flat Panel #11
+$BLC_Inv_Type_11                          2 bits      ; BLC inverter type
+$BLC_Inv_Polarity_11                      1 bit       ; BLC inverter polarity
+$BLC_GPIO_Pins_11                         3 bits      ; BLC inverter GPIO Pins
+$BLC_GMBus_Speed_11                       2 bits      ; BLC inverter GMBus speed
+$PWM_Frequency_11                         2 bytes     ; PWM inverter frequency
+$BLC_Min_Brightness_11                    1 byte      ; Minimum Brightness, 0 - 255
+$BLC_I2C_Addr_11                          1 byte      ; I2C inverter Slave address
+$BLC_Brightness_Cmd_11                    1 byte      ; I2C inverter command code
+
+; Flat Panel #12
+$BLC_Inv_Type_12                          2 bits      ; BLC inverter type
+$BLC_Inv_Polarity_12                      1 bit       ; BLC inverter polarity
+$BLC_GPIO_Pins_12                         3 bits      ; BLC inverter GPIO Pins
+$BLC_GMBus_Speed_12                       2 bits      ; BLC inverter GMBus speed
+$PWM_Frequency_12                         2 bytes     ; PWM inverter frequency
+$BLC_Min_Brightness_12                    1 byte      ; Minimum Brightness, 0 - 255
+$BLC_I2C_Addr_12                          1 byte      ; I2C inverter Slave address
+$BLC_Brightness_Cmd_12                    1 byte      ; I2C inverter command code
+
+; Flat Panel #13
+$BLC_Inv_Type_13                          2 bits      ; BLC inverter type
+$BLC_Inv_Polarity_13                      1 bit       ; BLC inverter polarity
+$BLC_GPIO_Pins_13                         3 bits      ; BLC inverter GPIO Pins
+$BLC_GMBus_Speed_13                       2 bits      ; BLC inverter GMBus speed
+$PWM_Frequency_13                         2 bytes     ; PWM inverter frequency
+$BLC_Min_Brightness_13                    1 byte      ; Minimum Brightness, 0 - 255
+$BLC_I2C_Addr_13                          1 byte      ; I2C inverter Slave address
+$BLC_Brightness_Cmd_13                    1 byte      ; I2C inverter command code
+
+; Flat Panel #14
+$BLC_Inv_Type_14                          2 bits      ; BLC inverter type
+$BLC_Inv_Polarity_14                      1 bit       ; BLC inverter polarity
+$BLC_GPIO_Pins_14                         3 bits      ; BLC inverter GPIO Pins
+$BLC_GMBus_Speed_14                       2 bits      ; BLC inverter GMBus speed
+$PWM_Frequency_14                         2 bytes     ; PWM inverter frequency
+$BLC_Min_Brightness_14                    1 byte      ; Minimum Brightness, 0 - 255
+$BLC_I2C_Addr_14                          1 byte      ; I2C inverter Slave address
+$BLC_Brightness_Cmd_14                    1 byte      ; I2C inverter command code
+
+; Flat Panel #15
+$BLC_Inv_Type_15                          2 bits      ; BLC inverter type
+$BLC_Inv_Polarity_15                      1 bit       ; BLC inverter polarity
+$BLC_GPIO_Pins_15                         3 bits      ; BLC inverter GPIO Pins
+$BLC_GMBus_Speed_15                       2 bits      ; BLC inverter GMBus speed
+$PWM_Frequency_15                         2 bytes     ; PWM inverter frequency
+$BLC_Min_Brightness_15                    1 byte      ; Minimum Brightness, 0 - 255
+$BLC_I2C_Addr_15                          1 byte      ; I2C inverter Slave address
+$BLC_Brightness_Cmd_15                    1 byte      ; I2C inverter command code
+
+; Flat Panel #16
+$BLC_Inv_Type_16                          2 bits      ; BLC inverter type
+$BLC_Inv_Polarity_16                      1 bit       ; BLC inverter polarity
+$BLC_GPIO_Pins_16                         3 bits      ; BLC inverter GPIO Pins
+$BLC_GMBus_Speed_16                       2 bits      ; BLC inverter GMBus speed
+$PWM_Frequency_16                         2 bytes     ; PWM inverter frequency
+$BLC_Min_Brightness_16                    1 byte      ; Minimum Brightness, 0 - 255
+$BLC_I2C_Addr_16                          1 byte      ; I2C inverter Slave address
+$BLC_Brightness_Cmd_16                    1 byte      ; I2C inverter command code
+
+$POST_BL_Brightness_01                    1 byte      ; Intial brightness value at POST for Flat Panel #01
+$POST_BL_Brightness_02                    1 byte      ; Intial brightness value at POST for Flat Panel #02
+$POST_BL_Brightness_03                    1 byte      ; Intial brightness value at POST for Flat Panel #03
+$POST_BL_Brightness_04                    1 byte      ; Intial brightness value at POST for Flat Panel #04
+$POST_BL_Brightness_05                    1 byte      ; Intial brightness value at POST for Flat Panel #05
+$POST_BL_Brightness_06                    1 byte      ; Intial brightness value at POST for Flat Panel #06
+$POST_BL_Brightness_07                    1 byte      ; Intial brightness value at POST for Flat Panel #07
+$POST_BL_Brightness_08                    1 byte      ; Intial brightness value at POST for Flat Panel #08
+$POST_BL_Brightness_09                    1 byte      ; Intial brightness value at POST for Flat Panel #09
+$POST_BL_Brightness_10                    1 byte      ; Intial brightness value at POST for Flat Panel #10
+$POST_BL_Brightness_11                    1 byte      ; Intial brightness value at POST for Flat Panel #11
+$POST_BL_Brightness_12                    1 byte      ; Intial brightness value at POST for Flat Panel #12
+$POST_BL_Brightness_13                    1 byte      ; Intial brightness value at POST for Flat Panel #13
+$POST_BL_Brightness_14                    1 byte      ; Intial brightness value at POST for Flat Panel #14
+$POST_BL_Brightness_15                    1 byte      ; Intial brightness value at POST for Flat Panel #15
+$POST_BL_Brightness_16                    1 byte      ; Intial brightness value at POST for Flat Panel #16
+
+$Lfp_Pwm_Source_Selection_01              4 bits      ; Pwm Source Selection for Panel #1
+$Lfp_Pwm_Controller_Selection_01          4 bits      ; Pwm Controller Selection for Panel #1
+
+$Lfp_Pwm_Source_Selection_02              4 bits      ; Pwm Source Selection for Panel #2
+$Lfp_Pwm_Controller_Selection_02          4 bits      ; Pwm Controller Selection for Panel #2
+
+$Lfp_Pwm_Source_Selection_03              4 bits      ; Pwm Source Selection for Panel #3
+$Lfp_Pwm_Controller_Selection_03          4 bits      ; Pwm Controller Selection for Panel #3
+
+$Lfp_Pwm_Source_Selection_04              4 bits      ; Pwm Source Selection for Panel #4
+$Lfp_Pwm_Controller_Selection_04          4 bits      ; Pwm Controller Selection for Panel #4
+
+$Lfp_Pwm_Source_Selection_05              4 bits      ; Pwm Source Selection for Panel #5
+$Lfp_Pwm_Controller_Selection_05          4 bits      ; Pwm Controller Selection for Panel #5
+
+$Lfp_Pwm_Source_Selection_06              4 bits      ; Pwm Source Selection for Panel #6
+$Lfp_Pwm_Controller_Selection_06          4 bits      ; Pwm Controller Selection for Panel #6
+
+$Lfp_Pwm_Source_Selection_07              4 bits      ; Pwm Source Selection for Panel #7
+$Lfp_Pwm_Controller_Selection_07          4 bits      ; Pwm Controller Selection for Panel #7
+
+$Lfp_Pwm_Source_Selection_08              4 bits      ; Pwm Source Selection for Panel #8
+$Lfp_Pwm_Controller_Selection_08          4 bits      ; Pwm Controller Selection for Panel #8
+
+$Lfp_Pwm_Source_Selection_09              4 bits      ; Pwm Source Selection for Panel #9
+$Lfp_Pwm_Controller_Selection_09          4 bits      ; Pwm Controller Selection for Panel #9
+
+$Lfp_Pwm_Source_Selection_10              4 bits      ; Pwm Source Selection for Panel #10
+$Lfp_Pwm_Controller_Selection_10          4 bits      ; Pwm Controller Selection for Panel #10
+
+$Lfp_Pwm_Source_Selection_11              4 bits      ; Pwm Source Selection for Panel #11
+$Lfp_Pwm_Controller_Selection_11          4 bits      ; Pwm Controller Selection for Panel #11
+
+$Lfp_Pwm_Source_Selection_12              4 bits      ; Pwm Source Selection for Panel #12
+$Lfp_Pwm_Controller_Selection_12          4 bits      ; Pwm Controller Selection for Panel #12
+
+$Lfp_Pwm_Source_Selection_13              4 bits      ; Pwm Source Selection for Panel #13
+$Lfp_Pwm_Controller_Selection_13          4 bits      ; Pwm Controller Selection for Panel #13
+
+$Lfp_Pwm_Source_Selection_14              4 bits      ; Pwm Source Selection for Panel #14
+$Lfp_Pwm_Controller_Selection_14          4 bits      ; Pwm Controller Selection for Panel #14
+
+$Lfp_Pwm_Source_Selection_15              4 bits      ; Pwm Source Selection for Panel #15
+$Lfp_Pwm_Controller_Selection_15          4 bits      ; Pwm Controller Selection for Panel #15
+
+$Lfp_Pwm_Source_Selection_16              4 bits      ; Pwm Source Selection for Panel #16
+$Lfp_Pwm_Controller_Selection_16          4 bits      ; Pwm Controller Selection for Panel #16
+
+;==============================================================================
+; Block 44 - BIA (Backlight Image Adaption) Support
+;------------------------------------------------------------------------------
+
+SKIP                                      3 bytes     ; Skip block ID and size
+
+SKIP                                      1 byte      ; Obsolete.
+
+ALIGN
+
+$ALS_Response_Data                        20 bytes    ; ALS Response Data
+
+SKIP                                      3 bits      ; Obsolete.
+SKIP                                      5 bits      ; Reserved
+
+$DPST_Enable_01                           1 bit       ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #01.
+$DPST_Enable_02                           1 bit       ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #02.
+$DPST_Enable_03                           1 bit       ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #03.
+$DPST_Enable_04                           1 bit       ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #04.
+$DPST_Enable_05                           1 bit       ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #05.
+$DPST_Enable_06                           1 bit       ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #06.
+$DPST_Enable_07                           1 bit       ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #07.
+$DPST_Enable_08                           1 bit       ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #08.
+$DPST_Enable_09                           1 bit       ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #09.
+$DPST_Enable_10                           1 bit       ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #10.
+$DPST_Enable_11                           1 bit       ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #11.
+$DPST_Enable_12                           1 bit       ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #12.
+$DPST_Enable_13                           1 bit       ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #13.
+$DPST_Enable_14                           1 bit       ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #14.
+$DPST_Enable_15                           1 bit       ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #15.
+$DPST_Enable_16                           1 bit       ; Intel Display Power Saving Technology (DPST) Enable/Disable Flag for Panel #16.
+
+$PSR_Enable_01                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #01.
+$PSR_Enable_02                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #02.
+$PSR_Enable_03                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #03.
+$PSR_Enable_04                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #04.
+$PSR_Enable_05                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #05.
+$PSR_Enable_06                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #06.
+$PSR_Enable_07                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #07.
+$PSR_Enable_08                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #08.
+$PSR_Enable_09                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #09.
+$PSR_Enable_10                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #10.
+$PSR_Enable_11                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #11.
+$PSR_Enable_12                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #12.
+$PSR_Enable_13                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #13.
+$PSR_Enable_14                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #14.
+$PSR_Enable_15                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #15.
+$PSR_Enable_16                            1 bit       ; Panel Self refresh feature (PSR) Enable/Disable Flag for Panel #16.
+
+$DRRS_Enable_01                           1 bit       ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #01.
+$DRRS_Enable_02                           1 bit       ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #02.
+$DRRS_Enable_03                           1 bit       ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #03.
+$DRRS_Enable_04                           1 bit       ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #04.
+$DRRS_Enable_05                           1 bit       ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #05.
+$DRRS_Enable_06                           1 bit       ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #06.
+$DRRS_Enable_07                           1 bit       ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #07.
+$DRRS_Enable_08                           1 bit       ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #08.
+$DRRS_Enable_09                           1 bit       ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #09.
+$DRRS_Enable_10                           1 bit       ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #10.
+$DRRS_Enable_11                           1 bit       ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #11.
+$DRRS_Enable_12                           1 bit       ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #12.
+$DRRS_Enable_13                           1 bit       ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #13.
+$DRRS_Enable_14                           1 bit       ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #14.
+$DRRS_Enable_15                           1 bit       ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #15.
+$DRRS_Enable_16                           1 bit       ; Intel Display Refresh Rate Switching (DRRS) Enable/Disable Flag for Panel #16.
+
+$LACE_Enable_01                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #01.
+$LACE_Enable_02                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #02.
+$LACE_Enable_03                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #03.
+$LACE_Enable_04                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #04.
+$LACE_Enable_05                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #05.
+$LACE_Enable_06                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #06.
+$LACE_Enable_07                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #07.
+$LACE_Enable_08                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #08.
+$LACE_Enable_09                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #09.
+$LACE_Enable_10                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #10.
+$LACE_Enable_11                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #11.
+$LACE_Enable_12                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #12.
+$LACE_Enable_13                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #13.
+$LACE_Enable_14                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #14.
+$LACE_Enable_15                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #15.
+$LACE_Enable_16                           1 bit       ; Display LACE Support Feature Enable/Disable Flag for Panel #16.
+
+
+$ADT_Enable_01                            1 bit       ; Assertive display technology enable/disable for Panel #01.
+$ADT_Enable_02                            1 bit       ; Assertive display technology enable/disable for Panel #02.
+$ADT_Enable_03                            1 bit       ; Assertive display technology enable/disable for Panel #03.
+$ADT_Enable_04                            1 bit       ; Assertive display technology enable/disable for Panel #04.
+$ADT_Enable_05                            1 bit       ; Assertive display technology enable/disable for Panel #05.
+$ADT_Enable_06                            1 bit       ; Assertive display technology enable/disable for Panel #06.
+$ADT_Enable_07                            1 bit       ; Assertive display technology enable/disable for Panel #07.
+$ADT_Enable_08                            1 bit       ; Assertive display technology enable/disable for Panel #08.
+$ADT_Enable_09                            1 bit       ; Assertive display technology enable/disable for Panel #09.
+$ADT_Enable_10                            1 bit       ; Assertive display technology enable/disable for Panel #10.
+$ADT_Enable_11                            1 bit       ; Assertive display technology enable/disable for Panel #11.
+$ADT_Enable_12                            1 bit       ; Assertive display technology enable/disable for Panel #12.
+$ADT_Enable_13                            1 bit       ; Assertive display technology enable/disable for Panel #13.
+$ADT_Enable_14                            1 bit       ; Assertive display technology enable/disable for Panel #14.
+$ADT_Enable_15                            1 bit       ; Assertive display technology enable/disable for Panel #15.
+$ADT_Enable_16                            1 bit       ; Assertive display technology enable/disable for Panel #16.
+
+$DMRRS_Enable_01                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #01.
+$DMRRS_Enable_02                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #02.
+$DMRRS_Enable_03                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #03.
+$DMRRS_Enable_04                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #04.
+$DMRRS_Enable_05                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #05.
+$DMRRS_Enable_06                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #06.
+$DMRRS_Enable_07                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #07.
+$DMRRS_Enable_08                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #08.
+$DMRRS_Enable_09                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #09.
+$DMRRS_Enable_10                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #10.
+$DMRRS_Enable_11                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #11.
+$DMRRS_Enable_12                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #12.
+$DMRRS_Enable_13                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #13.
+$DMRRS_Enable_14                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #14.
+$DMRRS_Enable_15                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #15.
+$DMRRS_Enable_16                          1 bit       ; Dynamic media refresh rate enable/disable for Panel #16.
+
+$ADB_Enable_01                            1 bit       ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #01.
+$ADB_Enable_02                            1 bit       ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #02.
+$ADB_Enable_03                            1 bit       ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #03.
+$ADB_Enable_04                            1 bit       ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #04.
+$ADB_Enable_05                            1 bit       ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #05.
+$ADB_Enable_06                            1 bit       ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #06.
+$ADB_Enable_07                            1 bit       ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #07.
+$ADB_Enable_08                            1 bit       ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #08.
+$ADB_Enable_09                            1 bit       ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #09.
+$ADB_Enable_10                            1 bit       ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #10.
+$ADB_Enable_11                            1 bit       ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #11.
+$ADB_Enable_12                            1 bit       ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #12.
+$ADB_Enable_13                            1 bit       ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #13.
+$ADB_Enable_14                            1 bit       ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #14.
+$ADB_Enable_15                            1 bit       ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #15.
+$ADB_Enable_16                            1 bit       ; Intel Automatic Display Brightness (ADB) Enable/Disable Flag for Panel #16.
+
+$LACE_Status_01                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #01.
+$LACE_Status_02                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #02.
+$LACE_Status_03                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #03.
+$LACE_Status_04                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #04.
+$LACE_Status_05                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #05.
+$LACE_Status_06                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #06.
+$LACE_Status_07                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #07.
+$LACE_Status_08                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #08.
+$LACE_Status_09                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #09.
+$LACE_Status_10                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #10.
+$LACE_Status_11                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #11.
+$LACE_Status_12                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #12.
+$LACE_Status_13                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #13.
+$LACE_Status_14                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #14.
+$LACE_Status_15                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #15.
+$LACE_Status_16                           1 bit       ;Default Display LACE Status  enable/disable Flag for Panel #16.
+
+$DPST_Aggressiveness_Profile_01           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #01.
+$LACE_Aggressiveness_Profile_01           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #01.
+
+$DPST_Aggressiveness_Profile_02           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #02.
+$LACE_Aggressiveness_Profile_02           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #02.
+
+$DPST_Aggressiveness_Profile_03           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #03.
+$LACE_Aggressiveness_Profile_03           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #03.
+
+$DPST_Aggressiveness_Profile_04           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #04.
+$LACE_Aggressiveness_Profile_04           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #04.
+
+$DPST_Aggressiveness_Profile_05           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #05.
+$LACE_Aggressiveness_Profile_05           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #05.
+
+$DPST_Aggressiveness_Profile_06           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #06.
+$LACE_Aggressiveness_Profile_06           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #06.
+
+$DPST_Aggressiveness_Profile_07           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #07.
+$LACE_Aggressiveness_Profile_07           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #07.
+
+$DPST_Aggressiveness_Profile_08           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #08.
+$LACE_Aggressiveness_Profile_08           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #08.
+
+$DPST_Aggressiveness_Profile_09           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #09.
+$LACE_Aggressiveness_Profile_09           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #09.
+
+$DPST_Aggressiveness_Profile_10           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #10.
+$LACE_Aggressiveness_Profile_10           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #10.
+
+$DPST_Aggressiveness_Profile_11           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #11.
+$LACE_Aggressiveness_Profile_11           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #11.
+
+$DPST_Aggressiveness_Profile_12           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #12.
+$LACE_Aggressiveness_Profile_12           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #12.
+
+$DPST_Aggressiveness_Profile_13           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #13.
+$LACE_Aggressiveness_Profile_13           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #13.
+
+$DPST_Aggressiveness_Profile_14           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #14.
+$LACE_Aggressiveness_Profile_14           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #14.
+
+$DPST_Aggressiveness_Profile_15           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #15.
+$LACE_Aggressiveness_Profile_15           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #15.
+
+$DPST_Aggressiveness_Profile_16           4 bits      ;DPST Aggressiveness profile Input Selection for Panel #16.
+$LACE_Aggressiveness_Profile_16           4 bits      ;Lace Aggressiveness profile Input Selection for Panel #16.
+
+;==============================================================================
+; Block 46 - Chromaticity  Support
+;------------------------------------------------------------------------------
+
+SKIP                                      3 bytes     ; Skip block ID and size
+
+; Flat Panel #01
+$Chromacity_Enable_01                     1 bit       ; enable or disable the chromacity bit
+$Override_EDID_Data_01                    1 bit       ; Override the chromaticity bit
+SKIP                                      6 bits      ; Reserved bits
+$Red_Green_01                             1 byte      ; Red/green chormaticity coordinates at 19h
+$Blue_White_01                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
+$Red_x_01                                 1 byte      ; Red x coordinate at 1Bh
+$Red_y_01                                 1 byte      ; Red y coordinate at 1Ch
+$Green_x_01                               1 byte      ; Green x coordinate at 1Dh
+$Green_y_01                               1 byte      ; Green y ccoordinate at 1Eh
+$Blue_x_01                                1 byte      ; Blue x coordinate at 1Fh
+$Blue_y_01                                1 byte      ; Blue y coordinate at 20h
+$White_x_01                               1 byte      ; White x coordiante at 21h
+$White_y_01                               1 byte      ; White y coordinate at 22h
+
+; Flat Panel #02
+$Chromacity_Enable_02                     1 bit       ; enable or disable the chromacity bit
+$Override_EDID_Data_02                    1 bit       ; Override the chromaticity bit
+SKIP                                      6 bits      ; Reserved bits
+$Red_Green_02                             1 byte      ; Red/green chormaticity coordinates at 19h
+$Blue_White_02                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
+$Red_x_02                                 1 byte      ; Red x coordinate at 1Bh
+$Red_y_02                                 1 byte      ; Red y coordinate at 1Ch
+$Green_x_02                               1 byte      ; Green x coordinate at 1Dh
+$Green_y_02                               1 byte      ; Green y ccoordinate at 1Eh
+$Blue_x_02                                1 byte      ; Blue x coordinate at 1Fh
+$Blue_y_02                                1 byte      ; Blue y coordinate at 20h
+$White_x_02                               1 byte      ; White x coordiante at 21h
+$White_y_02                               1 byte      ; White y coordinate at 22h
+
+; Flat Panel #03
+$Chromacity_Enable_03                     1 bit       ; enable or disable the chromacity bit
+$Override_EDID_Data_03                    1 bit       ; Override the chromaticity bit
+SKIP                                      6 bits      ; Reserved bits
+$Red_Green_03                             1 byte      ; Red/green chormaticity coordinates at 19h
+$Blue_White_03                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
+$Red_x_03                                 1 byte      ; Red x coordinate at 1Bh
+$Red_y_03                                 1 byte      ; Red y coordinate at 1Ch
+$Green_x_03                               1 byte      ; Green x coordinate at 1Dh
+$Green_y_03                               1 byte      ; Green y ccoordinate at 1Eh
+$Blue_x_03                                1 byte      ; Blue x coordinate at 1Fh
+$Blue_y_03                                1 byte      ; Blue y coordinate at 20h
+$White_x_03                               1 byte      ; White x coordiante at 21h
+$White_y_03                               1 byte      ; White y coordinate at 22h
+
+; Flat Panel #04
+$Chromacity_Enable_04                     1 bit       ; enable or disable the chromacity bit
+$Override_EDID_Data_04                    1 bit       ; Override the chromaticity bit
+SKIP                                      6 bits      ; Reserved bits
+$Red_Green_04                             1 byte      ; Red/green chormaticity coordinates at 19h
+$Blue_White_04                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
+$Red_x_04                                 1 byte      ; Red x coordinate at 1Bh
+$Red_y_04                                 1 byte      ; Red y coordinate at 1Ch
+$Green_x_04                               1 byte      ; Green x coordinate at 1Dh
+$Green_y_04                               1 byte      ; Green y ccoordinate at 1Eh
+$Blue_x_04                                1 byte      ; Blue x coordinate at 1Fh
+$Blue_y_04                                1 byte      ; Blue y coordinate at 20h
+$White_x_04                               1 byte      ; White x coordiante at 21h
+$White_y_04                               1 byte      ; White y coordinate at 22h
+
+; Flat Panel #05
+$Chromacity_Enable_05                     1 bit       ; enable or disable the chromacity bit
+$Override_EDID_Data_05                    1 bit       ; Override the chromaticity bit
+SKIP                                      6 bits      ; Reserved bits
+$Red_Green_05                             1 byte      ; Red/green chormaticity coordinates at 19h
+$Blue_White_05                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
+$Red_x_05                                 1 byte      ; Red x coordinate at 1Bh
+$Red_y_05                                 1 byte      ; Red y coordinate at 1Ch
+$Green_x_05                               1 byte      ; Green x coordinate at 1Dh
+$Green_y_05                               1 byte      ; Green y ccoordinate at 1Eh
+$Blue_x_05                                1 byte      ; Blue x coordinate at 1Fh
+$Blue_y_05                                1 byte      ; Blue y coordinate at 20h
+$White_x_05                               1 byte      ; White x coordiante at 21h
+$White_y_05                               1 byte      ; White y coordinate at 22h
+
+; Flat Panel #06
+$Chromacity_Enable_06                     1 bit       ; enable or disable the chromacity bit
+$Override_EDID_Data_06                    1 bit       ; Override the chromaticity bit
+SKIP                                      6 bits      ; Reserved bits
+$Red_Green_06                             1 byte      ; Red/green chormaticity coordinates at 19h
+$Blue_White_06                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
+$Red_x_06                                 1 byte      ; Red x coordinate at 1Bh
+$Red_y_06                                 1 byte      ; Red y coordinate at 1Ch
+$Green_x_06                               1 byte      ; Green x coordinate at 1Dh
+$Green_y_06                               1 byte      ; Green y ccoordinate at 1Eh
+$Blue_x_06                                1 byte      ; Blue x coordinate at 1Fh
+$Blue_y_06                                1 byte      ; Blue y coordinate at 20h
+$White_x_06                               1 byte      ; White x coordiante at 21h
+$White_y_06                               1 byte      ; White y coordinate at 22h
+
+; Flat Panel #07
+$Chromacity_Enable_07                     1 bit       ; enable or disable the chromacity bit
+$Override_EDID_Data_07                    1 bit       ; Override the chromaticity bit
+SKIP                                      6 bits      ; Reserved bits
+$Red_Green_07                             1 byte      ; Red/green chormaticity coordinates at 19h
+$Blue_White_07                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
+$Red_x_07                                 1 byte      ; Red x coordinate at 1Bh
+$Red_y_07                                 1 byte      ; Red y coordinate at 1Ch
+$Green_x_07                               1 byte      ; Green x coordinate at 1Dh
+$Green_y_07                               1 byte      ; Green y ccoordinate at 1Eh
+$Blue_x_07                                1 byte      ; Blue x coordinate at 1Fh
+$Blue_y_07                                1 byte      ; Blue y coordinate at 20h
+$White_x_07                               1 byte      ; White x coordiante at 21h
+$White_y_07                               1 byte      ; White y coordinate at 22h
+
+; Flat Panel #08
+$Chromacity_Enable_08                     1 bit       ; enable or disable the chromacity bit
+$Override_EDID_Data_08                    1 bit       ; Override the chromaticity bit
+SKIP                                      6 bits      ; Reserved bits
+$Red_Green_08                             1 byte      ; Red/green chormaticity coordinates at 19h
+$Blue_White_08                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
+$Red_x_08                                 1 byte      ; Red x coordinate at 1Bh
+$Red_y_08                                 1 byte      ; Red y coordinate at 1Ch
+$Green_x_08                               1 byte      ; Green x coordinate at 1Dh
+$Green_y_08                               1 byte      ; Green y ccoordinate at 1Eh
+$Blue_x_08                                1 byte      ; Blue x coordinate at 1Fh
+$Blue_y_08                                1 byte      ; Blue y coordinate at 20h
+$White_x_08                               1 byte      ; White x coordiante at 21h
+$White_y_08                               1 byte      ; White y coordinate at 22h
+
+; Flat Panel #09
+$Chromacity_Enable_09                     1 bit       ; enable or disable the chromacity bit
+$Override_EDID_Data_09                    1 bit       ; Override the chromaticity bit
+SKIP                                      6 bits      ; Reserved bits
+$Red_Green_09                             1 byte      ; Red/green chormaticity coordinates at 19h
+$Blue_White_09                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
+$Red_x_09                                 1 byte      ; Red x coordinate at 1Bh
+$Red_y_09                                 1 byte      ; Red y coordinate at 1Ch
+$Green_x_09                               1 byte      ; Green x coordinate at 1Dh
+$Green_y_09                               1 byte      ; Green y ccoordinate at 1Eh
+$Blue_x_09                                1 byte      ; Blue x coordinate at 1Fh
+$Blue_y_09                                1 byte      ; Blue y coordinate at 20h
+$White_x_09                               1 byte      ; White x coordiante at 21h
+$White_y_09                               1 byte      ; White y coordinate at 22h
+
+; Flat Panel #10
+$Chromacity_Enable_10                     1 bit       ; enable or disable the chromacity bit
+$Override_EDID_Data_10                    1 bit       ; Override the chromaticity bit
+SKIP                                      6 bits      ; Reserved bits
+$Red_Green_10                             1 byte      ; Red/green chormaticity coordinates at 19h
+$Blue_White_10                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
+$Red_x_10                                 1 byte      ; Red x coordinate at 1Bh
+$Red_y_10                                 1 byte      ; Red y coordinate at 1Ch
+$Green_x_10                               1 byte      ; Green x coordinate at 1Dh
+$Green_y_10                               1 byte      ; Green y ccoordinate at 1Eh
+$Blue_x_10                                1 byte      ; Blue x coordinate at 1Fh
+$Blue_y_10                                1 byte      ; Blue y coordinate at 20h
+$White_x_10                               1 byte      ; White x coordiante at 21h
+$White_y_10                               1 byte      ; White y coordinate at 22h
+
+; Flat Panel #11
+$Chromacity_Enable_11                     1 bit       ; enable or disable the chromacity bit
+$Override_EDID_Data_11                    1 bit       ; Override the chromaticity bit
+SKIP                                      6 bits      ; Reserved bits
+$Red_Green_11                             1 byte      ; Red/green chormaticity coordinates at 19h
+$Blue_White_11                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
+$Red_x_11                                 1 byte      ; Red x coordinate at 1Bh
+$Red_y_11                                 1 byte      ; Red y coordinate at 1Ch
+$Green_x_11                               1 byte      ; Green x coordinate at 1Dh
+$Green_y_11                               1 byte      ; Green y ccoordinate at 1Eh
+$Blue_x_11                                1 byte      ; Blue x coordinate at 1Fh
+$Blue_y_11                                1 byte      ; Blue y coordinate at 20h
+$White_x_11                               1 byte      ; White x coordiante at 21h
+$White_y_11                               1 byte      ; White y coordinate at 22h
+
+; Flat Panel #12
+$Chromacity_Enable_12                     1 bit       ; enable or disable the chromacity bit
+$Override_EDID_Data_12                    1 bit       ; Override the chromaticity bit
+SKIP                                      6 bits      ; Reserved bits
+$Red_Green_12                             1 byte      ; Red/green chormaticity coordinates at 19h
+$Blue_White_12                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
+$Red_x_12                                 1 byte      ; Red x coordinate at 1Bh
+$Red_y_12                                 1 byte      ; Red y coordinate at 1Ch
+$Green_x_12                               1 byte      ; Green x coordinate at 1Dh
+$Green_y_12                               1 byte      ; Green y ccoordinate at 1Eh
+$Blue_x_12                                1 byte      ; Blue x coordinate at 1Fh
+$Blue_y_12                                1 byte      ; Blue y coordinate at 20h
+$White_x_12                               1 byte      ; White x coordiante at 21h
+$White_y_12                               1 byte      ; White y coordinate at 22h
+
+; Flat Panel #13
+$Chromacity_Enable_13                     1 bit       ; enable or disable the chromacity bit
+$Override_EDID_Data_13                    1 bit       ; Override the chromaticity bit
+SKIP                                      6 bits      ; Reserved bits
+$Red_Green_13                             1 byte      ; Red/green chormaticity coordinates at 19h
+$Blue_White_13                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
+$Red_x_13                                 1 byte      ; Red x coordinate at 1Bh
+$Red_y_13                                 1 byte      ; Red y coordinate at 1Ch
+$Green_x_13                               1 byte      ; Green x coordinate at 1Dh
+$Green_y_13                               1 byte      ; Green y ccoordinate at 1Eh
+$Blue_x_13                                1 byte      ; Blue x coordinate at 1Fh
+$Blue_y_13                                1 byte      ; Blue y coordinate at 20h
+$White_x_13                               1 byte      ; White x coordiante at 21h
+$White_y_13                               1 byte      ; White y coordinate at 22h
+
+; Flat Panel #14
+$Chromacity_Enable_14                     1 bit       ; enable or disable the chromacity bit
+$Override_EDID_Data_14                    1 bit       ; Override the chromaticity bit
+SKIP                                      6 bits      ; Reserved bits
+$Red_Green_14                             1 byte      ; Red/green chormaticity coordinates at 19h
+$Blue_White_14                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
+$Red_x_14                                 1 byte      ; Red x coordinate at 1Bh
+$Red_y_14                                 1 byte      ; Red y coordinate at 1Ch
+$Green_x_14                               1 byte      ; Green x coordinate at 1Dh
+$Green_y_14                               1 byte      ; Green y ccoordinate at 1Eh
+$Blue_x_14                                1 byte      ; Blue x coordinate at 1Fh
+$Blue_y_14                                1 byte      ; Blue y coordinate at 20h
+$White_x_14                               1 byte      ; White x coordiante at 21h
+$White_y_14                               1 byte      ; White y coordinate at 22h
+
+; Flat Panel #15
+$Chromacity_Enable_15                     1 bit       ; enable or disable the chromacity bit
+$Override_EDID_Data_15                    1 bit       ; Override the chromaticity bit
+SKIP                                      6 bits      ; Reserved bits
+$Red_Green_15                             1 byte      ; Red/green chormaticity coordinates at 19h
+$Blue_White_15                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
+$Red_x_15                                 1 byte      ; Red x coordinate at 1Bh
+$Red_y_15                                 1 byte      ; Red y coordinate at 1Ch
+$Green_x_15                               1 byte      ; Green x coordinate at 1Dh
+$Green_y_15                               1 byte      ; Green y ccoordinate at 1Eh
+$Blue_x_15                                1 byte      ; Blue x coordinate at 1Fh
+$Blue_y_15                                1 byte      ; Blue y coordinate at 20h
+$White_x_15                               1 byte      ; White x coordiante at 21h
+$White_y_15                               1 byte      ; White y coordinate at 22h
+
+; Flat Panel #16
+$Chromacity_Enable_16                     1 bit       ; enable or disable the chromacity bit
+$Override_EDID_Data_16                    1 bit       ; Override the chromaticity bit
+SKIP                                      6 bits      ; Reserved bits
+$Red_Green_16                             1 byte      ; Red/green chormaticity coordinates at 19h
+$Blue_White_16                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
+$Red_x_16                                 1 byte      ; Red x coordinate at 1Bh
+$Red_y_16                                 1 byte      ; Red y coordinate at 1Ch
+$Green_x_16                               1 byte      ; Green x coordinate at 1Dh
+$Green_y_16                               1 byte      ; Green y ccoordinate at 1Eh
+$Blue_x_16                                1 byte      ; Blue x coordinate at 1Fh
+$Blue_y_16                                1 byte      ; Blue y coordinate at 20h
+$White_x_16                               1 byte      ; White x coordiante at 21h
+$White_y_16                               1 byte      ; White y coordinate at 22h
+
+; Luminance and gamma data structure
+
+; Flat Panel #01
+$Override_LUM_Data_01                     1 bit       ; Override Luminance value enable bit
+$Override_Gamma_Data_01                   1 bit       ; Override gamma value enable bit.
+SKIP                                      6 bits      ; Reserved
+$MinLuminance_01                          2 bytes     ; Native minimum luminance
+$MaxFullLuminance_01                      2 bytes     ; Native maximum luminance
+$MaxLuminance_01                          2 bytes     ; Native Maximum Luminance (1% Rectangular Coverage)
+$Gamma_01                                 1 byte      ; Gamma Range from 00h to FFh.
+
+; Luminance data structure
+; Flat Panel #02
+$Override_LUM_Data_02                     1 bit       ; Override Luminance value enable bit
+$Override_Gamma_Data_02                   1 bit       ; Override gamma value enable bit.
+SKIP                                      6 bits      ; Reserved
+$MinLuminance_02                          2 bytes     ; Native minimum luminance
+$MaxFullLuminance_02                      2 bytes     ; Native maximum luminance
+$MaxLuminance_02                          2 bytes     ; Native Maximum Luminance (1% Rectangular Coverage)
+$Gamma_02                                 1 byte      ; Gamma Range from 00h to FFh.
+
+; Luminance data structure
+; Flat Panel #03
+$Override_LUM_Data_03                     1 bit       ; Override Luminance value enable bit
+$Override_Gamma_Data_03                   1 bit       ; Override gamma value enable bit.
+SKIP                                      6 bits      ; Reserved
+$MinLuminance_03                          2 bytes     ; Native minimum luminance
+$MaxFullLuminance_03                      2 bytes     ; Native maximum luminance
+$MaxLuminance_03                          2 bytes     ; Native Maximum Luminance (1% Rectangular Coverage)
+$Gamma_03                                 1 byte      ; Gamma Range from 00h to FFh.
+
+; Luminance data structure
+; Flat Panel #04
+$Override_LUM_Data_04                     1 bit       ; Override Luminance value enable bit
+$Override_Gamma_Data_04                   1 bit       ; Override gamma value enable bit.
+SKIP                                      6 bits      ; Reserved
+$MinLuminance_04                          2 bytes     ; Native minimum luminance
+$MaxFullLuminance_04                      2 bytes     ; Native maximum luminance
+$MaxLuminance_04                          2 bytes     ; Native Maximum Luminance (1% Rectangular Coverage)
+$Gamma_04                                 1 byte      ; Gamma Range from 00h to FFh.
+
+; Luminance data structure
+; Flat Panel #05
+$Override_LUM_Data_05                     1 bit       ; Override Luminance value enable bit
+$Override_Gamma_Data_05                   1 bit       ; Override gamma value enable bit.
+SKIP                                      6 bits      ; Reserved
+$MinLuminance_05                          2 bytes     ; Native minimum luminance
+$MaxFullLuminance_05                      2 bytes     ; Native maximum luminance
+$MaxLuminance_05                          2 bytes     ; Native Maximum Luminance (1% Rectangular Coverage)
+$Gamma_05                                 1 byte      ; Gamma Range from 00h to FFh.
+
+; Luminance data structure
+; Flat Panel #06
+$Override_LUM_Data_06                     1 bit       ; Override Luminance value enable bit
+$Override_Gamma_Data_06                   1 bit       ; Override gamma value enable bit.
+SKIP                                      6 bits      ; Reserved
+$MinLuminance_06                          2 bytes     ; Native minimum luminance
+$MaxFullLuminance_06                      2 bytes     ; Native maximum luminance
+$MaxLuminance_06                          2 bytes     ; Native Maximum Luminance (1% Rectangular Coverage)
+$Gamma_06                                 1 byte      ; Gamma Range from 00h to FFh.
+
+; Luminance data structure
+; Flat Panel #07
+$Override_LUM_Data_07                     1 bit       ; Override Luminance value enable bit
+$Override_Gamma_Data_07                   1 bit       ; Override gamma value enable bit.
+SKIP                                      6 bits      ; Reserved
+$MinLuminance_07                          2 bytes     ; Native minimum luminance
+$MaxFullLuminance_07                      2 bytes     ; Native maximum luminance
+$MaxLuminance_07                          2 bytes     ; Native Maximum Luminance (1% Rectangular Coverage)
+$Gamma_07                                 1 byte      ; Gamma Range from 00h to FFh.
+
+; Luminance data structure
+; Flat Panel #08
+$Override_LUM_Data_08                     1 bit       ; Override Luminance value enable bit
+$Override_Gamma_Data_08                   1 bit       ; Override gamma value enable bit.
+SKIP                                      6 bits      ; Reserved
+$MinLuminance_08                          2 bytes     ; Native minimum luminance
+$MaxFullLuminance_08                      2 bytes     ; Native maximum luminance
+$MaxLuminance_08                          2 bytes     ; Native Maximum Luminance (1% Rectangular Coverage)
+$Gamma_08                                 1 byte      ; Gamma Range from 00h to FFh.
+
+; Luminance data structure
+; Flat Panel #09
+$Override_LUM_Data_09                     1 bit       ; Override Luminance value enable bit
+$Override_Gamma_Data_09                   1 bit       ; Override gamma value enable bit.
+SKIP                                      6 bits      ; Reserved
+$MinLuminance_09                          2 bytes     ; Native minimum luminance
+$MaxFullLuminance_09                      2 bytes     ; Native maximum luminance
+$MaxLuminance_09                          2 bytes     ; Native Maximum Luminance (1% Rectangular Coverage)
+$Gamma_09                                 1 byte      ; Gamma Range from 00h to FFh.
+
+; Luminance data structure
+; Flat Panel #10
+$Override_LUM_Data_10                     1 bit       ; Override Luminance value enable bit
+$Override_Gamma_Data_10                   1 bit       ; Override gamma value enable bit.
+SKIP                                      6 bits      ; Reserved
+$MinLuminance_10                          2 bytes     ; Native minimum luminance
+$MaxFullLuminance_10                      2 bytes     ; Native maximum luminance
+$MaxLuminance_10                          2 bytes     ; Native Maximum Luminance (1% Rectangular Coverage)
+$Gamma_10                                 1 byte      ; Gamma Range from 00h to FFh.
+
+; Luminance data structure
+; Flat Panel #11
+$Override_LUM_Data_11                     1 bit       ; Override Luminance value enable bit
+$Override_Gamma_Data_11                   1 bit       ; Override gamma value enable bit.
+SKIP                                      6 bits      ; Reserved
+$MinLuminance_11                          2 bytes     ; Native minimum luminance
+$MaxFullLuminance_11                      2 bytes     ; Native maximum luminance
+$MaxLuminance_11                          2 bytes     ; Native Maximum Luminance (1% Rectangular Coverage)
+$Gamma_11                                 1 byte      ; Gamma Range from 00h to FFh.
+
+; Luminance data structure
+; Flat Panel #12
+$Override_LUM_Data_12                     1 bit       ; Override Luminance value enable bit
+$Override_Gamma_Data_12                   1 bit       ; Override gamma value enable bit.
+SKIP                                      6 bits      ; Reserved
+$MinLuminance_12                          2 bytes     ; Native minimum luminance
+$MaxFullLuminance_12                      2 bytes     ; Native maximum luminance
+$MaxLuminance_12                          2 bytes     ; Native Maximum Luminance (1% Rectangular Coverage)
+$Gamma_12                                 1 byte      ; Gamma Range from 00h to FFh.
+
+; Luminance data structure
+; Flat Panel #13
+$Override_LUM_Data_13                     1 bit       ; Override Luminance value enable bit
+$Override_Gamma_Data_13                   1 bit       ; Override gamma value enable bit.
+SKIP                                      6 bits      ; Reserved
+$MinLuminance_13                          2 bytes     ; Native minimum luminance
+$MaxFullLuminance_13                      2 bytes     ; Native maximum luminance
+$MaxLuminance_13                          2 bytes     ; Native Maximum Luminance (1% Rectangular Coverage)
+$Gamma_13                                 1 byte      ; Gamma Range from 00h to FFh.
+
+; Luminance data structure
+; Flat Panel #14
+$Override_LUM_Data_14                     1 bit       ; Override Luminance value enable bit
+$Override_Gamma_Data_14                   1 bit       ; Override gamma value enable bit.
+SKIP                                      6 bits      ; Reserved
+$MinLuminance_14                          2 bytes     ; Native minimum luminance
+$MaxFullLuminance_14                      2 bytes     ; Native maximum luminance
+$MaxLuminance_14                          2 bytes     ; Native Maximum Luminance (1% Rectangular Coverage)
+$Gamma_14                                 1 byte      ; Gamma Range from 00h to FFh.
+
+; Luminance data structure
+; Flat Panel #15
+$Override_LUM_Data_15                     1 bit       ; Override Luminance value enable bit
+$Override_Gamma_Data_15                   1 bit       ; Override gamma value enable bit.
+SKIP                                      6 bits      ; Reserved
+$MinLuminance_15                          2 bytes     ; Native minimum luminance
+$MaxFullLuminance_15                      2 bytes     ; Native maximum luminance
+$MaxLuminance_15                          2 bytes     ; Native Maximum Luminance (1% Rectangular Coverage)
+$Gamma_15                                 1 byte      ; Gamma Range from 00h to FFh.
+
+; Luminance data structure
+; Flat Panel #16
+$Override_LUM_Data_16                     1 bit       ; Override Luminance value enable bit
+$Override_Gamma_Data_16                   1 bit       ; Override gamma value enable bit.
+SKIP                                      6 bits      ; Reserved
+$MinLuminance_16                          2 bytes     ; Native minimum luminance
+$MaxFullLuminance_16                      2 bytes     ; Native maximum luminance
+$MaxLuminance_16                          2 bytes     ; Native Maximum Luminance (1% Rectangular Coverage)
+$Gamma_16                                 1 byte      ; Gamma Range from 00h to FFh.
+
+;==============================================================================
+; Block 51 - Fixed Mode
+;------------------------------------------------------------------------------
+
+SKIP                                      3 bytes     ; Skip block ID and size
+
+$Feature_Enable                           1 byte      ; Enable or disable the feature
+$X_res                                    4 bytes     ; X resolution
+$Y_res                                    4 bytes     ; Y resolution
+
+EndStruct
+
+;==============================================================================
+; List Definitions
+;------------------------------------------------------------------------------
+
+List    &Pwr_Pref_List
+  Selection       0x01,       "1 - Maximum Quality with No DPST"
+  Selection       0x02,       "2"
+  Selection       0x03,       "3"
+  Selection       0x04,       "4"
+  Selection       0x05,       "5"
+  Selection       0x06,       "6 - Maximum Battery"
+EndList
+
+; This is the list for the selection of the Device Class
+List    &Int_EFP_Device_Type_List
+  Selection       0x0000,     "No Device"
+  Selection       0x68C6,     "Integrated DisplayPort Only"
+  Selection       0x60D6,     "Integrated DisplayPort with HDMI/DVI Compatible"
+  Selection       0x68D6,     "Integrated DisplayPort with DVI Compatible"
+  Selection       0x60D2,     "Integrated HDMI/DVI"
+  Selection       0x68D2,     "Integrated DVI Only"
+EndList
+
+; This is the list for the selection of the Device Class for DDI-E only.
+List    &Int_EFP4_Device_Type_List
+  Selection       0x0000,     "No Device"
+  Selection       0x68C6,     "Integrated DisplayPort Only"
+EndList
+
+List    &Disabled_Enabled_List
+  Selection       0,          "Disabled"
+  Selection       1,          "Enabled"
+EndList
+
+List    &Supported_List
+  Selection       0,          "Not supported"
+  Selection       1,          "Supported"
+EndList
+List    &Aggressiveness_Level_Profile
+  Selection       0x00,       "Minimum"
+  Selection       0x01,       "Moderate"
+  Selection       0x02,       "High"
+EndList    
+List    &Int_EFP_Port_List
+  Selection       0x00,       "N/A"
+  Selection       0x01,       "HDMI-B"
+  Selection       0x02,       "HDMI-C"
+  Selection       0x03,       "HDMI-D"
+  Selection       0x07,       "DisplayPort-B"
+  Selection       0x08,       "DisplayPort-C"
+  Selection       0x09,       "DisplayPort-D"
+EndList
+
+List    &Int_EFP4_Port_List
+  Selection       0x00,       "N/A"
+  Selection       0x0B,       "DisplayPort-E"
+EndList
+
+List    &eDP_Port_List
+  Selection       0x0A,       "DisplayPort-A"
+  ;Selection      0x09,       "DisplayPort-D"
+EndList
+
+List    &Int_DP_AUX_Channel_List
+  Selection       0x00,       "N/A"
+  Selection       0x40,       "AUX Channel A"
+  Selection       0x10,       "AUX Channel B"
+  Selection       0x20,       "AUX Channel C"
+  Selection       0x30,       "AUX Channel D"
+EndList
+
+List    &Int_eDP_AUX_Channel_List
+  Selection       0x40,       "AUX Channel A"
+  ;Selection      0x30,       "AUX Channel D"
+EndList
+
+List    &GPIO_Pin_List
+  Selection       0x00,       "N/A"
+  Selection       0x01,       "Pin-Pair #1"
+  Selection       0x02,       "Pin-Pair #2"
+  Selection       0x03,       "Pin-Pair #3"
+EndList  
+
+List    &GMBus_Speed_List
+  Selection       0x01,       "50 KHz"
+  Selection       0x00,       "100 KHz"
+  Selection       0x02,       "400 KHz"
+  Selection       0x03,       "1 MHz"
+EndList
+
+List    &Inv_Type_List
+  Selection       0x00,       "None/External"
+  Selection       0x02,       "PWM"
+EndList
+
+List    &Inv_Polarity_List
+  Selection       0x00,       "Normal"
+  Selection       0x01,       "Inverted"
+EndList
+
+List    &LFP_Config_List
+  Selection       0x0000,     "No Local Flat Panel"
+  Selection       0x1806,     "eDP (LFP Driven by Int-DisplayPort Encoder)"
+EndList
+
+List    &No_Yes_List
+  Selection       0,          "No"
+  Selection       1,          "Yes"
+EndList
+
+List    &Yes_No_List
+  Selection       0,          "Yes"
+  Selection       1,          "No"
+EndList
+
+List    &Off_On_List
+  Selection       0,          "Off"
+  Selection       1,          "On"
+EndList
+
+List    &OS_Driver_List
+  Selection       0,          "OS Default Algorithm"
+  Selection       1,          "Driver Algorithm"
+EndList
+
+List    &eDP_Panel_Color_Depth_List
+  Selection       0x00,       "18-bit Color Depth"
+  Selection       0x01,       "24-bit Color Depth"
+  Selection       0x02,       "30-bit Color Depth"
+  Selection       0x03,       "36-bit Color Depth"
+EndList
+
+List    &Panel_Rotation_List
+  Selection       0x00,       "  0 Degree"
+  ;Selection       0x01,       " 90 Degree"
+  Selection       0x02,       "180 Degree"
+  ;Selection       0x03,       "270 Degree"
+EndList
+
+List    &eDP_Link_DataRate_List
+  Selection       0x00,       "1.62 Gbps"
+  Selection       0x01,       "2.70 Gbps"
+  Selection       0x02,       "5.40 Gbps"
+EndList
+
+List    &eDP_Link_LaneCount_List
+  Selection       0x00,       "x1"
+  Selection       0x01,       "x2"
+  Selection       0x03,       "x4"
+EndList
+
+List    &DP_eDP_Link_PreEmp_List
+  Selection       0x00,       "Level-0"
+  Selection       0x01,       "Level-1"
+  Selection       0x02,       "Level-2"
+  Selection       0x03,       "Level-3"
+EndList
+
+List    &eDP_Link_VSwing_List
+  Selection       0x00,       "Swing-0"
+  Selection       0x01,       "Swing-1"
+  Selection       0x02,       "Swing-2"
+  Selection       0x03,       "Swing-3"
+EndList
+
+List    &DP_Link_VSwing_List
+  Selection       0x00,       "Swing-0"
+  Selection       0x01,       "Swing-1"
+  Selection       0x02,       "Swing-2"
+EndList
+
+List    &IBoost_Magnitude_List
+  Selection       0,          "0x1"
+  Selection       1,          "0x3"
+  Selection       2,          "0x7"
+EndList
+
+List    &Panel_List
+  Selection       0x00,       "PANEL #01"
+  Selection       0x01,       "PANEL #02"
+  Selection       0x02,       "PANEL #03"
+  Selection       0x03,       "PANEL #04"
+  Selection       0x04,       "PANEL #05"
+  Selection       0x05,       "PANEL #06"
+  Selection       0x06,       "PANEL #07"
+  Selection       0x07,       "PANEL #08"
+  Selection       0x08,       "PANEL #09"
+  Selection       0x09,       "PANEL #10"
+  Selection       0x0A,       "PANEL #11"
+  Selection       0x0B,       "PANEL #12"
+  Selection       0x0C,       "PANEL #13"
+  Selection       0x0D,       "PANEL #14"
+  Selection       0x0E,       "PANEL #15"
+  Selection       0x0F,       "PANEL #16"
+  Selection       0xFF,       "PANEL #FF"
+EndList
+
+List    &eDP_VSwing_Preemph_table_List
+  Selection       0x00,       "Low Power VSwing/Pre-Emphasis Table"
+  Selection       0x01,       "Default VSwing/Pre-Emphasis Table"
+EndList
+
+List    &Under_Over_List
+  Selection       0x0,        "Enable Underscan and Overscan modes"
+  Selection       0x1,        "Enable only overscan modes"
+  Selection       0x2,        "Enable only underscan modes"
+EndList
+
+List    &DPS_Panel_Type_List
+  Selection       0x00,       "Static DRRS"
+  Selection       0x02,       "Seamless"
+EndList
+
+List    &Blt_Control_Type_List
+  Selection       0x01,       "CCFL Backlight"
+  Selection       0x02,       "LED Backlight"
+EndList
+
+List    &Hdmi_LS_List
+  Selection       0x00,       "400mV 0.0dB"
+  Selection       0x01,       "400mV 3.5dB"
+  Selection       0x02,       "400mV 6.0dB"
+  Selection       0x03,       "450mV 0.0dB"
+  Selection       0x04,       "600mV 0.0dB"
+  Selection       0x05,       "600mV 2.5dB"
+  Selection       0x06,       "600mV 4.5dB"
+  Selection       0x07,       "800mV 0.0dB"
+  Selection       0x08,       "800mV 2.0dB"
+  Selection       0x09,       "1000mV 2.0dB"
+  Selection       0x0A,       "1200mV 0.0dB"
+EndList
+
+List    &wait_line_link
+  Selection       0x00,       "0 lines to wait"
+  Selection       0x01,       "1 lines to wait"
+  Selection       0x02,       "4 lines to wait"
+  Selection       0x03,       "8 lines to wait"
+EndList
+
+List    &PrimaryDisplayList
+  Selection       0x08,       "LFP"
+  Selection       0x04,       "EFP"
+  Selection       0x40,       "EFP2"
+  Selection       0x20,       "EFP3"
+  Selection       0x10,       "EFP4"
+  Selection       0x00,       "None"
+EndList
+
+List    &SecondaryDisplayList
+  Selection       0x04,       "EFP"
+  Selection       0x40,       "EFP2"
+  Selection       0x20,       "EFP3"
+  Selection       0x10,       "EFP4"
+  Selection       0x00,       "None"
+EndList
+
+List    &Hdmi2SupportOptions
+  Selection       0x00,       "Disabled"
+  Selection       0x01,       "Enabled"
+EndList
+
+List    &PsrWakeupTimeOptions
+  Selection       0x00,       "500 usec"
+  Selection       0x01,       "100 usec"
+  Selection       0x02,       "2.5 msec"
+  Selection       0x03,       "0 (Skip)"
+EndList
+
+List    &Pwm_Source_List
+  ; Selection       0x0,        "PWM From PMIC"
+  ; Selection       0x1,        "PWM From LPSS"
+  Selection       0x2,        "PWM From Display Engine"
+  ; Selection       0x3,        "PWM From LCD Panel"
+  Selection       0x4,        "Panel driver interface (OLED)"
+  Selection       0x5,        "VESA eDP AUX Interface"
+EndList
+
+List    &Dp_Port_Trace_Length_List
+  Selection       0x0,        "RVP Default"
+  Selection       0x1,        "Short trace length"
+  Selection       0x2,        "Long trace length"
+EndList
+
+;==============================================================================
+; Page Definitions
+;------------------------------------------------------------------------------
+
+BeginInfoBlock
+PPVer    "3.00"
+Image EOF Thru EOF At EOF
+EndInfoBlock
+
+;==============================================================================
+; Page - Revision History
+;------------------------------------------------------------------------------
+Page      "VBT Information"
+  Title     "PLATFORM : Coffeelake"
+  Title     "VBT version: 228"
+
+  #IF       ($LFP_Device_Class == 0x1806)
+    Title     "Supported LFP type: eDP"
+  #ELSE
+    Title     "Supported LFP type: No LFP"
+  #ENDIF
+EndPage   ; Revision History
+
+;==============================================================================
+; Page - General Platform Configuration
+;------------------------------------------------------------------------------
+Page      "General Platform Configuration"
+
+  Combo     $Embedded_Platform, "Embedded Platform: ", &No_Yes_List,
+  Help      "This feature allows a selectable option to determine whether "
+            "the platform is embedded design or not."
+
+  Combo     $bmp_Dynamic_CdClock_Supported, "Dynamic CD Clock Support: ", &Disabled_Enabled_List,
+  Help      "Enabling this feature configures optimal CD Clock frequency at run time .\n "
+
+  Combo     $Kvmr_Session_Enable, "KVMR Session/Fake DVI Display Support: ", &Disabled_Enabled_List,
+  Help      "When enabled, GOP and Gfx driver will keep a display pipe enable even if no displays are attached.\n"
+            "When no displays are attached, GOP or Gfx driver will check VBT settings for EFP1/2/3 for DVI support.\n"
+            "If any EFP setting supports DVI display type, GOP/driver will enable that port.\n"
+            "If none of the EFP settings support DVI display type, GOP/driver will enable DVI on port-B by default."
+
+EndPage   ; General platform Configuration
+
+;==============================================================================
+; Page - UEFI GOP Driver Configuration
+;------------------------------------------------------------------------------
+Page      "UEFI GOP Driver Configuration"
+
+  Combo     $Hotplug_Support_Enb, "Hot Plug Support:", &Disabled_Enabled_List,
+  Help      "This feature is to enable/disable Hot Plug Support for EFP displays in GOP driver."
+
+  Title     "Child Device Configuration"
+  Link      "Child Device List", "Child Device List"
+
+  Title     "Fixed Mode"
+  Link      "Fixed Mode Feature", "Fixed Mode Feature"
+
+  ;==============================================================================
+  ; Page - Child Device List
+  ;------------------------------------------------------------------------------
+
+  Page      "Child Device List"
+    Link      "Close Table" , ".."
+    Title     "A child device is a combination of one or more displays. Select the child devices that the GOP driver should enumerate if detected"
+    Title     "Note: The child devices are listed here in decreasing order of priority. In case the system BIOS does not specify the child device to start, then GOP driver selects the highest priority child device"
+
+    Title     "Child Device 1"
+    Combo     $ChildDevice1Primary, "\tPrimary display: " , &PrimaryDisplayList,
+    Help      "Primary Display\r\n"
+    Combo     $ChildDevice1Secondary, "\tSecondary display: " , &SecondaryDisplayList,
+    Help      "Secondary Display\r\n"
+
+    Title     " "
+    Title     "Child Device 2"
+    Combo     $ChildDevice2Primary, "\tPrimary display: " , &PrimaryDisplayList,
+    Help      "Primary Display\r\n"
+    Combo     $ChildDevice2Secondary, "\tSecondary display: " , &SecondaryDisplayList,
+    Help      "Secondary Display\r\n"
+
+    Title     " "
+    Title     "Child Device 3"
+    Combo     $ChildDevice3Primary, "\tPrimary display: " , &PrimaryDisplayList,
+    Help      "Primary Display\r\n"
+    Combo     $ChildDevice3Secondary, "\tSecondary display: " , &SecondaryDisplayList,
+    Help      "Secondary Display\r\n"
+
+    Title     " "
+    Title     "Child Device 4"
+    Combo     $ChildDevice4Primary, "\tPrimary display: " , &PrimaryDisplayList,
+    Help      "Primary Display\r\n"
+    Combo     $ChildDevice4Secondary, "\tSecondary display: " , &SecondaryDisplayList,
+    Help      "Secondary Display\r\n"
+
+    Title     " "
+    Title     "Child Device 5"
+    Combo     $ChildDevice5Primary, "\tPrimary display: " , &PrimaryDisplayList,
+    Help      "Primary Display\r\n"
+    Combo     $ChildDevice5Secondary, "\tSecondary display: " , &SecondaryDisplayList,
+    Help      "Secondary Display\r\n"
+
+    Title     " "
+    Title     "Child Device 6"
+    Combo     $ChildDevice6Primary, "\tPrimary display: " , &PrimaryDisplayList,
+    Help      "Primary Display\r\n"
+    Combo     $ChildDevice6Secondary, "\tSecondary display: " , &SecondaryDisplayList,
+    Help      "Secondary Display\r\n"
+
+    Title     " "
+    Title     "Child Device 7"
+    Combo     $ChildDevice7Primary, "\tPrimary display: " , &PrimaryDisplayList,
+    Help      "Primary Display\r\n"
+    Combo     $ChildDevice7Secondary, "\tSecondary display: " , &SecondaryDisplayList,
+    Help      "Secondary Display\r\n"
+
+    Title     " "
+    Title     "Child Device 8"
+    Combo     $ChildDevice8Primary, "\tPrimary display: " , &PrimaryDisplayList,
+    Help      "Primary Display\r\n"
+    Combo     $ChildDevice8Secondary, "\tSecondary display: " , &SecondaryDisplayList,
+    Help      "Secondary Display\r\n"
+
+    Title     " "
+    Title     "Child Device 9"
+    Combo     $ChildDevice9Primary, "\tPrimary display: " , &PrimaryDisplayList,
+    Help      "Primary Display\r\n"
+    Combo     $ChildDevice9Secondary, "\tSecondary display: " , &SecondaryDisplayList,
+    Help      "Secondary Display\r\n"
+
+    Title     " "
+    Title     "Child Device 10"
+    Combo     $ChildDevice10Primary, "\tPrimary display: " , &PrimaryDisplayList,
+    Help      "Primary Display\r\n"
+    Combo     $ChildDevice10Secondary, "\tSecondary display: " , &SecondaryDisplayList,
+    Help      "Secondary Display\r\n"
+
+    Title     " "
+    Title     "Child Device 11"
+    Combo     $ChildDevice11Primary, "\tPrimary display: " , &PrimaryDisplayList,
+    Help      "Primary Display\r\n"
+    Combo     $ChildDevice11Secondary, "\tSecondary display: " , &SecondaryDisplayList,
+    Help      "Secondary Display\r\n"
+
+    Title     " "
+    Title     "Child Device 12"
+    Combo     $ChildDevice12Primary, "\tPrimary display: " , &PrimaryDisplayList,
+    Help      "Primary Display\r\n"
+    Combo     $ChildDevice12Secondary, "\tSecondary display: " , &SecondaryDisplayList,
+    Help      "Secondary Display\r\n"
+
+    Title     " "
+    Title     "Child Device 13"
+    Combo     $ChildDevice13Primary, "\tPrimary display: " , &PrimaryDisplayList,
+    Help      "Primary Display\r\n"
+    Combo     $ChildDevice13Secondary, "\tSecondary display: " , &SecondaryDisplayList,
+    Help      "Secondary Display\r\n"
+
+    Title     " "
+    Title     "Child Device 14"
+    Combo     $ChildDevice14Primary, "\tPrimary display: " , &PrimaryDisplayList,
+    Help      "Primary Display\r\n"
+    Combo     $ChildDevice14Secondary, "\tSecondary display: " , &SecondaryDisplayList,
+    Help      "Secondary Display\r\n"
+
+    Title     " "
+    Title     "Child Device 15"
+    Combo     $ChildDevice15Primary, "\tPrimary display: " , &PrimaryDisplayList,
+    Help      "Primary Display\r\n"
+    Combo     $ChildDevice15Secondary, "\tSecondary display: " , &SecondaryDisplayList,
+    Help      "Secondary Display\r\n"
+
+    Title     " "
+    Title     "Child Device 16"
+    Combo     $ChildDevice16Primary, "\tPrimary display: " , &PrimaryDisplayList,
+    Help      "Primary Display\r\n"
+    Combo     $ChildDevice16Secondary, "\tSecondary display: " , &SecondaryDisplayList,
+    Help      "Secondary Display\r\n"
+  EndPage   ; "Child Device List"
+
+  ;============================================================================
+  ; Page - Fixed Mode Configuration
+  ;----------------------------------------------------------------------------
+
+  Page      "Fixed Mode Feature"
+    Link      "Close Table", ".."
+
+    Combo     $Feature_Enable, "Enable Feature:",  &No_Yes_List,
+    Help      "Fixed Mode Feature allows user to fix a mode during POST such that only that particular mode will be always set."
+              "This field specifies if user wants to enable/disable the feature."
+              "When enabled user is expected to provide a valid input."
+
+    EditNum   $X_res, "Horizontal Pixels:", DEC,
+    Help      "This value specifies the horizontal pixels of the mode."
+              "It should be always less than or equal to the native horizontal resolution."
+
+    EditNum   $Y_res, "Vertical Pixels:", DEC,
+    Help      "This value specifies the vertical pixels of the mode."
+              "It should be always less than or equal to the native vertical resolution."
+
+  EndPage
+
+EndPage   ; "UEFI GOP Driver Configuration"
+
+;============================================================================
+; Page - Windows Graphics driver Configuration
+;----------------------------------------------------------------------------
+Page      "Windows Graphics driver Configuration"
+
+  Link      "General Features" , "General Features"
+  Link      "Display Features" , "Display Features"
+  Link      "Power Conservation" , "Power Conservation"
+
+  Page      "General Features"
+    Link      "Close Table" , ".."
+
+    EditNum   $VBT_Customization_Version, "VBT Customization Version:", DEC,
+    Help      "This feature allows the OEM to have a customized VBT version number. "
+              "The permissible values for VBT Customization version is from 0 to 255."
+
+    Combo     $Disable_DisplayEnum, "Display subsystem disabled:", &No_Yes_List,
+    Help      "This option allows windows driver to be aware that display subsystem is not needed. "
+              "Driver could choose not to activate any display hardware if this bit is set. "
+              "However this is only valid if theres no LFP on the system or no Force projectable connector. "
+              "Please see driver documentation for detailed driver behaviour."
+
+  EndPage   ; General Features"
+
+  Page      "Display Features"
+    Link      "Close Table" , ".."
+
+    Combo     $CUI_Maintain_Aspect, "Enable 'Maintain Aspect Ratio':", &No_Yes_List,
+    Help      "This feature allows the OEM to enable or disable the 'Maintain Aspect Ratio' feature. "
+              "When the option is set to Yes, the feature will be enabled and CUI will show "
+              "for end user selection 'Maintain Aspect Ratio'. When the option is set to No, "
+              "the complete 'Maintain Aspect Ratio' feature will be disabled."
+
+    Title     "Legacy Monitor Mode Limit:"
+
+    EditNum   $Legacy_Monitor_Max_X, "    Maximum X Resolution (Pixels):", DEC,
+    Help      "This feature allows the limiting of selectable display modes "
+              "when a legacy monitor is detected. The maximum resolution is specified by "
+              "a maximum number of horizontal active pixels.\r\n"
+              "Note: A legacy monitor is defined as a monitor with no DDC available."
+
+    EditNum   $Legacy_Monitor_Max_Y, "    Maximum Y Resolution (Pixels):", DEC,
+    Help      "This feature allows the limiting of selectable display modes "
+              "when a legacy monitor is detected.  The maximum resolution is specified by "
+              "a maximum number of vertical active pixels.\r\n"
+              "Note: A legacy monitor is defined as a monitor with no DDC available."
+
+    EditNum   $Legacy_Monitor_Max_RR, "    Maximum Refresh Rate (Hz):", DEC,
+    Help      "This feature allows the limiting of selectable display modes "
+              "when a legacy monitor is detected.  The maximum refresh rate "
+              "is specified in Hz.\r\n"
+              "Note: A legacy monitor is defined as a monitor with no DDC available."
+
+    Title     "Rotation Configuration:"
+
+    Combo     $Rot_Enable, "    Enable Rotation:", &No_Yes_List,
+    Help      "This feature when set to yes, will allow for rotation. "
+              "Otherwise, when the feature is set to no, "
+              "the rotation functionality will be disabled within the driver."
+
+  EndPage   ; Display features
+
+  Page      "Power Conservation"
+    Link      "Close Table" , ".."
+
+    Title     "    "
+
+    Combo     $PC_Fields_Enable, "  PC Features Control Options", &Disabled_Enabled_List,
+    Help      "This feature determines the validity of the following PC Features Control Options.\r\n\r\n"
+              "1.  Intel Rapid Memory Power Management (RMPM)\r\n"
+              "2.  Intel Smart 2D Display Technology (S2DDT)\r\n"
+              "3.  DxgkDDI Backlight Control (DxgkDdiBLC) (Mobile only)\r\n"
+              "4.  Graphics Render Standby (RS)\r\n"
+              "5.  Intel Turbo Boost Technology\r\n"
+              "6.  Dynamic Frames Per Second (DFPS)\r\n"
+              "Note: Enable and Save the changes to display all the PC Features Control Options\r\n"
+
+    Combo     $PM_RMPM_Enable, "\tIntel Rapid Memory Power Management (RMPM)", &Disabled_Enabled_List,
+    Help      "This feature determines whether Intel Rapid Memory Power Management (RMPM) is to be enabled. "
+
+    Combo     $PM_S2DDT_Enable, "\tIntel Smart 2D Display Technology (S2DDT)", &Disabled_Enabled_List,
+    Help      "This feature determines whether Intel Smart 2D Display Technology (S2DDT) is to be enabled. "
+
+    Combo     $PM_BLC_Enable, "\tDxgkDDI Brightness Control Method (Mobile only)", &Disabled_Enabled_List,
+    Help      "This option determines whether the Vista, Win7, and future version DxgkDDI LFP Brightness Control method is to be enabled. "
+
+    Combo     $PM_RS_Enable, "\tGraphics Render Standby (RS)", &Disabled_Enabled_List,
+    Help      "This feature determines whether Graphics Render Standby (RS)is to be enabled."
+
+    Combo     $PM_Turbo_Enable, "\tIntel Turbo Boost Technology", &Disabled_Enabled_List,
+    Help      "This feature determines whether Intel Turbo Boost Technology is to be enabled."
+
+    Combo     $Dynamic_FPS_Enable, "\tDynamic Frames Per Second (DFPS)", &Disabled_Enabled_List,
+    Help      "This feature determines whether Dynamic Frames Per Second is to be enabled."
+
+    Page      "ADB Response Data (Mobile only)"
+      Link      "Close Table" , ".."
+
+      Table     $ALS_Response_Data " ADB Response Data (Mobile only)",
+      Column    "Backlight Adjust", 2 bytes, EHEX
+      Column    "Lux", 2 bytes, EHEX,
+      Help      "This feature defines values used to calibrate the Intel Automatic Display Brightness policy's "
+                "response to account for specific hardware implementation details such as sensor placement and optics. "
+                "Up to five points can be specified, where each point indicates a given ambient light illuminance "
+                "to display luminance mapping specified as (<%BacklightAdjust>, <Lux>).  Points should be "
+                "listed in monotonically increasing order by ambient light illuminance (lux). "
+                "A minimum of two points are required (min and max)."
+    EndPage   ; "ADB Response Data"
+  EndPage   ; Power Conservation
+EndPage   ; "Windows Graphics driver Configuration"
+
+;==============================================================================
+; Page - Display Configurations
+;------------------------------------------------------------------------------
+Page      "Integrated Display Configuration"
+  Title     "Integrated DP, HDMI, DVI, eDP Configuration"
+
+  Link      "LFP Configuration", "LFP Configuration"
+  Link      "Integrated DisplayPort/HDMI Configuration with External Connectors", "Integrated DisplayPort/HDMI Configuration with External Connectors"
+
+  ;==============================================================================
+  ; Page - LFP Configuration
+  ;----------------------------------------------------------------------------
+
+  Page      "LFP Configuration"
+    Link      "Close Table", ".."
+    Combo     $LFP_Device_Class , "Active Local Flat Panel Configuration", &LFP_Config_List,
+    Help      "This feature is for configuring LFP usage.\r\n"
+              "Note: To enable 4 lane eDP panels, make sure that the EFP4 settings in VBT has no device."
+
+    Title     "    "
+    Combo     $Int_eDP_Port, "Select Output port: ", &eDP_Port_List,
+    Help      "This feature, when enabled, will activate support for an eDP. "
+              "Driver also uses the same data for enabling eDP on the selected port.\r\n\r\n"
+              "Note: For both mobile and desktop CFL boards, eDP is supported on Port A only."
+
+    Combo     $Int_LFP_AUX_Channel, "Select AUX Channel: ", &Int_eDP_AUX_Channel_List,
+    Help      "This feature specifies the AUX Channel for embedded-DisplayPort. "
+              "This field is valid only if integrated eDP is selected for Device Type."
+
+    Title     "    "
+    Combo     $bmp_Panel_type, "Select Panel Type:", &Panel_List,
+    Help      "Select the Local Flat Panel (LFP) which display driver will enable.\r\n\r\n"
+              "If panel type is selected as 0xFF, Graphics Software will populate panel index by comparing actual PNP ID Data from panel to that of PNP ID Data for each panel in VBT."
+              "The panel index for which PNP ID Data matches with actual connected panel PNP ID Data is used by driver for all further references. EDID Read is assumed to be enabled if panel index is selected as 0xFF."
+              "Default LFP parameter values:\r\n"
+              "\tPANEL #01: 640x480 LFP\r\n"
+              "\tPANEL #02: 800x600 LFP\r\n"
+              "\tPANEL #03: 1024x768 LFP\r\n"
+              "\tPANEL #04: 1280x1024 LFP\r\n "
+              "\tPANEL #05: 1400x1050 Reduced Blanking LFP\r\n"
+              "\tPANEL #06: 1400x1050 Non-Reduced Blanking LFP\r\n"
+              "\tPANEL #07: 1600x1200 LFP\r\n"
+              "\tPANEL #08: 1280x768 LFP\r\n"
+              "\tPANEL #09: 1680x1050 LFP\r\n"
+              "\tPANEL #10: 1920x1200 LFP\r\n"
+              "\tPANEL #11: 1440x900 LFP\r\n"
+              "\tPANEL #12: 1600x900 LFP\r\n"
+              "\tPANEL #13: 1024x768 LFP\r\n"
+              "\tPANEL #14: 1280x800 LFP\r\n"
+              "\tPANEL #15: 1920x6108 LFP\r\n"
+              "\tPANEL #16: 2048x1536"
+
+    Combo     $bmp_Panel_EDID, "Local Flat Panel (LFP) EDID Support: ", &Disabled_Enabled_List,
+    Help      "This feature, when enabled, will activate support for a LFP with an EDID. "
+              "The GOP and driver will load the EDID and "
+              "use its data to set appropriate timing on current panel. "
+              "If disabled, there will be no attempt to read an EDID and "
+              "other methods will be used to set panel timing."
+
+
+    Combo     $LFP_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List,
+    Help      "This feature, when enabled, will set lane reversal bit for Selected Port "
+
+    Combo     $LFP_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List,
+    Help      "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels"
+
+    Combo     $Int_LFP_Dp_Boost_Magnitude, "\tIBoost Magnitude: ", &IBoost_Magnitude_List,
+    Help      "This field is applicable only if IBoost is enabled for the selected port."
+              "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7"
+
+    Combo     $Int_LFP_Dual_Pipe_Ganged_Enable, "Dual Port Ganged Support for eDP: ", &Disabled_Enabled_List,
+    Help      "This feature allows for configuring two different ports to be used for a single eDP panel.\n"
+              "When enabled, the end user can specify a slave port to be connected along with DDI-A to enable a higher resolution eDP panel.\n"
+              "When disabled, eDP display will always use DDI-A"
+
+    Combo     $Int_LFP_Slave_Dvo_Port, "\tSlave Port for Dual Port Ganged eDP Display: ", &Int_EFP_Port_List,
+    Help      "This field provides the slave port to be used along with master eDP port in case of dual port ganged support for eDP.\n"
+              "This field will be ignored by the software if dual port ganged support for eDP is disabled."
+
+    Title     "    "
+
+    Link      "Panel #01 ", "Panel #01 "
+    Link      "Panel #02 ", "Panel #02 "
+    Link      "Panel #03 ", "Panel #03 "
+    Link      "Panel #04 ", "Panel #04 "
+    Link      "Panel #05 ", "Panel #05 "
+    Link      "Panel #06 ", "Panel #06 "
+    Link      "Panel #07 ", "Panel #07 "
+    Link      "Panel #08 ", "Panel #08 "
+    Link      "Panel #09 ", "Panel #09 "
+    Link      "Panel #10 ", "Panel #10 "
+    Link      "Panel #11 ", "Panel #11 "
+    Link      "Panel #12 ", "Panel #12 "
+    Link      "Panel #13 ", "Panel #13 "
+    Link      "Panel #14 ", "Panel #14 "
+    Link      "Panel #15 ", "Panel #15 "
+    Link      "Panel #16 ", "Panel #16 "
+
+    ;==============================================================================
+    ; Page - Panel #01 (640x480 LVDS) Flat Panel parameters
+    ;------------------------------------------------------------------------------
+    Page      "Panel #01 "
+      EditText  $Panel_Name_01, "LFP panel name:",
+      Help      "This feature defines the LFP panel name, used by driver only. "
+                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."
+
+      EditNum   $Panel_Width_01, "LFP Width:", DEC,
+      Help      "This value specifies the LFP pixel width for this panel type."
+
+      EditNum   $Panel_Height_01, "LFP Height:", DEC,
+      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."
+
+      Combo     $eDP_VSwingPreEmph_01, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
+      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
+                "For Coffeelake, based on the selection respective table will be used.\r\n"
+                "Tables for Coffeelake: \r\n"
+                "Low Power VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
+                "\r\n\r\n"
+
+                "Default VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"
+
+      Combo     $eDP_Panel_Color_Depth_01, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
+      Help      "This feature specifies the color depth of eDP panel used."
+
+      Combo     $Panel_Rotation_01, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
+      TitleB    "eDP Spread Spectrum Clock Features"
+      Combo     $Enable_SSC01, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
+      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."
+
+      TitleB    "DPS Panel Type Features (Mobile only)"
+      Combo     $DPS_Panel_Type_01, "\tDPS Panel Type:", &DPS_Panel_Type_List,
+      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
+                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
+                "SDRRS:- Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience.\r\n"
+                "Seamless:-  Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience."
+                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
+                "during the refresh rate transitions"
+
+      TitleB    "BackLight Technology Type Features (Mobile only)"
+      Combo     $Blt_Control_01, "\tBackLight Technology:", &Blt_Control_Type_List,
+      Help      "This feature allows OEM to select the Backlight Technology."
+
+      Title     " "
+
+      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
+      Link      "DTD Timings Table" , "DTD Timings"
+      Link      "LFP PnP ID Table" , "LFP PnP ID"
+      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
+      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
+      Link      "Chromaticity Control" , "Chromaticity Control"
+      Link      "PSR feature" , "PSR feature"
+      Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
+
+      Page      "Panel Power Sequencing"
+        Link      "Close Table", ".."
+
+        Combo     $LcdVcc_On_During_S0_State_01, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
+        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
+                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
+                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
+                  "Note: This option is only applicable for Windows Graphics driver."
+
+        Combo     $eDP_T3_Optimization_01, "T3 optimization", &Disabled_Enabled_List,
+        Help      "This feature enables or disables T3 optimization. \r\n"
+                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
+                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"
+
+        EditNum   $eDP_Vcc_To_Hpd_Delay_01, "LCDVCC to HPD high delay (T3):", DEC,
+        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 200msec\r\n"
+
+        EditNum   $eDP_DataOn_To_BkltEnable_Delay_01, "Valid video data to Backlight Enable delay (T8):", DEC,
+        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
+                  "T8 is inclusive of T7.\r\n"
+                  "Valid Range of T7: 0 to 50msec\r\n"
+
+        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_01, "PWM-On To Backlight Enable delay:", DEC,
+        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
+                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
+                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"
+
+        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_01, "Backlight Disable to PWM-Off delay:", DEC,
+        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
+                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
+                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
+
+        EditNum   $eDP_BkltDisable_To_DataOff_Delay_01, "Backlight Disable to End of Valid video data delay (T9):", DEC,
+        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
+
+        EditNum   $eDP_DataOff_To_PowerOff_Delay_01, "End of Valid video data to Power-Off delay (T10):", DEC,
+        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 500 msec\r\n"
+
+        EditNum   $eDP_PowerCycle_Delay_01, "Power-off time (T12):", DEC,
+        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
+      EndPage
+
+      Page      "DTD Timings"
+        Link      "Close Table" , ".."
+
+        Table     $DVO_Tbl_01 " DTD Timings Values",
+        Column    "Timings" , 1 byte , EHEX,
+        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
+                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
+                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                  "\tByte16 \t: Horizontal Border in pixels\r\n"
+                  "\tByte17 \t: Vertical Border in lines\r\n"
+                  "\tByte18 \t: Flags:\r\n"
+                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
+                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 0:   0 = Reserved"
+      EndPage
+
+      Page      "LFP PnP ID"
+        Link      "Close Table" , ".."
+
+        Table     $LVDS_PnP_ID_01 " LFP PnP ID Values",
+        Column    "PnP ID" , 1 byte , EHEX,
+        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
+                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
+                  " Table Definition:\r\n"
+                  " \tWord:  ID Manufacturer Name\r\n"
+                  " \tWord:  ID Product Code\r\n"
+                  " \tDWord: ID Serial Number\r\n"
+                  " \tByte:  Week of Manufacture\r\n"
+                  " \tByte:  Year of Manufacture"
+      EndPage
+
+      Page      "Backlight Control Parameters"
+        Link      "Close Table" , ".."
+
+        Combo     $BLC_Inv_Type_01, "Inverter Type:", &Inv_Type_List,
+        Help      "This feature allows for the selection of the Backlight Inverter type "
+                  "that is to be used to control the backlight brightness of the LFP. \r\n"
+                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
+                  "via the integrated PWM solution for the applicable chipsets. \r\n"
+                  "When None/External is selected, the system BIOS will control the backlight brightness "
+                  "via the external solution."
+
+        Combo     $Lfp_Pwm_Source_Selection_01, "  Pwm Source Selection:", &Pwm_Source_List,
+        Help      "This field allows to select the Source of the PWM to be used  "
+                  "for the selected Local Flat Panel.\r\n"
+
+        Combo     $BLC_Inv_Polarity_01, "Inverter Polarity:", &Inv_Polarity_List,
+        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
+                  "Normal means 0 value is minimum brightness.\r\n"
+                  "Inverted means 0 value is maximum brightness."
+
+        EditNum   $BLC_Min_Brightness_01, "Minimum Brightness:", DEC,
+        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
+                  "The graphics driver will never decrease the backlight less than this value. "
+                  "The value must be specified using normal polarity semantics."
+
+        EditNum   $POST_BL_Brightness_01, "POST Brightness:", DEC,
+        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
+                  "This is configurable field of 0-255. "
+                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."
+
+        EditNum   $PWM_Frequency_01, "PWM Inverter Frequency (Hz):", DEC,
+        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
+                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
+      EndPage
+
+      Page      "Chromaticity Control"
+        Link      "Close Table" , ".."
+
+        Combo     $Chromacity_Enable_01, "Chromaticity Control Feature", &Disabled_Enabled_List,
+        Help      " This bit enables Chromaticity feature. \r\n"
+                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
+                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
+                  " Please refer to section 3.7 of EDID Specification 1.4"
+
+        Combo     $Override_EDID_Data_01, "Override the EDID values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
+
+        EditNum   $Red_Green_01, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"
+
+        EditNum   $Blue_White_01, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
+
+        EditNum   $Red_x_01, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
+        Help      " Bits 9:2 of red color x coordinate"
+
+        EditNum   $Red_y_01, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
+        Help      " Bits 9:2 of red color y coordinate"
+
+        EditNum   $Green_x_01, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
+        Help      " Bits 9:2 of Green color x coordinate"
+
+        EditNum   $Green_y_01, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
+        Help      " Bits 9:2 of Green color y coordinate"
+
+        EditNum   $Blue_x_01, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
+        Help      " Bits 9:2 of Blue color x coordinate"
+
+        EditNum   $Blue_y_01, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
+        Help      " Bits 9:2 of Blue color y coordinate"
+
+        EditNum   $White_x_01, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
+        Help      " Bits 9:2 of White color x coordinate"
+
+        EditNum   $White_y_01, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
+        Help      " Bits 9:2 of White color y coordinate"
+
+        Combo     $Override_LUM_Data_01, "Override Luminance values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override luminance values following VBT values"
+        EditNum   $MinLuminance_01, "\tMinimum Luminance" , EHEX,
+        Help      "Minimum luminance value. \r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+
+        EditNum   $MaxFullLuminance_01, "\tMaximum full frame luminance" , EHEX,
+        Help      "Maximum Full frame luminance value.\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"        
+
+        EditNum   $MaxLuminance_01,"\tMaximum Luminance" , EHEX,
+        Help      "Maximum luminance value(Relatively smaller portion of screen).\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+
+        Combo     $Override_Gamma_Data_01, "Override Gamma values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override gamma values through following VBT data"
+        EditNum   $Gamma_01, "\tPanel gamma" , EHEX,
+        Help      " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n"
+                  " Field Value = (Gamma (value in float) x 100) - 100 \n"
+                  " Field values range from 00h through FFh. \n"
+                  " FFh = No gamma information shall be provided \n"
+      EndPage   ; Chromaticity Control
+
+      Page      "eDP Link Training Configuration Parameters"
+
+        Link      "Close Table" , ".."
+
+        TitleB    "Full Link Training Parameters"
+
+        Combo     $eDP_Full_Link_Training_Params_Enable_01, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
+        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."
+
+        Combo     $eDP_Full_Link_Train_PreEmp_01, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Full_Link_Train_Vswing_01, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Title     "  "
+
+        TitleB    "Fast Link Training Parameters"
+
+        Combo     $eDP_Fast_Link_Training_Supported_01, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
+        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."
+
+        EditNum   $eDP_Fast_Link_Training_Data_Rate_01, "\tData Rate:", DEC,
+        Help      "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_LaneCount_01, "\tLane Count:", &eDP_Link_LaneCount_List,
+        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_PreEmp_01, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Link_Vswing_01, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+      EndPage
+
+      Page      "PSR feature"
+        Link      "Close Table" , ".."
+
+        Combo     $PSR_FullLink_Enable_01, "Full Link enable:", &Yes_No_List,
+        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."
+
+        Combo     $PSR_Require_AUX2Wakeup_01, "Require AUX to wake up:", &Yes_No_List,
+        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."
+
+        Combo     $PSR_Lines2Wait_B4LinkS3_01, "Lines to wait before link standby:", &wait_line_link,
+        Help      "This field determines Lines to wait before link standby \n"
+                  " 0 lines to wait (Default)\r\n"
+                  " 1 lines to wait\r\n"
+                  " 4 lines to wait\r\n"
+                  " 8 lines to wait\r\n"
+                  " Others Reserved"
+
+        EditNum   $PSR_IdleFrames2Wait_01, "Idle frames to wait:", DEC,
+        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."
+
+        Combo     $PSR_TP1_WaitTime_01, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
+
+        Combo     $PSR_TP_2_3_WaitTime_01, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
+      EndPage   ; PSR feature
+
+      Page      "Apical Feature"
+        Link      "Close Table" , ".."
+
+        Combo     $eDP_Apical_Display_Ip_Enable_01, "Apical Assertive Display IP", &Disabled_Enabled_List,
+        Help      "This field enables/disables the Apical Assertive Display IP for this panel."
+
+        EditNum   $eDP_Panel_Oui_01, "\tPanel OUI (IEEE OUI)", EHEX,
+        Help      "This field specifies the Apical IP specific Panel OUI field."
+
+        EditNum   $eDP_Dpcd_Base_Address_01, "\tDPCD Base Address", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD base address field."
+
+        EditNum   $eDP_Dpcd_Irdidix_Control0_01, "\tDPCD Irdidix Control 0", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."
+
+        EditNum   $eDP_Dpcd_Option_Select_01, "\tDPCD Option Select", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD option select field."
+
+        EditNum   $eDP_Dpcd_Backlight_01, "\tDPCD Backlight", EHEX,
+        Help      "This field specifies the Apical IP specific backlight value."
+
+        EditNum   $eDP_Ambient_Light_01, "\tAmbient Light", EHEX,
+        Help      "This field specifies the Apical IP specific Ambient light value."
+
+        EditNum   $eDP_Backlight_Scale_01, "\tBacklight scale", EHEX,
+        Help      "This field specifies the Apical IP specific backlight scale field."
+      EndPage   ; Apical Feature
+
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_01, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_01, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_01, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_01, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $ADT_Enable_01, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_01, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_01, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Automatic Display Brightness is to be enabled. "
+                  "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action."
+
+        Combo     $LACE_Status_01, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_01, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"     
+                  
+        Combo     $LACE_Aggressiveness_Profile_01, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"         
+      EndPage   ; Power Features
+    EndPage   ; Panel #01
+
+    ;==============================================================================
+    ; Page - Panel #02 (800x600 LVDS) Flat Panel parameters
+    ;------------------------------------------------------------------------------
+    Page      "Panel #02 "
+      EditText  $Panel_Name_02, "LFP panel name:",
+      Help      "This feature defines the LFP panel name, used by driver only. "
+                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."
+
+      EditNum   $Panel_Width_02, "LFP Width:", DEC,
+      Help      "This value specifies the LFP pixel width for this panel type."
+
+      EditNum   $Panel_Height_02, "LFP Height:", DEC,
+      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."
+
+      Combo     $eDP_VSwingPreEmph_02, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
+      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
+                "For Coffeelake, based on the selection respective table will be used.\r\n"
+                "Tables for Coffeelake: \r\n"
+                "Low Power VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
+                "\r\n\r\n"
+
+                "Default VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"
+
+      Combo     $eDP_Panel_Color_Depth_02, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
+      Help      "This feature specifies the color depth of eDP panel used."
+
+      Combo     $Panel_Rotation_02, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
+      TitleB    "eDP Spread Spectrum Clock Features"
+      Combo     $Enable_SSC02, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
+      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."
+
+      TitleB    "DPS Panel Type Features (Mobile only)"
+      Combo     $DPS_Panel_Type_02, "\tDPS Panel Type:", &DPS_Panel_Type_List,
+      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
+                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
+                "SDRRS:- Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience.\r\n"
+                "Seamless:-  Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience."
+                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
+                "during the refresh rate transitions"
+
+      TitleB    "BackLight Technology Type Features (Mobile only)"
+      Combo     $Blt_Control_02, "\tBackLight Technology:", &Blt_Control_Type_List,
+      Help      "This feature allows OEM to select the Backlight Technology."
+
+      Title     " "
+      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
+      Link      "DTD Timings Table" , "DTD Timings"
+      Link      "LFP PnP ID Table" , "LFP PnP ID"
+      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
+      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
+      Link      "Chromaticity Control" , "Chromaticity Control"
+      Link      "PSR feature" ,"PSR feature"
+      Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
+
+      Page      "Panel Power Sequencing"
+        Link      "Close Table", ".."
+
+        Combo     $LcdVcc_On_During_S0_State_02, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
+        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
+                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
+                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
+                  "Note: This option is only applicable for Windows Graphics driver."
+
+        Combo     $eDP_T3_Optimization_02, "T3 optimization", &Disabled_Enabled_List,
+        Help      "This feature enables or disables T3 optimization. \r\n"
+                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
+                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"
+
+        EditNum   $eDP_Vcc_To_Hpd_Delay_02, "LCDVCC to HPD high delay (T3):", DEC,
+        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 200msec\r\n"
+
+        EditNum   $eDP_DataOn_To_BkltEnable_Delay_02, "Valid video data to Backlight Enable delay (T8):", DEC,
+        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
+                  "T8 is inclusive of T7.\r\n"
+                  "Valid Range of T7: 0 to 50msec\r\n"
+
+        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_02, "PWM-On To Backlight Enable delay:", DEC,
+        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
+                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
+                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"
+
+        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_02, "Backlight Disable to PWM-Off delay:", DEC,
+        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
+                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
+                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
+
+        EditNum   $eDP_BkltDisable_To_DataOff_Delay_02, "Backlight Disable to End of Valid video data delay (T9):", DEC,
+        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
+
+        EditNum   $eDP_DataOff_To_PowerOff_Delay_02, "End of Valid video data to Power-Off delay (T10):", DEC,
+        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 500 msec\r\n"
+
+        EditNum   $eDP_PowerCycle_Delay_02, "Power-off time (T12):", DEC,
+        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
+      EndPage
+
+      Page      "DTD Timings"
+        Link      "Close Table" , ".."
+
+        Table     $DVO_Tbl_02 " DTD Timings Values",
+        Column    "Timings" , 1 byte , EHEX,
+        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
+                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
+                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                  "\tByte16 \t: Horizontal Border in pixels\r\n"
+                  "\tByte17 \t: Vertical Border in lines\r\n"
+                  "\tByte18 \t: Flags:\r\n"
+                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
+                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 0:   0 = Reserved"
+      EndPage
+
+      Page      "LFP PnP ID"
+        Link      "Close Table" , ".."
+
+        Table     $LVDS_PnP_ID_02 " LFP PnP ID Values",
+        Column    "PnP ID" , 1 byte , EHEX,
+        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
+                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
+                  " Table Definition:\r\n"
+                  " \tWord:  ID Manufacturer Name\r\n"
+                  " \tWord:  ID Product Code\r\n"
+                  " \tDWord: ID Serial Number\r\n"
+                  " \tByte:  Week of Manufacture\r\n"
+                  " \tByte:  Year of Manufacture"
+      EndPage
+
+      Page      "Backlight Control Parameters"
+        Link      "Close Table" , ".."
+
+        Combo     $BLC_Inv_Type_02, "Inverter Type:", &Inv_Type_List,
+        Help      "This feature allows for the selection of the Backlight Inverter type "
+                  "that is to be used to control the backlight brightness of the LFP. \r\n"
+                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
+                  "via the integrated PWM solution for the applicable chipsets. \r\n"
+                  "When None/External is selected, the system BIOS will control the backlight brightness "
+                  "via the external solution."
+
+        Combo     $Lfp_Pwm_Source_Selection_02, "  Pwm Source Selection:", &Pwm_Source_List,
+        Help      "This field allows to select the Source of the PWM to be used  "
+                  "for the selected Local Flat Panel.\r\n"
+
+        Combo     $BLC_Inv_Polarity_02, "Inverter Polarity:", &Inv_Polarity_List,
+        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
+                  "Normal means 0 value is minimum brightness.\r\n"
+                  "Inverted means 0 value is maximum brightness."
+
+        EditNum   $BLC_Min_Brightness_02, "Minimum Brightness:", DEC,
+        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
+                  "The graphics driver will never decrease the backlight less than this value. "
+                  "The value must be specified using normal polarity semantics."
+
+        EditNum   $POST_BL_Brightness_02, "POST Brightness:", DEC,
+        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
+                  "This is configurable field of 0-255. "
+                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."
+
+        EditNum   $PWM_Frequency_02, "PWM Inverter Frequency (Hz):", DEC,
+        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
+                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
+      EndPage
+
+      Page      "Chromaticity Control"
+        Link      "Close Table" , ".."
+
+        Combo     $Chromacity_Enable_02, "Chromaticity Control Feature", &Disabled_Enabled_List,
+        Help      " This bit enables Chromaticity feature. \r\n"
+                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
+                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
+                  " Please refer to section 3.7 of EDID Specification 1.4"
+
+        Combo     $Override_EDID_Data_02, "Override the EDID values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
+
+        EditNum   $Red_Green_02, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"
+
+        EditNum   $Blue_White_02, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
+
+        EditNum   $Red_x_02, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
+        Help      " Bits 9:2 of red color x coordinate"
+
+        EditNum   $Red_y_02, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
+        Help      " Bits 9:2 of red color y coordinate"
+
+        EditNum   $Green_x_02, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
+        Help      " Bits 9:2 of Green color x coordinate"
+
+        EditNum   $Green_y_02, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
+        Help      " Bits 9:2 of Green color y coordinate"
+
+        EditNum   $Blue_x_02, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
+        Help      " Bits 9:2 of Blue color x coordinate"
+
+        EditNum   $Blue_y_02, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
+        Help      " Bits 9:2 of Blue color y coordinate"
+
+        EditNum   $White_x_02, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
+        Help      " Bits 9:2 of White color x coordinate"
+
+        EditNum   $White_y_02, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
+        Help      " Bits 9:2 of White color y coordinate"
+
+        Combo     $Override_LUM_Data_02, "Override Luminance values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override luminance values following VBT values"
+        EditNum   $MinLuminance_02, "\tMinimum Luminance" , EHEX,
+        Help      "Minimum luminance value. \r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+
+        EditNum   $MaxFullLuminance_02, "\tMaximum full frame luminance" , EHEX,
+        Help      "Maximum Full frame luminance value.\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"        
+
+        EditNum   $MaxLuminance_02,"\tMaximum Luminance" , EHEX,
+        Help      "Maximum luminance value(Relatively smaller portion of screen).\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+
+        Combo     $Override_Gamma_Data_02, "Override Gamma values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override gamma values through following VBT data"
+        EditNum   $Gamma_02, "\tPanel gamma" , EHEX,
+        Help      " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n"
+                  " Field Value = (Gamma (value in float) x 100) - 100 \n"
+                  " Field values range from 00h through FFh. \n"
+                  " FFh = No gamma information shall be provided \n"
+      EndPage   ; Chromaticity Control
+
+      Page      "eDP Link Training Configuration Parameters"
+        Link      "Close Table" , ".."
+
+        TitleB    "Full Link Training Parameters"
+
+        Combo     $eDP_Full_Link_Training_Params_Enable_02, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
+        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."
+
+        Combo     $eDP_Full_Link_Train_PreEmp_02, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Full_Link_Train_Vswing_02, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Title     "  "
+
+        TitleB    "Fast Link Training Parameters"
+
+        Combo     $eDP_Fast_Link_Training_Supported_02, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
+        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."
+
+        EditNum   $eDP_Fast_Link_Training_Data_Rate_02, "\tData Rate:", DEC,
+        Help      "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_LaneCount_02, "\tLane Count:", &eDP_Link_LaneCount_List,
+        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_PreEmp_02, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Link_Vswing_02, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+      EndPage
+
+      Page      "PSR feature"
+        Link      "Close Table" , ".."
+
+        Combo     $PSR_FullLink_Enable_02, "Full Link enable:", &Yes_No_List,
+        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."
+
+        Combo     $PSR_Require_AUX2Wakeup_02, "Require AUX to wake up:", &Yes_No_List,
+        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."
+
+        Combo     $PSR_Lines2Wait_B4LinkS3_02, "Lines to wait before link standby:", &wait_line_link,
+        Help      "This field determines Lines to wait before link standby \n"
+                  " 0 lines to wait (Default)\r\n"
+                  " 1 lines to wait\r\n"
+                  " 4 lines to wait\r\n"
+                  " 8 lines to wait\r\n"
+                  " Others Reserved"
+
+        EditNum   $PSR_IdleFrames2Wait_02, "Idle frames to wait:", DEC,
+        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."
+
+        Combo     $PSR_TP1_WaitTime_02, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
+
+        Combo     $PSR_TP_2_3_WaitTime_02, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
+      EndPage   ; PSR feature
+
+      Page      "Apical Feature"
+        Link      "Close Table" , ".."
+
+        Combo     $eDP_Apical_Display_Ip_Enable_02, "Apical Assertive Display IP", &Disabled_Enabled_List,
+        Help      "This field enables/disables the Apical Assertive Display IP for this panel."
+
+        EditNum   $eDP_Panel_Oui_02, "\tPanel OUI (IEEE OUI)", EHEX,
+        Help      "This field specifies the Apical IP specific Panel OUI field."
+
+        EditNum   $eDP_Dpcd_Base_Address_02, "\tDPCD Base Address", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD base address field."
+
+        EditNum   $eDP_Dpcd_Irdidix_Control0_02, "\tDPCD Irdidix Control 0", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."
+
+        EditNum   $eDP_Dpcd_Option_Select_02, "\tDPCD Option Select", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD option select field."
+
+        EditNum   $eDP_Dpcd_Backlight_02, "\tDPCD Backlight", EHEX,
+        Help      "This field specifies the Apical IP specific backlight value."
+
+        EditNum   $eDP_Ambient_Light_02, "\tAmbient Light", EHEX,
+        Help      "This field specifies the Apical IP specific Ambient light value."
+
+        EditNum   $eDP_Backlight_Scale_02, "\tBacklight scale", EHEX,
+        Help      "This field specifies the Apical IP specific backlight scale field."
+      EndPage   ; Apical Feature
+
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_02, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_02, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_02, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_02, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $ADT_Enable_02, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_02, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_02, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Automatic Display Brightness is to be enabled. "
+                  "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_02, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_02, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"   
+                  
+        Combo     $LACE_Aggressiveness_Profile_02, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"   
+      EndPage   ; Power Features
+    EndPage
+
+    ;==============================================================================
+    ; Page - Panel #03 (1024x768 LVDS) Flat Panel parameters
+    ;------------------------------------------------------------------------------
+    Page      "Panel #03 "
+      EditText  $Panel_Name_03, "LFP panel name:",
+      Help      "This feature defines the LFP panel name, used by driver only. "
+                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."
+
+      EditNum   $Panel_Width_03, "LFP Width:", DEC,
+      Help      "This value specifies the LFP pixel width for this panel type."
+
+      EditNum   $Panel_Height_03, "LFP Height:", DEC,
+      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."
+
+      Combo     $eDP_VSwingPreEmph_03, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
+      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
+                "For Coffeelake, based on the selection respective table will be used.\r\n"
+                "Tables for Coffeelake: \r\n"
+                "Low Power VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
+                "\r\n\r\n"
+
+                "Default VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"
+
+      Combo     $eDP_Panel_Color_Depth_03, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
+      Help      "This feature specifies the color depth of eDP panel used."
+
+      Combo     $Panel_Rotation_03, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
+      TitleB    "eDP Spread Spectrum Clock Features"
+      Combo     $Enable_SSC03, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
+      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."
+
+      TitleB    "DPS Panel Type Features (Mobile only)"
+      Combo     $DPS_Panel_Type_03, "\tDPS Panel Type:", &DPS_Panel_Type_List,
+      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
+                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
+                "SDRRS:- Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience.\r\n"
+                "Seamless:-  Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience."
+                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
+                "during the refresh rate transitions"
+
+      TitleB    "BackLight Technology Type Features (Mobile only)"
+      Combo     $Blt_Control_03, "\tBackLight Technology:", &Blt_Control_Type_List,
+      Help      "This feature allows OEM to select the Backlight Technology."
+
+      Title     " "
+      Link      "PSR feature" ,"PSR feature"
+      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
+      Link      "DTD Timings Table" , "DTD Timings"
+      Link      "LFP PnP ID Table" , "LFP PnP ID"
+      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
+      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
+      Link      "Chromaticity Control" , "Chromaticity Control"
+      Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
+
+      Page      "Panel Power Sequencing"
+        Link      "Close Table", ".."
+
+        Combo     $LcdVcc_On_During_S0_State_03, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
+        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
+                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
+                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
+                  "Note: This option is only applicable for Windows Graphics driver."
+
+        Combo     $eDP_T3_Optimization_03, "T3 optimization", &Disabled_Enabled_List,
+        Help      "This feature enables or disables T3 optimization. \r\n"
+                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
+                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"
+
+        EditNum   $eDP_Vcc_To_Hpd_Delay_03, "LCDVCC to HPD high delay (T3):", DEC,
+        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 200msec\r\n"
+
+        EditNum   $eDP_DataOn_To_BkltEnable_Delay_03, "Valid video data to Backlight Enable delay (T8):", DEC,
+        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
+                  "T8 is inclusive of T7.\r\n"
+                  "Valid Range of T7: 0 to 50msec\r\n"
+
+        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_03, "PWM-On To Backlight Enable delay:", DEC,
+        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
+                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
+                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"
+
+        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_03, "Backlight Disable to PWM-Off delay:", DEC,
+        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
+                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
+                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
+
+        EditNum   $eDP_BkltDisable_To_DataOff_Delay_03, "Backlight Disable to End of Valid video data delay (T9):", DEC,
+        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
+
+        EditNum   $eDP_DataOff_To_PowerOff_Delay_03, "End of Valid video data to Power-Off delay (T10):", DEC,
+        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 500 msec\r\n"
+
+        EditNum   $eDP_PowerCycle_Delay_03, "Power-off time (T12):", DEC,
+        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
+      EndPage
+
+      Page      "DTD Timings"
+        Link      "Close Table" , ".."
+
+        Table     $DVO_Tbl_03 " DTD Timings Values",
+        Column    "Timings" , 1 byte , EHEX,
+        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
+                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
+                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                  "\tByte16 \t: Horizontal Border in pixels\r\n"
+                  "\tByte17 \t: Vertical Border in lines\r\n"
+                  "\tByte18 \t: Flags:\r\n"
+                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
+                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 0:   0 = Reserved"
+      EndPage
+
+      Page      "LFP PnP ID"
+        Link      "Close Table" , ".."
+
+        Table     $LVDS_PnP_ID_03 " LFP PnP ID Values",
+        Column    "PnP ID" , 1 byte , EHEX,
+        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
+                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
+                  " Table Definition:\r\n"
+                  " \tWord:  ID Manufacturer Name\r\n"
+                  " \tWord:  ID Product Code\r\n"
+                  " \tDWord: ID Serial Number\r\n"
+                  " \tByte:  Week of Manufacture\r\n"
+                  " \tByte:  Year of Manufacture"
+      EndPage
+
+      Page      "Backlight Control Parameters"
+        Link      "Close Table" , ".."
+
+        Combo     $BLC_Inv_Type_03, "Inverter Type:", &Inv_Type_List,
+        Help      "This feature allows for the selection of the Backlight Inverter type "
+                  "that is to be used to control the backlight brightness of the LFP. \r\n"
+                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
+                  "via the integrated PWM solution for the applicable chipsets. \r\n"
+                  "When None/External is selected, the system BIOS will control the backlight brightness "
+                  "via the external solution."
+
+        Combo     $Lfp_Pwm_Source_Selection_03, "  Pwm Source Selection:", &Pwm_Source_List,
+        Help      "This field allows to select the Source of the PWM to be used  "
+                  "for the selected Local Flat Panel.\r\n"
+
+        Combo     $BLC_Inv_Polarity_03, "Inverter Polarity:", &Inv_Polarity_List,
+        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
+                  "Normal means 0 value is minimum brightness.\r\n"
+                  "Inverted means 0 value is maximum brightness."
+
+        EditNum   $BLC_Min_Brightness_03, "Minimum Brightness:", DEC,
+        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
+                  "The graphics driver will never decrease the backlight less than this value. "
+                  "The value must be specified using normal polarity semantics."
+
+        EditNum   $POST_BL_Brightness_03, "POST Brightness:", DEC,
+        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
+                  "This is configurable field of 0-255. "
+                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."
+
+        EditNum   $PWM_Frequency_03, "PWM Inverter Frequency (Hz):", DEC,
+        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
+                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
+      EndPage
+
+      Page      "Chromaticity Control"
+        Link      "Close Table" , ".."
+
+        Combo     $Chromacity_Enable_03, "Chromaticity Control Feature", &Disabled_Enabled_List,
+        Help      " This bit enables Chromaticity feature. \r\n"
+                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
+                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
+                  " Please refer to section 3.7 of EDID Specification 1.4"
+
+        Combo     $Override_EDID_Data_03, "Override the EDID values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
+
+        EditNum   $Red_Green_03, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"
+
+        EditNum   $Blue_White_03, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
+
+        EditNum   $Red_x_03, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
+        Help      " Bits 9:2 of red color x coordinate"
+
+        EditNum   $Red_y_03, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
+        Help      " Bits 9:2 of red color y coordinate"
+
+        EditNum   $Green_x_03, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
+        Help      " Bits 9:2 of Green color x coordinate"
+
+        EditNum   $Green_y_03, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
+        Help      " Bits 9:2 of Green color y coordinate"
+
+        EditNum   $Blue_x_03, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
+        Help      " Bits 9:2 of Blue color x coordinate"
+
+        EditNum   $Blue_y_03, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
+        Help      " Bits 9:2 of Blue color y coordinate"
+
+        EditNum   $White_x_03, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
+        Help      " Bits 9:2 of White color x coordinate"
+
+        EditNum   $White_y_03, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
+        Help      " Bits 9:2 of White color y coordinate"
+
+        Combo     $Override_LUM_Data_03, "Override Luminance values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override luminance values following VBT values"
+        EditNum   $MinLuminance_03, "\tMinimum Luminance" , EHEX,
+        Help      "Minimum luminance value. \r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+
+        EditNum   $MaxFullLuminance_03, "\tMaximum full frame luminance" , EHEX,
+        Help      "Maximum Full frame luminance value.\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"        
+
+        EditNum   $MaxLuminance_03,"\tMaximum Luminance" , EHEX,
+        Help      "Maximum luminance value(Relatively smaller portion of screen).\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+        Combo     $Override_Gamma_Data_03, "Override Gamma values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override gamma values through following VBT data"
+
+        EditNum   $Gamma_03, "\tPanel gamma" , EHEX,
+        Help      " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n"
+                  " Field Value = (Gamma (value in float) x 100) - 100 \n"
+                  " Field values range from 00h through FFh. \n"
+                  " FFh = No gamma information shall be provided \n"
+      EndPage   ; Chromaticity Control
+
+      Page      "eDP Link Training Configuration Parameters"
+        Link      "Close Table" , ".."
+
+        TitleB    "Full Link Training Parameters"
+
+        Combo     $eDP_Full_Link_Training_Params_Enable_03, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
+        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."
+
+        Combo     $eDP_Full_Link_Train_PreEmp_03, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Full_Link_Train_Vswing_03, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Title     "  "
+
+        TitleB    "Fast Link Training Parameters"
+
+        Combo     $eDP_Fast_Link_Training_Supported_03, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
+        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."
+
+        EditNum   $eDP_Fast_Link_Training_Data_Rate_03, "\tData Rate:", DEC,
+        Help      "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_LaneCount_03, "\tLane Count:", &eDP_Link_LaneCount_List,
+        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_PreEmp_03, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Link_Vswing_03, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+      EndPage
+
+      Page      "PSR feature"
+        Link      "Close Table" , ".."
+
+        Combo     $PSR_FullLink_Enable_03, "Full Link enable:", &Yes_No_List,
+        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."
+
+        Combo     $PSR_Require_AUX2Wakeup_03, "Require AUX to wake up:", &Yes_No_List,
+        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."
+
+        Combo     $PSR_Lines2Wait_B4LinkS3_03, "Lines to wait before link standby:", &wait_line_link,
+        Help      "This field determines Lines to wait before link standby \n"
+                  " 0 lines to wait (Default)\r\n"
+                  " 1 lines to wait\r\n"
+                  " 4 lines to wait\r\n"
+                  " 8 lines to wait\r\n"
+                  " Others Reserved"
+
+        EditNum   $PSR_IdleFrames2Wait_03, "Idle frames to wait:", DEC,
+        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."
+
+        Combo     $PSR_TP1_WaitTime_03, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
+
+        Combo     $PSR_TP_2_3_WaitTime_03, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
+      EndPage   ; PSR feature
+
+      Page      "Apical Feature"
+        Link      "Close Table" , ".."
+
+        Combo     $eDP_Apical_Display_Ip_Enable_03, "Apical Assertive Display IP", &Disabled_Enabled_List,
+        Help      "This field enables/disables the Apical Assertive Display IP for this panel."
+
+        EditNum   $eDP_Panel_Oui_03, "\tPanel OUI (IEEE OUI)", EHEX,
+        Help      "This field specifies the Apical IP specific Panel OUI field."
+
+        EditNum   $eDP_Dpcd_Base_Address_03, "\tDPCD Base Address", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD base address field."
+
+        EditNum   $eDP_Dpcd_Irdidix_Control0_03, "\tDPCD Irdidix Control 0", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."
+
+        EditNum   $eDP_Dpcd_Option_Select_03, "\tDPCD Option Select", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD option select field."
+
+        EditNum   $eDP_Dpcd_Backlight_03, "\tDPCD Backlight", EHEX,
+        Help      "This field specifies the Apical IP specific backlight value."
+
+        EditNum   $eDP_Ambient_Light_03, "\tAmbient Light", EHEX,
+        Help      "This field specifies the Apical IP specific Ambient light value."
+
+        EditNum   $eDP_Backlight_Scale_03, "\tBacklight scale", EHEX,
+        Help      "This field specifies the Apical IP specific backlight scale field."
+      EndPage   ; Apical Feature
+
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_03, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_03, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_03, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_03, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $ADT_Enable_03, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_03, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_03, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Automatic Display Brightness is to be enabled. "
+                  "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_03, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_03, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"    
+                  
+        Combo     $LACE_Aggressiveness_Profile_03, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"
+      EndPage   ; Power Features
+    EndPage
+
+    ;==============================================================================
+    ; Page - Panel #04 (1280x1024 LVDS) Flat Panel parameters
+    ;------------------------------------------------------------------------------
+    Page      "Panel #04 "
+      EditText  $Panel_Name_04, "LFP panel name:",
+      Help      "This feature defines the LFP panel name, used by driver only. "
+                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."
+
+      EditNum   $Panel_Width_04, "LFP Width:", DEC,
+      Help      "This value specifies the LFP pixel width for this panel type."
+
+      EditNum   $Panel_Height_04, "LFP Height:", DEC,
+      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."
+
+      Combo     $eDP_VSwingPreEmph_04, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
+      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
+                "For Coffeelake, based on the selection respective table will be used.\r\n"
+                "Tables for Coffeelake: \r\n"
+                "Low Power VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
+                "\r\n\r\n"
+
+                "Default VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"
+
+      Combo     $eDP_Panel_Color_Depth_04, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
+      Help      "This feature specifies the color depth of eDP panel used."
+
+      Combo     $Panel_Rotation_04, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
+      TitleB    "eDP Spread Spectrum Clock Features"
+      Combo     $Enable_SSC04, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
+      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."
+
+      TitleB    "DPS Panel Type Features (Mobile only)"
+      Combo     $DPS_Panel_Type_04, "\tDPS Panel Type:", &DPS_Panel_Type_List,
+      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
+                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
+                "SDRRS:- Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience.\r\n"
+                "Seamless:-  Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience."
+                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
+                "during the refresh rate transitions"
+
+      TitleB    "BackLight Technology Type Features (Mobile only)"
+      Combo     $Blt_Control_04, "\tBackLight Technology:", &Blt_Control_Type_List,
+      Help      "This feature allows OEM to select the Backlight Technology."
+
+      Title     " "
+      Link      "PSR feature" ,"PSR feature"
+      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
+      Link      "DTD Timings Table" , "DTD Timings"
+      Link      "LFP PnP ID Table" , "LFP PnP ID"
+      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
+      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
+      Link      "Chromaticity Control" , "Chromaticity Control"
+      Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
+
+      Page      "Panel Power Sequencing"
+        Link      "Close Table", ".."
+
+        Combo     $LcdVcc_On_During_S0_State_04, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
+        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
+                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
+                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
+                  "Note: This option is only applicable for Windows Graphics driver."
+
+        Combo     $eDP_T3_Optimization_04, "T3 optimization", &Disabled_Enabled_List,
+        Help      "This feature enables or disables T3 optimization. \r\n"
+                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
+                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"
+
+        EditNum   $eDP_Vcc_To_Hpd_Delay_04, "LCDVCC to HPD high delay (T3):", DEC,
+        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 200msec\r\n"
+
+        EditNum   $eDP_DataOn_To_BkltEnable_Delay_04, "Valid video data to Backlight Enable delay (T8):", DEC,
+        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
+                  "T8 is inclusive of T7.\r\n"
+                  "Valid Range of T7: 0 to 50msec\r\n"
+
+        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_04, "PWM-On To Backlight Enable delay:", DEC,
+        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
+                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
+                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"
+
+        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_04, "Backlight Disable to PWM-Off delay:", DEC,
+        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
+                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
+                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
+
+        EditNum   $eDP_BkltDisable_To_DataOff_Delay_04, "Backlight Disable to End of Valid video data delay (T9):", DEC,
+        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
+
+        EditNum   $eDP_DataOff_To_PowerOff_Delay_04, "End of Valid video data to Power-Off delay (T10):", DEC,
+        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 500 msec\r\n"
+
+        EditNum   $eDP_PowerCycle_Delay_04, "Power-off time (T12):", DEC,
+        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
+      EndPage
+
+      Page      "DTD Timings"
+        Link      "Close Table" , ".."
+
+        Table     $DVO_Tbl_04 " DTD Timings Values",
+        Column    "Timings" , 1 byte , EHEX,
+        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
+                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
+                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                  "\tByte16 \t: Horizontal Border in pixels\r\n"
+                  "\tByte17 \t: Vertical Border in lines\r\n"
+                  "\tByte18 \t: Flags:\r\n"
+                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
+                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 0:   0 = Reserved"
+      EndPage
+
+      Page      "LFP PnP ID"
+        Link      "Close Table" , ".."
+
+        Table     $LVDS_PnP_ID_04 " LFP PnP ID Values",
+        Column    "PnP ID" , 1 byte , EHEX,
+        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
+                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
+                  " Table Definition:\r\n"
+                  " \tWord:  ID Manufacturer Name\r\n"
+                  " \tWord:  ID Product Code\r\n"
+                  " \tDWord: ID Serial Number\r\n"
+                  " \tByte:  Week of Manufacture\r\n"
+                  " \tByte:  Year of Manufacture"
+      EndPage
+
+      Page      "Backlight Control Parameters"
+        Link      "Close Table" , ".."
+
+        Combo     $BLC_Inv_Type_04, "Inverter Type:", &Inv_Type_List,
+        Help      "This feature allows for the selection of the Backlight Inverter type "
+                  "that is to be used to control the backlight brightness of the LFP. \r\n"
+                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
+                  "via the integrated PWM solution for the applicable chipsets. \r\n"
+                  "When None/External is selected, the system BIOS will control the backlight brightness "
+                  "via the external solution."
+
+        Combo     $Lfp_Pwm_Source_Selection_04, "  Pwm Source Selection:", &Pwm_Source_List,
+        Help      "This field allows to select the Source of the PWM to be used  "
+                  "for the selected Local Flat Panel.\r\n"
+
+        Combo     $BLC_Inv_Polarity_04, "Inverter Polarity:", &Inv_Polarity_List,
+        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
+                  "Normal means 0 value is minimum brightness.\r\n"
+                  "Inverted means 0 value is maximum brightness."
+
+        EditNum   $BLC_Min_Brightness_04, "Minimum Brightness:", DEC,
+        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
+                  "The graphics driver will never decrease the backlight less than this value. "
+                  "The value must be specified using normal polarity semantics."
+
+        EditNum   $POST_BL_Brightness_04, "POST Brightness:", DEC,
+        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
+                  "This is configurable field of 0-255. "
+                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."
+
+        EditNum   $PWM_Frequency_04, "PWM Inverter Frequency (Hz):", DEC,
+        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
+                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
+      EndPage
+
+      Page      "Chromaticity Control"
+        Link      "Close Table" , ".."
+
+        Combo     $Chromacity_Enable_04, "Chromaticity Control Feature", &Disabled_Enabled_List,
+        Help      " This bit enables Chromaticity feature. \r\n"
+                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
+                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
+                  " Please refer to section 3.7 of EDID Specification 1.4"
+
+        Combo     $Override_EDID_Data_04, "Override the EDID values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
+
+
+
+        EditNum   $Red_Green_04, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"
+
+        EditNum   $Blue_White_04, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
+
+        EditNum   $Red_x_04, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
+        Help      " Bits 9:2 of red color x coordinate"
+
+        EditNum   $Red_y_04, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
+        Help      " Bits 9:2 of red color y coordinate"
+
+        EditNum   $Green_x_04, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
+        Help      " Bits 9:2 of Green color x coordinate"
+
+        EditNum   $Green_y_04, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
+        Help      " Bits 9:2 of Green color y coordinate"
+
+        EditNum   $Blue_x_04, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
+        Help      " Bits 9:2 of Blue color x coordinate"
+
+        EditNum   $Blue_y_04, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
+        Help      " Bits 9:2 of Blue color y coordinate"
+
+        EditNum   $White_x_04, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
+        Help      " Bits 9:2 of White color x coordinate"
+
+        EditNum   $White_y_04, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
+        Help      " Bits 9:2 of White color y coordinate"
+
+        Combo     $Override_LUM_Data_04, "Override Luminance values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override luminance values following VBT values"
+        EditNum   $MinLuminance_04, "\tMinimum Luminance" , EHEX,
+        Help      "Minimum luminance value. \r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+
+        EditNum   $MaxFullLuminance_04, "\tMaximum full frame luminance" , EHEX,
+        Help      "Maximum Full frame luminance value.\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"        
+
+        EditNum   $MaxLuminance_04,"\tMaximum Luminance" , EHEX,
+        Help      "Maximum luminance value(Relatively smaller portion of screen).\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+
+        Combo     $Override_Gamma_Data_04, "Override Gamma values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override gamma values through following VBT data"
+        EditNum   $Gamma_04, "\tPanel gamma" , EHEX,
+        Help      " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n"
+                  " Field Value = (Gamma (value in float) x 100) - 100 \n"
+                  " Field values range from 00h through FFh. \n"
+                  " FFh = No gamma information shall be provided \n"
+      EndPage   ; Chromaticity Control
+
+      Page      "eDP Link Training Configuration Parameters"
+        Link      "Close Table" , ".."
+
+        TitleB    "Full Link Training Parameters"
+
+        Combo     $eDP_Full_Link_Training_Params_Enable_04, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
+        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."
+
+        Combo     $eDP_Full_Link_Train_PreEmp_04, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Full_Link_Train_Vswing_04, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Title     "  "
+
+        TitleB    "Fast Link Training Parameters"
+
+        Combo     $eDP_Fast_Link_Training_Supported_04, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
+        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."
+
+        EditNum   $eDP_Fast_Link_Training_Data_Rate_04, "\tData Rate:", DEC,
+        Help      "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_LaneCount_04, "\tLane Count:", &eDP_Link_LaneCount_List,
+        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_PreEmp_04, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Link_Vswing_04, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+      EndPage
+
+      Page      "PSR feature"
+        Link      "Close Table" , ".."
+
+        Combo     $PSR_FullLink_Enable_04, "Full Link enable:", &Yes_No_List,
+        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."
+
+        Combo     $PSR_Require_AUX2Wakeup_04, "Require AUX to wake up:", &Yes_No_List,
+        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."
+
+        Combo     $PSR_Lines2Wait_B4LinkS3_04, "Lines to wait before link standby:", &wait_line_link,
+        Help      "This field determines Lines to wait before link standby \n"
+                  " 0 lines to wait (Default)\r\n"
+                  " 1 lines to wait\r\n"
+                  " 4 lines to wait\r\n"
+                  " 8 lines to wait\r\n"
+                  " Others Reserved"
+
+        EditNum   $PSR_IdleFrames2Wait_04, "Idle frames to wait:", DEC,
+        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."
+
+        Combo     $PSR_TP1_WaitTime_04, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
+
+        Combo     $PSR_TP_2_3_WaitTime_04, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
+      EndPage   ; PSR feature
+
+      Page      "Apical Feature"
+        Link      "Close Table" , ".."
+
+        Combo     $eDP_Apical_Display_Ip_Enable_04, "Apical Assertive Display IP", &Disabled_Enabled_List,
+        Help      "This field enables/disables the Apical Assertive Display IP for this panel."
+
+        EditNum   $eDP_Panel_Oui_04, "\tPanel OUI (IEEE OUI)", EHEX,
+        Help      "This field specifies the Apical IP specific Panel OUI field."
+
+        EditNum   $eDP_Dpcd_Base_Address_04, "\tDPCD Base Address", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD base address field."
+
+        EditNum   $eDP_Dpcd_Irdidix_Control0_04, "\tDPCD Irdidix Control 0", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."
+
+        EditNum   $eDP_Dpcd_Option_Select_04, "\tDPCD Option Select", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD option select field."
+
+        EditNum   $eDP_Dpcd_Backlight_04, "\tDPCD Backlight", EHEX,
+        Help      "This field specifies the Apical IP specific backlight value."
+
+        EditNum   $eDP_Ambient_Light_04, "\tAmbient Light", EHEX,
+        Help      "This field specifies the Apical IP specific Ambient light value."
+
+        EditNum   $eDP_Backlight_Scale_04, "\tBacklight scale", EHEX,
+        Help      "This field specifies the Apical IP specific backlight scale field."
+      EndPage   ; Apical Feature
+
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_04, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_04, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_04, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_04, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $ADT_Enable_04, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_04, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_04, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Automatic Display Brightness is to be enabled. "
+                  "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_04, "\tDefault Display LACE Enabled status :", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_04, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST )\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"                  
+                  
+        Combo     $LACE_Aggressiveness_Profile_04, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"
+      EndPage   ; Power Features
+    EndPage
+
+    ;==============================================================================
+    ; Page - Panel #05 (1400x1050 LVDS - Reduced Blank) Flat Panel parameters
+    ;------------------------------------------------------------------------------
+    Page      "Panel #05 "
+      EditText  $Panel_Name_05, "LFP panel name:",
+      Help      "This feature defines the LFP panel name, used by driver only. "
+                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."
+
+      EditNum   $Panel_Width_05, "LFP Width:", DEC,
+      Help      "This value specifies the LFP pixel width for this panel type."
+
+      EditNum   $Panel_Height_05, "LFP Height:", DEC,
+      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."
+
+      Combo     $eDP_VSwingPreEmph_05, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
+      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
+                "For Coffeelake, based on the selection respective table will be used.\r\n"
+                "Tables for Coffeelake: \r\n"
+                "Low Power VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
+                "\r\n\r\n"
+
+                "Default VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"
+
+      Combo     $eDP_Panel_Color_Depth_05, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
+      Help      "This feature specifies the color depth of eDP panel used."
+
+      Combo     $Panel_Rotation_05, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
+      TitleB    "eDP Spread Spectrum Clock Features"
+      Combo     $Enable_SSC05, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
+      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."
+
+      TitleB    "DPS Panel Type Features (Mobile only)"
+      Combo     $DPS_Panel_Type_05, "\tDPS Panel Type:", &DPS_Panel_Type_List,
+      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
+                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
+                "SDRRS:- Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience.\r\n"
+                "Seamless:-  Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience."
+                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
+                "during the refresh rate transitions"
+
+      TitleB    "BackLight Technology Type Features (Mobile only)"
+      Combo     $Blt_Control_05, "\tBackLight Technology:", &Blt_Control_Type_List,
+      Help      "This feature allows OEM to select the Backlight Technology."
+
+      Title     " "
+      Link      "PSR feature" ,"PSR feature"
+      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
+      Link      "DTD Timings Table" , "DTD Timings"
+      Link      "LFP PnP ID Table" , "LFP PnP ID"
+      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
+      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
+      Link      "Chromaticity Control" , "Chromaticity Control"
+      Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
+
+      Page      "Panel Power Sequencing"
+        Link      "Close Table", ".."
+
+        Combo     $LcdVcc_On_During_S0_State_05, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
+        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
+                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
+                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
+                  "Note: This option is only applicable for Windows Graphics driver."
+
+        Combo     $eDP_T3_Optimization_05, "T3 optimization", &Disabled_Enabled_List,
+        Help      "This feature enables or disables T3 optimization. \r\n"
+                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
+                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"
+
+        EditNum   $eDP_Vcc_To_Hpd_Delay_05, "LCDVCC to HPD high delay (T3):", DEC,
+        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 200msec\r\n"
+
+        EditNum   $eDP_DataOn_To_BkltEnable_Delay_05, "Valid video data to Backlight Enable delay (T8):", DEC,
+        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
+                  "T8 is inclusive of T7.\r\n"
+                  "Valid Range of T7: 0 to 50msec\r\n"
+
+        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_05, "PWM-On To Backlight Enable delay:", DEC,
+        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
+                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
+                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"
+
+        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_05, "Backlight Disable to PWM-Off delay:", DEC,
+        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
+                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
+                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
+
+        EditNum   $eDP_BkltDisable_To_DataOff_Delay_05, "Backlight Disable to End of Valid video data delay (T9):", DEC,
+        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
+
+        EditNum   $eDP_DataOff_To_PowerOff_Delay_05, "End of Valid video data to Power-Off delay (T10):", DEC,
+        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 500 msec\r\n"
+
+        EditNum   $eDP_PowerCycle_Delay_05, "Power-off time (T12):", DEC,
+        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
+      EndPage
+
+      Page      "DTD Timings"
+        Link      "Close Table" , ".."
+
+        Table     $DVO_Tbl_05 " DTD Timings Values",
+        Column    "Timings" , 1 byte , EHEX,
+        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
+                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
+                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                  "\tByte16 \t: Horizontal Border in pixels\r\n"
+                  "\tByte17 \t: Vertical Border in lines\r\n"
+                  "\tByte18 \t: Flags:\r\n"
+                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
+                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 0:   0 = Reserved"
+      EndPage
+
+      Page      "LFP PnP ID"
+        Link      "Close Table" , ".."
+
+        Table     $LVDS_PnP_ID_05 " LFP PnP ID Values",
+        Column    "PnP ID" , 1 byte , EHEX,
+        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
+                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
+                  " Table Definition:\r\n"
+                  " \tWord:  ID Manufacturer Name\r\n"
+                  " \tWord:  ID Product Code\r\n"
+                  " \tDWord: ID Serial Number\r\n"
+                  " \tByte:  Week of Manufacture\r\n"
+                  " \tByte:  Year of Manufacture"
+      EndPage
+
+      Page      "Backlight Control Parameters"
+        Link      "Close Table" , ".."
+
+        Combo     $BLC_Inv_Type_05, "Inverter Type:", &Inv_Type_List,
+        Help      "This feature allows for the selection of the Backlight Inverter type "
+                  "that is to be used to control the backlight brightness of the LFP. \r\n"
+                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
+                  "via the integrated PWM solution for the applicable chipsets. \r\n"
+                  "When None/External is selected, the system BIOS will control the backlight brightness "
+                  "via the external solution."
+
+        Combo     $Lfp_Pwm_Source_Selection_05, "  Pwm Source Selection:", &Pwm_Source_List,
+        Help      "This field allows to select the Source of the PWM to be used  "
+                  "for the selected Local Flat Panel.\r\n"
+
+        Combo     $BLC_Inv_Polarity_05, "Inverter Polarity:", &Inv_Polarity_List,
+        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
+                  "Normal means 0 value is minimum brightness.\r\n"
+                  "Inverted means 0 value is maximum brightness."
+
+        EditNum   $BLC_Min_Brightness_05, "Minimum Brightness:", DEC,
+        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
+                  "The graphics driver will never decrease the backlight less than this value. "
+                  "The value must be specified using normal polarity semantics."
+
+        EditNum   $POST_BL_Brightness_05, "POST Brightness:", DEC,
+        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
+                  "This is configurable field of 0-255. "
+                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."
+
+        EditNum   $PWM_Frequency_05, "PWM Inverter Frequency (Hz):", DEC,
+        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
+                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
+      EndPage
+
+      Page      "Chromaticity Control"
+        Link      "Close Table" , ".."
+
+        Combo     $Chromacity_Enable_05, "Chromaticity Control Feature", &Disabled_Enabled_List,
+        Help      " This bit enables Chromaticity feature. \r\n"
+                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
+                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
+                  " Please refer to section 3.7 of EDID Specification 1.4"
+
+        Combo     $Override_EDID_Data_05, "Override the EDID values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
+
+
+
+        EditNum   $Red_Green_05, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"
+
+        EditNum   $Blue_White_05, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
+
+        EditNum   $Red_x_05, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
+        Help      " Bits 9:2 of red color x coordinate"
+
+        EditNum   $Red_y_05, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
+        Help      " Bits 9:2 of red color y coordinate"
+
+        EditNum   $Green_x_05, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
+        Help      " Bits 9:2 of Green color x coordinate"
+
+        EditNum   $Green_y_05, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
+        Help      " Bits 9:2 of Green color y coordinate"
+
+        EditNum   $Blue_x_05, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
+        Help      " Bits 9:2 of Blue color x coordinate"
+
+        EditNum   $Blue_y_05, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
+        Help      " Bits 9:2 of Blue color y coordinate"
+
+        EditNum   $White_x_05, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
+        Help      " Bits 9:2 of White color x coordinate"
+
+        EditNum   $White_y_05, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
+        Help      " Bits 9:2 of White color y coordinate"
+
+        Combo     $Override_LUM_Data_05, "Override Luminance values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override luminance values following VBT values"
+        EditNum   $MinLuminance_05, "\tMinimum Luminance" , EHEX,
+        Help      "Minimum luminance value. \r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+
+        EditNum   $MaxFullLuminance_05, "\tMaximum full frame luminance" , EHEX,
+        Help      "Maximum Full frame luminance value.\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"        
+
+        EditNum   $MaxLuminance_05,"\tMaximum Luminance" , EHEX,
+        Help      "Maximum luminance value(Relatively smaller portion of screen).\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+        Combo     $Override_Gamma_Data_05, "Override Gamma values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override gamma values through following VBT data"
+
+        EditNum   $Gamma_05, "\tPanel gamma" , EHEX,
+        Help      " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n"
+                  " Field Value = (Gamma (value in float) x 100) - 100 \n"
+                  " Field values range from 00h through FFh. \n"
+                  " FFh = No gamma information shall be provided \n"   
+
+      EndPage   ; Chromaticity Control
+
+      Page      "eDP Link Training Configuration Parameters"
+        Link      "Close Table" , ".."
+
+        TitleB    "Full Link Training Parameters"
+
+        Combo     $eDP_Full_Link_Training_Params_Enable_05, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
+        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."
+
+        Combo     $eDP_Full_Link_Train_PreEmp_05, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Full_Link_Train_Vswing_05, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Title     "  "
+
+        TitleB    "Fast Link Training Parameters"
+
+        Combo     $eDP_Fast_Link_Training_Supported_05, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
+        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."
+
+        EditNum   $eDP_Fast_Link_Training_Data_Rate_05, "\tData Rate:", DEC,
+        Help      "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_LaneCount_05, "\tLane Count:", &eDP_Link_LaneCount_List,
+        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_PreEmp_05, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Link_Vswing_05, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+      EndPage
+
+      Page      "PSR feature"
+        Link      "Close Table" , ".."
+
+        Combo     $PSR_FullLink_Enable_05, "Full Link enable:", &Yes_No_List,
+        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."
+
+        Combo     $PSR_Require_AUX2Wakeup_05, "Require AUX to wake up:", &Yes_No_List,
+        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."
+
+        Combo     $PSR_Lines2Wait_B4LinkS3_05, "Lines to wait before link standby:", &wait_line_link,
+        Help      "This field determines Lines to wait before link standby \n"
+                  " 0 lines to wait (Default)\r\n"
+                  " 1 lines to wait\r\n"
+                  " 4 lines to wait\r\n"
+                  " 8 lines to wait\r\n"
+                  " Others Reserved"
+
+        EditNum   $PSR_IdleFrames2Wait_05, "Idle frames to wait:", DEC,
+        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."
+
+        Combo     $PSR_TP1_WaitTime_05, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
+
+        Combo     $PSR_TP_2_3_WaitTime_05, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
+      EndPage   ; PSR feature
+
+      Page      "Apical Feature"
+        Link      "Close Table" , ".."
+
+        Combo     $eDP_Apical_Display_Ip_Enable_05, "Apical Assertive Display IP", &Disabled_Enabled_List,
+        Help      "This field enables/disables the Apical Assertive Display IP for this panel."
+
+        EditNum   $eDP_Panel_Oui_05, "\tPanel OUI (IEEE OUI)", EHEX,
+        Help      "This field specifies the Apical IP specific Panel OUI field."
+
+        EditNum   $eDP_Dpcd_Base_Address_05, "\tDPCD Base Address", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD base address field."
+
+        EditNum   $eDP_Dpcd_Irdidix_Control0_05, "\tDPCD Irdidix Control 0", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."
+
+        EditNum   $eDP_Dpcd_Option_Select_05, "\tDPCD Option Select", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD option select field."
+
+        EditNum   $eDP_Dpcd_Backlight_05, "\tDPCD Backlight", EHEX,
+        Help      "This field specifies the Apical IP specific backlight value."
+
+        EditNum   $eDP_Ambient_Light_05, "\tAmbient Light", EHEX,
+        Help      "This field specifies the Apical IP specific Ambient light value."
+
+        EditNum   $eDP_Backlight_Scale_05, "\tBacklight scale", EHEX,
+        Help      "This field specifies the Apical IP specific backlight scale field."
+      EndPage   ; Apical Feature
+
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_05, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_05, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_05, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_05, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $ADT_Enable_05, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_05, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_05, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Automatic Display Brightness is to be enabled. "
+                  "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_05, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_05, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"                      
+                  
+        Combo     $LACE_Aggressiveness_Profile_05, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"
+      EndPage   ; Power Features
+    EndPage
+
+    ;==============================================================================
+    ; Page - Panel #06 (1400x1050) Flat Panel parameters
+    ;------------------------------------------------------------------------------
+    Page      "Panel #06 "
+      EditText  $Panel_Name_06, "LFP panel name:",
+      Help      "This feature defines the LFP panel name, used by driver only. "
+                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."
+
+      EditNum   $Panel_Width_06, "LFP Width:", DEC,
+      Help      "This value specifies the LFP pixel width for this panel type."
+
+      EditNum   $Panel_Height_06, "LFP Height:", DEC,
+      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."
+
+      Combo     $eDP_VSwingPreEmph_06, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
+      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
+                "For Coffeelake, based on the selection respective table will be used.\r\n"
+                "Tables for Coffeelake: \r\n"
+                "Low Power VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
+                "\r\n\r\n"
+
+                "Default VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"
+
+      Combo     $eDP_Panel_Color_Depth_06, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
+      Help      "This feature specifies the color depth of eDP panel used."
+
+      Combo     $Panel_Rotation_06, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
+      TitleB    "eDP Spread Spectrum Clock Features"
+      Combo     $Enable_SSC06, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
+      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."
+
+      TitleB    "DPS Panel Type Features (Mobile only)"
+      Combo     $DPS_Panel_Type_06, "\tDPS Panel Type:", &DPS_Panel_Type_List,
+      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
+                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
+                "SDRRS:- Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience.\r\n"
+                "Seamless:-  Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience."
+                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
+                "during the refresh rate transitions"
+
+      TitleB    "BackLight Technology Type Features (Mobile only)"
+      Combo     $Blt_Control_06, "\tBackLight Technology:", &Blt_Control_Type_List,
+      Help      "This feature allows OEM to select the Backlight Technology."
+
+      Title     " "
+      Link      "PSR feature" ,"PSR feature"
+
+      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
+      Link      "DTD Timings Table" , "DTD Timings"
+      Link      "LFP PnP ID Table" , "LFP PnP ID"
+      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
+      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
+      Link      "Chromaticity Control" , "Chromaticity Control"
+      Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
+
+      Page      "Panel Power Sequencing"
+        Link      "Close Table", ".."
+
+        Combo     $LcdVcc_On_During_S0_State_06, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
+        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
+                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
+                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
+                  "Note: This option is only applicable for Windows Graphics driver."
+
+        Combo     $eDP_T3_Optimization_06, "T3 optimization", &Disabled_Enabled_List,
+        Help      "This feature enables or disables T3 optimization. \r\n"
+                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
+                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"
+
+        EditNum   $eDP_Vcc_To_Hpd_Delay_06, "LCDVCC to HPD high delay (T3):", DEC,
+        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 200msec\r\n"
+
+        EditNum   $eDP_DataOn_To_BkltEnable_Delay_06, "Valid video data to Backlight Enable delay (T8):", DEC,
+        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
+                  "T8 is inclusive of T7.\r\n"
+                  "Valid Range of T7: 0 to 50msec\r\n"
+
+        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_06, "PWM-On To Backlight Enable delay:", DEC,
+        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
+                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
+                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"
+
+        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_06, "Backlight Disable to PWM-Off delay:", DEC,
+        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
+                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
+                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
+
+        EditNum   $eDP_BkltDisable_To_DataOff_Delay_06, "Backlight Disable to End of Valid video data delay (T9):", DEC,
+        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
+
+        EditNum   $eDP_DataOff_To_PowerOff_Delay_06, "End of Valid video data to Power-Off delay (T10):", DEC,
+        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 500 msec\r\n"
+
+        EditNum   $eDP_PowerCycle_Delay_06, "Power-off time (T12):", DEC,
+        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
+      EndPage
+
+      Page      "DTD Timings"
+        Link      "Close Table" , ".."
+
+        Table     $DVO_Tbl_06 " DTD Timings Values",
+        Column    "Timings" , 1 byte , EHEX,
+        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
+                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
+                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                  "\tByte16 \t: Horizontal Border in pixels\r\n"
+                  "\tByte17 \t: Vertical Border in lines\r\n"
+                  "\tByte18 \t: Flags:\r\n"
+                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
+                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 0:   0 = Reserved"
+      EndPage
+
+      Page      "LFP PnP ID"
+        Link      "Close Table" , ".."
+
+        Table     $LVDS_PnP_ID_06 " LFP PnP ID Values",
+        Column    "PnP ID" , 1 byte , EHEX,
+        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
+                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
+                  " Table Definition:\r\n"
+                  " \tWord:  ID Manufacturer Name\r\n"
+                  " \tWord:  ID Product Code\r\n"
+                  " \tDWord: ID Serial Number\r\n"
+                  " \tByte:  Week of Manufacture\r\n"
+                  " \tByte:  Year of Manufacture"
+      EndPage
+
+      Page      "Backlight Control Parameters"
+        Link      "Close Table" , ".."
+
+        Combo     $BLC_Inv_Type_06, "Inverter Type:", &Inv_Type_List,
+        Help      "This feature allows for the selection of the Backlight Inverter type "
+                  "that is to be used to control the backlight brightness of the LFP. \r\n"
+                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
+                  "via the integrated PWM solution for the applicable chipsets. \r\n"
+                  "When None/External is selected, the system BIOS will control the backlight brightness "
+                  "via the external solution."
+
+        Combo     $Lfp_Pwm_Source_Selection_06, "  Pwm Source Selection:", &Pwm_Source_List,
+        Help      "This field allows to select the Source of the PWM to be used  "
+                  "for the selected Local Flat Panel.\r\n"
+
+        Combo     $BLC_Inv_Polarity_06, "Inverter Polarity:", &Inv_Polarity_List,
+        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
+                  "Normal means 0 value is minimum brightness.\r\n"
+                  "Inverted means 0 value is maximum brightness."
+
+        EditNum   $BLC_Min_Brightness_06, "Minimum Brightness:", DEC,
+        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
+                  "The graphics driver will never decrease the backlight less than this value. "
+                  "The value must be specified using normal polarity semantics."
+
+        EditNum   $POST_BL_Brightness_06, "POST Brightness:", DEC,
+        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
+                  "This is configurable field of 0-255. "
+                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."
+
+        EditNum   $PWM_Frequency_06, "PWM Inverter Frequency (Hz):", DEC,
+        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
+                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
+      EndPage
+
+      Page      "Chromaticity Control"
+        Link      "Close Table" , ".."
+
+        Combo     $Chromacity_Enable_06, "Chromaticity Control Feature", &Disabled_Enabled_List,
+        Help      " This bit enables Chromaticity feature. \r\n"
+                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
+                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
+                  " Please refer to section 3.7 of EDID Specification 1.4"
+
+        Combo     $Override_EDID_Data_06, "Override the EDID values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
+
+
+
+        EditNum   $Red_Green_06, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"
+
+        EditNum   $Blue_White_06, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
+
+        EditNum   $Red_x_06, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
+        Help      " Bits 9:2 of red color x coordinate"
+
+        EditNum   $Red_y_06, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
+        Help      " Bits 9:2 of red color y coordinate"
+
+        EditNum   $Green_x_06, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
+        Help      " Bits 9:2 of Green color x coordinate"
+
+        EditNum   $Green_y_06, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
+        Help      " Bits 9:2 of Green color y coordinate"
+
+        EditNum   $Blue_x_06, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
+        Help      " Bits 9:2 of Blue color x coordinate"
+
+        EditNum   $Blue_y_06, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
+        Help      " Bits 9:2 of Blue color y coordinate"
+
+        EditNum   $White_x_06, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
+        Help      " Bits 9:2 of White color x coordinate"
+
+        EditNum   $White_y_06, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
+        Help      " Bits 9:2 of White color y coordinate"
+
+        Combo     $Override_LUM_Data_06, "Override Luminance values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override luminance values following VBT values"
+        EditNum   $MinLuminance_06, "\tMinimum Luminance" , EHEX,
+        Help      "Minimum luminance value. \r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+
+        EditNum   $MaxFullLuminance_06, "\tMaximum full frame luminance" , EHEX,
+        Help      "Maximum Full frame luminance value.\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"        
+
+        EditNum   $MaxLuminance_06,"\tMaximum Luminance" , EHEX,
+        Help      "Maximum luminance value(Relatively smaller portion of screen).\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+        Combo     $Override_Gamma_Data_06, "Override Gamma values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override gamma values through following VBT data"
+
+        EditNum   $Gamma_06, "\tPanel gamma" , EHEX,
+        Help      " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n"
+                  " Field Value = (Gamma (value in float) x 100) - 100 \n"
+                  " Field values range from 00h through FFh. \n"
+                  " FFh = No gamma information shall be provided \n"
+
+      EndPage   ; Chromaticity Control
+
+      Page      "eDP Link Training Configuration Parameters"
+        Link      "Close Table" , ".."
+
+        TitleB    "Full Link Training Parameters"
+
+        Combo     $eDP_Full_Link_Training_Params_Enable_06, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
+        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."
+
+        Combo     $eDP_Full_Link_Train_PreEmp_06, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Full_Link_Train_Vswing_06, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Title     "  "
+
+        TitleB    "Fast Link Training Parameters"
+        Combo     $eDP_Fast_Link_Training_Supported_06, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
+        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."
+
+        EditNum   $eDP_Fast_Link_Training_Data_Rate_06, "\tData Rate:", DEC,
+        Help      "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_LaneCount_06, "\tLane Count:", &eDP_Link_LaneCount_List,
+        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_PreEmp_06, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Link_Vswing_06, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+      EndPage
+
+      Page      "PSR feature"
+        Link      "Close Table" , ".."
+
+        Combo     $PSR_FullLink_Enable_06, "Full Link enable:", &Yes_No_List,
+        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."
+
+        Combo     $PSR_Require_AUX2Wakeup_06, "Require AUX to wake up:", &Yes_No_List,
+        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."
+
+        Combo     $PSR_Lines2Wait_B4LinkS3_06, "Lines to wait before link standby:", &wait_line_link,
+        Help      "This field determines Lines to wait before link standby \n"
+                  " 0 lines to wait (Default)\r\n"
+                  " 1 lines to wait\r\n"
+                  " 4 lines to wait\r\n"
+                  " 8 lines to wait\r\n"
+                  " Others Reserved"
+
+        EditNum   $PSR_IdleFrames2Wait_06, "Idle frames to wait:", DEC,
+        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."
+
+        Combo     $PSR_TP1_WaitTime_06, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
+
+        Combo     $PSR_TP_2_3_WaitTime_06, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
+      EndPage   ; PSR feature
+
+      Page      "Apical Feature"
+        Link      "Close Table" , ".."
+
+        Combo     $eDP_Apical_Display_Ip_Enable_06, "Apical Assertive Display IP", &Disabled_Enabled_List,
+        Help      "This field enables/disables the Apical Assertive Display IP for this panel."
+
+        EditNum   $eDP_Panel_Oui_06, "\tPanel OUI (IEEE OUI)", EHEX,
+        Help      "This field specifies the Apical IP specific Panel OUI field."
+
+        EditNum   $eDP_Dpcd_Base_Address_06, "\tDPCD Base Address", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD base address field."
+
+        EditNum   $eDP_Dpcd_Irdidix_Control0_06, "\tDPCD Irdidix Control 0", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."
+
+        EditNum   $eDP_Dpcd_Option_Select_06, "\tDPCD Option Select", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD option select field."
+
+        EditNum   $eDP_Dpcd_Backlight_06, "\tDPCD Backlight", EHEX,
+        Help      "This field specifies the Apical IP specific backlight value."
+
+        EditNum   $eDP_Ambient_Light_06, "\tAmbient Light", EHEX,
+        Help      "This field specifies the Apical IP specific Ambient light value."
+
+        EditNum   $eDP_Backlight_Scale_06, "\tBacklight scale", EHEX,
+        Help      "This field specifies the Apical IP specific backlight scale field."
+      EndPage   ; Apical Feature
+
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_06, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_06, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_06, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_06, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled."  
+
+        Combo     $ADT_Enable_06, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_06, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_06, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Automatic Display Brightness is to be enabled. "
+                  "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_06, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_06, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"   
+                  
+        Combo     $LACE_Aggressiveness_Profile_06, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"                   
+      EndPage   ; Power Features
+    EndPage
+
+    ;==============================================================================
+    ; Page - Panel #07 (1600x1200) Flat Panel parameters
+    ;------------------------------------------------------------------------------
+    Page      "Panel #07 "
+      EditText  $Panel_Name_07, "LFP panel name:",
+      Help      "This feature defines the LFP panel name, used by driver only. "
+                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."
+
+      EditNum   $Panel_Width_07, "LFP Width:", DEC,
+      Help      "This value specifies the LFP pixel width for this panel type."
+
+      EditNum   $Panel_Height_07, "LFP Height:", DEC,
+      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."
+
+      Combo     $eDP_VSwingPreEmph_07, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
+      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
+                "For Coffeelake, based on the selection respective table will be used.\r\n"
+                "Tables for Coffeelake: \r\n"
+                "Low Power VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
+                "\r\n\r\n"
+
+                "Default VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"
+
+      Combo     $eDP_Panel_Color_Depth_07, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
+      Help      "This feature specifies the color depth of eDP panel used."
+
+      Combo     $Panel_Rotation_07, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
+      TitleB    "eDP Spread Spectrum Clock Features"
+      Combo     $Enable_SSC07, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
+      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."
+
+      TitleB    "DPS Panel Type Features (Mobile only)"
+      Combo     $DPS_Panel_Type_07, "\tDPS Panel Type:", &DPS_Panel_Type_List,
+      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
+                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
+                "SDRRS:- Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience.\r\n"
+                "Seamless:-  Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience."
+                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
+                "during the refresh rate transitions"
+
+      TitleB    "BackLight Technology Type Features (Mobile only)"
+      Combo     $Blt_Control_07, "\tBackLight Technology:", &Blt_Control_Type_List,
+      Help      "This feature allows OEM to select the Backlight Technology."
+
+      Title     " "
+      Link      "PSR feature" ,"PSR feature"
+      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
+      Link      "DTD Timings Table" , "DTD Timings"
+      Link      "LFP PnP ID Table" , "LFP PnP ID"
+      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
+      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
+      Link      "Chromaticity Control" , "Chromaticity Control"
+      Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
+
+      Page      "Panel Power Sequencing"
+        Link      "Close Table", ".."
+
+        Combo     $LcdVcc_On_During_S0_State_07, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
+        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
+                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
+                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
+                  "Note: This option is only applicable for Windows Graphics driver."
+
+        Combo     $eDP_T3_Optimization_07, "T3 optimization", &Disabled_Enabled_List,
+        Help      "This feature enables or disables T3 optimization. \r\n"
+                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
+                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"
+
+        EditNum   $eDP_Vcc_To_Hpd_Delay_07, "LCDVCC to HPD high delay (T3):", DEC,
+        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 200msec\r\n"
+
+        EditNum   $eDP_DataOn_To_BkltEnable_Delay_07, "Valid video data to Backlight Enable delay (T8):", DEC,
+        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
+                  "T8 is inclusive of T7.\r\n"
+                  "Valid Range of T7: 0 to 50msec\r\n"
+
+        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_07, "PWM-On To Backlight Enable delay:", DEC,
+        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
+                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
+                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"
+
+        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_07, "Backlight Disable to PWM-Off delay:", DEC,
+        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
+                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
+                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
+
+        EditNum   $eDP_BkltDisable_To_DataOff_Delay_07, "Backlight Disable to End of Valid video data delay (T9):", DEC,
+        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
+
+        EditNum   $eDP_DataOff_To_PowerOff_Delay_07, "End of Valid video data to Power-Off delay (T10):", DEC,
+        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 500 msec\r\n"
+
+        EditNum   $eDP_PowerCycle_Delay_07, "Power-off time (T12):", DEC,
+        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
+      EndPage
+
+      Page      "DTD Timings"
+        Link      "Close Table" , ".."
+
+        Table     $DVO_Tbl_07 " DTD Timings Values",
+        Column    "Timings" , 1 byte , EHEX,
+        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
+                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
+                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                  "\tByte16 \t: Horizontal Border in pixels\r\n"
+                  "\tByte17 \t: Vertical Border in lines\r\n"
+                  "\tByte18 \t: Flags:\r\n"
+                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
+                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 0:   0 = Reserved"
+      EndPage
+
+      Page      "LFP PnP ID"
+        Link      "Close Table" , ".."
+
+        Table     $LVDS_PnP_ID_07 " LFP PnP ID Values",
+        Column    "PnP ID" , 1 byte , EHEX,
+        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
+                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
+                  " Table Definition:\r\n"
+                  " \tWord:  ID Manufacturer Name\r\n"
+                  " \tWord:  ID Product Code\r\n"
+                  " \tDWord: ID Serial Number\r\n"
+                  " \tByte:  Week of Manufacture\r\n"
+                  " \tByte:  Year of Manufacture"
+      EndPage
+
+      Page      "Backlight Control Parameters"
+        Link      "Close Table" , ".."
+
+        Combo     $BLC_Inv_Type_07, "Inverter Type:", &Inv_Type_List,
+        Help      "This feature allows for the selection of the Backlight Inverter type "
+                  "that is to be used to control the backlight brightness of the LFP. \r\n"
+                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
+                  "via the integrated PWM solution for the applicable chipsets. \r\n"
+                  "When None/External is selected, the system BIOS will control the backlight brightness "
+                  "via the external solution."
+
+        Combo     $Lfp_Pwm_Source_Selection_07, "  Pwm Source Selection:", &Pwm_Source_List,
+        Help      "This field allows to select the Source of the PWM to be used  "
+                  "for the selected Local Flat Panel.\r\n"
+
+        Combo     $BLC_Inv_Polarity_07, "Inverter Polarity:", &Inv_Polarity_List,
+        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
+                  "Normal means 0 value is minimum brightness.\r\n"
+                  "Inverted means 0 value is maximum brightness."
+
+        EditNum   $BLC_Min_Brightness_07, "Minimum Brightness:", DEC,
+        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
+                  "The graphics driver will never decrease the backlight less than this value. "
+                  "The value must be specified using normal polarity semantics."
+
+        EditNum   $POST_BL_Brightness_07, "POST Brightness:", DEC,
+        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
+                  "This is configurable field of 0-255. "
+                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."
+
+        EditNum   $PWM_Frequency_07, "PWM Inverter Frequency (Hz):", DEC,
+        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
+                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
+      EndPage
+
+      Page      "Chromaticity Control"
+        Link      "Close Table" , ".."
+
+        Combo     $Chromacity_Enable_07, "Chromaticity Control Feature", &Disabled_Enabled_List,
+        Help      " This bit enables Chromaticity feature. \r\n"
+                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
+                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
+                  " Please refer to section 3.7 of EDID Specification 1.4"
+
+        Combo     $Override_EDID_Data_07, "Override the EDID values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
+
+
+
+        EditNum   $Red_Green_07, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"
+
+        EditNum   $Blue_White_07, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
+
+        EditNum   $Red_x_07, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
+        Help      " Bits 9:2 of red color x coordinate"
+
+        EditNum   $Red_y_07, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
+        Help      " Bits 9:2 of red color y coordinate"
+
+        EditNum   $Green_x_07, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
+        Help      " Bits 9:2 of Green color x coordinate"
+
+        EditNum   $Green_y_07, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
+        Help      " Bits 9:2 of Green color y coordinate"
+
+        EditNum   $Blue_x_07, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
+        Help      " Bits 9:2 of Blue color x coordinate"
+
+        EditNum   $Blue_y_07, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
+        Help      " Bits 9:2 of Blue color y coordinate"
+
+        EditNum   $White_x_07, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
+        Help      " Bits 9:2 of White color x coordinate"
+
+        EditNum   $White_y_07, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
+        Help      " Bits 9:2 of White color y coordinate"
+
+        Combo     $Override_LUM_Data_07, "Override Luminance values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override luminance values following VBT values"
+        EditNum   $MinLuminance_07, "\tMinimum Luminance" , EHEX,
+        Help      "Minimum luminance value. \r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+
+        EditNum   $MaxFullLuminance_07, "\tMaximum full frame luminance" , EHEX,
+        Help      "Maximum Full frame luminance value.\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"        
+
+        EditNum   $MaxLuminance_07,"\tMaximum Luminance" , EHEX,
+        Help      "Maximum luminance value(Relatively smaller portion of screen).\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+        Combo     $Override_Gamma_Data_07, "Override Gamma values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override gamma values through following VBT data"
+
+        EditNum   $Gamma_07, "\tPanel gamma" , EHEX,
+        Help      " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n"
+                  " Field Value = (Gamma (value in float) x 100) - 100 \n"
+                  " Field values range from 00h through FFh. \n"
+                  " FFh = No gamma information shall be provided \n"
+
+      EndPage   ; Chromaticity Control
+
+      Page      "eDP Link Training Configuration Parameters"
+        Link      "Close Table" , ".."
+
+        TitleB    "Full Link Training Parameters"
+
+        Combo     $eDP_Full_Link_Training_Params_Enable_07, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
+        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."
+
+        Combo     $eDP_Full_Link_Train_PreEmp_07, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Full_Link_Train_Vswing_07, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Title     "  "
+
+        TitleB    "Fast Link Training Parameters"
+        Combo     $eDP_Fast_Link_Training_Supported_07, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
+        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."
+
+        EditNum   $eDP_Fast_Link_Training_Data_Rate_07, "\tData Rate:", DEC,
+        Help      "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+
+        Combo     $eDP_Link_LaneCount_07, "\tLane Count:", &eDP_Link_LaneCount_List,
+        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_PreEmp_07, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Link_Vswing_07, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+      EndPage
+
+      Page      "PSR feature"
+        Link      "Close Table" , ".."
+
+        Combo     $PSR_FullLink_Enable_07, "Full Link enable:", &Yes_No_List,
+        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."
+
+        Combo     $PSR_Require_AUX2Wakeup_07, "Require AUX to wake up:", &Yes_No_List,
+        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."
+
+        Combo     $PSR_Lines2Wait_B4LinkS3_07, "Lines to wait before link standby:", &wait_line_link,
+        Help      "This field determines Lines to wait before link standby \n"
+                  " 0 lines to wait (Default)\r\n"
+                  " 1 lines to wait\r\n"
+                  " 4 lines to wait\r\n"
+                  " 8 lines to wait\r\n"
+                  " Others Reserved"
+
+        EditNum   $PSR_IdleFrames2Wait_07, "Idle frames to wait:", DEC,
+        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."
+
+        Combo     $PSR_TP1_WaitTime_07, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
+
+        Combo     $PSR_TP_2_3_WaitTime_07, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
+      EndPage   ; PSR feature
+
+      Page      "Apical Feature"
+        Link      "Close Table" , ".."
+
+        Combo     $eDP_Apical_Display_Ip_Enable_07, "Apical Assertive Display IP", &Disabled_Enabled_List,
+        Help      "This field enables/disables the Apical Assertive Display IP for this panel."
+
+        EditNum   $eDP_Panel_Oui_07, "\tPanel OUI (IEEE OUI)", EHEX,
+        Help      "This field specifies the Apical IP specific Panel OUI field."
+
+        EditNum   $eDP_Dpcd_Base_Address_07, "\tDPCD Base Address", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD base address field."
+
+        EditNum   $eDP_Dpcd_Irdidix_Control0_07, "\tDPCD Irdidix Control 0", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."
+
+        EditNum   $eDP_Dpcd_Option_Select_07, "\tDPCD Option Select", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD option select field."
+
+        EditNum   $eDP_Dpcd_Backlight_07, "\tDPCD Backlight", EHEX,
+        Help      "This field specifies the Apical IP specific backlight value."
+
+        EditNum   $eDP_Ambient_Light_07, "\tAmbient Light", EHEX,
+        Help      "This field specifies the Apical IP specific Ambient light value."
+
+        EditNum   $eDP_Backlight_Scale_07, "\tBacklight scale", EHEX,
+        Help      "This field specifies the Apical IP specific backlight scale field."
+      EndPage   ; Apical Feature
+
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_07, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_07, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_07, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_07, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled. " 
+
+        Combo     $ADT_Enable_07, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_07, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_07, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Automatic Display Brightness is to be enabled. "
+                  "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_07, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_07, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type. \n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery) "                     
+                  
+        Combo     $LACE_Aggressiveness_Profile_07, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Agressiveness level for this Panel Type. \n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"
+      EndPage   ; Power Features
+    EndPage
+
+    ;==============================================================================
+    ; Page - Panel #08 (1280x768) Flat Panel parameters
+    ;------------------------------------------------------------------------------
+    Page      "Panel #08 "
+      EditText  $Panel_Name_08, "LFP panel name:",
+      Help      "This feature defines the LFP panel name, used by driver only. "
+                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."
+
+      EditNum   $Panel_Width_08, "LFP Width:", DEC,
+      Help      "This value specifies the LFP pixel width for this panel type."
+
+      EditNum   $Panel_Height_08, "LFP Height:", DEC,
+      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."
+
+      Combo     $eDP_VSwingPreEmph_08, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
+      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
+                "For Coffeelake, based on the selection respective table will be used.\r\n"
+                "Tables for Coffeelake: \r\n"
+                "Low Power VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
+                "\r\n\r\n"
+
+                "Default VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"
+
+      Combo     $eDP_Panel_Color_Depth_08, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
+      Help      "This feature specifies the color depth of eDP panel used."
+
+      Combo     $Panel_Rotation_08, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
+      TitleB    "eDP Spread Spectrum Clock Features"
+      Combo     $Enable_SSC08, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
+      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."
+
+      TitleB    "DPS Panel Type Features (Mobile only)"
+      Combo     $DPS_Panel_Type_08, "\tDPS Panel Type:", &DPS_Panel_Type_List,
+      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
+                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
+                "SDRRS:- Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience.\r\n"
+                "Seamless:-  Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience."
+                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
+                "during the refresh rate transitions"
+
+      TitleB    "BackLight Technology Type Features (Mobile only)"
+      Combo     $Blt_Control_08, "\tBackLight Technology:", &Blt_Control_Type_List,
+      Help      "This feature allows OEM to select the Backlight Technology."
+
+      Title     " "
+      Link      "PSR feature" ,"PSR feature"
+      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
+      Link      "DTD Timings Table" , "DTD Timings"
+      Link      "LFP PnP ID Table" , "LFP PnP ID"
+      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
+      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
+      Link      "Chromaticity Control" , "Chromaticity Control"
+      Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
+
+      Page      "Panel Power Sequencing"
+        Link      "Close Table", ".."
+
+        Combo     $LcdVcc_On_During_S0_State_08, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
+        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
+                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
+                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
+                  "Note: This option is only applicable for Windows Graphics driver."
+
+        Combo     $eDP_T3_Optimization_08, "T3 optimization", &Disabled_Enabled_List,
+        Help      "This feature enables or disables T3 optimization. \r\n"
+                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
+                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"
+
+        EditNum   $eDP_Vcc_To_Hpd_Delay_08, "LCDVCC to HPD high delay (T3):", DEC,
+        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 200msec\r\n"
+
+        EditNum   $eDP_DataOn_To_BkltEnable_Delay_08, "Valid video data to Backlight Enable delay (T8):", DEC,
+        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
+                  "T8 is inclusive of T7.\r\n"
+                  "Valid Range of T7: 0 to 50msec\r\n"
+
+        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_08, "PWM-On To Backlight Enable delay:", DEC,
+        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
+                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
+                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"
+
+        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_08, "Backlight Disable to PWM-Off delay:", DEC,
+        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
+                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
+                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
+
+        EditNum   $eDP_BkltDisable_To_DataOff_Delay_08, "Backlight Disable to End of Valid video data delay (T9):", DEC,
+        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
+
+        EditNum   $eDP_DataOff_To_PowerOff_Delay_08, "End of Valid video data to Power-Off delay (T10):", DEC,
+        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 500 msec\r\n"
+
+        EditNum   $eDP_PowerCycle_Delay_08, "Power-off time (T12):", DEC,
+        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
+      EndPage
+
+      Page      "DTD Timings"
+        Link      "Close Table" , ".."
+
+        Table     $DVO_Tbl_08 " DTD Timings Values",
+        Column    "Timings" , 1 byte , EHEX,
+        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
+                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
+                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                  "\tByte16 \t: Horizontal Border in pixels\r\n"
+                  "\tByte17 \t: Vertical Border in lines\r\n"
+                  "\tByte18 \t: Flags:\r\n"
+                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
+                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 0:   0 = Reserved"
+      EndPage
+
+      Page      "LFP PnP ID"
+        Link      "Close Table" , ".."
+
+        Table     $LVDS_PnP_ID_08 " LFP PnP ID Values",
+        Column    "PnP ID" , 1 byte , EHEX,
+        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
+                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
+                  " Table Definition:\r\n"
+                  " \tWord:  ID Manufacturer Name\r\n"
+                  " \tWord:  ID Product Code\r\n"
+                  " \tDWord: ID Serial Number\r\n"
+                  " \tByte:  Week of Manufacture\r\n"
+                  " \tByte:  Year of Manufacture"
+      EndPage
+
+      Page      "Backlight Control Parameters"
+        Link      "Close Table" , ".."
+
+        Combo     $BLC_Inv_Type_08, "Inverter Type:", &Inv_Type_List,
+        Help      "This feature allows for the selection of the Backlight Inverter type "
+                  "that is to be used to control the backlight brightness of the LFP. \r\n"
+                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
+                  "via the integrated PWM solution for the applicable chipsets. \r\n"
+                  "When None/External is selected, the system BIOS will control the backlight brightness "
+                  "via the external solution."
+
+        Combo     $Lfp_Pwm_Source_Selection_08, "  Pwm Source Selection:", &Pwm_Source_List,
+        Help      "This field allows to select the Source of the PWM to be used  "
+                  "for the selected Local Flat Panel.\r\n"
+
+        Combo     $BLC_Inv_Polarity_08, "Inverter Polarity:", &Inv_Polarity_List,
+        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
+                  "Normal means 0 value is minimum brightness.\r\n"
+                  "Inverted means 0 value is maximum brightness."
+
+        EditNum   $BLC_Min_Brightness_08, "Minimum Brightness:", DEC,
+        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
+                  "The graphics driver will never decrease the backlight less than this value. "
+                  "The value must be specified using normal polarity semantics."
+
+        EditNum   $POST_BL_Brightness_08, "POST Brightness:", DEC,
+        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
+                  "This is configurable field of 0-255. "
+                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."
+
+        EditNum   $PWM_Frequency_08, "PWM Inverter Frequency (Hz):", DEC,
+        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
+                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
+      EndPage
+
+      Page      "Chromaticity Control"
+        Link      "Close Table" , ".."
+
+        Combo     $Chromacity_Enable_08, "Chromaticity Control Feature", &Disabled_Enabled_List,
+        Help      " This bit enables Chromaticity feature. \r\n"
+                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
+                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
+                  " Please refer to section 3.7 of EDID Specification 1.4"
+
+        Combo     $Override_EDID_Data_08, "Override the EDID values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
+
+
+
+        EditNum   $Red_Green_08, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"
+
+        EditNum   $Blue_White_08, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
+
+        EditNum   $Red_x_08, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
+        Help      " Bits 9:2 of red color x coordinate"
+
+        EditNum   $Red_y_08, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
+        Help      " Bits 9:2 of red color y coordinate"
+
+        EditNum   $Green_x_08, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
+        Help      " Bits 9:2 of Green color x coordinate"
+
+        EditNum   $Green_y_08, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
+        Help      " Bits 9:2 of Green color y coordinate"
+
+        EditNum   $Blue_x_08, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
+        Help      " Bits 9:2 of Blue color x coordinate"
+
+        EditNum   $Blue_y_08, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
+        Help      " Bits 9:2 of Blue color y coordinate"
+
+        EditNum   $White_x_08, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
+        Help      " Bits 9:2 of White color x coordinate"
+
+        EditNum   $White_y_08, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
+        Help      " Bits 9:2 of White color y coordinate"
+
+        Combo     $Override_LUM_Data_08, "Override Luminance values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override luminance values following VBT values"
+        EditNum   $MinLuminance_08, "\tMinimum Luminance" , EHEX,
+        Help      "Minimum luminance value. \r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+
+        EditNum   $MaxFullLuminance_08, "\tMaximum full frame luminance" , EHEX,
+        Help      "Maximum Full frame luminance value.\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"        
+
+        EditNum   $MaxLuminance_08,"\tMaximum Luminance" , EHEX,
+        Help      "Maximum luminance value(Relatively smaller portion of screen).\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+        Combo     $Override_Gamma_Data_08, "Override Gamma values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override gamma values through following VBT data"
+
+        EditNum   $Gamma_08, "\tPanel gamma" , EHEX,
+        Help      " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n"
+                  " Field Value = (Gamma (value in float) x 100) - 100 \n"
+                  " Field values range from 00h through FFh. \n"
+                  " FFh = No gamma information shall be provided \n"
+
+      EndPage   ; Chromaticity Control
+
+      Page      "eDP Link Training Configuration Parameters"
+        Link      "Close Table" , ".."
+
+        TitleB    "Full Link Training Parameters"
+
+        Combo     $eDP_Full_Link_Training_Params_Enable_08, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
+        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."
+
+        Combo     $eDP_Full_Link_Train_PreEmp_08, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Full_Link_Train_Vswing_08, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Title     "  "
+
+        TitleB    "Fast Link Training Parameters"
+
+        Combo     $eDP_Fast_Link_Training_Supported_08, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
+        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."
+
+        EditNum   $eDP_Fast_Link_Training_Data_Rate_08, "\tData Rate:", DEC,
+        Help      "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_LaneCount_08, "\tLane Count:", &eDP_Link_LaneCount_List,
+        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_PreEmp_08, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Link_Vswing_08, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+      EndPage
+
+      Page      "PSR feature"
+        Link      "Close Table" , ".."
+
+        Combo     $PSR_FullLink_Enable_08, "Full Link enable:", &Yes_No_List,
+        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."
+
+        Combo     $PSR_Require_AUX2Wakeup_08, "Require AUX to wake up:", &Yes_No_List,
+        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."
+
+        Combo     $PSR_Lines2Wait_B4LinkS3_08, "Lines to wait before link standby:", &wait_line_link,
+        Help      "This field determines Lines to wait before link standby \n"
+                  " 0 lines to wait (Default)\r\n"
+                  " 1 lines to wait\r\n"
+                  " 4 lines to wait\r\n"
+                  " 8 lines to wait\r\n"
+                  " Others Reserved"
+
+        EditNum   $PSR_IdleFrames2Wait_08, "Idle frames to wait:", DEC,
+        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."
+
+        Combo     $PSR_TP1_WaitTime_08, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
+
+        Combo     $PSR_TP_2_3_WaitTime_08, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
+      EndPage   ; PSR feature
+
+      Page      "Apical Feature"
+        Link      "Close Table" , ".."
+
+        Combo     $eDP_Apical_Display_Ip_Enable_08, "Apical Assertive Display IP", &Disabled_Enabled_List,
+        Help      "This field enables/disables the Apical Assertive Display IP for this panel."
+
+        EditNum   $eDP_Panel_Oui_08, "\tPanel OUI (IEEE OUI)", EHEX,
+        Help      "This field specifies the Apical IP specific Panel OUI field."
+
+        EditNum   $eDP_Dpcd_Base_Address_08, "\tDPCD Base Address", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD base address field."
+
+        EditNum   $eDP_Dpcd_Irdidix_Control0_08, "\tDPCD Irdidix Control 0", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."
+
+        EditNum   $eDP_Dpcd_Option_Select_08, "\tDPCD Option Select", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD option select field."
+
+        EditNum   $eDP_Dpcd_Backlight_08, "\tDPCD Backlight", EHEX,
+        Help      "This field specifies the Apical IP specific backlight value."
+
+        EditNum   $eDP_Ambient_Light_08, "\tAmbient Light", EHEX,
+        Help      "This field specifies the Apical IP specific Ambient light value."
+
+        EditNum   $eDP_Backlight_Scale_08, "\tBacklight scale", EHEX,
+        Help      "This field specifies the Apical IP specific backlight scale field."
+      EndPage   ; Apical Feature
+
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_08, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_08, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_08, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_08, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $ADT_Enable_08, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_08, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_08, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Automatic Display Brightness is to be enabled. "
+                  "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action."   
+
+        Combo     $LACE_Status_08, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_08, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"
+
+        Combo     $LACE_Aggressiveness_Profile_08, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"
+      EndPage   ; Power Features
+    EndPage
+
+    ;==============================================================================
+    ; Page - Panel #09 (1680x1050) Flat Panel parameters
+    ;------------------------------------------------------------------------------
+    Page      "Panel #09 "
+      EditText  $Panel_Name_09, "LFP panel name:",
+      Help      "This feature defines the LFP panel name, used by driver only. "
+                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."
+
+      EditNum   $Panel_Width_09, "LFP Width:", DEC,
+      Help      "This value specifies the LFP pixel width for this panel type."
+
+      EditNum   $Panel_Height_09, "LFP Height:", DEC,
+      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."
+
+      Combo     $eDP_VSwingPreEmph_09, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
+      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
+                "For Coffeelake, based on the selection respective table will be used.\r\n"
+                "Tables for Coffeelake: \r\n"
+                "Low Power VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
+                "\r\n\r\n"
+
+                "Default VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"
+
+      Combo     $eDP_Panel_Color_Depth_09, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
+      Help      "This feature specifies the color depth of eDP panel used."
+
+      Combo     $Panel_Rotation_09, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
+      TitleB    "eDP Spread Spectrum Clock Features"
+      Combo     $Enable_SSC09, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
+      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."
+
+      TitleB    "DPS Panel Type Features (Mobile only)"
+      Combo     $DPS_Panel_Type_09, "\tDPS Panel Type:", &DPS_Panel_Type_List,
+      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
+                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
+                "SDRRS:- Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience.\r\n"
+                "Seamless:-  Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience."
+                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
+                "during the refresh rate transitions"
+
+      TitleB    "BackLight Technology Type Features (Mobile only)"
+      Combo     $Blt_Control_09, "  BackLight Technology:", &Blt_Control_Type_List,
+      Help      "This feature allows OEM to select the Backlight Technology."
+
+      Title     " "
+      Link      "PSR feature" ,"PSR feature"
+      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
+      Link      "DTD Timings Table" , "DTD Timings"
+      Link      "LFP PnP ID Table" , "LFP PnP ID"
+      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
+      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
+      Link      "Chromaticity Control" , "Chromaticity Control"
+      Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
+
+      Page      "Panel Power Sequencing"
+        Link      "Close Table", ".."
+
+        Combo     $LcdVcc_On_During_S0_State_09, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
+        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
+                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
+                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
+                  "Note: This option is only applicable for Windows Graphics driver."
+
+        Combo     $eDP_T3_Optimization_09, "T3 optimization", &Disabled_Enabled_List,
+        Help      "This feature enables or disables T3 optimization. \r\n"
+                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
+                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"
+
+        EditNum   $eDP_Vcc_To_Hpd_Delay_09, "LCDVCC to HPD high delay (T3):", DEC,
+        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 200msec\r\n"
+
+        EditNum   $eDP_DataOn_To_BkltEnable_Delay_09, "Valid video data to Backlight Enable delay (T8):", DEC,
+        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
+                  "T8 is inclusive of T7.\r\n"
+                  "Valid Range of T7: 0 to 50msec\r\n"
+
+        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_09, "PWM-On To Backlight Enable delay:", DEC,
+        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
+                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
+                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"
+
+        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_09, "Backlight Disable to PWM-Off delay:", DEC,
+        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
+                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
+                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
+
+        EditNum   $eDP_BkltDisable_To_DataOff_Delay_09, "Backlight Disable to End of Valid video data delay (T9):", DEC,
+        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
+
+        EditNum   $eDP_DataOff_To_PowerOff_Delay_09, "End of Valid video data to Power-Off delay (T10):", DEC,
+        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 500 msec\r\n"
+
+        EditNum   $eDP_PowerCycle_Delay_09, "Power-off time (T12):", DEC,
+        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
+      EndPage
+
+      Page      "DTD Timings"
+        Link      "Close Table" , ".."
+
+        Table     $DVO_Tbl_09 " DTD Timings Values",
+        Column    "Timings" , 1 byte , EHEX,
+        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
+                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
+                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                  "\tByte16 \t: Horizontal Border in pixels\r\n"
+                  "\tByte17 \t: Vertical Border in lines\r\n"
+                  "\tByte18 \t: Flags:\r\n"
+                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
+                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 0:   0 = Reserved"
+      EndPage
+
+      Page      "LFP PnP ID"
+        Link      "Close Table" , ".."
+
+        Table     $LVDS_PnP_ID_09 " LFP PnP ID Values",
+        Column    "PnP ID" , 1 byte , EHEX,
+        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
+                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
+                  " Table Definition:\r\n"
+                  " \tWord:  ID Manufacturer Name\r\n"
+                  " \tWord:  ID Product Code\r\n"
+                  " \tDWord: ID Serial Number\r\n"
+                  " \tByte:  Week of Manufacture\r\n"
+                  " \tByte:  Year of Manufacture"
+      EndPage
+
+      Page      "Backlight Control Parameters"
+        Link      "Close Table" , ".."
+
+        Combo     $BLC_Inv_Type_09, "Inverter Type:", &Inv_Type_List,
+        Help      "This feature allows for the selection of the Backlight Inverter type "
+                  "that is to be used to control the backlight brightness of the LFP. \r\n"
+                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
+                  "via the integrated PWM solution for the applicable chipsets. \r\n"
+                  "When None/External is selected, the system BIOS will control the backlight brightness "
+                  "via the external solution."
+
+        Combo     $Lfp_Pwm_Source_Selection_09, "  Pwm Source Selection:", &Pwm_Source_List,
+        Help      "This field allows to select the Source of the PWM to be used  "
+                  "for the selected Local Flat Panel.\r\n"
+
+        Combo     $BLC_Inv_Polarity_09, "Inverter Polarity:", &Inv_Polarity_List,
+        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
+                  "Normal means 0 value is minimum brightness.\r\n"
+                  "Inverted means 0 value is maximum brightness."
+
+        EditNum   $BLC_Min_Brightness_09, "Minimum Brightness:", DEC,
+        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
+                  "The graphics driver will never decrease the backlight less than this value. "
+                  "The value must be specified using normal polarity semantics."
+
+        EditNum   $POST_BL_Brightness_09, "POST Brightness:", DEC,
+        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
+                  "This is configurable field of 0-255. "
+                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."
+
+        EditNum   $PWM_Frequency_09, "PWM Inverter Frequency (Hz):", DEC,
+        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
+                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
+      EndPage
+
+      Page      "Chromaticity Control"
+        Link      "Close Table" , ".."
+
+        Combo     $Chromacity_Enable_09, "Chromaticity Control Feature", &Disabled_Enabled_List,
+        Help      " This bit enables Chromaticity feature. \r\n"
+                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
+                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
+                  " Please refer to section 3.7 of EDID Specification 1.4"
+
+        Combo     $Override_EDID_Data_09, "Override the EDID values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
+
+        EditNum   $Red_Green_09, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"
+
+        EditNum   $Blue_White_09, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
+
+        EditNum   $Red_x_09, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
+        Help      " Bits 9:2 of red color x coordinate"
+
+        EditNum   $Red_y_09, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
+        Help      " Bits 9:2 of red color y coordinate"
+
+        EditNum   $Green_x_09, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
+        Help      " Bits 9:2 of Green color x coordinate"
+
+        EditNum   $Green_y_09, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
+        Help      " Bits 9:2 of Green color y coordinate"
+
+        EditNum   $Blue_x_09, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
+        Help      " Bits 9:2 of Blue color x coordinate"
+
+        EditNum   $Blue_y_09, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
+        Help      " Bits 9:2 of Blue color y coordinate"
+
+        EditNum   $White_x_09, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
+        Help      " Bits 9:2 of White color x coordinate"
+
+        EditNum   $White_y_09, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
+        Help      " Bits 9:2 of White color y coordinate"
+
+        Combo     $Override_LUM_Data_09, "Override Luminance values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override luminance values following VBT values"
+        EditNum   $MinLuminance_09, "\tMinimum Luminance" , EHEX,
+        Help      "Minimum luminance value. \r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+
+        EditNum   $MaxFullLuminance_09, "\tMaximum full frame luminance" , EHEX,
+        Help      "Maximum Full frame luminance value.\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"        
+
+        EditNum   $MaxLuminance_09,"\tMaximum Luminance" , EHEX,
+        Help      "Maximum luminance value(Relatively smaller portion of screen).\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+        Combo     $Override_Gamma_Data_09, "Override Gamma values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override gamma values through following VBT data"
+
+        EditNum   $Gamma_09, "\tPanel gamma" , EHEX,
+        Help      " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n"
+                  " Field Value = (Gamma (value in float) x 100) - 100 \n"
+                  " Field values range from 00h through FFh. \n"
+                  " FFh = No gamma information shall be provided \n"
+
+      EndPage   ; Chromaticity Control
+
+      Page      "eDP Link Training Configuration Parameters"
+        Link      "Close Table" , ".."
+
+        TitleB    "Full Link Training Parameters"
+
+        Combo     $eDP_Full_Link_Training_Params_Enable_09, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
+        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."
+
+        Combo     $eDP_Full_Link_Train_PreEmp_09, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Full_Link_Train_Vswing_09, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Title     "  "
+
+        TitleB    "Fast Link Training Parameters"
+        Combo     $eDP_Fast_Link_Training_Supported_09, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
+        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."
+
+        EditNum   $eDP_Fast_Link_Training_Data_Rate_09, "\tData Rate:", DEC,
+        Help      "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_LaneCount_09, "\tLane Count:", &eDP_Link_LaneCount_List,
+        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_PreEmp_09, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Link_Vswing_09, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+      EndPage
+
+      Page      "PSR feature"
+        Link      "Close Table" , ".."
+
+        Combo     $PSR_FullLink_Enable_09, "Full Link enable:", &Yes_No_List,
+        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."
+
+        Combo     $PSR_Require_AUX2Wakeup_09, "Require AUX to wake up:", &Yes_No_List,
+        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."
+
+        Combo     $PSR_Lines2Wait_B4LinkS3_09, "Lines to wait before link standby:", &wait_line_link,
+        Help      "This field determines Lines to wait before link standby \n"
+                  " 0 lines to wait (Default)\r\n"
+                  " 1 lines to wait\r\n"
+                  " 4 lines to wait\r\n"
+                  " 8 lines to wait\r\n"
+                  " Others Reserved"
+
+        EditNum   $PSR_IdleFrames2Wait_09, "Idle frames to wait:", DEC,
+        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."
+
+        Combo     $PSR_TP1_WaitTime_09, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
+
+        Combo     $PSR_TP_2_3_WaitTime_09, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
+      EndPage   ; PSR feature
+
+      Page      "Apical Feature"
+        Link      "Close Table" , ".."
+
+        Combo     $eDP_Apical_Display_Ip_Enable_09, "Apical Assertive Display IP", &Disabled_Enabled_List,
+        Help      "This field enables/disables the Apical Assertive Display IP for this panel."
+
+        EditNum   $eDP_Panel_Oui_09, "\tPanel OUI (IEEE OUI)", EHEX,
+        Help      "This field specifies the Apical IP specific Panel OUI field."
+
+        EditNum   $eDP_Dpcd_Base_Address_09, "\tDPCD Base Address", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD base address field."
+
+        EditNum   $eDP_Dpcd_Irdidix_Control0_09, "\tDPCD Irdidix Control 0", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."
+
+        EditNum   $eDP_Dpcd_Option_Select_09, "\tDPCD Option Select", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD option select field."
+
+        EditNum   $eDP_Dpcd_Backlight_09, "\tDPCD Backlight", EHEX,
+        Help      "This field specifies the Apical IP specific backlight value."
+
+        EditNum   $eDP_Ambient_Light_09, "\tAmbient Light", EHEX,
+        Help      "This field specifies the Apical IP specific Ambient light value."
+
+        EditNum   $eDP_Backlight_Scale_09, "\tBacklight scale", EHEX,
+        Help      "This field specifies the Apical IP specific backlight scale field."
+      EndPage   ; Apical Feature
+
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_09, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_09, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_09, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_09, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled. "
+
+        Combo     $ADT_Enable_09, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_09, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_09, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Automatic Display Brightness is to be enabled. "
+                  "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action."  
+
+        Combo     $LACE_Status_09, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_09, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"      
+                  
+        Combo     $LACE_Aggressiveness_Profile_09, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"            
+      EndPage   ; Power Features
+    EndPage
+
+    ;==============================================================================
+    ; Page - Panel #10 (1920x1200) Flat Panel parameters
+    ;------------------------------------------------------------------------------
+    Page      "Panel #10 "
+      EditText  $Panel_Name_10, "LFP panel name:",
+      Help      "This feature defines the LFP panel name, used by driver only. "
+                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."
+
+      EditNum   $Panel_Width_10, "LFP Width:", DEC,
+      Help      "This value specifies the LFP pixel width for this panel type."
+
+      EditNum   $Panel_Height_10, "LFP Height:", DEC,
+      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."
+
+      Combo     $eDP_VSwingPreEmph_10, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
+      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
+                "For Coffeelake, based on the selection respective table will be used.\r\n"
+                "Tables for Coffeelake: \r\n"
+                "Low Power VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
+                "\r\n\r\n"
+
+                "Default VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"
+
+      Combo     $eDP_Panel_Color_Depth_10, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
+      Help      "This feature specifies the color depth of eDP panel used."
+
+      Combo     $Panel_Rotation_10, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
+      TitleB    "eDP Spread Spectrum Clock Features"
+      Combo     $Enable_SSC10, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
+      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."
+
+      TitleB    "DPS Panel Type Features (Mobile only)"
+      Combo     $DPS_Panel_Type_10, "\tDPS Panel Type:", &DPS_Panel_Type_List,
+      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
+                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
+                "SDRRS:- Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience.\r\n"
+                "Seamless:-  Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience."
+                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
+                "during the refresh rate transitions"
+
+      TitleB    "BackLight Technology Type Features (Mobile only)"
+      Combo     $Blt_Control_10, "\tBackLight Technology:", &Blt_Control_Type_List,
+      Help      "This feature allows OEM to select the Backlight Technology."
+
+      Title     " "
+      Link      "PSR feature" ,"PSR feature"
+      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
+      Link      "DTD Timings Table" , "DTD Timings"
+      Link      "LFP PnP ID Table" , "LFP PnP ID"
+      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
+      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
+      Link      "Chromaticity Control" , "Chromaticity Control"
+      Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
+
+      Page      "Panel Power Sequencing"
+        Link      "Close Table", ".."
+
+        Combo     $LcdVcc_On_During_S0_State_10, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
+        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
+                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
+                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
+                  "Note: This option is only applicable for Windows Graphics driver."
+
+        Combo     $eDP_T3_Optimization_10, "T3 optimization", &Disabled_Enabled_List,
+        Help      "This feature enables or disables T3 optimization. \r\n"
+                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
+                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"
+
+        EditNum   $eDP_Vcc_To_Hpd_Delay_10, "LCDVCC to HPD high delay (T3):", DEC,
+        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 200msec\r\n"
+
+        EditNum   $eDP_DataOn_To_BkltEnable_Delay_10, "Valid video data to Backlight Enable delay (T8):", DEC,
+        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
+                  "T8 is inclusive of T7.\r\n"
+                  "Valid Range of T7: 0 to 50msec\r\n"
+
+        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_10, "PWM-On To Backlight Enable delay:", DEC,
+        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
+                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
+                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"
+
+        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_10, "Backlight Disable to PWM-Off delay:", DEC,
+        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
+                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
+                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
+
+        EditNum   $eDP_BkltDisable_To_DataOff_Delay_10, "Backlight Disable to End of Valid video data delay (T9):", DEC,
+        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
+
+        EditNum   $eDP_DataOff_To_PowerOff_Delay_10, "End of Valid video data to Power-Off delay (T10):", DEC,
+        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 500 msec\r\n"
+
+        EditNum   $eDP_PowerCycle_Delay_10, "Power-off time (T12):", DEC,
+        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
+      EndPage
+
+      Page      "DTD Timings"
+        Link      "Close Table" , ".."
+
+        Table     $DVO_Tbl_10 " DTD Timings Values",
+        Column    "Timings" , 1 byte , EHEX,
+        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
+                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
+                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                  "\tByte16 \t: Horizontal Border in pixels\r\n"
+                  "\tByte17 \t: Vertical Border in lines\r\n"
+                  "\tByte18 \t: Flags:\r\n"
+                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
+                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 0:   0 = Reserved"
+      EndPage
+
+      Page      "LFP PnP ID"
+        Link      "Close Table" , ".."
+
+        Table     $LVDS_PnP_ID_10 " LFP PnP ID Values",
+        Column    "PnP ID" , 1 byte , EHEX,
+        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
+                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
+                  " Table Definition:\r\n"
+                  " \tWord:  ID Manufacturer Name\r\n"
+                  " \tWord:  ID Product Code\r\n"
+                  " \tDWord: ID Serial Number\r\n"
+                  " \tByte:  Week of Manufacture\r\n"
+                  " \tByte:  Year of Manufacture"
+      EndPage
+
+      Page      "Backlight Control Parameters"
+        Link      "Close Table" , ".."
+
+        Combo     $BLC_Inv_Type_10, "Inverter Type:", &Inv_Type_List,
+        Help      "This feature allows for the selection of the Backlight Inverter type "
+                  "that is to be used to control the backlight brightness of the LFP. \r\n"
+                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
+                  "via the integrated PWM solution for the applicable chipsets. \r\n"
+                  "When None/External is selected, the system BIOS will control the backlight brightness "
+                  "via the external solution."
+
+        Combo     $Lfp_Pwm_Source_Selection_10, "  Pwm Source Selection:", &Pwm_Source_List,
+        Help      "This field allows to select the Source of the PWM to be used  "
+                  "for the selected Local Flat Panel.\r\n"
+
+        Combo     $BLC_Inv_Polarity_10, "Inverter Polarity:", &Inv_Polarity_List,
+        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
+                  "Normal means 0 value is minimum brightness.\r\n"
+                  "Inverted means 0 value is maximum brightness."
+
+        EditNum   $BLC_Min_Brightness_10, "Minimum Brightness:", DEC,
+        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
+                  "The graphics driver will never decrease the backlight less than this value. "
+                  "The value must be specified using normal polarity semantics."
+
+        EditNum   $POST_BL_Brightness_10, "POST Brightness:", DEC,
+        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
+                  "This is configurable field of 0-255. "
+                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."
+
+        EditNum   $PWM_Frequency_10, "PWM Inverter Frequency (Hz):", DEC,
+        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
+                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
+      EndPage
+
+      Page      "Chromaticity Control"
+        Link      "Close Table" , ".."
+
+        Combo     $Chromacity_Enable_10, "Chromaticity Control Feature", &Disabled_Enabled_List,
+        Help      " This bit enables Chromaticity feature. \r\n"
+                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
+                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
+                  " Please refer to section 3.7 of EDID Specification 1.4"
+
+        Combo     $Override_EDID_Data_10, "Override the EDID values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
+
+
+
+        EditNum   $Red_Green_10, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"
+
+        EditNum   $Blue_White_10, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
+
+        EditNum   $Red_x_10, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
+        Help      " Bits 9:2 of red color x coordinate"
+
+        EditNum   $Red_y_10, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
+        Help      " Bits 9:2 of red color y coordinate"
+
+        EditNum   $Green_x_10, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
+        Help      " Bits 9:2 of Green color x coordinate"
+
+        EditNum   $Green_y_10, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
+        Help      " Bits 9:2 of Green color y coordinate"
+
+        EditNum   $Blue_x_10, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
+        Help      " Bits 9:2 of Blue color x coordinate"
+
+        EditNum   $Blue_y_10, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
+        Help      " Bits 9:2 of Blue color y coordinate"
+
+        EditNum   $White_x_10, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
+        Help      " Bits 9:2 of White color x coordinate"
+
+        EditNum   $White_y_10, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
+        Help      " Bits 9:2 of White color y coordinate"
+
+        Combo     $Override_LUM_Data_10, "Override Luminance values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override luminance values following VBT values"
+        EditNum   $MinLuminance_10, "\tMinimum Luminance" , EHEX,
+        Help      "Minimum luminance value. \r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+
+        EditNum   $MaxFullLuminance_10, "\tMaximum full frame luminance" , EHEX,
+        Help      "Maximum Full frame luminance value.\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"        
+
+        EditNum   $MaxLuminance_10,"\tMaximum Luminance" , EHEX,
+        Help      "Maximum luminance value(Relatively smaller portion of screen).\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+        Combo     $Override_Gamma_Data_10, "Override Gamma values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override gamma values through following VBT data"
+
+        EditNum   $Gamma_10, "\tPanel gamma" , EHEX,
+        Help      " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n"
+                  " Field Value = (Gamma (value in float) x 100) - 100 \n"
+                  " Field values range from 00h through FFh. \n"
+                  " FFh = No gamma information shall be provided \n"
+
+      EndPage   ; Chromaticity Control
+
+      Page      "eDP Link Training Configuration Parameters"
+        Link      "Close Table" , ".."
+
+        TitleB    "Full Link Training Parameters"
+
+        Combo     $eDP_Full_Link_Training_Params_Enable_10, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
+        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."
+
+        Combo     $eDP_Full_Link_Train_PreEmp_10, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Full_Link_Train_Vswing_10, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Title     "  "
+
+        TitleB    "Fast Link Training Parameters"
+        Combo     $eDP_Fast_Link_Training_Supported_10, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
+        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."
+
+        EditNum   $eDP_Fast_Link_Training_Data_Rate_10, "\tData Rate:", DEC,
+        Help      "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_LaneCount_10, "\tLane Count:", &eDP_Link_LaneCount_List,
+        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_PreEmp_10, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Link_Vswing_10, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+      EndPage
+
+      Page      "PSR feature"
+        Link      "Close Table" , ".."
+
+        Combo     $PSR_FullLink_Enable_10, "Full Link enable:", &Yes_No_List,
+        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."
+
+        Combo     $PSR_Require_AUX2Wakeup_10, "Require AUX to wake up:", &Yes_No_List,
+        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."
+
+        Combo     $PSR_Lines2Wait_B4LinkS3_10, "Lines to wait before link standby:", &wait_line_link,
+        Help      "This field determines Lines to wait before link standby \n"
+                  " 0 lines to wait (Default)\r\n"
+                  " 1 lines to wait\r\n"
+                  " 4 lines to wait\r\n"
+                  " 8 lines to wait\r\n"
+                  " Others Reserved"
+
+        EditNum   $PSR_IdleFrames2Wait_10, "Idle frames to wait:", DEC,
+        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."
+
+        Combo     $PSR_TP1_WaitTime_10, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
+
+        Combo     $PSR_TP_2_3_WaitTime_10, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
+      EndPage   ; PSR feature
+
+      Page      "Apical Feature"
+        Link      "Close Table" , ".."
+
+        Combo     $eDP_Apical_Display_Ip_Enable_10, "Apical Assertive Display IP", &Disabled_Enabled_List,
+        Help      "This field enables/disables the Apical Assertive Display IP for this panel."
+
+        EditNum   $eDP_Panel_Oui_10, "\tPanel OUI (IEEE OUI)", EHEX,
+        Help      "This field specifies the Apical IP specific Panel OUI field."
+
+        EditNum   $eDP_Dpcd_Base_Address_10, "\tDPCD Base Address", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD base address field."
+
+        EditNum   $eDP_Dpcd_Irdidix_Control0_10, "\tDPCD Irdidix Control 0", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."
+
+        EditNum   $eDP_Dpcd_Option_Select_10, "\tDPCD Option Select", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD option select field."
+
+        EditNum   $eDP_Dpcd_Backlight_10, "\tDPCD Backlight", EHEX,
+        Help      "This field specifies the Apical IP specific backlight value."
+
+        EditNum   $eDP_Ambient_Light_10, "\tAmbient Light", EHEX,
+        Help      "This field specifies the Apical IP specific Ambient light value."
+
+        EditNum   $eDP_Backlight_Scale_10, "\tBacklight scale", EHEX,
+        Help      "This field specifies the Apical IP specific backlight scale field."
+      EndPage   ; Apical Feature
+
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_10, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_10, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_10, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_10, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled. "
+
+        Combo     $ADT_Enable_10, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_10, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_10, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Automatic Display Brightness is to be enabled. "
+                  "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action."   
+
+        Combo     $LACE_Status_10, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_10, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"
+                  
+        Combo     $LACE_Aggressiveness_Profile_10, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"                   
+      EndPage   ; Power Features
+    EndPage
+
+    ;==============================================================================
+    ; Page - Panel #11 (Reserved) Flat Panel parameters
+    ;------------------------------------------------------------------------------
+    Page      "Panel #11 "
+      EditText  $Panel_Name_11, "LFP panel name:",
+      Help      "This feature defines the LFP panel name, used by driver only. "
+                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."
+
+      EditNum   $Panel_Width_11, "LFP Width:", DEC,
+      Help      "This value specifies the LFP pixel width for this panel type."
+
+      EditNum   $Panel_Height_11, "LFP Height:", DEC,
+      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."
+
+      Combo     $eDP_VSwingPreEmph_11, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
+      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
+                "For Coffeelake, based on the selection respective table will be used.\r\n"
+                "Tables for Coffeelake: \r\n"
+                "Low Power VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
+                "\r\n\r\n"
+
+                "Default VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"
+
+      Combo     $eDP_Panel_Color_Depth_11, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
+      Help      "This feature specifies the color depth of eDP panel used."
+
+      Combo     $Panel_Rotation_11, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
+      TitleB    "eDP Spread Spectrum Clock Features"
+      Combo     $Enable_SSC11, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
+      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."
+
+      TitleB    "DPS Panel Type Features (Mobile only)"
+      Combo     $DPS_Panel_Type_11, "\tDPS Panel Type:", &DPS_Panel_Type_List,
+      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
+                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
+                "SDRRS:- Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience.\r\n"
+                "Seamless:-  Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience."
+                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
+                "during the refresh rate transitions"
+
+      TitleB    "BackLight Technology Type Features (Mobile only)"
+      Combo     $Blt_Control_11, "\tBackLight Technology:", &Blt_Control_Type_List,
+      Help      "This feature allows OEM to select the Backlight Technology."
+
+      Title     " "
+      Link      "PSR feature" ,"PSR feature"
+      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
+      Link      "DTD Timings Table" , "DTD Timings"
+      Link      "LFP PnP ID Table" , "LFP PnP ID"
+      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
+      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
+      Link      "Chromaticity Control" , "Chromaticity Control"
+      Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
+
+      Page      "Panel Power Sequencing"
+        Link      "Close Table", ".."
+
+        Combo     $LcdVcc_On_During_S0_State_11, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
+        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
+                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
+                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
+                  "Note: This option is only applicable for Windows Graphics driver."
+
+        Combo     $eDP_T3_Optimization_11, "T3 optimization", &Disabled_Enabled_List,
+        Help      "This feature enables or disables T3 optimization. \r\n"
+                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
+                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"
+
+        EditNum   $eDP_Vcc_To_Hpd_Delay_11, "LCDVCC to HPD high delay (T3):", DEC,
+        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 200msec\r\n"
+
+        EditNum   $eDP_DataOn_To_BkltEnable_Delay_11, "Valid video data to Backlight Enable delay (T8):", DEC,
+        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
+                  "T8 is inclusive of T7.\r\n"
+                  "Valid Range of T7: 0 to 50msec\r\n"
+
+        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_11, "PWM-On To Backlight Enable delay:", DEC,
+        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
+                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
+                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"
+
+        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_11, "Backlight Disable to PWM-Off delay:", DEC,
+        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
+                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
+                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
+
+        EditNum   $eDP_BkltDisable_To_DataOff_Delay_11, "Backlight Disable to End of Valid video data delay (T9):", DEC,
+        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
+
+        EditNum   $eDP_DataOff_To_PowerOff_Delay_11, "End of Valid video data to Power-Off delay (T10):", DEC,
+        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 500 msec\r\n"
+
+        EditNum   $eDP_PowerCycle_Delay_11, "Power-off time (T12):", DEC,
+        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
+      EndPage
+
+      Page      "DTD Timings"
+        Link      "Close Table" , ".."
+
+        Table     $DVO_Tbl_11 " DTD Timings Values",
+        Column    "Timings" , 1 byte , EHEX,
+        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
+                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
+                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                  "\tByte16 \t: Horizontal Border in pixels\r\n"
+                  "\tByte17 \t: Vertical Border in lines\r\n"
+                  "\tByte18 \t: Flags:\r\n"
+                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
+                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 0:   0 = Reserved"
+      EndPage
+
+      Page      "LFP PnP ID"
+        Link      "Close Table" , ".."
+
+        Table     $LVDS_PnP_ID_11 " LFP PnP ID Values",
+        Column    "PnP ID" , 1 byte , EHEX,
+        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
+                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
+                  " Table Definition:\r\n"
+                  " \tWord:  ID Manufacturer Name\r\n"
+                  " \tWord:  ID Product Code\r\n"
+                  " \tDWord: ID Serial Number\r\n"
+                  " \tByte:  Week of Manufacture\r\n"
+                  " \tByte:  Year of Manufacture"
+      EndPage
+
+      Page      "Backlight Control Parameters"
+        Link      "Close Table" , ".."
+
+        Combo     $BLC_Inv_Type_11, "Inverter Type:", &Inv_Type_List,
+        Help      "This feature allows for the selection of the Backlight Inverter type "
+                  "that is to be used to control the backlight brightness of the LFP. \r\n"
+                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
+                  "via the integrated PWM solution for the applicable chipsets. \r\n"
+                  "When None/External is selected, the system BIOS will control the backlight brightness "
+                  "via the external solution."
+
+        Combo     $Lfp_Pwm_Source_Selection_11, "  Pwm Source Selection:", &Pwm_Source_List,
+        Help      "This field allows to select the Source of the PWM to be used  "
+                  "for the selected Local Flat Panel.\r\n"
+
+        Combo     $BLC_Inv_Polarity_11, "Inverter Polarity:", &Inv_Polarity_List,
+        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
+                  "Normal means 0 value is minimum brightness.\r\n"
+                  "Inverted means 0 value is maximum brightness."
+
+        EditNum   $BLC_Min_Brightness_11, "Minimum Brightness:", DEC,
+        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
+                  "The graphics driver will never decrease the backlight less than this value. "
+                  "The value must be specified using normal polarity semantics."
+
+        EditNum   $POST_BL_Brightness_11, "POST Brightness:", DEC,
+        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
+                  "This is configurable field of 0-255. "
+                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."
+
+        EditNum   $PWM_Frequency_11, "PWM Inverter Frequency (Hz):", DEC,
+        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
+                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
+      EndPage
+
+      Page      "Chromaticity Control"
+        Link      "Close Table" , ".."
+
+        Combo     $Chromacity_Enable_11, "Chromaticity Control Feature", &Disabled_Enabled_List,
+        Help      " This bit enables Chromaticity feature. \r\n"
+                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
+                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
+                  " Please refer to section 3.7 of EDID Specification 1.4"
+
+        Combo     $Override_EDID_Data_11, "Override the EDID values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
+
+        EditNum   $Red_Green_11, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"
+
+        EditNum   $Blue_White_11, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
+
+        EditNum   $Red_x_11, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
+        Help      " Bits 9:2 of red color x coordinate"
+
+        EditNum   $Red_y_11, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
+        Help      " Bits 9:2 of red color y coordinate"
+
+        EditNum   $Green_x_11, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
+        Help      " Bits 9:2 of Green color x coordinate"
+
+        EditNum   $Green_y_11, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
+        Help      " Bits 9:2 of Green color y coordinate"
+
+        EditNum   $Blue_x_11, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
+        Help      " Bits 9:2 of Blue color x coordinate"
+
+        EditNum   $Blue_y_11, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
+        Help      " Bits 9:2 of Blue color y coordinate"
+
+        EditNum   $White_x_11, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
+        Help      " Bits 9:2 of White color x coordinate"
+
+        EditNum   $White_y_11, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
+        Help      " Bits 9:2 of White color y coordinate"
+
+        Combo     $Override_LUM_Data_11, "Override Luminance values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override luminance values following VBT values"
+        EditNum   $MinLuminance_11, "\tMinimum Luminance" , EHEX,
+        Help      "Minimum luminance value. \r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+
+        EditNum   $MaxFullLuminance_11, "\tMaximum full frame luminance" , EHEX,
+        Help      "Maximum Full frame luminance value.\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"        
+
+        EditNum   $MaxLuminance_11,"\tMaximum Luminance" , EHEX,
+        Help      "Maximum luminance value(Relatively smaller portion of screen).\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+        Combo     $Override_Gamma_Data_11, "Override Gamma values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override gamma values through following VBT data"
+
+        EditNum   $Gamma_11, "\tPanel gamma" , EHEX,
+        Help      " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n"
+                  " Field Value = (Gamma (value in float) x 100) - 100 \n"
+                  " Field values range from 00h through FFh. \n"
+                  " FFh = No gamma information shall be provided \n"
+
+      EndPage   ; Chromaticity Control
+
+      Page      "eDP Link Training Configuration Parameters"
+        Link      "Close Table" , ".."
+
+        TitleB    "Full Link Training Parameters"
+
+        Combo     $eDP_Full_Link_Training_Params_Enable_11, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
+        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."
+
+        Combo     $eDP_Full_Link_Train_PreEmp_11, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Full_Link_Train_Vswing_11, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Title     "  "
+
+        TitleB    "Fast Link Training Parameters"
+        Combo     $eDP_Fast_Link_Training_Supported_11, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
+        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."
+
+        EditNum   $eDP_Fast_Link_Training_Data_Rate_11, "\tData Rate:", DEC,
+        Help      "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_LaneCount_11, "\tLane Count:", &eDP_Link_LaneCount_List,
+        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_PreEmp_11, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Link_Vswing_11, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+      EndPage
+
+      Page      "PSR feature"
+        Link      "Close Table" , ".."
+
+        Combo     $PSR_FullLink_Enable_11, "Full Link enable:", &Yes_No_List,
+        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."
+
+        Combo     $PSR_Require_AUX2Wakeup_11, "Require AUX to wake up:", &Yes_No_List,
+        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."
+
+        Combo     $PSR_Lines2Wait_B4LinkS3_11, "Lines to wait before link standby:", &wait_line_link,
+        Help      "This field determines Lines to wait before link standby \n"
+                  " 0 lines to wait (Default)\r\n"
+                  " 1 lines to wait\r\n"
+                  " 4 lines to wait\r\n"
+                  " 8 lines to wait\r\n"
+                  " Others Reserved"
+
+        EditNum   $PSR_IdleFrames2Wait_11, "Idle frames to wait:", DEC,
+        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."
+
+        Combo     $PSR_TP1_WaitTime_11, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
+
+        Combo     $PSR_TP_2_3_WaitTime_11, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
+      EndPage   ; PSR feature
+
+      Page      "Apical Feature"
+        Link      "Close Table" , ".."
+
+        Combo     $eDP_Apical_Display_Ip_Enable_11, "Apical Assertive Display IP", &Disabled_Enabled_List,
+        Help      "This field enables/disables the Apical Assertive Display IP for this panel."
+
+        EditNum   $eDP_Panel_Oui_11, "\tPanel OUI (IEEE OUI)", EHEX,
+        Help      "This field specifies the Apical IP specific Panel OUI field."
+
+        EditNum   $eDP_Dpcd_Base_Address_11, "\tDPCD Base Address", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD base address field."
+
+        EditNum   $eDP_Dpcd_Irdidix_Control0_11, "\tDPCD Irdidix Control 0", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."
+
+        EditNum   $eDP_Dpcd_Option_Select_11, "\tDPCD Option Select", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD option select field."
+
+        EditNum   $eDP_Dpcd_Backlight_11, "\tDPCD Backlight", EHEX,
+        Help      "This field specifies the Apical IP specific backlight value."
+
+        EditNum   $eDP_Ambient_Light_11, "\tAmbient Light", EHEX,
+        Help      "This field specifies the Apical IP specific Ambient light value."
+
+        EditNum   $eDP_Backlight_Scale_11, "\tBacklight scale", EHEX,
+        Help      "This field specifies the Apical IP specific backlight scale field."
+      EndPage   ; Apical Feature
+
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_11, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_11, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_11, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_11, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled. " 
+
+        Combo     $ADT_Enable_11, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_11, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_11, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Automatic Display Brightness is to be enabled. "
+                  "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_11, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_11, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST  )\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"   
+                  
+        Combo     $LACE_Aggressiveness_Profile_11, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"
+      EndPage   ; Power Features
+    EndPage
+
+    ;==============================================================================
+    ; Page - Panel #12 (Reserved) Flat Panel parameters
+    ;------------------------------------------------------------------------------
+    Page      "Panel #12 "
+      EditText  $Panel_Name_12, "LFP panel name:",
+      Help      "This feature defines the LFP panel name, used by driver only. "
+                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."
+
+      EditNum   $Panel_Width_12, "LFP Width:", DEC,
+      Help      "This value specifies the LFP pixel width for this panel type."
+
+      EditNum   $Panel_Height_12, "LFP Height:", DEC,
+      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."
+
+      Combo     $eDP_VSwingPreEmph_12, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
+      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
+                "For Coffeelake, based on the selection respective table will be used.\r\n"
+                "Tables for Coffeelake: \r\n"
+                "Low Power VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
+                "\r\n\r\n"
+
+                "Default VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"
+
+      Combo     $eDP_Panel_Color_Depth_12, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
+      Help      "This feature specifies the color depth of eDP panel used."
+
+      Combo     $Panel_Rotation_12, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
+      TitleB    "eDP Spread Spectrum Clock Features"
+      Combo     $Enable_SSC12, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
+      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."
+
+      TitleB    "DPS Panel Type Features (Mobile only)"
+      Combo     $DPS_Panel_Type_12, "\tDPS Panel Type:", &DPS_Panel_Type_List,
+      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
+                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
+                "SDRRS:- Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience.\r\n"
+                "Seamless:-  Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience."
+                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
+                "during the refresh rate transitions"
+
+      TitleB    "BackLight Technology Type Features (Mobile only)"
+      Combo     $Blt_Control_12, "\tBackLight Technology:", &Blt_Control_Type_List,
+      Help      "This feature allows OEM to select the Backlight Technology."
+
+      Title     " "
+      Link      "PSR feature" ,"PSR feature"
+      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
+      Link      "DTD Timings Table" , "DTD Timings"
+      Link      "LFP PnP ID Table" , "LFP PnP ID"
+      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
+      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
+      Link      "Chromaticity Control" , "Chromaticity Control"
+      Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
+
+      Page      "Panel Power Sequencing"
+        Link      "Close Table", ".."
+
+        Combo     $LcdVcc_On_During_S0_State_12, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
+        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
+                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
+                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
+                  "Note: This option is only applicable for Windows Graphics driver."
+
+        Combo     $eDP_T3_Optimization_12, "T3 optimization", &Disabled_Enabled_List,
+        Help      "This feature enables or disables T3 optimization. \r\n"
+                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
+                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"
+
+        EditNum   $eDP_Vcc_To_Hpd_Delay_12, "LCDVCC to HPD high delay (T3):", DEC,
+        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 200msec\r\n"
+
+        EditNum   $eDP_DataOn_To_BkltEnable_Delay_12, "Valid video data to Backlight Enable delay (T8):", DEC,
+        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
+                  "T8 is inclusive of T7.\r\n"
+                  "Valid Range of T7: 0 to 50msec\r\n"
+
+        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_12, "PWM-On To Backlight Enable delay:", DEC,
+        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
+                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
+                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"
+
+        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_12, "Backlight Disable to PWM-Off delay:", DEC,
+        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
+                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
+                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
+
+        EditNum   $eDP_BkltDisable_To_DataOff_Delay_12, "Backlight Disable to End of Valid video data delay (T9):", DEC,
+        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
+
+        EditNum   $eDP_DataOff_To_PowerOff_Delay_12, "End of Valid video data to Power-Off delay (T10):", DEC,
+        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 500 msec\r\n"
+
+        EditNum   $eDP_PowerCycle_Delay_12, "Power-off time (T12):", DEC,
+        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
+      EndPage
+
+      Page      "DTD Timings"
+        Link      "Close Table" , ".."
+
+        Table     $DVO_Tbl_12 " DTD Timings Values",
+        Column    "Timings" , 1 byte , EHEX,
+        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
+                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
+                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                  "\tByte16 \t: Horizontal Border in pixels\r\n"
+                  "\tByte17 \t: Vertical Border in lines\r\n"
+                  "\tByte18 \t: Flags:\r\n"
+                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
+                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 0:   0 = Reserved"
+      EndPage
+
+      Page      "LFP PnP ID"
+        Link      "Close Table" , ".."
+
+        Table     $LVDS_PnP_ID_12 " LFP PnP ID Values",
+        Column    "PnP ID" , 1 byte , EHEX,
+        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
+                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
+                  " Table Definition:\r\n"
+                  " \tWord:  ID Manufacturer Name\r\n"
+                  " \tWord:  ID Product Code\r\n"
+                  " \tDWord: ID Serial Number\r\n"
+                  " \tByte:  Week of Manufacture\r\n"
+                  " \tByte:  Year of Manufacture"
+      EndPage
+
+      Page      "Backlight Control Parameters"
+        Link      "Close Table" , ".."
+
+        Combo     $BLC_Inv_Type_12, "Inverter Type:", &Inv_Type_List,
+        Help      "This feature allows for the selection of the Backlight Inverter type "
+                  "that is to be used to control the backlight brightness of the LFP. \r\n"
+                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
+                  "via the integrated PWM solution for the applicable chipsets. \r\n"
+                  "When None/External is selected, the system BIOS will control the backlight brightness "
+                  "via the external solution."
+
+        Combo     $Lfp_Pwm_Source_Selection_12, "  Pwm Source Selection:", &Pwm_Source_List,
+        Help      "This field allows to select the Source of the PWM to be used  "
+                  "for the selected Local Flat Panel.\r\n"
+
+        Combo     $BLC_Inv_Polarity_12, "Inverter Polarity:", &Inv_Polarity_List,
+        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
+                  "Normal means 0 value is minimum brightness.\r\n"
+                  "Inverted means 0 value is maximum brightness."
+
+        EditNum   $BLC_Min_Brightness_12, "Minimum Brightness:", DEC,
+        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
+                  "The graphics driver will never decrease the backlight less than this value. "
+                  "The value must be specified using normal polarity semantics."
+
+        EditNum   $POST_BL_Brightness_12, "POST Brightness:", DEC,
+        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
+                  "This is configurable field of 0-255. "
+                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."
+
+        EditNum   $PWM_Frequency_12, "PWM Inverter Frequency (Hz):", DEC,
+        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
+                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
+      EndPage
+
+      Page      "Chromaticity Control"
+        Link      "Close Table" , ".."
+
+        Combo     $Chromacity_Enable_12, "Chromaticity Control Feature", &Disabled_Enabled_List,
+        Help      " This bit enables Chromaticity feature. \r\n"
+                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
+                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
+                  " Please refer to section 3.7 of EDID Specification 1.4"
+
+        Combo     $Override_EDID_Data_12, "Override the EDID values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
+
+        EditNum   $Red_Green_12, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"
+
+        EditNum   $Blue_White_12, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
+
+        EditNum   $Red_x_12, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
+        Help      " Bits 9:2 of red color x coordinate"
+
+        EditNum   $Red_y_12, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
+        Help      " Bits 9:2 of red color y coordinate"
+
+        EditNum   $Green_x_12, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
+        Help      " Bits 9:2 of Green color x coordinate"
+
+        EditNum   $Green_y_12, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
+        Help      " Bits 9:2 of Green color y coordinate"
+
+        EditNum   $Blue_x_12, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
+        Help      " Bits 9:2 of Blue color x coordinate"
+
+        EditNum   $Blue_y_12, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
+        Help      " Bits 9:2 of Blue color y coordinate"
+
+        EditNum   $White_x_12, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
+        Help      " Bits 9:2 of White color x coordinate"
+
+        EditNum   $White_y_12, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
+        Help      " Bits 9:2 of White color y coordinate"
+
+        Combo     $Override_LUM_Data_12, "Override Luminance values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override luminance values following VBT values"
+        EditNum   $MinLuminance_12, "\tMinimum Luminance" , EHEX,
+        Help      "Minimum luminance value. \r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+
+        EditNum   $MaxFullLuminance_12, "\tMaximum full frame luminance" , EHEX,
+        Help      "Maximum Full frame luminance value.\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"        
+
+        EditNum   $MaxLuminance_12,"\tMaximum Luminance" , EHEX,
+        Help      "Maximum luminance value(Relatively smaller portion of screen).\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+        Combo     $Override_Gamma_Data_12, "Override Gamma values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override gamma values through following VBT data"
+
+        EditNum   $Gamma_12, "\tPanel gamma" , EHEX,
+        Help      " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n"
+                  " Field Value = (Gamma (value in float) x 100) - 100 \n"
+                  " Field values range from 00h through FFh. \n"
+                  " FFh = No gamma information shall be provided \n"
+
+      EndPage   ; Chromaticity Control
+
+      Page      "eDP Link Training Configuration Parameters"
+
+        Link      "Close Table" , ".."
+
+        TitleB    "Full Link Training Parameters"
+
+        Combo     $eDP_Full_Link_Training_Params_Enable_12, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
+        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."
+
+        Combo     $eDP_Full_Link_Train_PreEmp_12, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Full_Link_Train_Vswing_12, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Title     "  "
+
+        TitleB    "Fast Link Training Parameters"
+        Combo     $eDP_Fast_Link_Training_Supported_12, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
+        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."
+
+        EditNum   $eDP_Fast_Link_Training_Data_Rate_12, "\tData Rate:", DEC,
+        Help      "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_LaneCount_12, "\tLane Count:", &eDP_Link_LaneCount_List,
+        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_PreEmp_12, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Link_Vswing_12, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+      EndPage
+
+      Page      "PSR feature"
+        Link      "Close Table" , ".."
+
+        Combo     $PSR_FullLink_Enable_12, "Full Link enable:", &Yes_No_List,
+        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."
+
+        Combo     $PSR_Require_AUX2Wakeup_12, "Require AUX to wake up:", &Yes_No_List,
+        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."
+
+        Combo     $PSR_Lines2Wait_B4LinkS3_12, "Lines to wait before link standby:", &wait_line_link,
+        Help      "This field determines Lines to wait before link standby \n"
+                  " 0 lines to wait (Default)\r\n"
+                  " 1 lines to wait\r\n"
+                  " 4 lines to wait\r\n"
+                  " 8 lines to wait\r\n"
+                  " Others Reserved"
+
+        EditNum   $PSR_IdleFrames2Wait_12, "Idle frames to wait:", DEC,
+        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."
+
+        Combo     $PSR_TP1_WaitTime_12, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
+
+        Combo     $PSR_TP_2_3_WaitTime_12, "  TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
+      EndPage   ; PSR feature
+
+      Page      "Apical Feature"
+        Link      "Close Table" , ".."
+
+        Combo     $eDP_Apical_Display_Ip_Enable_12, "Apical Assertive Display IP", &Disabled_Enabled_List,
+        Help      "This field enables/disables the Apical Assertive Display IP for this panel."
+
+        EditNum   $eDP_Panel_Oui_12, "\tPanel OUI (IEEE OUI)", EHEX,
+        Help      "This field specifies the Apical IP specific Panel OUI field."
+
+        EditNum   $eDP_Dpcd_Base_Address_12, "\tDPCD Base Address", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD base address field."
+
+        EditNum   $eDP_Dpcd_Irdidix_Control0_12, "\tDPCD Irdidix Control 0", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."
+
+        EditNum   $eDP_Dpcd_Option_Select_12, "\tDPCD Option Select", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD option select field."
+
+        EditNum   $eDP_Dpcd_Backlight_12, "\tDPCD Backlight", EHEX,
+        Help      "This field specifies the Apical IP specific backlight value."
+
+        EditNum   $eDP_Ambient_Light_12, "\tAmbient Light", EHEX,
+        Help      "This field specifies the Apical IP specific Ambient light value."
+
+        EditNum   $eDP_Backlight_Scale_12, "\tBacklight scale", EHEX,
+        Help      "This field specifies the Apical IP specific backlight scale field."
+      EndPage   ; Apical Feature
+
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_12, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_12, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_12, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_12, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled. "
+
+        Combo     $ADT_Enable_12, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_12, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled."
+
+        Combo     $ADB_Enable_12, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Automatic Display Brightness is to be enabled. "
+                  "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_12, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_12, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"    
+                  
+        Combo     $LACE_Aggressiveness_Profile_12, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"             
+      EndPage   ; Power Features
+    EndPage
+
+    ;==============================================================================
+    ; Page - Panel #13 (Reserved) Flat Panel parameters
+    ;------------------------------------------------------------------------------
+    Page      "Panel #13 "
+      EditText  $Panel_Name_13, "LFP panel name:",
+      Help      "This feature defines the LFP panel name, used by driver only. "
+                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."
+
+      EditNum   $Panel_Width_13, "LFP Width:", DEC,
+      Help      "This value specifies the LFP pixel width for this panel type."
+
+      EditNum   $Panel_Height_13, "LFP Height:", DEC,
+      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."
+
+      Combo     $eDP_VSwingPreEmph_13, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
+      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
+                "For Coffeelake, based on the selection respective table will be used.\r\n"
+                "Tables for Coffeelake: \r\n"
+                "Low Power VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
+                "\r\n\r\n"
+
+                "Default VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"
+
+      Combo     $eDP_Panel_Color_Depth_13, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
+      Help      "This feature specifies the color depth of eDP panel used."
+
+      Combo     $Panel_Rotation_13, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
+      TitleB    "eDP Spread Spectrum Clock Features"
+      Combo     $Enable_SSC13, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
+      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."
+
+      TitleB    "DPS Panel Type Features (Mobile only)"
+      Combo     $DPS_Panel_Type_13, "\tDPS Panel Type:", &DPS_Panel_Type_List,
+      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
+                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
+                "SDRRS:- Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience.\r\n"
+                "Seamless:-  Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience."
+                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
+                "during the refresh rate transitions"
+
+      TitleB    "BackLight Technology Type Features (Mobile only)"
+      Combo     $Blt_Control_13, "\tBackLight Technology:", &Blt_Control_Type_List,
+      Help      "This feature allows OEM to select the Backlight Technology."
+
+      Title     " "
+      Link      "PSR feature" ,"PSR feature"
+      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
+      Link      "DTD Timings Table" , "DTD Timings"
+      Link      "LFP PnP ID Table" , "LFP PnP ID"
+      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
+      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
+      Link      "Chromaticity Control" , "Chromaticity Control"
+      Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
+
+      Page      "Panel Power Sequencing"
+        Link      "Close Table", ".."
+
+        Combo     $LcdVcc_On_During_S0_State_13, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
+        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
+                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
+                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
+                  "Note: This option is only applicable for Windows Graphics driver."
+
+        Combo     $eDP_T3_Optimization_13, "T3 optimization", &Disabled_Enabled_List,
+        Help      "This feature enables or disables T3 optimization. \r\n"
+                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
+                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"
+
+        EditNum   $eDP_Vcc_To_Hpd_Delay_13, "LCDVCC to HPD high delay (T3):", DEC,
+        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 200msec\r\n"
+
+        EditNum   $eDP_DataOn_To_BkltEnable_Delay_13, "Valid video data to Backlight Enable delay (T8):", DEC,
+        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
+                  "T8 is inclusive of T7.\r\n"
+                  "Valid Range of T7: 0 to 50msec\r\n"
+
+        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_13, "PWM-On To Backlight Enable delay:", DEC,
+        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
+                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
+                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"
+
+        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_13, "Backlight Disable to PWM-Off delay:", DEC,
+        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
+                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
+                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
+
+        EditNum   $eDP_BkltDisable_To_DataOff_Delay_13, "Backlight Disable to End of Valid video data delay (T9):", DEC,
+        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
+
+        EditNum   $eDP_DataOff_To_PowerOff_Delay_13, "End of Valid video data to Power-Off delay (T10):", DEC,
+        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 500 msec\r\n"
+
+        EditNum   $eDP_PowerCycle_Delay_13, "Power-off time (T12):", DEC,
+        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
+      EndPage
+
+      Page      "DTD Timings"
+        Link      "Close Table" , ".."
+
+        Table     $DVO_Tbl_13 " DTD Timings Values",
+        Column    "Timings" , 1 byte , EHEX,
+        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
+                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
+                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                  "\tByte16 \t: Horizontal Border in pixels\r\n"
+                  "\tByte17 \t: Vertical Border in lines\r\n"
+                  "\tByte18 \t: Flags:\r\n"
+                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
+                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 0:   0 = Reserved"
+      EndPage
+
+      Page      "LFP PnP ID"
+        Link      "Close Table" , ".."
+
+        Table     $LVDS_PnP_ID_13 " LFP PnP ID Values",
+        Column    "PnP ID" , 1 byte , EHEX,
+        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
+                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
+                  " Table Definition:\r\n"
+                  " \tWord:  ID Manufacturer Name\r\n"
+                  " \tWord:  ID Product Code\r\n"
+                  " \tDWord: ID Serial Number\r\n"
+                  " \tByte:  Week of Manufacture\r\n"
+                  " \tByte:  Year of Manufacture"
+      EndPage
+
+      Page      "Backlight Control Parameters"
+        Link      "Close Table" , ".."
+
+        Combo     $BLC_Inv_Type_13, "Inverter Type:", &Inv_Type_List,
+        Help      "This feature allows for the selection of the Backlight Inverter type "
+                  "that is to be used to control the backlight brightness of the LFP. \r\n"
+                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
+                  "via the integrated PWM solution for the applicable chipsets. \r\n"
+                  "When None/External is selected, the system BIOS will control the backlight brightness "
+                  "via the external solution."
+
+        Combo     $Lfp_Pwm_Source_Selection_13, "  Pwm Source Selection:", &Pwm_Source_List,
+        Help      "This field allows to select the Source of the PWM to be used  "
+                  "for the selected Local Flat Panel.\r\n"
+
+        Combo     $BLC_Inv_Polarity_13, "Inverter Polarity:", &Inv_Polarity_List,
+        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
+                  "Normal means 0 value is minimum brightness.\r\n"
+                  "Inverted means 0 value is maximum brightness."
+
+        EditNum   $BLC_Min_Brightness_13, "Minimum Brightness:", DEC,
+        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
+                  "The graphics driver will never decrease the backlight less than this value. "
+                  "The value must be specified using normal polarity semantics."
+
+        EditNum   $POST_BL_Brightness_13, "POST Brightness:", DEC,
+        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
+                  "This is configurable field of 0-255. "
+                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."
+
+        EditNum   $PWM_Frequency_13, "PWM Inverter Frequency (Hz):", DEC,
+        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
+                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
+      EndPage
+
+      Page      "Chromaticity Control"
+        Link      "Close Table" , ".."
+
+        Combo     $Chromacity_Enable_13, "Chromaticity Control Feature", &Disabled_Enabled_List,
+        Help      " This bit enables Chromaticity feature. \r\n"
+                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
+                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
+                  " Please refer to section 3.7 of EDID Specification 1.4"
+
+        Combo     $Override_EDID_Data_13, "Override the EDID values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
+
+
+
+        EditNum   $Red_Green_13, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"
+
+        EditNum   $Blue_White_13, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
+
+        EditNum   $Red_x_13, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
+        Help      " Bits 9:2 of red color x coordinate"
+
+        EditNum   $Red_y_13, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
+        Help      " Bits 9:2 of red color y coordinate"
+
+        EditNum   $Green_x_13, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
+        Help      " Bits 9:2 of Green color x coordinate"
+
+        EditNum   $Green_y_13, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
+        Help      " Bits 9:2 of Green color y coordinate"
+
+        EditNum   $Blue_x_13, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
+        Help      " Bits 9:2 of Blue color x coordinate"
+
+        EditNum   $Blue_y_13, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
+        Help      " Bits 9:2 of Blue color y coordinate"
+
+        EditNum   $White_x_13, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
+        Help      " Bits 9:2 of White color x coordinate"
+
+        EditNum   $White_y_13, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
+        Help      " Bits 9:2 of White color y coordinate"
+
+        Combo     $Override_LUM_Data_13, "Override Luminance values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override luminance values following VBT values"
+        EditNum   $MinLuminance_13, "\tMinimum Luminance" , EHEX,
+        Help      "Minimum luminance value. \r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+
+        EditNum   $MaxFullLuminance_13, "\tMaximum full frame luminance" , EHEX,
+        Help      "Maximum Full frame luminance value.\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"        
+
+        EditNum   $MaxLuminance_13,"\tMaximum Luminance" , EHEX,
+        Help      "Maximum luminance value(Relatively smaller portion of screen).\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+        Combo     $Override_Gamma_Data_13, "Override Gamma values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override gamma values through following VBT data"
+
+        EditNum   $Gamma_13, "\tPanel gamma" , EHEX,
+        Help      " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n"
+                  " Field Value = (Gamma (value in float) x 100) - 100 \n"
+                  " Field values range from 00h through FFh. \n"
+                  " FFh = No gamma information shall be provided \n"
+
+      EndPage   ; Chromaticity Control
+
+      Page      "eDP Link Training Configuration Parameters"
+
+        Link      "Close Table" , ".."
+
+        TitleB    "Full Link Training Parameters"
+
+        Combo     $eDP_Full_Link_Training_Params_Enable_13, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
+        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."
+
+        Combo     $eDP_Full_Link_Train_PreEmp_13, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Full_Link_Train_Vswing_13, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Title     "  "
+
+        TitleB    "Fast Link Training Parameters"
+        Combo     $eDP_Fast_Link_Training_Supported_13, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
+        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."
+
+        EditNum   $eDP_Fast_Link_Training_Data_Rate_13, "\tData Rate:", DEC,
+        Help      "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_LaneCount_13, "\tLane Count:", &eDP_Link_LaneCount_List,
+        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_PreEmp_13, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Link_Vswing_13, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+      EndPage
+
+      Page      "PSR feature"
+        Link      "Close Table" , ".."
+
+        Combo     $PSR_FullLink_Enable_13, "Full Link enable:", &Yes_No_List,
+        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."
+
+        Combo     $PSR_Require_AUX2Wakeup_13, "Require AUX to wake up:", &Yes_No_List,
+        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."
+
+        Combo     $PSR_Lines2Wait_B4LinkS3_13, "Lines to wait before link standby:", &wait_line_link,
+        Help      "This field determines Lines to wait before link standby \n"
+                  " 0 lines to wait (Default)\r\n"
+                  " 1 lines to wait\r\n"
+                  " 4 lines to wait\r\n"
+                  " 8 lines to wait\r\n"
+                  " Others Reserved"
+
+        EditNum   $PSR_IdleFrames2Wait_13, "Idle frames to wait:", DEC,
+        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."
+
+        Combo     $PSR_TP1_WaitTime_13, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
+
+        Combo     $PSR_TP_2_3_WaitTime_13, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
+      EndPage   ; PSR feature
+
+      Page      "Apical Feature"
+        Link      "Close Table" , ".."
+
+        Combo     $eDP_Apical_Display_Ip_Enable_13, "Apical Assertive Display IP", &Disabled_Enabled_List,
+        Help      "This field enables/disables the Apical Assertive Display IP for this panel."
+
+        EditNum   $eDP_Panel_Oui_13, "\tPanel OUI (IEEE OUI)", EHEX,
+        Help      "This field specifies the Apical IP specific Panel OUI field."
+
+        EditNum   $eDP_Dpcd_Base_Address_13, "\tDPCD Base Address", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD base address field."
+
+        EditNum   $eDP_Dpcd_Irdidix_Control0_13, "\tDPCD Irdidix Control 0", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."
+
+        EditNum   $eDP_Dpcd_Option_Select_13, "\tDPCD Option Select", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD option select field."
+
+        EditNum   $eDP_Dpcd_Backlight_13, "\tDPCD Backlight", EHEX,
+        Help      "This field specifies the Apical IP specific backlight value."
+
+        EditNum   $eDP_Ambient_Light_13, "\tAmbient Light", EHEX,
+        Help      "This field specifies the Apical IP specific Ambient light value."
+
+        EditNum   $eDP_Backlight_Scale_13, "\tBacklight scale", EHEX,
+        Help      "This field specifies the Apical IP specific backlight scale field."
+      EndPage   ; Apical Feature
+
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_13, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_13, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_13, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_13, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled. "
+
+        Combo     $ADT_Enable_13, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_13, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_13, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Automatic Display Brightness is to be enabled. "
+                  "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_13, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_13, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"               
+                  
+        Combo     $LACE_Aggressiveness_Profile_13, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"
+      EndPage   ; Power Features
+    EndPage
+
+    ;==============================================================================
+    ; Page - Panel #14 (1280x800) Flat Panel parameters
+    ;------------------------------------------------------------------------------
+    Page      "Panel #14 "
+      EditText  $Panel_Name_14, "LFP panel name:",
+      Help      "This feature defines the LFP panel name, used by driver only. "
+                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."
+
+      EditNum   $Panel_Width_14, "LFP Width:", DEC,
+      Help      "This value specifies the LFP pixel width for this panel type."
+
+      EditNum   $Panel_Height_14, "LFP Height:", DEC,
+      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."
+
+      Combo     $eDP_VSwingPreEmph_14, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
+      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
+                "For Coffeelake, based on the selection respective table will be used.\r\n"
+                "Tables for Coffeelake: \r\n"
+                "Low Power VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
+                "\r\n\r\n"
+
+                "Default VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"
+
+      Combo     $eDP_Panel_Color_Depth_14, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
+      Help      "This feature specifies the color depth of eDP panel used."
+
+      Combo     $Panel_Rotation_14, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
+      TitleB    "eDP Spread Spectrum Clock Features"
+      Combo     $Enable_SSC14, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
+      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."
+
+      TitleB    "DPS Panel Type Features (Mobile only)"
+      Combo     $DPS_Panel_Type_14, "\tDPS Panel Type:", &DPS_Panel_Type_List,
+      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
+                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
+                "SDRRS:- Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience.\r\n"
+                "Seamless:-  Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience."
+                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
+                "during the refresh rate transitions"
+
+      TitleB    "BackLight Technology Type Features (Mobile only)"
+      Combo     $Blt_Control_14, "\tBackLight Technology:", &Blt_Control_Type_List,
+      Help      "This feature allows OEM to select the Backlight Technology."
+
+      Title     " "
+      Link      "PSR feature" ,"PSR feature"
+      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
+      Link      "DTD Timings Table" , "DTD Timings"
+      Link      "LFP PnP ID Table" , "LFP PnP ID"
+      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
+      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
+      Link      "Chromaticity Control" , "Chromaticity Control"
+      Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
+
+      Page      "Panel Power Sequencing"
+        Link      "Close Table", ".."
+
+        Combo     $LcdVcc_On_During_S0_State_14, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
+        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
+                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
+                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
+                  "Note: This option is only applicable for Windows Graphics driver."
+
+        Combo     $eDP_T3_Optimization_14, "T3 optimization", &Disabled_Enabled_List,
+        Help      "This feature enables or disables T3 optimization. \r\n"
+                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
+                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"
+
+        EditNum   $eDP_Vcc_To_Hpd_Delay_14, "LCDVCC to HPD high delay (T3):", DEC,
+        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 200msec\r\n"
+
+        EditNum   $eDP_DataOn_To_BkltEnable_Delay_14, "Valid video data to Backlight Enable delay (T8):", DEC,
+        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
+                  "T8 is inclusive of T7.\r\n"
+                  "Valid Range of T7: 0 to 50msec\r\n"
+
+        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_14, "PWM-On To Backlight Enable delay:", DEC,
+        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
+                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
+                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"
+
+        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_14, "Backlight Disable to PWM-Off delay:", DEC,
+        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
+                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
+                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
+
+        EditNum   $eDP_BkltDisable_To_DataOff_Delay_14, "Backlight Disable to End of Valid video data delay (T9):", DEC,
+        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
+
+        EditNum   $eDP_DataOff_To_PowerOff_Delay_14, "End of Valid video data to Power-Off delay (T10):", DEC,
+        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 500 msec\r\n"
+
+        EditNum   $eDP_PowerCycle_Delay_14, "Power-off time (T12):", DEC,
+        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
+      EndPage
+
+      Page      "DTD Timings"
+        Link      "Close Table" , ".."
+
+        Table     $DVO_Tbl_14 " DTD Timings Values",
+        Column    "Timings" , 1 byte , EHEX,
+        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
+                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
+                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                  "\tByte16 \t: Horizontal Border in pixels\r\n"
+                  "\tByte17 \t: Vertical Border in lines\r\n"
+                  "\tByte18 \t: Flags:\r\n"
+                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
+                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 0:   0 = Reserved"
+      EndPage
+
+      Page      "LFP PnP ID"
+        Link      "Close Table" , ".."
+
+        Table     $LVDS_PnP_ID_14 " LFP PnP ID Values",
+        Column    "PnP ID" , 1 byte , EHEX,
+        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
+                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
+                  " Table Definition:\r\n"
+                  " \tWord:  ID Manufacturer Name\r\n"
+                  " \tWord:  ID Product Code\r\n"
+                  " \tDWord: ID Serial Number\r\n"
+                  " \tByte:  Week of Manufacture\r\n"
+                  " \tByte:  Year of Manufacture"
+      EndPage
+
+      Page      "Backlight Control Parameters"
+        Link      "Close Table" , ".."
+
+        Combo     $BLC_Inv_Type_14, "Inverter Type:", &Inv_Type_List,
+        Help      "This feature allows for the selection of the Backlight Inverter type "
+                  "that is to be used to control the backlight brightness of the LFP. \r\n"
+                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
+                  "via the integrated PWM solution for the applicable chipsets. \r\n"
+                  "When None/External is selected, the system BIOS will control the backlight brightness "
+                  "via the external solution."
+
+        Combo     $Lfp_Pwm_Source_Selection_14, "  Pwm Source Selection:", &Pwm_Source_List,
+        Help      "This field allows to select the Source of the PWM to be used  "
+                  "for the selected Local Flat Panel.\r\n"
+
+        Combo     $BLC_Inv_Polarity_14, "Inverter Polarity:", &Inv_Polarity_List,
+        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
+                  "Normal means 0 value is minimum brightness.\r\n"
+                  "Inverted means 0 value is maximum brightness."
+
+        EditNum   $BLC_Min_Brightness_14, "Minimum Brightness:", DEC,
+        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
+                  "The graphics driver will never decrease the backlight less than this value. "
+                  "The value must be specified using normal polarity semantics."
+
+        EditNum   $POST_BL_Brightness_14, "POST Brightness:", DEC,
+        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
+                  "This is configurable field of 0-255. "
+                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."
+
+        EditNum   $PWM_Frequency_14, "PWM Inverter Frequency (Hz):", DEC,
+        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
+                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
+      EndPage
+
+      Page      "Chromaticity Control"
+        Link      "Close Table" , ".."
+
+        Combo     $Chromacity_Enable_14, "Chromaticity Control Feature", &Disabled_Enabled_List,
+        Help      " This bit enables Chromaticity feature. \r\n"
+                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
+                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
+                  " Please refer to section 3.7 of EDID Specification 1.4"
+
+        Combo     $Override_EDID_Data_14, "Override the EDID values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
+
+        EditNum   $Red_Green_14, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"
+
+        EditNum   $Blue_White_14, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
+
+        EditNum   $Red_x_14, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
+        Help      " Bits 9:2 of red color x coordinate"
+
+        EditNum   $Red_y_14, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
+        Help      " Bits 9:2 of red color y coordinate"
+
+        EditNum   $Green_x_14, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
+        Help      " Bits 9:2 of Green color x coordinate"
+
+        EditNum   $Green_y_14, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
+        Help      " Bits 9:2 of Green color y coordinate"
+
+        EditNum   $Blue_x_14, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
+        Help      " Bits 9:2 of Blue color x coordinate"
+
+        EditNum   $Blue_y_14, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
+        Help      " Bits 9:2 of Blue color y coordinate"
+
+        EditNum   $White_x_14, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
+        Help      " Bits 9:2 of White color x coordinate"
+
+        EditNum   $White_y_14, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
+        Help      " Bits 9:2 of White color y coordinate"
+
+        Combo     $Override_LUM_Data_14, "Override Luminance values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override luminance values following VBT values"
+        EditNum   $MinLuminance_14, "\tMinimum Luminance" , EHEX,
+        Help      "Minimum luminance value. \r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+
+        EditNum   $MaxFullLuminance_14, "\tMaximum full frame luminance" , EHEX,
+        Help      "Maximum Full frame luminance value.\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"        
+
+        EditNum   $MaxLuminance_14,"\tMaximum Luminance" , EHEX,
+        Help      "Maximum luminance value(Relatively smaller portion of screen).\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+        Combo     $Override_Gamma_Data_14, "Override Gamma values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override gamma values through following VBT data"
+
+        EditNum   $Gamma_14, "\tPanel gamma" , EHEX,
+        Help      " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n"
+                  " Field Value = (Gamma (value in float) x 100) - 100 \n"
+                  " Field values range from 00h through FFh. \n"
+                  " FFh = No gamma information shall be provided \n"
+
+      EndPage   ; Chromaticity Control
+
+      Page      "eDP Link Training Configuration Parameters"
+        Link      "Close Table" , ".."
+
+        TitleB    "Full Link Training Parameters"
+
+        Combo     $eDP_Full_Link_Training_Params_Enable_14, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
+        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."
+
+        Combo     $eDP_Full_Link_Train_PreEmp_14, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Full_Link_Train_Vswing_14, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Title     "  "
+
+        TitleB    "Fast Link Training Parameters"
+        Combo     $eDP_Fast_Link_Training_Supported_14, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
+        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."
+
+        EditNum   $eDP_Fast_Link_Training_Data_Rate_14, "\tData Rate:", DEC,
+        Help      "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_LaneCount_14, "\tLane Count:", &eDP_Link_LaneCount_List,
+        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_PreEmp_14, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Link_Vswing_14, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+      EndPage
+
+      Page      "PSR feature"
+        Link      "Close Table" , ".."
+
+        Combo     $PSR_FullLink_Enable_14, "Full Link enable:", &Yes_No_List,
+        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."
+
+        Combo     $PSR_Require_AUX2Wakeup_14, "Require AUX to wake up:", &Yes_No_List,
+        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."
+
+        Combo     $PSR_Lines2Wait_B4LinkS3_14, "Lines to wait before link standby:", &wait_line_link,
+        Help      "This field determines Lines to wait before link standby \n"
+                  " 0 lines to wait (Default)\r\n"
+                  " 1 lines to wait\r\n"
+                  " 4 lines to wait\r\n"
+                  " 8 lines to wait\r\n"
+                  " Others Reserved"
+
+        EditNum   $PSR_IdleFrames2Wait_14, "Idle frames to wait:", DEC,
+        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."
+
+        Combo     $PSR_TP1_WaitTime_14, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
+
+        Combo     $PSR_TP_2_3_WaitTime_14, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
+      EndPage   ; PSR feature
+
+      Page      "Apical Feature"
+        Link      "Close Table" , ".."
+
+        Combo     $eDP_Apical_Display_Ip_Enable_14, "Apical Assertive Display IP", &Disabled_Enabled_List,
+        Help      "This field enables/disables the Apical Assertive Display IP for this panel."
+
+        EditNum   $eDP_Panel_Oui_14, "\tPanel OUI (IEEE OUI)", EHEX,
+        Help      "This field specifies the Apical IP specific Panel OUI field."
+
+        EditNum   $eDP_Dpcd_Base_Address_14, "\tDPCD Base Address", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD base address field."
+
+        EditNum   $eDP_Dpcd_Irdidix_Control0_14, "\tDPCD Irdidix Control 0", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."
+
+        EditNum   $eDP_Dpcd_Option_Select_14, "\tDPCD Option Select", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD option select field."
+
+        EditNum   $eDP_Dpcd_Backlight_14, "\tDPCD Backlight", EHEX,
+        Help      "This field specifies the Apical IP specific backlight value."
+
+        EditNum   $eDP_Ambient_Light_14, "\tAmbient Light", EHEX,
+        Help      "This field specifies the Apical IP specific Ambient light value."
+
+        EditNum   $eDP_Backlight_Scale_14, "\tBacklight scale", EHEX,
+        Help      "This field specifies the Apical IP specific backlight scale field."
+      EndPage   ; Apical Feature
+
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_14, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_14, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_14, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_14, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled. "
+
+        Combo     $ADT_Enable_14, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_14, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_14, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Automatic Display Brightness is to be enabled. "
+                  "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_14, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_14, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"              
+                  
+        Combo     $LACE_Aggressiveness_Profile_14, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Agressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"
+      EndPage   ; Power Features
+    EndPage
+
+    ;==============================================================================
+    ; Page - Panel #15 (1280x600) Flat Panel parameters
+    ;------------------------------------------------------------------------------
+    Page      "Panel #15 "
+      EditText  $Panel_Name_15, "LFP panel name:",
+      Help      "This feature defines the LFP panel name, used by driver only. "
+                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."
+
+      EditNum   $Panel_Width_15, "LFP Width:", DEC,
+      Help      "This value specifies the LFP pixel width for this panel type."
+
+      EditNum   $Panel_Height_15, "LFP Height:", DEC,
+      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."
+
+      Combo     $eDP_VSwingPreEmph_15, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
+      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
+                "For Coffeelake, based on the selection respective table will be used.\r\n"
+                "Tables for Coffeelake: \r\n"
+                "Low Power VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
+                "\r\n\r\n"
+
+                "Default VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"
+
+      Combo     $eDP_Panel_Color_Depth_15, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
+      Help      "This feature specifies the color depth of eDP panel used."
+
+      Combo     $Panel_Rotation_15, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
+      TitleB    "eDP Spread Spectrum Clock Features"
+      Combo     $Enable_SSC15, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
+      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."
+
+      TitleB    "DPS Panel Type Features (Mobile only)"
+      Combo     $DPS_Panel_Type_15, "\tDPS Panel Type:", &DPS_Panel_Type_List,
+      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
+                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
+                "SDRRS:- Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience.\r\n"
+                "Seamless:-  Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience."
+                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
+                "during the refresh rate transitions"
+
+      TitleB    "BackLight Technology Type Features (Mobile only)"
+      Combo     $Blt_Control_15, "\tBackLight Technology:", &Blt_Control_Type_List,
+      Help      "This feature allows OEM to select the Backlight Technology."
+
+      Title     " "
+      Link      "PSR feature" ,"PSR feature"
+      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
+      Link      "DTD Timings Table" , "DTD Timings"
+      Link      "LFP PnP ID Table" , "LFP PnP ID"
+      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
+      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
+      Link      "Chromaticity Control" , "Chromaticity Control"
+      Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
+
+      Page      "Panel Power Sequencing"
+        Link      "Close Table", ".."
+
+        Combo     $LcdVcc_On_During_S0_State_15, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
+        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
+                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
+                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
+                  "Note: This option is only applicable for Windows Graphics driver."
+
+        Combo     $eDP_T3_Optimization_15, "T3 optimization", &Disabled_Enabled_List,
+        Help      "This feature enables or disables T3 optimization. \r\n"
+                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
+                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"
+
+        EditNum   $eDP_Vcc_To_Hpd_Delay_15, "LCDVCC to HPD high delay (T3):", DEC,
+        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 200msec\r\n"
+
+        EditNum   $eDP_DataOn_To_BkltEnable_Delay_15, "Valid video data to Backlight Enable delay (T8):", DEC,
+        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
+                  "T8 is inclusive of T7.\r\n"
+                  "Valid Range of T7: 0 to 50msec\r\n"
+
+        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_15, "PWM-On To Backlight Enable delay:", DEC,
+        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
+                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
+                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"
+
+        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_15, "Backlight Disable to PWM-Off delay:", DEC,
+        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
+                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
+                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
+
+        EditNum   $eDP_BkltDisable_To_DataOff_Delay_15, "Backlight Disable to End of Valid video data delay (T9):", DEC,
+        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
+
+        EditNum   $eDP_DataOff_To_PowerOff_Delay_15, "End of Valid video data to Power-Off delay (T10):", DEC,
+        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 500 msec\r\n"
+
+        EditNum   $eDP_PowerCycle_Delay_15, "Power-off time (T12):", DEC,
+        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
+      EndPage
+
+      Page      "DTD Timings"
+        Link      "Close Table" , ".."
+
+        Table     $DVO_Tbl_15 " DTD Timings Values",
+        Column    "Timings" , 1 byte , EHEX,
+        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
+                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
+                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                  "\tByte16 \t: Horizontal Border in pixels\r\n"
+                  "\tByte17 \t: Vertical Border in lines\r\n"
+                  "\tByte18 \t: Flags:\r\n"
+                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
+                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 0:   0 = Reserved"
+      EndPage
+
+      Page      "LFP PnP ID"
+        Link      "Close Table" , ".."
+
+        Table     $LVDS_PnP_ID_15 " LFP PnP ID Values",
+        Column    "PnP ID" , 1 byte , EHEX,
+        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
+                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
+                  " Table Definition:\r\n"
+                  " \tWord:  ID Manufacturer Name\r\n"
+                  " \tWord:  ID Product Code\r\n"
+                  " \tDWord: ID Serial Number\r\n"
+                  " \tByte:  Week of Manufacture\r\n"
+                  " \tByte:  Year of Manufacture"
+      EndPage
+
+      Page      "Backlight Control Parameters"
+        Link      "Close Table" , ".."
+
+        Combo     $BLC_Inv_Type_15, "Inverter Type:", &Inv_Type_List,
+        Help      "This feature allows for the selection of the Backlight Inverter type "
+                  "that is to be used to control the backlight brightness of the LFP. \r\n"
+                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
+                  "via the integrated PWM solution for the applicable chipsets. \r\n"
+                  "When None/External is selected, the system BIOS will control the backlight brightness "
+                  "via the external solution."
+
+        Combo     $Lfp_Pwm_Source_Selection_15, "  Pwm Source Selection:", &Pwm_Source_List,
+        Help      "This field allows to select the Source of the PWM to be used  "
+                  "for the selected Local Flat Panel.\r\n"
+
+        Combo     $BLC_Inv_Polarity_15, "Inverter Polarity:", &Inv_Polarity_List,
+        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
+                  "Normal means 0 value is minimum brightness.\r\n"
+                  "Inverted means 0 value is maximum brightness."
+
+        EditNum   $BLC_Min_Brightness_15, "Minimum Brightness:", DEC,
+        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
+                  "The graphics driver will never decrease the backlight less than this value. "
+                  "The value must be specified using normal polarity semantics."
+
+        EditNum   $POST_BL_Brightness_15, "POST Brightness:", DEC,
+        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
+                  "This is configurable field of 0-255. "
+                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."
+
+        EditNum   $PWM_Frequency_15, "PWM Inverter Frequency (Hz):", DEC,
+        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
+                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
+      EndPage
+
+      Page      "Chromaticity Control"
+        Link      "Close Table" , ".."
+
+        Combo     $Chromacity_Enable_15, "Chromaticity Control Feature", &Disabled_Enabled_List,
+        Help      " This bit enables Chromaticity feature. \r\n"
+                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
+                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
+                  " Please refer to section 3.7 of EDID Specification 1.4"
+
+        Combo     $Override_EDID_Data_15, "Override the EDID values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
+
+
+
+        EditNum   $Red_Green_15, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"
+
+        EditNum   $Blue_White_15, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
+
+        EditNum   $Red_x_15, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
+        Help      " Bits 9:2 of red color x coordinate"
+
+        EditNum   $Red_y_15, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
+        Help      " Bits 9:2 of red color y coordinate"
+
+        EditNum   $Green_x_15, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
+        Help      " Bits 9:2 of Green color x coordinate"
+
+        EditNum   $Green_y_15, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
+        Help      " Bits 9:2 of Green color y coordinate"
+
+        EditNum   $Blue_x_15, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
+        Help      " Bits 9:2 of Blue color x coordinate"
+
+        EditNum   $Blue_y_15, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
+        Help      " Bits 9:2 of Blue color y coordinate"
+
+        EditNum   $White_x_15, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
+        Help      " Bits 9:2 of White color x coordinate"
+
+        EditNum   $White_y_15, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
+        Help      " Bits 9:2 of White color y coordinate"
+
+        Combo     $Override_LUM_Data_15, "Override Luminance values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override luminance values following VBT values"
+        EditNum   $MinLuminance_15, "\tMinimum Luminance" , EHEX,
+        Help      "Minimum luminance value. \r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+
+        EditNum   $MaxFullLuminance_15, "\tMaximum full frame luminance" , EHEX,
+        Help      "Maximum Full frame luminance value.\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"        
+
+        EditNum   $MaxLuminance_15,"\tMaximum Luminance" , EHEX,
+        Help      "Maximum luminance value(Relatively smaller portion of screen).\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+        Combo     $Override_Gamma_Data_15, "Override Gamma values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override gamma values through following VBT data"
+
+        EditNum   $Gamma_15, "\tPanel gamma" , EHEX,
+        Help      " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n"
+                  " Field Value = (Gamma (value in float) x 100) - 100 \n"
+                  " Field values range from 00h through FFh. \n"
+                  " FFh = No gamma information shall be provided \n"
+
+      EndPage   ; Chromaticity Control
+
+      Page      "eDP Link Training Configuration Parameters"
+        Link      "Close Table" , ".."
+
+        TitleB    "Full Link Training Parameters"
+
+        Combo     $eDP_Full_Link_Training_Params_Enable_15, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
+        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."
+
+        Combo     $eDP_Full_Link_Train_PreEmp_15, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Full_Link_Train_Vswing_15, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Title     "  "
+
+        TitleB    "Fast Link Training Parameters"
+
+        Combo     $eDP_Fast_Link_Training_Supported_15, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
+        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."
+
+        EditNum   $eDP_Fast_Link_Training_Data_Rate_15, "\tData Rate:", DEC,
+        Help      "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_LaneCount_15, "\tLane Count:", &eDP_Link_LaneCount_List,
+        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_PreEmp_15, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Link_Vswing_15, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+      EndPage
+
+      Page      "PSR feature"
+        Link      "Close Table" , ".."
+
+        Combo     $PSR_FullLink_Enable_15, "Full Link enable:", &Yes_No_List,
+        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."
+
+        Combo     $PSR_Require_AUX2Wakeup_15, "Require AUX to wake up:", &Yes_No_List,
+        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."
+
+        Combo     $PSR_Lines2Wait_B4LinkS3_15, "Lines to wait before link standby:", &wait_line_link,
+        Help      "This field determines Lines to wait before link standby \n"
+                  " 0 lines to wait (Default)\r\n"
+                  " 1 lines to wait\r\n"
+                  " 4 lines to wait\r\n"
+                  " 8 lines to wait\r\n"
+                  " Others Reserved"
+
+        EditNum   $PSR_IdleFrames2Wait_15, "Idle frames to wait:", DEC,
+        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."
+
+        Combo     $PSR_TP1_WaitTime_15, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
+
+        Combo     $PSR_TP_2_3_WaitTime_15, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
+      EndPage   ; PSR feature
+
+      Page      "Apical Feature"
+        Link      "Close Table" , ".."
+
+        Combo     $eDP_Apical_Display_Ip_Enable_15, "Apical Assertive Display IP", &Disabled_Enabled_List,
+        Help      "This field enables/disables the Apical Assertive Display IP for this panel."
+
+        EditNum   $eDP_Panel_Oui_15, "\tPanel OUI (IEEE OUI)", EHEX,
+        Help      "This field specifies the Apical IP specific Panel OUI field."
+
+        EditNum   $eDP_Dpcd_Base_Address_15, "\tDPCD Base Address", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD base address field."
+
+        EditNum   $eDP_Dpcd_Irdidix_Control0_15, "\tDPCD Irdidix Control 0", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."
+
+        EditNum   $eDP_Dpcd_Option_Select_15, "\tDPCD Option Select", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD option select field."
+
+        EditNum   $eDP_Dpcd_Backlight_15, "\tDPCD Backlight", EHEX,
+        Help      "This field specifies the Apical IP specific backlight value."
+
+        EditNum   $eDP_Ambient_Light_15, "\tAmbient Light", EHEX,
+        Help      "This field specifies the Apical IP specific Ambient light value."
+
+        EditNum   $eDP_Backlight_Scale_15, "\tBacklight scale", EHEX,
+        Help      "This field specifies the Apical IP specific backlight scale field."
+      EndPage   ; Apical Feature
+
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_15, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_15, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_15, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_15, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled. "
+
+        Combo     $ADT_Enable_15, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_15, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_15, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Automatic Display Brightness is to be enabled. "
+                  "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_15, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_15, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"       
+                  
+        Combo     $LACE_Aggressiveness_Profile_15, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"
+      EndPage   ; Power Features
+    EndPage
+
+    ;==============================================================================
+    ; Page - Panel #16 (Reserved) Flat Panel parameters
+    ;------------------------------------------------------------------------------
+    Page      "Panel #16 "
+      EditText  $Panel_Name_16, "LFP panel name:",
+      Help      "This feature defines the LFP panel name, used by driver only. "
+                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."
+
+      EditNum   $Panel_Width_16, "LFP Width:", DEC,
+      Help      "This value specifies the LFP pixel width for this panel type."
+
+      EditNum   $Panel_Height_16, "LFP Height:", DEC,
+      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."
+
+      Combo     $eDP_VSwingPreEmph_16, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
+      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
+                "For Coffeelake, based on the selection respective table will be used.\r\n"
+                "Tables for Coffeelake: \r\n"
+                "Low Power VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
+                "\r\n\r\n"
+
+                "Default VSwing Pre-Emphasis Setting Table:\n"
+                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
+                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
+                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
+                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
+                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
+                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"
+
+      Combo     $eDP_Panel_Color_Depth_16, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
+      Help      "This feature specifies the color depth of eDP panel used."
+
+      Combo     $Panel_Rotation_16, "Panel Rotation:", &Panel_Rotation_List,
+      Help      "This feature specifies the Panel Rotation of eDP panel used."
+
+      TitleB    "eDP Spread Spectrum Clock Features"
+      Combo     $Enable_SSC16, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
+      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."
+
+      TitleB    "DPS Panel Type Features (Mobile only)"
+      Combo     $DPS_Panel_Type_16, "\tDPS Panel Type:", &DPS_Panel_Type_List,
+      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
+                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
+                "SDRRS:- Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience.\r\n"
+                "Seamless:-  Allows power savings when on battery mode and "
+                "when a lower refresh rate will not adversely impact the user experience."
+                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
+                "during the refresh rate transitions"
+
+      TitleB    "BackLight Technology Type Features (Mobile only)"
+      Combo     $Blt_Control_16, "\tBackLight Technology:", &Blt_Control_Type_List,
+      Help      "This feature allows OEM to select the Backlight Technology."
+
+      Title     " "
+      Link      "PSR feature" ,"PSR feature"
+      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
+      Link      "DTD Timings Table" , "DTD Timings"
+      Link      "LFP PnP ID Table" , "LFP PnP ID"
+      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
+      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
+      Link      "Chromaticity Control" , "Chromaticity Control"
+      Link      "Apical Feature" , "Apical Feature"
+      Link      "Power Features" , "Power Features"
+
+      Page      "Panel Power Sequencing"
+        Link      "Close Table", ".."
+
+        Combo     $LcdVcc_On_During_S0_State_16, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
+        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
+                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
+                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
+                  "Note: This option is only applicable for Windows Graphics driver."
+
+        Combo     $eDP_T3_Optimization_16, "T3 optimization", &Disabled_Enabled_List,
+        Help      "This feature enables or disables T3 optimization. \r\n"
+                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
+                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"
+
+        EditNum   $eDP_Vcc_To_Hpd_Delay_16, "LCDVCC to HPD high delay (T3):", DEC,
+        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 200msec\r\n"
+
+        EditNum   $eDP_DataOn_To_BkltEnable_Delay_16, "Valid video data to Backlight Enable delay (T8):", DEC,
+        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
+                  "T8 is inclusive of T7.\r\n"
+                  "Valid Range of T7: 0 to 50msec\r\n"
+
+        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_16, "PWM-On To Backlight Enable delay:", DEC,
+        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
+                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
+                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"
+
+        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_16, "Backlight Disable to PWM-Off delay:", DEC,
+        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
+                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
+                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
+
+        EditNum   $eDP_BkltDisable_To_DataOff_Delay_16, "Backlight Disable to End of Valid video data delay (T9):", DEC,
+        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
+
+        EditNum   $eDP_DataOff_To_PowerOff_Delay_16, "End of Valid video data to Power-Off delay (T10):", DEC,
+        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
+                  "Valid Range: 0 to 500 msec\r\n"
+
+        EditNum   $eDP_PowerCycle_Delay_16, "Power-off time (T12):", DEC,
+        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
+      EndPage
+
+      Page      "DTD Timings"
+        Link      "Close Table" , ".."
+
+        Table     $DVO_Tbl_16 " DTD Timings Values",
+        Column    "Timings" , 1 byte , EHEX,
+        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
+                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
+                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                  "\tByte16 \t: Horizontal Border in pixels\r\n"
+                  "\tByte17 \t: Vertical Border in lines\r\n"
+                  "\tByte18 \t: Flags:\r\n"
+                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
+                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t    \t:   Bit 0:   0 = Reserved"
+      EndPage
+
+      Page      "LFP PnP ID"
+        Link      "Close Table" , ".."
+
+        Table     $LVDS_PnP_ID_16 " LFP PnP ID Values",
+        Column    "PnP ID" , 1 byte , EHEX,
+        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
+                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
+                  " Table Definition:\r\n"
+                  " \tWord:  ID Manufacturer Name\r\n"
+                  " \tWord:  ID Product Code\r\n"
+                  " \tDWord: ID Serial Number\r\n"
+                  " \tByte:  Week of Manufacture\r\n"
+                  " \tByte:  Year of Manufacture"
+      EndPage
+
+      Page      "Backlight Control Parameters"
+        Link      "Close Table" , ".."
+
+        Combo     $BLC_Inv_Type_16, "Inverter Type:", &Inv_Type_List,
+        Help      "This feature allows for the selection of the Backlight Inverter type "
+                  "that is to be used to control the backlight brightness of the LFP. \r\n"
+                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
+                  "via the integrated PWM solution for the applicable chipsets. \r\n"
+                  "When None/External is selected, the system BIOS will control the backlight brightness "
+                  "via the external solution."
+
+        Combo     $Lfp_Pwm_Source_Selection_16, "  Pwm Source Selection:", &Pwm_Source_List,
+        Help      "This field allows to select the Source of the PWM to be used  "
+                  "for the selected Local Flat Panel.\r\n"
+
+        Combo     $BLC_Inv_Polarity_16, "Inverter Polarity:", &Inv_Polarity_List,
+        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
+                  "Normal means 0 value is minimum brightness.\r\n"
+                  "Inverted means 0 value is maximum brightness."
+
+        EditNum   $BLC_Min_Brightness_16, "Minimum Brightness:", DEC,
+        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
+                  "The graphics driver will never decrease the backlight less than this value. "
+                  "The value must be specified using normal polarity semantics."
+
+        EditNum   $POST_BL_Brightness_16, "POST Brightness:", DEC,
+        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
+                  "This is configurable field of 0-255. "
+                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."
+
+        EditNum   $PWM_Frequency_16, "PWM Inverter Frequency (Hz):", DEC,
+        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
+                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
+      EndPage
+
+      Page      "Chromaticity Control"
+        Link      "Close Table" , ".."
+
+        Combo     $Chromacity_Enable_16, "Chromaticity Control Feature", &Disabled_Enabled_List,
+        Help      " This bit enables Chromaticity feature. \r\n"
+                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
+                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
+                  " Please refer to section 3.7 of EDID Specification 1.4"
+
+        Combo     $Override_EDID_Data_16, "Override the EDID values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
+
+        EditNum   $Red_Green_16, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"
+
+        EditNum   $Blue_White_16, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
+        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
+
+        EditNum   $Red_x_16, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
+        Help      " Bits 9:2 of red color x coordinate"
+
+        EditNum   $Red_y_16, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
+        Help      " Bits 9:2 of red color y coordinate"
+
+        EditNum   $Green_x_16, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
+        Help      " Bits 9:2 of Green color x coordinate"
+
+        EditNum   $Green_y_16, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
+        Help      " Bits 9:2 of Green color y coordinate"
+
+        EditNum   $Blue_x_16, "\tBlue_x (Bits 9:2 at 1F)" , EHEX,
+        Help      " Bits 9:2 of Blue color x coordinate"
+
+        EditNum   $Blue_y_16, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
+        Help      " Bits 9:2 of Blue color y coordinate"
+
+        EditNum   $White_x_16, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
+        Help      " Bits 9:2 of White color x coordinate"
+
+        EditNum   $White_y_16, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
+        Help      " Bits 9:2 of White color y coordinate"
+
+        Combo     $Override_LUM_Data_16, "Override Luminance values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override luminance values following VBT values"
+        EditNum   $MinLuminance_16, "\tMinimum Luminance" , EHEX,
+        Help      "Minimum luminance value. \r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+
+        EditNum   $MaxFullLuminance_16, "\tMaximum full frame luminance" , EHEX,
+        Help      "Maximum Full frame luminance value.\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"        
+
+        EditNum   $MaxLuminance_16,"\tMaximum Luminance" , EHEX,
+        Help      "Maximum luminance value(Relatively smaller portion of screen).\r\n"
+                  "2 byte value, encoded in IEEE 754 half-precision binary floating point format"
+        Combo     $Override_Gamma_Data_16, "Override Gamma values", &No_Yes_List,
+        Help      "This option when enabled along with Chromaticity feature will override gamma values through following VBT data"
+
+        EditNum   $Gamma_16, "\tPanel gamma" , EHEX,
+        Help      " Value shall define the gamma range, from 1.00 to 3.54, as follows: \r\n"
+                  " Field Value = (Gamma (value in float) x 100) - 100 \n"
+                  " Field values range from 00h through FFh. \n"
+                  " FFh = No gamma information shall be provided \n"
+
+      EndPage   ; Chromaticity Control
+
+      Page      "eDP Link Training Configuration Parameters"
+        Link      "Close Table" , ".."
+
+        TitleB    "Full Link Training Parameters"
+
+        Combo     $eDP_Full_Link_Training_Params_Enable_16, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
+        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."
+
+        Combo     $eDP_Full_Link_Train_PreEmp_16, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Full_Link_Train_Vswing_16, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Title     "  "
+
+        TitleB    "Fast Link Training Parameters"
+
+        Combo     $eDP_Fast_Link_Training_Supported_16, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
+        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."
+
+        EditNum   $eDP_Fast_Link_Training_Data_Rate_16, "\tData Rate:", DEC,
+        Help      "This field specifies Data Rate to be used for Fast Link Training in unit of 200KHz for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_LaneCount_16, "\tLane Count:", &eDP_Link_LaneCount_List,
+        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training."
+
+        Combo     $eDP_Link_PreEmp_16, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+
+        Combo     $eDP_Link_Vswing_16, "\tVoltage Swing:", &eDP_Link_VSwing_List,
+        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
+                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
+                  "In case of Coffeelake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
+                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
+                  "For Example: Panel #3 is configured for eDP. "
+                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
+                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
+      EndPage
+
+      Page      "PSR feature"
+        Link      "Close Table" , ".."
+
+        Combo     $PSR_FullLink_Enable_16, "Full Link enable:", &Yes_No_List,
+        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."
+
+        Combo     $PSR_Require_AUX2Wakeup_16, "Require AUX to wake up:", &Yes_No_List,
+        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."
+
+        Combo     $PSR_Lines2Wait_B4LinkS3_16, "Lines to wait before link standby:", &wait_line_link,
+        Help      "This field determines Lines to wait before link standby \n"
+                  " 0 lines to wait (Default)\r\n"
+                  " 1 lines to wait\r\n"
+                  " 4 lines to wait\r\n"
+                  " 8 lines to wait\r\n"
+                  " Others Reserved"
+
+        EditNum   $PSR_IdleFrames2Wait_16, "Idle frames to wait:", DEC,
+        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."
+
+        Combo     $PSR_TP1_WaitTime_16, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
+
+        Combo     $PSR_TP_2_3_WaitTime_16, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
+        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
+      EndPage   ; PSR feature
+
+      Page      "Apical Feature"
+        Link      "Close Table" , ".."
+
+        Combo     $eDP_Apical_Display_Ip_Enable_16, "Apical Assertive Display IP", &Disabled_Enabled_List,
+        Help      "This field enables/disables the Apical Assertive Display IP for this panel."
+
+        EditNum   $eDP_Panel_Oui_16, "\tPanel OUI (IEEE OUI)", EHEX,
+        Help      "This field specifies the Apical IP specific Panel OUI field."
+
+        EditNum   $eDP_Dpcd_Base_Address_16, "\tDPCD Base Address", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD base address field."
+
+        EditNum   $eDP_Dpcd_Irdidix_Control0_16, "\tDPCD Irdidix Control 0", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."
+
+        EditNum   $eDP_Dpcd_Option_Select_16, "\tDPCD Option Select", EHEX,
+        Help      "This field specifies the Apical IP specific DPCD option select field."
+
+        EditNum   $eDP_Dpcd_Backlight_16, "\tDPCD Backlight", EHEX,
+        Help      "This field specifies the Apical IP specific backlight value."
+
+        EditNum   $eDP_Ambient_Light_16, "\tAmbient Light", EHEX,
+        Help      "This field specifies the Apical IP specific Ambient light value."
+
+        EditNum   $eDP_Backlight_Scale_16, "\tBacklight scale", EHEX,
+        Help      "This field specifies the Apical IP specific backlight scale field."
+      EndPage   ; Apical Feature
+
+      Page      "Power Features"
+        Link      "Close Table" , ".."
+
+        Combo     $DPST_Enable_16, "\tIntel Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether the Intel Display Power Savings Technology (DPST) is enabled or disabled. "
+                  "Intel DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
+                  "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
+                  "the LFP is the only active display device."
+
+        Combo     $PSR_Enable_16, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."
+
+        Combo     $DRRS_Enable_16, "\tIntel Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Display Refresh Rate Switching (DRRS) is to be enabled."
+
+        Combo     $LACE_Enable_16, "\tEnable Display Lace Support", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Display Lace Support "
+                  "otherwise, the  functionality will be disabled. "
+
+        Combo     $ADT_Enable_16, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Assertive display technology is to be enabled. "
+
+        Combo     $DMRRS_Enable_16, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
+        Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled. "
+
+        Combo     $ADB_Enable_16, "\tIntel Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
+        Help      "This feature determines whether Intel Automatic Display Brightness is to be enabled. "
+                  "Intel Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
+                  "depending on the current ambient light environment. "
+                  "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
+                  "depending on the ambient environment if and only if the LFP is the only active display. "
+                  "When disabled, the driver will perform no action." 
+
+        Combo     $LACE_Status_16, "\tDefault Display LACE Enabled status", &Disabled_Enabled_List,
+        Help      "This feature, when enabled, will set Default Display LACE Enabled status "
+                  "otherwise, the  functionality will be disabled."
+
+        Combo     $DPST_Aggressiveness_Profile_16, "\tDPST Aggressiveness Level", &Pwr_Pref_List,
+        Help      "This feature allows for the selection of DPST Aggressiveness level for this Panel Type.\n"
+                  "1 (Maximum Quality with No DPST)\n"
+                  "2\n"
+                  "3\n"    
+                  "4\n"    
+                  "5\n"
+                  "6 (Maximum Battery)"              
+                  
+        Combo     $LACE_Aggressiveness_Profile_16, "\tLACE Aggressiveness Level", &Aggressiveness_Level_Profile,
+        Help      "This feature allows for the selection of LACE Aggressiveness level for this Panel Type.\n"
+                  "Minimum   0\n"
+                  "Moderate  1\n"
+                  "High      2"
+      EndPage   ; Power Features
+    EndPage   ; "Panel #16 "
+  EndPage   ; "LFP Configuration"
+
+  ;==============================================================================
+  ; Page - Integrated DisplayPort/HDMI Configuration
+  ;------------------------------------------------------------------------------
+
+  Page      "Integrated DisplayPort/HDMI Configuration with External Connectors"
+    Title     "Configurations for DisplayPort/HDMI Solution (External Connectors):"
+    Link      "Close Window" , ".."
+
+    Title     "DisplayPort SSC configuration: "
+    Combo     $DP_SSC_Enb, "\tDisplayPort (External Connectors) Spread Spectrum Clock:", &Disabled_Enabled_List,
+    Help      "This feature allow OEMs to enable/disable SSC for external DisplayPort. "
+              "This feature is valid only the attached DisplayPort panel support SSC."
+
+    Combo     $DP_SSC_Dongle_Enb, "\tDisplayPort Spread Spectrum Clock Enable/Disable for Dongles:", &Disabled_Enabled_List,
+    Help      "This feature is to enable or disable DisplayPort Dongle Spread Spectrum Clock when dongle are used "
+              "and the attached DisplayPort panel should support SSC"
+
+    Title     "DisplayPort Device Configuration "
+    Link      "Device 1 Configuration" , "Device 1 (EFP1)"
+    Link      "Device 2 Configuration" , "Device 2 (EFP2)"
+    Link      "Device 3 Configuration" , "Device 3 (EFP3)"
+    Link      "Device 4 Configuration" , "Device 4 (EFP4 for DDI-E only)"
+
+    ;==============================================================================
+    ; Page - Device 1 (EFP1)
+    ;------------------------------------------------------------------------------
+    Page      "Device 1 (EFP1)"
+      Link      "Close Window" , ".."
+
+      Combo     $Int_EFP1_Type, "Select Device Type:", &Int_EFP_Device_Type_List,
+      Help      "This feature specifies the Device Type for this add-in device."
+
+      Combo     $Int_EFP1_Port, "Select Output Port:", &Int_EFP_Port_List,
+      Help      "This feature specifies which DVO port the device is configured."
+
+      Combo     $Int_EFP1_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List,
+      Help      "This feature specifies the GPIO pin pair used as DDC bus by this device. "
+                "If this device doesn't support DDC bus, this field will be ignored."
+                "Below is recommended Pin-Pair to Port mapping based on PCH used:"
+
+                "\r\n--------------------------------------------------------------\r\n"
+                "| Pin Pair Values    | CNL-PCH Port Mapping | \r\n"
+                "--------------------------------------------------------------\r\n"
+                "|    N/A    |    Not Used    |  \r\n"
+                "|    Pin-Pair #1    |    DDI-B DDC    |  \r\n"
+                "|    Pin-Pair #2    |    DDI-C DDC    |  \r\n"
+                "|    Pin-Pair #3    |    DDI-D DDC    | \r\n"
+                "--------------------------------------------------------------\r\n"
+
+      Combo     $Int_EFP1_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List,
+      Help      "This feature specifies the AUX Channel for int-DisplayPort. "
+                "This field is valid only if integrated DP is selected for Device Type."
+
+      Combo     $Int_EFP1_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List,
+      Help      "This feature specifies the Level shifter configuration for HDMI. "
+                "This field is valid only if HDMI is selected for Device Type."
+
+      Combo     $Int_EFP1_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List,
+      Help      "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels"
+
+      Combo     $Int_EFP1_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List,
+      Help      "This field is applicable only if IBoost is enabled for the selected port."
+                "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7"
+
+      Combo     $Int_EFP1_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List,
+      Help      "This field is applicable only if IBoost is enabled for the selected port."
+                "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7"
+
+      Title     "    "
+
+      Combo     $EFP1_EDIDless_en, "EDIDless Panel: ", &No_Yes_List,
+      Help      "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority."
+
+      Link      "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings"
+
+      Title     "    "
+
+      Combo     $LSPcon1_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions,
+      Help      "This option is used to enable or disable the OnBoard LSPCON chip."
+
+      Combo     $EFP1_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List,
+      Help      "This feature, when enabled, will set lane reversal bit for selected Port "
+
+      Combo     $EFP1_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List,
+      Help      "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n"
+
+      Combo     $EFP1_DP_Port_Trace_Length, "DP Port trace length: ", &Dp_Port_Trace_Length_List,
+      Help      "This field determines the DP port trace length from silicon to the DP output port.\r\n"
+                "The default setting is as per Intel Reference boards or RVP.\r\n"
+                "Custom boards with short of long trace length may select the trace length appropriately."
+
+      Combo     $Int_EFP1_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List,
+      Help      "This feature will describe if this Port is Dockable or Not."
+
+      Title     "Select DisplayPort Redriver "
+      Link      "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )"
+
+      Page      "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )"
+        Combo     $Int_EFP1_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List,
+        Help      "This feature will describe if Non-Dock Topology/OnBoard Redriver DP Link is present or Not."
+
+        Combo     $Int_EFP1_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\r\n"
+                  "Level 0 (0 dB)\n"
+                  "Level 1 (3.5 dB)\n"
+                  "Level 2 (6.0 dB)\n"
+                  "Level 3 (9.5 dB)"
+
+        Combo     $Int_EFP1_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List,
+        Help      "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\r\n"
+                  "Swing-0 (0.4 V)\n" 
+                  "Swing-1 (0.6 V)\n"
+                  "Swing-2 (0.8 V)\n"
+        ; "Swing-3 (1.2 V)"
+
+        Title     "    "
+        Combo     $Int_EFP1_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List,
+        Help      "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not."
+
+        Combo     $Int_EFP1_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\r\n"
+                  "Level 0 (0 dB)\n"
+                  "Level 1 (3.5 dB)\n"
+                  "Level 2 (6.0 dB)\n"
+                  "Level 3 (9.5 dB)"
+
+        Combo     $Int_EFP1_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List,
+        Help      "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\r\n"
+                  "Swing-0 (0.4 V)\n" 
+                  "Swing-1 (0.6 V)\n"
+                  "Swing-2 (0.8 V)\n"
+        ; "Swing-3 (1.2 V)"
+      EndPage   ; "DisplayPort Redriver Configuration"
+
+      Page      "EDID-less EFP Panel DTD Timings"
+        Link      "Close Table" , ".."
+
+        Table     $EFP1_DTD " DTD Timings Values",
+        Column    "Timings" , 1 byte , EHEX,
+        Help      "This feature allows for the definition of the DTD timings parameters. "
+                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
+                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                  "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                  "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                  "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                  "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                  "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                  "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                  "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                  "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                  "\tByte16 \t: Horizontal Border in pixels\r\n"
+                  "\tByte17 \t: Vertical Border in lines\r\n"
+                  "\tByte18 \t: Flags:\r\n"
+                  "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                  "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
+                  "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                  "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t   \t:   Bit 0:   0 = Reserved"
+      EndPage   ; "EDID-less EFP Panel DTD Timings"
+    EndPage   ; "Device 1 (EFP1)"
+
+    ;==============================================================================
+    ; Page - Device 2 (EFP2)
+    ;------------------------------------------------------------------------------
+    Page      "Device 2 (EFP2)"
+      Link      "Close Window" , ".."
+
+      Combo     $Int_EFP2_Type, "Select Device Type:", &Int_EFP_Device_Type_List,
+      Help      "This feature specifies the Device Type for this add-in device."
+
+      Combo     $Int_EFP2_Port, "Select Output Port:", &Int_EFP_Port_List,
+      Help      "This feature specifies which DVO port the device is configured."
+
+      Combo     $Int_EFP2_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List,
+      Help      "This feature specifies the GPIO pin pair used as DDC bus by this device. "
+                "If this device doesn't support DDC bus, this field will be ignored."
+                "Below is recommended Pin-Pair to Port mapping based on PCH used:"
+
+                "\r\n--------------------------------------------------------------\r\n"
+                "| Pin Pair Values    | CNL-PCH Port Mapping | \r\n"
+                "--------------------------------------------------------------\r\n"
+                "|    N/A    |    Not Used    |  \r\n"
+                "|    Pin-Pair #1    |    DDI-B DDC    |  \r\n"
+                "|    Pin-Pair #2    |    DDI-C DDC    |  \r\n"
+                "|    Pin-Pair #3    |    DDI-D DDC    | \r\n"
+                "--------------------------------------------------------------\r\n"
+
+      Combo     $Int_EFP2_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List,
+      Help      "This feature specifies the AUX Channel for int-DisplayPort. "
+                "This field is valid only if integrated DP is selected for Device Type."
+
+      Combo     $Int_EFP2_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List,
+      Help      "This feature specifies the Level shifter configuration for HDMI. "
+                "This field is valid only if HDMI is selected for Device Type."
+
+      Combo     $Int_EFP2_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List,
+      Help      "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels"
+
+      Combo     $Int_EFP2_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List,
+      Help      "This field is applicable only if IBoost is enabled for the selected port."
+                "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7"
+
+      Combo     $Int_EFP2_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List,
+      Help      "This field is applicable only if IBoost is enabled for the selected port."
+                "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7"
+
+      Title     "    "
+
+      Combo     $EFP2_EDIDless_en, "EDIDless Panel: ", &No_Yes_List,
+      Help      "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority."
+
+      Link      "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings"
+
+      Title     "    "
+
+      Combo     $LSPcon2_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions,
+      Help      "This option is used to enable or disable the OnBoard LSPCON chip."
+
+      Combo     $EFP2_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List,
+      Help      "This feature, when enabled, will set lane reversal bit for selected Port "
+
+      Combo     $EFP2_DP_Port_Trace_Length, "DP Port trace length: ", &Dp_Port_Trace_Length_List,
+      Help      "This field determines the DP port trace length from silicon to the DP output port.\r\n"
+                "The default setting is as per Intel Reference boards or RVP.\r\n"
+                "Custom boards with short of long trace length may select the trace length appropriately."
+
+      Combo     $EFP2_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List,
+      Help      "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n"
+
+      Combo     $Int_EFP2_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List,
+      Help      "This feature will describe if this port is dockable or not."
+
+      Title     "Select DisplayPort Redriver "
+      Link      "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )"
+
+      Page      "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )"
+        Combo     $Int_EFP2_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List,
+        Help      "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not."
+
+        Combo     $Int_EFP2_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\n"
+                  "Level 0 (0 dB)\n"
+                  "Level 1 (3.5 dB)\n"
+                  "Level 2 (6.0 dB)\n"
+                  "Level 3 (9.5 dB)"
+
+        Combo     $Int_EFP2_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List,
+        Help      "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\n"
+                  "Swing-0 (0.4 V)\n" 
+                  "Swing-1 (0.6 V)\n"
+                  "Swing-2 (0.8 V)\n"
+        ; "Swing-3 (1.2 V)"
+
+        Title     "    "
+        Combo     $Int_EFP2_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List,
+        Help      "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n"
+
+        Combo     $Int_EFP2_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\r\n"
+                  "Level 0 (0 dB)\n"
+                  "Level 1 (3.5 dB)\n"
+                  "Level 2 (6.0 dB)\n"
+                  "Level 3 (9.5 dB)"
+
+        Combo     $Int_EFP2_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List,
+        Help      "This feature allows for the selection of voltage swing level for the Dock redriver DP link."
+                  "Swing-0 (0.4 V)\n" 
+                  "Swing-1 (0.6 V)\n"
+                  "Swing-2 (0.8 V)\n"
+        ; "Swing-3 (1.2 V)"
+      EndPage   ; "DisplayPort Redriver Configuration"
+
+      Page      "EDID-less EFP Panel DTD Timings"
+        Link      "Close Table" , ".."
+
+        Table     $EFP2_DTD " DTD Timings Values",
+        Column    "Timings" , 1 byte , EHEX,
+        Help      "This feature allows for the definition of the DTD timings parameters. "
+                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
+                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                  "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                  "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                  "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                  "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                  "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                  "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                  "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                  "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                  "\tByte16 \t: Horizontal Border in pixels\r\n"
+                  "\tByte17 \t: Vertical Border in lines\r\n"
+                  "\tByte18 \t: Flags:\r\n"
+                  "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                  "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
+                  "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                  "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t   \t:   Bit 0:   0 = Reserved"
+      EndPage   ; "EDID-less EFP Panel DTD Timings"
+    EndPage   ; "Device 2"  (EFP2)
+
+    ;==============================================================================
+    ; Page - Device 3 (EFP3)
+    ;------------------------------------------------------------------------------
+    Page      "Device 3 (EFP3)"
+      Link      "Close Window" , ".."
+
+      Combo     $Int_EFP3_Type, "Select Device Type:", &Int_EFP_Device_Type_List,
+      Help      "This feature specifies the Device Type for this add-in device."
+
+      Combo     $Int_EFP3_Port, "Select Output Port:", &Int_EFP_Port_List,
+      Help      "This feature specifies which DVO port the device is configured."
+
+      Combo     $Int_EFP3_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List,
+      Help      "This feature specifies the GPIO pin pair used as DDC bus by this device. "
+                "If this device doesn't support DDC bus, this field will be ignored."
+                "Below is recommended Pin-Pair to Port mapping based on PCH used:"
+
+                "\r\n--------------------------------------------------------------\r\n"
+                "| Pin Pair Values    | CNL-PCH Port Mapping | \r\n"
+                "--------------------------------------------------------------\r\n"
+                "|    N/A    |    Not Used    |  \r\n"
+                "|    Pin-Pair #1    |    DDI-B DDC    |  \r\n"
+                "|    Pin-Pair #2    |    DDI-C DDC    |  \r\n"
+                "|    Pin-Pair #3    |    DDI-D DDC    | \r\n"
+                "--------------------------------------------------------------\r\n"
+
+      Combo     $Int_EFP3_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List,
+      Help      "This feature specifies the AUX Channel for int-DisplayPort. "
+                "This field is valid only if integrated DP is selected for Device Type."
+
+      Combo     $Int_EFP3_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List,
+      Help      "This feature specifies the Level shifter configuration for HDMI. "
+                "This field is valid only if HDMI is selected for Device Type."
+
+      Combo     $Int_EFP3_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List,
+      Help      "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels"
+
+      Combo     $Int_EFP3_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List,
+      Help      "This field is applicable only if IBoost is enabled for the selected port."
+                "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7"
+
+      Combo     $Int_EFP3_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List,
+      Help      "This field is applicable only if IBoost is enabled for the selected port."
+                "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7"
+
+      Title     "    "
+
+      Combo     $EFP3_EDIDless_en, "EDIDless Panel: ", &No_Yes_List,
+      Help      "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority."
+
+      Link      "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings"
+
+      Title     "    "
+
+      Combo     $LSPcon3_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions,
+      Help      "This option is used to enable or disable the OnBoard LSPCON chip."
+
+      Combo     $EFP3_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List,
+      Help      "This feature, when enabled, will set lane reversal bit for selected Port "
+
+      Combo     $EFP3_DP_Port_Trace_Length, "DP Port trace length: ", &Dp_Port_Trace_Length_List,
+      Help      "This field determines the DP port trace length from silicon to the DP output port.\r\n"
+                "The default setting is as per Intel Reference boards or RVP.\r\n"
+                "Custom boards with short of long trace length may select the trace length appropriately."
+
+      Combo     $EFP3_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List,
+      Help      "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n"
+
+      Combo     $Int_EFP3_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List,
+      Help      "This feature will describe if this Port is Dockable or Not."
+
+      Title     "Select DisplayPort Redriver "
+      Link      "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )"
+
+      Page      "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )"
+        Combo     $Int_EFP3_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List,
+        Help      "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not."
+
+        Combo     $Int_EFP3_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\n"
+                  "Level 0 (0 dB)\n"
+                  "Level 1 (3.5 dB)\n"
+                  "Level 2 (6.0 dB)\n"
+                  "Level 3 (9.5 dB)"
+
+        Combo     $Int_EFP3_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List,
+        Help      "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\n"
+                  "Swing-0 (0.4 V)\n" 
+                  "Swing-1 (0.6 V)\n"
+                  "Swing-2 (0.8 V)\n"
+        ; "Swing-3 (1.2 V)"
+
+        Title     "    "
+        Combo     $Int_EFP3_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List,
+        Help      "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n"
+
+        Combo     $Int_EFP3_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List,
+        Help      "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link."
+                  "Level 0 (0 dB)\n"
+                  "Level 1 (3.5 dB)\n"
+                  "Level 2 (6.0 dB)\n"
+                  "Level 3 (9.5 dB)"
+
+        Combo     $Int_EFP3_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List,
+        Help      "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\r\n"
+                  "Swing-0 (0.4 V)\n" 
+                  "Swing-1 (0.6 V)\n"
+                  "Swing-2 (0.8 V)\n"
+        ; "Swing-3 (1.2 V)"
+      EndPage   ; "DisplayPort Redriver Configuration"
+
+      Page      "EDID-less EFP Panel DTD Timings"
+        Link      "Close Table" , ".."
+
+        Table     $EFP3_DTD " DTD Timings Values",
+        Column    "Timings" , 1 byte , EHEX,
+        Help      "This feature allows for the definition of the DTD timings parameters. "
+                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
+                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                  "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                  "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                  "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                  "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                  "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                  "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                  "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                  "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                  "\tByte16 \t: Horizontal Border in pixels\r\n"
+                  "\tByte17 \t: Vertical Border in lines\r\n"
+                  "\tByte18 \t: Flags:\r\n"
+                  "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                  "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
+                  "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                  "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                  "\t   \t:   Bit 0:   0 = Reserved"
+      EndPage   ; "EDID-less EFP Panel DTD Timings"
+    EndPage   ; "Device 3  (EFP3)"
+
+    ;==============================================================================
+    ; Page - Device 4 (EFP4)
+    ;------------------------------------------------------------------------------
+    Page      "Device 4 (EFP4 for DDI-E only)"
+      Link      "Close Window" , ".."
+
+      Combo     $Int_EFP4_Type, "Select Device Type:", &Int_EFP4_Device_Type_List,
+      Help      "This feature specifies the Device Type for this add-in device."
+
+      Combo     $Int_EFP4_Port, "Select Output Port:", &Int_EFP4_Port_List,
+      Help      "This feature specifies which DVO port the device is configured."
+
+      Combo     $Int_EFP4_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List,
+      Help      "This feature specifies the AUX Channel for int-DisplayPort. "
+                "This field is valid only if integrated DP is selected for Device Type."
+
+      Combo     $Int_EFP4_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List,
+      Help      "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels"
+
+      Combo     $Int_EFP4_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List,
+      Help      "This field is applicable only if IBoost is enabled for the selected port."
+                "The IBoost magnitude levels supported on CFL are 0x1, 0x3, 0x7"
+
+    EndPage   ; "Device 4 (EFP4)"
+
+  EndPage   ; "Integrated DisplayPort/HDMI Configuration with External Connectors"
+EndPage   ; Display configuration
+
+;==============================================================================
+; Page - Display Device Toggle Lists
+;------------------------------------------------------------------------------
+Page      "Display Device Toggle Lists (Mobile only)"
+  Link      "Toggle/Capabilities List 1" , "Display Toggle List 1"
+  Link      "Toggle/Capabilities List 2" , "Display Toggle List 2"
+  Link      "Toggle/Capabilities List 3" , "Display Toggle List 3"
+  Link      "Toggle/Capabilities List 4" , "Display Toggle List 4"
+
+  Page      "Display Toggle List 1"
+    Link      "Close Table" , ".."
+
+    Table     $Toggle_List1 "Display Toggle List 1",
+    Column    "Display Select", 2 bytes, EHEX,
+
+    Help      "These toggle lists are used by the video BIOS and Graphics drivers "
+              "to help support the system BIOS with switch display device Hot Keys. "
+              "The basic algorithm is that the current display is found on the list and "
+              "the next settable display combination is set. "
+              "If no settable display combinations are found the function returns fail.\r\n\r\n"
+              "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n"
+              "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"
+              "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n"
+              "EFPx.x nomenclature\r\n"
+              "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n"
+              "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n"
+              "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n"
+              "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n"
+              "Examples:\r\n"
+              "\t Display Config\r\n"
+              "\t00000000 00001100b  ; Toggle display to EFP & LFP combination\r\n"
+              "\t00000100 00001000b  ; Toggle display to second DP Port on EFP3 and LFP combination."
+  EndPage   ; Display Toggle List 1
+
+  Page      "Display Toggle List 2"
+    Link      "Close Table" , ".."
+
+    Table     $Toggle_List2 "Display Toggle List 2",
+    Column    "Display Select", 2 bytes, EHEX,
+    Help      "These toggle lists are used by the video BIOS and Graphics drivers "
+              "to help support the system BIOS with switch display device Hot Keys. "
+              "The basic algorithm is that the current display is found on the list and "
+              "the next settable display combination is set. "
+              "If no settable display combinations are found the function returns fail.\r\n\r\n"
+              "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n"
+              "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"
+              "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n"
+              "EFPx.x nomenclature\r\n"
+              "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n"
+              "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n"
+              "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n"
+              "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n"
+              "Examples:\r\n"
+              "\t Display Config\r\n"
+              "\t00000000 00001100b  ; Toggle display to EFP & LFP combination\r\n"
+              "\t00000100 00001000b  ; Toggle display to second DP Port on EFP3 and LFP combination."
+  EndPage   ; Display Toggle List 2
+
+  Page      "Display Toggle List 3"
+    Link      "Close Table" , ".."
+
+    Table     $Toggle_List3 "Display Toggle List 3",
+    Column    "Display Select", 2 bytes, EHEX,
+    Help      "These toggle lists are used by the video BIOS and Graphics drivers "
+              "to help support the system BIOS with switch display device Hot Keys. "
+              "The basic algorithm is that the current display is found on the list and "
+              "the next settable display combination is set. "
+              "If no settable display combinations are found the function returns fail.\r\n\r\n"
+              "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n"
+              "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"
+              "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n"
+              "EFPx.x nomenclature\r\n"
+              "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n"
+              "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n"
+              "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n"
+              "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n"
+              "Examples:\r\n"
+              "\t Display Config\r\n"
+              "\t00000000 00001100b  ; Toggle display to EFP & LFP combination\r\n"
+              "\t00000100 00001000b  ; Toggle display to second DP Port on EFP3 and LFP combination."
+  EndPage   ; Display Toggle List 3
+
+  Page      "Display Toggle List 4"
+    Link      "Close Table" , ".."
+
+    Table     $Toggle_List4 "Display Toggle List 4",
+    Column    "Display Select", 2 bytes, EHEX,
+    Help      "These toggle lists are used by the video BIOS and Graphics drivers "
+              "to help support the system BIOS with switch display device Hot Keys. "
+              "The basic algorithm is that the current display is found on the list and "
+              "the next settable display combination is set. "
+              "If no settable display combinations are found the function returns fail.\r\n\r\n"
+              "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n"
+              "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"
+              "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n"
+              "EFPx.x nomenclature\r\n"
+              "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n"
+              "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n"
+              "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n"
+              "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n"
+              "Examples:\r\n"
+              "\t Display Config\r\n"
+              "\t00000000 00001100b  ; Toggle display to EFP & LFP combination\r\n"
+              "\t00000100 00001000b  ; Toggle display to second DP Port on EFP3 and LFP combination."
+  EndPage   ; Display Toggle List 4
+EndPage   ; Display Device Toggle Lists
+
+;==============================================================================
+; Page - Modes Removal Table
+;------------------------------------------------------------------------------
+
+Page      "Modes Removal Table"
+
+  Table     $Mode_Rem_Table "Modes Removal Table",
+  Column    "X-Resolution",     2 bytes, DEC
+  Column    "Y-Resolution",     2 bytes, DEC
+  Column    "BPP",              1 byte,  DEC
+  Column    "Refresh Rate",     2 bytes, EHEX
+  Column    "Removal Flags",    1 byte,  EHEX
+  Column    "Panel Type",       2 bytes, EHEX,
+
+  Help      "This feature allows removing support for selected modes resolutions.\r\n"
+            "X-Resolution, Y-Resolution, and BPP in Decimal or Hexadecimal (0FFFFh or 0FFh means disable all).\r\n\r\n"
+            "Refresh Rate bitmap selection (0 = Do not remove, 1 = Remove):\r\n"
+            "\tBit \t     15 \t14 \t13 \t12 \t11 \t10 \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 \r\n"
+            "\tRRate(Hz)  Rsvd \t48 \t25 \t24 \t50 \t40 \t30 \t120 \t100 \t85 \t75 \t72 \t70 \t60 \t56 \t43 \r\n\r\n"
+            "Removal Flags bitmap selection (0 = Do not remove, 1 = Remove):\r\n"
+            "\tBit        \t     7 \t  6 \t\t5 \t4 \t3 \t2 \t1 \t0 \r\n"
+            "\tComponent  Rsvd \tTV Scan Mode \tLFP \tEFP \tRsvd \tRsvd \tDriver \tRsvd \r\n\r\n"
+            "Note: \t1) In order to remove mode from both Windows and DOS, "
+            "both bits 1 and Bit 0 must be set to 1.\r\n"
+            "\t2) The defaule setting '0' for Bit6 is for removing Progressive scan mode from TV device, "
+            "and setting '1' is for removing Interlaced scan mode from TV device.\r\n\r\n"
+            "(Mobile only) Panel Type bitmap selection (0 = Do not remove, 1 = Remove if panel is active):\r\n"
+            "\tBit  \t15 14 13 12 11 10  9  8 7 6 5 4 3 2 1 0 \r\n"
+            "\tType \t16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 \r\n"
+            "Note: Default is to remove a mode resolution from all panel types."
+EndPage
+
+;==============================================================================
+; Page - Display Configuration Removal Table
+;------------------------------------------------------------------------------
+Page      "Display Configuration Removal Table (Mobile only)"
+
+  Table     $Dev_Removed_Table " Display Device Configuration Removal Table",
+  Column    "Display Configuration" , 2 bytes , EHEX,
+  Help      "This feature allows blocking selected display configurations by the driver.\r\n"
+            "Display Devices are specified in the following bit patterns:\r\n"
+            "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"
+            "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n"
+            "EFPx.x nomenclature\r\n"
+            "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n"
+            "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n"
+            "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n"
+            "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n"
+            "Examples:\r\n"
+            "\tDisplay Config\r\n"
+            "\t00000000 00001100b  ; EFP & LFP combination to be removed\r\n"
+            "\t00000100 00001000b  ; Second DP Port on EFP3 and LFP to be removed."
+EndPage
+
+;==============================================================================
+; Page - OEM Customizable Modes
+;------------------------------------------------------------------------------
+Page      "OEM Customizable Modes"
+  Link      "OEM Mode 1 Configuration", "OEM Mode #1"
+  Link      "OEM Mode 2 Configuration", "OEM Mode #2"
+  Link      "OEM Mode 3 Configuration", "OEM Mode #3"
+  Link      "OEM Mode 4 Configuration", "OEM Mode #4"
+  Link      "OEM Mode 5 Configuration", "OEM Mode #5"
+  Link      "OEM Mode 6 Configuration", "OEM Mode #6"
+
+  Page      "OEM Mode #1"
+    Link      "Close Table" , ".."
+
+    Title     "     8 bpp = VGA mode 60h / VESA mode 160h"
+    Title     "    16 bpp = VGA mode 61h / VESA mode 161h"
+    Title     "    32 bpp = VGA mode 62h / VESA mode 162h"
+
+    EditNum   $OEM_Mode_Flags1, "Support Flags:", BIN,
+    Help      "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
+              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
+              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd"
+
+    EditNum   $OEM_Display_Flags1, "Display Flags:", BIN,
+    Help      "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
+              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
+              "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd"
+
+    TitleB    "Mode Characteristics"
+    EditNum   $OEM_Mode_X1, "\tX Resolution:", DEC,
+    Help      "X Resolution in pixels (decimal)."
+
+    EditNum   $OEM_Mode_Y1, "\tY Resolution:", DEC,
+    Help      "Y Resolution in pixels (decimal)."
+
+    EditNum   $OEM_Mode_Color1, "\tColor Depth:", BIN,
+    Help      "Color Depth, bits can be set simultaneously (binary).\r\n\r\n"
+              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t  Bit 0\r\n"
+              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP"
+
+    EditNum   $OEM_Mode_RRate1, "\tRefresh Rate:", DEC,
+    Help      "Refresh rate for OEM customizable mode (decimal)."
+    Link      "18 Bytes DTD" , "DTD"
+
+    Page      "DTD"
+      Link      "Close Table" , ".."
+      Table     $OEM_Mode_DTD1 " Detailed Timings Descriptor",
+      Column    "Timings" , 1 byte , EHEX,
+      Help      "This table is the 18-byte DTD(Detailed Timings Descriptor) structure "
+                "as defined in the VESA EDID version 1.x. "
+                "This is used by VBIOS only.\r\n\r\n"
+                "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                "\tByte16 \t: Horizontal Border in pixels\r\n"
+                "\tByte17 \t: Vertical Border in lines\r\n"
+                "\tByte18 \t: Flags:\r\n"
+                "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
+                "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                "\t   \t:   Bit 0:   0 = Reserved"
+    EndPage   ; DTD
+  EndPage   ; OEM Mode #1
+
+  Page      "OEM Mode #2"
+    Link      "Close Table" , ".."
+
+    Title     "     8 bpp = VGA mode 63h / VESA mode 163h"
+    Title     "    16 bpp = VGA mode 64h / VESA mode 164h"
+    Title     "    32 bpp = VGA mode 65h / VESA mode 165h"
+
+    EditNum   $OEM_Mode_Flags2, "Support Flags:", BIN,
+    Help      "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
+              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
+              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd"
+
+    EditNum   $OEM_Display_Flags2, "Display Flags:", BIN,
+    Help      "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
+              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
+              "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd"
+
+    TitleB    "Mode Characteristics"
+
+    EditNum   $OEM_Mode_X2, "\tX Resolution:", DEC,
+    Help      "X Resolution in pixels (decimal)."
+
+    EditNum   $OEM_Mode_Y2, "\tY Resolution:", DEC,
+    Help      "Y Resolution in pixels (decimal)."
+
+    EditNum   $OEM_Mode_Color2, "\tColor Depth:", BIN,
+    Help      "Color Depth, bits can be set simultaneously (binary).\r\n\r\n"
+              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t  Bit 0\r\n"
+              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP"
+
+    EditNum   $OEM_Mode_RRate2, "\tRefresh Rate:", DEC,
+    Help      "Refresh rate for OEM customizable mode (decimal)."
+
+    Link      "18 Bytes DTD" , "DTD"
+
+    Page      "DTD"
+      Link      "Close Table" , ".."
+
+      Table     $OEM_Mode_DTD2 " Detailed Timings Descriptor",
+      Column    "Timings" , 1 byte , EHEX,
+      Help      "This table is the 18-byte DTD(Detailed Timings Descriptor) structure "
+                "as defined in the VESA EDID version 1.x. "
+                "This is used by VBIOS only.\r\n\r\n"
+                "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                "\tByte16 \t: Horizontal Border in pixels\r\n"
+                "\tByte17 \t: Vertical Border in lines\r\n"
+                "\tByte18 \t: Flags:\r\n"
+                "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
+                "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                "\t   \t:   Bit 0:   0 = Reserved"
+    EndPage   ; DTD
+  EndPage   ; OEM Mode #2
+
+  Page      "OEM Mode #3"
+    Link      "Close Table" , ".."
+
+    Title     "     8 bpp = VGA mode 66h / VESA mode 166h"
+    Title     "    16 bpp = VGA mode 67h / VESA mode 167h"
+    Title     "    32 bpp = VGA mode 68h / VESA mode 168h"
+
+    EditNum   $OEM_Mode_Flags3, "Support Flags:", BIN,
+    Help      "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
+              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
+              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd"
+
+    EditNum   $OEM_Display_Flags3, "Display Flags:", BIN,
+    Help      "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
+              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
+              "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd"
+
+    TitleB    "Mode Characteristics"
+
+    EditNum   $OEM_Mode_X3, "\tX Resolution:", DEC,
+    Help      "X Resolution in pixels (decimal)."
+
+    EditNum   $OEM_Mode_Y3, "\tY Resolution:", DEC,
+    Help      "Y Resolution in pixels (decimal)."
+
+    EditNum   $OEM_Mode_Color3, "\tColor Depth:", BIN,
+    Help      "Color Depth, bits can be set simultaneously (binary).\r\n\r\n"
+              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t  Bit 0\r\n"
+              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP"
+
+    EditNum   $OEM_Mode_RRate3, "\tRefresh Rate:", DEC,
+    Help      "Refresh rate for OEM customizable mode (decimal)."
+
+    Link      "18 Bytes DTD" , "DTD"
+
+    Page      "DTD"
+      Link      "Close Table" , ".."
+
+      Table     $OEM_Mode_DTD3 " Detailed Timings Descriptor",
+      Column    "Timings" , 1 byte , EHEX,
+      Help      "This table is the 18-byte DTD(Detailed Timings Descriptor) structure "
+                "as defined in the VESA EDID version 1.x. "
+                "This is used by VBIOS only.\r\n\r\n"
+                "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                "\tByte16 \t: Horizontal Border in pixels\r\n"
+                "\tByte17 \t: Vertical Border in lines\r\n"
+                "\tByte18 \t: Flags:\r\n"
+                "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
+                "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                "\t   \t:   Bit 0:   0 = Reserved"
+    EndPage   ; DTD
+  EndPage   ; OEM Mode #3
+
+  Page      "OEM Mode #4"
+    Link      "Close Table" , ".."
+
+    Title     "     8 bpp = VGA mode 69h / VESA mode 169h"
+    Title     "    16 bpp = VGA mode 6Ah / VESA mode 16Ah"
+    Title     "    32 bpp = VGA mode 6Bh / VESA mode 16Bh"
+
+    EditNum   $OEM_Mode_Flags4, "Support Flags:", BIN,
+    Help      "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
+              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
+              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd"
+
+    EditNum   $OEM_Display_Flags4, "Display Flags:", BIN,
+    Help      "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
+              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
+              "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd"
+
+    TitleB    "Mode Characteristics"
+
+    EditNum   $OEM_Mode_X4, "\tX Resolution:", DEC,
+    Help      "X Resolution in pixels (decimal)."
+
+    EditNum   $OEM_Mode_Y4, "\tY Resolution:", DEC,
+    Help      "Y Resolution in pixels (decimal)."
+
+    EditNum   $OEM_Mode_Color4, "\tColor Depth:", BIN,
+    Help      "Color Depth, bits can be set simultaneously (binary).\r\n\r\n"
+              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t  Bit 0\r\n"
+              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP"
+
+    EditNum   $OEM_Mode_RRate4, "\tRefresh Rate:", DEC,
+    Help      "Refresh rate for OEM customizable mode (decimal)."
+
+    Link      "18 Bytes DTD" , "DTD"
+
+    Page      "DTD"
+
+      Link      "Close Table" , ".."
+
+      Table     $OEM_Mode_DTD4 " Detailed Timings Descriptor",
+      Column    "Timings" , 1 byte , EHEX,
+      Help      "This table is the 18-byte DTD(Detailed Timings Descriptor) structure "
+                "as defined in the VESA EDID version 1.x. "
+                "This is used by VBIOS only.\r\n\r\n"
+                "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                "\tByte16 \t: Horizontal Border in pixels\r\n"
+                "\tByte17 \t: Vertical Border in lines\r\n"
+                "\tByte18 \t: Flags:\r\n"
+                "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
+                "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                "\t   \t:   Bit 0:   0 = Reserved"
+    EndPage   ; DTD
+  EndPage   ; OEM Mode #4
+
+  Page      "OEM Mode #5"
+    Link      "Close Table" , ".."
+
+    Title     "     8 bpp = VGA mode 6Ch / VESA mode 16Ch"
+    Title     "    16 bpp = VGA mode 6Dh / VESA mode 16Dh"
+    Title     "    32 bpp = VGA mode 6Eh / VESA mode 16Eh"
+
+    EditNum   $OEM_Mode_Flags5, "Support Flags:", BIN,
+    Help      "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
+              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
+              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd"
+
+    EditNum   $OEM_Display_Flags5, "Display Flags:", BIN,
+    Help      "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
+              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
+              "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd"
+
+    TitleB    "Mode Characteristics"
+
+    EditNum   $OEM_Mode_X5, "\tX Resolution:", DEC,
+    Help      "X Resolution in pixels (decimal)."
+
+    EditNum   $OEM_Mode_Y5, "\tY Resolution:", DEC,
+    Help      "Y Resolution in pixels (decimal)."
+
+    EditNum   $OEM_Mode_Color5, "\tColor Depth:", BIN,
+    Help      "Color Depth, bits can be set simultaneously (binary).\r\n\r\n"
+              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t  Bit 0\r\n"
+              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP"
+
+    EditNum   $OEM_Mode_RRate5, "\tRefresh Rate:", DEC,
+    Help      "Refresh rate for OEM customizable mode (decimal)."
+
+    Link      "18 Bytes DTD" , "DTD"
+
+    Page      "DTD"
+      Link      "Close Table" , ".."
+
+      Table     $OEM_Mode_DTD5 " Detailed Timings Descriptor",
+      Column    "Timings" , 1 byte , EHEX,
+      Help      "This table is the 18-byte DTD(Detailed Timings Descriptor) structure "
+                "as defined in the VESA EDID version 1.x. "
+                "This is used by VBIOS only.\r\n\r\n"
+                "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                "\tByte16 \t: Horizontal Border in pixels\r\n"
+                "\tByte17 \t: Vertical Border in lines\r\n"
+                "\tByte18 \t: Flags:\r\n"
+                "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
+                "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                "\t   \t:   Bit 0:   0 = Reserved"
+    EndPage   ; DTD
+  EndPage   ; OEM Mode #5
+
+  Page      "OEM Mode #6"
+    Link      "Close Table" , ".."
+
+    Title     "     8 bpp = VGA mode 6Fh / VESA mode 16Fh"
+    Title     "    16 bpp = VGA mode 70h / VESA mode 170h"
+    Title     "    32 bpp = VGA mode 71h / VESA mode 171h"
+
+    EditNum   $OEM_Mode_Flags6, "Support Flags:", BIN,
+    Help      "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
+              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
+              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tGOP\tDriver\tRsvd"
+
+    EditNum   $OEM_Display_Flags6, "Display Flags:", BIN,
+    Help      "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
+              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
+              "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd"
+
+    TitleB    "Mode Characteristics"
+
+    EditNum   $OEM_Mode_X6, "\tX Resolution:", DEC,
+    Help      "X Resolution in pixels (decimal)."
+
+    EditNum   $OEM_Mode_Y6, "\tY Resolution:", DEC,
+    Help      "Y Resolution in pixels (decimal)."
+
+    EditNum   $OEM_Mode_Color6, "\tColor Depth:", BIN,
+    Help      "Color Depth, bits can be set simultaneously (binary).\r\n\r\n"
+              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t  Bit 0\r\n"
+              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP"
+
+    EditNum   $OEM_Mode_RRate6, "\tRefresh Rate:", DEC,
+    Help      "Refresh rate for OEM customizable mode (decimal)."
+
+    Link      "18 Bytes DTD" , "DTD"
+
+    Page      "DTD"
+      Link      "Close Table" , ".."
+
+      Table     $OEM_Mode_DTD6 " Detailed Timings Descriptor",
+      Column    "Timings" , 1 byte , EHEX,
+      Help      "This table is the 18-byte DTD(Detailed Timings Descriptor) structure "
+                "as defined in the VESA EDID version 1.x. "
+                "This is used by VBIOS only.\r\n\r\n"
+                "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
+                "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
+                "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
+                "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
+                "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
+                "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
+                "\tByte6 \t: Vertical Active in lines, LSB\r\n"
+                "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
+                "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
+                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
+                "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
+                "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
+                "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
+                "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
+                "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
+                "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
+                "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
+                "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
+                "\tByte13 \t: Horizontal Image Size, LSB\r\n"
+                "\tByte14 \t: Vertical Image Size, LSB\r\n"
+                "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
+                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
+                "\tByte16 \t: Horizontal Border in pixels\r\n"
+                "\tByte17 \t: Vertical Border in lines\r\n"
+                "\tByte18 \t: Flags:\r\n"
+                "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
+                "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
+                "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
+                "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
+                "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
+                "\t   \t:   Bit 0:   0 = Reserved"
+    EndPage   ; DTD
+  EndPage   ; OEM Mode #6
+EndPage   ; OEM Customizable Modes
+;============================================================================
+; End of File
+;----------------------------------------------------------------------------
author	Nate DeSimone <nathaniel.l.desimone@intel.com>	2020-04-24 11:50:18 +0300
committer	Nate DeSimone <nathaniel.l.desimone@intel.com>	2020-04-24 12:54:06 +0300
commit	5453e67a504dc6c2e682b0c20f10af0335f11049 (patch)
tree	009e15f374cccf8160976d8ecf7b22b40b790307
parent	5eccfa02a433e2c365d532be42d782d6bb41b427 (diff)
download	FSP-5453e67a504dc6c2e682b0c20f10af0335f11049.tar.xz