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<title>Tianocore/FSP.git, branch master</title>
<subtitle>Intel(R) Firmware Support Package (FSP) (mirror)</subtitle>
<id>https://git.radix-linux.su/Tianocore/FSP.git/atom?h=master</id>
<link rel='self' href='https://git.radix-linux.su/Tianocore/FSP.git/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/FSP.git/'/>
<updated>2026-09-04T08:34:08+00:00</updated>
<entry>
<title>Edge Platforms PTL-H MR1 (4260_57) FSP ver 2.11.E026.3230</title>
<updated>2026-09-04T08:34:08+00:00</updated>
<author>
<name>Wong, Swee Heng</name>
<email>swee.heng.wong@intel.com</email>
</author>
<published>2026-09-04T08:34:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/FSP.git/commit/?id=e5a1f82272484435852f916f31e27769d1ee3caa'/>
<id>urn:sha1:e5a1f82272484435852f916f31e27769d1ee3caa</id>
<content type='text'>
Include file clean up.
</content>
</entry>
<entry>
<title>Merge branch 'master' of https://github.com/intel/FSP</title>
<updated>2026-09-04T08:11:45+00:00</updated>
<author>
<name>Wong, Swee Heng</name>
<email>swee.heng.wong@intel.com</email>
</author>
<published>2026-09-04T08:11:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/FSP.git/commit/?id=0823023f6566ca052be5ce22b93a78f12398c01b'/>
<id>urn:sha1:0823023f6566ca052be5ce22b93a78f12398c01b</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Edge Platforms PTL-H MR1 (4260_57) FSP ver 2.11.E026.3230</title>
<updated>2026-09-04T08:11:38+00:00</updated>
<author>
<name>Wong, Swee Heng</name>
<email>swee.heng.wong@intel.com</email>
</author>
<published>2026-09-04T08:11:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/FSP.git/commit/?id=81e52d1998c242fef8aa08a5c33c82a451029a86'/>
<id>urn:sha1:81e52d1998c242fef8aa08a5c33c82a451029a86</id>
<content type='text'>
FSP updated for BIOS v4260_57
</content>
</entry>
<entry>
<title>	 This FSP is aligned to BIOS ID 3038.P28 PLR6 release.</title>
<updated>2026-08-26T08:18:05+00:00</updated>
<author>
<name>Sarvenisha Jaya Kumar</name>
<email>sarvenisha.jayakumar@intel.com</email>
</author>
<published>2026-08-26T08:18:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/FSP.git/commit/?id=5a2795469c47874ed956524b749d5666018d67cc'/>
<id>urn:sha1:5a2795469c47874ed956524b749d5666018d67cc</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Edge Platforms RPL-S IPU2026.4 (7117_51) FSP ver 0C.E1.03.20</title>
<updated>2026-08-03T06:32:56+00:00</updated>
<author>
<name>Andrew S</name>
<email>andrew.sak@intel.com</email>
</author>
<published>2026-08-03T06:32:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/FSP.git/commit/?id=3e040dce33c2e188b28f894adcc20d3a83b33ac7'/>
<id>urn:sha1:3e040dce33c2e188b28f894adcc20d3a83b33ac7</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Edge Platforms RPL-PS IPU2026.4 (7117_51) FSP ver 0C.E1.03.20</title>
<updated>2026-08-03T06:29:14+00:00</updated>
<author>
<name>Andrew S</name>
<email>andrew.sak@intel.com</email>
</author>
<published>2026-08-03T06:29:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/FSP.git/commit/?id=6c7d41905e82637ecdbee1a1ac4c1c2afdc5568d'/>
<id>urn:sha1:6c7d41905e82637ecdbee1a1ac4c1c2afdc5568d</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Edge Platforms RPL-P IPU2026.4 (7117_51) FSP ver 0C.E1.03.20</title>
<updated>2026-08-03T06:25:50+00:00</updated>
<author>
<name>Andrew S</name>
<email>andrew.sak@intel.com</email>
</author>
<published>2026-08-03T06:25:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/FSP.git/commit/?id=e57c5412117a303537ed4d67fffda13a157e49fe'/>
<id>urn:sha1:e57c5412117a303537ed4d67fffda13a157e49fe</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Edge Platforms PTL-H PV2 (4063_65) FSP ver 2.11.E026.1930</title>
<updated>2026-07-17T06:41:51+00:00</updated>
<author>
<name>swong23</name>
<email>swee.heng.wong@intel.com</email>
</author>
<published>2026-07-17T06:41:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/FSP.git/commit/?id=c22c01cf871af3e62ebb0dadf9892fafd04ac6d4'/>
<id>urn:sha1:c22c01cf871af3e62ebb0dadf9892fafd04ac6d4</id>
<content type='text'>
Addressed Issue#: 130</content>
</entry>
<entry>
<title>Merge branch 'master' of https://github.com/intel/FSP</title>
<updated>2026-06-29T09:09:51+00:00</updated>
<author>
<name>Swee Ching Lim</name>
<email>swee.ching.lim@intel.com</email>
</author>
<published>2026-06-29T09:09:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/FSP.git/commit/?id=7cb9638a8d2233017fcc37e446bc8656bb27e92e'/>
<id>urn:sha1:7cb9638a8d2233017fcc37e446bc8656bb27e92e</id>
<content type='text'>
</content>
</entry>
<entry>
<title>IPU2026.3 - New FSP UPDs for NTB Support.</title>
<updated>2026-06-29T09:09:47+00:00</updated>
<author>
<name>Swee Ching Lim</name>
<email>swee.ching.lim@intel.com</email>
</author>
<published>2026-06-29T09:09:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/FSP.git/commit/?id=bd3496339f0e8629937b84d9cd2deec5284000a6'/>
<id>urn:sha1:bd3496339f0e8629937b84d9cd2deec5284000a6</id>
<content type='text'>
Minor correct on 915064_Intel_Xeon_D1700_FSP_IG_Rev004.pdf.
</content>
</entry>
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