1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
|
[
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts every core cycle when a Data-side (walks due to a data operation) page walk is in progress.",
"EventCode": "0x05",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "PAGE_WALKS.D_SIDE_CYCLES",
"SampleAfterValue": "200003",
"BriefDescription": "Duration of D-side page-walks in cycles"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts every core cycle when a Instruction-side (walks due to an instruction fetch) page walk is in progress.",
"EventCode": "0x05",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "PAGE_WALKS.I_SIDE_CYCLES",
"SampleAfterValue": "200003",
"BriefDescription": "Duration of I-side pagewalks in cycles"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts every core cycle a page-walk is in progress due to either a data memory operation or an instruction fetch.",
"EventCode": "0x05",
"Counter": "0,1,2,3",
"UMask": "0x3",
"EventName": "PAGE_WALKS.CYCLES",
"SampleAfterValue": "200003",
"BriefDescription": "Duration of page-walks in cycles"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch. It counts when new translation are filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.",
"EventCode": "0x81",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "ITLB.MISS",
"SampleAfterValue": "200003",
"BriefDescription": "ITLB misses"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts load uops retired that caused a DTLB miss.",
"EventCode": "0xD0",
"Counter": "0,1,2,3",
"UMask": "0x11",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
"SampleAfterValue": "200003",
"BriefDescription": "Load uops retired that missed the DTLB (Precise event capable)",
"Data_LA": "1"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts store uops retired that caused a DTLB miss.",
"EventCode": "0xD0",
"Counter": "0,1,2,3",
"UMask": "0x12",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES",
"SampleAfterValue": "200003",
"BriefDescription": "Store uops retired that missed the DTLB (Precise event capable)",
"Data_LA": "1"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts uops retired that had a DTLB miss on load, store or either. Note that when two distinct memory operations to the same page miss the DTLB, only one of them will be recorded as a DTLB miss.",
"EventCode": "0xD0",
"Counter": "0,1,2,3",
"UMask": "0x13",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS",
"SampleAfterValue": "200003",
"BriefDescription": "Memory uops retired that missed the DTLB (Precise event capable)",
"Data_LA": "1"
}
]
|
