1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*/
/dts-v1/;
#include "sparx5_pcb_common.dtsi"
/ {
model = "Sparx5 PCB125 Reference Board";
compatible = "microchip,sparx5-pcb125", "microchip,sparx5";
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x10000000>;
};
};
&gpio {
emmc_pins: emmc-pins {
/* NB: No "GPIO_35", "GPIO_36", "GPIO_37"
* (N/A: CARD_nDETECT, CARD_WP, CARD_LED)
*/
pins = "GPIO_34", "GPIO_38", "GPIO_39",
"GPIO_40", "GPIO_41", "GPIO_42",
"GPIO_43", "GPIO_44", "GPIO_45",
"GPIO_46", "GPIO_47";
drive-strength = <3>;
function = "emmc";
};
};
&sdhci0 {
status = "okay";
bus-width = <8>;
non-removable;
pinctrl-0 = <&emmc_pins>;
max-frequency = <8000000>;
microchip,clock-delay = <10>;
};
&spi0 {
status = "okay";
spi@0 {
compatible = "spi-mux";
mux-controls = <&mux>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0>; /* CS0 */
spi-flash@9 {
compatible = "jedec,spi-nor";
spi-max-frequency = <8000000>;
reg = <0x9>; /* SPI */
};
};
spi@1 {
compatible = "spi-mux";
mux-controls = <&mux 0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <1>; /* CS1 */
spi-flash@9 {
compatible = "spi-nand";
pinctrl-0 = <&cs1_pins>;
pinctrl-names = "default";
spi-max-frequency = <8000000>;
reg = <0x9>; /* SPI */
};
};
};
&i2c1 {
status = "okay";
};
|
