/* * MPC8548 CDS Device Tree Source * * Copyright 2006, 2008 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ /include/ "fsl/mpc8548si-pre.dtsi" / { model = "MPC8548CDS"; compatible = "MPC8548CDS", "MPC85xxCDS"; aliases { ethernet0 = &enet0; ethernet1 = &enet1; ethernet2 = &enet2; ethernet3 = &enet3; serial0 = &serial0; serial1 = &serial1; pci0 = &pci0; pci1 = &pci1; pci2 = &pci2; }; memory { device_type = "memory"; reg = <0 0 0x0 0x8000000>; // 128M at 0x0 }; lbc: localbus@e0005000 { reg = <0 0xe0005000 0 0x1000>; }; soc: soc8548@e0000000 { ranges = <0 0x0 0xe0000000 0x100000>; i2c@3000 { eeprom@50 { compatible = "atmel,24c64"; reg = <0x50>; }; eeprom@56 { compatible = "atmel,24c64"; reg = <0x56>; }; eeprom@57 { compatible = "atmel,24c64"; reg = <0x57>; }; }; i2c@3100 { eeprom@50 { compatible = "atmel,24c64"; reg = <0x50>; }; }; enet0: ethernet@24000 { tbi-handle = <&tbi0>; phy-handle = <&phy0>; }; mdio@24520 { phy0: ethernet-phy@0 { interrupts = <5 1 0 0>; reg = <0x0>; device_type = "ethernet-phy"; }; phy1: ethernet-phy@1 { interrupts = <5 1 0 0>; reg = <0x1>; device_type = "ethernet-phy"; }; phy2: ethernet-phy@2 { interrupts = <5 1 0 0>; reg = <0x2>; device_type = "ethernet-phy"; }; phy3: ethernet-phy@3 { interrupts = <5 1 0 0>; reg = <0x3>; device_type = "ethernet-phy"; }; tbi0: tbi-phy@11 { reg = <0x11>; device_type = "tbi-phy"; }; }; enet1: ethernet@25000 { tbi-handle = <&tbi1>; phy-handle = <&phy1>; }; mdio@25520 { tbi1: tbi-phy@11 { reg = <0x11>; device_type = "tbi-phy"; }; }; enet2: ethernet@26000 { tbi-handle = <&tbi2>; phy-handle = <&phy2>; }; mdio@26520 { tbi2: tbi-phy@11 { reg = <0x11>; device_type = "tbi-phy"; }; }; enet3: ethernet@27000 { tbi-handle = <&tbi3>; phy-handle = <&phy3>; }; mdio@27520 { tbi3: tbi-phy@11 { reg = <0x11>; device_type = "tbi-phy"; }; }; }; pci0: pci@e0008000 { reg = <0 0xe0008000 0 0x1000>; ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000 0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>; clock-frequency = <66666666>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x4 (PCIX Slot 2) */ 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 /* IDSEL 0x5 (PCIX Slot 3) */ 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0 /* IDSEL 0x6 (PCIX Slot 4) */ 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 /* IDSEL 0x8 (PCIX Slot 5) */ 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 /* IDSEL 0xC (Tsi310 bridge) */ 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 /* IDSEL 0x14 (Slot 2) */ 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 /* IDSEL 0x15 (Slot 3) */ 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0 /* IDSEL 0x16 (Slot 4) */ 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 /* IDSEL 0x18 (Slot 5) */ 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */ 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>; pci_bridge@1c { interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x00 (PrPMC Site) */ 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 /* IDSEL 0x04 (VIA chip) */ 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 /* IDSEL 0x05 (8139) */ 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0 /* IDSEL 0x06 (Slot 6) */ 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 /* IDESL 0x07 (Slot 7) */ 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>; reg = <0xe000 0x0 0x0 0x0 0x0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; ranges = <0x2000000 0x0 0x80000000 0x2000000 0x0 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0x1000000 0x0 0x0 0x0 0x80000>; clock-frequency = <33333333>; isa@4 { device_type = "isa"; #interrupt-cells = <2>; #size-cells = <1>; #address-cells = <2>; reg = <0x2000 0x0 0x0 0x0 0x0>; ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>; interrupt-parent = <&i8259>; i8259: interrupt-controller@20 { interrupt-controller; device_type = "interrupt-controller"; reg = <0x1 0x20 0x2 0x1 0xa0 0x2 0x1 0x4d0 0x2>; #address-cells = <0>; #interrupt-cells = <2>; compatible = "chrp,iic"; interrupts = <0 1 0 0>; interrupt-parent = <&mpic>; }; rtc@70 { compatible = "pnpPNP,b00"; reg = <0x1 0x70 0x2>; }; }; }; }; pci1: pci@e0009000 { reg = <0 0xe0009000 0 0x1000>; ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>; clock-frequency = <66666666>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x15 */ 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>; }; pci2: pcie@e000a000 { reg = <0 0xe000a000 0 0x1000>; ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>; pcie@0 { ranges = <0x2000000 0x0 0xa0000000 0x2000000 0x0 0xa0000000 0x0 0x20000000 0x1000000 0x0 0x0 0x1000000 0x0 0x0 0x0 0x100000>; }; }; }; /include/ "fsl/mpc8548si-post.dtsi"