From dd2b5959785c75c23ab2295a4095700e47dabff3 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Thu, 27 Jun 2019 10:12:06 +0200 Subject: drm/bochs: fix framebuffer setup. The driver doesn't consider framebuffer pitch and offset, leading to a wrong display in case offset != 0 or pitch != width * bpp. Fix it. Signed-off-by: Gerd Hoffmann Reviewed-by: Daniel Vetter Acked-by: Thomas Zimmermann Link: http://patchwork.freedesktop.org/patch/msgid/20190627081206.23135-1-kraxel@redhat.com --- drivers/gpu/drm/bochs/bochs.h | 2 +- drivers/gpu/drm/bochs/bochs_hw.c | 14 ++++++++++---- drivers/gpu/drm/bochs/bochs_kms.c | 3 ++- 3 files changed, 13 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/bochs/bochs.h b/drivers/gpu/drm/bochs/bochs.h index cc35d492142c..2a65434500ee 100644 --- a/drivers/gpu/drm/bochs/bochs.h +++ b/drivers/gpu/drm/bochs/bochs.h @@ -86,7 +86,7 @@ void bochs_hw_setmode(struct bochs_device *bochs, void bochs_hw_setformat(struct bochs_device *bochs, const struct drm_format_info *format); void bochs_hw_setbase(struct bochs_device *bochs, - int x, int y, u64 addr); + int x, int y, int stride, u64 addr); int bochs_hw_load_edid(struct bochs_device *bochs); /* bochs_mm.c */ diff --git a/drivers/gpu/drm/bochs/bochs_hw.c b/drivers/gpu/drm/bochs/bochs_hw.c index 791ab2f79947..ebfea8744fe6 100644 --- a/drivers/gpu/drm/bochs/bochs_hw.c +++ b/drivers/gpu/drm/bochs/bochs_hw.c @@ -255,16 +255,22 @@ void bochs_hw_setformat(struct bochs_device *bochs, } void bochs_hw_setbase(struct bochs_device *bochs, - int x, int y, u64 addr) + int x, int y, int stride, u64 addr) { - unsigned long offset = (unsigned long)addr + + unsigned long offset; + unsigned int vx, vy, vwidth; + + bochs->stride = stride; + offset = (unsigned long)addr + y * bochs->stride + x * (bochs->bpp / 8); - int vy = offset / bochs->stride; - int vx = (offset % bochs->stride) * 8 / bochs->bpp; + vy = offset / bochs->stride; + vx = (offset % bochs->stride) * 8 / bochs->bpp; + vwidth = stride * 8 / bochs->bpp; DRM_DEBUG_DRIVER("x %d, y %d, addr %llx -> offset %lx, vx %d, vy %d\n", x, y, addr, offset, vx, vy); + bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH, vwidth); bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, vx); bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, vy); } diff --git a/drivers/gpu/drm/bochs/bochs_kms.c b/drivers/gpu/drm/bochs/bochs_kms.c index 5904eddc83a5..bc19dbd531ef 100644 --- a/drivers/gpu/drm/bochs/bochs_kms.c +++ b/drivers/gpu/drm/bochs/bochs_kms.c @@ -36,7 +36,8 @@ static void bochs_plane_update(struct bochs_device *bochs, bochs_hw_setbase(bochs, state->crtc_x, state->crtc_y, - gbo->bo.offset); + state->fb->pitches[0], + state->fb->offsets[0] + gbo->bo.offset); bochs_hw_setformat(bochs, state->fb->format); } -- cgit v1.2.3 From c0898fca3fce00f824e7f5d48e1edd0900378a03 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 28 Jun 2019 14:16:45 +0200 Subject: drm/selftests: reduce stack usage Putting a large drm_connector object on the stack can lead to warnings in some configuration, such as: drivers/gpu/drm/selftests/test-drm_cmdline_parser.c:18:12: error: stack frame size of 1040 bytes in function 'drm_cmdline_test_res' [-Werror,-Wframe-larger-than=] static int drm_cmdline_test_res(void *ignored) Since the object is never modified, just declare it as 'static const' and allow this to be passed down. Fixes: b7ced38916a9 ("drm/selftests: Add command line parser selftests") Signed-off-by: Arnd Bergmann Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20190628121712.1928142-1-arnd@arndb.de --- drivers/gpu/drm/drm_modes.c | 8 +- .../gpu/drm/selftests/test-drm_cmdline_parser.c | 136 ++++++++------------- include/drm/drm_modes.h | 2 +- 3 files changed, 53 insertions(+), 93 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c index 57e6408288c8..910561d4f071 100644 --- a/drivers/gpu/drm/drm_modes.c +++ b/drivers/gpu/drm/drm_modes.c @@ -1448,7 +1448,7 @@ static int drm_mode_parse_cmdline_refresh(const char *str, char **end_ptr, } static int drm_mode_parse_cmdline_extra(const char *str, int length, - struct drm_connector *connector, + const struct drm_connector *connector, struct drm_cmdline_mode *mode) { int i; @@ -1493,7 +1493,7 @@ static int drm_mode_parse_cmdline_extra(const char *str, int length, static int drm_mode_parse_cmdline_res_mode(const char *str, unsigned int length, bool extras, - struct drm_connector *connector, + const struct drm_connector *connector, struct drm_cmdline_mode *mode) { const char *str_start = str; @@ -1555,7 +1555,7 @@ static int drm_mode_parse_cmdline_res_mode(const char *str, unsigned int length, } static int drm_mode_parse_cmdline_options(char *str, size_t len, - struct drm_connector *connector, + const struct drm_connector *connector, struct drm_cmdline_mode *mode) { unsigned int rotation = 0; @@ -1689,7 +1689,7 @@ static int drm_mode_parse_cmdline_options(char *str, size_t len, * True if a valid modeline has been parsed, false otherwise. */ bool drm_mode_parse_command_line_for_connector(const char *mode_option, - struct drm_connector *connector, + const struct drm_connector *connector, struct drm_cmdline_mode *mode) { const char *name; diff --git a/drivers/gpu/drm/selftests/test-drm_cmdline_parser.c b/drivers/gpu/drm/selftests/test-drm_cmdline_parser.c index bef4edde6f9f..14c96edb13df 100644 --- a/drivers/gpu/drm/selftests/test-drm_cmdline_parser.c +++ b/drivers/gpu/drm/selftests/test-drm_cmdline_parser.c @@ -15,13 +15,14 @@ #include "drm_selftest.h" #include "test-drm_modeset_common.h" +static const struct drm_connector no_connector = {}; + static int drm_cmdline_test_res(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -42,11 +43,10 @@ static int drm_cmdline_test_res(void *ignored) static int drm_cmdline_test_res_missing_x(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(drm_mode_parse_command_line_for_connector("x480", - &connector, + &no_connector, &mode)); return 0; @@ -54,11 +54,10 @@ static int drm_cmdline_test_res_missing_x(void *ignored) static int drm_cmdline_test_res_missing_y(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(drm_mode_parse_command_line_for_connector("1024x", - &connector, + &no_connector, &mode)); return 0; @@ -66,11 +65,10 @@ static int drm_cmdline_test_res_missing_y(void *ignored) static int drm_cmdline_test_res_bad_y(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(drm_mode_parse_command_line_for_connector("1024xtest", - &connector, + &no_connector, &mode)); return 0; @@ -78,11 +76,10 @@ static int drm_cmdline_test_res_bad_y(void *ignored) static int drm_cmdline_test_res_missing_y_bpp(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(drm_mode_parse_command_line_for_connector("1024x-24", - &connector, + &no_connector, &mode)); return 0; @@ -90,11 +87,10 @@ static int drm_cmdline_test_res_missing_y_bpp(void *ignored) static int drm_cmdline_test_res_vesa(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480M", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -115,11 +111,10 @@ static int drm_cmdline_test_res_vesa(void *ignored) static int drm_cmdline_test_res_vesa_rblank(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480MR", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -140,11 +135,10 @@ static int drm_cmdline_test_res_vesa_rblank(void *ignored) static int drm_cmdline_test_res_rblank(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480R", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -165,11 +159,10 @@ static int drm_cmdline_test_res_rblank(void *ignored) static int drm_cmdline_test_res_bpp(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480-24", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -191,11 +184,10 @@ static int drm_cmdline_test_res_bpp(void *ignored) static int drm_cmdline_test_res_bad_bpp(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(drm_mode_parse_command_line_for_connector("720x480-test", - &connector, + &no_connector, &mode)); return 0; @@ -203,11 +195,10 @@ static int drm_cmdline_test_res_bad_bpp(void *ignored) static int drm_cmdline_test_res_refresh(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480@60", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -229,11 +220,10 @@ static int drm_cmdline_test_res_refresh(void *ignored) static int drm_cmdline_test_res_bad_refresh(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(drm_mode_parse_command_line_for_connector("720x480@refresh", - &connector, + &no_connector, &mode)); return 0; @@ -241,11 +231,10 @@ static int drm_cmdline_test_res_bad_refresh(void *ignored) static int drm_cmdline_test_res_bpp_refresh(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480-24@60", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -268,11 +257,10 @@ static int drm_cmdline_test_res_bpp_refresh(void *ignored) static int drm_cmdline_test_res_bpp_refresh_interlaced(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480-24@60i", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -295,11 +283,10 @@ static int drm_cmdline_test_res_bpp_refresh_interlaced(void *ignored) static int drm_cmdline_test_res_bpp_refresh_margins(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480-24@60m", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -322,11 +309,10 @@ static int drm_cmdline_test_res_bpp_refresh_margins(void *ignored) static int drm_cmdline_test_res_bpp_refresh_force_off(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480-24@60d", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -349,11 +335,10 @@ static int drm_cmdline_test_res_bpp_refresh_force_off(void *ignored) static int drm_cmdline_test_res_bpp_refresh_force_on_off(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(drm_mode_parse_command_line_for_connector("720x480-24@60de", - &connector, + &no_connector, &mode)); return 0; @@ -361,11 +346,10 @@ static int drm_cmdline_test_res_bpp_refresh_force_on_off(void *ignored) static int drm_cmdline_test_res_bpp_refresh_force_on(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480-24@60e", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -388,11 +372,10 @@ static int drm_cmdline_test_res_bpp_refresh_force_on(void *ignored) static int drm_cmdline_test_res_bpp_refresh_force_on_analog(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480-24@60D", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -415,10 +398,11 @@ static int drm_cmdline_test_res_bpp_refresh_force_on_analog(void *ignored) static int drm_cmdline_test_res_bpp_refresh_force_on_digital(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; + static const struct drm_connector connector = { + .connector_type = DRM_MODE_CONNECTOR_DVII, + }; - connector.connector_type = DRM_MODE_CONNECTOR_DVII; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480-24@60D", &connector, &mode)); @@ -443,11 +427,10 @@ static int drm_cmdline_test_res_bpp_refresh_force_on_digital(void *ignored) static int drm_cmdline_test_res_bpp_refresh_interlaced_margins_force_on(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480-24@60ime", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -470,11 +453,10 @@ static int drm_cmdline_test_res_bpp_refresh_interlaced_margins_force_on(void *ig static int drm_cmdline_test_res_margins_force_on(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480me", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -495,11 +477,10 @@ static int drm_cmdline_test_res_margins_force_on(void *ignored) static int drm_cmdline_test_res_vesa_margins(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480Mm", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -520,11 +501,10 @@ static int drm_cmdline_test_res_vesa_margins(void *ignored) static int drm_cmdline_test_res_invalid_mode(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(drm_mode_parse_command_line_for_connector("720x480f", - &connector, + &no_connector, &mode)); return 0; @@ -532,11 +512,10 @@ static int drm_cmdline_test_res_invalid_mode(void *ignored) static int drm_cmdline_test_res_bpp_wrong_place_mode(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(drm_mode_parse_command_line_for_connector("720x480e-24", - &connector, + &no_connector, &mode)); return 0; @@ -544,11 +523,10 @@ static int drm_cmdline_test_res_bpp_wrong_place_mode(void *ignored) static int drm_cmdline_test_name(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("NTSC", - &connector, + &no_connector, &mode)); FAIL_ON(strcmp(mode.name, "NTSC")); FAIL_ON(mode.refresh_specified); @@ -559,11 +537,10 @@ static int drm_cmdline_test_name(void *ignored) static int drm_cmdline_test_name_bpp(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("NTSC-24", - &connector, + &no_connector, &mode)); FAIL_ON(strcmp(mode.name, "NTSC")); @@ -577,11 +554,10 @@ static int drm_cmdline_test_name_bpp(void *ignored) static int drm_cmdline_test_name_bpp_refresh(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(drm_mode_parse_command_line_for_connector("NTSC-24@60", - &connector, + &no_connector, &mode)); return 0; @@ -589,11 +565,10 @@ static int drm_cmdline_test_name_bpp_refresh(void *ignored) static int drm_cmdline_test_name_refresh(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(drm_mode_parse_command_line_for_connector("NTSC@60", - &connector, + &no_connector, &mode)); return 0; @@ -601,11 +576,10 @@ static int drm_cmdline_test_name_refresh(void *ignored) static int drm_cmdline_test_name_refresh_wrong_mode(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(drm_mode_parse_command_line_for_connector("NTSC@60m", - &connector, + &no_connector, &mode)); return 0; @@ -613,11 +587,10 @@ static int drm_cmdline_test_name_refresh_wrong_mode(void *ignored) static int drm_cmdline_test_name_refresh_invalid_mode(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(drm_mode_parse_command_line_for_connector("NTSC@60f", - &connector, + &no_connector, &mode)); return 0; @@ -625,11 +598,10 @@ static int drm_cmdline_test_name_refresh_invalid_mode(void *ignored) static int drm_cmdline_test_name_option(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("NTSC,rotate=180", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(strcmp(mode.name, "NTSC")); @@ -640,11 +612,10 @@ static int drm_cmdline_test_name_option(void *ignored) static int drm_cmdline_test_name_bpp_option(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("NTSC-24,rotate=180", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(strcmp(mode.name, "NTSC")); @@ -657,11 +628,10 @@ static int drm_cmdline_test_name_bpp_option(void *ignored) static int drm_cmdline_test_rotate_0(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480,rotate=0", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -683,11 +653,10 @@ static int drm_cmdline_test_rotate_0(void *ignored) static int drm_cmdline_test_rotate_90(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480,rotate=90", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -709,11 +678,10 @@ static int drm_cmdline_test_rotate_90(void *ignored) static int drm_cmdline_test_rotate_180(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480,rotate=180", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -735,11 +703,10 @@ static int drm_cmdline_test_rotate_180(void *ignored) static int drm_cmdline_test_rotate_270(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480,rotate=270", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -761,11 +728,10 @@ static int drm_cmdline_test_rotate_270(void *ignored) static int drm_cmdline_test_rotate_invalid_val(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(drm_mode_parse_command_line_for_connector("720x480,rotate=42", - &connector, + &no_connector, &mode)); return 0; @@ -773,11 +739,10 @@ static int drm_cmdline_test_rotate_invalid_val(void *ignored) static int drm_cmdline_test_rotate_truncated(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(drm_mode_parse_command_line_for_connector("720x480,rotate=", - &connector, + &no_connector, &mode)); return 0; @@ -785,11 +750,10 @@ static int drm_cmdline_test_rotate_truncated(void *ignored) static int drm_cmdline_test_hmirror(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480,reflect_x", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -811,11 +775,10 @@ static int drm_cmdline_test_hmirror(void *ignored) static int drm_cmdline_test_vmirror(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480,reflect_y", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -837,11 +800,10 @@ static int drm_cmdline_test_vmirror(void *ignored) static int drm_cmdline_test_margin_options(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480,margin_right=14,margin_left=24,margin_bottom=36,margin_top=42", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -866,11 +828,10 @@ static int drm_cmdline_test_margin_options(void *ignored) static int drm_cmdline_test_multiple_options(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(!drm_mode_parse_command_line_for_connector("720x480,rotate=270,reflect_x", - &connector, + &no_connector, &mode)); FAIL_ON(!mode.specified); FAIL_ON(mode.xres != 720); @@ -892,11 +853,10 @@ static int drm_cmdline_test_multiple_options(void *ignored) static int drm_cmdline_test_invalid_option(void *ignored) { - struct drm_connector connector = { }; struct drm_cmdline_mode mode = { }; FAIL_ON(drm_mode_parse_command_line_for_connector("720x480,test=42", - &connector, + &no_connector, &mode)); return 0; diff --git a/include/drm/drm_modes.h b/include/drm/drm_modes.h index 083f16747369..e946e20c61d8 100644 --- a/include/drm/drm_modes.h +++ b/include/drm/drm_modes.h @@ -537,7 +537,7 @@ void drm_connector_list_update(struct drm_connector *connector); /* parsing cmdline modes */ bool drm_mode_parse_command_line_for_connector(const char *mode_option, - struct drm_connector *connector, + const struct drm_connector *connector, struct drm_cmdline_mode *mode); struct drm_display_mode * drm_mode_create_from_cmdline_mode(struct drm_device *dev, -- cgit v1.2.3 From dae1ccee012ea7514af8e4a88429844157aca7dc Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 24 Jun 2019 17:40:14 +0200 Subject: drm: panel-orientation-quirks: Add extra quirk table entry for GPD MicroPC Newer GPD MicroPC BIOS versions have proper DMI strings, add an extra quirk table entry for these new strings. This is good news, as this means that we no longer have to update the BIOS dates list with every BIOS update. Fixes: 652b8b086538("drm: panel-orientation-quirks: Add quirk for GPD MicroPC") Acked-by: Maxime Ripard Signed-off-by: Hans de Goede Link: https://patchwork.freedesktop.org/patch/msgid/20190624154014.8557-2-hdegoede@redhat.com --- drivers/gpu/drm/drm_panel_orientation_quirks.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c b/drivers/gpu/drm/drm_panel_orientation_quirks.c index d8a0bcd02f34..ffd95bfeaa94 100644 --- a/drivers/gpu/drm/drm_panel_orientation_quirks.c +++ b/drivers/gpu/drm/drm_panel_orientation_quirks.c @@ -90,6 +90,12 @@ static const struct drm_dmi_panel_orientation_data itworks_tw891 = { .orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP, }; +static const struct drm_dmi_panel_orientation_data lcd720x1280_rightside_up = { + .width = 720, + .height = 1280, + .orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP, +}; + static const struct drm_dmi_panel_orientation_data lcd800x1280_rightside_up = { .width = 800, .height = 1280, @@ -123,6 +129,12 @@ static const struct dmi_system_id orientation_data[] = { DMI_EXACT_MATCH(DMI_BOARD_NAME, "Default string"), }, .driver_data = (void *)&gpd_micropc, + }, { /* GPD MicroPC (later BIOS versions with proper DMI strings) */ + .matches = { + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "GPD"), + DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "MicroPC"), + }, + .driver_data = (void *)&lcd720x1280_rightside_up, }, { /* * GPD Pocket, note that the the DMI data is less generic then * it seems, devices with a board-vendor of "AMI Corporation" -- cgit v1.2.3 From e5704b3fe9d5ffa810abd8ce00215f52f3fd675b Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 28 Jun 2019 12:39:05 +0200 Subject: drm: connector: remove bogus NULL check mode->name is a character array in a structure, checking it's address is pointless and causes a warning with some compilers: drivers/gpu/drm/drm_connector.c:144:15: error: address of array 'mode->name' will always evaluate to 'true' [-Werror,-Wpointer-bool-conversion] mode->name ? mode->name : "", ~~~~~~^~~~ ~ include/drm/drm_print.h:366:29: note: expanded from macro 'DRM_DEBUG_KMS' drm_dbg(DRM_UT_KMS, fmt, ##__VA_ARGS__) ^~~~~~~~~~~ Remove the check here. Fixes: 3aeeb13d8996 ("drm/modes: Support modes names on the command line") Signed-off-by: Arnd Bergmann Reviewed-by: Ramalingam C Reviewed-by: Boris Brezillon Signed-off-by: Boris Brezillon Link: https://patchwork.freedesktop.org/patch/msgid/20190628103925.2686249-1-arnd@arndb.de --- drivers/gpu/drm/drm_connector.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c index 3afed5677946..b3f2cf7eae9c 100644 --- a/drivers/gpu/drm/drm_connector.c +++ b/drivers/gpu/drm/drm_connector.c @@ -141,7 +141,7 @@ static void drm_connector_get_cmdline_mode(struct drm_connector *connector) DRM_DEBUG_KMS("cmdline mode for connector %s %s %dx%d@%dHz%s%s%s\n", connector->name, - mode->name ? mode->name : "", + mode->name, mode->xres, mode->yres, mode->refresh_specified ? mode->refresh : 60, mode->rb ? " reduced blanking" : "", -- cgit v1.2.3 From 505f6cff880e33a9725bc8337bcb2941c6dd43a6 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 5 Jul 2019 14:10:02 +0200 Subject: drm/komeda: Remove clock ratio property Properties are uapi like anything else, with all the usual rules regarding review, testcases, open source userspace ... Furthermore driver-private kms properties are highly discouraged, over the past few years we've realized we need to make a serious effort at better standardizing this stuff. From the discussion with Liviu the solution for these here needs multiple pieces: - For being able to reliably read the memory clock we need a DT property, plus maybe DT override snippets to fix it if it's wrong. - For exposing plane limitations to userspace there's TEST_ONLY. There is a bit a gap in telling userspace better that scaling doesn't work due to limits (atm a good strategy is to retry again without scaling when adding a plane didn't work the first time around). But that needs a more generic solution, not exposing something extremely komeda specific. - If this is needed by validation tools, you can still expose it in debugfs. We have an entire nice infrastructure for debug printing of kms objects already, see the various atomic_print_state callbacks and infrastructure around them. Fixes: 1f7f9ab7900e ("drm/komeda: Add engine clock requirement check for the downscaling") Cc: Lowry Li (Arm Technology China) Cc: James Qian Wang (Arm Technology China) Cc: Liviu Dudau Cc: Mali DP Maintainers Cc: Brian Starkey Signed-off-by: Daniel Vetter Signed-off-by: Daniel Vetter Signed-off-by: Liviu Dudau Link: https://patchwork.freedesktop.org/patch/msgid/20190705121006.26085-1-daniel.vetter@ffwll.ch --- drivers/gpu/drm/arm/display/komeda/komeda_crtc.c | 39 ------------------------ drivers/gpu/drm/arm/display/komeda/komeda_kms.h | 3 -- 2 files changed, 42 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c index 3f222f464eb2..e852dc27f1b8 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c @@ -454,24 +454,6 @@ static void komeda_crtc_vblank_disable(struct drm_crtc *crtc) mdev->funcs->on_off_vblank(mdev, kcrtc->master->id, false); } -static int -komeda_crtc_atomic_get_property(struct drm_crtc *crtc, - const struct drm_crtc_state *state, - struct drm_property *property, uint64_t *val) -{ - struct komeda_crtc *kcrtc = to_kcrtc(crtc); - struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(state); - - if (property == kcrtc->clock_ratio_property) { - *val = kcrtc_st->clock_ratio; - } else { - DRM_DEBUG_DRIVER("Unknown property %s\n", property->name); - return -EINVAL; - } - - return 0; -} - static const struct drm_crtc_funcs komeda_crtc_funcs = { .gamma_set = drm_atomic_helper_legacy_gamma_set, .destroy = drm_crtc_cleanup, @@ -482,7 +464,6 @@ static const struct drm_crtc_funcs komeda_crtc_funcs = { .atomic_destroy_state = komeda_crtc_atomic_destroy_state, .enable_vblank = komeda_crtc_vblank_enable, .disable_vblank = komeda_crtc_vblank_disable, - .atomic_get_property = komeda_crtc_atomic_get_property, }; int komeda_kms_setup_crtcs(struct komeda_kms_dev *kms, @@ -518,22 +499,6 @@ int komeda_kms_setup_crtcs(struct komeda_kms_dev *kms, return 0; } -static int komeda_crtc_create_clock_ratio_property(struct komeda_crtc *kcrtc) -{ - struct drm_crtc *crtc = &kcrtc->base; - struct drm_property *prop; - - prop = drm_property_create_range(crtc->dev, DRM_MODE_PROP_ATOMIC, - "CLOCK_RATIO", 0, U64_MAX); - if (!prop) - return -ENOMEM; - - drm_object_attach_property(&crtc->base, prop, 0); - kcrtc->clock_ratio_property = prop; - - return 0; -} - static int komeda_crtc_create_slave_planes_property(struct komeda_crtc *kcrtc) { struct drm_crtc *crtc = &kcrtc->base; @@ -590,10 +555,6 @@ static int komeda_crtc_add(struct komeda_kms_dev *kms, crtc->port = kcrtc->master->of_output_port; - err = komeda_crtc_create_clock_ratio_property(kcrtc); - if (err) - return err; - err = komeda_crtc_create_slave_planes_property(kcrtc); if (err) return err; diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_kms.h b/drivers/gpu/drm/arm/display/komeda/komeda_kms.h index 219fa3f0c336..2775f34bf4ab 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_kms.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_kms.h @@ -95,9 +95,6 @@ struct komeda_crtc { /** @disable_done: this flip_done is for tracing the disable */ struct completion *disable_done; - /** @clock_ratio_property: property for ratio of (aclk << 32)/pxlclk */ - struct drm_property *clock_ratio_property; - /** @slave_planes_property: property for slaves of the planes */ struct drm_property *slave_planes_property; }; -- cgit v1.2.3 From 8aa0625f48559861b17606cf73fb24bd9f479303 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 5 Jul 2019 14:10:03 +0200 Subject: drm/komeda: remove slave_planes property Properties are uapi like anything else, with all the usual rules regarding review, testcases, open source userspace ... Furthermore driver-private kms properties are highly discouraged, over the past few years we've realized we need to make a serious effort at better standardizing this stuff. Again this probably needs multiple pieces to solve this properly: - To make plane configuration less surprising to userspace you propably need to virtualize planes, and reorder which logical plane you map to which physical one dynamically. Instead of exposing a komeda-specific limitation to userspace and expecting them to dtrt. I think msm and rcar-du do that already (and others), if you need people to chat with or example code. - If this is needed for validation, again ->atomic_print_state and the infrastructure around that is your friend. Fixes: 3b9dfa4ef28c ("drm/komeda: Add slave pipeline support") Cc: Lowry Li (Arm Technology China) Cc: James Qian Wang (Arm Technology China) Cc: Liviu Dudau Cc: Mali DP Maintainers Cc: Brian Starkey Signed-off-by: Daniel Vetter Signed-off-by: Daniel Vetter Signed-off-by: Liviu Dudau Link: https://patchwork.freedesktop.org/patch/msgid/20190705121006.26085-2-daniel.vetter@ffwll.ch --- drivers/gpu/drm/arm/display/komeda/komeda_crtc.c | 24 ------------------------ drivers/gpu/drm/arm/display/komeda/komeda_kms.h | 3 --- 2 files changed, 27 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c index e852dc27f1b8..f4400788ab94 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c @@ -499,26 +499,6 @@ int komeda_kms_setup_crtcs(struct komeda_kms_dev *kms, return 0; } -static int komeda_crtc_create_slave_planes_property(struct komeda_crtc *kcrtc) -{ - struct drm_crtc *crtc = &kcrtc->base; - struct drm_property *prop; - - if (kcrtc->slave_planes == 0) - return 0; - - prop = drm_property_create_range(crtc->dev, DRM_MODE_PROP_IMMUTABLE, - "slave_planes", 0, U32_MAX); - if (!prop) - return -ENOMEM; - - drm_object_attach_property(&crtc->base, prop, kcrtc->slave_planes); - - kcrtc->slave_planes_property = prop; - - return 0; -} - static struct drm_plane * get_crtc_primary(struct komeda_kms_dev *kms, struct komeda_crtc *crtc) { @@ -555,10 +535,6 @@ static int komeda_crtc_add(struct komeda_kms_dev *kms, crtc->port = kcrtc->master->of_output_port; - err = komeda_crtc_create_slave_planes_property(kcrtc); - if (err) - return err; - return err; } diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_kms.h b/drivers/gpu/drm/arm/display/komeda/komeda_kms.h index 2775f34bf4ab..c545cb963d40 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_kms.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_kms.h @@ -94,9 +94,6 @@ struct komeda_crtc { /** @disable_done: this flip_done is for tracing the disable */ struct completion *disable_done; - - /** @slave_planes_property: property for slaves of the planes */ - struct drm_property *slave_planes_property; }; /** -- cgit v1.2.3 From a76f612c1de8f82b1712e78e73d223f677f8254e Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 5 Jul 2019 14:10:04 +0200 Subject: drm/komeda: remove img_enhancement property Properties are uapi like anything else, with all the usual rules regarding review, testcases, open source userspace ... Furthermore driver-private kms properties are highly discouraged, over the past few years we've realized we need to make a serious effort at better standardizing this stuff. Again this probably needs multiple pieces to solve this properly: - Instead of expecting userspace to compute this (and duplicating modeset code), the kernel driver should compute when it's possible to enable this better up/downscale mode (assuming I understood Liviu correctly on what this does) automatically. - If this is needed for validation then you want a debugfs file to force this one way or the other, or alternatively use ->atomic_print_state to dump such hidden driver-private state. Depends upon how you do your validation ofc. Fixes: 42b6f118f6d1 ("drm/komeda: Add image enhancement support") Cc: Lowry Li (Arm Technology China) Cc: James Qian Wang (Arm Technology China) Cc: Liviu Dudau Cc: Mali DP Maintainers Cc: Brian Starkey Signed-off-by: Daniel Vetter Signed-off-by: Daniel Vetter Signed-off-by: Liviu Dudau Link: https://patchwork.freedesktop.org/patch/msgid/20190705121006.26085-3-daniel.vetter@ffwll.ch --- drivers/gpu/drm/arm/display/komeda/komeda_kms.h | 2 -- drivers/gpu/drm/arm/display/komeda/komeda_plane.c | 19 ++----------------- 2 files changed, 2 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_kms.h b/drivers/gpu/drm/arm/display/komeda/komeda_kms.h index c545cb963d40..fb2adc233760 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_kms.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_kms.h @@ -34,8 +34,6 @@ struct komeda_plane { */ struct komeda_layer *layer; - /** @prop_img_enhancement: for on/off image enhancement */ - struct drm_property *prop_img_enhancement; /** @prop_layer_split: for on/off layer_split */ struct drm_property *prop_layer_split; }; diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c index 04b122f28fb6..23db38650a46 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c @@ -197,9 +197,7 @@ komeda_plane_atomic_get_property(struct drm_plane *plane, struct komeda_plane *kplane = to_kplane(plane); struct komeda_plane_state *st = to_kplane_st(state); - if (property == kplane->prop_img_enhancement) - *val = st->img_enhancement; - else if (property == kplane->prop_layer_split) + if (property == kplane->prop_layer_split) *val = st->layer_split; else return -EINVAL; @@ -216,9 +214,7 @@ komeda_plane_atomic_set_property(struct drm_plane *plane, struct komeda_plane *kplane = to_kplane(plane); struct komeda_plane_state *st = to_kplane_st(state); - if (property == kplane->prop_img_enhancement) - st->img_enhancement = !!val; - else if (property == kplane->prop_layer_split) + if (property == kplane->prop_layer_split) st->layer_split = !!val; else return -EINVAL; @@ -258,17 +254,6 @@ komeda_plane_create_layer_properties(struct komeda_plane *kplane, struct drm_plane *plane = &kplane->base; struct drm_property *prop = NULL; - /* property: layer image_enhancement */ - if (layer->base.supported_outputs & KOMEDA_PIPELINE_SCALERS) { - prop = drm_property_create_bool(drm, DRM_MODE_PROP_ATOMIC, - "img_enhancement"); - if (!prop) - return -ENOMEM; - - drm_object_attach_property(&plane->base, prop, 0); - kplane->prop_img_enhancement = prop; - } - /* property: layer split */ if (layer->right) { prop = drm_property_create_bool(drm, DRM_MODE_PROP_ATOMIC, -- cgit v1.2.3 From c945623c05c34814c655a0c87155dca81d7e7146 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 5 Jul 2019 14:10:05 +0200 Subject: drm/komeda: Remove layer_split property Properties are uapi like anything else, with all the usual rules regarding review, testcases, open source userspace ... Furthermore driver-private kms properties are highly discouraged, over the past few years we've realized we need to make a serious effort at better standardizing this stuff. Again this probably needs multiple pieces to solve this properly: - Instead of expecting userspace to compute this (and duplicating modeset code), the kernel driver should compute when it's necessary to enable layer_split mode to make a configuration possible. I.e. in komeda_plane_atomic_check() first try komeda_build_layer_data_flow() and if that fails, try komeda_build_layer_split_data_flow(), and set dflow.en_split accordingly. Assuming I understand somewhat correctly what this does. - If this is needed for validation then you want a debugfs file to force this one way or the other, or alternatively use ->atomic_print_state to dump such hidden driver-private state. Depends upon how you do your validation ofc. Fixes: a407a6509393 ("drm/komeda: Add layer split support") Cc: Lowry Li (Arm Technology China) Cc: James Qian Wang (Arm Technology China) Cc: Liviu Dudau Cc: Mali DP Maintainers Cc: Brian Starkey Signed-off-by: Daniel Vetter Signed-off-by: Daniel Vetter Signed-off-by: Liviu Dudau Link: https://patchwork.freedesktop.org/patch/msgid/20190705121006.26085-4-daniel.vetter@ffwll.ch --- drivers/gpu/drm/arm/display/komeda/komeda_kms.h | 3 -- drivers/gpu/drm/arm/display/komeda/komeda_plane.c | 61 ----------------------- 2 files changed, 64 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_kms.h b/drivers/gpu/drm/arm/display/komeda/komeda_kms.h index fb2adc233760..0c006576a25c 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_kms.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_kms.h @@ -33,9 +33,6 @@ struct komeda_plane { * Layers with same capabilities. */ struct komeda_layer *layer; - - /** @prop_layer_split: for on/off layer_split */ - struct drm_property *prop_layer_split; }; /** diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c index 23db38650a46..5bb8553cc117 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c @@ -188,40 +188,6 @@ komeda_plane_atomic_destroy_state(struct drm_plane *plane, kfree(to_kplane_st(state)); } -static int -komeda_plane_atomic_get_property(struct drm_plane *plane, - const struct drm_plane_state *state, - struct drm_property *property, - uint64_t *val) -{ - struct komeda_plane *kplane = to_kplane(plane); - struct komeda_plane_state *st = to_kplane_st(state); - - if (property == kplane->prop_layer_split) - *val = st->layer_split; - else - return -EINVAL; - - return 0; -} - -static int -komeda_plane_atomic_set_property(struct drm_plane *plane, - struct drm_plane_state *state, - struct drm_property *property, - uint64_t val) -{ - struct komeda_plane *kplane = to_kplane(plane); - struct komeda_plane_state *st = to_kplane_st(state); - - if (property == kplane->prop_layer_split) - st->layer_split = !!val; - else - return -EINVAL; - - return 0; -} - static bool komeda_plane_format_mod_supported(struct drm_plane *plane, u32 format, u64 modifier) @@ -241,32 +207,9 @@ static const struct drm_plane_funcs komeda_plane_funcs = { .reset = komeda_plane_reset, .atomic_duplicate_state = komeda_plane_atomic_duplicate_state, .atomic_destroy_state = komeda_plane_atomic_destroy_state, - .atomic_get_property = komeda_plane_atomic_get_property, - .atomic_set_property = komeda_plane_atomic_set_property, .format_mod_supported = komeda_plane_format_mod_supported, }; -static int -komeda_plane_create_layer_properties(struct komeda_plane *kplane, - struct komeda_layer *layer) -{ - struct drm_device *drm = kplane->base.dev; - struct drm_plane *plane = &kplane->base; - struct drm_property *prop = NULL; - - /* property: layer split */ - if (layer->right) { - prop = drm_property_create_bool(drm, DRM_MODE_PROP_ATOMIC, - "layer_split"); - if (!prop) - return -ENOMEM; - kplane->prop_layer_split = prop; - drm_object_attach_property(&plane->base, prop, 0); - } - - return 0; -} - /* for komeda, which is pipeline can be share between crtcs */ static u32 get_possible_crtcs(struct komeda_kms_dev *kms, struct komeda_pipeline *pipe) @@ -360,10 +303,6 @@ static int komeda_plane_add(struct komeda_kms_dev *kms, if (err) goto cleanup; - err = komeda_plane_create_layer_properties(kplane, layer); - if (err) - goto cleanup; - err = drm_plane_create_color_properties(plane, BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709) | -- cgit v1.2.3 From 1930c11204b1d83549a6f5f32500b35a4b909dbb Mon Sep 17 00:00:00 2001 From: "james qian wang (Arm Technology China)" Date: Mon, 8 Jul 2019 07:59:45 +0100 Subject: drm/komeda: Computing layer_split internally For layer_split no need user to enable/disable it, but compute it in komeda internally, komeda will enable it if the scaling exceed the acceptable range of scaler. Signed-off-by: james qian wang (Arm Technology China) Signed-off-by: Liviu Dudau Link: https://patchwork.freedesktop.org/patch/msgid/20190708065923.4887-1-james.qian.wang@arm.com --- drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h | 3 ++- drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c | 11 ++++++++++- drivers/gpu/drm/arm/display/komeda/komeda_plane.c | 3 +-- drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c | 10 +--------- 4 files changed, 14 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h index fc1b8613385e..a90bcbb3cb23 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h @@ -537,7 +537,8 @@ void komeda_pipeline_disable(struct komeda_pipeline *pipe, void komeda_pipeline_update(struct komeda_pipeline *pipe, struct drm_atomic_state *old_state); -void komeda_complete_data_flow_cfg(struct komeda_data_flow_cfg *dflow, +void komeda_complete_data_flow_cfg(struct komeda_layer *layer, + struct komeda_data_flow_cfg *dflow, struct drm_framebuffer *fb); #endif /* _KOMEDA_PIPELINE_H_*/ diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c index 2b415ef2b7d3..972a0f25254d 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c @@ -784,9 +784,11 @@ komeda_timing_ctrlr_validate(struct komeda_timing_ctrlr *ctrlr, return 0; } -void komeda_complete_data_flow_cfg(struct komeda_data_flow_cfg *dflow, +void komeda_complete_data_flow_cfg(struct komeda_layer *layer, + struct komeda_data_flow_cfg *dflow, struct drm_framebuffer *fb) { + struct komeda_scaler *scaler = layer->base.pipeline->scalers[0]; u32 w = dflow->in_w; u32 h = dflow->in_h; @@ -803,6 +805,13 @@ void komeda_complete_data_flow_cfg(struct komeda_data_flow_cfg *dflow, dflow->en_scaling = (w != dflow->out_w) || (h != dflow->out_h); dflow->is_yuv = fb->format->is_yuv; + + /* try to enable split if scaling exceed the scaler's acceptable + * input/output range. + */ + if (dflow->en_scaling && scaler) + dflow->en_split = !in_range(&scaler->hsize, dflow->in_w) || + !in_range(&scaler->hsize, dflow->out_w); } static bool merger_is_available(struct komeda_pipeline *pipe, diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c index 5bb8553cc117..b1386438357b 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c @@ -58,9 +58,8 @@ komeda_plane_init_data_flow(struct drm_plane_state *st, } dflow->en_img_enhancement = !!kplane_st->img_enhancement; - dflow->en_split = !!kplane_st->layer_split; - komeda_complete_data_flow_cfg(dflow, fb); + komeda_complete_data_flow_cfg(kplane->layer, dflow, fb); return 0; } diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c b/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c index bb8a61f6e9a4..617e1f7b8472 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c @@ -13,7 +13,6 @@ komeda_wb_init_data_flow(struct komeda_layer *wb_layer, struct komeda_crtc_state *kcrtc_st, struct komeda_data_flow_cfg *dflow) { - struct komeda_scaler *scaler = wb_layer->base.pipeline->scalers[0]; struct drm_framebuffer *fb = conn_st->writeback_job->fb; memset(dflow, 0, sizeof(*dflow)); @@ -28,14 +27,7 @@ komeda_wb_init_data_flow(struct komeda_layer *wb_layer, dflow->pixel_blend_mode = DRM_MODE_BLEND_PIXEL_NONE; dflow->rot = DRM_MODE_ROTATE_0; - komeda_complete_data_flow_cfg(dflow, fb); - - /* if scaling exceed the acceptable scaler input/output range, try to - * enable split. - */ - if (dflow->en_scaling && scaler) - dflow->en_split = !in_range(&scaler->hsize, dflow->in_w) || - !in_range(&scaler->hsize, dflow->out_w); + komeda_complete_data_flow_cfg(wb_layer, dflow, fb); return 0; } -- cgit v1.2.3 From 990dee3aa45690217e8d83e7704cf07b2f3d9821 Mon Sep 17 00:00:00 2001 From: "james qian wang (Arm Technology China)" Date: Mon, 8 Jul 2019 08:00:22 +0100 Subject: drm/komeda: Computing image enhancer internally Enable image enhancer when the input data flow is 2x+ upscaling. Signed-off-by: james qian wang (Arm Technology China) Signed-off-by: Liviu Dudau Link: https://patchwork.freedesktop.org/patch/msgid/20190708070000.4945-1-james.qian.wang@arm.com --- drivers/gpu/drm/arm/display/komeda/komeda_kms.h | 7 ++----- drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c | 4 ++++ drivers/gpu/drm/arm/display/komeda/komeda_plane.c | 5 ----- 3 files changed, 6 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_kms.h b/drivers/gpu/drm/arm/display/komeda/komeda_kms.h index 0c006576a25c..8c89fc245b83 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_kms.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_kms.h @@ -47,11 +47,8 @@ struct komeda_plane_state { /** @zlist_node: zorder list node */ struct list_head zlist_node; - /* @img_enhancement: on/off image enhancement - * @layer_split: on/off layer_split - */ - u8 img_enhancement : 1, - layer_split : 1; + /** @layer_split: on/off layer_split */ + u8 layer_split : 1; }; /** diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c index 972a0f25254d..950235af1e79 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c @@ -806,6 +806,10 @@ void komeda_complete_data_flow_cfg(struct komeda_layer *layer, dflow->en_scaling = (w != dflow->out_w) || (h != dflow->out_h); dflow->is_yuv = fb->format->is_yuv; + /* try to enable image enhancer if data flow is a 2x+ upscaling */ + dflow->en_img_enhancement = dflow->out_w >= 2 * w || + dflow->out_h >= 2 * h; + /* try to enable split if scaling exceed the scaler's acceptable * input/output range. */ diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c index b1386438357b..c095af154216 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c @@ -18,7 +18,6 @@ komeda_plane_init_data_flow(struct drm_plane_state *st, struct komeda_data_flow_cfg *dflow) { struct komeda_plane *kplane = to_kplane(st->plane); - struct komeda_plane_state *kplane_st = to_kplane_st(st); struct drm_framebuffer *fb = st->fb; const struct komeda_format_caps *caps = to_kfb(fb)->format_caps; struct komeda_pipeline *pipe = kplane->layer->base.pipeline; @@ -57,8 +56,6 @@ komeda_plane_init_data_flow(struct drm_plane_state *st, return -EINVAL; } - dflow->en_img_enhancement = !!kplane_st->img_enhancement; - komeda_complete_data_flow_cfg(kplane->layer, dflow, fb); return 0; @@ -174,8 +171,6 @@ komeda_plane_atomic_duplicate_state(struct drm_plane *plane) old = to_kplane_st(plane->state); - new->img_enhancement = old->img_enhancement; - return &new->base; } -- cgit v1.2.3 From 32eaeae0ef193b64a67177006bdf5d9130d83fd3 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 8 Jul 2019 13:33:22 -0500 Subject: drm/amdgpu/psp: add a mutex to protect access to the psp ring We need to serialize access to the psp ring if there are multiple callers at runtime. Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 16 ++++++++++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 + 3 files changed, 16 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 7401bc95c15b..5a7f893cf724 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2537,6 +2537,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, hash_init(adev->mn_hash); mutex_init(&adev->lock_reset); mutex_init(&adev->virt.dpm_mutex); + mutex_init(&adev->psp.mutex); r = amdgpu_device_check_arguments(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index e69ad6e089c5..9882d90e765e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -130,6 +130,8 @@ psp_cmd_submit_buf(struct psp_context *psp, int index; int timeout = 2000; + mutex_lock(&psp->mutex); + memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); @@ -139,6 +141,7 @@ psp_cmd_submit_buf(struct psp_context *psp, fence_mc_addr, index); if (ret) { atomic_dec(&psp->fence_value); + mutex_unlock(&psp->mutex); return ret; } @@ -161,8 +164,10 @@ psp_cmd_submit_buf(struct psp_context *psp, ucode->ucode_id); DRM_WARN("psp command failed and response status is (%d)\n", psp->cmd_buf_mem->resp.status); - if (!timeout) + if (!timeout) { + mutex_unlock(&psp->mutex); return -EINVAL; + } } /* get xGMI session id from response buffer */ @@ -172,6 +177,7 @@ psp_cmd_submit_buf(struct psp_context *psp, ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; } + mutex_unlock(&psp->mutex); return ret; } @@ -1188,10 +1194,16 @@ failed: int psp_gpu_reset(struct amdgpu_device *adev) { + int ret; + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) return 0; - return psp_mode1_reset(&adev->psp); + mutex_lock(&adev->psp.mutex); + ret = psp_mode1_reset(&adev->psp); + mutex_unlock(&adev->psp.mutex); + + return ret; } int psp_rlc_autoload_start(struct psp_context *psp) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 6039acc84346..e28cf5e4016e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -201,6 +201,7 @@ struct psp_context uint8_t *ta_ras_start_addr; struct psp_xgmi_context xgmi_context; struct psp_ras_context ras; + struct mutex mutex; }; struct amdgpu_psp_funcs { -- cgit v1.2.3 From 7f3bbc0b817b51206948b743331c7441bf918c7f Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Tue, 9 Jul 2019 17:51:51 +0300 Subject: drm/modes: Skip invalid cmdline mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The named mode could be invalid and then cmdline parser misses to validate mode's dimensions, happily adding 0x0 mode as a valid mode. One case where this happens is NVIDIA Tegra devices that are using downstream bootloader which adds "video=tegrafb" to the kernel's cmdline and thus upstream Tegra DRM driver fails to probe because of the invalid mode. Fixes: 3aeeb13d8996 ("drm/modes: Support modes names on the command line") Reviewed-by: Ville Syrjälä Signed-off-by: Dmitry Osipenko Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20190709145151.23086-1-digetx@gmail.com --- drivers/gpu/drm/drm_client_modeset.c | 3 ++- drivers/gpu/drm/drm_modes.c | 6 ++++++ 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_client_modeset.c b/drivers/gpu/drm/drm_client_modeset.c index e95fceac8f8b..56d36779d213 100644 --- a/drivers/gpu/drm/drm_client_modeset.c +++ b/drivers/gpu/drm/drm_client_modeset.c @@ -180,7 +180,8 @@ again: create_mode: mode = drm_mode_create_from_cmdline_mode(connector->dev, cmdline_mode); - list_add(&mode->head, &connector->modes); + if (mode) + list_add(&mode->head, &connector->modes); return mode; } diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c index 910561d4f071..74a5739df506 100644 --- a/drivers/gpu/drm/drm_modes.c +++ b/drivers/gpu/drm/drm_modes.c @@ -158,6 +158,9 @@ struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay, int interlace; u64 tmp; + if (!hdisplay || !vdisplay) + return NULL; + /* allocate the drm_display_mode structure. If failure, we will * return directly */ @@ -392,6 +395,9 @@ drm_gtf_mode_complex(struct drm_device *dev, int hdisplay, int vdisplay, int hsync, hfront_porch, vodd_front_porch_lines; unsigned int tmp1, tmp2; + if (!hdisplay || !vdisplay) + return NULL; + drm_mode = drm_mode_create(dev); if (!drm_mode) return NULL; -- cgit v1.2.3 From 7e4dec58032deb75181ec56f31aa25184333f7d0 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 9 Jul 2019 19:31:21 -0400 Subject: drm/amdgpu: Fix potential integer overflows With mm_nodes larger than 4GB, byte_count in amdgpu_fill_buffer would overflow. Signed-off-by: Felix Kuehling Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 333cfbdf6dd0..8462934d23ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2059,9 +2059,9 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, mm_node = bo->tbo.mem.mm_node; num_loops = 0; while (num_pages) { - uint32_t byte_count = mm_node->size << PAGE_SHIFT; + uint64_t byte_count = mm_node->size << PAGE_SHIFT; - num_loops += DIV_ROUND_UP(byte_count, max_bytes); + num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes); num_pages -= mm_node->size; ++mm_node; } @@ -2087,12 +2087,13 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, mm_node = bo->tbo.mem.mm_node; while (num_pages) { - uint32_t byte_count = mm_node->size << PAGE_SHIFT; + uint64_t byte_count = mm_node->size << PAGE_SHIFT; uint64_t dst_addr; dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem); while (byte_count) { - uint32_t cur_size_in_bytes = min(byte_count, max_bytes); + uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count, + max_bytes); amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr, cur_size_in_bytes); -- cgit v1.2.3 From 617a64dc85f91c46ccf65aefbf7a4d194280a453 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Wed, 3 Jul 2019 09:21:37 +0800 Subject: drm/amd/powerplay: increase the SMU msg response waiting time This is expected to fix some mode1 reset failures. And this affects SMU part only as the timeout setting for other parts is controlled by a different macro. Signed-off-by: Evan Quan Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/amd_shared.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index d352b8d76365..a0a7211438f2 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -26,7 +26,7 @@ #include -#define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */ +#define AMD_MAX_USEC_TIMEOUT 1000000 /* 1000 ms */ /* * Chip flags -- cgit v1.2.3 From a54166d79a6b910182703c18379a26e414539501 Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Thu, 11 Jul 2019 15:37:50 +0800 Subject: drm/amd/powerplay: bug fix for sysfs when we set profile_peak to sysfs:power_dpm_force_performance_level, we gets the wrong socclk level and mclk level.this patch fix this issue. Signed-off-by: Kenneth Feng Reviewed-by: Feifei Xu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index 880fe0930d9e..4404528f969a 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -1157,14 +1157,14 @@ static int navi10_get_profiling_clk_mask(struct smu_context *smu, ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count); if (ret) return ret; - *sclk_mask = level_count - 1; + *mclk_mask = level_count - 1; } if(soc_mask) { ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count); if (ret) return ret; - *sclk_mask = level_count - 1; + *soc_mask = level_count - 1; } } -- cgit v1.2.3 From a349b39253d597a83f3d5eb85e129da429652583 Mon Sep 17 00:00:00 2001 From: tiancyin Date: Thu, 11 Jul 2019 14:09:50 +0800 Subject: drm/amdgpu/discovery: fix DCE_HWIP mapping error in hw_id_map array ID of DCE_HWIP from vbios is DMU_HWID, mismatch cause null pointer crash in navi10 modprobe. Reviewed-by: Feifei Xu Reviewed-by: Xiaojie Yuan Signed-off-by: tiancyin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index e049ae6a76fb..1481899f86c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -123,7 +123,7 @@ static int hw_id_map[MAX_HWIP] = { [UVD_HWIP] = UVD_HWID, [VCE_HWIP] = VCE_HWID, [DF_HWIP] = DF_HWID, - [DCE_HWIP] = DCEAZ_HWID, + [DCE_HWIP] = DMU_HWID, [OSSSYS_HWIP] = OSSSYS_HWID, [SMUIO_HWIP] = SMUIO_HWID, [PWR_HWIP] = PWR_HWID, -- cgit v1.2.3 From 63e2fef631383b9a44a2b727b9507fe058cba9c1 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 8 Jul 2019 13:47:12 -0500 Subject: drm/amdgpu: enable IP discovery by default on navi Use the IP discovery table rather than hardcoding the settings in the driver. Reviewed-by: Xiaojie Yuan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 1b0613c7cf95..ca7543e6aef8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -140,7 +140,7 @@ uint amdgpu_smu_memory_pool_size = 0; uint amdgpu_dc_feature_mask = 0; int amdgpu_async_gfx_ring = 1; int amdgpu_mcbp = 0; -int amdgpu_discovery = 0; +int amdgpu_discovery = -1; int amdgpu_mes = 0; struct amdgpu_mgpu_info mgpu_info = { @@ -593,6 +593,7 @@ module_param_named(mcbp, amdgpu_mcbp, int, 0444); /** * DOC: discovery (int) * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. + * (-1 = auto (default), 0 = disabled, 1 = enabled) */ MODULE_PARM_DESC(discovery, "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); -- cgit v1.2.3 From 70df8273ca0cebd2bba443a4444b4944a5929151 Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Tue, 9 Jul 2019 15:33:53 -0400 Subject: drm/amdkfd: fix cp hang in eviction The cp hang occurs in OCL conformance test only on supermicro platform which has 40 cores and the test generates 40 threads. The root cause is race condition in non-protected flags. The fix is to add flags of is_evicted and is_active(init_mqd()) into protected area. Signed-off-by: Eric Huang Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 584748c23f14..e6a4288bfaa6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -1157,12 +1157,7 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( q->properties.type)]; - /* - * Eviction state logic: mark all queues as evicted, even ones - * not currently active. Restoring inactive queues later only - * updates the is_evicted flag but is a no-op otherwise. - */ - q->properties.is_evicted = !!qpd->evicted; + if (q->properties.type == KFD_QUEUE_TYPE_SDMA || q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) dqm->asic_ops.init_sdma_vm(dqm, q, qpd); @@ -1173,9 +1168,16 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, retval = -ENOMEM; goto out_deallocate_doorbell; } + + dqm_lock(dqm); + /* + * Eviction state logic: mark all queues as evicted, even ones + * not currently active. Restoring inactive queues later only + * updates the is_evicted flag but is a no-op otherwise. + */ + q->properties.is_evicted = !!qpd->evicted; mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr, &q->properties); - dqm_lock(dqm); list_add(&q->list, &qpd->queues_list); qpd->queue_count++; -- cgit v1.2.3 From 5fdb7c4c7f2691efd760b0b0dc00da4a3699f1a6 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Fri, 28 Jun 2019 13:39:41 -0400 Subject: drm/amd/display: Expose audio inst from DC to DM [Why] In order to give pin notifications to the sound driver from DM we need to know whether audio is enabled on a stream and what pin it's using from DC. [How] Expose the instance via stream status if it's a mapped resource for the stream. It will be -1 if there's no audio mapped. Cc: Leo Li Cc: Harry Wentland Signed-off-by: Nicholas Kazlauskas Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 +++ drivers/gpu/drm/amd/display/dc/dc_stream.h | 1 + 2 files changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 173fcfb5abe6..48dfb305a0b0 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -2011,6 +2011,9 @@ enum dc_status resource_map_pool_resources( if (context->streams[i] == stream) { context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst; context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id; + context->stream_status[i].audio_inst = + pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1; + return DC_OK; } diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index e253a5c591f6..0fa1c26bc20d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -42,6 +42,7 @@ struct dc_stream_status { int primary_otg_inst; int stream_enc_inst; int plane_count; + int audio_inst; struct timing_sync_info timing_sync_info; struct dc_plane_state *plane_states[MAX_SURFACE_NUM]; }; -- cgit v1.2.3 From 6ce8f316673f61416738e6df7329ca508a607762 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Thu, 11 Jul 2019 14:31:46 -0500 Subject: drm/amd/display: Add drm_audio_component support to amdgpu_dm [Why] The drm_audio_component can be used to give pin ELD notifications directly to the sound driver. This fixes audio endpoints disappearing due to missing unsolicited notifications. [How] Send the notification via the audio component whenever we enable or disable audio state on a stream. This matches what i915 does with their drm_audio_component and what Takashi Iwai's proposed hack for radeon/amdpgu did. This is a bit delayed in when the notification actually occurs, however. We wait until after all the programming is complete rather than sending the notification mid sequence. Particular care is needed for the get ELD callback since it can happen outside the locking and fencing DRM does for atomic commits. Cc: Leo Li Cc: Harry Wentland Signed-off-by: Nicholas Kazlauskas Reviewed-by: Alex Deucher Reviewed-by: Takashi Iwai Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/Kconfig | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 222 ++++++++++++++++++++++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 25 +++ 3 files changed, 248 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index 7073cfcf04e8..f954bf61af28 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -5,6 +5,7 @@ menu "Display Engine Configuration" config DRM_AMD_DC bool "AMD DC - Enable new display engine" default y + select SND_HDA_COMPONENT if SND_HDA_CORE select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS) help Choose this option if you want to use the new display engine diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0242d693f4f6..4a29f72334d0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -56,6 +56,7 @@ #include #include #include +#include #include #include @@ -65,6 +66,7 @@ #include #include #include +#include #if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" @@ -508,6 +510,139 @@ static void amdgpu_dm_fbc_init(struct drm_connector *connector) } +static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, + int pipe, bool *enabled, + unsigned char *buf, int max_bytes) +{ + struct drm_device *dev = dev_get_drvdata(kdev); + struct amdgpu_device *adev = dev->dev_private; + struct drm_connector *connector; + struct drm_connector_list_iter conn_iter; + struct amdgpu_dm_connector *aconnector; + int ret = 0; + + *enabled = false; + + mutex_lock(&adev->dm.audio_lock); + + drm_connector_list_iter_begin(dev, &conn_iter); + drm_for_each_connector_iter(connector, &conn_iter) { + aconnector = to_amdgpu_dm_connector(connector); + if (aconnector->audio_inst != port) + continue; + + *enabled = true; + ret = drm_eld_size(connector->eld); + memcpy(buf, connector->eld, min(max_bytes, ret)); + + break; + } + drm_connector_list_iter_end(&conn_iter); + + mutex_unlock(&adev->dm.audio_lock); + + DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); + + return ret; +} + +static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { + .get_eld = amdgpu_dm_audio_component_get_eld, +}; + +static int amdgpu_dm_audio_component_bind(struct device *kdev, + struct device *hda_kdev, void *data) +{ + struct drm_device *dev = dev_get_drvdata(kdev); + struct amdgpu_device *adev = dev->dev_private; + struct drm_audio_component *acomp = data; + + acomp->ops = &amdgpu_dm_audio_component_ops; + acomp->dev = kdev; + adev->dm.audio_component = acomp; + + return 0; +} + +static void amdgpu_dm_audio_component_unbind(struct device *kdev, + struct device *hda_kdev, void *data) +{ + struct drm_device *dev = dev_get_drvdata(kdev); + struct amdgpu_device *adev = dev->dev_private; + struct drm_audio_component *acomp = data; + + acomp->ops = NULL; + acomp->dev = NULL; + adev->dm.audio_component = NULL; +} + +static const struct component_ops amdgpu_dm_audio_component_bind_ops = { + .bind = amdgpu_dm_audio_component_bind, + .unbind = amdgpu_dm_audio_component_unbind, +}; + +static int amdgpu_dm_audio_init(struct amdgpu_device *adev) +{ + int i, ret; + + if (!amdgpu_audio) + return 0; + + adev->mode_info.audio.enabled = true; + + adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; + + for (i = 0; i < adev->mode_info.audio.num_pins; i++) { + adev->mode_info.audio.pin[i].channels = -1; + adev->mode_info.audio.pin[i].rate = -1; + adev->mode_info.audio.pin[i].bits_per_sample = -1; + adev->mode_info.audio.pin[i].status_bits = 0; + adev->mode_info.audio.pin[i].category_code = 0; + adev->mode_info.audio.pin[i].connected = false; + adev->mode_info.audio.pin[i].id = + adev->dm.dc->res_pool->audios[i]->inst; + adev->mode_info.audio.pin[i].offset = 0; + } + + ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); + if (ret < 0) + return ret; + + adev->dm.audio_registered = true; + + return 0; +} + +static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) +{ + if (!amdgpu_audio) + return; + + if (!adev->mode_info.audio.enabled) + return; + + if (adev->dm.audio_registered) { + component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); + adev->dm.audio_registered = false; + } + + /* TODO: Disable audio? */ + + adev->mode_info.audio.enabled = false; +} + +void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) +{ + struct drm_audio_component *acomp = adev->dm.audio_component; + + if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { + DRM_DEBUG_KMS("Notify ELD: %d\n", pin); + + acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, + pin, -1); + } +} + static int amdgpu_dm_init(struct amdgpu_device *adev) { struct dc_init_data init_data; @@ -518,6 +653,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) memset(&init_data, 0, sizeof(init_data)); mutex_init(&adev->dm.dc_lock); + mutex_init(&adev->dm.audio_lock); if(amdgpu_dm_irq_init(adev)) { DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); @@ -621,6 +757,8 @@ error: static void amdgpu_dm_fini(struct amdgpu_device *adev) { + amdgpu_dm_audio_fini(adev); + amdgpu_dm_destroy_drm_device(&adev->dm); /* DC Destroy TODO: Replace destroy DAL */ @@ -641,6 +779,7 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) adev->dm.freesync_module = NULL; } + mutex_destroy(&adev->dm.audio_lock); mutex_destroy(&adev->dm.dc_lock); return; @@ -1888,6 +2027,10 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) if (r) return r; + r = amdgpu_dm_audio_init(adev); + if (r) + return r; + return 0; } @@ -4834,6 +4977,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, aconnector->base.stereo_allowed = false; aconnector->base.dpms = DRM_MODE_DPMS_OFF; aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ + aconnector->audio_inst = -1; mutex_init(&aconnector->hpd_lock); /* @@ -5728,6 +5872,81 @@ cleanup: kfree(bundle); } +static void amdgpu_dm_commit_audio(struct drm_device *dev, + struct drm_atomic_state *state) +{ + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_dm_connector *aconnector; + struct drm_connector *connector; + struct drm_connector_state *old_con_state, *new_con_state; + struct drm_crtc_state *new_crtc_state; + struct dm_crtc_state *new_dm_crtc_state; + const struct dc_stream_status *status; + int i, inst; + + /* Notify device removals. */ + for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { + if (old_con_state->crtc != new_con_state->crtc) { + /* CRTC changes require notification. */ + goto notify; + } + + if (!new_con_state->crtc) + continue; + + new_crtc_state = drm_atomic_get_new_crtc_state( + state, new_con_state->crtc); + + if (!new_crtc_state) + continue; + + if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) + continue; + + notify: + aconnector = to_amdgpu_dm_connector(connector); + + mutex_lock(&adev->dm.audio_lock); + inst = aconnector->audio_inst; + aconnector->audio_inst = -1; + mutex_unlock(&adev->dm.audio_lock); + + amdgpu_dm_audio_eld_notify(adev, inst); + } + + /* Notify audio device additions. */ + for_each_new_connector_in_state(state, connector, new_con_state, i) { + if (!new_con_state->crtc) + continue; + + new_crtc_state = drm_atomic_get_new_crtc_state( + state, new_con_state->crtc); + + if (!new_crtc_state) + continue; + + if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) + continue; + + new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); + if (!new_dm_crtc_state->stream) + continue; + + status = dc_stream_get_status(new_dm_crtc_state->stream); + if (!status) + continue; + + aconnector = to_amdgpu_dm_connector(connector); + + mutex_lock(&adev->dm.audio_lock); + inst = status->audio_inst; + aconnector->audio_inst = inst; + mutex_unlock(&adev->dm.audio_lock); + + amdgpu_dm_audio_eld_notify(adev, inst); + } +} + /* * Enable interrupts on CRTCs that are newly active, undergone * a modeset, or have active planes again. @@ -6106,6 +6325,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) /* Enable interrupts for CRTCs going from 0 to n active planes. */ amdgpu_dm_enable_crtc_interrupts(dev, state, false); + /* Update audio instances for each connector. */ + amdgpu_dm_commit_audio(dev, state); + /* * send vblank event on all events not handled in flip and * mark consumed event for drm_atomic_helper_commit_hw_done diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index baca5dc22b92..b89cbbfcc0e9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -143,6 +143,28 @@ struct amdgpu_display_manager { */ struct mutex dc_lock; + /** + * @audio_lock: + * + * Guards access to audio instance changes. + */ + struct mutex audio_lock; + + /** + * @audio_component: + * + * Used to notify ELD changes to sound driver. + */ + struct drm_audio_component *audio_component; + + /** + * @audio_registered: + * + * True if the audio component has been registered + * successfully, false otherwise. + */ + bool audio_registered; + /** * @irq_handler_list_low_tab: * @@ -254,6 +276,9 @@ struct amdgpu_dm_connector { int max_vfreq ; int pixel_clock_mhz; + /* Audio instance - protected by audio_lock. */ + int audio_inst; + struct mutex hpd_lock; bool fake_enable; -- cgit v1.2.3 From 5f0f531c4f8a97258dd3133db74926574e6373ab Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Mon, 8 Jul 2019 13:50:05 +0200 Subject: drm/amdgpu: Print out voltage in DM_PPLIB As the clock is already logged, also log the voltage. Signed-off-by: Paul Menzel Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c index eac09bfe3be2..086a3bf83226 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c @@ -308,7 +308,8 @@ static void pp_to_dc_clock_levels_with_voltage( DC_DECODE_PP_CLOCK_TYPE(dc_clk_type)); for (i = 0; i < clk_level_info->num_levels; i++) { - DRM_INFO("DM_PPLIB:\t %d in kHz\n", pp_clks->data[i].clocks_in_khz); + DRM_INFO("DM_PPLIB:\t %d in kHz, %d in mV\n", pp_clks->data[i].clocks_in_khz, + pp_clks->data[i].voltage_in_mv); clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz; clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv; } -- cgit v1.2.3 From 3840fe256ae431d79e93988757a6f89db8192237 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Thu, 11 Jul 2019 22:02:02 +0800 Subject: drm/amdgpu: switch to macro for psp bootloader command The command will be sent to psp bootloader from driver to ask psp bootloader to exerise tOS, sys_drv and kdb loading Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher Reviewed-by: Xiaojie Yuan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 6 ++++++ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 4 ++-- 3 files changed, 10 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index e28cf5e4016e..6dcad432de1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -42,6 +42,12 @@ struct psp_context; struct psp_xgmi_node_info; struct psp_xgmi_topology_info; +enum psp_bootloader_cmd { + PSP_BL__LOAD_SYSDRV = 0x10000, + PSP_BL__LOAD_SOSDRV = 0x20000, + PSP_BL__LOAD_KEY_DATABASE = 0x80000, +}; + enum psp_ring_type { PSP_RING_TYPE__INVALID = 0, diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c index 61744e2d16fb..a5f84b62cd8f 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c @@ -208,7 +208,7 @@ static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) /* Provide the sys driver to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (uint32_t)(psp->fw_pri_mc_addr >> 20)); - psp_gfxdrv_command_reg = 1 << 16; + psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV; WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, psp_gfxdrv_command_reg); @@ -249,7 +249,7 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) /* Provide the PSP secure OS to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (uint32_t)(psp->fw_pri_mc_addr >> 20)); - psp_gfxdrv_command_reg = 2 << 16; + psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, psp_gfxdrv_command_reg); diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index 2ea772692037..019c47feee42 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c @@ -155,7 +155,7 @@ static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) /* Provide the sys driver to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (uint32_t)(psp->fw_pri_mc_addr >> 20)); - psp_gfxdrv_command_reg = 1 << 16; + psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV; WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, psp_gfxdrv_command_reg); @@ -218,7 +218,7 @@ static int psp_v3_1_bootloader_load_sos(struct psp_context *psp) /* Provide the PSP secure OS to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (uint32_t)(psp->fw_pri_mc_addr >> 20)); - psp_gfxdrv_command_reg = 2 << 16; + psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, psp_gfxdrv_command_reg); -- cgit v1.2.3 From 4298935924a9057f2424636d1d29ae7caef4764a Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Thu, 11 Jul 2019 00:13:54 +0800 Subject: drm/amdgpu: support key database loading for navi10 Starting from navi10, driver should send Key Database Load command to bootloader before loading sys_drv and sos Signed-off-by: John Clements Signed-off-by: Hawking Zhang Reviewed-by: Xiaojie Yuan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 9 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 5 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 6 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 3 ++ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 48 ++++++++++++++++++++++++++++++- 5 files changed, 70 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 9882d90e765e..c5b7049cc01d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -769,6 +769,15 @@ static int psp_hw_start(struct psp_context *psp) int ret; if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) { + if (psp->kdb_start_addr && + (psp->funcs->bootloader_load_kdb != NULL)) { + ret = psp_bootloader_load_kdb(psp); + if (ret) { + DRM_ERROR("PSP load kdb failed!\n"); + return ret; + } + } + ret = psp_bootloader_load_sysdrv(psp); if (ret) { DRM_ERROR("PSP load sysdrv failed!\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 6dcad432de1b..e0fc2a790e53 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -79,6 +79,7 @@ enum psp_reg_prog_id { struct psp_funcs { int (*init_microcode)(struct psp_context *psp); + int (*bootloader_load_kdb)(struct psp_context *psp); int (*bootloader_load_sysdrv)(struct psp_context *psp); int (*bootloader_load_sos)(struct psp_context *psp); int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type); @@ -162,9 +163,11 @@ struct psp_context uint32_t sys_bin_size; uint32_t sos_bin_size; uint32_t toc_bin_size; + uint32_t kdb_bin_size; uint8_t *sys_start_addr; uint8_t *sos_start_addr; uint8_t *toc_start_addr; + uint8_t *kdb_start_addr; /* tmr buffer */ struct amdgpu_bo *tmr_bo; @@ -226,6 +229,8 @@ struct amdgpu_psp_funcs { (psp)->funcs->compare_sram_data((psp), (ucode), (type)) #define psp_init_microcode(psp) \ ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) +#define psp_bootloader_load_kdb(psp) \ + ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0) #define psp_bootloader_load_sysdrv(psp) \ ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) #define psp_bootloader_load_sos(psp) \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index c352a519ddd4..bfaa0eac3213 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -262,6 +262,12 @@ void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr) le32_to_cpu(psp_hdr_v1_1->toc_offset_bytes)); DRM_DEBUG("toc_size_bytes: %u\n", le32_to_cpu(psp_hdr_v1_1->toc_size_bytes)); + DRM_DEBUG("kdb_header_version: %u\n", + le32_to_cpu(psp_hdr_v1_1->kdb_header_version)); + DRM_DEBUG("kdb_offset_bytes: %u\n", + le32_to_cpu(psp_hdr_v1_1->kdb_offset_bytes)); + DRM_DEBUG("kdb_size_bytes: %u\n", + le32_to_cpu(psp_hdr_v1_1->kdb_size_bytes)); } } else { DRM_ERROR("Unknown PSP ucode version: %u.%u\n", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h index f46944453c6e..c1fb6dc86440 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h @@ -85,6 +85,9 @@ struct psp_firmware_header_v1_1 { uint32_t toc_header_version; uint32_t toc_offset_bytes; uint32_t toc_size_bytes; + uint32_t kdb_header_version; + uint32_t kdb_offset_bytes; + uint32_t kdb_size_bytes; }; /* version_major=1, version_minor=0 */ diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c index a5f84b62cd8f..41b72588adcf 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c @@ -103,6 +103,9 @@ static int psp_v11_0_init_microcode(struct psp_context *psp) adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); + adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes); + adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + + le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes); } break; default: @@ -177,6 +180,48 @@ out: return err; } +static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp) +{ + int ret; + uint32_t psp_gfxdrv_command_reg = 0; + struct amdgpu_device *adev = psp->adev; + uint32_t sol_reg; + + /* Check tOS sign of life register to confirm sys driver and sOS + * are already been loaded. + */ + sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); + if (sol_reg) { + psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); + dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version); + return 0; + } + + /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), + 0x80000000, 0x80000000, false); + if (ret) + return ret; + + memset(psp->fw_pri_buf, 0, PSP_1_MEG); + + /* Copy PSP KDB binary to memory */ + memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size); + + /* Provide the sys driver to bootloader */ + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, + (uint32_t)(psp->fw_pri_mc_addr >> 20)); + psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE; + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, + psp_gfxdrv_command_reg); + + /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1*/ + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), + 0x80000000, 0x80000000, false); + + return ret; +} + static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) { int ret; @@ -190,7 +235,7 @@ static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); if (sol_reg) { psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); - printk("sos fw version = 0x%x.\n", psp->sos_fw_version); + dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version); return 0; } @@ -822,6 +867,7 @@ static int psp_v11_0_rlc_autoload_start(struct psp_context *psp) static const struct psp_funcs psp_v11_0_funcs = { .init_microcode = psp_v11_0_init_microcode, + .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb, .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, .bootloader_load_sos = psp_v11_0_bootloader_load_sos, .ring_init = psp_v11_0_ring_init, -- cgit v1.2.3 From d36893362d22ff46fdb105ebab12df00bbf23397 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Thu, 11 Jul 2019 21:33:17 +0800 Subject: drm/amd/powerplay: fix smu clock type change miss error in the smu module, use the smu_xxxclk type to identify the CLK type use SMU_SCLK, SMU_MCLK to replace PP_SCLK, PP_MCLK. Signed-off-by: Kevin Wang Reviewed-by: Feifei Xu Reviewed-by: Evan Quan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index 3093917adc2d..c382eb901178 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -1385,8 +1385,8 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu, &soc_mask); if (ret) return ret; - smu_force_clk_levels(smu, PP_SCLK, 1 << sclk_mask); - smu_force_clk_levels(smu, PP_MCLK, 1 << mclk_mask); + smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask); + smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask); break; case AMD_DPM_FORCED_LEVEL_MANUAL: -- cgit v1.2.3 From 64974ab24908a92b5dfe52e1ace3d67c47d657cb Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Fri, 12 Jul 2019 11:27:50 +0800 Subject: drm/amd/powerplay: add pstate mclk(uclk) support for navi10 add pstate mclk(uclk) support. Signed-off-by: Kevin Wang Reviewed-by: Evan Quan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 1 + drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 8 +++++++- 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index c382eb901178..04132653e289 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -136,6 +136,7 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, return -EINVAL; switch (clk_type) { + case SMU_MCLK: case SMU_UCLK: if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { pr_warn("uclk dpm is not enabled\n"); diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index 4404528f969a..e25c1e3094ef 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -709,7 +709,7 @@ static int navi10_force_clk_levels(struct smu_context *smu, static int navi10_populate_umd_state_clk(struct smu_context *smu) { int ret = 0; - uint32_t min_sclk_freq = 0; + uint32_t min_sclk_freq = 0, min_mclk_freq = 0; ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL); if (ret) @@ -717,6 +717,12 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu) smu->pstate_sclk = min_sclk_freq * 100; + ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL); + if (ret) + return ret; + + smu->pstate_mclk = min_mclk_freq * 100; + return ret; } -- cgit v1.2.3 From 7e446b3c76b4ef0d3808305c0a51f895236b37bf Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 12 Jul 2019 11:37:00 +0200 Subject: drm/amd/display: Support clang option for stack alignment As previously fixed for dml in commit 4769278e5c7f ("amdgpu/dc/dml: Support clang option for stack alignment") and calcs in commit cc32ad8f559c ("amdgpu/dc/calcs: Support clang option for stack alignment"), dcn20 uses an option that is not available with clang: clang: error: unknown argument: '-mpreferred-stack-boundary=4' scripts/Makefile.build:281: recipe for target 'drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.o' failed Use the same trick that we have in the other two files. Fixes: 7ed4e6352c16 ("drm/amd/display: Add DCN2 HW Sequencer and Resource") Signed-off-by: Arnd Bergmann Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 8 +++++++- drivers/gpu/drm/amd/display/dc/dsc/Makefile | 16 ++++++++++++---- 2 files changed, 19 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile index 1b68de27ba74..e9721a906592 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile @@ -10,7 +10,13 @@ ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT DCN20 += dcn20_dsc.o endif -CFLAGS_dcn20_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4 +ifneq ($(call cc-option, -mpreferred-stack-boundary=4),) + cc_stack_align := -mpreferred-stack-boundary=4 +else ifneq ($(call cc-option, -mstack-alignment=16),) + cc_stack_align := -mstack-alignment=16 +endif + +CFLAGS_dcn20_resource.o := -mhard-float -msse $(cc_stack_align) AMD_DAL_DCN20 = $(addprefix $(AMDDALPATH)/dc/dcn20/,$(DCN20)) diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile b/drivers/gpu/drm/amd/display/dc/dsc/Makefile index c5d5b94e2604..e019cd9447e8 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile @@ -1,10 +1,18 @@ # # Makefile for the 'dsc' sub-component of DAL. -CFLAGS_rc_calc.o := -mhard-float -msse -mpreferred-stack-boundary=4 -CFLAGS_rc_calc_dpi.o := -mhard-float -msse -mpreferred-stack-boundary=4 -CFLAGS_codec_main_amd.o := -mhard-float -msse -mpreferred-stack-boundary=4 -CFLAGS_dc_dsc.o := -mhard-float -msse -mpreferred-stack-boundary=4 +ifneq ($(call cc-option, -mpreferred-stack-boundary=4),) + cc_stack_align := -mpreferred-stack-boundary=4 +else ifneq ($(call cc-option, -mstack-alignment=16),) + cc_stack_align := -mstack-alignment=16 +endif + +dsc_ccflags := -mhard-float -msse $(cc_stack_align) + +CFLAGS_rc_calc.o := $(dsc_ccflags) +CFLAGS_rc_calc_dpi.o := $(dsc_ccflags) +CFLAGS_codec_main_amd.o := $(dsc_ccflags) +CFLAGS_dc_dsc.o := $(dsc_ccflags) DSC = dc_dsc.o rc_calc.o rc_calc_dpi.o -- cgit v1.2.3 From 7a17c8ce3321bb0738283706d3b46b047a9cbcfb Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 12 Jul 2019 11:39:52 +0200 Subject: drm/amd/display: return 'NULL' instead of 'false' from dcn20_acquire_idle_pipe_for_layer clang complains that 'false' is a not a pointer: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:2428:10: error: expression which evaluates to zero treated as a null pointer constant of type 'struct pipe_ctx *' [-Werror,-Wnon-literal-null-conversion] return false; Changing it to 'NULL' looks like the right thing that will shut up the warning and make it easier to read, while not changing behavior. Fixes: 7ed4e6352c16 ("drm/amd/display: Add DCN2 HW Sequencer and Resource") Reviewed-by: Nathan Chancellor Signed-off-by: Arnd Bergmann Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index 4e52df82c993..3ad609276b2e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -2415,7 +2415,7 @@ struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer( ASSERT(0); if (!idle_pipe) - return false; + return NULL; idle_pipe->stream = head_pipe->stream; idle_pipe->stream_res.tg = head_pipe->stream_res.tg; -- cgit v1.2.3 From 75ee64875e758b2f10d319a50dc787516c52d3de Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Fri, 21 Jun 2019 19:50:03 -0400 Subject: drm/amdkfd: Consistently apply noretry setting MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Apply the same setting to SH_MEM_CONFIG and VM_CONTEXT1_CNTL. This makes the noretry param no longer KFD-specific. On GFX10 I'm not changing SH_MEM_CONFIG in this commit because GFX10 has different retry behaviour in the SQ and I don't have a way to test it at the moment. Suggested-by: Christian König CC: Philip Yang Signed-off-by: Felix Kuehling Reviewed-by : Shaoyun.liu < Shaoyun.liu@amd.com> Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 16 +++++----------- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 3 ++- drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 3 ++- drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 3 ++- drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +- 9 files changed, 20 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index f88d8141447c..8199d201b43a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -164,6 +164,7 @@ extern int amdgpu_async_gfx_ring; extern int amdgpu_mcbp; extern int amdgpu_discovery; extern int amdgpu_mes; +extern int amdgpu_noretry; #ifdef CONFIG_DRM_AMDGPU_SI extern int amdgpu_si_support; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index ca7543e6aef8..f2e8b4238efd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -142,6 +142,7 @@ int amdgpu_async_gfx_ring = 1; int amdgpu_mcbp = 0; int amdgpu_discovery = -1; int amdgpu_mes = 0; +int amdgpu_noretry; struct amdgpu_mgpu_info mgpu_info = { .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), @@ -608,6 +609,10 @@ MODULE_PARM_DESC(mes, "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); module_param_named(mes, amdgpu_mes, int, 0444); +MODULE_PARM_DESC(noretry, + "Disable retry faults (0 = retry enabled (default), 1 = retry disabled)"); +module_param_named(noretry, amdgpu_noretry, int, 0644); + #ifdef CONFIG_HSA_AMD /** * DOC: sched_policy (int) @@ -683,17 +688,6 @@ module_param(ignore_crat, int, 0444); MODULE_PARM_DESC(ignore_crat, "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)"); -/** - * DOC: noretry (int) - * This parameter sets sh_mem_config.retry_disable. Default value, 0, enables retry. - * Setting 1 disables retry. - * Retry is needed for recoverable page faults. - */ -int noretry; -module_param(noretry, int, 0644); -MODULE_PARM_DESC(noretry, - "Set sh_mem_config.retry_disable on Vega10 (0 = retry enabled (default), 1 = retry disabled)"); - /** * DOC: halt_if_hws_hang (int) * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 5ba332376710..68dc6b2314c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1942,11 +1942,15 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev) if (i == 0) { tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, SH_MEM_ALIGNMENT_MODE_UNALIGNED); + tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, + !!amdgpu_noretry); WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0); } else { tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, SH_MEM_ALIGNMENT_MODE_UNALIGNED); + tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, + !!amdgpu_noretry); WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, (adev->gmc.private_aperture_start >> 48)); diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c index 9f0f189fc111..15986748f59f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c @@ -236,7 +236,8 @@ static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) block_size); /* Send no-retry XNACK on fault to suppress VM fault storm. */ tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, - RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 1); + RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, + !amdgpu_noretry); WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp); WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c index b7de60a15623..d605b4963f8a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c @@ -215,7 +215,8 @@ static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) adev->vm_manager.block_size - 9); /* Send no-retry XNACK on fault to suppress VM fault storm. */ tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, - RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); + RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, + !amdgpu_noretry); WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i, tmp); WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index 05d1d448c8f5..dc5ce03034d3 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c @@ -265,7 +265,8 @@ static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) block_size); /* Send no-retry XNACK on fault to suppress VM fault storm. */ tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, - RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 1); + RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, + !amdgpu_noretry); WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp); WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c index 37a1a318ae63..0f9549f19ade 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c @@ -205,7 +205,8 @@ static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) adev->vm_manager.block_size - 9); /* Send no-retry XNACK on fault to suppress VM fault storm. */ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, - RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); + RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, + !amdgpu_noretry); WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i, tmp); WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c index e9fe39382371..95a82ac455f2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c @@ -61,7 +61,7 @@ static int update_qpd_v9(struct device_queue_manager *dqm, qpd->sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; - if (noretry && + if (amdgpu_noretry && !dqm->dev->device_info->needs_iommu_device) qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 08a0feb9d0a0..3933fb6a371e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -157,7 +157,7 @@ extern int ignore_crat; /* * Set sh_mem_config.retry_disable on Vega10 */ -extern int noretry; +extern int amdgpu_noretry; /* * Halt if HWS hang is detected -- cgit v1.2.3 From eaf963b5c17e611ca35850f65db7ebe929bef774 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Fri, 12 Jul 2019 14:40:12 +0800 Subject: drm/amd/powerplay: add socclk profile dpm support. 1.miss socclk profile support when bringup. 2.add feature check for socclk. Signed-off-by: Kevin Wang Reviewed-by: Evan Quan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index 04132653e289..5f844357e6ac 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -149,6 +149,11 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, pr_warn("gfxclk dpm is not enabled\n"); return 0; } + case SMU_SOCCLK: + if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { + pr_warn("sockclk dpm is not enabled\n"); + return 0; + } break; default: break; @@ -1388,6 +1393,7 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu, return ret; smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask); smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask); + smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); break; case AMD_DPM_FORCED_LEVEL_MANUAL: -- cgit v1.2.3 From 75728f512e1f6cc37da9c173b7a7690b10b1c3f5 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Fri, 12 Jul 2019 14:42:12 +0800 Subject: drm/amd/powerplay: add standard profile dpm support for smu 1. the standard dpm is not support before. 2. use auto profile to adapt standard profile. Signed-off-by: Kevin Wang Reviewed-by: Evan Quan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index 5f844357e6ac..e6f103988c6a 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -1378,10 +1378,10 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu, break; case AMD_DPM_FORCED_LEVEL_AUTO: + case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: ret = smu_unforce_dpm_levels(smu); break; - case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: -- cgit v1.2.3 From 42b3aa9a5bafef922de78f0b4d54435bf774d1c1 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Tue, 16 Jul 2019 13:07:23 -0500 Subject: drm/amd/powerplay: avoid double check feature enabled the unforce_dpm_levels doesn't need to check feature enablement. because the smu_get_dpm_freq_range function has check feature logic. Signed-off-by: Kevin Wang Reviewed-by: Evan Quan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index e25c1e3094ef..3e5d5f359c11 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -833,27 +833,20 @@ static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest) return ret; } -static int navi10_unforce_dpm_levels(struct smu_context *smu) { - +static int navi10_unforce_dpm_levels(struct smu_context *smu) +{ int ret = 0, i = 0; uint32_t min_freq, max_freq; enum smu_clk_type clk_type; - struct clk_feature_map { - enum smu_clk_type clk_type; - uint32_t feature; - } clk_feature_map[] = { - {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT}, - {SMU_MCLK, SMU_FEATURE_DPM_UCLK_BIT}, - {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT}, + enum smu_clk_type clks[] = { + SMU_GFXCLK, + SMU_MCLK, + SMU_SOCCLK, }; - for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { - if (!smu_feature_is_enabled(smu, clk_feature_map[i].feature)) - continue; - - clk_type = clk_feature_map[i].clk_type; - + for (i = 0; i < ARRAY_SIZE(clks); i++) { + clk_type = clks[i]; ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq); if (ret) return ret; -- cgit v1.2.3 From 8e33376b7649b353ffd55f2b40fe129ead3880f7 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Fri, 12 Jul 2019 17:05:52 +0800 Subject: drm/amd/powerplay: fix save dpm level error for smu the save dpm level should be save previous dpm profile level, should not modified by get dpm level function. eg: default auto 1. auto -> standard ==> dpm_level = standard, save_dpm = auto. 2. standard -> auto ==> dpm_level = auto, save_dpm = standard. Signed-off-by: Kevin Wang Reviewed-by: Evan Quan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index e6f103988c6a..8150cb81009f 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -1448,17 +1448,16 @@ int smu_handle_task(struct smu_context *smu, enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu) { struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); + enum amd_dpm_forced_level level; if (!smu_dpm_ctx->dpm_context) return -EINVAL; mutex_lock(&(smu->mutex)); - if (smu_dpm_ctx->dpm_level != smu_dpm_ctx->saved_dpm_level) { - smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; - } + level = smu_dpm_ctx->dpm_level; mutex_unlock(&(smu->mutex)); - return smu_dpm_ctx->dpm_level; + return level; } int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level) -- cgit v1.2.3 From 54728170e00cecfac0394c6ee7ea4043778a512b Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Fri, 12 Jul 2019 15:22:40 +0800 Subject: drm/amd/powerplay: add helper of smu_clk_dpm_is_enabled for smu v2: change function name to smu_clk_dpm_is_enabled. add this helper function to check dpm clk feature is enabled. Signed-off-by: Kevin Wang Reviewed-by: Evan Quan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 63 ++++++++++++++++---------- drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 + 2 files changed, 41 insertions(+), 23 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index 8150cb81009f..20257c036a65 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -69,6 +69,9 @@ int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, if (min <= 0 && max <= 0) return -EINVAL; + if (!smu_clk_dpm_is_enabled(smu, clk_type)) + return 0; + clk_id = smu_clk_get_index(smu, clk_type); if (clk_id < 0) return clk_id; @@ -102,6 +105,9 @@ int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, if (min <= 0 && max <= 0) return -EINVAL; + if (!smu_clk_dpm_is_enabled(smu, clk_type)) + return 0; + clk_id = smu_clk_get_index(smu, clk_type); if (clk_id < 0) return clk_id; @@ -135,29 +141,8 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, if (!min && !max) return -EINVAL; - switch (clk_type) { - case SMU_MCLK: - case SMU_UCLK: - if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { - pr_warn("uclk dpm is not enabled\n"); - return 0; - } - break; - case SMU_GFXCLK: - case SMU_SCLK: - if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { - pr_warn("gfxclk dpm is not enabled\n"); - return 0; - } - case SMU_SOCCLK: - if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { - pr_warn("sockclk dpm is not enabled\n"); - return 0; - } - break; - default: - break; - } + if (!smu_clk_dpm_is_enabled(smu, clk_type)) + return 0; mutex_lock(&smu->mutex); clk_id = smu_clk_get_index(smu, clk_type); @@ -200,6 +185,9 @@ int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_typ if (!value) return -EINVAL; + if (!smu_clk_dpm_is_enabled(smu, clk_type)) + return 0; + clk_id = smu_clk_get_index(smu, clk_type); if (clk_id < 0) return clk_id; @@ -228,6 +216,35 @@ int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type, return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value); } +bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type) +{ + enum smu_feature_mask feature_id = 0; + + switch (clk_type) { + case SMU_MCLK: + case SMU_UCLK: + feature_id = SMU_FEATURE_DPM_UCLK_BIT; + break; + case SMU_GFXCLK: + case SMU_SCLK: + feature_id = SMU_FEATURE_DPM_GFXCLK_BIT; + break; + case SMU_SOCCLK: + feature_id = SMU_FEATURE_DPM_SOCCLK_BIT; + break; + default: + return true; + } + + if(!smu_feature_is_enabled(smu, feature_id)) { + pr_warn("smu %d clk dpm feature %d is not enabled\n", clk_type, feature_id); + return false; + } + + return true; +} + + int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type, bool gate) { diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h index c97324ef7db2..135a3236f7ed 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h @@ -973,5 +973,6 @@ int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu); int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level); int smu_set_display_count(struct smu_context *smu, uint32_t count); +bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type); #endif -- cgit v1.2.3 From 0fa4246e8ebfb389142034ffcdf6e70de32dddf4 Mon Sep 17 00:00:00 2001 From: Tom St Denis Date: Fri, 12 Jul 2019 09:27:06 -0400 Subject: drm/amd/amdgpu: Add VMID to SRBM debugfs bank selection Add 5 bits to the offset for SRBM selection to handle VMIDs. Also update the select_me_pipe_q() callback to also select VMID. Signed-off-by: Tom St Denis Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 9 +++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++-- 6 files changed, 14 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 20ce158490db..c40abf819f3d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -106,10 +106,10 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct file *f, ssize_t result = 0; int r; bool pm_pg_lock, use_bank, use_ring; - unsigned instance_bank, sh_bank, se_bank, me, pipe, queue; + unsigned instance_bank, sh_bank, se_bank, me, pipe, queue, vmid; pm_pg_lock = use_bank = use_ring = false; - instance_bank = sh_bank = se_bank = me = pipe = queue = 0; + instance_bank = sh_bank = se_bank = me = pipe = queue = vmid = 0; if (size & 0x3 || *pos & 0x3 || ((*pos & (1ULL << 62)) && (*pos & (1ULL << 61)))) @@ -135,6 +135,7 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct file *f, me = (*pos & GENMASK_ULL(33, 24)) >> 24; pipe = (*pos & GENMASK_ULL(43, 34)) >> 34; queue = (*pos & GENMASK_ULL(53, 44)) >> 44; + vmid = (*pos & GENMASK_ULL(48, 45)) >> 54; use_ring = 1; } else { @@ -152,7 +153,7 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct file *f, sh_bank, instance_bank); } else if (use_ring) { mutex_lock(&adev->srbm_mutex); - amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue); + amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid); } if (pm_pg_lock) @@ -185,7 +186,7 @@ end: amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); mutex_unlock(&adev->grbm_idx_mutex); } else if (use_ring) { - amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0); + amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index f96407ba9770..1199b5828b90 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -195,7 +195,7 @@ struct amdgpu_gfx_funcs { uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, - u32 queue); + u32 queue, u32 vmid); }; struct amdgpu_ngg_buf { @@ -327,7 +327,7 @@ struct amdgpu_gfx { #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) -#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q)) +#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid)) /** * amdgpu_gfx_create_bitmask - create a bitmask diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 789e900905e9..7f0a63628c43 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -3043,7 +3043,7 @@ static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, } static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev, - u32 me, u32 pipe, u32 q) + u32 me, u32 pipe, u32 q, u32 vm) { DRM_INFO("Not implemented\n"); } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 341b5024e598..0db9f488da7e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -4169,9 +4169,9 @@ static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, } static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev, - u32 me, u32 pipe, u32 q) + u32 me, u32 pipe, u32 q, u32 vm) { - cik_srbm_select(adev, me, pipe, q, 0); + cik_srbm_select(adev, me, pipe, q, vm); } static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 032e76dbc51f..5f401b41ef7c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -3436,9 +3436,9 @@ static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, } static void gfx_v8_0_select_me_pipe_q(struct amdgpu_device *adev, - u32 me, u32 pipe, u32 q) + u32 me, u32 pipe, u32 q, u32 vm) { - vi_srbm_select(adev, me, pipe, q, 0); + vi_srbm_select(adev, me, pipe, q, vm); } static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 68dc6b2314c4..f4c4eea62526 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1313,9 +1313,9 @@ static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, } static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev, - u32 me, u32 pipe, u32 q) + u32 me, u32 pipe, u32 q, u32 vm) { - soc15_grbm_select(adev, me, pipe, q, 0); + soc15_grbm_select(adev, me, pipe, q, vm); } static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { -- cgit v1.2.3 From ca9db7d1e07237db81c81518d52241d33d72298f Mon Sep 17 00:00:00 2001 From: Tom St Denis Date: Fri, 12 Jul 2019 09:41:32 -0400 Subject: drm/amd/amdgpu: Add missing select_me_pipe_q() for gfx10 The ability to select GFX GRBM me/pipe/queue/vmid was missing from the gfx10 driver. This patch adds it. Used by the debugfs register interface to select GFX resources when read/writing registers. Signed-off-by: Tom St Denis Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index ee41d5592c51..435678933d86 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -995,6 +995,12 @@ static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, start + SQIND_WAVE_VGPRS_OFFSET, size, dst); } +static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, + u32 me, u32 pipe, u32 q, u32 vm) + { + nv_grbm_select(adev, me, pipe, q, vm); + } + static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, @@ -1002,6 +1008,7 @@ static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { .read_wave_data = &gfx_v10_0_read_wave_data, .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, + .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, }; static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) -- cgit v1.2.3 From 9417f703afe3bf4e9c87342fb191d113ee83a818 Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Mon, 15 Jul 2019 08:53:06 -0400 Subject: drm/amdgpu: Fix Vega20 Perf counter for pcie_bw The perf counter for Vega20 is 108, instead of 104 which it was on all previous GPUs, so add a check to use the appropriate value. Signed-off-by: Kent Russell Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 87152d8ef0df..5b8f5d9fc3c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -717,9 +717,15 @@ static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, return; /* Set the 2 events that we wish to watch, defined above */ - /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */ + /* Reg 40 is # received msgs */ perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); - perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); + /* Pre-VG20, Reg 104 is # of posted requests sent. On VG20 it's 108 */ + if (adev->asic_type == CHIP_VEGA20) + perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, + EVENT1_SEL, 108); + else + perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, + EVENT1_SEL, 104); /* Write to enable desired perf counters */ WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); -- cgit v1.2.3 From b5203d16aef462f52df47242178718768038319a Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 12 Jul 2019 11:40:49 +0200 Subject: drm/amd/amdgpu: hide #warning for missing DC config It is annoying to have #warnings that trigger in randconfig builds like drivers/gpu/drm/amd/amdgpu/soc15.c:653:3: error: "Enable CONFIG_DRM_AMD_DC for display support on SOC15." drivers/gpu/drm/amd/amdgpu/nv.c:400:3: error: "Enable CONFIG_DRM_AMD_DC for display support on navi." Remove these and rely on the users to turn these on. Signed-off-by: Arnd Bergmann Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nv.c | 2 -- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ---- 2 files changed, 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index ad430cbcd72f..662612f89c70 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -392,8 +392,6 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) #if defined(CONFIG_DRM_AMD_DC) else if (amdgpu_device_has_dc_support(adev)) amdgpu_device_ip_block_add(adev, &dm_ip_block); -#else -# warning "Enable CONFIG_DRM_AMD_DC for display support on navi." #endif amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 5b8f5d9fc3c0..23265414d448 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -649,8 +649,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) #if defined(CONFIG_DRM_AMD_DC) else if (amdgpu_device_has_dc_support(adev)) amdgpu_device_ip_block_add(adev, &dm_ip_block); -#else -# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15." #endif if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); @@ -671,8 +669,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) #if defined(CONFIG_DRM_AMD_DC) else if (amdgpu_device_has_dc_support(adev)) amdgpu_device_ip_block_add(adev, &dm_ip_block); -#else -# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15." #endif amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); break; -- cgit v1.2.3 From 5db7b0d29086b621e294d5c52bb3ff25283cff60 Mon Sep 17 00:00:00 2001 From: Fuqian Huang Date: Mon, 15 Jul 2019 11:17:31 +0800 Subject: drm/amdgpu: remove memset after kzalloc kzalloc has already zeroed the memory during the allocation. So memset is unneeded. Reviewed-by: Emil Velikov Signed-off-by: Fuqian Huang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c | 2 -- drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 2 -- drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 2 -- drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 2 -- 4 files changed, 8 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c index 1cd5a8b5cdc1..b760f95e7fa7 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c @@ -1067,8 +1067,6 @@ static int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE((NULL != hwmgr->pptable), "Failed to allocate hwmgr->pptable!", return -ENOMEM); - memset(hwmgr->pptable, 0x00, sizeof(struct phm_ppt_v1_information)); - powerplay_table = get_powerplay_table(hwmgr); PP_ASSERT_WITH_CODE((NULL != powerplay_table), diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c index 6c81cb91ebae..15590fd86ef4 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c @@ -2705,8 +2705,6 @@ static int ci_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2)); cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2)); - memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table)); - result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table); if (0 == result) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c index 9e0dd56fe7c5..732005c03a82 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c @@ -2634,8 +2634,6 @@ static int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2)); cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2)); - memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table)); - result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table); if (0 == result) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c index ba3394303b9c..f19bac7ef7ba 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c @@ -3117,8 +3117,6 @@ static int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2)); - memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table)); - result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table); if (!result) -- cgit v1.2.3 From 3bd532692d93a9c72f4f11e38437b30c0e13007f Mon Sep 17 00:00:00 2001 From: Wang Xiayang Date: Mon, 15 Jul 2019 16:53:01 +0800 Subject: drm/amdgpu: replace simple_strtol() by kstrtou32() The simple_strtol() function is deprecated. kstrto[l,u32]() is the correct replacement as it can properly handle overflows. This patch replaces the deprecated simple_strtol() use introduced recently. As clk is of type uint32_t, we are safe to use kstrtou32(). It is also safe to return zero on string parsing error, similar to the case of returning zero if buf is empty in parse_clk(). Fixes: bb5a2bdf36a8 ("drm/amdgpu: support dpm level modification under virtualization v3") Signed-off-by: Wang Xiayang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 07a7e3820b7b..59dd204498c5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -390,7 +390,8 @@ static uint32_t parse_clk(char *buf, bool min) if (!ptr) break; ptr+=2; - clk = simple_strtoul(ptr, NULL, 10); + if (kstrtou32(ptr, 10, &clk)) + return 0; } while (!min); return clk * 100; -- cgit v1.2.3 From 9288b874c5006a22d1fbff303b812cb03241cdfb Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Sat, 13 Jul 2019 02:35:37 -0400 Subject: drm/amdgpu: Fix unaligned memory copies MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When starting a new mm_node, the page_offset becomes 0. Signed-off-by: Felix Kuehling Reviewed-by: Alex Deucher Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 8462934d23ea..9892f13bcbc0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -391,6 +391,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm, src->mem); src_node_size = (src_mm->size << PAGE_SHIFT); + src_page_offset = 0; } else { src_node_start += cur_size; src_page_offset = src_node_start & (PAGE_SIZE - 1); @@ -400,6 +401,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm, dst->mem); dst_node_size = (dst_mm->size << PAGE_SHIFT); + dst_page_offset = 0; } else { dst_node_start += cur_size; dst_page_offset = dst_node_start & (PAGE_SIZE - 1); -- cgit v1.2.3 From f216994613bc9f44202eac3a298e52124eb3e35e Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Tue, 16 Jul 2019 13:48:19 +0800 Subject: drm/amdgpu: check kdb_bin_size to exclude kdb loading sequence The legacy navi10 sos binary will not carry on kdb image. the kdb_start_addr is actually the start address of sys_drv image and shouldn't be sent to psp bootloader. Signed-off-by: Hawking Zhang Reviewed-by: John Clements Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index c5b7049cc01d..c027e5e7713e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -769,7 +769,7 @@ static int psp_hw_start(struct psp_context *psp) int ret; if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) { - if (psp->kdb_start_addr && + if (psp->kdb_bin_size && (psp->funcs->bootloader_load_kdb != NULL)) { ret = psp_bootloader_load_kdb(psp); if (ret) { -- cgit v1.2.3 From 597292eb73eefe4e48f9f72640955813d59b733a Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Tue, 16 Jul 2019 15:01:31 +0800 Subject: drm/amd/powerplay: enable fw ctf,apcc dfll and gfx ss enable fw ctf, apcc dfll and gfx ss on navi10. fw ctf: when the fw ctf is triggered, the gfx and soc power domain are shut down. fan speed is boosted to the maximum. gfx ss: hardware feature, sanity check has been done. apcc dfll: can check the scoreboard in smu fw to confirm if it's enabled. no need to do further check since the gfx hardware control the frequency once a pcc signal comes. Signed-off-by: Kenneth Feng Reviewed-by: Evan Quan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index 3e5d5f359c11..7f11c641b7b8 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -331,7 +331,10 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) | FEATURE_MASK(FEATURE_BACO_BIT) - | FEATURE_MASK(FEATURE_ACDC_BIT); + | FEATURE_MASK(FEATURE_ACDC_BIT) + | FEATURE_MASK(FEATURE_GFX_SS_BIT) + | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) + | FEATURE_MASK(FEATURE_FW_CTF_BIT); if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) @@ -339,8 +342,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); if (adev->pm.pp_feature & PP_GFXOFF_MASK) { - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_SS_BIT) - | FEATURE_MASK(FEATURE_GFXOFF_BIT); + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); /* TODO: remove it once fw fix the bug */ *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_FW_DSTATE_BIT); } @@ -465,9 +467,6 @@ static int navi10_append_powerplay_table(struct smu_context *smu) smc_pptable->MvddRatio = smc_dpm_table->MvddRatio; if (adev->pm.pp_feature & PP_GFXOFF_MASK) { - *(uint64_t *)smc_pptable->FeaturesToRun |= FEATURE_MASK(FEATURE_GFX_SS_BIT) - | FEATURE_MASK(FEATURE_GFXOFF_BIT); - /* TODO: remove it once SMU fw fix it */ smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN; } -- cgit v1.2.3 From 08473888e09b0136ceb4d65784b02b537d977a2a Mon Sep 17 00:00:00 2001 From: Nicolai Hähnle Date: Tue, 16 Jul 2019 13:11:22 -0500 Subject: drm/amdgpu/gfx10: set SH_MEM_CONFIG.INITIAL_INST_PREFETCH MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Prefetch mode 0 is not supported and can lead to hangs with certain very specific code patterns. Set a sound prefetch mode for all VMIDs rather than forcing all shaders to set the prefetch mode at the beginning. Reduce code duplication a bit while we're at it. Note that the 64-bit address mode enum and the retry all enum are both 0, so the only functional change is in the INITIAL_INST_PREFETCH field. Signed-off-by: Nicolai Hähnle Reviewed-by: Marek Olšák Acked-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 27 ++++++++++----------------- 1 file changed, 10 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 435678933d86..1675d5837c3c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -109,6 +109,13 @@ static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = /* Pending on emulation bring up */ }; +#define DEFAULT_SH_MEM_CONFIG \ + ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ + (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ + (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ + (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) + + static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); @@ -1415,7 +1422,6 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) { int i; - uint32_t sh_mem_config; uint32_t sh_mem_bases; /* @@ -1426,15 +1432,11 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) */ sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); - sh_mem_config = SH_MEM_ADDRESS_MODE_64 | - SH_MEM_ALIGNMENT_MODE_UNALIGNED << - SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; - mutex_lock(&adev->srbm_mutex); for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { nv_grbm_select(adev, 0, 0, 0, i); /* CP and shaders */ - WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); + WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); } nv_grbm_select(adev, 0, 0, 0, 0); @@ -1527,17 +1529,8 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev) for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) { nv_grbm_select(adev, 0, 0, 0, i); /* CP and shaders */ - if (i == 0) { - tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, - SH_MEM_ALIGNMENT_MODE_UNALIGNED); - tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_MODE, 0); - WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); - WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0); - } else { - tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, - SH_MEM_ALIGNMENT_MODE_UNALIGNED); - tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_MODE, 0); - WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); + WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); + if (i != 0) { tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, (adev->gmc.private_aperture_start >> 48)); tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, -- cgit v1.2.3 From d72e04d97efdd518514018bf96169bf68922eed6 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Wed, 3 Jul 2019 22:52:17 -0700 Subject: drm/amd/powerplay: Use proper enums in vega20_print_clk_levels clang warns: drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:995:39: warning: implicit conversion from enumeration type 'PPCLK_e' to different enumeration type 'enum smu_clk_type' [-Wenum-conversion] ret = smu_get_current_clk_freq(smu, PPCLK_SOCCLK, &now); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:1016:39: warning: implicit conversion from enumeration type 'PPCLK_e' to different enumeration type 'enum smu_clk_type' [-Wenum-conversion] ret = smu_get_current_clk_freq(smu, PPCLK_FCLK, &now); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:1031:39: warning: implicit conversion from enumeration type 'PPCLK_e' to different enumeration type 'enum smu_clk_type' [-Wenum-conversion] ret = smu_get_current_clk_freq(smu, PPCLK_DCEFCLK, &now); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~ The values are mapped one to one in vega20_get_smu_clk_index so just use the proper enums here. Fixes: 096761014227 ("drm/amd/powerplay: support sysfs to get socclk, fclk, dcefclk") Link: https://github.com/ClangBuiltLinux/linux/issues/587 Reviewed-by: Evan Quan Signed-off-by: Nathan Chancellor Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c index a76a22a18eb4..9204e4e50d09 100644 --- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c @@ -992,7 +992,7 @@ static int vega20_print_clk_levels(struct smu_context *smu, break; case SMU_SOCCLK: - ret = smu_get_current_clk_freq(smu, PPCLK_SOCCLK, &now); + ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now); if (ret) { pr_err("Attempt to get current socclk Failed!"); return ret; @@ -1013,7 +1013,7 @@ static int vega20_print_clk_levels(struct smu_context *smu, break; case SMU_FCLK: - ret = smu_get_current_clk_freq(smu, PPCLK_FCLK, &now); + ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now); if (ret) { pr_err("Attempt to get current fclk Failed!"); return ret; @@ -1028,7 +1028,7 @@ static int vega20_print_clk_levels(struct smu_context *smu, break; case SMU_DCEFCLK: - ret = smu_get_current_clk_freq(smu, PPCLK_DCEFCLK, &now); + ret = smu_get_current_clk_freq(smu, SMU_DCEFCLK, &now); if (ret) { pr_err("Attempt to get current dcefclk Failed!"); return ret; -- cgit v1.2.3 From 6ea624f60393edc114feb33fa738d6f2f47e9032 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 16 Jul 2019 09:28:41 -0500 Subject: drm/amdgpu: drop dead header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not used anymore. Reviewed-by: Evan Quan Acked-by: Christian König Noticed-by: Dave Airlie Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vi.c | 1 - drivers/gpu/drm/amd/amdgpu/vi_dpm.h | 32 -------------------------------- 2 files changed, 33 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdgpu/vi_dpm.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index d40ed1a828dd..6575ddcfcf00 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -59,7 +59,6 @@ #include "vid.h" #include "vi.h" -#include "vi_dpm.h" #include "gmc_v8_0.h" #include "gmc_v7_0.h" #include "gfx_v8_0.h" diff --git a/drivers/gpu/drm/amd/amdgpu/vi_dpm.h b/drivers/gpu/drm/amd/amdgpu/vi_dpm.h deleted file mode 100644 index c43e03fddfba..000000000000 --- a/drivers/gpu/drm/amd/amdgpu/vi_dpm.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef __VI_DPM_H__ -#define __VI_DPM_H__ - -extern const struct amd_ip_funcs cz_dpm_ip_funcs; -int cz_smu_init(struct amdgpu_device *adev); -int cz_smu_start(struct amdgpu_device *adev); -int cz_smu_fini(struct amdgpu_device *adev); - -#endif -- cgit v1.2.3 From 67adb569ddf4aee12de999e02c67c1a168dd1a15 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Sat, 13 Jul 2019 02:27:34 -0400 Subject: drm/amdgpu: Fix silent amdgpu_bo_move failures MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Under memory pressure, buffer moves between RAM to VRAM can fail when there is no GTT space available. In those cases amdgpu_bo_move falls back to ttm_bo_move_memcpy, which seems to succeed, although it doesn't really support non-contiguous or invisible VRAM. This manifests as VM faults with corrupted page table entries in KFD eviction stress tests. Print some helpful messages when lack of GTT space is causing buffer moves to fail. Check that source and destination memory regions are supported by ttm_bo_move_memcpy before taking that fallback. Signed-off-by: Felix Kuehling Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 40 ++++++++++++++++++++++++++++++--- 1 file changed, 37 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 9892f13bcbc0..2bb9420b77a1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -489,6 +489,7 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict, placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); if (unlikely(r)) { + pr_err("Failed to find GTT space for blit from VRAM\n"); return r; } @@ -547,6 +548,7 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict, placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); if (unlikely(r)) { + pr_err("Failed to find GTT space for blit to VRAM\n"); return r; } @@ -566,6 +568,30 @@ out_cleanup: return r; } +/** + * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy + * + * Called by amdgpu_bo_move() + */ +static bool amdgpu_mem_visible(struct amdgpu_device *adev, + struct ttm_mem_reg *mem) +{ + struct drm_mm_node *nodes = mem->mm_node; + + if (mem->mem_type == TTM_PL_SYSTEM || + mem->mem_type == TTM_PL_TT) + return true; + if (mem->mem_type != TTM_PL_VRAM) + return false; + + /* ttm_mem_reg_ioremap only supports contiguous memory */ + if (nodes->size != mem->num_pages) + return false; + + return ((nodes->start + nodes->size) << PAGE_SHIFT) + <= adev->gmc.visible_vram_size; +} + /** * amdgpu_bo_move - Move a buffer object to a new memory location * @@ -610,8 +636,10 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, return 0; } - if (!adev->mman.buffer_funcs_enabled) + if (!adev->mman.buffer_funcs_enabled) { + r = -ENODEV; goto memcpy; + } if (old_mem->mem_type == TTM_PL_VRAM && new_mem->mem_type == TTM_PL_SYSTEM) { @@ -626,10 +654,16 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, if (r) { memcpy: - r = ttm_bo_move_memcpy(bo, ctx, new_mem); - if (r) { + /* Check that all memory is CPU accessible */ + if (!amdgpu_mem_visible(adev, old_mem) || + !amdgpu_mem_visible(adev, new_mem)) { + pr_err("Move buffer fallback to memcpy unavailable\n"); return r; } + + r = ttm_bo_move_memcpy(bo, ctx, new_mem); + if (r) + return r; } if (bo->type == ttm_bo_type_device && -- cgit v1.2.3 From 366cf03ec00f18e802f304c2cc057cac842e1244 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Fri, 12 Jul 2019 10:07:31 +0800 Subject: drm/amd/powerplay: fix memory allocation failure check V2 Fix memory allocation failure check. - V2: fix one more similar error Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c index 9204e4e50d09..3c605257b89c 100644 --- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c @@ -319,7 +319,7 @@ static int vega20_tables_init(struct smu_context *smu, struct smu_table *tables) AMDGPU_GEM_DOMAIN_VRAM); smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); - if (smu_table->metrics_table) + if (!smu_table->metrics_table) return -ENOMEM; smu_table->metrics_time = 0; @@ -1502,7 +1502,7 @@ static int vega20_set_default_od8_setttings(struct smu_context *smu) od8_settings = kzalloc(sizeof(struct vega20_od8_settings), GFP_KERNEL); - if (od8_settings) + if (!od8_settings) return -ENOMEM; smu->od_settings = (void *)od8_settings; -- cgit v1.2.3 From 7ef65bbd01fd59b749e8bd5b19d0c01e315fef8d Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Fri, 12 Jul 2019 10:32:02 +0800 Subject: drm/amd/powerplay: avoid access before allocation No access before allocation. Signed-off-by: Evan Quan Reviewed-by: Feifei Xu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c index 3c605257b89c..6d267aeacda3 100644 --- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c @@ -441,7 +441,6 @@ static int vega20_store_powerplay_table(struct smu_context *smu) { ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL; struct smu_table_context *table_context = &smu->smu_table; - int ret; if (!table_context->power_play_table) return -EINVAL; @@ -455,9 +454,7 @@ static int vega20_store_powerplay_table(struct smu_context *smu) table_context->thermal_controller_type = powerplay_table->ucThermalControllerType; table_context->TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]); - ret = vega20_setup_od8_information(smu); - - return ret; + return 0; } static int vega20_append_powerplay_table(struct smu_context *smu) @@ -1507,6 +1504,12 @@ static int vega20_set_default_od8_setttings(struct smu_context *smu) smu->od_settings = (void *)od8_settings; + ret = vega20_setup_od8_information(smu); + if (ret) { + pr_err("Retrieve board OD limits failed!\n"); + return ret; + } + if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] && od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 && -- cgit v1.2.3 From f68ccf43acbc31751cff48d0ac1e5ff50d91a451 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Fri, 12 Jul 2019 13:18:16 +0800 Subject: drm/amd/powerplay: fix deadlock around smu_handle_task V2 As the lock was already held on the entrance to smu_handle_task. - V2: lock in small granularity Signed-off-by: Evan Quan Reviewed-by: Kevin Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 193d53720d9b..397af9094a39 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -2996,13 +2996,10 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) } if (is_support_sw_smu(adev)) { - struct smu_context *smu = &adev->smu; struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm; - mutex_lock(&(smu->mutex)); smu_handle_task(&adev->smu, smu_dpm->dpm_level, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE); - mutex_unlock(&(smu->mutex)); } else { if (adev->powerplay.pp_funcs->dispatch_tasks) { if (!amdgpu_device_has_dc_support(adev)) { -- cgit v1.2.3 From 0d9d78b57bf32fdc4baf6eb8853e65059dcd5e06 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Thu, 11 Jul 2019 15:13:17 +0800 Subject: drm/amd/powerplay: correct smu_update_table usage The interface was used in a confusing way. In profile mode scenario, the 2nd parameter of the interface was used in a different way from other scenarios. Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++-- drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 +- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 16 ++++++++-------- drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 4 ++-- drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 20 ++++++++++---------- 5 files changed, 23 insertions(+), 23 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index 20257c036a65..f1565c448de5 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -323,7 +323,7 @@ int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor, return ret; } -int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, +int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument, void *table_data, bool drv2smu) { struct smu_table_context *smu_table = &smu->smu_table; @@ -350,7 +350,7 @@ int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, ret = smu_send_smc_msg_with_param(smu, drv2smu ? SMU_MSG_TransferTableDram2Smu : SMU_MSG_TransferTableSmu2Dram, - table_id); + table_id | ((argument & 0xFFFF) << 16)); if (ret) return ret; diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h index 135a3236f7ed..1af992fb0bde 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h @@ -937,7 +937,7 @@ extern int smu_feature_is_supported(struct smu_context *smu, extern int smu_feature_set_supported(struct smu_context *smu, enum smu_feature_mask mask, bool enable); -int smu_update_table(struct smu_context *smu, uint32_t table_index, +int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument, void *table_data, bool drv2smu); bool is_support_sw_smu(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index 7f11c641b7b8..2dae0ae0829e 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -613,7 +613,7 @@ static int navi10_get_current_clk_freq_by_table(struct smu_context *smu, memset(&metrics, 0, sizeof(metrics)); - ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics, false); + ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false); if (ret) return ret; @@ -866,7 +866,7 @@ static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value) if (!value) return -EINVAL; - ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics, + ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false); if (ret) return ret; @@ -888,7 +888,7 @@ static int navi10_get_current_activity_percent(struct smu_context *smu, msleep(1); - ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, + ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false); if (ret) return ret; @@ -929,7 +929,7 @@ static int navi10_get_fan_speed(struct smu_context *smu, uint16_t *value) memset(&metrics, 0, sizeof(metrics)); - ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, + ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false); if (ret) return ret; @@ -995,7 +995,7 @@ static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf) /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ workload_type = smu_workload_get_type(smu, i); result = smu_update_table(smu, - SMU_TABLE_ACTIVITY_MONITOR_COEFF | workload_type << 16, + SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, (void *)(&activity_monitor), false); if (result) { pr_err("[%s] Failed to get activity monitor!", __func__); @@ -1068,7 +1068,7 @@ static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, u return -EINVAL; ret = smu_update_table(smu, - SMU_TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16, + SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, (void *)(&activity_monitor), false); if (ret) { pr_err("[%s] Failed to get activity monitor!", __func__); @@ -1112,7 +1112,7 @@ static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, u } ret = smu_update_table(smu, - SMU_TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16, + SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, (void *)(&activity_monitor), true); if (ret) { pr_err("[%s] Failed to set activity monitor!", __func__); @@ -1278,7 +1278,7 @@ static int navi10_thermal_get_temperature(struct smu_context *smu, if (!value) return -EINVAL; - ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics, false); + ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false); if (ret) return ret; diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c index a87b86ae2cc5..f182d75e127d 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c @@ -703,7 +703,7 @@ static int smu_v11_0_write_pptable(struct smu_context *smu) struct smu_table_context *table_context = &smu->smu_table; int ret = 0; - ret = smu_update_table(smu, SMU_TABLE_PPTABLE, + ret = smu_update_table(smu, SMU_TABLE_PPTABLE, 0, table_context->driver_pptable, true); return ret; @@ -722,7 +722,7 @@ static int smu_v11_0_write_watermarks_table(struct smu_context *smu) if (!table->cpu_addr) return -EINVAL; - ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, table->cpu_addr, + ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr, true); return ret; diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c index 6d267aeacda3..bb9bb09cfc7a 100644 --- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c @@ -1680,7 +1680,7 @@ static int vega20_get_metrics_table(struct smu_context *smu, int ret = 0; if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) { - ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, + ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)smu_table->metrics_table, false); if (ret) { pr_info("Failed to export SMU metrics table!\n"); @@ -1709,7 +1709,7 @@ static int vega20_set_default_od_settings(struct smu_context *smu, if (!table_context->overdrive_table) return -ENOMEM; - ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, + ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false); if (ret) { pr_err("Failed to export over drive table!\n"); @@ -1721,7 +1721,7 @@ static int vega20_set_default_od_settings(struct smu_context *smu, return ret; } - ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, + ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true); if (ret) { pr_err("Failed to import over drive table!\n"); @@ -1805,7 +1805,7 @@ static int vega20_get_power_profile_mode(struct smu_context *smu, char *buf) /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ workload_type = smu_workload_get_type(smu, i); result = smu_update_table(smu, - SMU_TABLE_ACTIVITY_MONITOR_COEFF | workload_type << 16, + SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, (void *)(&activity_monitor), false); if (result) { pr_err("[%s] Failed to get activity monitor!", __func__); @@ -1891,7 +1891,7 @@ static int vega20_set_power_profile_mode(struct smu_context *smu, long *input, u if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { ret = smu_update_table(smu, - SMU_TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16, + SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, (void *)(&activity_monitor), false); if (ret) { pr_err("[%s] Failed to get activity monitor!", __func__); @@ -1946,7 +1946,7 @@ static int vega20_set_power_profile_mode(struct smu_context *smu, long *input, u } ret = smu_update_table(smu, - SMU_TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16, + SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, (void *)(&activity_monitor), true); if (ret) { pr_err("[%s] Failed to set activity monitor!", __func__); @@ -2495,7 +2495,7 @@ static int vega20_update_od8_settings(struct smu_context *smu, struct smu_table_context *table_context = &smu->smu_table; int ret; - ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, + ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false); if (ret) { pr_err("Failed to export over drive table!\n"); @@ -2506,7 +2506,7 @@ static int vega20_update_od8_settings(struct smu_context *smu, if (ret) return ret; - ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, + ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true); if (ret) { pr_err("Failed to import over drive table!\n"); @@ -2770,7 +2770,7 @@ static int vega20_odn_edit_dpm_table(struct smu_context *smu, break; case PP_OD_RESTORE_DEFAULT_TABLE: - ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, table_context->overdrive_table, false); + ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false); if (ret) { pr_err("Failed to export over drive table!\n"); return ret; @@ -2779,7 +2779,7 @@ static int vega20_odn_edit_dpm_table(struct smu_context *smu, break; case PP_OD_COMMIT_DPM_TABLE: - ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, table_context->overdrive_table, true); + ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true); if (ret) { pr_err("Failed to import over drive table!\n"); return ret; -- cgit v1.2.3 From 93002849ffc7d1f12db60a37c30610d02844363b Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Tue, 16 Jul 2019 14:20:22 +0800 Subject: drm/amd/powerplay: maintain SMU FW backward compatibility Do not halt driver loading on if_version mismatch. As our driver and FWs are backward compatible. Signed-off-by: Evan Quan Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c index f182d75e127d..95c7c4dae523 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c @@ -261,14 +261,20 @@ static int smu_v11_0_check_fw_version(struct smu_context *smu) smu_minor = (smu_version >> 8) & 0xff; smu_debug = (smu_version >> 0) & 0xff; - + /* + * 1. if_version mismatch is not critical as our fw is designed + * to be backward compatible. + * 2. New fw usually brings some optimizations. But that's visible + * only on the paired driver. + * Considering above, we just leave user a warning message instead + * of halt driver loading. + */ if (if_version != smu->smc_if_version) { pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, " "smu fw version = 0x%08x (%d.%d.%d)\n", smu->smc_if_version, if_version, smu_version, smu_major, smu_minor, smu_debug); - pr_err("SMU driver if version not matched\n"); - ret = -EINVAL; + pr_warn("SMU driver if version not matched\n"); } return ret; -- cgit v1.2.3 From cd6e0c4ba19375ec5a7bcb959015d5f90eef0a1c Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Fri, 12 Jul 2019 10:53:11 +0800 Subject: drm/amd/powerplay: update vega20 driver if to fit latest SMU firmware Optimization for the socket power calculation is introduced. Signed-off-by: Evan Quan Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h index 195c4ae67058..755d51f9c6a9 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h @@ -27,7 +27,7 @@ // *** IMPORTANT *** // SMU TEAM: Always increment the interface version if // any structure is changed in this file -#define SMU11_DRIVER_IF_VERSION 0x12 +#define SMU11_DRIVER_IF_VERSION 0x13 #define PPTABLE_V20_SMU_VERSION 3 @@ -615,6 +615,7 @@ typedef struct { uint16_t UclkAverageLpfTau; uint16_t GfxActivityLpfTau; uint16_t UclkActivityLpfTau; + uint16_t SocketPowerLpfTau; uint32_t MmHubPadding[8]; @@ -665,7 +666,8 @@ typedef struct { uint32_t ThrottlerStatus ; uint8_t LinkDpmLevel; - uint8_t Padding[3]; + uint16_t AverageSocketPower; + uint8_t Padding; uint32_t MmHubPadding[7]; -- cgit v1.2.3 From 88891430a2c06b6be9b1ed08c095befb17fb4cb2 Mon Sep 17 00:00:00 2001 From: Tom St Denis Date: Tue, 16 Jul 2019 07:23:22 -0400 Subject: drm/amd/amdgpu: Fix offset for vmid selection in debugfs interface MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The register debugfs interface was using the wrong bitmask for vmid selection for GFX_CNTL. Signed-off-by: Tom St Denis Acked-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index c40abf819f3d..6d54decef7f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -135,7 +135,7 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct file *f, me = (*pos & GENMASK_ULL(33, 24)) >> 24; pipe = (*pos & GENMASK_ULL(43, 34)) >> 34; queue = (*pos & GENMASK_ULL(53, 44)) >> 44; - vmid = (*pos & GENMASK_ULL(48, 45)) >> 54; + vmid = (*pos & GENMASK_ULL(58, 54)) >> 54; use_ring = 1; } else { -- cgit v1.2.3 From 6a5d4877544b9014c70533200ad4a5f9d6e005c5 Mon Sep 17 00:00:00 2001 From: Joseph Greathouse Date: Wed, 17 Jul 2019 09:47:58 -0500 Subject: drm/amdkfd: Remove GWS from process during uninit If we shut down a process without having destroyed its GWS-using queues, it is possible that GWS BO will still be in the process BO list during the gpuvm destruction. This list should be empty at that time, so we should remove the GWS allocation at the process uninit point if it is still around. Signed-off-by: Joseph Greathouse Acked-by: Alex Deucher Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index da0958625861..7e6c3ee82f5b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -150,6 +150,9 @@ void pqm_uninit(struct process_queue_manager *pqm) struct process_queue_node *pqn, *next; list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) { + if (pqn->q && pqn->q->gws) + amdgpu_amdkfd_remove_gws_from_process(pqm->process->kgd_process_info, + pqn->q->gws); uninit_queue(pqn->q); list_del(&pqn->process_queue_list); kfree(pqn); -- cgit v1.2.3 From 02316e963a5a2217aa13f64bb5fc37a3a6d0f5ef Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Fri, 5 Jul 2019 16:54:28 -0400 Subject: drm/amd/display: Force uclk to max for every state Workaround for now to avoid underflow. The uclk switch time should really be bumped up to 404, but doing so would expose p-state hang issues for higher bandwidth display configurations. Signed-off-by: Nicholas Kazlauskas Signed-off-by: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 6 +++--- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 10 ++++++++++ 2 files changed, 13 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c index 086a3bf83226..592fa499c9f8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c @@ -911,11 +911,11 @@ void dm_pp_get_funcs( /* todo set_pme_wa_enable cause 4k@6ohz display not light up */ funcs->nv_funcs.set_pme_wa_enable = NULL; /* todo debug waring message */ - funcs->nv_funcs.set_hard_min_uclk_by_freq = NULL; + funcs->nv_funcs.set_hard_min_uclk_by_freq = pp_nv_set_hard_min_uclk_by_freq; /* todo compare data with window driver*/ - funcs->nv_funcs.get_maximum_sustainable_clocks = NULL; + funcs->nv_funcs.get_maximum_sustainable_clocks = pp_nv_get_maximum_sustainable_clocks; /*todo compare data with window driver */ - funcs->nv_funcs.get_uclk_dpm_states = NULL; + funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states; break; #endif default: diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index 3ad609276b2e..d200bc3cec71 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -2576,6 +2576,9 @@ static void cap_soc_clocks( && max_clocks.uClockInKhz != 0) bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16; + // HACK: Force every uclk to max for now to "disable" uclk switching. + bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16; + if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000)) && max_clocks.fabricClockInKhz != 0) bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000); @@ -2783,6 +2786,8 @@ static bool init_soc_bounding_box(struct dc *dc, le32_to_cpu(bb->vmm_page_size_bytes); dcn2_0_soc.dram_clock_change_latency_us = fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us); + // HACK!! Lower uclock latency switch time so we don't switch + dcn2_0_soc.dram_clock_change_latency_us = 10; dcn2_0_soc.writeback_dram_clock_change_latency_us = fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us); dcn2_0_soc.return_bus_width_bytes = @@ -2824,6 +2829,7 @@ static bool init_soc_bounding_box(struct dc *dc, struct pp_smu_nv_clock_table max_clocks = {0}; unsigned int uclk_states[8] = {0}; unsigned int num_states = 0; + int i; enum pp_smu_status status; bool clock_limits_available = false; bool uclk_states_available = false; @@ -2845,6 +2851,10 @@ static bool init_soc_bounding_box(struct dc *dc, clock_limits_available = (status == PP_SMU_RESULT_OK); } + // HACK: Use the max uclk_states value for all elements. + for (i = 0; i < num_states; i++) + uclk_states[i] = uclk_states[num_states - 1]; + if (clock_limits_available && uclk_states_available && num_states) update_bounding_box(dc, &dcn2_0_soc, &max_clocks, uclk_states, num_states); else if (clock_limits_available) -- cgit v1.2.3 From 8a5b5d425e5454fdef0e5457826f4aa7f96cf463 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 17 Jul 2019 13:10:39 -0500 Subject: drm/amdgpu/pm: remove check for pp funcs in freq sysfs handlers The dpm sensor function already does this for us. This fixes the freq*_input files with the new SMU implementation. Reviewed-by: Evan Quan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 397af9094a39..8b7efd0a7028 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -2077,11 +2077,6 @@ static ssize_t amdgpu_hwmon_show_sclk(struct device *dev, (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) return -EINVAL; - /* sanity check PP is enabled */ - if (!(adev->powerplay.pp_funcs && - adev->powerplay.pp_funcs->read_sensor)) - return -EINVAL; - /* get the sclk */ r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&sclk, &size); @@ -2112,11 +2107,6 @@ static ssize_t amdgpu_hwmon_show_mclk(struct device *dev, (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) return -EINVAL; - /* sanity check PP is enabled */ - if (!(adev->powerplay.pp_funcs && - adev->powerplay.pp_funcs->read_sensor)) - return -EINVAL; - /* get the sclk */ r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&mclk, &size); -- cgit v1.2.3 From 41a5a2a8531f95d18bb4efddea581ccb469e8ee5 Mon Sep 17 00:00:00 2001 From: hersen wu Date: Wed, 26 Jun 2019 13:06:07 -0400 Subject: drm/amd/display: init res_pool dccg_ref, dchub_ref with xtalin_freq [WHY] dc sw clock implementation of navi10 and raven are not exact the same. dcccg, dchub reference clock initialization is done after dc calls vbios dispcontroller_init table. for raven family, before dispcontroller_init is called by dc, the ref clk values are referred by sw clock implementation and program asic register using wrong values. this causes dchub pstate error. This need provide valid ref clk values. for navi10, since dispcontroller_init is not called, dchubbub_global_timer_enable = 0, hubbub2_get_dchub_ref_freq will hit aeert. this need remove hubbub2_get_dchub_ref_freq from this location and move to dcn20_init_hw. [HOW] for all asic, initialize dccg, dchub ref clk with data from vbios firmware table by default. for raven asic family, use these data from vbios, for asic which support sw dccg component, like navi10, read ref clk by sw dccg functions and update the ref clk. Signed-off-by: hersen wu Reviewed-by: Jun Lei Acked-by: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 42 +++++++++------------- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 25 +++++++++++++ 2 files changed, 41 insertions(+), 26 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 48dfb305a0b0..51a78283a86d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -175,32 +175,22 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, if (res_pool != NULL) { struct dc_firmware_info fw_info = { { 0 } }; - if (dc->ctx->dc_bios->funcs->get_firmware_info( - dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) { - res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency; - - if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { - // On FPGA these dividers are currently not configured by GDB - res_pool->ref_clocks.dccg_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz; - res_pool->ref_clocks.dchub_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz; - } else if (res_pool->dccg && res_pool->hubbub) { - // If DCCG reference frequency cannot be determined (usually means not set to xtalin) then this is a critical error - // as this value must be known for DCHUB programming - (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, - fw_info.pll_info.crystal_frequency, - &res_pool->ref_clocks.dccg_ref_clock_inKhz); - - // Similarly, if DCHUB reference frequency cannot be determined, then it is also a critical error - (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, - res_pool->ref_clocks.dccg_ref_clock_inKhz, - &res_pool->ref_clocks.dchub_ref_clock_inKhz); - } else { - // Not all ASICs have DCCG sw component - res_pool->ref_clocks.dccg_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz; - res_pool->ref_clocks.dchub_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz; - } - } else - ASSERT_CRITICAL(false); + if (dc->ctx->dc_bios->funcs->get_firmware_info(dc->ctx->dc_bios, + &fw_info) == BP_RESULT_OK) { + res_pool->ref_clocks.xtalin_clock_inKhz = + fw_info.pll_info.crystal_frequency; + /* initialize with firmware data first, no all + * ASIC have DCCG SW component. FPGA or + * simulation need initialization of + * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz + * with xtalin_clock_inKhz + */ + res_pool->ref_clocks.dccg_ref_clock_inKhz = + res_pool->ref_clocks.xtalin_clock_inKhz; + res_pool->ref_clocks.dchub_ref_clock_inKhz = + res_pool->ref_clocks.xtalin_clock_inKhz; + } else + ASSERT_CRITICAL(false); } return res_pool; diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 6925d25d2457..0b84a322b8a2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -523,6 +523,7 @@ static void dcn20_init_hw(struct dc *dc) struct dc_bios *dcb = dc->ctx->dc_bios; struct resource_pool *res_pool = dc->res_pool; struct dc_state *context = dc->current_state; + struct dc_firmware_info fw_info = { { 0 } }; if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); @@ -546,6 +547,30 @@ static void dcn20_init_hw(struct dc *dc) } else { if (!dcb->funcs->is_accelerated_mode(dcb)) { bios_golden_init(dc); + if (dc->ctx->dc_bios->funcs->get_firmware_info( + dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) { + res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency; + + if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { + if (res_pool->dccg && res_pool->hubbub) { + + (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, + fw_info.pll_info.crystal_frequency, + &res_pool->ref_clocks.dccg_ref_clock_inKhz); + + (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, + res_pool->ref_clocks.dccg_ref_clock_inKhz, + &res_pool->ref_clocks.dchub_ref_clock_inKhz); + } else { + // Not all ASICs have DCCG sw component + res_pool->ref_clocks.dccg_ref_clock_inKhz = + res_pool->ref_clocks.xtalin_clock_inKhz; + res_pool->ref_clocks.dchub_ref_clock_inKhz = + res_pool->ref_clocks.xtalin_clock_inKhz; + } + } + } else + ASSERT_CRITICAL(false); disable_vga(dc->hwseq); } -- cgit v1.2.3 From bb2b4074f8d99214718f45c379ceb74564aad3bc Mon Sep 17 00:00:00 2001 From: Timo Wiren Date: Wed, 22 May 2019 20:01:06 +0300 Subject: drm/nouveau/mcp89/mmu: Use mcp77_mmu_new instead of g84_mmu_new on MCP89. Fix a crash or broken depth testing in all OpenGL applications that use the depth buffer on MCP89 (GeForce 320M) seen on a MacBook Pro Late 2010. The bug is tracked in https://bugs.freedesktop.org/show_bug.cgi?id=108500 Signed-off-by: Timo Wiren Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 10d91e8bbb94..c08be2860d03 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -1316,7 +1316,7 @@ nvaf_chipset = { .i2c = g94_i2c_new, .imem = nv50_instmem_new, .mc = gt215_mc_new, - .mmu = g84_mmu_new, + .mmu = mcp77_mmu_new, .mxm = nv50_mxm_new, .pci = g94_pci_new, .pmu = gt215_pmu_new, -- cgit v1.2.3 From f8d6211ac77f0d1f7aebc64e961dc28771ba0052 Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Sat, 25 May 2019 18:41:48 -0400 Subject: drm/nouveau/disp/nv50-: force scaler for any non-default LVDS/eDP modes Higher layers tend to add a lot of modes not actually in the EDID, such as the standard DMT modes. Changing this would be extremely intrusive to everyone, so just force the scaler more often. There are no practical cases we're aware of where a LVDS/eDP panel has multiple resolutions exposed, and i915 already does it this way. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110660 Signed-off-by: Ilia Mirkin Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/disp.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index 7ba373f493b2..8497768f1b41 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -322,8 +322,13 @@ nv50_outp_atomic_check_view(struct drm_encoder *encoder, switch (connector->connector_type) { case DRM_MODE_CONNECTOR_LVDS: case DRM_MODE_CONNECTOR_eDP: - /* Force use of scaler for non-EDID modes. */ - if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER) + /* Don't force scaler for EDID modes with + * same size as the native one (e.g. different + * refresh rate) + */ + if (adjusted_mode->hdisplay == native_mode->hdisplay && + adjusted_mode->vdisplay == native_mode->vdisplay && + adjusted_mode->type & DRM_MODE_TYPE_DRIVER) break; mode = native_mode; asyc->scaler.full = true; -- cgit v1.2.3 From 533f4752407543f488a9118d817b8c504352b6fb Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Sat, 25 May 2019 18:41:49 -0400 Subject: drm/nouveau/disp/nv50-: fix center/aspect-corrected scaling Previously center scaling would get scaling applied to it (when it was only supposed to center the image), and aspect-corrected scaling did not always correctly pick whether to reduce width or height for a particular combination of inputs/outputs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110660 Signed-off-by: Ilia Mirkin Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/head.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.c b/drivers/gpu/drm/nouveau/dispnv50/head.c index 48a6485ec4e0..929d93b1677e 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head.c @@ -169,14 +169,34 @@ nv50_head_atomic_check_view(struct nv50_head_atom *armh, */ switch (mode) { case DRM_MODE_SCALE_CENTER: - asyh->view.oW = min((u16)umode->hdisplay, asyh->view.oW); - asyh->view.oH = min((u16)umode_vdisplay, asyh->view.oH); - /* fall-through */ + /* NOTE: This will cause scaling when the input is + * larger than the output. + */ + asyh->view.oW = min(asyh->view.iW, asyh->view.oW); + asyh->view.oH = min(asyh->view.iH, asyh->view.oH); + break; case DRM_MODE_SCALE_ASPECT: - if (asyh->view.oH < asyh->view.oW) { + /* Determine whether the scaling should be on width or on + * height. This is done by comparing the aspect ratios of the + * sizes. If the output AR is larger than input AR, that means + * we want to change the width (letterboxed on the + * left/right), otherwise on the height (letterboxed on the + * top/bottom). + * + * E.g. 4:3 (1.333) AR image displayed on a 16:10 (1.6) AR + * screen will have letterboxes on the left/right. However a + * 16:9 (1.777) AR image on that same screen will have + * letterboxes on the top/bottom. + * + * inputAR = iW / iH; outputAR = oW / oH + * outputAR > inputAR is equivalent to oW * iH > iW * oH + */ + if (asyh->view.oW * asyh->view.iH > asyh->view.iW * asyh->view.oH) { + /* Recompute output width, i.e. left/right letterbox */ u32 r = (asyh->view.iW << 19) / asyh->view.iH; asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19; } else { + /* Recompute output height, i.e. top/bottom letterbox */ u32 r = (asyh->view.iH << 19) / asyh->view.iW; asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19; } -- cgit v1.2.3 From d1084184789d677df4e9c110f38cb3f3d709195d Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 29 May 2019 09:58:18 +1000 Subject: drm/nouveau/kms: disallow dual-link harder if hdmi connection detected The fallthrough cases (pre-Fermi) would accidentally allow dual-link pixel clocks even where they shouldn't be. This leads to a high resolution HDMI displays, connected via a DVI->HDMI adapter, to fail on the original NV50. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_connector.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index 4116ee62adaf..caa8c7595889 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -978,11 +978,13 @@ get_tmds_link_bandwidth(struct drm_connector *connector) struct nouveau_drm *drm = nouveau_drm(connector->dev); struct dcb_output *dcb = nv_connector->detected_encoder->dcb; struct drm_display_info *info = NULL; - const unsigned duallink_scale = + unsigned duallink_scale = nouveau_duallink && nv_encoder->dcb->duallink_possible ? 2 : 1; - if (drm_detect_hdmi_monitor(nv_connector->edid)) + if (drm_detect_hdmi_monitor(nv_connector->edid)) { info = &nv_connector->base.display_info; + duallink_scale = 1; + } if (info) { if (nouveau_hdmimhz > 0) @@ -1003,6 +1005,7 @@ get_tmds_link_bandwidth(struct drm_connector *connector) if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI) return 225000; } + if (dcb->location != DCB_LOC_ON_CHIP || drm->client.device.info.chipset >= 0x46) return 165000 * duallink_scale; -- cgit v1.2.3 From 75dec321cd2dceb439686b771c67e677c47618c5 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 17 Jun 2019 12:52:48 +1000 Subject: drm/nouveau/core: recognise TU116 chipset Modesetting only, still waiting on ACR/GR firmware from NVIDIA for Turing graphics/compute bring-up. Each subsystem was compared with traces, along with various tests to check that things generally work as they should, and appears compatible enough with the current TU117 code to enable support. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 36 +++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index c08be2860d03..c3c7159f3411 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -2575,6 +2575,41 @@ nv167_chipset = { .sec2 = tu102_sec2_new, }; +static const struct nvkm_device_chip +nv168_chipset = { + .name = "TU116", + .bar = tu102_bar_new, + .bios = nvkm_bios_new, + .bus = gf100_bus_new, + .devinit = tu102_devinit_new, + .fault = tu102_fault_new, + .fb = gv100_fb_new, + .fuse = gm107_fuse_new, + .gpio = gk104_gpio_new, + .gsp = gv100_gsp_new, + .i2c = gm200_i2c_new, + .ibus = gm200_ibus_new, + .imem = nv50_instmem_new, + .ltc = gp102_ltc_new, + .mc = tu102_mc_new, + .mmu = tu102_mmu_new, + .pci = gp100_pci_new, + .pmu = gp102_pmu_new, + .therm = gp100_therm_new, + .timer = gk20a_timer_new, + .top = gk104_top_new, + .ce[0] = tu102_ce_new, + .ce[1] = tu102_ce_new, + .ce[2] = tu102_ce_new, + .ce[3] = tu102_ce_new, + .ce[4] = tu102_ce_new, + .disp = tu102_disp_new, + .dma = gv100_dma_new, + .fifo = tu102_fifo_new, + .nvdec[0] = gp102_nvdec_new, + .sec2 = tu102_sec2_new, +}; + static int nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size, struct nvkm_notify *notify) @@ -3052,6 +3087,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, case 0x164: device->chip = &nv164_chipset; break; case 0x166: device->chip = &nv166_chipset; break; case 0x167: device->chip = &nv167_chipset; break; + case 0x168: device->chip = &nv168_chipset; break; default: nvdev_error(device, "unknown chipset (%08x)\n", boot0); goto done; -- cgit v1.2.3 From 3485b7b50b53953d6e9e7cb997949f42bc624853 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 18 Jun 2019 18:40:16 +1000 Subject: drm/nouveau/disp/tu102-: wire up scdc parameter setter Regs seem valid here still, and tested on TU116. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c index d57b73ada89e..4d5f3791ea7b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c @@ -72,6 +72,7 @@ tu102_sor = { .clock = gf119_sor_clock, .hdmi = { .ctrl = gv100_hdmi_ctrl, + .scdc = gm200_hdmi_scdc, }, .dp = { .lanes = { 0, 1, 2, 3 }, -- cgit v1.2.3 From 7cb95eeea6706c790571042a06782e378b2561ea Mon Sep 17 00:00:00 2001 From: Lyude Paul Date: Wed, 26 Jun 2019 14:10:27 -0400 Subject: drm/nouveau/i2c: Enable i2c pads & busses during preinit It turns out that while disabling i2c bus access from software when the GPU is suspended was a step in the right direction with: commit 342406e4fbba ("drm/nouveau/i2c: Disable i2c bus access after ->fini()") We also ended up accidentally breaking the vbios init scripts on some older Tesla GPUs, as apparently said scripts can actually use the i2c bus. Since these scripts are executed before initializing any subdevices, we end up failing to acquire access to the i2c bus which has left a number of cards with their fan controllers uninitialized. Luckily this doesn't break hardware - it just means the fan gets stuck at 100%. This also means that we've always been using our i2c busses before initializing them during the init scripts for older GPUs, we just didn't notice it until we started preventing them from being used until init. It's pretty impressive this never caused us any issues before! So, fix this by initializing our i2c pad and busses during subdev pre-init. We skip initializing aux busses during pre-init, as those are guaranteed to only ever be used by nouveau for DP aux transactions. Signed-off-by: Lyude Paul Tested-by: Marc Meledandri Fixes: 342406e4fbba ("drm/nouveau/i2c: Disable i2c bus access after ->fini()") Cc: stable@vger.kernel.org Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c index ecacb22834d7..719345074711 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c @@ -184,6 +184,25 @@ nvkm_i2c_fini(struct nvkm_subdev *subdev, bool suspend) return 0; } +static int +nvkm_i2c_preinit(struct nvkm_subdev *subdev) +{ + struct nvkm_i2c *i2c = nvkm_i2c(subdev); + struct nvkm_i2c_bus *bus; + struct nvkm_i2c_pad *pad; + + /* + * We init our i2c busses as early as possible, since they may be + * needed by the vbios init scripts on some cards + */ + list_for_each_entry(pad, &i2c->pad, head) + nvkm_i2c_pad_init(pad); + list_for_each_entry(bus, &i2c->bus, head) + nvkm_i2c_bus_init(bus); + + return 0; +} + static int nvkm_i2c_init(struct nvkm_subdev *subdev) { @@ -238,6 +257,7 @@ nvkm_i2c_dtor(struct nvkm_subdev *subdev) static const struct nvkm_subdev_func nvkm_i2c = { .dtor = nvkm_i2c_dtor, + .preinit = nvkm_i2c_preinit, .init = nvkm_i2c_init, .fini = nvkm_i2c_fini, .intr = nvkm_i2c_intr, -- cgit v1.2.3 From b7019ac550eb3916f34d79db583e9b7ea2524afa Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Wed, 19 Jun 2019 20:13:43 -0400 Subject: drm/nouveau: fix bogus GPL-2 license header The bulk SPDX addition made all these files into GPL-2.0 licensed files. However the remainder of the project is MIT-licensed, these files (primarily header files) were simply missing the boiler plate and got caught up in the global update. Fixes: b24413180f5 (License cleanup: add SPDX GPL-2.0 license identifier to files with no license) Signed-off-by: Ilia Mirkin Acked-by: Emil Velikov Acked-by: Karol Herbst Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv04/cursor.c | 2 +- drivers/gpu/drm/nouveau/dispnv04/disp.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/cl0002.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/cl0046.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/cl006b.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/cl0080.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/cl506e.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/cl506f.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/cl5070.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/cl507a.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/cl507b.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/cl507c.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/cl507d.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/cl507e.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/cl826e.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/cl826f.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/cl906f.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/cl9097.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/cla06f.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/class.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/clc36f.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/clc37b.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/clc37e.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/client.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/device.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/driver.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/event.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/if0000.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/if0001.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/if0002.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/if0003.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/if0004.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/if0005.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/ioctl.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/notify.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/object.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/os.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/unpack.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/client.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/debug.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/device.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/engine.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/enum.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/event.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/firmware.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/ioctl.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/memory.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/mm.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/notify.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/object.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/oproxy.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/option.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/os.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/pci.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/ramht.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/engine/msenc.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/engine/nvdec.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/engine/vic.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0203.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0205.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0209.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/P0260.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bit.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bmp.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/fan.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/i2c.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/iccsense.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/image.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/mxm.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/npde.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pcir.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/power_budget.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/rammap.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/therm.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vpstate.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/xpio.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/iccsense.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/vga.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h | 2 +- drivers/gpu/drm/nouveau/nouveau_abi16.h | 2 +- drivers/gpu/drm/nouveau/nouveau_acpi.c | 2 +- drivers/gpu/drm/nouveau/nouveau_acpi.h | 2 +- drivers/gpu/drm/nouveau/nouveau_bo.h | 2 +- drivers/gpu/drm/nouveau/nouveau_chan.h | 2 +- drivers/gpu/drm/nouveau/nouveau_debugfs.h | 2 +- drivers/gpu/drm/nouveau/nouveau_display.h | 2 +- drivers/gpu/drm/nouveau/nouveau_drv.h | 2 +- drivers/gpu/drm/nouveau/nouveau_fence.h | 2 +- drivers/gpu/drm/nouveau/nouveau_gem.h | 2 +- drivers/gpu/drm/nouveau/nouveau_ioctl.h | 2 +- drivers/gpu/drm/nouveau/nouveau_reg.h | 2 +- drivers/gpu/drm/nouveau/nouveau_sgdma.c | 2 +- drivers/gpu/drm/nouveau/nouveau_ttm.h | 2 +- drivers/gpu/drm/nouveau/nouveau_usif.h | 2 +- drivers/gpu/drm/nouveau/nouveau_vga.c | 2 +- drivers/gpu/drm/nouveau/nouveau_vga.h | 2 +- drivers/gpu/drm/nouveau/nv10_fence.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/ce/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/head.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/dma/user.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/regsnv04.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/os.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/mpeg/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/mspdec/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/msppp/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/msvld/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/nvdec/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/g98.fuc0s.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/sw/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/falcon/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/bios/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/bus/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/clk/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/regsnv04.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bus.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/ibus/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/mxm/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gt215.fuc3.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/os.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/timer/regsnv04.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/top/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/volt/priv.h | 2 +- 277 files changed, 277 insertions(+), 277 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/dispnv04/cursor.c b/drivers/gpu/drm/nouveau/dispnv04/cursor.c index ebf860bd59af..16e09f6b9113 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/cursor.c +++ b/drivers/gpu/drm/nouveau/dispnv04/cursor.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: MIT #include #include #include "nouveau_drv.h" diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.h b/drivers/gpu/drm/nouveau/dispnv04/disp.h index c6ed20a09f4a..6ccfc09bcf0f 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/disp.h +++ b/drivers/gpu/drm/nouveau/dispnv04/disp.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NV04_DISPLAY_H__ #define __NV04_DISPLAY_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl0002.h b/drivers/gpu/drm/nouveau/include/nvif/cl0002.h index 1a8b45b4631f..65d432a5bd6c 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl0002.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl0002.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CL0002_H__ #define __NVIF_CL0002_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl0046.h b/drivers/gpu/drm/nouveau/include/nvif/cl0046.h index c0d5eba4f8fc..d490d401870a 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl0046.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl0046.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CL0046_H__ #define __NVIF_CL0046_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl006b.h b/drivers/gpu/drm/nouveau/include/nvif/cl006b.h index d0e8f35d9e92..c960c449e430 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl006b.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl006b.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CL006B_H__ #define __NVIF_CL006B_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl0080.h b/drivers/gpu/drm/nouveau/include/nvif/cl0080.h index 4cbed0329367..cd9a2e687bb6 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl0080.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl0080.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CL0080_H__ #define __NVIF_CL0080_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl506e.h b/drivers/gpu/drm/nouveau/include/nvif/cl506e.h index 989690fe3cd8..9df289c7a84f 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl506e.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl506e.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CL506E_H__ #define __NVIF_CL506E_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl506f.h b/drivers/gpu/drm/nouveau/include/nvif/cl506f.h index 5137b6879abd..327c96a994bb 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl506f.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl506f.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CL506F_H__ #define __NVIF_CL506F_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl5070.h b/drivers/gpu/drm/nouveau/include/nvif/cl5070.h index bced81987269..38bf4f38e869 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl5070.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl5070.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CL5070_H__ #define __NVIF_CL5070_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl507a.h b/drivers/gpu/drm/nouveau/include/nvif/cl507a.h index 36e537218596..3b2a9809b8ce 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl507a.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl507a.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CL507A_H__ #define __NVIF_CL507A_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl507b.h b/drivers/gpu/drm/nouveau/include/nvif/cl507b.h index 3e643b752bfc..0f3d05581ea5 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl507b.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl507b.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CL507B_H__ #define __NVIF_CL507B_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl507c.h b/drivers/gpu/drm/nouveau/include/nvif/cl507c.h index fd9e336d0a24..7da8813f4f5c 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl507c.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl507c.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CL507C_H__ #define __NVIF_CL507C_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl507d.h b/drivers/gpu/drm/nouveau/include/nvif/cl507d.h index e994c6894e3e..4a56e42d8bc9 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl507d.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl507d.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CL507D_H__ #define __NVIF_CL507D_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl507e.h b/drivers/gpu/drm/nouveau/include/nvif/cl507e.h index 8082d2fde248..633936cb6313 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl507e.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl507e.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CL507E_H__ #define __NVIF_CL507E_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl826e.h b/drivers/gpu/drm/nouveau/include/nvif/cl826e.h index 1a875090b251..1b6496d31580 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl826e.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl826e.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CL826E_H__ #define __NVIF_CL826E_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl826f.h b/drivers/gpu/drm/nouveau/include/nvif/cl826f.h index e4e50cfe88f1..148602264a76 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl826f.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl826f.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CL826F_H__ #define __NVIF_CL826F_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl906f.h b/drivers/gpu/drm/nouveau/include/nvif/cl906f.h index ab0fa8adb756..3823d6891b55 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl906f.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl906f.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CL906F_H__ #define __NVIF_CL906F_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl9097.h b/drivers/gpu/drm/nouveau/include/nvif/cl9097.h index e4c8de6d00b7..599d858afa36 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl9097.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl9097.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CL9097_H__ #define __NVIF_CL9097_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/cla06f.h b/drivers/gpu/drm/nouveau/include/nvif/cla06f.h index 81401eb970ea..cfa18f1fbf83 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cla06f.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cla06f.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CLA06F_H__ #define __NVIF_CLA06F_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h index 7d556a1c92fa..f704ae600e94 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/class.h +++ b/drivers/gpu/drm/nouveau/include/nvif/class.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CLASS_H__ #define __NVIF_CLASS_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/clc36f.h b/drivers/gpu/drm/nouveau/include/nvif/clc36f.h index 6b14d7e3f6bb..f66885891238 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/clc36f.h +++ b/drivers/gpu/drm/nouveau/include/nvif/clc36f.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CLC36F_H__ #define __NVIF_CLC36F_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/clc37b.h b/drivers/gpu/drm/nouveau/include/nvif/clc37b.h index 89b18189d43b..970a5ac4cb95 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/clc37b.h +++ b/drivers/gpu/drm/nouveau/include/nvif/clc37b.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CLC37B_H__ #define __NVIF_CLC37B_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/clc37e.h b/drivers/gpu/drm/nouveau/include/nvif/clc37e.h index 899db9e915ef..7ea23695e7e1 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/clc37e.h +++ b/drivers/gpu/drm/nouveau/include/nvif/clc37e.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CLC37E_H__ #define __NVIF_CLC37E_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/client.h b/drivers/gpu/drm/nouveau/include/nvif/client.h index f5df8b30c599..e63c6c965b54 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/client.h +++ b/drivers/gpu/drm/nouveau/include/nvif/client.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_CLIENT_H__ #define __NVIF_CLIENT_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h index ef839bd1d37e..25d969dcf67d 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/device.h +++ b/drivers/gpu/drm/nouveau/include/nvif/device.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_DEVICE_H__ #define __NVIF_DEVICE_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/driver.h b/drivers/gpu/drm/nouveau/include/nvif/driver.h index 93bccd45a042..8e85b936eaa0 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/driver.h +++ b/drivers/gpu/drm/nouveau/include/nvif/driver.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_DRIVER_H__ #define __NVIF_DRIVER_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvif/event.h b/drivers/gpu/drm/nouveau/include/nvif/event.h index ec5c924f576a..a6b1ee4f10ca 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/event.h +++ b/drivers/gpu/drm/nouveau/include/nvif/event.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_EVENT_H__ #define __NVIF_EVENT_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0000.h b/drivers/gpu/drm/nouveau/include/nvif/if0000.h index 30ecd31db5df..f7b8f8f48760 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/if0000.h +++ b/drivers/gpu/drm/nouveau/include/nvif/if0000.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_IF0000_H__ #define __NVIF_IF0000_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0001.h b/drivers/gpu/drm/nouveau/include/nvif/if0001.h index ca9215262215..4ced50e98ced 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/if0001.h +++ b/drivers/gpu/drm/nouveau/include/nvif/if0001.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_IF0001_H__ #define __NVIF_IF0001_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0002.h b/drivers/gpu/drm/nouveau/include/nvif/if0002.h index d9235c011196..df2915d6a61e 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/if0002.h +++ b/drivers/gpu/drm/nouveau/include/nvif/if0002.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_IF0002_H__ #define __NVIF_IF0002_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0003.h b/drivers/gpu/drm/nouveau/include/nvif/if0003.h index ae30b8261b88..78467da07c37 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/if0003.h +++ b/drivers/gpu/drm/nouveau/include/nvif/if0003.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_IF0003_H__ #define __NVIF_IF0003_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0004.h b/drivers/gpu/drm/nouveau/include/nvif/if0004.h index b35547c8ea36..d324c73c27fb 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/if0004.h +++ b/drivers/gpu/drm/nouveau/include/nvif/if0004.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_IF0004_H__ #define __NVIF_IF0004_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0005.h b/drivers/gpu/drm/nouveau/include/nvif/if0005.h index 8ed0ae101715..fb9305b3b32c 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/if0005.h +++ b/drivers/gpu/drm/nouveau/include/nvif/if0005.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_IF0005_H__ #define __NVIF_IF0005_H__ #define NV10_NVSW_NTFY_UEVENT 0x00 diff --git a/drivers/gpu/drm/nouveau/include/nvif/ioctl.h b/drivers/gpu/drm/nouveau/include/nvif/ioctl.h index b93d586a2304..886c63fe753f 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/ioctl.h +++ b/drivers/gpu/drm/nouveau/include/nvif/ioctl.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_IOCTL_H__ #define __NVIF_IOCTL_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/notify.h b/drivers/gpu/drm/nouveau/include/nvif/notify.h index 4ed169230657..6863732eb286 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/notify.h +++ b/drivers/gpu/drm/nouveau/include/nvif/notify.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_NOTIFY_H__ #define __NVIF_NOTIFY_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/object.h b/drivers/gpu/drm/nouveau/include/nvif/object.h index 8407651f6ac6..604fabc0e689 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/object.h +++ b/drivers/gpu/drm/nouveau/include/nvif/object.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_OBJECT_H__ #define __NVIF_OBJECT_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/os.h b/drivers/gpu/drm/nouveau/include/nvif/os.h index fd09b2842972..429d0106c123 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/os.h +++ b/drivers/gpu/drm/nouveau/include/nvif/os.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NOUVEAU_OS_H__ #define __NOUVEAU_OS_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvif/unpack.h b/drivers/gpu/drm/nouveau/include/nvif/unpack.h index 7f0d9f6cc1e7..0584b938e8f9 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/unpack.h +++ b/drivers/gpu/drm/nouveau/include/nvif/unpack.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVIF_UNPACK_H__ #define __NVIF_UNPACK_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h index 757fac823a10..5d7017fe5039 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_CLIENT_H__ #define __NVKM_CLIENT_H__ #define nvkm_client(p) container_of((p), struct nvkm_client, object) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/debug.h b/drivers/gpu/drm/nouveau/include/nvkm/core/debug.h index 966d1822dd80..b4a9c7d991ca 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/debug.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/debug.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_DEBUG_H__ #define __NVKM_DEBUG_H__ #define NV_DBG_FATAL 0 diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h index 642492344196..6d55cd0476aa 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_DEVICE_H__ #define __NVKM_DEVICE_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h b/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h index 8a2be5b635e2..c6b401a6ea23 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_ENGINE_H__ #define __NVKM_ENGINE_H__ #define nvkm_engine(p) container_of((p), struct nvkm_engine, subdev) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/enum.h b/drivers/gpu/drm/nouveau/include/nvkm/core/enum.h index 38acbde2de4f..ce98efd4b209 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/enum.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/enum.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_ENUM_H__ #define __NVKM_ENUM_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/event.h b/drivers/gpu/drm/nouveau/include/nvkm/core/event.h index d3c45e90a1c1..a7a413f07a78 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/event.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/event.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_EVENT_H__ #define __NVKM_EVENT_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/firmware.h b/drivers/gpu/drm/nouveau/include/nvkm/core/firmware.h index 54da9c6bc8d5..383370c32428 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/firmware.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/firmware.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_FIRMWARE_H__ #define __NVKM_FIRMWARE_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h b/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h index 10eeaeebc242..0f515ec28fa9 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_GPUOBJ_H__ #define __NVKM_GPUOBJ_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/ioctl.h b/drivers/gpu/drm/nouveau/include/nvkm/core/ioctl.h index e2d39192fa26..71ed147ad077 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/ioctl.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/ioctl.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_IOCTL_H__ #define __NVKM_IOCTL_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/memory.h b/drivers/gpu/drm/nouveau/include/nvkm/core/memory.h index f34c80310861..b23bf6109f2d 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/memory.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/memory.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_MEMORY_H__ #define __NVKM_MEMORY_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h b/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h index b0726c39429e..4ecfbde88537 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_MM_H__ #define __NVKM_MM_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/notify.h b/drivers/gpu/drm/nouveau/include/nvkm/core/notify.h index 4eb82bc563f3..3d358a66db3a 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/notify.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/notify.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_NOTIFY_H__ #define __NVKM_NOTIFY_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/object.h b/drivers/gpu/drm/nouveau/include/nvkm/core/object.h index 270f893cc154..7efcd5d2f2ff 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/object.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/object.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_OBJECT_H__ #define __NVKM_OBJECT_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/oproxy.h b/drivers/gpu/drm/nouveau/include/nvkm/core/oproxy.h index d950d5ee188b..0e70a9afba33 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/oproxy.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/oproxy.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_OPROXY_H__ #define __NVKM_OPROXY_H__ #define nvkm_oproxy(p) container_of((p), struct nvkm_oproxy, base) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/option.h b/drivers/gpu/drm/nouveau/include/nvkm/core/option.h index a34a79bacbd0..6882eb7c7e26 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/option.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/option.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_OPTION_H__ #define __NVKM_OPTION_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h index 445602d1e8d3..029a416197db 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_OS_H__ #define __NVKM_OS_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/pci.h b/drivers/gpu/drm/nouveau/include/nvkm/core/pci.h index 4c7f647d2dc9..b4b5df3e1610 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/pci.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/pci.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_DEVICE_PCI_H__ #define __NVKM_DEVICE_PCI_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/ramht.h b/drivers/gpu/drm/nouveau/include/nvkm/core/ramht.h index d5d789663aca..bc2d1dcccb4e 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/ramht.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/ramht.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_RAMHT_H__ #define __NVKM_RAMHT_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h b/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h index 85a0777c2ce4..1218f28c14ba 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_SUBDEV_H__ #define __NVKM_SUBDEV_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h b/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h index 5c102d0206a7..924009dd2bb0 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_DEVICE_TEGRA_H__ #define __NVKM_DEVICE_TEGRA_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h index 40613983fccb..f938f024db81 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_BSP_H__ #define __NVKM_BSP_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h index 5f3650692e4d..86f420f4630b 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_CE_H__ #define __NVKM_CE_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h index 72b9da2de7c2..66c5c5e27520 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_CIPHER_H__ #define __NVKM_CIPHER_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h index 3026b22d44fb..5a96c942d912 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_DISP_H__ #define __NVKM_DISP_H__ #define nvkm_disp(p) container_of((p), struct nvkm_disp, engine) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h index f0c1b2c8c78c..2e12cdb6bb93 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_DMA_H__ #define __NVKM_DMA_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h index 6427747b6f77..23b582d696c6 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_FALCON_H__ #define __NVKM_FALCON_H__ #define nvkm_falcon(p) container_of((p), struct nvkm_falcon, engine) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h index b7fc04dd1628..b335f3a1e66d 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_FIFO_H__ #define __NVKM_FIFO_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h index 1e924c7f7ba7..2cde36f3c064 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_GR_H__ #define __NVKM_GR_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h index 4ef3d4c5e358..8585a31f5943 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_MPEG_H__ #define __NVKM_MPEG_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/msenc.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/msenc.h index 985fc9490643..08fbe7b3cb4b 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/msenc.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/msenc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_MSENC_H__ #define __NVKM_MSENC_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h index e03f33472486..83bb2fcb2cbf 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_MSPDEC_H__ #define __NVKM_MSPDEC_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h index 760bf17ea63d..69e09fd96e0c 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_MSPPP_H__ #define __NVKM_MSPPP_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h index 281866d2501d..9e11cefc9649 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_MSVLD_H__ #define __NVKM_MSVLD_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/nvdec.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/nvdec.h index b72a4844c5f7..7c7d7f0abfcc 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/nvdec.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/nvdec.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_NVDEC_H__ #define __NVKM_NVDEC_H__ #define nvkm_nvdec(p) container_of((p), struct nvkm_nvdec, engine) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h index cdd68a8bab8b..21624046d0a1 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_NVENC_H__ #define __NVKM_NVENC_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h index 6cce8502f9df..4d754e7650d9 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_PM_H__ #define __NVKM_PM_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h index b206b918c43e..f14e98a8a0ca 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_SEC_H__ #define __NVKM_SEC_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h index c93ad332461a..33078f86c779 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_SEC2_H__ #define __NVKM_SEC2_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h index 83a17c4e11e7..2e91769e3ee2 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_SW_H__ #define __NVKM_SW_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/vic.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/vic.h index 9b7d4877cf41..35555c559eab 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/vic.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/vic.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_VIC_H__ #define __NVKM_VIC_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h index 53bf8aed48fb..8984415b2a3d 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_VP_H__ #define __NVKM_VP_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h index 13c00ce6d556..fbf27b2293a9 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_XTENSA_H__ #define __NVKM_XTENSA_H__ #define nvkm_xtensa(p) container_of((p), struct nvkm_xtensa, engine) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h index da14486317ca..14b09f7e46a5 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_BAR_H__ #define __NVKM_BAR_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h index 979e9a144e7b..f2860f8e0c2e 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_BIOS_H__ #define __NVKM_BIOS_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0203.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0203.h index 425ccc47e3b7..9227ed640132 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0203.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0203.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_M0203_H__ #define __NVBIOS_M0203_H__ struct nvbios_M0203T { diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0205.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0205.h index b4e14e45a0e8..7ec1dabc5fe4 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0205.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0205.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_M0205_H__ #define __NVBIOS_M0205_H__ struct nvbios_M0205T { diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0209.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0209.h index c09376894d12..49a7bb0f3c50 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0209.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0209.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_M0209_H__ #define __NVBIOS_M0209_H__ u32 nvbios_M0209Te(struct nvkm_bios *, diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/P0260.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/P0260.h index 901d94ef11b8..caad7256d9e5 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/P0260.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/P0260.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_P0260_H__ #define __NVBIOS_P0260_H__ u32 nvbios_P0260Te(struct nvkm_bios *, diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bit.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bit.h index d068586f3263..ebfe45fce965 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bit.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bit.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_BIT_H__ #define __NVBIOS_BIT_H__ struct bit_entry { diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bmp.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bmp.h index 9a3f9483ee75..263408a535ae 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bmp.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bmp.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_BMP_H__ #define __NVBIOS_BMP_H__ static inline u16 diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h index a1c48c6b223b..489fd3554a17 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_BOOST_H__ #define __NVBIOS_BOOST_H__ u32 nvbios_boostTe(struct nvkm_bios *, u8 *, u8 *, u8 *, u8 *, u8 *, u8 *); diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h index 8463b421d345..f5f59261ea81 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_CONN_H__ #define __NVBIOS_CONN_H__ enum dcb_connector_type { diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h index 49343d276e11..6a287a016580 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_CSTEP_H__ #define __NVBIOS_CSTEP_H__ u32 nvbios_cstepTe(struct nvkm_bios *, diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h index 63ddc6ed897a..a27a0f3fe7aa 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_DCB_H__ #define __NVBIOS_DCB_H__ enum dcb_output_type { diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h index 423d92de0aae..ef44205a91f6 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_DISP_H__ #define __NVBIOS_DISP_H__ u16 nvbios_disp_table(struct nvkm_bios *, diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h index 512e25a41803..1df5e1618455 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_DP_H__ #define __NVBIOS_DP_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h index f93e4f951f2f..f29f2d8da142 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_EXTDEV_H__ #define __NVBIOS_EXTDEV_H__ enum nvbios_extdev_type { diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/fan.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/fan.h index 09c1d3b9d009..8b3fb1f5d3ab 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/fan.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/fan.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_FAN_H__ #define __NVBIOS_FAN_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h index b71a3555c64e..7c4f00366e71 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_GPIO_H__ #define __NVBIOS_GPIO_H__ enum dcb_gpio_func_name { diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/i2c.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/i2c.h index ae1f7483dd28..e84a0eb6df26 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/i2c.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/i2c.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_I2C_H__ #define __NVBIOS_I2C_H__ enum dcb_i2c_type { diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/iccsense.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/iccsense.h index e220a1ac1387..4c108fd2c805 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/iccsense.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/iccsense.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_ICCSENSE_H__ #define __NVBIOS_ICCSENSE_H__ struct pwr_rail_resistor_t { diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/image.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/image.h index 893288b060de..e13dc059a9ee 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/image.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/image.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_IMAGE_H__ #define __NVBIOS_IMAGE_H__ struct nvbios_image { diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h index 744b1868e789..10df0215475e 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_INIT_H__ #define __NVBIOS_INIT_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/mxm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/mxm.h index 327bf9c4b703..7204c6f4f247 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/mxm.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/mxm.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_MXM_H__ #define __NVBIOS_MXM_H__ u16 mxm_table(struct nvkm_bios *, u8 *ver, u8 *hdr); diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/npde.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/npde.h index ee5419b7b45b..f10f176a3323 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/npde.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/npde.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_NPDE_H__ #define __NVBIOS_NPDE_H__ struct nvbios_npdeT { diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pcir.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pcir.h index 1dffe8d6cc81..bb7bf67d1d19 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pcir.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pcir.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_PCIR_H__ #define __NVBIOS_PCIR_H__ struct nvbios_pcirT { diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h index 0ee84ea6d737..1b67c0958721 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_PERF_H__ #define __NVBIOS_PERF_H__ u32 nvbios_perf_table(struct nvkm_bios *, u8 *ver, u8 *hdr, diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h index ab964e085f02..b2c2d0959f6f 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_PLL_H__ #define __NVBIOS_PLL_H__ /*XXX: kill me */ diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h index fb41ecab8f8c..7177d39371cf 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_PMU_H__ #define __NVBIOS_PMU_H__ struct nvbios_pmuT { diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/power_budget.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/power_budget.h index ff12d810dce3..95306be163cc 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/power_budget.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/power_budget.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_POWER_BUDGET_H__ #define __NVBIOS_POWER_BUDGET_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h index 2b87a38adb7a..153edf898b5d 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_RAMCFG_H__ #define __NVBIOS_RAMCFG_H__ struct nvbios_ramcfg { diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/rammap.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/rammap.h index 471eef434b51..7f054042f9d7 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/rammap.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/rammap.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_RAMMAP_H__ #define __NVBIOS_RAMMAP_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/therm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/therm.h index 46a3b15e10ec..0fb8a3480871 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/therm.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/therm.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_THERM_H__ #define __NVBIOS_THERM_H__ struct nvbios_therm_threshold { diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h index 40ceabf37827..c1f77773aace 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_TIMING_H__ #define __NVBIOS_TIMING_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h index 67419bad584c..13103b9b5b96 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_VMAP_H__ #define __NVBIOS_VMAP_H__ struct nvbios_vmap { diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h index 6b36d5ecb8f9..0c9be1b2ebbf 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_VOLT_H__ #define __NVBIOS_VOLT_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vpstate.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vpstate.h index 36f3028d58ef..df94e26f873a 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vpstate.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vpstate.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_VPSTATE_H__ #define __NVBIOS_VPSTATE_H__ struct nvbios_vpstate_header { diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/xpio.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/xpio.h index d1bb5d044585..11b4c4d27e5f 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/xpio.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/xpio.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVBIOS_XPIO_H__ #define __NVBIOS_XPIO_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h index 7695f7f77a06..ae9ad6c034fb 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_BUS_H__ #define __NVKM_BUS_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h index 15db75ef0189..bf937e7dfd77 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_CLK_H__ #define __NVKM_CLK_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h index 8ba982c2fdfb..1a39e52e09e3 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_DEVINIT_H__ #define __NVKM_DEVINIT_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h index 27298f8b7ead..239ad222b95a 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_FB_H__ #define __NVKM_FB_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h index 092193b7f98e..00111c34311e 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_FUSE_H__ #define __NVKM_FUSE_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h index ee54899076e3..eaacf8d80527 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_GPIO_H__ #define __NVKM_GPIO_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h index 7957eafa5f0e..81b977319640 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_I2C_H__ #define __NVKM_I2C_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h index 919653c1d101..db791411eaa8 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_IBUS_H__ #define __NVKM_IBUS_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/iccsense.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/iccsense.h index be9475cd94fd..f483dcd7cd1c 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/iccsense.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/iccsense.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_ICCSENSE_H__ #define __NVKM_ICCSENSE_H__ diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h index 36ed520ed2d0..c74ab7c31d05 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_INSTMEM_H__ #define __NVKM_INSTMEM_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h index 9db5f8293198..644d527c3b96 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_LTC_H__ #define __NVKM_LTC_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h index e38f4958dea2..6641fe4c252c 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_MC_H__ #define __NVKM_MC_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h index 28ade86f74c5..54cdcb017518 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_MMU_H__ #define __NVKM_MMU_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h index 0fd6d6f8eada..78df1e9def05 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_MXM_H__ #define __NVKM_MXM_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h index 23803cc859fd..4803a4fad4a2 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_PCI_H__ #define __NVKM_PCI_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h index 4bc9384046c6..24fbcccd93eb 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_PMU_H__ #define __NVKM_PMU_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h index 9398d9f09339..62c34f98c930 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_THERM_H__ #define __NVKM_THERM_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h index 3693ebf371b6..a8c21c6c800b 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_TIMER_H__ #define __NVKM_TIMER_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h index 2904e67d79d2..7be0e7e7bd77 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_TOP_H__ #define __NVKM_TOP_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/vga.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/vga.h index 312933ad7c2b..15ee5c321574 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/vga.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/vga.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NOUVEAU_VGA_H__ #define __NOUVEAU_VGA_H__ #include diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h index 6a765682fbfa..45053a280930 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_VOLT_H__ #define __NVKM_VOLT_H__ #include diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.h b/drivers/gpu/drm/nouveau/nouveau_abi16.h index 36fde1ff3ad5..195546719bfe 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.h +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NOUVEAU_ABI16_H__ #define __NOUVEAU_ABI16_H__ diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c b/drivers/gpu/drm/nouveau/nouveau_acpi.c index ffb195850314..fe3a10255c36 100644 --- a/drivers/gpu/drm/nouveau/nouveau_acpi.c +++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: MIT #include #include #include diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.h b/drivers/gpu/drm/nouveau/nouveau_acpi.h index b86294fc99e8..1e6e8a8c0455 100644 --- a/drivers/gpu/drm/nouveau/nouveau_acpi.h +++ b/drivers/gpu/drm/nouveau/nouveau_acpi.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NOUVEAU_ACPI_H__ #define __NOUVEAU_ACPI_H__ diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.h b/drivers/gpu/drm/nouveau/nouveau_bo.h index 846f4bdec0de..383ac36d5869 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.h +++ b/drivers/gpu/drm/nouveau/nouveau_bo.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NOUVEAU_BO_H__ #define __NOUVEAU_BO_H__ diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.h b/drivers/gpu/drm/nouveau/nouveau_chan.h index 93814d1d31e4..9307357e1361 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.h +++ b/drivers/gpu/drm/nouveau/nouveau_chan.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NOUVEAU_CHAN_H__ #define __NOUVEAU_CHAN_H__ #include diff --git a/drivers/gpu/drm/nouveau/nouveau_debugfs.h b/drivers/gpu/drm/nouveau/nouveau_debugfs.h index 1d01a82d4b6f..9420a6aca138 100644 --- a/drivers/gpu/drm/nouveau/nouveau_debugfs.h +++ b/drivers/gpu/drm/nouveau/nouveau_debugfs.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NOUVEAU_DEBUGFS_H__ #define __NOUVEAU_DEBUGFS_H__ diff --git a/drivers/gpu/drm/nouveau/nouveau_display.h b/drivers/gpu/drm/nouveau/nouveau_display.h index 311e175f0513..9185f01e2d9b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.h +++ b/drivers/gpu/drm/nouveau/nouveau_display.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NOUVEAU_DISPLAY_H__ #define __NOUVEAU_DISPLAY_H__ #include "nouveau_drv.h" diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index 35ff0ca01a3b..aae035816383 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NOUVEAU_DRV_H__ #define __NOUVEAU_DRV_H__ diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.h b/drivers/gpu/drm/nouveau/nouveau_fence.h index ad27caeca0fd..c9e24baaaa4f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fence.h +++ b/drivers/gpu/drm/nouveau/nouveau_fence.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NOUVEAU_FENCE_H__ #define __NOUVEAU_FENCE_H__ diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.h b/drivers/gpu/drm/nouveau/nouveau_gem.h index fe39998f65cc..03371204a47c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.h +++ b/drivers/gpu/drm/nouveau/nouveau_gem.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NOUVEAU_GEM_H__ #define __NOUVEAU_GEM_H__ diff --git a/drivers/gpu/drm/nouveau/nouveau_ioctl.h b/drivers/gpu/drm/nouveau/nouveau_ioctl.h index 380ede26806c..d17505530e3e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_ioctl.h +++ b/drivers/gpu/drm/nouveau/nouveau_ioctl.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NOUVEAU_IOCTL_H__ #define __NOUVEAU_IOCTL_H__ diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h index b5b5fe40779d..cff7389f6ed3 100644 --- a/drivers/gpu/drm/nouveau/nouveau_reg.h +++ b/drivers/gpu/drm/nouveau/nouveau_reg.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #define NV04_PFB_BOOT_0 0x00100000 # define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003 diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c index 8ebdc74cc0ad..feaac908efed 100644 --- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c +++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: MIT #include #include diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.h b/drivers/gpu/drm/nouveau/nouveau_ttm.h index 89929ad8c7cd..085280754b3e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_ttm.h +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NOUVEAU_TTM_H__ #define __NOUVEAU_TTM_H__ diff --git a/drivers/gpu/drm/nouveau/nouveau_usif.h b/drivers/gpu/drm/nouveau/nouveau_usif.h index c68f1c65af3b..dc90d4a9d0d9 100644 --- a/drivers/gpu/drm/nouveau/nouveau_usif.h +++ b/drivers/gpu/drm/nouveau/nouveau_usif.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NOUVEAU_USIF_H__ #define __NOUVEAU_USIF_H__ diff --git a/drivers/gpu/drm/nouveau/nouveau_vga.c b/drivers/gpu/drm/nouveau/nouveau_vga.c index 8f1ce4833230..8f4b12a8092c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_vga.c +++ b/drivers/gpu/drm/nouveau/nouveau_vga.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: MIT #include #include diff --git a/drivers/gpu/drm/nouveau/nouveau_vga.h b/drivers/gpu/drm/nouveau/nouveau_vga.h index 6a3000c88142..951a83f984dd 100644 --- a/drivers/gpu/drm/nouveau/nouveau_vga.h +++ b/drivers/gpu/drm/nouveau/nouveau_vga.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NOUVEAU_VGA_H__ #define __NOUVEAU_VGA_H__ diff --git a/drivers/gpu/drm/nouveau/nv10_fence.h b/drivers/gpu/drm/nouveau/nv10_fence.h index 7616c66803f8..300cf3fdbb46 100644 --- a/drivers/gpu/drm/nouveau/nv10_fence.h +++ b/drivers/gpu/drm/nouveau/nv10_fence.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NV10_FENCE_H_ #define __NV10_FENCE_H_ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3.h index da130f5058e5..96d934f81600 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ static uint32_t gf100_ce_data[] = { /* 0x0000: ctx_object */ 0x00000000, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3.h index 0b92eb32598d..d3fbd4ab5e31 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ static uint32_t gt215_ce_data[] = { /* 0x0000: ctx_object */ 0x00000000, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/ce/priv.h index 0e3d08f11b0b..b0c8342db15f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_CE_PRIV_H__ #define __NVKM_CE_PRIV_H__ #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h index 6a62021e9861..1d3c5cf7c3b4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_DEVICE_ACPI_H__ #define __NVKM_DEVICE_ACPI_H__ #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.h b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.h index ebcc5c52fbd1..9f6d7f23af8d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_DEVICE_CTRL_H__ #define __NVKM_DEVICE_CTRL_H__ #define nvkm_control(p) container_of((p), struct nvkm_control, object) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h index 2a53e37dfa7a..d8be2f77ac66 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_DEVICE_PRIV_H__ #define __NVKM_DEVICE_PRIV_H__ #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h index adc9d76d09cc..e55054b7329f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NV50_DISP_CHAN_H__ #define __NV50_DISP_CHAN_H__ #define nv50_disp_chan(p) container_of((p), struct nv50_disp_chan, object) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h index 090e869ae612..dcbe60a4b911 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_DISP_CONN_H__ #define __NVKM_DISP_CONN_H__ #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h index 495f665a0ee6..428b3f488f03 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_DISP_DP_H__ #define __NVKM_DISP_DP_H__ #define nvkm_dp(p) container_of((p), struct nvkm_dp, outp) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.c index 10f2aa9f29a4..7147dc6d9018 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: MIT #include "hdmi.h" void pack_hdmi_infoframe(struct packed_hdmi_infoframe *packed_frame, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.h index 45094c6e1425..fb1c3e3c5d4c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_DISP_HDMI_H__ #define __NVKM_DISP_HDMI_H__ #include "ior.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/head.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/head.h index 7d55faf52fcb..7dde6237441d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/head.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/head.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_DISP_HEAD_H__ #define __NVKM_DISP_HEAD_H__ #include "priv.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h index 1681ddccd298..009d3a8b7a50 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_DISP_IOR_H__ #define __NVKM_DISP_IOR_H__ #include "priv.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h index e5d00f478bb1..a677161c7f3a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NV50_DISP_H__ #define __NV50_DISP_H__ #define nv50_disp(p) container_of((p), struct nv50_disp, base) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h index 6c8aa5cfed9d..721b068b87ef 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_DISP_OUTP_H__ #define __NVKM_DISP_OUTP_H__ #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h index ef66c5f38ad5..f815a5342880 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_DISP_PRIV_H__ #define __NVKM_DISP_PRIV_H__ #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h index aee9822a7a87..a1f942793f98 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NV50_DISP_ROOT_H__ #define __NV50_DISP_ROOT_H__ #define nv50_disp_root(p) container_of((p), struct nv50_disp_root, object) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h index 4307cbecd5c5..0c9d9640a59d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_DMA_PRIV_H__ #define __NVKM_DMA_PRIV_H__ #define nvkm_dma(p) container_of((p), struct nvkm_dma, engine) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.h b/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.h index 9fe01fd75474..9c72ee214be7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_DMA_USER_H__ #define __NVKM_DMA_USER_H__ #define nvkm_dmaobj(p) container_of((p), struct nvkm_dmaobj, object) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h index 2c7c5afc1ea5..177e10562600 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_FIFO_CHAN_H__ #define __NVKM_FIFO_CHAN_H__ #define nvkm_fifo_chan(p) container_of((p), struct nvkm_fifo_chan, object) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h index b653664e081b..7c125a15f963 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __GF100_FIFO_CHAN_H__ #define __GF100_FIFO_CHAN_H__ #define gf100_fifo_chan(p) container_of((p), struct gf100_fifo_chan, base) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h index f8557cdfbd81..22698661aa85 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __GK104_FIFO_CHAN_H__ #define __GK104_FIFO_CHAN_H__ #define gk104_fifo_chan(p) container_of((p), struct gk104_fifo_chan, base) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h index 15b06bdf5067..60ca79465aff 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NV04_FIFO_CHAN_H__ #define __NV04_FIFO_CHAN_H__ #define nv04_fifo_chan(p) container_of((p), struct nv04_fifo_chan, base) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h index 2e3c4005b874..5735ff72a9d1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NV50_FIFO_CHAN_H__ #define __NV50_FIFO_CHAN_H__ #define nv50_fifo_chan(p) container_of((p), struct nv50_fifo_chan, base) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h index 68f97ba03df6..b8642490eb2f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __GF100_FIFO_H__ #define __GF100_FIFO_H__ #define gf100_fifo(p) container_of((p), struct gf100_fifo, base) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h index d4e565658f46..c33f4593cbc6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __GK104_FIFO_H__ #define __GK104_FIFO_H__ #define gk104_fifo(p) container_of((p), struct gk104_fifo, base) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h index 1d70542553cc..e5ecceee77ae 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NV04_FIFO_H__ #define __NV04_FIFO_H__ #define nv04_fifo(p) container_of((p), struct nv04_fifo, base) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h index a3994e8db462..87d30b6bd2ea 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NV50_FIFO_H__ #define __NV50_FIFO_H__ #define nv50_fifo(p) container_of((p), struct nv50_fifo, base) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h index d5acbba293f4..c66f5370b21f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_FIFO_PRIV_H__ #define __NVKM_FIFO_PRIV_H__ #define nvkm_fifo(p) container_of((p), struct nvkm_fifo, engine) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/regsnv04.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/regsnv04.h index 49892a5e7201..4445a12b9a26 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/regsnv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/regsnv04.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NV04_FIFO_REGS_H__ #define __NV04_FIFO_REGS_H__ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h index 33e932bd73b1..478b4723d0f9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_GRCTX_NVC0_H__ #define __NVKM_GRCTX_NVC0_H__ #include "gf100.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h index 4d67d90261b8..7917567ade3a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_GRCTX_H__ #define __NVKM_GRCTX_H__ #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h index 0323acb739c8..54e14b4d31b3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ static uint32_t gf100_grgpc_data[] = { /* 0x0000: gpc_mmio_list_head */ 0x00000064, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h index 1bb265917915..67524e615d81 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ static uint32_t gf117_grgpc_data[] = { /* 0x0000: gpc_mmio_list_head */ 0x0000006c, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h index cf8343a693ba..60c8b7e89913 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ static uint32_t gk104_grgpc_data[] = { /* 0x0000: gpc_mmio_list_head */ 0x0000006c, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h index f4bfa109ed27..c99d1566554c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ static uint32_t gk110_grgpc_data[] = { /* 0x0000: gpc_mmio_list_head */ 0x0000006c, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h index 59a3e1b2927f..753aa66729bf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ static uint32_t gk208_grgpc_data[] = { /* 0x0000: gpc_mmio_list_head */ 0x0000006c, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h index 8daa0516704a..db8b294cee39 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ static uint32_t gm107_grgpc_data[] = { /* 0x0000: gpc_mmio_list_head */ 0x0000006c, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3.h index cbf2351f8da8..56162f6a6a94 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ static uint32_t gf100_grhub_data[] = { /* 0x0000: hub_mmio_list_head */ 0x00000300, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3.h index 70830036ffee..9b9f0d93f915 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ static uint32_t gf117_grhub_data[] = { /* 0x0000: hub_mmio_list_head */ 0x00000300, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3.h index 7f2fd84d0c3a..fa11857b9d31 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ static uint32_t gk104_grhub_data[] = { /* 0x0000: hub_mmio_list_head */ 0x00000300, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3.h index 560063789de8..1d741b30a04a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ static uint32_t gk110_grhub_data[] = { /* 0x0000: hub_mmio_list_head */ 0x00000300, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h index 71e85784b615..c24f35ad56a6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ static uint32_t gk208_grhub_data[] = { /* 0x0000: hub_mmio_list_head */ 0x00000300, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h index d85eac6d1c61..649a442b4390 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ static uint32_t gm107_grhub_data[] = { /* 0x0000: hub_mmio_list_head */ 0x00000300, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/os.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/os.h index f87693809c9f..6ac155b9663b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/os.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/os.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_GRAPH_OS_H__ #define __NVKM_GRAPH_OS_H__ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.h index d5a376c4dd0b..4327baea02af 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NV10_GR_H__ #define __NV10_GR_H__ #include "priv.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c index 111c8bb4497b..d837630a3625 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: MIT #include "nv20.h" #include "regs.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h index 979dc5f7b32e..e57407a8a7c3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NV20_GR_H__ #define __NV20_GR_H__ #define nv20_gr(p) container_of((p), struct nv20_gr, base) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c index e59a28a26d65..32d29d3faee0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: MIT #include "nv20.h" #include "regs.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c index e113b2d4c811..f941062c66f0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: MIT #include "nv20.h" #include "regs.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c index 4aac2c224874..785ec956df0f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: MIT #include "nv20.h" #include "regs.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c index 301556503e93..bd610d75c677 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: MIT #include "nv20.h" #include "regs.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c index 5d6926611a5b..89db7f523037 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: MIT #include "nv20.h" #include "regs.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h index 731400937edd..e6128791b2d2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NV40_GR_H__ #define __NV40_GR_H__ #define nv40_gr(p) container_of((p), struct nv40_gr, base) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h index 5b9d99bee207..465f4da0ddfc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NV50_GR_H__ #define __NV50_GR_H__ #define nv50_gr(p) container_of((p), struct nv50_gr, base) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h index d4d5601c51e7..3b30f24032cc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_GR_PRIV_H__ #define __NVKM_GR_PRIV_H__ #define nvkm_gr(p) container_of((p), struct nvkm_gr, engine) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h index dc4f936675ac..fd1b7d35c62b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_GR_REGS_H__ #define __NVKM_GR_REGS_H__ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h index b31fad8bdaad..b3e131538858 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NV31_MPEG_H__ #define __NV31_MPEG_H__ #define nv31_mpeg(p) container_of((p), struct nv31_mpeg, engine) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/priv.h index 26f9d14151e2..667a2d05dd89 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_MPEG_PRIV_H__ #define __NVKM_MPEG_PRIV_H__ #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/priv.h index db305072a82f..86445a2600d0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_MSPDEC_PRIV_H__ #define __NVKM_MSPDEC_PRIV_H__ #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/priv.h index 7708e52c9043..f20b10915db2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_MSPPP_PRIV_H__ #define __NVKM_MSPPP_PRIV_H__ #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/priv.h index 66c36049abca..5cd1e83badbb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_MSVLD_PRIV_H__ #define __NVKM_MSVLD_PRIV_H__ #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/priv.h index 6c300739f621..57bfa3aa1835 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_NVDEC_PRIV_H__ #define __NVKM_NVDEC_PRIV_H__ #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h index c74fd4557d41..461bb219b1c0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_PM_NVC0_H__ #define __NVKM_PM_NVC0_H__ #include "priv.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h index 3f37b713936c..8ed19320fda1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_PM_NV40_H__ #define __NVKM_PM_NV40_H__ #define nv40_pm(p) container_of((p), struct nv40_pm, base) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h index 9fad3611a843..cd6f8f79b235 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_PM_PRIV_H__ #define __NVKM_PM_PRIV_H__ #define nvkm_pm(p) container_of((p), struct nvkm_pm, engine) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/g98.fuc0s.h b/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/g98.fuc0s.h index 6278a0c5fe83..fe90f2e05853 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/g98.fuc0s.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/g98.fuc0s.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ static uint32_t g98_sec_data[] = { /* 0x0000: ctx_dma */ /* 0x0000: ctx_dma_query */ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h index ab0165e2d1a3..b331b00517e6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_SEC2_PRIV_H__ #define __NVKM_SEC2_PRIV_H__ #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.h b/drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.h index d42862fc43fd..32de53427aa4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_SW_CHAN_H__ #define __NVKM_SW_CHAN_H__ #define nvkm_sw_chan(p) container_of((p), struct nvkm_sw_chan, object) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h index 459afd30a484..6d364d7b406a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_SW_NV50_H__ #define __NVKM_SW_NV50_H__ #define nv50_sw_chan(p) container_of((p), struct nv50_sw_chan, base) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.h b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.h index d7034950ba87..d2f846499b92 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_NVSW_H__ #define __NVKM_NVSW_H__ #define nvkm_nvsw(p) container_of((p), struct nvkm_nvsw, object) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/sw/priv.h index 4aca1791abc3..6d18fc6180f2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_SW_PRIV_H__ #define __NVKM_SW_PRIV_H__ #define nvkm_sw(p) container_of((p), struct nvkm_sw, engine) diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/priv.h b/drivers/gpu/drm/nouveau/nvkm/falcon/priv.h index d515ad994199..900fe1d37b4d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/falcon/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_FALCON_PRIV_H__ #define __NVKM_FALCON_PRIV_H__ #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h index 4f2b66e8d795..4ae4c7145712 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __GF100_BAR_H__ #define __GF100_BAR_H__ #define gf100_bar(p) container_of((p), struct gf100_bar, base) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h index 2fe833f6d9f7..e4193deb2e51 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NV50_BAR_H__ #define __NV50_BAR_H__ #define nv50_bar(p) container_of((p), struct nv50_bar, base) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h index 01ba5b26666e..869ad184f923 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_BAR_PRIV_H__ #define __NVKM_BAR_PRIV_H__ #define nvkm_bar(p) container_of((p), struct nvkm_bar, subdev) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/priv.h index 33435ca16311..fac1bff1311b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_BIOS_PRIV_H__ #define __NVKM_BIOS_PRIV_H__ #define nvkm_bios(p) container_of((p), struct nvkm_bios, subdev) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h index 17ac1812a928..217a0a4a3bc5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_BUS_HWSQ_H__ #define __NVKM_BUS_HWSQ_H__ #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/priv.h index ef01e569352d..76f7ba1c6494 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_BUS_PRIV_H__ #define __NVKM_BUS_PRIV_H__ #define nvkm_bus(p) container_of((p), struct nvkm_bus, subdev) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.h index 1ea886a4301f..34754efbfb1e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_CLK_NVA3_H__ #define __NVKM_CLK_NVA3_H__ #include "priv.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h index f134d979d884..7c7713238ec4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NV50_CLK_H__ #define __NV50_CLK_H__ #define nv50_clk(p) container_of((p), struct nv50_clk, base) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h index 9a39f1fd2976..631907564e71 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_PLL_H__ #define __NVKM_PLL_H__ #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/priv.h index b656177923fb..81dfb37480ae 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_CLK_PRIV_H__ #define __NVKM_CLK_PRIV_H__ #define nvkm_clk(p) container_of((p), struct nvkm_clk, subdev) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h index d0715fe84328..e4b362d3449b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_CLK_SEQ_H__ #define __NVKM_CLK_SEQ_H__ #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h index b18e49847eee..15b029ddf6df 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NV04_DEVINIT_H__ #define __NV04_DEVINIT_H__ #define nv04_devinit(p) container_of((p), struct nv04_devinit, base) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h index 72d130bb7f7c..e8d37a6145a2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NV50_DEVINIT_H__ #define __NV50_DEVINIT_H__ #define nv50_devinit(p) container_of((p), struct nv50_devinit, base) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h index 5b3097a586dd..94723352137a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_DEVINIT_PRIV_H__ #define __NVKM_DEVINIT_PRIV_H__ #define nvkm_devinit(p) container_of((p), struct nvkm_devinit, subdev) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h index ab261310753a..2ed7cdaab37c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_RAM_NVC0_H__ #define __NVKM_RAM_NVC0_H__ #define gf100_fb(p) container_of((p), struct gf100_fb, base) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h index dacc696387b6..5e2b0c9539ed 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_FB_NV50_H__ #define __NVKM_FB_NV50_H__ #define nv50_fb(p) container_of((p), struct nv50_fb, base) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h index 1e4ad61c19e1..c4e9f55af283 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_FB_PRIV_H__ #define __NVKM_FB_PRIV_H__ #define nvkm_fb(p) container_of((p), struct nvkm_fb, subdev) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h index 330132e95b6f..d723a9b4e3c4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_FB_RAM_PRIV_H__ #define __NVKM_FB_RAM_PRIV_H__ #include "priv.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h index a65fa5586af8..247c0f8a723b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_FBRAM_FUC_H__ #define __NVKM_FBRAM_FUC_H__ #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.h index 11f6bb2936b9..a87de0871dfc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NV40_FB_RAM_H__ #define __NV40_FB_RAM_H__ #define nv40_ram(p) container_of((p), struct nv40_ram, base) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h index d8f5053e8e2a..aba5b73781d3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_FBRAM_SEQ_H__ #define __NVKM_FBRAM_SEQ_H__ #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/regsnv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/regsnv04.h index ad26fcbe9e06..8098cd77dfdd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/regsnv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/regsnv04.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_FB_REGS_04_H__ #define __NVKM_FB_REGS_04_H__ diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h index 3a5595a9e457..2edc612408dd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_FUSE_PRIV_H__ #define __NVKM_FUSE_PRIV_H__ #define nvkm_fuse(p) container_of((p), struct nvkm_fuse, subdev) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h index 9759f13447bf..59e39affe2a0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_GPIO_PRIV_H__ #define __NVKM_GPIO_PRIV_H__ #define nvkm_gpio(p) container_of((p), struct nvkm_gpio, subdev) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.h b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.h index 08f6b2ee64ab..30b48896965e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_I2C_AUX_H__ #define __NVKM_I2C_AUX_H__ #include "pad.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bus.h b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bus.h index 465464bba58b..4c236ab34929 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bus.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bus.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_I2C_BUS_H__ #define __NVKM_I2C_BUS_H__ #include "pad.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.h b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.h index 33f0c809e583..461016814f4f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_I2C_PAD_H__ #define __NVKM_I2C_PAD_H__ #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h index f476a69b6cb7..bd86bc298ebe 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_I2C_PRIV_H__ #define __NVKM_I2C_PRIV_H__ #define nvkm_i2c(p) container_of((p), struct nvkm_i2c, subdev) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/priv.h index 504a6d37ec50..302d69e384d8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_IBUS_PRIV_H__ #define __NVKM_IBUS_PRIV_H__ diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/priv.h index bd599b8252ca..cc09c6c504af 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_ICCSENSE_PRIV_H__ #define __NVKM_ICCSENSE_PRIV_H__ #define nvkm_iccsense(p) container_of((p), struct nvkm_iccsense, subdev) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h index b9e4751b9921..f5da8fcbdde3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_INSTMEM_PRIV_H__ #define __NVKM_INSTMEM_PRIV_H__ #define nvkm_instmem(p) container_of((p), struct nvkm_instmem, subdev) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h index 9dcde43c0f3c..2fcf18e46ce3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_LTC_PRIV_H__ #define __NVKM_LTC_PRIV_H__ #define nvkm_ltc(p) container_of((p), struct nvkm_ltc, subdev) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h index eb91a4cf452b..4aab753a6040 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_MC_PRIV_H__ #define __NVKM_MC_PRIV_H__ #define nvkm_mc(p) container_of((p), struct nvkm_mc, subdev) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/priv.h index 2ad1102a4e31..07f2fcd18f3d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_MMU_PRIV_H__ #define __NVKM_MMU_PRIV_H__ #define nvkm_mmu(p) container_of((p), struct nvkm_mmu, subdev) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.h index 011a67fe4a8b..d9676b282ac0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVMXM_MXMS_H__ #define __NVMXM_MXMS_H__ #include "priv.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/priv.h index 6767c2279e7c..fc8f69e6fc64 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_MXM_PRIV_H__ #define __NVKM_MXM_PRIV_H__ #define nvkm_mxm(p) container_of((p), struct nvkm_mxm, subdev) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.h index edb7f00f0de5..ad4d3621d02b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #include "priv.h" #if defined(CONFIG_AGP) || (defined(CONFIG_AGP_MODULE) && defined(MODULE)) #ifndef __NVKM_PCI_AGP_H__ diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h index c17f6063c9ea..7009aad86b6e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_PCI_PRIV_H__ #define __NVKM_PCI_PRIV_H__ #define nvkm_pci(p) container_of((p), struct nvkm_pci, subdev) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3.h index 1dbe593e5960..4cf888f2bd03 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ static uint32_t gf100_pmu_data[] = { /* 0x0000: proc_kern */ 0x52544e49, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4.h index e1e981966c2d..e80eff18e5d4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ static uint32_t gf119_pmu_data[] = { /* 0x0000: proc_kern */ 0x52544e49, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h index e0222cb832fb..275ec71bc0c0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ static uint32_t gk208_pmu_data[] = { /* 0x0000: proc_kern */ 0x52544e49, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gt215.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gt215.fuc3.h index defddf5957ee..4b071e9bec7d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gt215.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gt215.fuc3.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ static uint32_t gt215_pmu_data[] = { /* 0x0000: proc_kern */ 0x52544e49, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/os.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/os.h index 30d9480b9be5..0d5abf27ee52 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/os.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/os.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_PWR_OS_H__ #define __NVKM_PWR_OS_H__ diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c index 7b052879af72..22eaebefced3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: MIT #ifndef __NVKM_PMU_MEMX_H__ #define __NVKM_PMU_MEMX_H__ #include "priv.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h index e9c6f9725afe..26d73f9cd6d3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_PMU_PRIV_H__ #define __NVKM_PMU_PRIV_H__ #define nvkm_pmu(p) container_of((p), struct nvkm_pmu, subdev) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h index 3b8878486faa..89e97294b182 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_TIMER_PRIV_H__ #define __NVKM_TIMER_PRIV_H__ #define nvkm_timer(p) container_of((p), struct nvkm_timer, subdev) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/regsnv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/regsnv04.h index 23d07f5f44d9..34a740bc6e4a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/regsnv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/regsnv04.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #define NV04_PTIMER_INTR_0 0x009100 #define NV04_PTIMER_INTR_EN_0 0x009140 #define NV04_PTIMER_NUMERATOR 0x009200 diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/top/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/top/priv.h index 4f49b0acaa0e..a16baa2941cf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/top/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/top/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_TOP_PRIV_H__ #define __NVKM_TOP_PRIV_H__ #define nvkm_top(p) container_of((p), struct nvkm_top, subdev) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/priv.h index 1a8ad560321b..75f13a34671f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/priv.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_VOLT_PRIV_H__ #define __NVKM_VOLT_PRIV_H__ #define nvkm_volt(p) container_of((p), struct nvkm_volt, subdev) -- cgit v1.2.3 From b0f84a84fff180718995b1269da2988e5b28be42 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 5 Jul 2019 15:11:42 +1000 Subject: drm/nouveau: fix bogus GPL-2 license header The bulk SPDX addition made all these files into GPL-2.0 licensed files. However the remainder of the project is MIT-licensed, these files were simply missing the boiler plate and got caught up in the global update. Fixes: 96ac6d4351004 (treewide: Add SPDX license identifier - Kbuild) Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/Kbuild | 2 +- drivers/gpu/drm/nouveau/dispnv04/Kbuild | 2 +- drivers/gpu/drm/nouveau/dispnv50/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvif/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/core/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/dma/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/mpeg/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/msenc/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/nvdec/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/nvenc/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/sec2/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/vic/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/falcon/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/bios/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/bus/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fault/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fuse/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/gsp/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/mxm/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/top/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/volt/Kbuild | 2 +- 55 files changed, 55 insertions(+), 55 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/Kbuild b/drivers/gpu/drm/nouveau/Kbuild index b0f53f4f71bf..7a62fa04272d 100644 --- a/drivers/gpu/drm/nouveau/Kbuild +++ b/drivers/gpu/drm/nouveau/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT ccflags-y += -I $(srctree)/$(src)/include ccflags-y += -I $(srctree)/$(src)/include/nvkm ccflags-y += -I $(srctree)/$(src)/nvkm diff --git a/drivers/gpu/drm/nouveau/dispnv04/Kbuild b/drivers/gpu/drm/nouveau/dispnv04/Kbuild index 65a3990b4e16..975c4e226936 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/Kbuild +++ b/drivers/gpu/drm/nouveau/dispnv04/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nouveau-y += dispnv04/arb.o nouveau-y += dispnv04/crtc.o nouveau-y += dispnv04/cursor.o diff --git a/drivers/gpu/drm/nouveau/dispnv50/Kbuild b/drivers/gpu/drm/nouveau/dispnv50/Kbuild index 475c630308d1..e0c435eae664 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/Kbuild +++ b/drivers/gpu/drm/nouveau/dispnv50/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nouveau-y += dispnv50/disp.o nouveau-y += dispnv50/lut.o diff --git a/drivers/gpu/drm/nouveau/nvif/Kbuild b/drivers/gpu/drm/nouveau/nvif/Kbuild index 7eebd7d18b6d..50d583d63807 100644 --- a/drivers/gpu/drm/nouveau/nvif/Kbuild +++ b/drivers/gpu/drm/nouveau/nvif/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvif-y := nvif/object.o nvif-y += nvif/client.o nvif-y += nvif/device.o diff --git a/drivers/gpu/drm/nouveau/nvkm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/Kbuild index a8ec75cf02dc..b53de9ba8c73 100644 --- a/drivers/gpu/drm/nouveau/nvkm/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT include $(src)/nvkm/core/Kbuild include $(src)/nvkm/falcon/Kbuild include $(src)/nvkm/subdev/Kbuild diff --git a/drivers/gpu/drm/nouveau/nvkm/core/Kbuild b/drivers/gpu/drm/nouveau/nvkm/core/Kbuild index 01de22144259..2b471ab585b4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/core/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y := nvkm/core/client.o nvkm-y += nvkm/core/engine.o nvkm-y += nvkm/core/enum.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild index 5a43bcfb3622..c6dfed18f35b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/engine/falcon.o nvkm-y += nvkm/engine/xtensa.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild index ad1bcfa6fc6c..b596b990519c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild @@ -1,2 +1,2 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/engine/bsp/g84.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild index 157a70721629..ba88613e1e46 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/engine/ce/gt215.o nvkm-y += nvkm/engine/ce/gf100.o nvkm-y += nvkm/engine/ce/gk104.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild index 95708b59496c..ffad341f42bc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild @@ -1,2 +1,2 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/engine/cipher/g84.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild index 206163da52e1..293c57678dab 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/engine/device/acpi.o nvkm-y += nvkm/engine/device/base.o nvkm-y += nvkm/engine/device/ctrl.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild index dbfda73cfea6..0d584d0da59c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/engine/disp/base.o nvkm-y += nvkm/engine/disp/nv04.o nvkm-y += nvkm/engine/disp/nv50.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/dma/Kbuild index 3e2680cbe370..a0e551b92c8d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/engine/dma/base.o nvkm-y += nvkm/engine/dma/nv04.o nvkm-y += nvkm/engine/dma/nv50.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild index 1f0eddacc9b7..90e9a0972a44 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/engine/fifo/base.o nvkm-y += nvkm/engine/fifo/nv04.o nvkm-y += nvkm/engine/fifo/nv10.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild index 50bd9830694f..73724a8cb861 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/engine/gr/base.o nvkm-y += nvkm/engine/gr/nv04.o nvkm-y += nvkm/engine/gr/nv10.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/Kbuild index 651270137268..8d2d9eae5604 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/engine/mpeg/nv31.o nvkm-y += nvkm/engine/mpeg/nv40.o nvkm-y += nvkm/engine/mpeg/nv44.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msenc/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/msenc/Kbuild index b808d9e9c964..4bf033ff4d41 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msenc/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msenc/Kbuild @@ -1,2 +1,2 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT #nvkm-y += nvkm/engine/msenc/base.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild index df50010e5f2c..0cd957d72593 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/engine/mspdec/base.o nvkm-y += nvkm/engine/mspdec/g98.o nvkm-y += nvkm/engine/mspdec/gt215.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild index 322e3470b2f1..788ce7255b61 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/engine/msppp/base.o nvkm-y += nvkm/engine/msppp/g98.o nvkm-y += nvkm/engine/msppp/gt215.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild index beddd82f5755..d68b4431cd80 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/engine/msvld/base.o nvkm-y += nvkm/engine/msvld/g98.o nvkm-y += nvkm/engine/msvld/gt215.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/Kbuild index 29d7ddb56f0e..cdf631822282 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/Kbuild @@ -1,3 +1,3 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/engine/nvdec/base.o nvkm-y += nvkm/engine/nvdec/gp102.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/Kbuild index 85725b11200b..f316de8d45a8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/Kbuild @@ -1,2 +1,2 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT #nvkm-y += nvkm/engine/nvenc/base.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild index ceb7302e292f..2cc8a5f6fe0c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/engine/pm/base.o nvkm-y += nvkm/engine/pm/nv40.o nvkm-y += nvkm/engine/pm/nv50.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild index f72ee558f8e8..b6e02ceb1c5a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild @@ -1,2 +1,2 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/engine/sec/g98.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/Kbuild index 9a2f4f669291..97c4696171f0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/engine/sec2/base.o nvkm-y += nvkm/engine/sec2/gp102.o nvkm-y += nvkm/engine/sec2/tu102.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild index 91cf08084bc1..94fe25964f51 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/engine/sw/base.o nvkm-y += nvkm/engine/sw/nv04.o nvkm-y += nvkm/engine/sw/nv10.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/vic/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/vic/Kbuild index 9281c82ea99c..70164f482cc5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/vic/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/vic/Kbuild @@ -1,2 +1,2 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT #nvkm-y += nvkm/engine/vic/base.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild index 456e43fd1f6c..d48ea0fd1d27 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild @@ -1,2 +1,2 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/engine/vp/g84.o diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/Kbuild b/drivers/gpu/drm/nouveau/nvkm/falcon/Kbuild index 8afbf0f9bc86..b5665ada850a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/falcon/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/falcon/base.o nvkm-y += nvkm/falcon/v1.o nvkm-y += nvkm/falcon/msgqueue.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild index d8c287173f4c..4e136f3d7c28 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT include $(src)/nvkm/subdev/bar/Kbuild include $(src)/nvkm/subdev/bios/Kbuild include $(src)/nvkm/subdev/bus/Kbuild diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild index 8210bf9c52a5..8faee3317a74 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/bar/base.o nvkm-y += nvkm/subdev/bar/nv50.o nvkm-y += nvkm/subdev/bar/g84.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/Kbuild index bb4759cc38a6..5a970fb8f7ee 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/bios/base.o nvkm-y += nvkm/subdev/bios/bit.o nvkm-y += nvkm/subdev/bios/boost.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/Kbuild index 409137fbdddf..01d737989d00 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/bus/base.o nvkm-y += nvkm/subdev/bus/hwsq.o nvkm-y += nvkm/subdev/bus/nv04.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild index 0a8a7072bcbc..dcecd499d8df 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/clk/base.o nvkm-y += nvkm/subdev/clk/nv04.o nvkm-y += nvkm/subdev/clk/nv40.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild index f054c44acab2..b3429371ed82 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/devinit/base.o nvkm-y += nvkm/subdev/devinit/nv04.o nvkm-y += nvkm/subdev/devinit/nv05.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/Kbuild index c9bcf3744e5c..53b9d638f2c8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/fault/base.o nvkm-y += nvkm/subdev/fault/user.o nvkm-y += nvkm/subdev/fault/gp100.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild index 88b1668929ba..43a42159a3d0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/fb/base.o nvkm-y += nvkm/subdev/fb/nv04.o nvkm-y += nvkm/subdev/fb/nv10.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/Kbuild index 9626715768c8..8e7cd9d27f23 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/fuse/base.o nvkm-y += nvkm/subdev/fuse/nv50.o nvkm-y += nvkm/subdev/fuse/gf100.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild index 0169fc30a2f9..b2ad5922a1c2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/gpio/base.o nvkm-y += nvkm/subdev/gpio/nv10.o nvkm-y += nvkm/subdev/gpio/nv50.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/Kbuild index fa566ea6cb95..e7c4f068936e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/Kbuild @@ -1,2 +1,2 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/gsp/gv100.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild index 69f341e11d70..723d0284caef 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/i2c/base.o nvkm-y += nvkm/subdev/i2c/nv04.o nvkm-y += nvkm/subdev/i2c/nv4e.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild index 557530355064..127efb51f67d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/ibus/gf100.o nvkm-y += nvkm/subdev/ibus/gf117.o nvkm-y += nvkm/subdev/ibus/gk104.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/Kbuild index 52eb0746c750..6634bcdc5eeb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/Kbuild @@ -1,3 +1,3 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/iccsense/base.o nvkm-y += nvkm/subdev/iccsense/gf100.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/Kbuild index e0031b5c06b1..06cbe19ce376 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/instmem/base.o nvkm-y += nvkm/subdev/instmem/nv04.o nvkm-y += nvkm/subdev/instmem/nv40.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild index 61f655c2de0c..2b6d36ea7067 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/ltc/base.o nvkm-y += nvkm/subdev/ltc/gf100.o nvkm-y += nvkm/subdev/ltc/gk104.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild index 15da199d2fca..2585ef07532a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/mc/base.o nvkm-y += nvkm/subdev/mc/nv04.o nvkm-y += nvkm/subdev/mc/nv11.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild index 697dc22c937c..a602b0cb5b31 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/mmu/base.o nvkm-y += nvkm/subdev/mmu/nv04.o nvkm-y += nvkm/subdev/mmu/nv41.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/Kbuild index 7a549386e675..5124a0c41367 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/mxm/base.o nvkm-y += nvkm/subdev/mxm/mxms.o nvkm-y += nvkm/subdev/mxm/nv50.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild index 6fbd008d6f10..174bdf995271 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/pci/agp.o nvkm-y += nvkm/subdev/pci/base.o nvkm-y += nvkm/subdev/pci/pcie.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild index 132ae3341d55..e37b6e45eaa2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/pmu/base.o nvkm-y += nvkm/subdev/pmu/memx.o nvkm-y += nvkm/subdev/pmu/gt215.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/Kbuild index 51b33799cfdb..f3dee2693c79 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/secboot/base.o nvkm-y += nvkm/subdev/secboot/hs_ucode.o nvkm-y += nvkm/subdev/secboot/ls_ucode_gr.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild index 0cc1439d863b..9aa76a2befa8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/therm/base.o nvkm-y += nvkm/subdev/therm/fan.o nvkm-y += nvkm/subdev/therm/fannil.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild index a4aa8e621eb2..f710da4427cf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/timer/base.o nvkm-y += nvkm/subdev/timer/nv04.o nvkm-y += nvkm/subdev/timer/nv40.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/top/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/top/Kbuild index e0b27242eeea..438d9d78ab52 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/top/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/top/Kbuild @@ -1,3 +1,3 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/top/base.o nvkm-y += nvkm/subdev/top/gk104.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/Kbuild index e80bc64b638a..523a7cd155a6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/Kbuild @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/volt/base.o nvkm-y += nvkm/subdev/volt/gpio.o nvkm-y += nvkm/subdev/volt/nv40.o -- cgit v1.2.3 From 68bf8b577977a2804af82ffe03ce25d952f82fd2 Mon Sep 17 00:00:00 2001 From: Karol Herbst Date: Tue, 18 Jun 2019 13:01:33 +0200 Subject: drm/nouveau/hwmon: return EINVAL if the GPU is powered down for sensors reads fixes bogus values userspace gets from hwmon while the GPU is powered down Signed-off-by: Karol Herbst Reviewed-by: Rhys Kidd Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_hwmon.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_hwmon.c b/drivers/gpu/drm/nouveau/nouveau_hwmon.c index 08a1ab6b150d..6af2d299c3f9 100644 --- a/drivers/gpu/drm/nouveau/nouveau_hwmon.c +++ b/drivers/gpu/drm/nouveau/nouveau_hwmon.c @@ -428,6 +428,8 @@ nouveau_temp_read(struct device *dev, u32 attr, int channel, long *val) switch (attr) { case hwmon_temp_input: + if (drm_dev->switch_power_state != DRM_SWITCH_POWER_ON) + return -EINVAL; ret = nvkm_therm_temp_get(therm); *val = ret < 0 ? ret : (ret * 1000); break; @@ -474,6 +476,8 @@ nouveau_fan_read(struct device *dev, u32 attr, int channel, long *val) switch (attr) { case hwmon_fan_input: + if (drm_dev->switch_power_state != DRM_SWITCH_POWER_ON) + return -EINVAL; *val = nvkm_therm_fan_sense(therm); break; default: @@ -496,6 +500,8 @@ nouveau_in_read(struct device *dev, u32 attr, int channel, long *val) switch (attr) { case hwmon_in_input: + if (drm_dev->switch_power_state != DRM_SWITCH_POWER_ON) + return -EINVAL; ret = nvkm_volt_get(volt); *val = ret < 0 ? ret : (ret / 1000); break; @@ -527,6 +533,8 @@ nouveau_pwm_read(struct device *dev, u32 attr, int channel, long *val) *val = therm->attr_get(therm, NVKM_THERM_ATTR_FAN_MODE); break; case hwmon_pwm_input: + if (drm_dev->switch_power_state != DRM_SWITCH_POWER_ON) + return -EINVAL; *val = therm->fan_get(therm); break; default: @@ -548,6 +556,8 @@ nouveau_power_read(struct device *dev, u32 attr, int channel, long *val) switch (attr) { case hwmon_power_input: + if (drm_dev->switch_power_state != DRM_SWITCH_POWER_ON) + return -EINVAL; *val = nvkm_iccsense_read_all(iccsense); break; case hwmon_power_max: -- cgit v1.2.3 From d304654bd79332ace9ac46b9a3d8de60acb15da3 Mon Sep 17 00:00:00 2001 From: Ralph Campbell Date: Fri, 14 Jun 2019 13:20:03 -0700 Subject: drm/nouveau/dmem: missing mutex_lock in error path In nouveau_dmem_pages_alloc(), the drm->dmem->mutex is unlocked before calling nouveau_dmem_chunk_alloc() as shown when CONFIG_PROVE_LOCKING is enabled: [ 1294.871933] ===================================== [ 1294.876656] WARNING: bad unlock balance detected! [ 1294.881375] 5.2.0-rc3+ #5 Not tainted [ 1294.885048] ------------------------------------- [ 1294.889773] test-malloc-vra/6299 is trying to release lock (&drm->dmem->mutex) at: [ 1294.897482] [] nouveau_dmem_migrate_alloc_and_copy+0x79f/0xbf0 [nouveau] [ 1294.905782] but there are no more locks to release! [ 1294.910690] [ 1294.910690] other info that might help us debug this: [ 1294.917249] 1 lock held by test-malloc-vra/6299: [ 1294.921881] #0: 0000000016e10454 (&mm->mmap_sem#2){++++}, at: nouveau_svmm_bind+0x142/0x210 [nouveau] [ 1294.931313] [ 1294.931313] stack backtrace: [ 1294.935702] CPU: 4 PID: 6299 Comm: test-malloc-vra Not tainted 5.2.0-rc3+ #5 [ 1294.942786] Hardware name: ASUS X299-A/PRIME X299-A, BIOS 1401 05/21/2018 [ 1294.949590] Call Trace: [ 1294.952059] dump_stack+0x7c/0xc0 [ 1294.955469] ? nouveau_dmem_migrate_alloc_and_copy+0x79f/0xbf0 [nouveau] [ 1294.962213] print_unlock_imbalance_bug.cold.52+0xca/0xcf [ 1294.967641] lock_release+0x306/0x380 [ 1294.971383] ? nouveau_dmem_migrate_alloc_and_copy+0x79f/0xbf0 [nouveau] [ 1294.978089] ? lock_downgrade+0x2d0/0x2d0 [ 1294.982121] ? find_held_lock+0xac/0xd0 [ 1294.985979] __mutex_unlock_slowpath+0x8f/0x3f0 [ 1294.990540] ? wait_for_completion+0x230/0x230 [ 1294.995002] ? rwlock_bug.part.2+0x60/0x60 [ 1294.999197] nouveau_dmem_migrate_alloc_and_copy+0x79f/0xbf0 [nouveau] [ 1295.005751] ? page_mapping+0x98/0x110 [ 1295.009511] migrate_vma+0xa74/0x1090 [ 1295.013186] ? move_to_new_page+0x480/0x480 [ 1295.017400] ? __kmalloc+0x153/0x300 [ 1295.021052] ? nouveau_dmem_migrate_vma+0xd8/0x1e0 [nouveau] [ 1295.026796] nouveau_dmem_migrate_vma+0x157/0x1e0 [nouveau] [ 1295.032466] ? nouveau_dmem_init+0x490/0x490 [nouveau] [ 1295.037612] ? vmacache_find+0xc2/0x110 [ 1295.041537] nouveau_svmm_bind+0x1b4/0x210 [nouveau] [ 1295.046583] ? nouveau_svm_fault+0x13e0/0x13e0 [nouveau] [ 1295.051912] drm_ioctl_kernel+0x14d/0x1a0 [ 1295.055930] ? drm_setversion+0x330/0x330 [ 1295.059971] drm_ioctl+0x308/0x530 [ 1295.063384] ? drm_version+0x150/0x150 [ 1295.067153] ? find_held_lock+0xac/0xd0 [ 1295.070996] ? __pm_runtime_resume+0x3f/0xa0 [ 1295.075285] ? mark_held_locks+0x29/0xa0 [ 1295.079230] ? _raw_spin_unlock_irqrestore+0x3c/0x50 [ 1295.084232] ? lockdep_hardirqs_on+0x17d/0x250 [ 1295.088768] nouveau_drm_ioctl+0x9a/0x100 [nouveau] [ 1295.093661] do_vfs_ioctl+0x137/0x9a0 [ 1295.097341] ? ioctl_preallocate+0x140/0x140 [ 1295.101623] ? match_held_lock+0x1b/0x230 [ 1295.105646] ? match_held_lock+0x1b/0x230 [ 1295.109660] ? find_held_lock+0xac/0xd0 [ 1295.113512] ? __do_page_fault+0x324/0x630 [ 1295.117617] ? lock_downgrade+0x2d0/0x2d0 [ 1295.121648] ? mark_held_locks+0x79/0xa0 [ 1295.125583] ? handle_mm_fault+0x352/0x430 [ 1295.129687] ksys_ioctl+0x60/0x90 [ 1295.133020] ? mark_held_locks+0x29/0xa0 [ 1295.136964] __x64_sys_ioctl+0x3d/0x50 [ 1295.140726] do_syscall_64+0x68/0x250 [ 1295.144400] entry_SYSCALL_64_after_hwframe+0x49/0xbe [ 1295.149465] RIP: 0033:0x7f1a3495809b [ 1295.153053] Code: 0f 1e fa 48 8b 05 ed bd 0c 00 64 c7 00 26 00 00 00 48 c7 c0 ff ff ff ff c3 66 0f 1f 44 00 00 f3 0f 1e fa b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d bd bd 0c 00 f7 d8 64 89 01 48 [ 1295.171850] RSP: 002b:00007ffef7ed1358 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 [ 1295.179451] RAX: ffffffffffffffda RBX: 00007ffef7ed1628 RCX: 00007f1a3495809b [ 1295.186601] RDX: 00007ffef7ed13b0 RSI: 0000000040406449 RDI: 0000000000000004 [ 1295.193759] RBP: 00007ffef7ed13b0 R08: 0000000000000000 R09: 000000000157e770 [ 1295.200917] R10: 000000000151c010 R11: 0000000000000246 R12: 0000000040406449 [ 1295.208083] R13: 0000000000000004 R14: 0000000000000000 R15: 0000000000000000 Reacquire the lock before continuing to the next page. Signed-off-by: Ralph Campbell Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_dmem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_dmem.c b/drivers/gpu/drm/nouveau/nouveau_dmem.c index 40c47d6a7d78..745e197a4775 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dmem.c +++ b/drivers/gpu/drm/nouveau/nouveau_dmem.c @@ -385,9 +385,10 @@ nouveau_dmem_pages_alloc(struct nouveau_drm *drm, ret = nouveau_dmem_chunk_alloc(drm); if (ret) { if (c) - break; + return 0; return ret; } + mutex_lock(&drm->dmem->mutex); continue; } -- cgit v1.2.3 From 09b90e2fe35faeace2488234e2a7728f2ea8ba26 Mon Sep 17 00:00:00 2001 From: Yongxin Liu Date: Mon, 1 Jul 2019 09:46:22 +0800 Subject: drm/nouveau: fix memory leak in nouveau_conn_reset() In nouveau_conn_reset(), if connector->state is true, __drm_atomic_helper_connector_destroy_state() will be called, but the memory pointed by asyc isn't freed. Memory leak happens in the following function __drm_atomic_helper_connector_reset(), where newly allocated asyc->state will be assigned to connector->state. So using nouveau_conn_atomic_destroy_state() instead of __drm_atomic_helper_connector_destroy_state to free the "old" asyc. Here the is the log showing memory leak. unreferenced object 0xffff8c5480483c80 (size 192): comm "kworker/0:2", pid 188, jiffies 4294695279 (age 53.179s) hex dump (first 32 bytes): 00 f0 ba 7b 54 8c ff ff 00 00 00 00 00 00 00 00 ...{T........... 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ backtrace: [<000000005005c0d0>] kmem_cache_alloc_trace+0x195/0x2c0 [<00000000a122baed>] nouveau_conn_reset+0x25/0xc0 [nouveau] [<000000004fd189a2>] nouveau_connector_create+0x3a7/0x610 [nouveau] [<00000000c73343a8>] nv50_display_create+0x343/0x980 [nouveau] [<000000002e2b03c3>] nouveau_display_create+0x51f/0x660 [nouveau] [<00000000c924699b>] nouveau_drm_device_init+0x182/0x7f0 [nouveau] [<00000000cc029436>] nouveau_drm_probe+0x20c/0x2c0 [nouveau] [<000000007e961c3e>] local_pci_probe+0x47/0xa0 [<00000000da14d569>] work_for_cpu_fn+0x1a/0x30 [<0000000028da4805>] process_one_work+0x27c/0x660 [<000000001d415b04>] worker_thread+0x22b/0x3f0 [<0000000003b69f1f>] kthread+0x12f/0x150 [<00000000c94c29b7>] ret_from_fork+0x3a/0x50 Signed-off-by: Yongxin Liu Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_connector.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index caa8c7595889..8f15281faa79 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -252,7 +252,7 @@ nouveau_conn_reset(struct drm_connector *connector) return; if (connector->state) - __drm_atomic_helper_connector_destroy_state(connector->state); + nouveau_conn_atomic_destroy_state(connector, connector->state); __drm_atomic_helper_connector_reset(connector, &asyc->state); asyc->dither.mode = DITHERING_MODE_AUTO; asyc->dither.depth = DITHERING_DEPTH_AUTO; -- cgit v1.2.3 From 5210e967d3c9d32b5394c1f86edebb03e3202954 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 2 Jul 2019 07:52:15 +1000 Subject: drm/nouveau/flcn/gp102-: improve implementation of bind_context() on SEC2/GSP Fixes various issues encountered while attempting to initialise ACR. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/falcon/v1.c | 36 ++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/v1.c b/drivers/gpu/drm/nouveau/nvkm/falcon/v1.c index 9def926f24d4..6d978feebbd7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/falcon/v1.c +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/v1.c @@ -182,6 +182,7 @@ nvkm_falcon_v1_read_dmem(struct nvkm_falcon *falcon, u32 start, u32 size, static void nvkm_falcon_v1_bind_context(struct nvkm_falcon *falcon, struct nvkm_memory *ctx) { + struct nvkm_device *device = falcon->owner->device; u32 inst_loc; u32 fbif; @@ -233,6 +234,41 @@ nvkm_falcon_v1_bind_context(struct nvkm_falcon *falcon, struct nvkm_memory *ctx) nvkm_falcon_mask(falcon, 0x090, 0x10000, 0x10000); nvkm_falcon_mask(falcon, 0x0a4, 0x8, 0x8); + + /* Not sure if this is a WAR for a HW issue, or some additional + * programming sequence that's needed to properly complete the + * context switch we trigger above. + * + * Fixes unreliability of booting the SEC2 RTOS on Quadro P620, + * particularly when resuming from suspend. + * + * Also removes the need for an odd workaround where we needed + * to program SEC2's FALCON_CPUCTL_ALIAS_STARTCPU twice before + * the SEC2 RTOS would begin executing. + */ + switch (falcon->owner->index) { + case NVKM_SUBDEV_GSP: + case NVKM_ENGINE_SEC2: + nvkm_msec(device, 10, + u32 irqstat = nvkm_falcon_rd32(falcon, 0x008); + u32 flcn0dc = nvkm_falcon_rd32(falcon, 0x0dc); + if ((irqstat & 0x00000008) && + (flcn0dc & 0x00007000) == 0x00005000) + break; + ); + + nvkm_falcon_mask(falcon, 0x004, 0x00000008, 0x00000008); + nvkm_falcon_mask(falcon, 0x058, 0x00000002, 0x00000002); + + nvkm_msec(device, 10, + u32 flcn0dc = nvkm_falcon_rd32(falcon, 0x0dc); + if ((flcn0dc & 0x00007000) == 0x00000000) + break; + ); + break; + default: + break; + } } static void -- cgit v1.2.3 From 4d352dbd5850bfc752609d46b5c8403ae0bd5163 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 2 Jul 2019 16:29:40 +1000 Subject: drm/nouveau/secboot/gp102-: remove WAR for SEC2 RTOS start bug Appears to be fixed by "flcn/gp102-: improve implementation of bind_context() on SEC2/GSP". Tested on GP10[24678] and GV100. Signed-off-by: Ben Skeggs --- .../nvkm/subdev/secboot/ls_ucode_msgqueue.c | 29 ---------------------- 1 file changed, 29 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c index 77c13b096a67..a84a999445bb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c @@ -164,41 +164,12 @@ acr_ls_sec2_post_run(const struct nvkm_acr *acr, const struct nvkm_secboot *sb) struct nvkm_sec2 *sec = device->sec2; /* on SEC arguments are always at the beginning of EMEM */ const u32 addr_args = 0x01000000; - u32 reg; int ret; ret = acr_ls_msgqueue_post_run(sec->queue, sec->falcon, addr_args); if (ret) return ret; - /* - * There is a bug where the LS firmware sometimes require to be started - * twice (this happens only on SEC). Detect and workaround that - * condition. - * - * Once started, the falcon will end up in STOPPED condition (bit 5) - * if successful, or in HALT condition (bit 4) if not. - */ - nvkm_msec(device, 1, - if ((reg = nvkm_falcon_rd32(sb->boot_falcon, 0x100) & 0x30) != 0) - break; - ); - if (reg & BIT(4)) { - nvkm_debug(subdev, "applying workaround for start bug...\n"); - nvkm_falcon_start(sb->boot_falcon); - nvkm_msec(subdev->device, 1, - if ((reg = nvkm_rd32(subdev->device, - sb->boot_falcon->addr + 0x100) - & 0x30) != 0) - break; - ); - if (reg & BIT(4)) { - nvkm_error(subdev, "%s failed to start\n", - nvkm_secboot_falcon_name[acr->boot_falcon]); - return -EINVAL; - } - } - nvkm_debug(&sb->subdev, "%s started\n", nvkm_secboot_falcon_name[acr->boot_falcon]); -- cgit v1.2.3