From da5a662a2326931bef25f0e534c9c1702f862399 Mon Sep 17 00:00:00 2001 From: Vladislav Zolotarov Date: Wed, 13 Aug 2008 15:50:00 -0700 Subject: bnx2x: Load/Unload under traffic Load/Unload under traffic Few issues were found when loading and unloading under traffic: - When receiving Tx interrupt call netif_wake_queue if the queue is stopped but the state is open - Check that interrupts are enabled before doing anything else on the msix_fp_int function - In nic_load, enable the interrupts only when needed and ready for it - Function stop_leading returns status since it can fail - Add 1ms delay when unloading the driver to validate that there are no open transactions that already started by the FW - Splitting the "has work" function into Tx and Rx so the same function will be used on unload and interrupts - Do not request for WoL if only resetting the device (save the time that it takes the FW to set the link after reset) - Fixing the device reset after iSCSI boot and before driver load - all internal buffers must be cleared before the driver is loaded Signed-off-by: Vladislav Zolotarov Signed-off-by: Eilon Greenstein Signed-off-by: David S. Miller --- drivers/net/bnx2x_reg.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/net/bnx2x_reg.h') diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h index 40c3a7735d25..b5313c209caa 100644 --- a/drivers/net/bnx2x_reg.h +++ b/drivers/net/bnx2x_reg.h @@ -1677,6 +1677,7 @@ /* [RW 8] init credit counter for port0 in LLH */ #define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554 #define NIG_REG_LLH0_XCM_MASK 0x10130 +#define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248 /* [RW 1] send to BRB1 if no match on any of RMP rules. */ #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc /* [RW 2] Determine the classification participants. 0: no classification.1: @@ -4962,6 +4963,7 @@ #define MISC_REGISTERS_GPIO_PORT_SHIFT 4 #define MISC_REGISTERS_GPIO_SET_POS 8 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588 +#define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7) #define MISC_REGISTERS_RESET_REG_1_SET 0x584 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0) @@ -4997,6 +4999,7 @@ #define HW_LOCK_RESOURCE_8072_MDIO 0 #define HW_LOCK_RESOURCE_GPIO 1 #define HW_LOCK_RESOURCE_SPIO 2 +#define HW_LOCK_RESOURCE_UNDI 5 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18) #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31) #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9) -- cgit v1.2.3