From b79c7adf82e8b8a6d6ad1dadf7e687a4a030cf8c Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 2 Feb 2010 13:01:25 +0900 Subject: mtd: trivial sh_flctl changes This patch contains a few changes for the sh_flctl driver: - not sh7723-only driver - get rid of kconfig dependency - use dev_err() instead of printk() - use __devinit and __devexit for probe()/remove() - fix probe() return values Signed-off-by: Magnus Damm Acked-by: Yoshihiro Shimoda Signed-off-by: Paul Mundt --- drivers/mtd/nand/Kconfig | 4 ++-- drivers/mtd/nand/sh_flctl.c | 42 +++++++++++++++++++++++------------------- 2 files changed, 25 insertions(+), 21 deletions(-) (limited to 'drivers/mtd') diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 677cd53f18c3..bb6465604235 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -457,10 +457,10 @@ config MTD_NAND_NOMADIK config MTD_NAND_SH_FLCTL tristate "Support for NAND on Renesas SuperH FLCTL" - depends on MTD_NAND && SUPERH && CPU_SUBTYPE_SH7723 + depends on MTD_NAND && SUPERH help Several Renesas SuperH CPU has FLCTL. This option enables support - for NAND Flash using FLCTL. This driver support SH7723. + for NAND Flash using FLCTL. config MTD_NAND_DAVINCI tristate "Support NAND on DaVinci SoC" diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c index 02bef21f2e4b..ab068a503b29 100644 --- a/drivers/mtd/nand/sh_flctl.c +++ b/drivers/mtd/nand/sh_flctl.c @@ -1,10 +1,10 @@ /* * SuperH FLCTL nand controller * - * Copyright © 2008 Renesas Solutions Corp. - * Copyright © 2008 Atom Create Engineering Co., Ltd. + * Copyright (c) 2008 Renesas Solutions Corp. + * Copyright (c) 2008 Atom Create Engineering Co., Ltd. * - * Based on fsl_elbc_nand.c, Copyright © 2006-2007 Freescale Semiconductor + * Based on fsl_elbc_nand.c, Copyright (c) 2006-2007 Freescale Semiconductor * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -75,6 +75,11 @@ static void start_translation(struct sh_flctl *flctl) writeb(TRSTRT, FLTRCR(flctl)); } +static void timeout_error(struct sh_flctl *flctl, const char *str) +{ + dev_err(&flctl->pdev->dev, "Timeout occured in %s\n", str); +} + static void wait_completion(struct sh_flctl *flctl) { uint32_t timeout = LOOP_TIMEOUT_MAX; @@ -87,7 +92,7 @@ static void wait_completion(struct sh_flctl *flctl) udelay(1); } - printk(KERN_ERR "wait_completion(): Timeout occured \n"); + timeout_error(flctl, __func__); writeb(0x0, FLTRCR(flctl)); } @@ -132,7 +137,7 @@ static void wait_rfifo_ready(struct sh_flctl *flctl) return; udelay(1); } - printk(KERN_ERR "wait_rfifo_ready(): Timeout occured \n"); + timeout_error(flctl, __func__); } static void wait_wfifo_ready(struct sh_flctl *flctl) @@ -146,7 +151,7 @@ static void wait_wfifo_ready(struct sh_flctl *flctl) return; udelay(1); } - printk(KERN_ERR "wait_wfifo_ready(): Timeout occured \n"); + timeout_error(flctl, __func__); } static int wait_recfifo_ready(struct sh_flctl *flctl, int sector_number) @@ -198,7 +203,7 @@ static int wait_recfifo_ready(struct sh_flctl *flctl, int sector_number) writel(0, FL4ECCCR(flctl)); } - printk(KERN_ERR "wait_recfifo_ready(): Timeout occured \n"); + timeout_error(flctl, __func__); return 1; /* timeout */ } @@ -214,7 +219,7 @@ static void wait_wecfifo_ready(struct sh_flctl *flctl) return; udelay(1); } - printk(KERN_ERR "wait_wecfifo_ready(): Timeout occured \n"); + timeout_error(flctl, __func__); } static void read_datareg(struct sh_flctl *flctl, int offset) @@ -769,38 +774,36 @@ static int flctl_chip_init_tail(struct mtd_info *mtd) return 0; } -static int __init flctl_probe(struct platform_device *pdev) +static int __devinit flctl_probe(struct platform_device *pdev) { struct resource *res; struct sh_flctl *flctl; struct mtd_info *flctl_mtd; struct nand_chip *nand; struct sh_flctl_platform_data *pdata; - int ret; + int ret = -ENXIO; pdata = pdev->dev.platform_data; if (pdata == NULL) { - printk(KERN_ERR "sh_flctl platform_data not found.\n"); - return -ENODEV; + dev_err(&pdev->dev, "no platform data defined\n"); + return -EINVAL; } flctl = kzalloc(sizeof(struct sh_flctl), GFP_KERNEL); if (!flctl) { - printk(KERN_ERR "Unable to allocate NAND MTD dev structure.\n"); + dev_err(&pdev->dev, "failed to allocate driver data\n"); return -ENOMEM; } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { - printk(KERN_ERR "%s: resource not found.\n", __func__); - ret = -ENODEV; + dev_err(&pdev->dev, "failed to get I/O memory\n"); goto err; } - flctl->reg = ioremap(res->start, res->end - res->start + 1); + flctl->reg = ioremap(res->start, resource_size(res)); if (flctl->reg == NULL) { - printk(KERN_ERR "%s: ioremap error.\n", __func__); - ret = -ENOMEM; + dev_err(&pdev->dev, "failed to remap I/O memory\n"); goto err; } @@ -808,6 +811,7 @@ static int __init flctl_probe(struct platform_device *pdev) flctl_mtd = &flctl->mtd; nand = &flctl->chip; flctl_mtd->priv = nand; + flctl->pdev = pdev; flctl->hwecc = pdata->has_hwecc; flctl_register_init(flctl, pdata->flcmncr_val); @@ -846,7 +850,7 @@ err: return ret; } -static int __exit flctl_remove(struct platform_device *pdev) +static int __devexit flctl_remove(struct platform_device *pdev) { struct sh_flctl *flctl = platform_get_drvdata(pdev); -- cgit v1.2.3 From 010ab820582d03bcd3648416b5837107e8a9c5f3 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 27 Jan 2010 09:17:21 +0000 Subject: mtd: sh_flctl SHBUSSEL and SEL_16BIT support This patch extends the sh_flctl driver with support for 16-bit bus configuration using SEL_16BIT and support for multiplexed pins using SHBUSSEL. Signed-off-by: Magnus Damm Acked-by: Yoshihiro Shimoda Signed-off-by: Paul Mundt --- drivers/mtd/nand/sh_flctl.c | 27 ++++++++++++++++++++++++++- include/linux/mtd/sh_flctl.h | 2 ++ 2 files changed, 28 insertions(+), 1 deletion(-) (limited to 'drivers/mtd') diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c index ab068a503b29..1842df8bdd93 100644 --- a/drivers/mtd/nand/sh_flctl.c +++ b/drivers/mtd/nand/sh_flctl.c @@ -105,6 +105,8 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr) addr = page_addr; /* ERASE1 */ } else if (page_addr != -1) { /* SEQIN, READ0, etc.. */ + if (flctl->chip.options & NAND_BUSWIDTH_16) + column >>= 1; if (flctl->page_size) { addr = column & 0x0FFF; addr |= (page_addr & 0xff) << 16; @@ -280,7 +282,7 @@ static void write_fiforeg(struct sh_flctl *flctl, int rlen, int offset) static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_val) { struct sh_flctl *flctl = mtd_to_flctl(mtd); - uint32_t flcmncr_val = readl(FLCMNCR(flctl)); + uint32_t flcmncr_val = readl(FLCMNCR(flctl)) & ~SEL_16BIT; uint32_t flcmdcr_val, addr_len_bytes = 0; /* Set SNAND bit if page size is 2048byte */ @@ -302,6 +304,8 @@ static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_va case NAND_CMD_READOOB: addr_len_bytes = flctl->rw_ADRCNT; flcmdcr_val |= CDSRC_E; + if (flctl->chip.options & NAND_BUSWIDTH_16) + flcmncr_val |= SEL_16BIT; break; case NAND_CMD_SEQIN: /* This case is that cmd is READ0 or READ1 or READ00 */ @@ -310,6 +314,8 @@ static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_va case NAND_CMD_PAGEPROG: addr_len_bytes = flctl->rw_ADRCNT; flcmdcr_val |= DOCMD2_E | CDSRC_E | SELRW; + if (flctl->chip.options & NAND_BUSWIDTH_16) + flcmncr_val |= SEL_16BIT; break; case NAND_CMD_READID: flcmncr_val &= ~SNAND_E; @@ -528,6 +534,8 @@ static void flctl_cmdfunc(struct mtd_info *mtd, unsigned int command, set_addr(mtd, 0, page_addr); flctl->read_bytes = mtd->writesize + mtd->oobsize; + if (flctl->chip.options & NAND_BUSWIDTH_16) + column >>= 1; flctl->index += column; goto read_normal_exit; @@ -691,6 +699,18 @@ static uint8_t flctl_read_byte(struct mtd_info *mtd) return data; } +static uint16_t flctl_read_word(struct mtd_info *mtd) +{ + struct sh_flctl *flctl = mtd_to_flctl(mtd); + int index = flctl->index; + uint16_t data; + uint16_t *buf = (uint16_t *)&flctl->done_buff[index]; + + data = *buf; + flctl->index += 2; + return data; +} + static void flctl_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) { int i; @@ -829,6 +849,11 @@ static int __devinit flctl_probe(struct platform_device *pdev) nand->select_chip = flctl_select_chip; nand->cmdfunc = flctl_cmdfunc; + if (pdata->flcmncr_val & SEL_16BIT) { + nand->options |= NAND_BUSWIDTH_16; + nand->read_word = flctl_read_word; + } + ret = nand_scan_ident(flctl_mtd, 1); if (ret) goto err; diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h index 164c9d4013c0..ab77609ec337 100644 --- a/include/linux/mtd/sh_flctl.h +++ b/include/linux/mtd/sh_flctl.h @@ -51,6 +51,8 @@ #define _4ECCCNTEN (0x1 << 24) #define _4ECCEN (0x1 << 23) #define _4ECCCORRECT (0x1 << 22) +#define SHBUSSEL (0x1 << 20) +#define SEL_16BIT (0x1 << 19) #define SNAND_E (0x1 << 18) /* SNAND (0=512 1=2048)*/ #define QTSEL_E (0x1 << 17) #define ENDIAN (0x1 << 16) /* 1 = little endian */ -- cgit v1.2.3 From 9bdcf336d0c061e77f4c45c7b2bc32e3ed6b57e3 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Sun, 4 Oct 2009 14:55:24 +0200 Subject: MIPS: Alchemy: devboard register abstraction All Alchemy development boards have external CPLDs with a few registers in them. They all share an identical register layout with only a few minor differences (except the PB1000) in bit functions and base addresses. This patch - adds a primitive facility to initialize and use these external registers, - replaces all occurrences of bcsr->xxx accesses with calls to the new functions (the pb1200 cascade irq handling code is special). - collects BCSR register information scattered throughout the board headers in a central place. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- arch/mips/alchemy/devboards/Makefile | 2 +- arch/mips/alchemy/devboards/bcsr.c | 76 ++++++++ arch/mips/alchemy/devboards/db1x00/board_setup.c | 62 +++--- arch/mips/alchemy/devboards/pb1100/board_setup.c | 7 +- arch/mips/alchemy/devboards/pb1200/board_setup.c | 49 +++-- arch/mips/alchemy/devboards/pb1200/irqmap.c | 42 ++-- arch/mips/alchemy/devboards/pb1200/platform.c | 25 +-- arch/mips/alchemy/devboards/pb1500/board_setup.c | 7 +- arch/mips/alchemy/devboards/pb1550/board_setup.c | 11 +- arch/mips/include/asm/mach-db1x00/bcsr.h | 235 +++++++++++++++++++++++ arch/mips/include/asm/mach-db1x00/db1200.h | 109 +---------- arch/mips/include/asm/mach-db1x00/db1x00.h | 92 --------- arch/mips/include/asm/mach-pb1x00/pb1100.h | 49 ----- arch/mips/include/asm/mach-pb1x00/pb1200.h | 109 +---------- arch/mips/include/asm/mach-pb1x00/pb1500.h | 13 -- arch/mips/include/asm/mach-pb1x00/pb1550.h | 89 --------- drivers/mtd/nand/au1550nd.c | 4 +- drivers/net/irda/au1k_ir.c | 14 +- drivers/pcmcia/au1000_db1x00.c | 76 ++++---- 19 files changed, 475 insertions(+), 596 deletions(-) create mode 100644 arch/mips/alchemy/devboards/bcsr.c create mode 100644 arch/mips/include/asm/mach-db1x00/bcsr.h (limited to 'drivers/mtd') diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index 730f9f2b30e8..adc6717d7688 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -2,7 +2,7 @@ # Alchemy Develboards # -obj-y += prom.o +obj-y += prom.o bcsr.o obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_MIPS_PB1000) += pb1000/ obj-$(CONFIG_MIPS_PB1100) += pb1100/ diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c new file mode 100644 index 000000000000..85b7715901af --- /dev/null +++ b/arch/mips/alchemy/devboards/bcsr.c @@ -0,0 +1,76 @@ +/* + * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction. + * + * All Alchemy development boards (except, of course, the weird PB1000) + * have a few registers in a CPLD with standardised layout; they mostly + * only differ in base address. + * All registers are 16bits wide with 32bit spacing. + */ + +#include +#include +#include +#include +#include + +static struct bcsr_reg { + void __iomem *raddr; + spinlock_t lock; +} bcsr_regs[BCSR_CNT]; + +void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys) +{ + int i; + + bcsr1_phys = KSEG1ADDR(CPHYSADDR(bcsr1_phys)); + bcsr2_phys = KSEG1ADDR(CPHYSADDR(bcsr2_phys)); + + for (i = 0; i < BCSR_CNT; i++) { + if (i >= BCSR_HEXLEDS) + bcsr_regs[i].raddr = (void __iomem *)bcsr2_phys + + (0x04 * (i - BCSR_HEXLEDS)); + else + bcsr_regs[i].raddr = (void __iomem *)bcsr1_phys + + (0x04 * i); + + spin_lock_init(&bcsr_regs[i].lock); + } +} + +unsigned short bcsr_read(enum bcsr_id reg) +{ + unsigned short r; + unsigned long flags; + + spin_lock_irqsave(&bcsr_regs[reg].lock, flags); + r = __raw_readw(bcsr_regs[reg].raddr); + spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags); + return r; +} +EXPORT_SYMBOL_GPL(bcsr_read); + +void bcsr_write(enum bcsr_id reg, unsigned short val) +{ + unsigned long flags; + + spin_lock_irqsave(&bcsr_regs[reg].lock, flags); + __raw_writew(val, bcsr_regs[reg].raddr); + wmb(); + spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags); +} +EXPORT_SYMBOL_GPL(bcsr_write); + +void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set) +{ + unsigned short r; + unsigned long flags; + + spin_lock_irqsave(&bcsr_regs[reg].lock, flags); + r = __raw_readw(bcsr_regs[reg].raddr); + r &= ~clr; + r |= set; + __raw_writew(r, bcsr_regs[reg].raddr); + wmb(); + spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags); +} +EXPORT_SYMBOL_GPL(bcsr_mod); diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c index de30d8ea7176..e713390c69e6 100644 --- a/arch/mips/alchemy/devboards/db1x00/board_setup.c +++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c @@ -32,12 +32,10 @@ #include #include +#include #include - -static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; - const char *get_system_type(void) { #ifdef CONFIG_MIPS_BOSPORUS @@ -49,15 +47,43 @@ const char *get_system_type(void) void board_reset(void) { - /* Hit BCSR.SW_RESET[RESET] */ - bcsr->swreset = 0x0000; + bcsr_write(BCSR_SYSTEM, 0); } void __init board_setup(void) { + unsigned long bcsr1, bcsr2; u32 pin_func = 0; char *argptr; + bcsr1 = DB1000_BCSR_PHYS_ADDR; + bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS; + +#ifdef CONFIG_MIPS_DB1000 + printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n"); +#endif +#ifdef CONFIG_MIPS_DB1500 + printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n"); +#endif +#ifdef CONFIG_MIPS_DB1100 + printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n"); +#endif +#ifdef CONFIG_MIPS_BOSPORUS + printk(KERN_INFO "AMD Alchemy Bosporus Board\n"); +#endif +#ifdef CONFIG_MIPS_MIRAGE + printk(KERN_INFO "AMD Alchemy Mirage Board\n"); +#endif +#ifdef CONFIG_MIPS_DB1550 + printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n"); + + bcsr1 = DB1550_BCSR_PHYS_ADDR; + bcsr2 = DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS; +#endif + + /* initialize board register space */ + bcsr_init(bcsr1, bcsr2); + argptr = prom_getcmdline(); #ifdef CONFIG_SERIAL_8250_CONSOLE argptr = strstr(argptr, "console="); @@ -89,11 +115,10 @@ void __init board_setup(void) pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF; au_writel(pin_func, SYS_PINFUNC); /* Power off until the driver is in use */ - bcsr->resets &= ~BCSR_RESETS_IRDA_MODE_MASK; - bcsr->resets |= BCSR_RESETS_IRDA_MODE_OFF; - au_sync(); + bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK, + BCSR_RESETS_IRDA_MODE_OFF); #endif - bcsr->pcmcia = 0x0000; /* turn off PCMCIA power */ + bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */ /* Enable GPIO[31:0] inputs */ alchemy_gpio1_input_enable(); @@ -123,23 +148,4 @@ void __init board_setup(void) #endif au_sync(); - -#ifdef CONFIG_MIPS_DB1000 - printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n"); -#endif -#ifdef CONFIG_MIPS_DB1500 - printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n"); -#endif -#ifdef CONFIG_MIPS_DB1100 - printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n"); -#endif -#ifdef CONFIG_MIPS_BOSPORUS - printk(KERN_INFO "AMD Alchemy Bosporus Board\n"); -#endif -#ifdef CONFIG_MIPS_MIRAGE - printk(KERN_INFO "AMD Alchemy Mirage Board\n"); -#endif -#ifdef CONFIG_MIPS_DB1550 - printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n"); -#endif } diff --git a/arch/mips/alchemy/devboards/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100/board_setup.c index 61263081ef58..eb749fb9daa1 100644 --- a/arch/mips/alchemy/devboards/pb1100/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1100/board_setup.c @@ -30,6 +30,7 @@ #include #include +#include #include @@ -49,8 +50,7 @@ const char *get_system_type(void) void board_reset(void) { - /* Hit BCSR.RST_VDDI[SOFT_RESET] */ - au_writel(0x00000000, PB1100_RST_VDDI); + bcsr_write(BCSR_SYSTEM, 0); } void __init board_init_irq(void) @@ -63,6 +63,9 @@ void __init board_setup(void) volatile void __iomem *base = (volatile void __iomem *)0xac000000UL; char *argptr; + bcsr_init(DB1000_BCSR_PHYS_ADDR, + DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS); + argptr = prom_getcmdline(); #ifdef CONFIG_SERIAL_8250_CONSOLE argptr = strstr(argptr, "console="); diff --git a/arch/mips/alchemy/devboards/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c index 94e6b7e7753d..db563800c31d 100644 --- a/arch/mips/alchemy/devboards/pb1200/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1200/board_setup.c @@ -27,6 +27,8 @@ #include #include +#include + #include #include @@ -38,14 +40,25 @@ const char *get_system_type(void) void board_reset(void) { - bcsr->resets = 0; - bcsr->system = 0; + bcsr_write(BCSR_RESETS, 0); + bcsr_write(BCSR_SYSTEM, 0); } void __init board_setup(void) { char *argptr; +#ifdef CONFIG_MIPS_PB1200 + printk(KERN_INFO "AMD Alchemy Pb1200 Board\n"); + bcsr_init(PB1200_BCSR_PHYS_ADDR, + PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS); +#endif +#ifdef CONFIG_MIPS_DB1200 + printk(KERN_INFO "AMD Alchemy Db1200 Board\n"); + bcsr_init(DB1200_BCSR_PHYS_ADDR, + DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); +#endif + argptr = prom_getcmdline(); #ifdef CONFIG_SERIAL_8250_CONSOLE argptr = strstr(argptr, "console="); @@ -82,7 +95,7 @@ void __init board_setup(void) u32 pin_func; /* Select SMBus in CPLD */ - bcsr->resets &= ~BCSR_RESETS_PCS0MUX; + bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); pin_func = au_readl(SYS_PINFUNC); au_sync(); @@ -116,38 +129,24 @@ void __init board_setup(void) /* * The Pb1200 development board uses external MUX for PSC0 to - * support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI + * support SMB/SPI. bcsr_resets bit 12: 0=SMB 1=SPI */ #ifdef CONFIG_I2C_AU1550 - bcsr->resets &= ~BCSR_RESETS_PCS0MUX; + bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); #endif au_sync(); - -#ifdef CONFIG_MIPS_PB1200 - printk(KERN_INFO "AMD Alchemy Pb1200 Board\n"); -#endif -#ifdef CONFIG_MIPS_DB1200 - printk(KERN_INFO "AMD Alchemy Db1200 Board\n"); -#endif } int board_au1200fb_panel(void) { - BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; - int p; - - p = bcsr->switches; - p >>= 8; - p &= 0x0F; - return p; + return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; } int board_au1200fb_panel_init(void) { /* Apply power */ - BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; - - bcsr->board |= BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL; + bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | + BCSR_BOARD_LCDBL); /* printk(KERN_DEBUG "board_au1200fb_panel_init()\n"); */ return 0; } @@ -155,10 +154,8 @@ int board_au1200fb_panel_init(void) int board_au1200fb_panel_shutdown(void) { /* Remove power */ - BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; - - bcsr->board &= ~(BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | - BCSR_BOARD_LCDBL); + bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | + BCSR_BOARD_LCDBL, 0); /* printk(KERN_DEBUG "board_au1200fb_panel_shutdown()\n"); */ return 0; } diff --git a/arch/mips/alchemy/devboards/pb1200/irqmap.c b/arch/mips/alchemy/devboards/pb1200/irqmap.c index fe47498da280..f379b02213f1 100644 --- a/arch/mips/alchemy/devboards/pb1200/irqmap.c +++ b/arch/mips/alchemy/devboards/pb1200/irqmap.c @@ -38,11 +38,14 @@ #define PB1200_INT_END DB1200_INT_END #endif +#include + struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { /* This is external interrupt cascade */ { AU1000_GPIO_7, IRQF_TRIGGER_LOW, 0 }, }; +static void __iomem *bcsr_virt; /* * Support for External interrupts on the Pb1200 Development platform. @@ -50,7 +53,7 @@ struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { static void pb1200_cascade_handler(unsigned int irq, struct irq_desc *d) { - unsigned short bisr = bcsr->int_status; + unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT); for ( ; bisr; bisr &= bisr - 1) generic_handle_irq(PB1200_INT_BEGIN + __ffs(bisr)); @@ -61,24 +64,27 @@ static void pb1200_cascade_handler(unsigned int irq, struct irq_desc *d) */ static void pb1200_mask_irq(unsigned int irq_nr) { - bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN); - bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN); - au_sync(); + unsigned short v = 1 << (irq_nr - PB1200_INT_BEGIN); + __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR); + __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); + wmb(); } static void pb1200_maskack_irq(unsigned int irq_nr) { - bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN); - bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN); - bcsr->int_status = 1 << (irq_nr - PB1200_INT_BEGIN); /* ack */ - au_sync(); + unsigned short v = 1 << (irq_nr - PB1200_INT_BEGIN); + __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR); + __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); + __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */ + wmb(); } static void pb1200_unmask_irq(unsigned int irq_nr) { - bcsr->intset = 1 << (irq_nr - PB1200_INT_BEGIN); - bcsr->intset_mask = 1 << (irq_nr - PB1200_INT_BEGIN); - au_sync(); + unsigned short v = 1 << (irq_nr - PB1200_INT_BEGIN); + __raw_writew(v, bcsr_virt + BCSR_REG_INTSET); + __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET); + wmb(); } static struct irq_chip pb1200_cpld_irq_type = { @@ -100,8 +106,10 @@ void __init board_init_irq(void) au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map)); #ifdef CONFIG_MIPS_PB1200 + bcsr_virt = (void __iomem *)KSEG1ADDR(PB1200_BCSR_PHYS_ADDR); + /* We have a problem with CPLD rev 3. */ - if (((bcsr->whoami & BCSR_WHOAMI_CPLD) >> 4) <= 3) { + if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) { printk(KERN_ERR "WARNING!!!\n"); printk(KERN_ERR "WARNING!!!\n"); printk(KERN_ERR "WARNING!!!\n"); @@ -119,12 +127,14 @@ void __init board_init_irq(void) printk(KERN_ERR "WARNING!!!\n"); panic("Game over. Your score is 0."); } +#else + bcsr_virt = (void __iomem *)KSEG1ADDR(DB1200_BCSR_PHYS_ADDR); #endif + /* mask & disable & ack all */ - bcsr->intclr_mask = 0xffff; - bcsr->intclr = 0xffff; - bcsr->int_status = 0xffff; - au_sync(); + bcsr_write(BCSR_INTCLR, 0xffff); + bcsr_write(BCSR_MASKCLR, 0xffff); + bcsr_write(BCSR_INTSTAT, 0xffff); for (irq = PB1200_INT_BEGIN; irq <= PB1200_INT_END; irq++) set_irq_chip_and_handler_name(irq, &pb1200_cpld_irq_type, diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c index b93dff4a6789..dfdaabf77909 100644 --- a/arch/mips/alchemy/devboards/pb1200/platform.c +++ b/arch/mips/alchemy/devboards/pb1200/platform.c @@ -26,27 +26,28 @@ #include #include +#include static int mmc_activity; static void pb1200mmc0_set_power(void *mmc_host, int state) { if (state) - bcsr->board |= BCSR_BOARD_SD0PWR; + bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR); else - bcsr->board &= ~BCSR_BOARD_SD0PWR; + bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0); - au_sync_delay(1); + msleep(1); } static int pb1200mmc0_card_readonly(void *mmc_host) { - return (bcsr->status & BCSR_STATUS_SD0WP) ? 1 : 0; + return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0; } static int pb1200mmc0_card_inserted(void *mmc_host) { - return (bcsr->sig_status & BCSR_INT_SD0INSERT) ? 1 : 0; + return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0; } static void pb1200_mmcled_set(struct led_classdev *led, @@ -54,10 +55,10 @@ static void pb1200_mmcled_set(struct led_classdev *led, { if (brightness != LED_OFF) { if (++mmc_activity == 1) - bcsr->disk_leds &= ~(1 << 8); + bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); } else { if (--mmc_activity == 0) - bcsr->disk_leds |= (1 << 8); + bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); } } @@ -69,21 +70,21 @@ static struct led_classdev pb1200mmc_led = { static void pb1200mmc1_set_power(void *mmc_host, int state) { if (state) - bcsr->board |= BCSR_BOARD_SD1PWR; + bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR); else - bcsr->board &= ~BCSR_BOARD_SD1PWR; + bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0); - au_sync_delay(1); + msleep(1); } static int pb1200mmc1_card_readonly(void *mmc_host) { - return (bcsr->status & BCSR_STATUS_SD1WP) ? 1 : 0; + return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0; } static int pb1200mmc1_card_inserted(void *mmc_host) { - return (bcsr->sig_status & BCSR_INT_SD1INSERT) ? 1 : 0; + return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0; } #endif diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c index d7a56569e7ed..c5389e5afb93 100644 --- a/arch/mips/alchemy/devboards/pb1500/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c @@ -30,6 +30,7 @@ #include #include +#include #include @@ -55,8 +56,7 @@ const char *get_system_type(void) void board_reset(void) { - /* Hit BCSR.RST_VDDI[SOFT_RESET] */ - au_writel(0x00000000, PB1500_RST_VDDI); + bcsr_write(BCSR_SYSTEM, 0); } void __init board_init_irq(void) @@ -70,6 +70,9 @@ void __init board_setup(void) u32 sys_freqctrl, sys_clksrc; char *argptr; + bcsr_init(DB1000_BCSR_PHYS_ADDR, + DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS); + argptr = prom_getcmdline(); #ifdef CONFIG_SERIAL_8250_CONSOLE argptr = strstr(argptr, "console="); diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c index b6e9e7d247a3..af7a1b5fe7c7 100644 --- a/arch/mips/alchemy/devboards/pb1550/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c @@ -32,6 +32,7 @@ #include #include +#include #include @@ -53,8 +54,7 @@ const char *get_system_type(void) void board_reset(void) { - /* Hit BCSR.SYSTEM[RESET] */ - au_writew(au_readw(0xAF00001C) & ~BCSR_SYSTEM_RESET, 0xAF00001C); + bcsr_write(BCSR_SYSTEM, 0); } void __init board_init_irq(void) @@ -66,6 +66,10 @@ void __init board_setup(void) { u32 pin_func; + bcsr_init(PB1550_BCSR_PHYS_ADDR, + PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS); + + #ifdef CONFIG_SERIAL_8250_CONSOLE char *argptr; argptr = prom_getcmdline(); @@ -85,8 +89,7 @@ void __init board_setup(void) pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; au_writel(pin_func, SYS_PINFUNC); - au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */ - au_sync(); + bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */ printk(KERN_INFO "AMD Alchemy Pb1550 Board\n"); } diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h new file mode 100644 index 000000000000..ecbe19e3c14e --- /dev/null +++ b/arch/mips/include/asm/mach-db1x00/bcsr.h @@ -0,0 +1,235 @@ +/* + * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction. + * + * All Alchemy development boards (except, of course, the weird PB1000) + * have a few registers in a CPLD with standardised layout; they mostly + * only differ in base address and bit meanings in the RESETS and BOARD + * registers. + * + * All data taken from the official AMD board documentation sheets. + */ + +#ifndef _DB1XXX_BCSR_H_ +#define _DB1XXX_BCSR_H_ + + +/* BCSR base addresses on various boards. BCSR base 2 refers to the + * physical address of the first HEXLEDS register, which is usually + * a variable offset from the WHOAMI register. + */ + +/* DB1000, DB1100, DB1500, PB1100, PB1500 */ +#define DB1000_BCSR_PHYS_ADDR 0x0E000000 +#define DB1000_BCSR_HEXLED_OFS 0x01000000 + +#define DB1550_BCSR_PHYS_ADDR 0x0F000000 +#define DB1550_BCSR_HEXLED_OFS 0x00400000 + +#define PB1550_BCSR_PHYS_ADDR 0x0F000000 +#define PB1550_BCSR_HEXLED_OFS 0x00800000 + +#define DB1200_BCSR_PHYS_ADDR 0x19800000 +#define DB1200_BCSR_HEXLED_OFS 0x00400000 + +#define PB1200_BCSR_PHYS_ADDR 0x0D800000 +#define PB1200_BCSR_HEXLED_OFS 0x00400000 + + +enum bcsr_id { + /* BCSR base 1 */ + BCSR_WHOAMI = 0, + BCSR_STATUS, + BCSR_SWITCHES, + BCSR_RESETS, + BCSR_PCMCIA, + BCSR_BOARD, + BCSR_LEDS, + BCSR_SYSTEM, + /* Au1200/1300 based boards */ + BCSR_INTCLR, + BCSR_INTSET, + BCSR_MASKCLR, + BCSR_MASKSET, + BCSR_SIGSTAT, + BCSR_INTSTAT, + + /* BCSR base 2 */ + BCSR_HEXLEDS, + BCSR_RSVD1, + BCSR_HEXCLEAR, + + BCSR_CNT, +}; + +/* register offsets, valid for all Db1xxx/Pb1xxx boards */ +#define BCSR_REG_WHOAMI 0x00 +#define BCSR_REG_STATUS 0x04 +#define BCSR_REG_SWITCHES 0x08 +#define BCSR_REG_RESETS 0x0c +#define BCSR_REG_PCMCIA 0x10 +#define BCSR_REG_BOARD 0x14 +#define BCSR_REG_LEDS 0x18 +#define BCSR_REG_SYSTEM 0x1c +/* Au1200/Au1300 based boards: CPLD IRQ muxer */ +#define BCSR_REG_INTCLR 0x20 +#define BCSR_REG_INTSET 0x24 +#define BCSR_REG_MASKCLR 0x28 +#define BCSR_REG_MASKSET 0x2c +#define BCSR_REG_SIGSTAT 0x30 +#define BCSR_REG_INTSTAT 0x34 + +/* hexled control, offset from BCSR base 2 */ +#define BCSR_REG_HEXLEDS 0x00 +#define BCSR_REG_HEXCLEAR 0x08 + +/* + * Register Bits and Pieces. + */ +#define BCSR_WHOAMI_DCID(x) ((x) & 0xf) +#define BCSR_WHOAMI_CPLD(x) (((x) >> 4) & 0xf) +#define BCSR_WHOAMI_BOARD(x) (((x) >> 8) & 0xf) + +/* register "WHOAMI" bits 11:8 identify the board */ +enum bcsr_whoami_boards { + BCSR_WHOAMI_PB1500 = 1, + BCSR_WHOAMI_PB1500R2, + BCSR_WHOAMI_PB1100, + BCSR_WHOAMI_DB1000, + BCSR_WHOAMI_DB1100, + BCSR_WHOAMI_DB1500, + BCSR_WHOAMI_DB1550, + BCSR_WHOAMI_PB1550_DDR, + BCSR_WHOAMI_PB1550 = BCSR_WHOAMI_PB1550_DDR, + BCSR_WHOAMI_PB1550_SDR, + BCSR_WHOAMI_PB1200_DDR1, + BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1, + BCSR_WHOAMI_PB1200_DDR2, + BCSR_WHOAMI_DB1200, +}; + +/* STATUS reg. Unless otherwise noted, they're valid on all boards. + * PB1200 = DB1200. + */ +#define BCSR_STATUS_PC0VS 0x0003 +#define BCSR_STATUS_PC1VS 0x000C +#define BCSR_STATUS_PC0FI 0x0010 +#define BCSR_STATUS_PC1FI 0x0020 +#define BCSR_STATUS_PB1550_SWAPBOOT 0x0040 +#define BCSR_STATUS_SRAMWIDTH 0x0080 +#define BCSR_STATUS_FLASHBUSY 0x0100 +#define BCSR_STATUS_ROMBUSY 0x0400 +#define BCSR_STATUS_SD0WP 0x0400 /* DB1200 */ +#define BCSR_STATUS_SD1WP 0x0800 +#define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */ +#define BCSR_STATUS_DB1000_SWAPBOOT 0x2000 +#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200 */ +#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200 */ +#define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */ +#define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */ +#define BCSR_STATUS_FLASHDEN 0xC000 +#define BCSR_STATUS_DB1550_U0RXD 0x1000 /* DB1550 */ +#define BCSR_STATUS_DB1550_U3RXD 0x2000 /* DB1550 */ +#define BCSR_STATUS_PB1550_U0RXD 0x1000 /* PB1550 */ +#define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */ +#define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */ + + +/* DB/PB1000,1100,1500,1550 */ +#define BCSR_RESETS_PHY0 0x0001 +#define BCSR_RESETS_PHY1 0x0002 +#define BCSR_RESETS_DC 0x0004 +#define BCSR_RESETS_FIR_SEL 0x2000 +#define BCSR_RESETS_IRDA_MODE_MASK 0xC000 +#define BCSR_RESETS_IRDA_MODE_FULL 0x0000 +#define BCSR_RESETS_PB1550_WSCFSM 0x2000 +#define BCSR_RESETS_IRDA_MODE_OFF 0x4000 +#define BCSR_RESETS_IRDA_MODE_2_3 0x8000 +#define BCSR_RESETS_IRDA_MODE_1_3 0xC000 +#define BCSR_RESETS_DMAREQ 0x8000 /* PB1550 */ + +#define BCSR_BOARD_PCIM66EN 0x0001 +#define BCSR_BOARD_SD0PWR 0x0040 +#define BCSR_BOARD_SD1PWR 0x0080 +#define BCSR_BOARD_PCIM33 0x0100 +#define BCSR_BOARD_PCIEXTARB 0x0200 +#define BCSR_BOARD_GPIO200RST 0x0400 +#define BCSR_BOARD_PCICLKOUT 0x0800 +#define BCSR_BOARD_PCICFG 0x1000 +#define BCSR_BOARD_SPISEL 0x4000 /* PB/DB1550 */ +#define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */ +#define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */ + + +/* DB/PB1200 */ +#define BCSR_RESETS_ETH 0x0001 +#define BCSR_RESETS_CAMERA 0x0002 +#define BCSR_RESETS_DC 0x0004 +#define BCSR_RESETS_IDE 0x0008 +#define BCSR_RESETS_TV 0x0010 /* DB1200 */ +/* Not resets but in the same register */ +#define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */ +#define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */ +#define BCSR_RESETS_PSC0MUX 0x1000 +#define BCSR_RESETS_PSC1MUX 0x2000 +#define BCSR_RESETS_SPISEL 0x4000 +#define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */ + +#define BCSR_BOARD_LCDVEE 0x0001 +#define BCSR_BOARD_LCDVDD 0x0002 +#define BCSR_BOARD_LCDBL 0x0004 +#define BCSR_BOARD_CAMSNAP 0x0010 +#define BCSR_BOARD_CAMPWR 0x0020 +#define BCSR_BOARD_SD0PWR 0x0040 + + +#define BCSR_SWITCHES_DIP 0x00FF +#define BCSR_SWITCHES_DIP_1 0x0080 +#define BCSR_SWITCHES_DIP_2 0x0040 +#define BCSR_SWITCHES_DIP_3 0x0020 +#define BCSR_SWITCHES_DIP_4 0x0010 +#define BCSR_SWITCHES_DIP_5 0x0008 +#define BCSR_SWITCHES_DIP_6 0x0004 +#define BCSR_SWITCHES_DIP_7 0x0002 +#define BCSR_SWITCHES_DIP_8 0x0001 +#define BCSR_SWITCHES_ROTARY 0x0F00 + + +#define BCSR_PCMCIA_PC0VPP 0x0003 +#define BCSR_PCMCIA_PC0VCC 0x000C +#define BCSR_PCMCIA_PC0DRVEN 0x0010 +#define BCSR_PCMCIA_PC0RST 0x0080 +#define BCSR_PCMCIA_PC1VPP 0x0300 +#define BCSR_PCMCIA_PC1VCC 0x0C00 +#define BCSR_PCMCIA_PC1DRVEN 0x1000 +#define BCSR_PCMCIA_PC1RST 0x8000 + + +#define BCSR_LEDS_DECIMALS 0x0003 +#define BCSR_LEDS_LED0 0x0100 +#define BCSR_LEDS_LED1 0x0200 +#define BCSR_LEDS_LED2 0x0400 +#define BCSR_LEDS_LED3 0x0800 + + +#define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */ +#define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */ +#define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */ + + + + +/* initialize BCSR for a board. Provide the PHYSICAL addresses of both + * BCSR spaces. + */ +void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys); + +/* read a board register */ +unsigned short bcsr_read(enum bcsr_id reg); + +/* write to a board register */ +void bcsr_write(enum bcsr_id reg, unsigned short val); + +/* modify a register. clear bits set in 'clr', set bits set in 'set' */ +void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set); + +#endif diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h index 27f26102b1bb..2909b834e4af 100644 --- a/arch/mips/include/asm/mach-db1x00/db1200.h +++ b/arch/mips/include/asm/mach-db1x00/db1200.h @@ -45,113 +45,6 @@ #define AC97_PSC_BASE PSC1_BASE_ADDR #define I2S_PSC_BASE PSC1_BASE_ADDR -#define BCSR_KSEG1_ADDR 0xB9800000 - -typedef volatile struct -{ - /*00*/ u16 whoami; - u16 reserved0; - /*04*/ u16 status; - u16 reserved1; - /*08*/ u16 switches; - u16 reserved2; - /*0C*/ u16 resets; - u16 reserved3; - - /*10*/ u16 pcmcia; - u16 reserved4; - /*14*/ u16 board; - u16 reserved5; - /*18*/ u16 disk_leds; - u16 reserved6; - /*1C*/ u16 system; - u16 reserved7; - - /*20*/ u16 intclr; - u16 reserved8; - /*24*/ u16 intset; - u16 reserved9; - /*28*/ u16 intclr_mask; - u16 reserved10; - /*2C*/ u16 intset_mask; - u16 reserved11; - - /*30*/ u16 sig_status; - u16 reserved12; - /*34*/ u16 int_status; - u16 reserved13; - /*38*/ u16 reserved14; - u16 reserved15; - /*3C*/ u16 reserved16; - u16 reserved17; - -} BCSR; - -static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; - -/* - * Register bit definitions for the BCSRs - */ -#define BCSR_WHOAMI_DCID 0x000F -#define BCSR_WHOAMI_CPLD 0x00F0 -#define BCSR_WHOAMI_BOARD 0x0F00 - -#define BCSR_STATUS_PCMCIA0VS 0x0003 -#define BCSR_STATUS_PCMCIA1VS 0x000C -#define BCSR_STATUS_SWAPBOOT 0x0040 -#define BCSR_STATUS_FLASHBUSY 0x0100 -#define BCSR_STATUS_IDECBLID 0x0200 -#define BCSR_STATUS_SD0WP 0x0400 -#define BCSR_STATUS_U0RXD 0x1000 -#define BCSR_STATUS_U1RXD 0x2000 - -#define BCSR_SWITCHES_OCTAL 0x00FF -#define BCSR_SWITCHES_DIP_1 0x0080 -#define BCSR_SWITCHES_DIP_2 0x0040 -#define BCSR_SWITCHES_DIP_3 0x0020 -#define BCSR_SWITCHES_DIP_4 0x0010 -#define BCSR_SWITCHES_DIP_5 0x0008 -#define BCSR_SWITCHES_DIP_6 0x0004 -#define BCSR_SWITCHES_DIP_7 0x0002 -#define BCSR_SWITCHES_DIP_8 0x0001 -#define BCSR_SWITCHES_ROTARY 0x0F00 - -#define BCSR_RESETS_ETH 0x0001 -#define BCSR_RESETS_CAMERA 0x0002 -#define BCSR_RESETS_DC 0x0004 -#define BCSR_RESETS_IDE 0x0008 -#define BCSR_RESETS_TV 0x0010 -/* Not resets but in the same register */ -#define BCSR_RESETS_PWMR1MUX 0x0800 -#define BCSR_RESETS_PCS0MUX 0x1000 -#define BCSR_RESETS_PCS1MUX 0x2000 -#define BCSR_RESETS_SPISEL 0x4000 - -#define BCSR_PCMCIA_PC0VPP 0x0003 -#define BCSR_PCMCIA_PC0VCC 0x000C -#define BCSR_PCMCIA_PC0DRVEN 0x0010 -#define BCSR_PCMCIA_PC0RST 0x0080 -#define BCSR_PCMCIA_PC1VPP 0x0300 -#define BCSR_PCMCIA_PC1VCC 0x0C00 -#define BCSR_PCMCIA_PC1DRVEN 0x1000 -#define BCSR_PCMCIA_PC1RST 0x8000 - -#define BCSR_BOARD_LCDVEE 0x0001 -#define BCSR_BOARD_LCDVDD 0x0002 -#define BCSR_BOARD_LCDBL 0x0004 -#define BCSR_BOARD_CAMSNAP 0x0010 -#define BCSR_BOARD_CAMPWR 0x0020 -#define BCSR_BOARD_SD0PWR 0x0040 - -#define BCSR_LEDS_DECIMALS 0x0003 -#define BCSR_LEDS_LED0 0x0100 -#define BCSR_LEDS_LED1 0x0200 -#define BCSR_LEDS_LED2 0x0400 -#define BCSR_LEDS_LED3 0x0800 - -#define BCSR_SYSTEM_POWEROFF 0x4000 -#define BCSR_SYSTEM_RESET 0x8000 - /* Bit positions for the different interrupt sources */ #define BCSR_INT_IDE 0x0001 #define BCSR_INT_ETH 0x0002 @@ -222,7 +115,7 @@ enum external_pb1200_ints { #define BOARD_PC0_INT DB1200_PC0_INT #define BOARD_PC1_INT DB1200_PC1_INT -#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET))) +#define BOARD_CARD_INSERTED(SOCKET) (bcsr_read(BCSR_SIGSTAT) & (1 << (8 + (2 * SOCKET)))) /* NAND chip select */ #define NAND_CS 1 diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h index 1a515b8c870f..cfa64297da08 100644 --- a/arch/mips/include/asm/mach-db1x00/db1x00.h +++ b/arch/mips/include/asm/mach-db1x00/db1x00.h @@ -41,102 +41,10 @@ #define SMBUS_PSC_BASE PSC2_BASE_ADDR #define I2S_PSC_BASE PSC3_BASE_ADDR -#define BCSR_KSEG1_ADDR 0xAF000000 #define NAND_PHYS_ADDR 0x20000000 -#else -#define BCSR_KSEG1_ADDR 0xAE000000 #endif -/* - * Overlay data structure of the DBAu1x00 board registers. - * Registers are located at physical 0E0000xx, KSEG1 0xAE0000xx. - */ -typedef volatile struct -{ - /*00*/ unsigned short whoami; - unsigned short reserved0; - /*04*/ unsigned short status; - unsigned short reserved1; - /*08*/ unsigned short switches; - unsigned short reserved2; - /*0C*/ unsigned short resets; - unsigned short reserved3; - /*10*/ unsigned short pcmcia; - unsigned short reserved4; - /*14*/ unsigned short specific; - unsigned short reserved5; - /*18*/ unsigned short leds; - unsigned short reserved6; - /*1C*/ unsigned short swreset; - unsigned short reserved7; - -} BCSR; - - -/* - * Register/mask bit definitions for the BCSRs - */ -#define BCSR_WHOAMI_DCID 0x000F -#define BCSR_WHOAMI_CPLD 0x00F0 -#define BCSR_WHOAMI_BOARD 0x0F00 - -#define BCSR_STATUS_PC0VS 0x0003 -#define BCSR_STATUS_PC1VS 0x000C -#define BCSR_STATUS_PC0FI 0x0010 -#define BCSR_STATUS_PC1FI 0x0020 -#define BCSR_STATUS_FLASHBUSY 0x0100 -#define BCSR_STATUS_ROMBUSY 0x0400 -#define BCSR_STATUS_SWAPBOOT 0x2000 -#define BCSR_STATUS_FLASHDEN 0xC000 - -#define BCSR_SWITCHES_DIP 0x00FF -#define BCSR_SWITCHES_DIP_1 0x0080 -#define BCSR_SWITCHES_DIP_2 0x0040 -#define BCSR_SWITCHES_DIP_3 0x0020 -#define BCSR_SWITCHES_DIP_4 0x0010 -#define BCSR_SWITCHES_DIP_5 0x0008 -#define BCSR_SWITCHES_DIP_6 0x0004 -#define BCSR_SWITCHES_DIP_7 0x0002 -#define BCSR_SWITCHES_DIP_8 0x0001 -#define BCSR_SWITCHES_ROTARY 0x0F00 - -#define BCSR_RESETS_PHY0 0x0001 -#define BCSR_RESETS_PHY1 0x0002 -#define BCSR_RESETS_DC 0x0004 -#define BCSR_RESETS_FIR_SEL 0x2000 -#define BCSR_RESETS_IRDA_MODE_MASK 0xC000 -#define BCSR_RESETS_IRDA_MODE_FULL 0x0000 -#define BCSR_RESETS_IRDA_MODE_OFF 0x4000 -#define BCSR_RESETS_IRDA_MODE_2_3 0x8000 -#define BCSR_RESETS_IRDA_MODE_1_3 0xC000 - -#define BCSR_PCMCIA_PC0VPP 0x0003 -#define BCSR_PCMCIA_PC0VCC 0x000C -#define BCSR_PCMCIA_PC0DRVEN 0x0010 -#define BCSR_PCMCIA_PC0RST 0x0080 -#define BCSR_PCMCIA_PC1VPP 0x0300 -#define BCSR_PCMCIA_PC1VCC 0x0C00 -#define BCSR_PCMCIA_PC1DRVEN 0x1000 -#define BCSR_PCMCIA_PC1RST 0x8000 - -#define BCSR_BOARD_PCIM66EN 0x0001 -#define BCSR_BOARD_SD0_PWR 0x0040 -#define BCSR_BOARD_SD1_PWR 0x0080 -#define BCSR_BOARD_PCIM33 0x0100 -#define BCSR_BOARD_GPIO200RST 0x0400 -#define BCSR_BOARD_PCICFG 0x1000 -#define BCSR_BOARD_SD0_WP 0x4000 -#define BCSR_BOARD_SD1_WP 0x8000 - -#define BCSR_LEDS_DECIMALS 0x0003 -#define BCSR_LEDS_LED0 0x0100 -#define BCSR_LEDS_LED1 0x0200 -#define BCSR_LEDS_LED2 0x0400 -#define BCSR_LEDS_LED3 0x0800 - -#define BCSR_SWRESET_RESET 0x0080 - /* PCMCIA DBAu1x00 specific defines */ #define PCMCIA_MAX_SOCK 1 #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) diff --git a/arch/mips/include/asm/mach-pb1x00/pb1100.h b/arch/mips/include/asm/mach-pb1x00/pb1100.h index b1a60f1cbd02..f2bf73a11fb2 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1100.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1100.h @@ -26,55 +26,6 @@ #ifndef __ASM_PB1100_H #define __ASM_PB1100_H -#define PB1100_IDENT 0xAE000000 -#define BOARD_STATUS_REG 0xAE000004 -# define PB1100_ROM_SEL (1 << 15) -# define PB1100_ROM_SIZ (1 << 14) -# define PB1100_SWAP_BOOT (1 << 13) -# define PB1100_FLASH_WP (1 << 12) -# define PB1100_ROM_H_STS (1 << 11) -# define PB1100_ROM_L_STS (1 << 10) -# define PB1100_FLASH_H_STS (1 << 9) -# define PB1100_FLASH_L_STS (1 << 8) -# define PB1100_SRAM_SIZ (1 << 7) -# define PB1100_TSC_BUSY (1 << 6) -# define PB1100_PCMCIA_VS_MASK (3 << 4) -# define PB1100_RS232_CD (1 << 3) -# define PB1100_RS232_CTS (1 << 2) -# define PB1100_RS232_DSR (1 << 1) -# define PB1100_RS232_RI (1 << 0) - -#define PB1100_IRDA_RS232 0xAE00000C -# define PB1100_IRDA_FULL (0 << 14) /* full power */ -# define PB1100_IRDA_SHUTDOWN (1 << 14) -# define PB1100_IRDA_TT (2 << 14) /* 2/3 power */ -# define PB1100_IRDA_OT (3 << 14) /* 1/3 power */ -# define PB1100_IRDA_FIR (1 << 13) - -#define PCMCIA_BOARD_REG 0xAE000010 -# define PB1100_SD_WP1_RO (1 << 15) /* read only */ -# define PB1100_SD_WP0_RO (1 << 14) /* read only */ -# define PB1100_SD_PWR1 (1 << 11) /* applies power to SD1 */ -# define PB1100_SD_PWR0 (1 << 10) /* applies power to SD0 */ -# define PB1100_SEL_SD_CONN1 (1 << 9) -# define PB1100_SEL_SD_CONN0 (1 << 8) -# define PC_DEASSERT_RST (1 << 7) -# define PC_DRV_EN (1 << 4) - -#define PB1100_G_CONTROL 0xAE000014 /* graphics control */ - -#define PB1100_RST_VDDI 0xAE00001C -# define PB1100_SOFT_RESET (1 << 15) /* clear to reset the board */ -# define PB1100_VDDI_MASK 0x1F - -#define PB1100_LEDS 0xAE000018 - -/* - * 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED. - * 7:0 is the LED Display's decimal points. - */ -#define PB1100_HEX_LED 0xAE000018 - /* PCMCIA Pb1100 specific defines */ #define PCMCIA_MAX_SOCK 0 #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h index c8618df88cb5..a51512c68177 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1200.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h @@ -43,113 +43,8 @@ * Refer to board documentation. */ #define AC97_PSC_BASE PSC1_BASE_ADDR -#define I2S_PSC_BASE PSC1_BASE_ADDR +#define I2S_PSC_BASE PSC1_BASE_ADDR -#define BCSR_KSEG1_ADDR 0xAD800000 - -typedef volatile struct -{ - /*00*/ u16 whoami; - u16 reserved0; - /*04*/ u16 status; - u16 reserved1; - /*08*/ u16 switches; - u16 reserved2; - /*0C*/ u16 resets; - u16 reserved3; - - /*10*/ u16 pcmcia; - u16 reserved4; - /*14*/ u16 board; - u16 reserved5; - /*18*/ u16 disk_leds; - u16 reserved6; - /*1C*/ u16 system; - u16 reserved7; - - /*20*/ u16 intclr; - u16 reserved8; - /*24*/ u16 intset; - u16 reserved9; - /*28*/ u16 intclr_mask; - u16 reserved10; - /*2C*/ u16 intset_mask; - u16 reserved11; - - /*30*/ u16 sig_status; - u16 reserved12; - /*34*/ u16 int_status; - u16 reserved13; - /*38*/ u16 reserved14; - u16 reserved15; - /*3C*/ u16 reserved16; - u16 reserved17; - -} BCSR; - -static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; - -/* - * Register bit definitions for the BCSRs - */ -#define BCSR_WHOAMI_DCID 0x000F -#define BCSR_WHOAMI_CPLD 0x00F0 -#define BCSR_WHOAMI_BOARD 0x0F00 - -#define BCSR_STATUS_PCMCIA0VS 0x0003 -#define BCSR_STATUS_PCMCIA1VS 0x000C -#define BCSR_STATUS_SWAPBOOT 0x0040 -#define BCSR_STATUS_FLASHBUSY 0x0100 -#define BCSR_STATUS_IDECBLID 0x0200 -#define BCSR_STATUS_SD0WP 0x0400 -#define BCSR_STATUS_SD1WP 0x0800 -#define BCSR_STATUS_U0RXD 0x1000 -#define BCSR_STATUS_U1RXD 0x2000 - -#define BCSR_SWITCHES_OCTAL 0x00FF -#define BCSR_SWITCHES_DIP_1 0x0080 -#define BCSR_SWITCHES_DIP_2 0x0040 -#define BCSR_SWITCHES_DIP_3 0x0020 -#define BCSR_SWITCHES_DIP_4 0x0010 -#define BCSR_SWITCHES_DIP_5 0x0008 -#define BCSR_SWITCHES_DIP_6 0x0004 -#define BCSR_SWITCHES_DIP_7 0x0002 -#define BCSR_SWITCHES_DIP_8 0x0001 -#define BCSR_SWITCHES_ROTARY 0x0F00 - -#define BCSR_RESETS_ETH 0x0001 -#define BCSR_RESETS_CAMERA 0x0002 -#define BCSR_RESETS_DC 0x0004 -#define BCSR_RESETS_IDE 0x0008 -/* not resets but in the same register */ -#define BCSR_RESETS_WSCFSM 0x0800 -#define BCSR_RESETS_PCS0MUX 0x1000 -#define BCSR_RESETS_PCS1MUX 0x2000 -#define BCSR_RESETS_SPISEL 0x4000 -#define BCSR_RESETS_SD1MUX 0x8000 - -#define BCSR_PCMCIA_PC0VPP 0x0003 -#define BCSR_PCMCIA_PC0VCC 0x000C -#define BCSR_PCMCIA_PC0DRVEN 0x0010 -#define BCSR_PCMCIA_PC0RST 0x0080 -#define BCSR_PCMCIA_PC1VPP 0x0300 -#define BCSR_PCMCIA_PC1VCC 0x0C00 -#define BCSR_PCMCIA_PC1DRVEN 0x1000 -#define BCSR_PCMCIA_PC1RST 0x8000 - -#define BCSR_BOARD_LCDVEE 0x0001 -#define BCSR_BOARD_LCDVDD 0x0002 -#define BCSR_BOARD_LCDBL 0x0004 -#define BCSR_BOARD_CAMSNAP 0x0010 -#define BCSR_BOARD_CAMPWR 0x0020 -#define BCSR_BOARD_SD0PWR 0x0040 -#define BCSR_BOARD_SD1PWR 0x0080 - -#define BCSR_LEDS_DECIMALS 0x00FF -#define BCSR_LEDS_LED0 0x0100 -#define BCSR_LEDS_LED1 0x0200 -#define BCSR_LEDS_LED2 0x0400 -#define BCSR_LEDS_LED3 0x0800 #define BCSR_SYSTEM_VDDI 0x001F #define BCSR_SYSTEM_POWEROFF 0x4000 @@ -251,7 +146,7 @@ enum external_pb1200_ints { #define BOARD_PC0_INT PB1200_PC0_INT #define BOARD_PC1_INT PB1200_PC1_INT -#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET))) +#define BOARD_CARD_INSERTED(SOCKET) (bcsr_read(BCSR_SIGSTAT & (1 << (8 + (2 * SOCKET)))) /* NAND chip select */ #define NAND_CS 1 diff --git a/arch/mips/include/asm/mach-pb1x00/pb1500.h b/arch/mips/include/asm/mach-pb1x00/pb1500.h index da51a2eb7b82..82431a7ab942 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1500.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1500.h @@ -26,19 +26,6 @@ #ifndef __ASM_PB1500_H #define __ASM_PB1500_H -#define IDENT_BOARD_REG 0xAE000000 -#define BOARD_STATUS_REG 0xAE000004 -#define PCI_BOARD_REG 0xAE000010 -#define PCMCIA_BOARD_REG 0xAE000010 -# define PC_DEASSERT_RST 0x80 -# define PC_DRV_EN 0x10 -#define PB1500_G_CONTROL 0xAE000014 -#define PB1500_RST_VDDI 0xAE00001C -#define PB1500_LEDS 0xAE000018 - -#define PB1500_HEX_LED 0xAF000004 -#define PB1500_HEX_LED_BLANK 0xAF000008 - /* PCMCIA Pb1500 specific defines */ #define PCMCIA_MAX_SOCK 0 #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h index 6704a11497db..306d584abbd4 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1550.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h @@ -40,95 +40,6 @@ #define SMBUS_PSC_BASE PSC2_BASE_ADDR #define I2S_PSC_BASE PSC3_BASE_ADDR -#define BCSR_PHYS_ADDR 0xAF000000 - -typedef volatile struct -{ - /*00*/ u16 whoami; - u16 reserved0; - /*04*/ u16 status; - u16 reserved1; - /*08*/ u16 switches; - u16 reserved2; - /*0C*/ u16 resets; - u16 reserved3; - /*10*/ u16 pcmcia; - u16 reserved4; - /*14*/ u16 pci; - u16 reserved5; - /*18*/ u16 leds; - u16 reserved6; - /*1C*/ u16 system; - u16 reserved7; - -} BCSR; - -static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR; - -/* - * Register bit definitions for the BCSRs - */ -#define BCSR_WHOAMI_DCID 0x000F -#define BCSR_WHOAMI_CPLD 0x00F0 -#define BCSR_WHOAMI_BOARD 0x0F00 - -#define BCSR_STATUS_PCMCIA0VS 0x0003 -#define BCSR_STATUS_PCMCIA1VS 0x000C -#define BCSR_STATUS_PCMCIA0FI 0x0010 -#define BCSR_STATUS_PCMCIA1FI 0x0020 -#define BCSR_STATUS_SWAPBOOT 0x0040 -#define BCSR_STATUS_SRAMWIDTH 0x0080 -#define BCSR_STATUS_FLASHBUSY 0x0100 -#define BCSR_STATUS_ROMBUSY 0x0200 -#define BCSR_STATUS_USBOTGID 0x0800 -#define BCSR_STATUS_U0RXD 0x1000 -#define BCSR_STATUS_U1RXD 0x2000 -#define BCSR_STATUS_U3RXD 0x8000 - -#define BCSR_SWITCHES_OCTAL 0x00FF -#define BCSR_SWITCHES_DIP_1 0x0080 -#define BCSR_SWITCHES_DIP_2 0x0040 -#define BCSR_SWITCHES_DIP_3 0x0020 -#define BCSR_SWITCHES_DIP_4 0x0010 -#define BCSR_SWITCHES_DIP_5 0x0008 -#define BCSR_SWITCHES_DIP_6 0x0004 -#define BCSR_SWITCHES_DIP_7 0x0002 -#define BCSR_SWITCHES_DIP_8 0x0001 -#define BCSR_SWITCHES_ROTARY 0x0F00 - -#define BCSR_RESETS_PHY0 0x0001 -#define BCSR_RESETS_PHY1 0x0002 -#define BCSR_RESETS_DC 0x0004 -#define BCSR_RESETS_WSC 0x2000 -#define BCSR_RESETS_SPISEL 0x4000 -#define BCSR_RESETS_DMAREQ 0x8000 - -#define BCSR_PCMCIA_PC0VPP 0x0003 -#define BCSR_PCMCIA_PC0VCC 0x000C -#define BCSR_PCMCIA_PC0DRVEN 0x0010 -#define BCSR_PCMCIA_PC0RST 0x0080 -#define BCSR_PCMCIA_PC1VPP 0x0300 -#define BCSR_PCMCIA_PC1VCC 0x0C00 -#define BCSR_PCMCIA_PC1DRVEN 0x1000 -#define BCSR_PCMCIA_PC1RST 0x8000 - -#define BCSR_PCI_M66EN 0x0001 -#define BCSR_PCI_M33 0x0100 -#define BCSR_PCI_EXTERNARB 0x0200 -#define BCSR_PCI_GPIO200RST 0x0400 -#define BCSR_PCI_CLKOUT 0x0800 -#define BCSR_PCI_CFGHOST 0x1000 - -#define BCSR_LEDS_DECIMALS 0x00FF -#define BCSR_LEDS_LED0 0x0100 -#define BCSR_LEDS_LED1 0x0200 -#define BCSR_LEDS_LED2 0x0400 -#define BCSR_LEDS_LED3 0x0800 - -#define BCSR_SYSTEM_VDDI 0x001F -#define BCSR_SYSTEM_POWEROFF 0x4000 -#define BCSR_SYSTEM_RESET 0x8000 - #define PCMCIA_MAX_SOCK 1 #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c index 92c334ff4508..43d46e424040 100644 --- a/drivers/mtd/nand/au1550nd.c +++ b/drivers/mtd/nand/au1550nd.c @@ -19,6 +19,7 @@ #include #include +#include /* * MTD structure for NAND controller @@ -475,7 +476,8 @@ static int __init au1xxx_nand_init(void) /* set gpio206 high */ au_writel(au_readl(GPIO2_DIR) & ~(1 << 6), GPIO2_DIR); - boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr->status >> 6) & 0x1); + boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr_read(BCSR_STATUS) >> 6) & 0x1); + switch (boot_swapboot) { case 0: case 2: diff --git a/drivers/net/irda/au1k_ir.c b/drivers/net/irda/au1k_ir.c index 9b2eebdbb25b..b5cbd39d0685 100644 --- a/drivers/net/irda/au1k_ir.c +++ b/drivers/net/irda/au1k_ir.c @@ -36,6 +36,7 @@ #include #elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) #include +#include #else #error au1k_ir: unsupported board #endif @@ -66,10 +67,6 @@ static char version[] __devinitdata = #define RUN_AT(x) (jiffies + (x)) -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) -static BCSR * const bcsr = (BCSR *)0xAE000000; -#endif - static DEFINE_SPINLOCK(ir_lock); /* @@ -282,9 +279,8 @@ static int au1k_irda_net_init(struct net_device *dev) #if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) /* power on */ - bcsr->resets &= ~BCSR_RESETS_IRDA_MODE_MASK; - bcsr->resets |= BCSR_RESETS_IRDA_MODE_FULL; - au_sync(); + bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK, + BCSR_RESETS_IRDA_MODE_FULL); #endif return 0; @@ -720,14 +716,14 @@ au1k_irda_set_speed(struct net_device *dev, int speed) if (speed == 4000000) { #if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) - bcsr->resets |= BCSR_RESETS_FIR_SEL; + bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_FIR_SEL); #else /* Pb1000 and Pb1100 */ writel(1<<13, CPLD_AUX1); #endif } else { #if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) - bcsr->resets &= ~BCSR_RESETS_FIR_SEL; + bcsr_mod(BCSR_RESETS, BCSR_RESETS_FIR_SEL, 0); #else /* Pb1000 and Pb1100 */ writel(readl(CPLD_AUX1) & ~(1<<13), CPLD_AUX1); #endif diff --git a/drivers/pcmcia/au1000_db1x00.c b/drivers/pcmcia/au1000_db1x00.c index c78d77fd7e3b..3fdd664e41c6 100644 --- a/drivers/pcmcia/au1000_db1x00.c +++ b/drivers/pcmcia/au1000_db1x00.c @@ -47,9 +47,9 @@ #include #else #include - static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; #endif +#include #include "au1000_generic.h" #if 0 @@ -76,8 +76,8 @@ static int db1x00_pcmcia_hw_init(struct au1000_pcmcia_socket *skt) static void db1x00_pcmcia_shutdown(struct au1000_pcmcia_socket *skt) { - bcsr->pcmcia = 0; /* turn off power */ - au_sync_delay(2); + bcsr_write(BCSR_PCMCIA, 0); /* turn off power */ + msleep(2); } static void @@ -93,19 +93,19 @@ db1x00_pcmcia_socket_state(struct au1000_pcmcia_socket *skt, struct pcmcia_state switch (skt->nr) { case 0: - vs = bcsr->status & 0x3; + vs = bcsr_read(BCSR_STATUS) & 0x3; #if defined(CONFIG_MIPS_DB1200) || defined(CONFIG_MIPS_PB1200) inserted = BOARD_CARD_INSERTED(0); #else - inserted = !(bcsr->status & (1<<4)); + inserted = !(bcsr_read(BCSR_STATUS) & (1 << 4)); #endif break; case 1: - vs = (bcsr->status & 0xC)>>2; + vs = (bcsr_read(BCSR_STATUS) & 0xC) >> 2; #if defined(CONFIG_MIPS_DB1200) || defined(CONFIG_MIPS_PB1200) inserted = BOARD_CARD_INSERTED(1); #else - inserted = !(bcsr->status & (1<<5)); + inserted = !(bcsr_read(BCSR_STATUS) & (1<<5)); #endif break; default:/* should never happen */ @@ -114,7 +114,7 @@ db1x00_pcmcia_socket_state(struct au1000_pcmcia_socket *skt, struct pcmcia_state if (inserted) debug("db1x00 socket %d: inserted %d, vs %d pcmcia %x\n", - skt->nr, inserted, vs, bcsr->pcmcia); + skt->nr, inserted, vs, bcsr_read(BCSR_PCMCIA)); if (inserted) { switch (vs) { @@ -136,19 +136,21 @@ db1x00_pcmcia_socket_state(struct au1000_pcmcia_socket *skt, struct pcmcia_state /* if the card was previously inserted and then ejected, * we should turn off power to it */ - if ((skt->nr == 0) && (bcsr->pcmcia & BCSR_PCMCIA_PC0RST)) { - bcsr->pcmcia &= ~(BCSR_PCMCIA_PC0RST | - BCSR_PCMCIA_PC0DRVEN | - BCSR_PCMCIA_PC0VPP | - BCSR_PCMCIA_PC0VCC); - au_sync_delay(10); + if ((skt->nr == 0) && + (bcsr_read(BCSR_PCMCIA) & BCSR_PCMCIA_PC0RST)) { + bcsr_mod(BCSR_PCMCIA, BCSR_PCMCIA_PC0RST | + BCSR_PCMCIA_PC0DRVEN | + BCSR_PCMCIA_PC0VPP | + BCSR_PCMCIA_PC0VCC, 0); + msleep(10); } - else if ((skt->nr == 1) && bcsr->pcmcia & BCSR_PCMCIA_PC1RST) { - bcsr->pcmcia &= ~(BCSR_PCMCIA_PC1RST | - BCSR_PCMCIA_PC1DRVEN | - BCSR_PCMCIA_PC1VPP | - BCSR_PCMCIA_PC1VCC); - au_sync_delay(10); + else if ((skt->nr == 1) && + (bcsr_read(BCSR_PCMCIA) & BCSR_PCMCIA_PC1RST)) { + bcsr_mod(BCSR_PCMCIA, BCSR_PCMCIA_PC1RST | + BCSR_PCMCIA_PC1DRVEN | + BCSR_PCMCIA_PC1VPP | + BCSR_PCMCIA_PC1VCC, 0); + msleep(10); } } @@ -171,7 +173,7 @@ db1x00_pcmcia_configure_socket(struct au1000_pcmcia_socket *skt, struct socket_s * initializing a socket not to wipe out the settings of the * other socket. */ - pwr = bcsr->pcmcia; + pwr = bcsr_read(BCSR_PCMCIA); pwr &= ~(0xf << sock*8); /* clear voltage settings */ state->Vpp = 0; @@ -228,37 +230,37 @@ db1x00_pcmcia_configure_socket(struct au1000_pcmcia_socket *skt, struct socket_s break; } - bcsr->pcmcia = pwr; - au_sync_delay(300); + bcsr_write(BCSR_PCMCIA, pwr); + msleep(300); if (sock == 0) { if (!(state->flags & SS_RESET)) { pwr |= BCSR_PCMCIA_PC0DRVEN; - bcsr->pcmcia = pwr; - au_sync_delay(300); + bcsr_write(BCSR_PCMCIA, pwr); + msleep(300); pwr |= BCSR_PCMCIA_PC0RST; - bcsr->pcmcia = pwr; - au_sync_delay(100); + bcsr_write(BCSR_PCMCIA, pwr); + msleep(100); } else { pwr &= ~(BCSR_PCMCIA_PC0RST | BCSR_PCMCIA_PC0DRVEN); - bcsr->pcmcia = pwr; - au_sync_delay(100); + bcsr_write(BCSR_PCMCIA, pwr); + msleep(100); } } else { if (!(state->flags & SS_RESET)) { pwr |= BCSR_PCMCIA_PC1DRVEN; - bcsr->pcmcia = pwr; - au_sync_delay(300); + bcsr_write(BCSR_PCMCIA, pwr); + msleep(300); pwr |= BCSR_PCMCIA_PC1RST; - bcsr->pcmcia = pwr; - au_sync_delay(100); + bcsr_write(BCSR_PCMCIA, pwr); + msleep(100); } else { pwr &= ~(BCSR_PCMCIA_PC1RST | BCSR_PCMCIA_PC1DRVEN); - bcsr->pcmcia = pwr; - au_sync_delay(100); + bcsr_write(BCSR_PCMCIA, pwr); + msleep(100); } } return 0; @@ -298,8 +300,8 @@ struct pcmcia_low_level db1x00_pcmcia_ops = { int au1x_board_init(struct device *dev) { int ret = -ENODEV; - bcsr->pcmcia = 0; /* turn off power, if it's not already off */ - au_sync_delay(2); + bcsr_write(BCSR_PCMCIA, 0); /* turn off power, if it's not already off */ + msleep(2); ret = au1x00_pcmcia_socket_probe(dev, &db1x00_pcmcia_ops, 0, 2); return ret; } -- cgit v1.2.3 From 206aa6cdadad8bbedee5649f1346fe47e922a039 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Mon, 19 Oct 2009 12:53:37 +0200 Subject: MIPS: Alchemy: physmap-flash for all devboards Replace the devboard NOR MTD mapping driver with physmap-flash support. Also honor the "swapboot" switch settings wrt. to the layout of the NOR partitions. Signed-off-by: Manuel Lauss Cc: Linux-MIPS Acked-By: David Woodhouse Signed-off-by: Ralf Baechle --- arch/mips/alchemy/devboards/db1x00/platform.c | 20 +++ arch/mips/alchemy/devboards/pb1000/board_setup.c | 7 + arch/mips/alchemy/devboards/pb1100/platform.c | 7 + arch/mips/alchemy/devboards/pb1200/platform.c | 9 ++ arch/mips/alchemy/devboards/pb1500/platform.c | 7 + arch/mips/alchemy/devboards/pb1550/platform.c | 6 + arch/mips/alchemy/devboards/platform.c | 104 ++++++++++++++ arch/mips/alchemy/devboards/platform.h | 3 + drivers/mtd/maps/Kconfig | 6 - drivers/mtd/maps/Makefile | 1 - drivers/mtd/maps/alchemy-flash.c | 166 ----------------------- 11 files changed, 163 insertions(+), 173 deletions(-) delete mode 100644 drivers/mtd/maps/alchemy-flash.c (limited to 'drivers/mtd') diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c index 0ac5dd05d3c0..62e2a96fe119 100644 --- a/arch/mips/alchemy/devboards/db1x00/platform.c +++ b/arch/mips/alchemy/devboards/db1x00/platform.c @@ -22,6 +22,7 @@ #include #include +#include #include "../platform.h" /* DB1xxx PCMCIA interrupt sources: @@ -32,6 +33,7 @@ */ #define DB1XXX_HAS_PCMCIA +#define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT) #if defined(CONFIG_MIPS_DB1000) #define DB1XXX_PCMCIA_CD0 AU1000_GPIO0_INT @@ -40,6 +42,8 @@ #define DB1XXX_PCMCIA_CD1 AU1000_GPIO3_INT #define DB1XXX_PCMCIA_STSCHG1 AU1000_GPIO4_INT #define DB1XXX_PCMCIA_CARD1 AU1000_GPIO5_INT +#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ +#define BOARD_FLASH_WIDTH 4 /* 32-bits */ #elif defined(CONFIG_MIPS_DB1100) #define DB1XXX_PCMCIA_CD0 AU1100_GPIO0_INT #define DB1XXX_PCMCIA_STSCHG0 AU1100_GPIO1_INT @@ -47,6 +51,8 @@ #define DB1XXX_PCMCIA_CD1 AU1100_GPIO3_INT #define DB1XXX_PCMCIA_STSCHG1 AU1100_GPIO4_INT #define DB1XXX_PCMCIA_CARD1 AU1100_GPIO5_INT +#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ +#define BOARD_FLASH_WIDTH 4 /* 32-bits */ #elif defined(CONFIG_MIPS_DB1500) #define DB1XXX_PCMCIA_CD0 AU1500_GPIO0_INT #define DB1XXX_PCMCIA_STSCHG0 AU1500_GPIO1_INT @@ -54,6 +60,8 @@ #define DB1XXX_PCMCIA_CD1 AU1500_GPIO3_INT #define DB1XXX_PCMCIA_STSCHG1 AU1500_GPIO4_INT #define DB1XXX_PCMCIA_CARD1 AU1500_GPIO5_INT +#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ +#define BOARD_FLASH_WIDTH 4 /* 32-bits */ #elif defined(CONFIG_MIPS_DB1550) #define DB1XXX_PCMCIA_CD0 AU1550_GPIO0_INT #define DB1XXX_PCMCIA_STSCHG0 AU1550_GPIO21_INT @@ -61,9 +69,20 @@ #define DB1XXX_PCMCIA_CD1 AU1550_GPIO1_INT #define DB1XXX_PCMCIA_STSCHG1 AU1550_GPIO22_INT #define DB1XXX_PCMCIA_CARD1 AU1550_GPIO5_INT +#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */ +#define BOARD_FLASH_WIDTH 4 /* 32-bits */ #else /* other board: no PCMCIA */ #undef DB1XXX_HAS_PCMCIA +#undef F_SWAPPED +#define F_SWAPPED 0 +#if defined(CONFIG_MIPS_BOSPORUS) +#define BOARD_FLASH_SIZE 0x01000000 /* 16MB */ +#define BOARD_FLASH_WIDTH 2 /* 16-bits */ +#elif defined(CONFIG_MIPS_MIRAGE) +#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */ +#define BOARD_FLASH_WIDTH 4 /* 32-bits */ +#endif #endif static int __init db1xxx_dev_init(void) @@ -93,6 +112,7 @@ static int __init db1xxx_dev_init(void) 0, 1); #endif + db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED); return 0; } device_initcall(db1xxx_dev_init); diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c index 50fff504ae05..28b8bd278a16 100644 --- a/arch/mips/alchemy/devboards/pb1000/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c @@ -31,6 +31,7 @@ #include #include +#include "../platform.h" const char *get_system_type(void) { @@ -194,3 +195,9 @@ static int __init pb1000_init_irq(void) return 0; } arch_initcall(pb1000_init_irq); + +static int __init pb1000_device_init(void) +{ + return db1x_register_norflash(8 * 1024 * 1024, 4, 0); +} +device_initcall(pb1000_device_init); diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c index ec932e773a40..bfc5ab6a121c 100644 --- a/arch/mips/alchemy/devboards/pb1100/platform.c +++ b/arch/mips/alchemy/devboards/pb1100/platform.c @@ -21,11 +21,14 @@ #include #include +#include #include "../platform.h" static int __init pb1100_dev_init(void) { + int swapped; + /* PCMCIA. single socket, identical to Pb1500 */ db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS, PCMCIA_ATTR_PSEUDO_PHYS + 0x00040000 - 1, @@ -38,6 +41,10 @@ static int __init pb1100_dev_init(void) /*AU1100_GPIO10_INT*/0, /* stschg */ 0, /* eject */ 0); /* id */ + + swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; + db1x_register_norflash(64 * 1024 * 1024, 4, swapped); + return 0; } device_initcall(pb1100_dev_init); diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c index c8b7ae3f3253..736d647ebe0c 100644 --- a/arch/mips/alchemy/devboards/pb1200/platform.c +++ b/arch/mips/alchemy/devboards/pb1200/platform.c @@ -172,6 +172,8 @@ static struct platform_device *board_platform_devices[] __initdata = { static int __init board_register_devices(void) { + int swapped; + #ifdef CONFIG_MIPS_PB1200 db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS, PCMCIA_ATTR_PSEUDO_PHYS + 0x00040000 - 1, @@ -222,6 +224,13 @@ static int __init board_register_devices(void) 1); #endif + swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; +#ifdef CONFIG_MIPS_PB1200 + db1x_register_norflash(128 * 1024 * 1024, 2, swapped); +#else + db1x_register_norflash(64 * 1024 * 1024, 2, swapped); +#endif + return platform_add_devices(board_platform_devices, ARRAY_SIZE(board_platform_devices)); } diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c index cdce775e2131..529acb789254 100644 --- a/arch/mips/alchemy/devboards/pb1500/platform.c +++ b/arch/mips/alchemy/devboards/pb1500/platform.c @@ -20,11 +20,14 @@ #include #include +#include #include "../platform.h" static int __init pb1500_dev_init(void) { + int swapped; + /* PCMCIA. single socket, identical to Pb1500 */ db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS, PCMCIA_ATTR_PSEUDO_PHYS + 0x00040000 - 1, @@ -37,6 +40,10 @@ static int __init pb1500_dev_init(void) /*AU1500_GPIO10_INT*/0, /* stschg */ 0, /* eject */ 0); /* id */ + + swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; + db1x_register_norflash(64 * 1024 * 1024, 4, swapped); + return 0; } device_initcall(pb1500_dev_init); diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c index b496fb6de231..461339166a4e 100644 --- a/arch/mips/alchemy/devboards/pb1550/platform.c +++ b/arch/mips/alchemy/devboards/pb1550/platform.c @@ -22,11 +22,14 @@ #include #include +#include #include "../platform.h" static int __init pb1550_dev_init(void) { + int swapped; + /* Pb1550, like all others, also has statuschange irqs; however they're * wired up on one of the Au1550's shared GPIO201_205 line, which also * services the PCMCIA card interrupts. So we ignore statuschange and @@ -58,6 +61,9 @@ static int __init pb1550_dev_init(void) 0, 1); + swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT; + db1x_register_norflash(128 * 1024 * 1024, 4, swapped); + return 0; } device_initcall(pb1550_dev_init); diff --git a/arch/mips/alchemy/devboards/platform.c b/arch/mips/alchemy/devboards/platform.c index 48c537cc8efb..7f2bcee7ac34 100644 --- a/arch/mips/alchemy/devboards/platform.c +++ b/arch/mips/alchemy/devboards/platform.c @@ -3,6 +3,9 @@ */ #include +#include +#include +#include #include #include @@ -87,3 +90,104 @@ out: kfree(sr); return ret; } + +#define YAMON_SIZE 0x00100000 +#define YAMON_ENV_SIZE 0x00040000 + +int __init db1x_register_norflash(unsigned long size, int width, + int swapped) +{ + struct physmap_flash_data *pfd; + struct platform_device *pd; + struct mtd_partition *parts; + struct resource *res; + int ret, i; + + if (size < (8 * 1024 * 1024)) + return -EINVAL; + + ret = -ENOMEM; + parts = kzalloc(sizeof(struct mtd_partition) * 5, GFP_KERNEL); + if (!parts) + goto out; + + res = kzalloc(sizeof(struct resource), GFP_KERNEL); + if (!res) + goto out1; + + pfd = kzalloc(sizeof(struct physmap_flash_data), GFP_KERNEL); + if (!pfd) + goto out2; + + pd = platform_device_alloc("physmap-flash", 0); + if (!pd) + goto out3; + + /* NOR flash ends at 0x20000000, regardless of size */ + res->start = 0x20000000 - size; + res->end = 0x20000000 - 1; + res->flags = IORESOURCE_MEM; + + /* partition setup. Most Develboards have a switch which allows + * to swap the physical locations of the 2 NOR flash banks. + */ + i = 0; + if (!swapped) { + /* first NOR chip */ + parts[i].offset = 0; + parts[i].name = "User FS"; + parts[i].size = size / 2; + i++; + } + + parts[i].offset = MTDPART_OFS_APPEND; + parts[i].name = "User FS 2"; + parts[i].size = (size / 2) - (0x20000000 - 0x1fc00000); + i++; + + parts[i].offset = MTDPART_OFS_APPEND; + parts[i].name = "YAMON"; + parts[i].size = YAMON_SIZE; + parts[i].mask_flags = MTD_WRITEABLE; + i++; + + parts[i].offset = MTDPART_OFS_APPEND; + parts[i].name = "raw kernel"; + parts[i].size = 0x00400000 - YAMON_SIZE - YAMON_ENV_SIZE; + i++; + + parts[i].offset = MTDPART_OFS_APPEND; + parts[i].name = "YAMON Env"; + parts[i].size = YAMON_ENV_SIZE; + parts[i].mask_flags = MTD_WRITEABLE; + i++; + + if (swapped) { + parts[i].offset = MTDPART_OFS_APPEND; + parts[i].name = "User FS"; + parts[i].size = size / 2; + i++; + } + + pfd->width = width; + pfd->parts = parts; + pfd->nr_parts = 5; + + pd->dev.platform_data = pfd; + pd->resource = res; + pd->num_resources = 1; + + ret = platform_device_add(pd); + if (!ret) + return ret; + + platform_device_put(pd); +out3: + kfree(pfd); +out2: + kfree(res); +out1: + kfree(parts); +out: + return ret; +} diff --git a/arch/mips/alchemy/devboards/platform.h b/arch/mips/alchemy/devboards/platform.h index 55ecf7e9258f..828c54e31157 100644 --- a/arch/mips/alchemy/devboards/platform.h +++ b/arch/mips/alchemy/devboards/platform.h @@ -15,4 +15,7 @@ int __init db1x_register_pcmcia_socket(unsigned long pseudo_attr_start, int eject_irq, int id); +int __init db1x_register_norflash(unsigned long size, int width, + int swapped); + #endif diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig index 2de0cc823d60..2bb03a8b9ef1 100644 --- a/drivers/mtd/maps/Kconfig +++ b/drivers/mtd/maps/Kconfig @@ -251,12 +251,6 @@ config MTD_NETtel help Support for flash chips on NETtel/SecureEdge/SnapGear boards. -config MTD_ALCHEMY - tristate "AMD Alchemy Pb1xxx/Db1xxx/RDK MTD support" - depends on SOC_AU1X00 && MTD_PARTITIONS && MTD_CFI - help - Flash memory access on AMD Alchemy Pb/Db/RDK Reference Boards - config MTD_DILNETPC tristate "CFI Flash device mapped on DIL/Net PC" depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile index ce315214ff2b..a44919f3f3d2 100644 --- a/drivers/mtd/maps/Makefile +++ b/drivers/mtd/maps/Makefile @@ -40,7 +40,6 @@ obj-$(CONFIG_MTD_SCx200_DOCFLASH)+= scx200_docflash.o obj-$(CONFIG_MTD_DBOX2) += dbox2-flash.o obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o obj-$(CONFIG_MTD_PCI) += pci.o -obj-$(CONFIG_MTD_ALCHEMY) += alchemy-flash.o obj-$(CONFIG_MTD_AUTCPU12) += autcpu12-nvram.o obj-$(CONFIG_MTD_EDB7312) += edb7312.o obj-$(CONFIG_MTD_IMPA7) += impa7.o diff --git a/drivers/mtd/maps/alchemy-flash.c b/drivers/mtd/maps/alchemy-flash.c deleted file mode 100644 index 845ad4f2a542..000000000000 --- a/drivers/mtd/maps/alchemy-flash.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Flash memory access on AMD Alchemy evaluation boards - * - * (C) 2003, 2004 Pete Popov - */ - -#include -#include -#include -#include - -#include -#include -#include - -#include - -#ifdef CONFIG_MIPS_PB1000 -#define BOARD_MAP_NAME "Pb1000 Flash" -#define BOARD_FLASH_SIZE 0x00800000 /* 8MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#endif - -#ifdef CONFIG_MIPS_PB1500 -#define BOARD_MAP_NAME "Pb1500 Flash" -#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#endif - -#ifdef CONFIG_MIPS_PB1100 -#define BOARD_MAP_NAME "Pb1100 Flash" -#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#endif - -#ifdef CONFIG_MIPS_PB1550 -#define BOARD_MAP_NAME "Pb1550 Flash" -#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#endif - -#ifdef CONFIG_MIPS_PB1200 -#define BOARD_MAP_NAME "Pb1200 Flash" -#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */ -#define BOARD_FLASH_WIDTH 2 /* 16-bits */ -#endif - -#ifdef CONFIG_MIPS_DB1000 -#define BOARD_MAP_NAME "Db1000 Flash" -#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#endif - -#ifdef CONFIG_MIPS_DB1500 -#define BOARD_MAP_NAME "Db1500 Flash" -#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#endif - -#ifdef CONFIG_MIPS_DB1100 -#define BOARD_MAP_NAME "Db1100 Flash" -#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#endif - -#ifdef CONFIG_MIPS_DB1550 -#define BOARD_MAP_NAME "Db1550 Flash" -#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#endif - -#ifdef CONFIG_MIPS_DB1200 -#define BOARD_MAP_NAME "Db1200 Flash" -#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */ -#define BOARD_FLASH_WIDTH 2 /* 16-bits */ -#endif - -#ifdef CONFIG_MIPS_BOSPORUS -#define BOARD_MAP_NAME "Bosporus Flash" -#define BOARD_FLASH_SIZE 0x01000000 /* 16MB */ -#define BOARD_FLASH_WIDTH 2 /* 16-bits */ -#endif - -#ifdef CONFIG_MIPS_MIRAGE -#define BOARD_MAP_NAME "Mirage Flash" -#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#define USE_LOCAL_ACCESSORS /* why? */ -#endif - -static struct map_info alchemy_map = { - .name = BOARD_MAP_NAME, -}; - -static struct mtd_partition alchemy_partitions[] = { - { - .name = "User FS", - .size = BOARD_FLASH_SIZE - 0x00400000, - .offset = 0x0000000 - },{ - .name = "YAMON", - .size = 0x0100000, - .offset = MTDPART_OFS_APPEND, - .mask_flags = MTD_WRITEABLE - },{ - .name = "raw kernel", - .size = (0x300000 - 0x40000), /* last 256KB is yamon env */ - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct mtd_info *mymtd; - -static int __init alchemy_mtd_init(void) -{ - struct mtd_partition *parts; - int nb_parts = 0; - unsigned long window_addr; - unsigned long window_size; - - /* Default flash buswidth */ - alchemy_map.bankwidth = BOARD_FLASH_WIDTH; - - window_addr = 0x20000000 - BOARD_FLASH_SIZE; - window_size = BOARD_FLASH_SIZE; - - /* - * Static partition definition selection - */ - parts = alchemy_partitions; - nb_parts = ARRAY_SIZE(alchemy_partitions); - alchemy_map.size = window_size; - - /* - * Now let's probe for the actual flash. Do it here since - * specific machine settings might have been set above. - */ - printk(KERN_NOTICE BOARD_MAP_NAME ": probing %d-bit flash bus\n", - alchemy_map.bankwidth*8); - alchemy_map.virt = ioremap(window_addr, window_size); - mymtd = do_map_probe("cfi_probe", &alchemy_map); - if (!mymtd) { - iounmap(alchemy_map.virt); - return -ENXIO; - } - mymtd->owner = THIS_MODULE; - - add_mtd_partitions(mymtd, parts, nb_parts); - return 0; -} - -static void __exit alchemy_mtd_cleanup(void) -{ - if (mymtd) { - del_mtd_partitions(mymtd); - map_destroy(mymtd); - iounmap(alchemy_map.virt); - } -} - -module_init(alchemy_mtd_init); -module_exit(alchemy_mtd_cleanup); - -MODULE_AUTHOR("Embedded Alley Solutions, Inc"); -MODULE_DESCRIPTION(BOARD_MAP_NAME " MTD driver"); -MODULE_LICENSE("GPL"); -- cgit v1.2.3