From 524883bb48464ed76bd635819989284a249bf917 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Fri, 4 Sep 2015 19:59:33 +0900 Subject: drm/nouveau/ttm: convert to DMA API The pci_dma_* functions are now superseeded in the kernel by the DMA API. Make the conversion to this more generic API. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_ttm.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nouveau_ttm.c') diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c index 3f0fb55cb473..bd287c2728c8 100644 --- a/drivers/gpu/drm/nouveau/nouveau_ttm.c +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c @@ -338,7 +338,7 @@ nouveau_ttm_init(struct nouveau_drm *drm) struct nvkm_device *device = nvxx_device(&drm->device); struct nvkm_pci *pci = device->pci; struct drm_device *dev = drm->dev; - u32 bits; + u8 bits; int ret; if (pci && pci->agp.bridge) { @@ -351,18 +351,16 @@ nouveau_ttm_init(struct nouveau_drm *drm) bits = nvxx_mmu(&drm->device)->dma_bits; if (nvxx_device(&drm->device)->func->pci) { if (drm->agp.bridge || - !pci_dma_supported(dev->pdev, DMA_BIT_MASK(bits))) + !dma_supported(dev->dev, DMA_BIT_MASK(bits))) bits = 32; - ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(bits)); + ret = dma_set_mask(dev->dev, DMA_BIT_MASK(bits)); if (ret) return ret; - ret = pci_set_consistent_dma_mask(dev->pdev, - DMA_BIT_MASK(bits)); + ret = dma_set_coherent_mask(dev->dev, DMA_BIT_MASK(bits)); if (ret) - pci_set_consistent_dma_mask(dev->pdev, - DMA_BIT_MASK(32)); + dma_set_coherent_mask(dev->dev, DMA_BIT_MASK(32)); } ret = nouveau_ttm_global_init(drm); -- cgit v1.2.3 From b31cf78b93243f8ff64297c1f77a4d030c32ca56 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Fri, 4 Sep 2015 19:59:34 +0900 Subject: drm/nouveau/ttm: set the DMA mask for platform devices So far the DMA mask was not set for platform devices, which limited them to a 32-bit physical space. Allow dma_set_mask() to be called for non-PCI devices, and also take the IOMMU bit into account since it could restrict the physically addressable space. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_ttm.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nouveau_ttm.c') diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c index bd287c2728c8..3f713c1b5dc1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_ttm.c +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c @@ -29,6 +29,9 @@ #include "nouveau_gem.h" #include "drm_legacy.h" + +#include + static int nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize) { @@ -353,16 +356,26 @@ nouveau_ttm_init(struct nouveau_drm *drm) if (drm->agp.bridge || !dma_supported(dev->dev, DMA_BIT_MASK(bits))) bits = 32; + } else if (device->func->tegra) { + struct nvkm_device_tegra *tegra = device->func->tegra(device); - ret = dma_set_mask(dev->dev, DMA_BIT_MASK(bits)); - if (ret) - return ret; + /* + * If the platform can use a IOMMU, then the addressable DMA + * space is constrained by the IOMMU bit + */ + if (tegra->func->iommu_bit) + bits = min(bits, tegra->func->iommu_bit); - ret = dma_set_coherent_mask(dev->dev, DMA_BIT_MASK(bits)); - if (ret) - dma_set_coherent_mask(dev->dev, DMA_BIT_MASK(32)); } + ret = dma_set_mask(dev->dev, DMA_BIT_MASK(bits)); + if (ret) + return ret; + + ret = dma_set_coherent_mask(dev->dev, DMA_BIT_MASK(bits)); + if (ret) + dma_set_coherent_mask(dev->dev, DMA_BIT_MASK(32)); + ret = nouveau_ttm_global_init(drm); if (ret) return ret; -- cgit v1.2.3