From 8b9d5d63a7193156b6b397c4f5078efbc200695f Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 15:37:19 +1000 Subject: drm/nouveau/bo: split buffer move functions into their own source files Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_bo9039.c | 81 ++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 drivers/gpu/drm/nouveau/nouveau_bo9039.c (limited to 'drivers/gpu/drm/nouveau/nouveau_bo9039.c') diff --git a/drivers/gpu/drm/nouveau/nouveau_bo9039.c b/drivers/gpu/drm/nouveau/nouveau_bo9039.c new file mode 100644 index 000000000000..14424f6c3f59 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nouveau_bo9039.c @@ -0,0 +1,81 @@ +/* + * Copyright 2007 Dave Airlied + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/* + * Authors: Dave Airlied + * Ben Skeggs + * Jeremy Kolb + */ +#include "nouveau_bo.h" +#include "nouveau_dma.h" +#include "nouveau_mem.h" + +int +nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, + struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) +{ + struct nouveau_mem *mem = nouveau_mem(old_reg); + u64 src_offset = mem->vma[0].addr; + u64 dst_offset = mem->vma[1].addr; + u32 page_count = new_reg->num_pages; + int ret; + + page_count = new_reg->num_pages; + while (page_count) { + int line_count = (page_count > 2047) ? 2047 : page_count; + + ret = RING_SPACE(chan, 12); + if (ret) + return ret; + + BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2); + OUT_RING (chan, upper_32_bits(dst_offset)); + OUT_RING (chan, lower_32_bits(dst_offset)); + BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6); + OUT_RING (chan, upper_32_bits(src_offset)); + OUT_RING (chan, lower_32_bits(src_offset)); + OUT_RING (chan, PAGE_SIZE); /* src_pitch */ + OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ + OUT_RING (chan, PAGE_SIZE); /* line_length */ + OUT_RING (chan, line_count); + BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); + OUT_RING (chan, 0x00100110); + + page_count -= line_count; + src_offset += (PAGE_SIZE * line_count); + dst_offset += (PAGE_SIZE * line_count); + } + + return 0; +} + +int +nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle) +{ + int ret = RING_SPACE(chan, 2); + if (ret == 0) { + BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); + OUT_RING (chan, handle); + } + return ret; +} -- cgit v1.2.3 From 01c43a66eb7aac48b3a978158cfb45674b18a48e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 15:54:52 +1000 Subject: drm/nouveau/bo: convert move init() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_bo0039.c | 19 +++++++++++-------- drivers/gpu/drm/nouveau/nouveau_bo5039.c | 23 +++++++++++++---------- drivers/gpu/drm/nouveau/nouveau_bo9039.c | 17 +++++++++++------ drivers/gpu/drm/nouveau/nouveau_boa0b5.c | 18 +++++++++++------- 4 files changed, 46 insertions(+), 31 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nouveau_bo9039.c') diff --git a/drivers/gpu/drm/nouveau/nouveau_bo0039.c b/drivers/gpu/drm/nouveau/nouveau_bo0039.c index d5e9a200a64c..ddf2f5ee1140 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo0039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo0039.c @@ -30,6 +30,8 @@ #include "nouveau_dma.h" #include "nouveau_drv.h" +#include + static inline uint32_t nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, struct nouveau_channel *chan, struct ttm_mem_reg *reg) @@ -88,13 +90,14 @@ nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, int nv04_bo_move_init(struct nouveau_channel *chan, u32 handle) { - int ret = RING_SPACE(chan, 4); - if (ret == 0) { - BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); - OUT_RING (chan, handle); - BEGIN_NV04(chan, NvSubCopy, 0x0180, 1); - OUT_RING (chan, chan->drm->ntfy.handle); - } + struct nvif_push *push = chan->chan.push; + int ret; - return ret; + ret = PUSH_WAIT(push, 4); + if (ret) + return ret; + + PUSH_NVSQ(push, NV039, 0x0000, handle); + PUSH_NVSQ(push, NV039, 0x0180, chan->drm->ntfy.handle); + return 0; } diff --git a/drivers/gpu/drm/nouveau/nouveau_bo5039.c b/drivers/gpu/drm/nouveau/nouveau_bo5039.c index a047f7943e6d..9a667dc93dd3 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo5039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo5039.c @@ -31,6 +31,8 @@ #include "nouveau_drv.h" #include "nouveau_mem.h" +#include + int nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) @@ -107,15 +109,16 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, int nv50_bo_move_init(struct nouveau_channel *chan, u32 handle) { - int ret = RING_SPACE(chan, 6); - if (ret == 0) { - BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); - OUT_RING (chan, handle); - BEGIN_NV04(chan, NvSubCopy, 0x0180, 3); - OUT_RING (chan, chan->drm->ntfy.handle); - OUT_RING (chan, chan->vram.handle); - OUT_RING (chan, chan->vram.handle); - } + struct nvif_push *push = chan->chan.push; + int ret; - return ret; + ret = PUSH_WAIT(push, 6); + if (ret) + return ret; + + PUSH_NVSQ(push, NV5039, 0x0000, handle); + PUSH_NVSQ(push, NV5039, 0x0180, chan->drm->ntfy.handle, + 0x0184, chan->vram.handle, + 0x0188, chan->vram.handle); + return 0; } diff --git a/drivers/gpu/drm/nouveau/nouveau_bo9039.c b/drivers/gpu/drm/nouveau/nouveau_bo9039.c index 14424f6c3f59..f9ba04faf1a2 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo9039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo9039.c @@ -30,6 +30,8 @@ #include "nouveau_dma.h" #include "nouveau_mem.h" +#include + int nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) @@ -72,10 +74,13 @@ nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, int nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle) { - int ret = RING_SPACE(chan, 2); - if (ret == 0) { - BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); - OUT_RING (chan, handle); - } - return ret; + struct nvif_push *push = chan->chan.push; + int ret; + + ret = PUSH_WAIT(push, 2); + if (ret) + return ret; + + PUSH_NVSQ(push, NV9039, 0x0000, handle); + return 0; } diff --git a/drivers/gpu/drm/nouveau/nouveau_boa0b5.c b/drivers/gpu/drm/nouveau/nouveau_boa0b5.c index 55529ee4e823..9c09691623d0 100644 --- a/drivers/gpu/drm/nouveau/nouveau_boa0b5.c +++ b/drivers/gpu/drm/nouveau/nouveau_boa0b5.c @@ -30,6 +30,8 @@ #include "nouveau_dma.h" #include "nouveau_mem.h" +#include + int nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) @@ -54,11 +56,13 @@ nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, int nve0_bo_move_init(struct nouveau_channel *chan, u32 handle) { - int ret = RING_SPACE(chan, 2); - if (ret == 0) { - BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); - OUT_RING (chan, handle & 0x0000ffff); - FIRE_RING (chan); - } - return ret; + struct nvif_push *push = chan->chan.push; + int ret; + + ret = PUSH_WAIT(push, 2); + if (ret) + return ret; + + PUSH_NVSQ(push, NVA0B5, 0x0000, handle & 0x0000ffff); + return 0; } -- cgit v1.2.3 From fe4249afd6a94363e2ef7334d5257171da474bb6 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 16:20:32 +1000 Subject: drm/nouveau/bo: convert move move() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_bo0039.c | 31 +++++++-------- drivers/gpu/drm/nouveau/nouveau_bo5039.c | 65 +++++++++++++++----------------- drivers/gpu/drm/nouveau/nouveau_bo74c1.c | 27 +++++++------ drivers/gpu/drm/nouveau/nouveau_bo85b5.c | 25 ++++++------ drivers/gpu/drm/nouveau/nouveau_bo9039.c | 24 ++++++------ drivers/gpu/drm/nouveau/nouveau_bo90b5.c | 25 ++++++------ drivers/gpu/drm/nouveau/nouveau_boa0b5.c | 31 ++++++++------- drivers/gpu/drm/nouveau/nouveau_dma.h | 17 --------- 8 files changed, 114 insertions(+), 131 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nouveau_bo9039.c') diff --git a/drivers/gpu/drm/nouveau/nouveau_bo0039.c b/drivers/gpu/drm/nouveau/nouveau_bo0039.c index ddf2f5ee1140..e00ec7cfce5f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo0039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo0039.c @@ -45,39 +45,36 @@ int nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { + struct nvif_push *push = chan->chan.push; u32 src_offset = old_reg->start << PAGE_SHIFT; u32 dst_offset = new_reg->start << PAGE_SHIFT; u32 page_count = new_reg->num_pages; int ret; - ret = RING_SPACE(chan, 3); + ret = PUSH_WAIT(push, 3); if (ret) return ret; - BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); - OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_reg)); - OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_reg)); + PUSH_NVSQ(push, NV039, 0x0184, nouveau_bo_mem_ctxdma(bo, chan, old_reg), + 0x0188, nouveau_bo_mem_ctxdma(bo, chan, new_reg)); page_count = new_reg->num_pages; while (page_count) { int line_count = (page_count > 2047) ? 2047 : page_count; - ret = RING_SPACE(chan, 11); + ret = PUSH_WAIT(push, 11); if (ret) return ret; - BEGIN_NV04(chan, NvSubCopy, - NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); - OUT_RING (chan, src_offset); - OUT_RING (chan, dst_offset); - OUT_RING (chan, PAGE_SIZE); /* src_pitch */ - OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ - OUT_RING (chan, PAGE_SIZE); /* line_length */ - OUT_RING (chan, line_count); - OUT_RING (chan, 0x00000101); - OUT_RING (chan, 0x00000000); - BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); - OUT_RING (chan, 0); + PUSH_NVSQ(push, NV039, 0x030c, src_offset, + 0x0310, dst_offset, + 0x0314, PAGE_SIZE, /* src_pitch */ + 0x0318, PAGE_SIZE, /* dst_pitch */ + 0x031c, PAGE_SIZE, /* line_length */ + 0x0320, line_count, + 0x0324, 0x00000101, + 0x0328, 0x00000000); + PUSH_NVSQ(push, NV039, 0x0100, 0x00000000); page_count -= line_count; src_offset += (PAGE_SIZE * line_count); diff --git a/drivers/gpu/drm/nouveau/nouveau_bo5039.c b/drivers/gpu/drm/nouveau/nouveau_bo5039.c index 9a667dc93dd3..19fb36b35ff9 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo5039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo5039.c @@ -38,6 +38,7 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { struct nouveau_mem *mem = nouveau_mem(old_reg); + struct nvif_push *push = chan->chan.push; u64 length = (new_reg->num_pages << PAGE_SHIFT); u64 src_offset = mem->vma[0].addr; u64 dst_offset = mem->vma[1].addr; @@ -48,7 +49,7 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, while (length) { u32 amount, stride, height; - ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled)); + ret = PUSH_WAIT(push, 18 + 6 * (src_tiled + dst_tiled)); if (ret) return ret; @@ -57,46 +58,40 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, height = amount / stride; if (src_tiled) { - BEGIN_NV04(chan, NvSubCopy, 0x0200, 7); - OUT_RING (chan, 0); - OUT_RING (chan, 0); - OUT_RING (chan, stride); - OUT_RING (chan, height); - OUT_RING (chan, 1); - OUT_RING (chan, 0); - OUT_RING (chan, 0); + PUSH_NVSQ(push, NV5039, 0x0200, 0, + 0x0204, 0, + 0x0208, stride, + 0x020c, height, + 0x0210, 1, + 0x0214, 0, + 0x0218, 0); } else { - BEGIN_NV04(chan, NvSubCopy, 0x0200, 1); - OUT_RING (chan, 1); + PUSH_NVSQ(push, NV5039, 0x0200, 1); } + if (dst_tiled) { - BEGIN_NV04(chan, NvSubCopy, 0x021c, 7); - OUT_RING (chan, 0); - OUT_RING (chan, 0); - OUT_RING (chan, stride); - OUT_RING (chan, height); - OUT_RING (chan, 1); - OUT_RING (chan, 0); - OUT_RING (chan, 0); + PUSH_NVSQ(push, NV5039, 0x021c, 0, + 0x0220, 0, + 0x0224, stride, + 0x0228, height, + 0x022c, 1, + 0x0230, 0, + 0x0234, 0); } else { - BEGIN_NV04(chan, NvSubCopy, 0x021c, 1); - OUT_RING (chan, 1); + PUSH_NVSQ(push, NV5039, 0x021c, 1); } - BEGIN_NV04(chan, NvSubCopy, 0x0238, 2); - OUT_RING (chan, upper_32_bits(src_offset)); - OUT_RING (chan, upper_32_bits(dst_offset)); - BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); - OUT_RING (chan, lower_32_bits(src_offset)); - OUT_RING (chan, lower_32_bits(dst_offset)); - OUT_RING (chan, stride); - OUT_RING (chan, stride); - OUT_RING (chan, stride); - OUT_RING (chan, height); - OUT_RING (chan, 0x00000101); - OUT_RING (chan, 0x00000000); - BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); - OUT_RING (chan, 0); + PUSH_NVSQ(push, NV5039, 0x0238, upper_32_bits(src_offset), + 0x023c, upper_32_bits(dst_offset)); + PUSH_NVSQ(push, NV5039, 0x030c, lower_32_bits(src_offset), + 0x0310, lower_32_bits(dst_offset), + 0x0314, stride, + 0x0318, stride, + 0x031c, stride, + 0x0320, height, + 0x0324, 0x00000101, + 0x0328, 0x00000000); + PUSH_NVSQ(push, NV5039, 0x0100, 0x00000000); length -= amount; src_offset += amount; diff --git a/drivers/gpu/drm/nouveau/nouveau_bo74c1.c b/drivers/gpu/drm/nouveau/nouveau_bo74c1.c index 7528a03229b2..1b5fd78ddcba 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo74c1.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo74c1.c @@ -30,20 +30,25 @@ #include "nouveau_dma.h" #include "nouveau_mem.h" +#include + int nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { struct nouveau_mem *mem = nouveau_mem(old_reg); - int ret = RING_SPACE(chan, 7); - if (ret == 0) { - BEGIN_NV04(chan, NvSubCopy, 0x0304, 6); - OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); - OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); - OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); - OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); - OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); - OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */); - } - return ret; + struct nvif_push *push = chan->chan.push; + int ret; + + ret = PUSH_WAIT(push, 7); + if (ret) + return ret; + + PUSH_NVSQ(push, NV74C1, 0x0304, new_reg->num_pages << PAGE_SHIFT, + 0x0308, upper_32_bits(mem->vma[0].addr), + 0x030c, lower_32_bits(mem->vma[0].addr), + 0x0310, upper_32_bits(mem->vma[1].addr), + 0x0314, lower_32_bits(mem->vma[1].addr), + 0x0318, 0x00000000 /* MODE_COPY, QUERY_NONE */); + return 0; } diff --git a/drivers/gpu/drm/nouveau/nouveau_bo85b5.c b/drivers/gpu/drm/nouveau/nouveau_bo85b5.c index c658c5e5fe04..f0df172b029e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo85b5.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo85b5.c @@ -30,6 +30,8 @@ #include "nouveau_dma.h" #include "nouveau_mem.h" +#include + /*XXX: Fixup class to be compatible with NVIDIA's, which will allow sharing * code with KeplerDmaCopyA. */ @@ -39,6 +41,7 @@ nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { struct nouveau_mem *mem = nouveau_mem(old_reg); + struct nvif_push *push = chan->chan.push; u64 src_offset = mem->vma[0].addr; u64 dst_offset = mem->vma[1].addr; u32 page_count = new_reg->num_pages; @@ -48,21 +51,19 @@ nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, while (page_count) { int line_count = (page_count > 8191) ? 8191 : page_count; - ret = RING_SPACE(chan, 11); + ret = PUSH_WAIT(push, 11); if (ret) return ret; - BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); - OUT_RING (chan, upper_32_bits(src_offset)); - OUT_RING (chan, lower_32_bits(src_offset)); - OUT_RING (chan, upper_32_bits(dst_offset)); - OUT_RING (chan, lower_32_bits(dst_offset)); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, line_count); - BEGIN_NV04(chan, NvSubCopy, 0x0300, 1); - OUT_RING (chan, 0x00000110); + PUSH_NVSQ(push, NV85B5, 0x030c, upper_32_bits(src_offset), + 0x0310, lower_32_bits(src_offset), + 0x0314, upper_32_bits(dst_offset), + 0x0318, lower_32_bits(dst_offset), + 0x031c, PAGE_SIZE, + 0x0320, PAGE_SIZE, + 0x0324, PAGE_SIZE, + 0x0328, line_count); + PUSH_NVSQ(push, NV85B5, 0x0300, 0x00000110); page_count -= line_count; src_offset += (PAGE_SIZE * line_count); diff --git a/drivers/gpu/drm/nouveau/nouveau_bo9039.c b/drivers/gpu/drm/nouveau/nouveau_bo9039.c index f9ba04faf1a2..995ebe7ffe00 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo9039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo9039.c @@ -36,6 +36,7 @@ int nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { + struct nvif_push *push = chan->chan.push; struct nouveau_mem *mem = nouveau_mem(old_reg); u64 src_offset = mem->vma[0].addr; u64 dst_offset = mem->vma[1].addr; @@ -46,22 +47,19 @@ nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, while (page_count) { int line_count = (page_count > 2047) ? 2047 : page_count; - ret = RING_SPACE(chan, 12); + ret = PUSH_WAIT(push, 12); if (ret) return ret; - BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2); - OUT_RING (chan, upper_32_bits(dst_offset)); - OUT_RING (chan, lower_32_bits(dst_offset)); - BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6); - OUT_RING (chan, upper_32_bits(src_offset)); - OUT_RING (chan, lower_32_bits(src_offset)); - OUT_RING (chan, PAGE_SIZE); /* src_pitch */ - OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ - OUT_RING (chan, PAGE_SIZE); /* line_length */ - OUT_RING (chan, line_count); - BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); - OUT_RING (chan, 0x00100110); + PUSH_NVSQ(push, NV9039, 0x0238, upper_32_bits(dst_offset), + 0x023c, lower_32_bits(dst_offset)); + PUSH_NVSQ(push, NV9039, 0x030c, upper_32_bits(src_offset), + 0x0310, lower_32_bits(src_offset), + 0x0314, PAGE_SIZE, /* src_pitch */ + 0x0318, PAGE_SIZE, /* dst_pitch */ + 0x031c, PAGE_SIZE, /* line_length */ + 0x0320, line_count); + PUSH_NVSQ(push, NV9039, 0x0300, 0x00100110); page_count -= line_count; src_offset += (PAGE_SIZE * line_count); diff --git a/drivers/gpu/drm/nouveau/nouveau_bo90b5.c b/drivers/gpu/drm/nouveau/nouveau_bo90b5.c index 4c014f9a641f..34b79d561c7f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo90b5.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo90b5.c @@ -23,6 +23,8 @@ #include "nouveau_dma.h" #include "nouveau_mem.h" +#include + /*XXX: Fixup class to be compatible with NVIDIA's, which will allow sharing * code with KeplerDmaCopyA. */ @@ -32,6 +34,7 @@ nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { struct nouveau_mem *mem = nouveau_mem(old_reg); + struct nvif_push *push = chan->chan.push; u64 src_offset = mem->vma[0].addr; u64 dst_offset = mem->vma[1].addr; u32 page_count = new_reg->num_pages; @@ -41,21 +44,19 @@ nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, while (page_count) { int line_count = (page_count > 8191) ? 8191 : page_count; - ret = RING_SPACE(chan, 11); + ret = PUSH_WAIT(push, 10); if (ret) return ret; - BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8); - OUT_RING (chan, upper_32_bits(src_offset)); - OUT_RING (chan, lower_32_bits(src_offset)); - OUT_RING (chan, upper_32_bits(dst_offset)); - OUT_RING (chan, lower_32_bits(dst_offset)); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, line_count); - BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); - OUT_RING (chan, 0x00000110); + PUSH_NVSQ(push, NV90B5, 0x030c, upper_32_bits(src_offset), + 0x0310, lower_32_bits(src_offset), + 0x0314, upper_32_bits(dst_offset), + 0x0318, lower_32_bits(dst_offset), + 0x031c, PAGE_SIZE, + 0x0320, PAGE_SIZE, + 0x0324, PAGE_SIZE, + 0x0328, line_count); + PUSH_NVIM(push, NV90B5, 0x0300, 0x0110); page_count -= line_count; src_offset += (PAGE_SIZE * line_count); diff --git a/drivers/gpu/drm/nouveau/nouveau_boa0b5.c b/drivers/gpu/drm/nouveau/nouveau_boa0b5.c index 9c09691623d0..b1afb2724fb7 100644 --- a/drivers/gpu/drm/nouveau/nouveau_boa0b5.c +++ b/drivers/gpu/drm/nouveau/nouveau_boa0b5.c @@ -37,20 +37,23 @@ nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { struct nouveau_mem *mem = nouveau_mem(old_reg); - int ret = RING_SPACE(chan, 10); - if (ret == 0) { - BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8); - OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); - OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); - OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); - OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, new_reg->num_pages); - BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386); - } - return ret; + struct nvif_push *push = chan->chan.push; + int ret; + + ret = PUSH_WAIT(push, 10); + if (ret) + return ret; + + PUSH_NVSQ(push, NVA0B5, 0x0400, upper_32_bits(mem->vma[0].addr), + 0x0404, lower_32_bits(mem->vma[0].addr), + 0x0408, upper_32_bits(mem->vma[1].addr), + 0x040c, lower_32_bits(mem->vma[1].addr), + 0x0410, PAGE_SIZE, + 0x0414, PAGE_SIZE, + 0x0418, PAGE_SIZE, + 0x041c, new_reg->num_pages); + PUSH_NVIM(push, NVA0B5, 0x0300, 0x0386); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index 72de20437542..8778fd6002c0 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -63,23 +63,6 @@ enum { NvEvoSema1 = 0x80000011, }; -#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039 -#define NV_MEMORY_TO_MEMORY_FORMAT_NAME 0x00000000 -#define NV_MEMORY_TO_MEMORY_FORMAT_SET_REF 0x00000050 -#define NV_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100 -#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 -#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE 0x00000000 -#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN 0x00000001 -#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY 0x00000180 -#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE 0x00000184 -#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c - -#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039 -#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK200 0x00000200 -#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK21C 0x0000021c -#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238 -#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c - static __must_check inline int RING_SPACE(struct nouveau_channel *chan, int size) { -- cgit v1.2.3 From e767835a52cd6d427a4ab6941118e530cbfa638c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 16:29:45 +1000 Subject: drm/nouveau/bo: use NVIDIA's headers for move init() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- .../gpu/drm/nouveau/include/nvhw/class/cl0039.h | 45 ++++++ .../gpu/drm/nouveau/include/nvhw/class/cl5039.h | 153 +++++++++++++++++++++ .../gpu/drm/nouveau/include/nvhw/class/cl9039.h | 74 ++++++++++ drivers/gpu/drm/nouveau/nouveau_bo0039.c | 6 +- drivers/gpu/drm/nouveau/nouveau_bo5039.c | 10 +- drivers/gpu/drm/nouveau/nouveau_bo9039.c | 4 +- 6 files changed, 285 insertions(+), 7 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl0039.h create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl5039.h create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl9039.h (limited to 'drivers/gpu/drm/nouveau/nouveau_bo9039.c') diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl0039.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl0039.h new file mode 100644 index 000000000000..5386ed64ab72 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl0039.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2001-2001, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0039_h_ +#define _cl0039_h_ + +/* dma method offsets, fields, and values */ +#define NV039_SET_OBJECT (0x00000000) +#define NV039_NO_OPERATION (0x00000100) +#define NV039_SET_CONTEXT_DMA_NOTIFIES (0x00000180) +#define NV039_SET_CONTEXT_DMA_BUFFER_IN (0x00000184) +#define NV039_SET_CONTEXT_DMA_BUFFER_OUT (0x00000188) + +#define NV039_OFFSET_IN (0x0000030C) +#define NV039_OFFSET_OUT (0x00000310) +#define NV039_PITCH_IN (0x00000314) +#define NV039_PITCH_OUT (0x00000318) +#define NV039_LINE_LENGTH_IN (0x0000031C) +#define NV039_LINE_COUNT (0x00000320) +#define NV039_FORMAT (0x00000324) +#define NV039_FORMAT_IN 7:0 +#define NV039_FORMAT_OUT 31:8 +#define NV039_BUFFER_NOTIFY (0x00000328) +#define NV039_BUFFER_NOTIFY_WRITE_ONLY (0x00000000) +#define NV039_BUFFER_NOTIFY_WRITE_THEN_AWAKEN (0x00000001) +#endif /* _cl0039_h_ */ diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl5039.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl5039.h new file mode 100644 index 000000000000..5b2ca337cf2b --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl5039.h @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_nv50_memory_to_memory_format_h_ +#define _cl_nv50_memory_to_memory_format_h_ + +#define NV5039_SET_OBJECT 0x0000 +#define NV5039_SET_OBJECT_POINTER 15:0 + +#define NV5039_NO_OPERATION 0x0100 +#define NV5039_NO_OPERATION_V 31:0 + +#define NV5039_SET_CONTEXT_DMA_NOTIFY 0x0180 +#define NV5039_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0 + +#define NV5039_SET_CONTEXT_DMA_BUFFER_IN 0x0184 +#define NV5039_SET_CONTEXT_DMA_BUFFER_IN_HANDLE 31:0 + +#define NV5039_SET_CONTEXT_DMA_BUFFER_OUT 0x0188 +#define NV5039_SET_CONTEXT_DMA_BUFFER_OUT_HANDLE 31:0 + +#define NV5039_SET_SRC_MEMORY_LAYOUT 0x0200 +#define NV5039_SET_SRC_MEMORY_LAYOUT_V 0:0 +#define NV5039_SET_SRC_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000 +#define NV5039_SET_SRC_MEMORY_LAYOUT_V_PITCH 0x00000001 + +#define NV5039_SET_SRC_BLOCK_SIZE 0x0204 +#define NV5039_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NV5039_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NV5039_SET_SRC_WIDTH 0x0208 +#define NV5039_SET_SRC_WIDTH_V 31:0 + +#define NV5039_SET_SRC_HEIGHT 0x020c +#define NV5039_SET_SRC_HEIGHT_V 31:0 + +#define NV5039_SET_SRC_DEPTH 0x0210 +#define NV5039_SET_SRC_DEPTH_V 31:0 + +#define NV5039_SET_SRC_LAYER 0x0214 +#define NV5039_SET_SRC_LAYER_V 31:0 + +#define NV5039_SET_SRC_ORIGIN 0x0218 +#define NV5039_SET_SRC_ORIGIN_X 15:0 +#define NV5039_SET_SRC_ORIGIN_Y 31:16 + +#define NV5039_SET_DST_MEMORY_LAYOUT 0x021c +#define NV5039_SET_DST_MEMORY_LAYOUT_V 0:0 +#define NV5039_SET_DST_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000 +#define NV5039_SET_DST_MEMORY_LAYOUT_V_PITCH 0x00000001 + +#define NV5039_SET_DST_BLOCK_SIZE 0x0220 +#define NV5039_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NV5039_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV5039_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NV5039_SET_DST_WIDTH 0x0224 +#define NV5039_SET_DST_WIDTH_V 31:0 + +#define NV5039_SET_DST_HEIGHT 0x0228 +#define NV5039_SET_DST_HEIGHT_V 31:0 + +#define NV5039_SET_DST_DEPTH 0x022c +#define NV5039_SET_DST_DEPTH_V 31:0 + +#define NV5039_SET_DST_LAYER 0x0230 +#define NV5039_SET_DST_LAYER_V 31:0 + +#define NV5039_SET_DST_ORIGIN 0x0234 +#define NV5039_SET_DST_ORIGIN_X 15:0 +#define NV5039_SET_DST_ORIGIN_Y 31:16 + +#define NV5039_OFFSET_IN_UPPER 0x0238 +#define NV5039_OFFSET_IN_UPPER_VALUE 7:0 + +#define NV5039_OFFSET_OUT_UPPER 0x023c +#define NV5039_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NV5039_OFFSET_IN 0x030c +#define NV5039_OFFSET_IN_VALUE 31:0 + +#define NV5039_OFFSET_OUT 0x0310 +#define NV5039_OFFSET_OUT_VALUE 31:0 + +#define NV5039_PITCH_IN 0x0314 +#define NV5039_PITCH_IN_VALUE 31:0 + +#define NV5039_PITCH_OUT 0x0318 +#define NV5039_PITCH_OUT_VALUE 31:0 + +#define NV5039_LINE_LENGTH_IN 0x031c +#define NV5039_LINE_LENGTH_IN_VALUE 31:0 + +#define NV5039_LINE_COUNT 0x0320 +#define NV5039_LINE_COUNT_VALUE 31:0 + +#define NV5039_FORMAT 0x0324 +#define NV5039_FORMAT_IN 7:0 +#define NV5039_FORMAT_IN_ONE 0x00000001 +#define NV5039_FORMAT_OUT 15:8 +#define NV5039_FORMAT_OUT_ONE 0x00000001 + +#define NV5039_BUFFER_NOTIFY 0x0328 +#define NV5039_BUFFER_NOTIFY_TYPE 31:0 +#define NV5039_BUFFER_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NV5039_BUFFER_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 +#endif /* _cl_nv50_memory_to_memory_format_h_ */ diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl9039.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl9039.h new file mode 100644 index 000000000000..b8282a615ec0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl9039.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_fermi_memory_to_memory_format_a_h_ +#define _cl_fermi_memory_to_memory_format_a_h_ + +#define NV9039_SET_OBJECT 0x0000 +#define NV9039_SET_OBJECT_CLASS_ID 15:0 +#define NV9039_SET_OBJECT_ENGINE_ID 20:16 + +#define NV9039_OFFSET_OUT_UPPER 0x0238 +#define NV9039_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NV9039_OFFSET_OUT 0x023c +#define NV9039_OFFSET_OUT_VALUE 31:0 + +#define NV9039_LAUNCH_DMA 0x0300 +#define NV9039_LAUNCH_DMA_SRC_INLINE 0:0 +#define NV9039_LAUNCH_DMA_SRC_INLINE_FALSE 0x00000000 +#define NV9039_LAUNCH_DMA_SRC_INLINE_TRUE 0x00000001 +#define NV9039_LAUNCH_DMA_SRC_MEMORY_LAYOUT 4:4 +#define NV9039_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NV9039_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH 0x00000001 +#define NV9039_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NV9039_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NV9039_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NV9039_LAUNCH_DMA_COMPLETION_TYPE 13:12 +#define NV9039_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NV9039_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NV9039_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NV9039_LAUNCH_DMA_INTERRUPT_TYPE 17:16 +#define NV9039_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NV9039_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NV9039_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 20:20 +#define NV9039_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NV9039_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 + +#define NV9039_OFFSET_IN_UPPER 0x030c +#define NV9039_OFFSET_IN_UPPER_VALUE 7:0 + +#define NV9039_OFFSET_IN 0x0310 +#define NV9039_OFFSET_IN_VALUE 31:0 + +#define NV9039_PITCH_IN 0x0314 +#define NV9039_PITCH_IN_VALUE 31:0 + +#define NV9039_PITCH_OUT 0x0318 +#define NV9039_PITCH_OUT_VALUE 31:0 + +#define NV9039_LINE_LENGTH_IN 0x031c +#define NV9039_LINE_LENGTH_IN_VALUE 31:0 + +#define NV9039_LINE_COUNT 0x0320 +#define NV9039_LINE_COUNT_VALUE 31:0 +#endif /* _cl_fermi_memory_to_memory_format_a_h_ */ diff --git a/drivers/gpu/drm/nouveau/nouveau_bo0039.c b/drivers/gpu/drm/nouveau/nouveau_bo0039.c index e00ec7cfce5f..8f1f78b0105d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo0039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo0039.c @@ -32,6 +32,8 @@ #include +#include + static inline uint32_t nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, struct nouveau_channel *chan, struct ttm_mem_reg *reg) @@ -94,7 +96,7 @@ nv04_bo_move_init(struct nouveau_channel *chan, u32 handle) if (ret) return ret; - PUSH_NVSQ(push, NV039, 0x0000, handle); - PUSH_NVSQ(push, NV039, 0x0180, chan->drm->ntfy.handle); + PUSH_MTHD(push, NV039, SET_OBJECT, handle); + PUSH_MTHD(push, NV039, SET_CONTEXT_DMA_NOTIFIES, chan->drm->ntfy.handle); return 0; } diff --git a/drivers/gpu/drm/nouveau/nouveau_bo5039.c b/drivers/gpu/drm/nouveau/nouveau_bo5039.c index 19fb36b35ff9..232877f8b93d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo5039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo5039.c @@ -33,6 +33,8 @@ #include +#include + int nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) @@ -111,9 +113,9 @@ nv50_bo_move_init(struct nouveau_channel *chan, u32 handle) if (ret) return ret; - PUSH_NVSQ(push, NV5039, 0x0000, handle); - PUSH_NVSQ(push, NV5039, 0x0180, chan->drm->ntfy.handle, - 0x0184, chan->vram.handle, - 0x0188, chan->vram.handle); + PUSH_MTHD(push, NV5039, SET_OBJECT, handle); + PUSH_MTHD(push, NV5039, SET_CONTEXT_DMA_NOTIFY, chan->drm->ntfy.handle, + SET_CONTEXT_DMA_BUFFER_IN, chan->vram.handle, + SET_CONTEXT_DMA_BUFFER_OUT, chan->vram.handle); return 0; } diff --git a/drivers/gpu/drm/nouveau/nouveau_bo9039.c b/drivers/gpu/drm/nouveau/nouveau_bo9039.c index 995ebe7ffe00..785d831e5d18 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo9039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo9039.c @@ -32,6 +32,8 @@ #include +#include + int nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) @@ -79,6 +81,6 @@ nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle) if (ret) return ret; - PUSH_NVSQ(push, NV9039, 0x0000, handle); + PUSH_MTHD(push, NV9039, SET_OBJECT, handle); return 0; } -- cgit v1.2.3 From 6c75137274b050e9baaa5b2904b165a49c671273 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 17:07:31 +1000 Subject: drm/nouveau/bo: use NVIDIA's headers for move move() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- .../gpu/drm/nouveau/include/nvhw/class/cla0b5.h | 162 +++++++++++++++++++++ drivers/gpu/drm/nouveau/nouveau_bo0039.c | 29 ++-- drivers/gpu/drm/nouveau/nouveau_bo5039.c | 84 +++++++---- drivers/gpu/drm/nouveau/nouveau_bo9039.c | 30 ++-- drivers/gpu/drm/nouveau/nouveau_boa0b5.c | 37 +++-- 5 files changed, 286 insertions(+), 56 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cla0b5.h (limited to 'drivers/gpu/drm/nouveau/nouveau_bo9039.c') diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cla0b5.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cla0b5.h new file mode 100644 index 000000000000..fe5d10f05468 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cla0b5.h @@ -0,0 +1,162 @@ +/******************************************************************************* + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cla0b5_h_ +#define _cla0b5_h_ + +#define NVA0B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVA0B5_SET_DST_PHYS_MODE (0x00000264) +#define NVA0B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVA0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVA0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVA0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVA0B5_LAUNCH_DMA (0x00000300) +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVA0B5_LAUNCH_DMA_BYPASS_L2 11:11 +#define NVA0B5_LAUNCH_DMA_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVA0B5_LAUNCH_DMA_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVA0B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVA0B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVA0B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVA0B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVA0B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVA0B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN (0x0000000B) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX (0x0000000C) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMUL (0x0000000D) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMUL (0x0000000E) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVA0B5_OFFSET_IN_UPPER (0x00000400) +#define NVA0B5_OFFSET_IN_UPPER_UPPER 7:0 +#define NVA0B5_OFFSET_IN_LOWER (0x00000404) +#define NVA0B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVA0B5_OFFSET_OUT_UPPER (0x00000408) +#define NVA0B5_OFFSET_OUT_UPPER_UPPER 7:0 +#define NVA0B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVA0B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVA0B5_PITCH_IN (0x00000410) +#define NVA0B5_PITCH_IN_VALUE 31:0 +#define NVA0B5_PITCH_OUT (0x00000414) +#define NVA0B5_PITCH_OUT_VALUE 31:0 +#define NVA0B5_LINE_LENGTH_IN (0x00000418) +#define NVA0B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVA0B5_LINE_COUNT (0x0000041C) +#define NVA0B5_LINE_COUNT_VALUE 31:0 +#define NVA0B5_SET_REMAP_CONST_A (0x00000700) +#define NVA0B5_SET_REMAP_CONST_A_V 31:0 +#define NVA0B5_SET_REMAP_CONST_B (0x00000704) +#define NVA0B5_SET_REMAP_CONST_B_V 31:0 +#define NVA0B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#endif // _cla0b5_h diff --git a/drivers/gpu/drm/nouveau/nouveau_bo0039.c b/drivers/gpu/drm/nouveau/nouveau_bo0039.c index 8f1f78b0105d..bf7ae2cecaf6 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo0039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo0039.c @@ -48,7 +48,9 @@ nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { struct nvif_push *push = chan->chan.push; + u32 src_ctxdma = nouveau_bo_mem_ctxdma(bo, chan, old_reg); u32 src_offset = old_reg->start << PAGE_SHIFT; + u32 dst_ctxdma = nouveau_bo_mem_ctxdma(bo, chan, new_reg); u32 dst_offset = new_reg->start << PAGE_SHIFT; u32 page_count = new_reg->num_pages; int ret; @@ -57,8 +59,8 @@ nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, if (ret) return ret; - PUSH_NVSQ(push, NV039, 0x0184, nouveau_bo_mem_ctxdma(bo, chan, old_reg), - 0x0188, nouveau_bo_mem_ctxdma(bo, chan, new_reg)); + PUSH_MTHD(push, NV039, SET_CONTEXT_DMA_BUFFER_IN, src_ctxdma, + SET_CONTEXT_DMA_BUFFER_OUT, dst_ctxdma); page_count = new_reg->num_pages; while (page_count) { @@ -68,15 +70,20 @@ nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, if (ret) return ret; - PUSH_NVSQ(push, NV039, 0x030c, src_offset, - 0x0310, dst_offset, - 0x0314, PAGE_SIZE, /* src_pitch */ - 0x0318, PAGE_SIZE, /* dst_pitch */ - 0x031c, PAGE_SIZE, /* line_length */ - 0x0320, line_count, - 0x0324, 0x00000101, - 0x0328, 0x00000000); - PUSH_NVSQ(push, NV039, 0x0100, 0x00000000); + PUSH_MTHD(push, NV039, OFFSET_IN, src_offset, + OFFSET_OUT, dst_offset, + PITCH_IN, PAGE_SIZE, + PITCH_OUT, PAGE_SIZE, + LINE_LENGTH_IN, PAGE_SIZE, + LINE_COUNT, line_count, + + FORMAT, + NVVAL(NV039, FORMAT, IN, 1) | + NVVAL(NV039, FORMAT, OUT, 1), + + BUFFER_NOTIFY, NV039_BUFFER_NOTIFY_WRITE_ONLY); + + PUSH_MTHD(push, NV039, NO_OPERATION, 0x00000000); page_count -= line_count; src_offset += (PAGE_SIZE * line_count); diff --git a/drivers/gpu/drm/nouveau/nouveau_bo5039.c b/drivers/gpu/drm/nouveau/nouveau_bo5039.c index 232877f8b93d..f9b9b85abe44 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo5039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo5039.c @@ -60,40 +60,70 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, height = amount / stride; if (src_tiled) { - PUSH_NVSQ(push, NV5039, 0x0200, 0, - 0x0204, 0, - 0x0208, stride, - 0x020c, height, - 0x0210, 1, - 0x0214, 0, - 0x0218, 0); + PUSH_MTHD(push, NV5039, SET_SRC_MEMORY_LAYOUT, + NVDEF(NV5039, SET_SRC_MEMORY_LAYOUT, V, BLOCKLINEAR), + + SET_SRC_BLOCK_SIZE, + NVDEF(NV5039, SET_SRC_BLOCK_SIZE, WIDTH, ONE_GOB) | + NVDEF(NV5039, SET_SRC_BLOCK_SIZE, HEIGHT, ONE_GOB) | + NVDEF(NV5039, SET_SRC_BLOCK_SIZE, DEPTH, ONE_GOB), + + SET_SRC_WIDTH, stride, + SET_SRC_HEIGHT, height, + SET_SRC_DEPTH, 1, + SET_SRC_LAYER, 0, + + SET_SRC_ORIGIN, + NVVAL(NV5039, SET_SRC_ORIGIN, X, 0) | + NVVAL(NV5039, SET_SRC_ORIGIN, Y, 0)); } else { - PUSH_NVSQ(push, NV5039, 0x0200, 1); + PUSH_MTHD(push, NV5039, SET_SRC_MEMORY_LAYOUT, + NVDEF(NV5039, SET_SRC_MEMORY_LAYOUT, V, PITCH)); } if (dst_tiled) { - PUSH_NVSQ(push, NV5039, 0x021c, 0, - 0x0220, 0, - 0x0224, stride, - 0x0228, height, - 0x022c, 1, - 0x0230, 0, - 0x0234, 0); + PUSH_MTHD(push, NV5039, SET_DST_MEMORY_LAYOUT, + NVDEF(NV5039, SET_DST_MEMORY_LAYOUT, V, BLOCKLINEAR), + + SET_DST_BLOCK_SIZE, + NVDEF(NV5039, SET_DST_BLOCK_SIZE, WIDTH, ONE_GOB) | + NVDEF(NV5039, SET_DST_BLOCK_SIZE, HEIGHT, ONE_GOB) | + NVDEF(NV5039, SET_DST_BLOCK_SIZE, DEPTH, ONE_GOB), + + SET_DST_WIDTH, stride, + SET_DST_HEIGHT, height, + SET_DST_DEPTH, 1, + SET_DST_LAYER, 0, + + SET_DST_ORIGIN, + NVVAL(NV5039, SET_DST_ORIGIN, X, 0) | + NVVAL(NV5039, SET_DST_ORIGIN, Y, 0)); } else { - PUSH_NVSQ(push, NV5039, 0x021c, 1); + PUSH_MTHD(push, NV5039, SET_DST_MEMORY_LAYOUT, + NVDEF(NV5039, SET_DST_MEMORY_LAYOUT, V, PITCH)); } - PUSH_NVSQ(push, NV5039, 0x0238, upper_32_bits(src_offset), - 0x023c, upper_32_bits(dst_offset)); - PUSH_NVSQ(push, NV5039, 0x030c, lower_32_bits(src_offset), - 0x0310, lower_32_bits(dst_offset), - 0x0314, stride, - 0x0318, stride, - 0x031c, stride, - 0x0320, height, - 0x0324, 0x00000101, - 0x0328, 0x00000000); - PUSH_NVSQ(push, NV5039, 0x0100, 0x00000000); + PUSH_MTHD(push, NV5039, OFFSET_IN_UPPER, + NVVAL(NV5039, OFFSET_IN_UPPER, VALUE, upper_32_bits(src_offset)), + + OFFSET_OUT_UPPER, + NVVAL(NV5039, OFFSET_OUT_UPPER, VALUE, upper_32_bits(dst_offset))); + + PUSH_MTHD(push, NV5039, OFFSET_IN, lower_32_bits(src_offset), + OFFSET_OUT, lower_32_bits(dst_offset), + PITCH_IN, stride, + PITCH_OUT, stride, + LINE_LENGTH_IN, stride, + LINE_COUNT, height, + + FORMAT, + NVDEF(NV5039, FORMAT, IN, ONE) | + NVDEF(NV5039, FORMAT, OUT, ONE), + + BUFFER_NOTIFY, + NVDEF(NV5039, BUFFER_NOTIFY, TYPE, WRITE_ONLY)); + + PUSH_MTHD(push, NV5039, NO_OPERATION, 0x00000000); length -= amount; src_offset += amount; diff --git a/drivers/gpu/drm/nouveau/nouveau_bo9039.c b/drivers/gpu/drm/nouveau/nouveau_bo9039.c index 785d831e5d18..52fefb37064c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo9039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo9039.c @@ -53,15 +53,27 @@ nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, if (ret) return ret; - PUSH_NVSQ(push, NV9039, 0x0238, upper_32_bits(dst_offset), - 0x023c, lower_32_bits(dst_offset)); - PUSH_NVSQ(push, NV9039, 0x030c, upper_32_bits(src_offset), - 0x0310, lower_32_bits(src_offset), - 0x0314, PAGE_SIZE, /* src_pitch */ - 0x0318, PAGE_SIZE, /* dst_pitch */ - 0x031c, PAGE_SIZE, /* line_length */ - 0x0320, line_count); - PUSH_NVSQ(push, NV9039, 0x0300, 0x00100110); + PUSH_MTHD(push, NV9039, OFFSET_OUT_UPPER, + NVVAL(NV9039, OFFSET_OUT_UPPER, VALUE, upper_32_bits(dst_offset)), + + OFFSET_OUT, lower_32_bits(dst_offset)); + + PUSH_MTHD(push, NV9039, OFFSET_IN_UPPER, + NVVAL(NV9039, OFFSET_IN_UPPER, VALUE, upper_32_bits(src_offset)), + + OFFSET_IN, lower_32_bits(src_offset), + PITCH_IN, PAGE_SIZE, + PITCH_OUT, PAGE_SIZE, + LINE_LENGTH_IN, PAGE_SIZE, + LINE_COUNT, line_count); + + PUSH_MTHD(push, NV9039, LAUNCH_DMA, + NVDEF(NV9039, LAUNCH_DMA, SRC_INLINE, FALSE) | + NVDEF(NV9039, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) | + NVDEF(NV9039, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) | + NVDEF(NV9039, LAUNCH_DMA, COMPLETION_TYPE, FLUSH_DISABLE) | + NVDEF(NV9039, LAUNCH_DMA, INTERRUPT_TYPE, NONE) | + NVDEF(NV9039, LAUNCH_DMA, SEMAPHORE_STRUCT_SIZE, ONE_WORD)); page_count -= line_count; src_offset += (PAGE_SIZE * line_count); diff --git a/drivers/gpu/drm/nouveau/nouveau_boa0b5.c b/drivers/gpu/drm/nouveau/nouveau_boa0b5.c index b1afb2724fb7..394e29012e50 100644 --- a/drivers/gpu/drm/nouveau/nouveau_boa0b5.c +++ b/drivers/gpu/drm/nouveau/nouveau_boa0b5.c @@ -32,6 +32,8 @@ #include +#include + int nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) @@ -44,15 +46,32 @@ nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, if (ret) return ret; - PUSH_NVSQ(push, NVA0B5, 0x0400, upper_32_bits(mem->vma[0].addr), - 0x0404, lower_32_bits(mem->vma[0].addr), - 0x0408, upper_32_bits(mem->vma[1].addr), - 0x040c, lower_32_bits(mem->vma[1].addr), - 0x0410, PAGE_SIZE, - 0x0414, PAGE_SIZE, - 0x0418, PAGE_SIZE, - 0x041c, new_reg->num_pages); - PUSH_NVIM(push, NVA0B5, 0x0300, 0x0386); + PUSH_MTHD(push, NVA0B5, OFFSET_IN_UPPER, + NVVAL(NVA0B5, OFFSET_IN_UPPER, UPPER, upper_32_bits(mem->vma[0].addr)), + + OFFSET_IN_LOWER, lower_32_bits(mem->vma[0].addr), + + OFFSET_OUT_UPPER, + NVVAL(NVA0B5, OFFSET_OUT_UPPER, UPPER, upper_32_bits(mem->vma[1].addr)), + + OFFSET_OUT_LOWER, lower_32_bits(mem->vma[1].addr), + PITCH_IN, PAGE_SIZE, + PITCH_OUT, PAGE_SIZE, + LINE_LENGTH_IN, PAGE_SIZE, + LINE_COUNT, new_reg->num_pages); + + PUSH_IMMD(push, NVA0B5, LAUNCH_DMA, + NVDEF(NVA0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED) | + NVDEF(NVA0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE) | + NVDEF(NVA0B5, LAUNCH_DMA, SEMAPHORE_TYPE, NONE) | + NVDEF(NVA0B5, LAUNCH_DMA, INTERRUPT_TYPE, NONE) | + NVDEF(NVA0B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) | + NVDEF(NVA0B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) | + NVDEF(NVA0B5, LAUNCH_DMA, MULTI_LINE_ENABLE, TRUE) | + NVDEF(NVA0B5, LAUNCH_DMA, REMAP_ENABLE, FALSE) | + NVDEF(NVA0B5, LAUNCH_DMA, BYPASS_L2, USE_PTE_SETTING) | + NVDEF(NVA0B5, LAUNCH_DMA, SRC_TYPE, VIRTUAL) | + NVDEF(NVA0B5, LAUNCH_DMA, DST_TYPE, VIRTUAL)); return 0; } -- cgit v1.2.3