From c943b4948b5848fc0e07f875edbd35a973879e22 Mon Sep 17 00:00:00 2001 From: Chandan Uddaraju Date: Thu, 27 Aug 2020 14:16:55 -0700 Subject: drm/msm/dp: add displayPort driver support Add the needed displayPort files to enable DP driver on msm target. "dp_display" module is the main module that calls into other sub-modules. "dp_drm" file represents the interface between DRM framework and DP driver. Changes in v12: -- Add support of pm ops in display port driver -- Clear bpp depth bits before writing to MISC register -- Fix edid read Previous Change log: https://lkml.kernel.org/lkml/20200818051137.21478-3-tanmay@codeaurora.org/ Signed-off-by: Chandan Uddaraju Signed-off-by: Vara Reddy Signed-off-by: Tanmay Shah Co-developed-by: Abhinav Kumar Signed-off-by: Abhinav Kumar Co-developed-by: Kuogee Hsieh Signed-off-by: Kuogee Hsieh Co-developed-by: Guenter Roeck Signed-off-by: Guenter Roeck Co-developed-by: Stephen Boyd Signed-off-by: Stephen Boyd Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 1694 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 1694 insertions(+) create mode 100644 drivers/gpu/drm/msm/dp/dp_ctrl.c (limited to 'drivers/gpu/drm/msm/dp/dp_ctrl.c') diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c new file mode 100644 index 000000000000..9a06cbf40af1 --- /dev/null +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -0,0 +1,1694 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + */ + +#define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__ + +#include +#include +#include +#include +#include + +#include "dp_reg.h" +#include "dp_ctrl.h" +#include "dp_link.h" + +#define DP_KHZ_TO_HZ 1000 +#define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */ +#define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2) + +#define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0) +#define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3) + +#define MR_LINK_TRAINING1 0x8 +#define MR_LINK_SYMBOL_ERM 0x80 +#define MR_LINK_PRBS7 0x100 +#define MR_LINK_CUSTOM80 0x200 + +struct dp_tu_calc_input { + u64 lclk; /* 162, 270, 540 and 810 */ + u64 pclk_khz; /* in KHz */ + u64 hactive; /* active h-width */ + u64 hporch; /* bp + fp + pulse */ + int nlanes; /* no.of.lanes */ + int bpp; /* bits */ + int pixel_enc; /* 444, 420, 422 */ + int dsc_en; /* dsc on/off */ + int async_en; /* async mode */ + int fec_en; /* fec */ + int compress_ratio; /* 2:1 = 200, 3:1 = 300, 3.75:1 = 375 */ + int num_of_dsc_slices; /* number of slices per line */ +}; + +struct dp_vc_tu_mapping_table { + u32 vic; + u8 lanes; + u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */ + u8 bpp; + u8 valid_boundary_link; + u16 delay_start_link; + bool boundary_moderation_en; + u8 valid_lower_boundary_link; + u8 upper_boundary_count; + u8 lower_boundary_count; + u8 tu_size_minus1; +}; + +struct dp_ctrl_private { + struct dp_ctrl dp_ctrl; + + struct device *dev; + struct drm_dp_aux *aux; + struct dp_panel *panel; + struct dp_link *link; + struct dp_power *power; + struct dp_parser *parser; + struct dp_catalog *catalog; + + struct completion idle_comp; + struct mutex push_idle_mutex; + struct completion video_comp; +}; + +static int dp_aux_link_configure(struct drm_dp_aux *aux, + struct dp_link_info *link) +{ + u8 values[2]; + int err; + + values[0] = drm_dp_link_rate_to_bw_code(link->rate); + values[1] = link->num_lanes; + + if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) + values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; + + err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values)); + if (err < 0) + return err; + + return 0; +} + +void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl) +{ + struct dp_ctrl_private *ctrl; + + ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); + + mutex_lock(&ctrl->push_idle_mutex); + + reinit_completion(&ctrl->idle_comp); + dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE); + + if (!wait_for_completion_timeout(&ctrl->idle_comp, + IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) + pr_warn("PUSH_IDLE pattern timedout\n"); + + mutex_unlock(&ctrl->push_idle_mutex); + pr_debug("mainlink off done\n"); +} + +static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl) +{ + u32 config = 0, tbd; + u8 *dpcd = ctrl->panel->dpcd; + + /* Default-> LSCLK DIV: 1/4 LCLK */ + config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); + + /* Scrambler reset enable */ + if (dpcd[DP_EDP_CONFIGURATION_CAP] & DP_ALTERNATE_SCRAMBLER_RESET_CAP) + config |= DP_CONFIGURATION_CTRL_ASSR; + + tbd = dp_link_get_test_bits_depth(ctrl->link, + ctrl->panel->dp_mode.bpp); + + if (tbd == DP_TEST_BIT_DEPTH_UNKNOWN) { + pr_debug("BIT_DEPTH not set. Configure default\n"); + tbd = DP_TEST_BIT_DEPTH_8; + } + + config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; + + /* Num of Lanes */ + config |= ((ctrl->link->link_params.num_lanes - 1) + << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT); + + if (drm_dp_enhanced_frame_cap(dpcd)) + config |= DP_CONFIGURATION_CTRL_ENHANCED_FRAMING; + + config |= DP_CONFIGURATION_CTRL_P_INTERLACED; /* progressive video */ + + /* sync clock & static Mvid */ + config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN; + config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK; + + dp_catalog_ctrl_config_ctrl(ctrl->catalog, config); +} + +static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl) +{ + u32 cc, tb; + + dp_catalog_ctrl_lane_mapping(ctrl->catalog); + dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); + + dp_ctrl_config_ctrl(ctrl); + + tb = dp_link_get_test_bits_depth(ctrl->link, + ctrl->panel->dp_mode.bpp); + cc = dp_link_get_colorimetry_config(ctrl->link); + dp_catalog_ctrl_config_misc(ctrl->catalog, cc, tb); + dp_panel_timing_cfg(ctrl->panel); +} + +/* + * The structure and few functions present below are IP/Hardware + * specific implementation. Most of the implementation will not + * have coding comments + */ +struct tu_algo_data { + s64 lclk_fp; + s64 pclk_fp; + s64 lwidth; + s64 lwidth_fp; + s64 hbp_relative_to_pclk; + s64 hbp_relative_to_pclk_fp; + int nlanes; + int bpp; + int pixelEnc; + int dsc_en; + int async_en; + int bpc; + + uint delay_start_link_extra_pixclk; + int extra_buffer_margin; + s64 ratio_fp; + s64 original_ratio_fp; + + s64 err_fp; + s64 n_err_fp; + s64 n_n_err_fp; + int tu_size; + int tu_size_desired; + int tu_size_minus1; + + int valid_boundary_link; + s64 resulting_valid_fp; + s64 total_valid_fp; + s64 effective_valid_fp; + s64 effective_valid_recorded_fp; + int n_tus; + int n_tus_per_lane; + int paired_tus; + int remainder_tus; + int remainder_tus_upper; + int remainder_tus_lower; + int extra_bytes; + int filler_size; + int delay_start_link; + + int extra_pclk_cycles; + int extra_pclk_cycles_in_link_clk; + s64 ratio_by_tu_fp; + s64 average_valid2_fp; + int new_valid_boundary_link; + int remainder_symbols_exist; + int n_symbols; + s64 n_remainder_symbols_per_lane_fp; + s64 last_partial_tu_fp; + s64 TU_ratio_err_fp; + + int n_tus_incl_last_incomplete_tu; + int extra_pclk_cycles_tmp; + int extra_pclk_cycles_in_link_clk_tmp; + int extra_required_bytes_new_tmp; + int filler_size_tmp; + int lower_filler_size_tmp; + int delay_start_link_tmp; + + bool boundary_moderation_en; + int boundary_mod_lower_err; + int upper_boundary_count; + int lower_boundary_count; + int i_upper_boundary_count; + int i_lower_boundary_count; + int valid_lower_boundary_link; + int even_distribution_BF; + int even_distribution_legacy; + int even_distribution; + int min_hblank_violated; + s64 delay_start_time_fp; + s64 hbp_time_fp; + s64 hactive_time_fp; + s64 diff_abs_fp; + + s64 ratio; +}; + +static int _tu_param_compare(s64 a, s64 b) +{ + u32 a_sign; + u32 b_sign; + s64 a_temp, b_temp, minus_1; + + if (a == b) + return 0; + + minus_1 = drm_fixp_from_fraction(-1, 1); + + a_sign = (a >> 32) & 0x80000000 ? 1 : 0; + + b_sign = (b >> 32) & 0x80000000 ? 1 : 0; + + if (a_sign > b_sign) + return 2; + else if (b_sign > a_sign) + return 1; + + if (!a_sign && !b_sign) { /* positive */ + if (a > b) + return 1; + else + return 2; + } else { /* negative */ + a_temp = drm_fixp_mul(a, minus_1); + b_temp = drm_fixp_mul(b, minus_1); + + if (a_temp > b_temp) + return 2; + else + return 1; + } +} + +static void dp_panel_update_tu_timings(struct dp_tu_calc_input *in, + struct tu_algo_data *tu) +{ + int nlanes = in->nlanes; + int dsc_num_slices = in->num_of_dsc_slices; + int dsc_num_bytes = 0; + int numerator; + s64 pclk_dsc_fp; + s64 dwidth_dsc_fp; + s64 hbp_dsc_fp; + + int tot_num_eoc_symbols = 0; + int tot_num_hor_bytes = 0; + int tot_num_dummy_bytes = 0; + int dwidth_dsc_bytes = 0; + int eoc_bytes = 0; + + s64 temp1_fp, temp2_fp, temp3_fp; + + tu->lclk_fp = drm_fixp_from_fraction(in->lclk, 1); + tu->pclk_fp = drm_fixp_from_fraction(in->pclk_khz, 1000); + tu->lwidth = in->hactive; + tu->hbp_relative_to_pclk = in->hporch; + tu->nlanes = in->nlanes; + tu->bpp = in->bpp; + tu->pixelEnc = in->pixel_enc; + tu->dsc_en = in->dsc_en; + tu->async_en = in->async_en; + tu->lwidth_fp = drm_fixp_from_fraction(in->hactive, 1); + tu->hbp_relative_to_pclk_fp = drm_fixp_from_fraction(in->hporch, 1); + + if (tu->pixelEnc == 420) { + temp1_fp = drm_fixp_from_fraction(2, 1); + tu->pclk_fp = drm_fixp_div(tu->pclk_fp, temp1_fp); + tu->lwidth_fp = drm_fixp_div(tu->lwidth_fp, temp1_fp); + tu->hbp_relative_to_pclk_fp = + drm_fixp_div(tu->hbp_relative_to_pclk_fp, 2); + } + + if (tu->pixelEnc == 422) { + switch (tu->bpp) { + case 24: + tu->bpp = 16; + tu->bpc = 8; + break; + case 30: + tu->bpp = 20; + tu->bpc = 10; + break; + default: + tu->bpp = 16; + tu->bpc = 8; + break; + } + } else { + tu->bpc = tu->bpp/3; + } + + if (!in->dsc_en) + goto fec_check; + + temp1_fp = drm_fixp_from_fraction(in->compress_ratio, 100); + temp2_fp = drm_fixp_from_fraction(in->bpp, 1); + temp3_fp = drm_fixp_div(temp2_fp, temp1_fp); + temp2_fp = drm_fixp_mul(tu->lwidth_fp, temp3_fp); + + temp1_fp = drm_fixp_from_fraction(8, 1); + temp3_fp = drm_fixp_div(temp2_fp, temp1_fp); + + numerator = drm_fixp2int(temp3_fp); + + dsc_num_bytes = numerator / dsc_num_slices; + eoc_bytes = dsc_num_bytes % nlanes; + tot_num_eoc_symbols = nlanes * dsc_num_slices; + tot_num_hor_bytes = dsc_num_bytes * dsc_num_slices; + tot_num_dummy_bytes = (nlanes - eoc_bytes) * dsc_num_slices; + + if (dsc_num_bytes == 0) + pr_info("incorrect no of bytes per slice=%d\n", dsc_num_bytes); + + dwidth_dsc_bytes = (tot_num_hor_bytes + + tot_num_eoc_symbols + + (eoc_bytes == 0 ? 0 : tot_num_dummy_bytes)); + + dwidth_dsc_fp = drm_fixp_from_fraction(dwidth_dsc_bytes, 3); + + temp2_fp = drm_fixp_mul(tu->pclk_fp, dwidth_dsc_fp); + temp1_fp = drm_fixp_div(temp2_fp, tu->lwidth_fp); + pclk_dsc_fp = temp1_fp; + + temp1_fp = drm_fixp_div(pclk_dsc_fp, tu->pclk_fp); + temp2_fp = drm_fixp_mul(tu->hbp_relative_to_pclk_fp, temp1_fp); + hbp_dsc_fp = temp2_fp; + + /* output */ + tu->pclk_fp = pclk_dsc_fp; + tu->lwidth_fp = dwidth_dsc_fp; + tu->hbp_relative_to_pclk_fp = hbp_dsc_fp; + +fec_check: + if (in->fec_en) { + temp1_fp = drm_fixp_from_fraction(976, 1000); /* 0.976 */ + tu->lclk_fp = drm_fixp_mul(tu->lclk_fp, temp1_fp); + } +} + +static void _tu_valid_boundary_calc(struct tu_algo_data *tu) +{ + s64 temp1_fp, temp2_fp, temp, temp1, temp2; + int compare_result_1, compare_result_2, compare_result_3; + + temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); + temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); + + tu->new_valid_boundary_link = drm_fixp2int_ceil(temp2_fp); + + temp = (tu->i_upper_boundary_count * + tu->new_valid_boundary_link + + tu->i_lower_boundary_count * + (tu->new_valid_boundary_link-1)); + tu->average_valid2_fp = drm_fixp_from_fraction(temp, + (tu->i_upper_boundary_count + + tu->i_lower_boundary_count)); + + temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); + temp2_fp = tu->lwidth_fp; + temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); + temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp); + tu->n_tus = drm_fixp2int(temp2_fp); + if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000) + tu->n_tus += 1; + + temp1_fp = drm_fixp_from_fraction(tu->n_tus, 1); + temp2_fp = drm_fixp_mul(temp1_fp, tu->average_valid2_fp); + temp1_fp = drm_fixp_from_fraction(tu->n_symbols, 1); + temp2_fp = temp1_fp - temp2_fp; + temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); + temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); + tu->n_remainder_symbols_per_lane_fp = temp2_fp; + + temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); + tu->last_partial_tu_fp = + drm_fixp_div(tu->n_remainder_symbols_per_lane_fp, + temp1_fp); + + if (tu->n_remainder_symbols_per_lane_fp != 0) + tu->remainder_symbols_exist = 1; + else + tu->remainder_symbols_exist = 0; + + temp1_fp = drm_fixp_from_fraction(tu->n_tus, tu->nlanes); + tu->n_tus_per_lane = drm_fixp2int(temp1_fp); + + tu->paired_tus = (int)((tu->n_tus_per_lane) / + (tu->i_upper_boundary_count + + tu->i_lower_boundary_count)); + + tu->remainder_tus = tu->n_tus_per_lane - tu->paired_tus * + (tu->i_upper_boundary_count + + tu->i_lower_boundary_count); + + if ((tu->remainder_tus - tu->i_upper_boundary_count) > 0) { + tu->remainder_tus_upper = tu->i_upper_boundary_count; + tu->remainder_tus_lower = tu->remainder_tus - + tu->i_upper_boundary_count; + } else { + tu->remainder_tus_upper = tu->remainder_tus; + tu->remainder_tus_lower = 0; + } + + temp = tu->paired_tus * (tu->i_upper_boundary_count * + tu->new_valid_boundary_link + + tu->i_lower_boundary_count * + (tu->new_valid_boundary_link - 1)) + + (tu->remainder_tus_upper * + tu->new_valid_boundary_link) + + (tu->remainder_tus_lower * + (tu->new_valid_boundary_link - 1)); + tu->total_valid_fp = drm_fixp_from_fraction(temp, 1); + + if (tu->remainder_symbols_exist) { + temp1_fp = tu->total_valid_fp + + tu->n_remainder_symbols_per_lane_fp; + temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1); + temp2_fp = temp2_fp + tu->last_partial_tu_fp; + temp1_fp = drm_fixp_div(temp1_fp, temp2_fp); + } else { + temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1); + temp1_fp = drm_fixp_div(tu->total_valid_fp, temp2_fp); + } + tu->effective_valid_fp = temp1_fp; + + temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); + temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); + tu->n_n_err_fp = tu->effective_valid_fp - temp2_fp; + + temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); + temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); + tu->n_err_fp = tu->average_valid2_fp - temp2_fp; + + tu->even_distribution = tu->n_tus % tu->nlanes == 0 ? 1 : 0; + + temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); + temp2_fp = tu->lwidth_fp; + temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); + temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp); + + if (temp2_fp) + tu->n_tus_incl_last_incomplete_tu = drm_fixp2int_ceil(temp2_fp); + else + tu->n_tus_incl_last_incomplete_tu = 0; + + temp1 = 0; + temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); + temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); + temp1_fp = tu->average_valid2_fp - temp2_fp; + temp2_fp = drm_fixp_from_fraction(tu->n_tus_incl_last_incomplete_tu, 1); + temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); + + if (temp1_fp) + temp1 = drm_fixp2int_ceil(temp1_fp); + + temp = tu->i_upper_boundary_count * tu->nlanes; + temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); + temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); + temp1_fp = drm_fixp_from_fraction(tu->new_valid_boundary_link, 1); + temp2_fp = temp1_fp - temp2_fp; + temp1_fp = drm_fixp_from_fraction(temp, 1); + temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); + + if (temp2_fp) + temp2 = drm_fixp2int_ceil(temp2_fp); + else + temp2 = 0; + tu->extra_required_bytes_new_tmp = (int)(temp1 + temp2); + + temp1_fp = drm_fixp_from_fraction(8, tu->bpp); + temp2_fp = drm_fixp_from_fraction( + tu->extra_required_bytes_new_tmp, 1); + temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); + + if (temp1_fp) + tu->extra_pclk_cycles_tmp = drm_fixp2int_ceil(temp1_fp); + else + tu->extra_pclk_cycles_tmp = 0; + + temp1_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles_tmp, 1); + temp2_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); + temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp); + + if (temp1_fp) + tu->extra_pclk_cycles_in_link_clk_tmp = + drm_fixp2int_ceil(temp1_fp); + else + tu->extra_pclk_cycles_in_link_clk_tmp = 0; + + tu->filler_size_tmp = tu->tu_size - tu->new_valid_boundary_link; + + tu->lower_filler_size_tmp = tu->filler_size_tmp + 1; + + tu->delay_start_link_tmp = tu->extra_pclk_cycles_in_link_clk_tmp + + tu->lower_filler_size_tmp + + tu->extra_buffer_margin; + + temp1_fp = drm_fixp_from_fraction(tu->delay_start_link_tmp, 1); + tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); + + compare_result_1 = _tu_param_compare(tu->n_n_err_fp, tu->diff_abs_fp); + if (compare_result_1 == 2) + compare_result_1 = 1; + else + compare_result_1 = 0; + + compare_result_2 = _tu_param_compare(tu->n_n_err_fp, tu->err_fp); + if (compare_result_2 == 2) + compare_result_2 = 1; + else + compare_result_2 = 0; + + compare_result_3 = _tu_param_compare(tu->hbp_time_fp, + tu->delay_start_time_fp); + if (compare_result_3 == 2) + compare_result_3 = 0; + else + compare_result_3 = 1; + + if (((tu->even_distribution == 1) || + ((tu->even_distribution_BF == 0) && + (tu->even_distribution_legacy == 0))) && + tu->n_err_fp >= 0 && tu->n_n_err_fp >= 0 && + compare_result_2 && + (compare_result_1 || (tu->min_hblank_violated == 1)) && + (tu->new_valid_boundary_link - 1) > 0 && + compare_result_3 && + (tu->delay_start_link_tmp <= 1023)) { + tu->upper_boundary_count = tu->i_upper_boundary_count; + tu->lower_boundary_count = tu->i_lower_boundary_count; + tu->err_fp = tu->n_n_err_fp; + tu->boundary_moderation_en = true; + tu->tu_size_desired = tu->tu_size; + tu->valid_boundary_link = tu->new_valid_boundary_link; + tu->effective_valid_recorded_fp = tu->effective_valid_fp; + tu->even_distribution_BF = 1; + tu->delay_start_link = tu->delay_start_link_tmp; + } else if (tu->boundary_mod_lower_err == 0) { + compare_result_1 = _tu_param_compare(tu->n_n_err_fp, + tu->diff_abs_fp); + if (compare_result_1 == 2) + tu->boundary_mod_lower_err = 1; + } +} + +static void _dp_ctrl_calc_tu(struct dp_tu_calc_input *in, + struct dp_vc_tu_mapping_table *tu_table) +{ + struct tu_algo_data tu; + int compare_result_1, compare_result_2; + u64 temp = 0; + s64 temp_fp = 0, temp1_fp = 0, temp2_fp = 0; + + s64 LCLK_FAST_SKEW_fp = drm_fixp_from_fraction(6, 10000); /* 0.0006 */ + s64 const_p49_fp = drm_fixp_from_fraction(49, 100); /* 0.49 */ + s64 const_p56_fp = drm_fixp_from_fraction(56, 100); /* 0.56 */ + s64 RATIO_SCALE_fp = drm_fixp_from_fraction(1001, 1000); + + u8 DP_BRUTE_FORCE = 1; + s64 BRUTE_FORCE_THRESHOLD_fp = drm_fixp_from_fraction(1, 10); /* 0.1 */ + uint EXTRA_PIXCLK_CYCLE_DELAY = 4; + uint HBLANK_MARGIN = 4; + + memset(&tu, 0, sizeof(tu)); + + dp_panel_update_tu_timings(in, &tu); + + tu.err_fp = drm_fixp_from_fraction(1000, 1); /* 1000 */ + + temp1_fp = drm_fixp_from_fraction(4, 1); + temp2_fp = drm_fixp_mul(temp1_fp, tu.lclk_fp); + temp_fp = drm_fixp_div(temp2_fp, tu.pclk_fp); + tu.extra_buffer_margin = drm_fixp2int_ceil(temp_fp); + + temp1_fp = drm_fixp_from_fraction(tu.bpp, 8); + temp2_fp = drm_fixp_mul(tu.pclk_fp, temp1_fp); + temp1_fp = drm_fixp_from_fraction(tu.nlanes, 1); + temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); + tu.ratio_fp = drm_fixp_div(temp2_fp, tu.lclk_fp); + + tu.original_ratio_fp = tu.ratio_fp; + tu.boundary_moderation_en = false; + tu.upper_boundary_count = 0; + tu.lower_boundary_count = 0; + tu.i_upper_boundary_count = 0; + tu.i_lower_boundary_count = 0; + tu.valid_lower_boundary_link = 0; + tu.even_distribution_BF = 0; + tu.even_distribution_legacy = 0; + tu.even_distribution = 0; + tu.delay_start_time_fp = 0; + + tu.err_fp = drm_fixp_from_fraction(1000, 1); + tu.n_err_fp = 0; + tu.n_n_err_fp = 0; + + tu.ratio = drm_fixp2int(tu.ratio_fp); + temp1_fp = drm_fixp_from_fraction(tu.nlanes, 1); + div64_u64_rem(tu.lwidth_fp, temp1_fp, &temp2_fp); + if (temp2_fp != 0 && + !tu.ratio && tu.dsc_en == 0) { + tu.ratio_fp = drm_fixp_mul(tu.ratio_fp, RATIO_SCALE_fp); + tu.ratio = drm_fixp2int(tu.ratio_fp); + if (tu.ratio) + tu.ratio_fp = drm_fixp_from_fraction(1, 1); + } + + if (tu.ratio > 1) + tu.ratio = 1; + + if (tu.ratio == 1) + goto tu_size_calc; + + compare_result_1 = _tu_param_compare(tu.ratio_fp, const_p49_fp); + if (!compare_result_1 || compare_result_1 == 1) + compare_result_1 = 1; + else + compare_result_1 = 0; + + compare_result_2 = _tu_param_compare(tu.ratio_fp, const_p56_fp); + if (!compare_result_2 || compare_result_2 == 2) + compare_result_2 = 1; + else + compare_result_2 = 0; + + if (tu.dsc_en && compare_result_1 && compare_result_2) { + HBLANK_MARGIN += 4; + DRM_DEBUG_DP("Info: increase HBLANK_MARGIN to %d\n", + HBLANK_MARGIN); + } + +tu_size_calc: + for (tu.tu_size = 32; tu.tu_size <= 64; tu.tu_size++) { + temp1_fp = drm_fixp_from_fraction(tu.tu_size, 1); + temp2_fp = drm_fixp_mul(tu.ratio_fp, temp1_fp); + temp = drm_fixp2int_ceil(temp2_fp); + temp1_fp = drm_fixp_from_fraction(temp, 1); + tu.n_err_fp = temp1_fp - temp2_fp; + + if (tu.n_err_fp < tu.err_fp) { + tu.err_fp = tu.n_err_fp; + tu.tu_size_desired = tu.tu_size; + } + } + + tu.tu_size_minus1 = tu.tu_size_desired - 1; + + temp1_fp = drm_fixp_from_fraction(tu.tu_size_desired, 1); + temp2_fp = drm_fixp_mul(tu.ratio_fp, temp1_fp); + tu.valid_boundary_link = drm_fixp2int_ceil(temp2_fp); + + temp1_fp = drm_fixp_from_fraction(tu.bpp, 8); + temp2_fp = tu.lwidth_fp; + temp2_fp = drm_fixp_mul(temp2_fp, temp1_fp); + + temp1_fp = drm_fixp_from_fraction(tu.valid_boundary_link, 1); + temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); + tu.n_tus = drm_fixp2int(temp2_fp); + if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000) + tu.n_tus += 1; + + tu.even_distribution_legacy = tu.n_tus % tu.nlanes == 0 ? 1 : 0; + DRM_DEBUG_DP("Info: n_sym = %d, num_of_tus = %d\n", + tu.valid_boundary_link, tu.n_tus); + + temp1_fp = drm_fixp_from_fraction(tu.tu_size_desired, 1); + temp2_fp = drm_fixp_mul(tu.original_ratio_fp, temp1_fp); + temp1_fp = drm_fixp_from_fraction(tu.valid_boundary_link, 1); + temp2_fp = temp1_fp - temp2_fp; + temp1_fp = drm_fixp_from_fraction(tu.n_tus + 1, 1); + temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); + + temp = drm_fixp2int(temp2_fp); + if (temp && temp2_fp) + tu.extra_bytes = drm_fixp2int_ceil(temp2_fp); + else + tu.extra_bytes = 0; + + temp1_fp = drm_fixp_from_fraction(tu.extra_bytes, 1); + temp2_fp = drm_fixp_from_fraction(8, tu.bpp); + temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp); + + if (temp && temp1_fp) + tu.extra_pclk_cycles = drm_fixp2int_ceil(temp1_fp); + else + tu.extra_pclk_cycles = drm_fixp2int(temp1_fp); + + temp1_fp = drm_fixp_div(tu.lclk_fp, tu.pclk_fp); + temp2_fp = drm_fixp_from_fraction(tu.extra_pclk_cycles, 1); + temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); + + if (temp1_fp) + tu.extra_pclk_cycles_in_link_clk = drm_fixp2int_ceil(temp1_fp); + else + tu.extra_pclk_cycles_in_link_clk = drm_fixp2int(temp1_fp); + + tu.filler_size = tu.tu_size_desired - tu.valid_boundary_link; + + temp1_fp = drm_fixp_from_fraction(tu.tu_size_desired, 1); + tu.ratio_by_tu_fp = drm_fixp_mul(tu.ratio_fp, temp1_fp); + + tu.delay_start_link = tu.extra_pclk_cycles_in_link_clk + + tu.filler_size + tu.extra_buffer_margin; + + tu.resulting_valid_fp = + drm_fixp_from_fraction(tu.valid_boundary_link, 1); + + temp1_fp = drm_fixp_from_fraction(tu.tu_size_desired, 1); + temp2_fp = drm_fixp_div(tu.resulting_valid_fp, temp1_fp); + tu.TU_ratio_err_fp = temp2_fp - tu.original_ratio_fp; + + temp1_fp = drm_fixp_from_fraction(HBLANK_MARGIN, 1); + temp1_fp = tu.hbp_relative_to_pclk_fp - temp1_fp; + tu.hbp_time_fp = drm_fixp_div(temp1_fp, tu.pclk_fp); + + temp1_fp = drm_fixp_from_fraction(tu.delay_start_link, 1); + tu.delay_start_time_fp = drm_fixp_div(temp1_fp, tu.lclk_fp); + + compare_result_1 = _tu_param_compare(tu.hbp_time_fp, + tu.delay_start_time_fp); + if (compare_result_1 == 2) /* if (hbp_time_fp < delay_start_time_fp) */ + tu.min_hblank_violated = 1; + + tu.hactive_time_fp = drm_fixp_div(tu.lwidth_fp, tu.pclk_fp); + + compare_result_2 = _tu_param_compare(tu.hactive_time_fp, + tu.delay_start_time_fp); + if (compare_result_2 == 2) + tu.min_hblank_violated = 1; + + tu.delay_start_time_fp = 0; + + /* brute force */ + + tu.delay_start_link_extra_pixclk = EXTRA_PIXCLK_CYCLE_DELAY; + tu.diff_abs_fp = tu.resulting_valid_fp - tu.ratio_by_tu_fp; + + temp = drm_fixp2int(tu.diff_abs_fp); + if (!temp && tu.diff_abs_fp <= 0xffff) + tu.diff_abs_fp = 0; + + /* if(diff_abs < 0) diff_abs *= -1 */ + if (tu.diff_abs_fp < 0) + tu.diff_abs_fp = drm_fixp_mul(tu.diff_abs_fp, -1); + + tu.boundary_mod_lower_err = 0; + if ((tu.diff_abs_fp != 0 && + ((tu.diff_abs_fp > BRUTE_FORCE_THRESHOLD_fp) || + (tu.even_distribution_legacy == 0) || + (DP_BRUTE_FORCE == 1))) || + (tu.min_hblank_violated == 1)) { + do { + tu.err_fp = drm_fixp_from_fraction(1000, 1); + + temp1_fp = drm_fixp_div(tu.lclk_fp, tu.pclk_fp); + temp2_fp = drm_fixp_from_fraction( + tu.delay_start_link_extra_pixclk, 1); + temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); + + if (temp1_fp) + tu.extra_buffer_margin = + drm_fixp2int_ceil(temp1_fp); + else + tu.extra_buffer_margin = 0; + + temp1_fp = drm_fixp_from_fraction(tu.bpp, 8); + temp1_fp = drm_fixp_mul(tu.lwidth_fp, temp1_fp); + + if (temp1_fp) + tu.n_symbols = drm_fixp2int_ceil(temp1_fp); + else + tu.n_symbols = 0; + + for (tu.tu_size = 32; tu.tu_size <= 64; tu.tu_size++) { + for (tu.i_upper_boundary_count = 1; + tu.i_upper_boundary_count <= 15; + tu.i_upper_boundary_count++) { + for (tu.i_lower_boundary_count = 1; + tu.i_lower_boundary_count <= 15; + tu.i_lower_boundary_count++) { + _tu_valid_boundary_calc(&tu); + } + } + } + tu.delay_start_link_extra_pixclk--; + } while (tu.boundary_moderation_en != true && + tu.boundary_mod_lower_err == 1 && + tu.delay_start_link_extra_pixclk != 0); + + if (tu.boundary_moderation_en == true) { + temp1_fp = drm_fixp_from_fraction( + (tu.upper_boundary_count * + tu.valid_boundary_link + + tu.lower_boundary_count * + (tu.valid_boundary_link - 1)), 1); + temp2_fp = drm_fixp_from_fraction( + (tu.upper_boundary_count + + tu.lower_boundary_count), 1); + tu.resulting_valid_fp = + drm_fixp_div(temp1_fp, temp2_fp); + + temp1_fp = drm_fixp_from_fraction( + tu.tu_size_desired, 1); + tu.ratio_by_tu_fp = + drm_fixp_mul(tu.original_ratio_fp, temp1_fp); + + tu.valid_lower_boundary_link = + tu.valid_boundary_link - 1; + + temp1_fp = drm_fixp_from_fraction(tu.bpp, 8); + temp1_fp = drm_fixp_mul(tu.lwidth_fp, temp1_fp); + temp2_fp = drm_fixp_div(temp1_fp, + tu.resulting_valid_fp); + tu.n_tus = drm_fixp2int(temp2_fp); + + tu.tu_size_minus1 = tu.tu_size_desired - 1; + tu.even_distribution_BF = 1; + + temp1_fp = + drm_fixp_from_fraction(tu.tu_size_desired, 1); + temp2_fp = + drm_fixp_div(tu.resulting_valid_fp, temp1_fp); + tu.TU_ratio_err_fp = temp2_fp - tu.original_ratio_fp; + } + } + + temp2_fp = drm_fixp_mul(LCLK_FAST_SKEW_fp, tu.lwidth_fp); + + if (temp2_fp) + temp = drm_fixp2int_ceil(temp2_fp); + else + temp = 0; + + temp1_fp = drm_fixp_from_fraction(tu.nlanes, 1); + temp2_fp = drm_fixp_mul(tu.original_ratio_fp, temp1_fp); + temp1_fp = drm_fixp_from_fraction(tu.bpp, 8); + temp2_fp = drm_fixp_div(temp1_fp, temp2_fp); + temp1_fp = drm_fixp_from_fraction(temp, 1); + temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); + temp = drm_fixp2int(temp2_fp); + + if (tu.async_en) + tu.delay_start_link += (int)temp; + + temp1_fp = drm_fixp_from_fraction(tu.delay_start_link, 1); + tu.delay_start_time_fp = drm_fixp_div(temp1_fp, tu.lclk_fp); + + /* OUTPUTS */ + tu_table->valid_boundary_link = tu.valid_boundary_link; + tu_table->delay_start_link = tu.delay_start_link; + tu_table->boundary_moderation_en = tu.boundary_moderation_en; + tu_table->valid_lower_boundary_link = tu.valid_lower_boundary_link; + tu_table->upper_boundary_count = tu.upper_boundary_count; + tu_table->lower_boundary_count = tu.lower_boundary_count; + tu_table->tu_size_minus1 = tu.tu_size_minus1; + + DRM_DEBUG_DP("TU: valid_boundary_link: %d\n", + tu_table->valid_boundary_link); + DRM_DEBUG_DP("TU: delay_start_link: %d\n", + tu_table->delay_start_link); + DRM_DEBUG_DP("TU: boundary_moderation_en: %d\n", + tu_table->boundary_moderation_en); + DRM_DEBUG_DP("TU: valid_lower_boundary_link: %d\n", + tu_table->valid_lower_boundary_link); + DRM_DEBUG_DP("TU: upper_boundary_count: %d\n", + tu_table->upper_boundary_count); + DRM_DEBUG_DP("TU: lower_boundary_count: %d\n", + tu_table->lower_boundary_count); + DRM_DEBUG_DP("TU: tu_size_minus1: %d\n", tu_table->tu_size_minus1); +} + +static void dp_ctrl_calc_tu_parameters(struct dp_ctrl_private *ctrl, + struct dp_vc_tu_mapping_table *tu_table) +{ + struct dp_tu_calc_input in; + struct drm_display_mode *drm_mode; + + drm_mode = &ctrl->panel->dp_mode.drm_mode; + + in.lclk = ctrl->link->link_params.rate / 1000; + in.pclk_khz = drm_mode->clock; + in.hactive = drm_mode->hdisplay; + in.hporch = drm_mode->htotal - drm_mode->hdisplay; + in.nlanes = ctrl->link->link_params.num_lanes; + in.bpp = ctrl->panel->dp_mode.bpp; + in.pixel_enc = 444; + in.dsc_en = 0; + in.async_en = 0; + in.fec_en = 0; + in.num_of_dsc_slices = 0; + in.compress_ratio = 100; + + _dp_ctrl_calc_tu(&in, tu_table); +} + +static void dp_ctrl_setup_tr_unit(struct dp_ctrl_private *ctrl) +{ + u32 dp_tu = 0x0; + u32 valid_boundary = 0x0; + u32 valid_boundary2 = 0x0; + struct dp_vc_tu_mapping_table tu_calc_table; + + dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table); + + dp_tu |= tu_calc_table.tu_size_minus1; + valid_boundary |= tu_calc_table.valid_boundary_link; + valid_boundary |= (tu_calc_table.delay_start_link << 16); + + valid_boundary2 |= (tu_calc_table.valid_lower_boundary_link << 1); + valid_boundary2 |= (tu_calc_table.upper_boundary_count << 16); + valid_boundary2 |= (tu_calc_table.lower_boundary_count << 20); + + if (tu_calc_table.boundary_moderation_en) + valid_boundary2 |= BIT(0); + + pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n", + dp_tu, valid_boundary, valid_boundary2); + + dp_catalog_ctrl_update_transfer_unit(ctrl->catalog, + dp_tu, valid_boundary, valid_boundary2); +} + +static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl) +{ + int ret = 0; + + if (!wait_for_completion_timeout(&ctrl->video_comp, + WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES)) { + DRM_ERROR("Link Train timedout\n"); + ret = -ETIMEDOUT; + } + return ret; +} + +static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl) +{ + struct dp_link *link = ctrl->link; + int ret = 0, lane, lane_cnt; + u8 buf[4]; + u32 max_level_reached = 0; + u32 voltage_swing_level = link->phy_params.v_level; + u32 pre_emphasis_level = link->phy_params.p_level; + + ret = dp_catalog_ctrl_update_vx_px(ctrl->catalog, + voltage_swing_level, pre_emphasis_level); + + if (ret) + return ret; + + if (voltage_swing_level > DP_TRAIN_VOLTAGE_SWING_MAX) { + DRM_DEBUG_DP("max. voltage swing level reached %d\n", + voltage_swing_level); + max_level_reached |= DP_TRAIN_MAX_SWING_REACHED; + } + + if (pre_emphasis_level == DP_TRAIN_PRE_EMPHASIS_MAX) { + DRM_DEBUG_DP("max. pre-emphasis level reached %d\n", + pre_emphasis_level); + max_level_reached |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; + } + + pre_emphasis_level <<= DP_TRAIN_PRE_EMPHASIS_SHIFT; + + lane_cnt = ctrl->link->link_params.num_lanes; + for (lane = 0; lane < lane_cnt; lane++) + buf[lane] = voltage_swing_level | pre_emphasis_level + | max_level_reached; + + DRM_DEBUG_DP("sink: p|v=0x%x\n", voltage_swing_level + | pre_emphasis_level); + ret = drm_dp_dpcd_write(ctrl->aux, DP_TRAINING_LANE0_SET, + buf, lane_cnt); + if (ret == lane_cnt) + ret = 0; + + return ret; +} + +static bool dp_ctrl_train_pattern_set(struct dp_ctrl_private *ctrl, + u8 pattern) +{ + u8 buf; + int ret = 0; + + DRM_DEBUG_DP("sink: pattern=%x\n", pattern); + + buf = pattern; + ret = drm_dp_dpcd_writeb(ctrl->aux, + DP_TRAINING_PATTERN_SET, buf); + return ret == 1; +} + +static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl, + u8 *link_status) +{ + int len = 0; + u32 const offset = DP_LANE_ALIGN_STATUS_UPDATED - DP_LANE0_1_STATUS; + u32 link_status_read_max_retries = 100; + + while (--link_status_read_max_retries) { + len = drm_dp_dpcd_read_link_status(ctrl->aux, + link_status); + if (len != DP_LINK_STATUS_SIZE) { + DRM_ERROR("DP link status read failed, err: %d\n", len); + return len; + } + + if (!(link_status[offset] & DP_LINK_STATUS_UPDATED)) + return 0; + } + + return -ETIMEDOUT; +} + +static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl) +{ + int tries, old_v_level, ret = 0; + u8 link_status[DP_LINK_STATUS_SIZE]; + int const maximum_retries = 5; + + dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); + + ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, DP_TRAINING_PATTERN_1); + if (ret) + return ret; + dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 | + DP_LINK_SCRAMBLING_DISABLE); + ret = dp_ctrl_update_vx_px(ctrl); + if (ret) + return ret; + + tries = 0; + old_v_level = ctrl->link->phy_params.v_level; + for (tries = 0; tries < maximum_retries; tries++) { + drm_dp_link_train_clock_recovery_delay(ctrl->panel->dpcd); + + ret = dp_ctrl_read_link_status(ctrl, link_status); + if (ret) + return ret; + + if (drm_dp_clock_recovery_ok(link_status, + ctrl->link->link_params.num_lanes)) { + return ret; + } + + if (ctrl->link->phy_params.v_level > + DP_TRAIN_VOLTAGE_SWING_MAX) { + DRM_ERROR_RATELIMITED("max v_level reached\n"); + return -EAGAIN; + } + + if (old_v_level != ctrl->link->phy_params.v_level) { + tries = 0; + old_v_level = ctrl->link->phy_params.v_level; + } + + DRM_DEBUG_DP("clock recovery not done, adjusting vx px\n"); + + dp_link_adjust_levels(ctrl->link, link_status); + ret = dp_ctrl_update_vx_px(ctrl); + if (ret) + return ret; + } + + DRM_ERROR("max tries reached\n"); + return -ETIMEDOUT; +} + +static void dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl) +{ + switch (ctrl->link->link_params.rate) { + case 810000: + ctrl->link->link_params.rate = 540000; + break; + case 540000: + ctrl->link->link_params.rate = 270000; + break; + case 270000: + case 162000: + default: + ctrl->link->link_params.rate = 162000; + break; + }; + + DRM_DEBUG_DP("new rate=0x%x\n", ctrl->link->link_params.rate); +} + +static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl) +{ + dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE); + drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd); +} + +static int dp_ctrl_link_training_2(struct dp_ctrl_private *ctrl) +{ + int tries = 0, ret = 0; + char pattern; + int const maximum_retries = 5; + u8 link_status[DP_LINK_STATUS_SIZE]; + + dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); + + if (drm_dp_tps3_supported(ctrl->panel->dpcd)) + pattern = DP_TRAINING_PATTERN_3; + else + pattern = DP_TRAINING_PATTERN_2; + + ret = dp_ctrl_update_vx_px(ctrl); + if (ret) + return ret; + + ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, pattern); + if (ret) + return ret; + + dp_ctrl_train_pattern_set(ctrl, pattern | DP_RECOVERED_CLOCK_OUT_EN); + + for (tries = 0; tries <= maximum_retries; tries++) { + drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd); + + ret = dp_ctrl_read_link_status(ctrl, link_status); + if (ret) + return ret; + + if (drm_dp_channel_eq_ok(link_status, + ctrl->link->link_params.num_lanes)) + return ret; + + dp_link_adjust_levels(ctrl->link, link_status); + ret = dp_ctrl_update_vx_px(ctrl); + if (ret) + return ret; + + } + + return -ETIMEDOUT; +} + +static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl) +{ + int ret = 0; + u8 encoding = DP_SET_ANSI_8B10B; + struct dp_link_info link_info = {0}; + + ctrl->link->phy_params.p_level = 0; + ctrl->link->phy_params.v_level = 0; + + dp_ctrl_config_ctrl(ctrl); + + link_info.num_lanes = ctrl->link->link_params.num_lanes; + link_info.rate = ctrl->link->link_params.rate; + link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING; + + dp_aux_link_configure(ctrl->aux, &link_info); + drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, + &encoding, 1); + + ret = dp_ctrl_link_train_1(ctrl); + if (ret) { + DRM_ERROR("link training #1 failed. ret=%d\n", ret); + goto end; + } + + /* print success info as this is a result of user initiated action */ + DRM_DEBUG_DP("link training #1 successful\n"); + + ret = dp_ctrl_link_training_2(ctrl); + if (ret) { + DRM_ERROR("link training #2 failed. ret=%d\n", ret); + goto end; + } + + /* print success info as this is a result of user initiated action */ + DRM_DEBUG_DP("link training #2 successful\n"); + +end: + dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); + + dp_ctrl_clear_training_pattern(ctrl); + return ret; +} + +static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl, bool train) +{ + bool mainlink_ready = false; + int ret = 0; + + dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); + + ret = dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, false); + if (ret) + return ret; + + if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) + return ret; + + if (train) { + /* + * As part of previous calls, DP controller state might have + * transitioned to PUSH_IDLE. In order to start transmitting + * a link training pattern, we have to first do soft reset. + */ + dp_catalog_ctrl_reset(ctrl->catalog); + + ret = dp_ctrl_link_train(ctrl); + if (ret) + return ret; + } + + /* + * Set up transfer unit values and set controller state to send + * video. + */ + dp_ctrl_setup_tr_unit(ctrl); + dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); + + ret = dp_ctrl_wait4video_ready(ctrl); + if (ret) + return ret; + + mainlink_ready = dp_catalog_ctrl_mainlink_ready(ctrl->catalog); + DRM_DEBUG_DP("mainlink %s\n", mainlink_ready ? "READY" : "NOT READY"); + return ret; +} + +static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl, + char *name, u32 rate) +{ + u32 num = ctrl->parser->mp[DP_CTRL_PM].num_clk; + struct dss_clk *cfg = ctrl->parser->mp[DP_CTRL_PM].clk_config; + + while (num && strcmp(cfg->clk_name, name)) { + num--; + cfg++; + } + + DRM_DEBUG_DP("setting rate=%d on clk=%s\n", rate, name); + + if (num) + cfg->rate = rate; + else + DRM_ERROR("%s clock doesn't exit to set rate %d\n", + name, rate); +} + +static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) +{ + int ret = 0; + + dp_power_set_link_clk_parent(ctrl->power); + + dp_ctrl_set_clock_rate(ctrl, "ctrl_link", + ctrl->link->link_params.rate); + + dp_ctrl_set_clock_rate(ctrl, "stream_pixel", + ctrl->dp_ctrl.pixel_rate); + + ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true); + if (ret) + DRM_ERROR("Unable to start link clocks. ret=%d\n", ret); + + return ret; +} + +int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip) +{ + struct dp_ctrl_private *ctrl; + + if (!dp_ctrl) { + DRM_ERROR("Invalid input data\n"); + return -EINVAL; + } + + ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); + + ctrl->dp_ctrl.orientation = flip; + + dp_catalog_ctrl_usb_reset(ctrl->catalog, flip); + dp_catalog_ctrl_phy_reset(ctrl->catalog); + dp_catalog_ctrl_enable_irq(ctrl->catalog, true); + + return 0; +} + +/** + * dp_ctrl_host_deinit() - Uninitialize DP controller + * @dp_ctrl: Display Port Driver data + * + * Perform required steps to uninitialize DP controller + * and its resources. + */ +void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl) +{ + struct dp_ctrl_private *ctrl; + + if (!dp_ctrl) { + DRM_ERROR("Invalid input data\n"); + return; + } + + ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); + + dp_catalog_ctrl_enable_irq(ctrl->catalog, false); + + DRM_DEBUG_DP("Host deinitialized successfully\n"); +} + +static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl) +{ + u8 *dpcd = ctrl->panel->dpcd; + u32 edid_quirks = 0; + + edid_quirks = drm_dp_get_edid_quirks(ctrl->panel->edid); + /* + * For better interop experience, used a fixed NVID=0x8000 + * whenever connected to a VGA dongle downstream. + */ + if (drm_dp_is_branch(dpcd)) + return (drm_dp_has_quirk(&ctrl->panel->desc, edid_quirks, + DP_DPCD_QUIRK_CONSTANT_N)); + + return false; +} + +static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl) +{ + int ret = 0; + + dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); + dp_catalog_ctrl_phy_lane_cfg(ctrl->catalog, + ctrl->dp_ctrl.orientation, ctrl->link->link_params.num_lanes); + /* + * Disable and re-enable the mainlink clock since the + * link clock might have been adjusted as part of the + * link maintenance. + */ + ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); + if (ret) { + DRM_ERROR("Failed to disable clocks. ret=%d\n", ret); + return ret; + } + /* hw recommended delay before re-enabling clocks */ + msleep(20); + + ret = dp_ctrl_enable_mainlink_clocks(ctrl); + if (ret) { + DRM_ERROR("Failed to enable mainlink clks. ret=%d\n", ret); + return ret; + } + + dp_ctrl_configure_source_params(ctrl); + dp_catalog_ctrl_config_msa(ctrl->catalog, + ctrl->link->link_params.rate, + ctrl->dp_ctrl.pixel_rate, dp_ctrl_use_fixed_nvid(ctrl)); + reinit_completion(&ctrl->idle_comp); + + return ret; +} + +static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl) +{ + int ret = 0; + int tries; + + dp_ctrl_push_idle(&ctrl->dp_ctrl); + dp_catalog_ctrl_reset(ctrl->catalog); + + ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; + + for (tries = 0; tries < 10; tries++) { + ret = dp_ctrl_reinitialize_mainlink(ctrl); + if (ret) { + DRM_ERROR("Failed to reinitialize mainlink. ret=%d\n", + ret); + break; + } + + ret = dp_ctrl_setup_main_link(ctrl, true); + if (ret == -EAGAIN) /* try with lower link rate */ + dp_ctrl_link_rate_down_shift(ctrl); + } + return ret; +} + +static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl) +{ + int ret = 0; + + if (!ctrl->link->phy_params.phy_test_pattern_sel) { + DRM_DEBUG_DP("no test pattern selected by sink\n"); + return ret; + } + + dp_ctrl_push_idle(&ctrl->dp_ctrl); + /* + * The global reset will need DP link related clocks to be + * running. Add the global reset just before disabling the + * link clocks and core clocks. + */ + dp_catalog_ctrl_reset(ctrl->catalog); + ret = dp_ctrl_off(&ctrl->dp_ctrl); + if (ret) { + DRM_ERROR("failed to disable DP controller\n"); + return ret; + } + + ret = dp_ctrl_on(&ctrl->dp_ctrl); + if (ret) + DRM_ERROR("failed to enable DP controller\n"); + + return ret; +} + +static bool dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl) +{ + bool success = false; + u32 pattern_sent = 0x0; + u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel; + + DRM_DEBUG_DP("request: 0x%x\n", pattern_requested); + + if (dp_catalog_ctrl_update_vx_px(ctrl->catalog, + ctrl->link->phy_params.v_level, + ctrl->link->phy_params.p_level)) { + DRM_ERROR("Failed to set v/p levels\n"); + return false; + } + dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested); + dp_link_send_test_response(ctrl->link); + + pattern_sent = dp_catalog_ctrl_read_phy_pattern(ctrl->catalog); + + switch (pattern_sent) { + case MR_LINK_TRAINING1: + success = pattern_requested == + DP_LINK_QUAL_PATTERN_D10_2; + break; + case MR_LINK_SYMBOL_ERM: + success = (pattern_requested == + DP_LINK_QUAL_PATTERN_ERROR_RATE) + || (pattern_requested == + DP_LINK_QUAL_PATTERN_HBR2_EYE); + break; + case MR_LINK_PRBS7: + success = pattern_requested == DP_LINK_QUAL_PATTERN_PRBS7; + break; + case MR_LINK_CUSTOM80: + success = pattern_requested == + DP_LINK_QUAL_PATTERN_80BIT_CUSTOM; + break; + default: + success = false; + } + + DRM_DEBUG_DP("%s: test->0x%x\n", success ? "success" : "failed", + pattern_requested); + return success; +} + +void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl) +{ + struct dp_ctrl_private *ctrl; + u32 sink_request = 0x0; + + if (!dp_ctrl) { + DRM_ERROR("invalid input\n"); + return; + } + + ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); + sink_request = ctrl->link->sink_request; + + if (sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { + DRM_DEBUG_DP("PHY_TEST_PATTERN request\n"); + if (dp_ctrl_process_phy_test_request(ctrl)) { + DRM_ERROR("process phy_test_req failed\n"); + return; + } + } + + if (sink_request & DP_LINK_STATUS_UPDATED) + if (dp_ctrl_link_maintenance(ctrl)) { + DRM_ERROR("LM failed: STATUS_UPDATED\n"); + return; + } + + + if (sink_request & DP_TEST_LINK_TRAINING) { + dp_link_send_test_response(ctrl->link); + if (dp_ctrl_link_maintenance(ctrl)) { + DRM_ERROR("LM failed: TEST_LINK_TRAINING\n"); + return; + } + } +} + +int dp_ctrl_on(struct dp_ctrl *dp_ctrl) +{ + int rc = 0; + struct dp_ctrl_private *ctrl; + u32 rate = 0; + u32 link_train_max_retries = 10; + u32 const phy_cts_pixel_clk_khz = 148500; + + if (!dp_ctrl) + return -EINVAL; + + ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); + + rate = ctrl->panel->link_info.rate; + + dp_power_clk_enable(ctrl->power, DP_CORE_PM, true); + dp_catalog_ctrl_hpd_config(ctrl->catalog, true); + + if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { + DRM_DEBUG_DP("using phy test link parameters\n"); + if (!ctrl->panel->dp_mode.drm_mode.clock) + ctrl->dp_ctrl.pixel_rate = phy_cts_pixel_clk_khz; + } else { + ctrl->link->link_params.rate = rate; + ctrl->link->link_params.num_lanes = + ctrl->panel->link_info.num_lanes; + ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; + } + + DRM_DEBUG_DP("rate=%d, num_lanes=%d, pixel_rate=%d\n", + ctrl->link->link_params.rate, + ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate); + + dp_catalog_ctrl_phy_lane_cfg(ctrl->catalog, + ctrl->dp_ctrl.orientation, + ctrl->link->link_params.num_lanes); + + rc = dp_ctrl_enable_mainlink_clocks(ctrl); + if (rc) + return rc; + + while (--link_train_max_retries && + !atomic_read(&ctrl->dp_ctrl.aborted)) { + rc = dp_ctrl_reinitialize_mainlink(ctrl); + if (rc) { + DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n", + rc); + break; + } + rc = dp_ctrl_setup_main_link(ctrl, true); + if (!rc) + break; + /* try with lower link rate */ + dp_ctrl_link_rate_down_shift(ctrl); + } + + if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) + dp_ctrl_send_phy_test_pattern(ctrl); + + return rc; +} + +int dp_ctrl_off(struct dp_ctrl *dp_ctrl) +{ + struct dp_ctrl_private *ctrl; + int ret = 0; + + if (!dp_ctrl) + return -EINVAL; + + ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); + + dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); + dp_catalog_ctrl_reset(ctrl->catalog); + ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); + if (ret) { + DRM_ERROR("Failed to disable clocks. ret=%d\n", ret); + return ret; + } + + DRM_DEBUG_DP("DP off done\n"); + return ret; +} + +void dp_ctrl_isr(struct dp_ctrl *dp_ctrl) +{ + struct dp_ctrl_private *ctrl; + u32 isr; + + if (!dp_ctrl) + return; + + ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); + + isr = dp_catalog_ctrl_get_interrupt(ctrl->catalog); + + if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) { + DRM_DEBUG_DP("dp_video_ready\n"); + complete(&ctrl->video_comp); + } + + if (isr & DP_CTRL_INTR_IDLE_PATTERN_SENT) { + DRM_DEBUG_DP("idle_patterns_sent\n"); + complete(&ctrl->idle_comp); + } +} + +struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link, + struct dp_panel *panel, struct drm_dp_aux *aux, + struct dp_power *power, struct dp_catalog *catalog, + struct dp_parser *parser) +{ + struct dp_ctrl_private *ctrl; + + if (!dev || !panel || !aux || + !link || !catalog) { + DRM_ERROR("invalid input\n"); + return ERR_PTR(-EINVAL); + } + + ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) { + DRM_ERROR("Mem allocation failure\n"); + return ERR_PTR(-ENOMEM); + } + + init_completion(&ctrl->idle_comp); + init_completion(&ctrl->video_comp); + mutex_init(&ctrl->push_idle_mutex); + + /* in parameters */ + ctrl->parser = parser; + ctrl->panel = panel; + ctrl->power = power; + ctrl->aux = aux; + ctrl->link = link; + ctrl->catalog = catalog; + ctrl->dev = dev; + + return &ctrl->dp_ctrl; +} + +void dp_ctrl_put(struct dp_ctrl *dp_ctrl) +{ +} -- cgit v1.2.3 From 220b856a3d3742a22831cb6cd94e48133a58d30e Mon Sep 17 00:00:00 2001 From: Tanmay Shah Date: Thu, 27 Aug 2020 14:16:58 -0700 Subject: drm/msm/dp: Add Display Port HPD feature Configure HPD registers in DP controller and enable HPD interrupt. Add interrupt to handle HPD connect and disconnect events. Changes in v8: None Signed-off-by: Tanmay Shah Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 18 ++++++ drivers/gpu/drm/msm/dp/dp_catalog.c | 67 ++++++++++++-------- drivers/gpu/drm/msm/dp/dp_catalog.h | 5 +- drivers/gpu/drm/msm/dp/dp_ctrl.c | 1 - drivers/gpu/drm/msm/dp/dp_display.c | 108 +++++++++++++++++++++++++++++--- drivers/gpu/drm/msm/dp/dp_reg.h | 12 ++++ drivers/gpu/drm/msm/msm_drv.h | 6 ++ 7 files changed, 182 insertions(+), 35 deletions(-) (limited to 'drivers/gpu/drm/msm/dp/dp_ctrl.c') diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 3469f6ef792e..bcb5ee50568c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -774,6 +774,23 @@ static void dpu_irq_preinstall(struct msm_kms *kms) dpu_core_irq_preinstall(dpu_kms); } +static int dpu_irq_postinstall(struct msm_kms *kms) +{ + struct msm_drm_private *priv; + struct dpu_kms *dpu_kms = to_dpu_kms(kms); + + if (!dpu_kms || !dpu_kms->dev) + return -EINVAL; + + priv = dpu_kms->dev->dev_private; + if (!priv) + return -EINVAL; + + msm_dp_irq_postinstall(priv->dp); + + return 0; +} + static void dpu_irq_uninstall(struct msm_kms *kms) { struct dpu_kms *dpu_kms = to_dpu_kms(kms); @@ -784,6 +801,7 @@ static void dpu_irq_uninstall(struct msm_kms *kms) static const struct msm_kms_funcs kms_funcs = { .hw_init = dpu_kms_hw_init, .irq_preinstall = dpu_irq_preinstall, + .irq_postinstall = dpu_irq_postinstall, .irq_uninstall = dpu_irq_uninstall, .irq = dpu_irq, .enable_commit = dpu_kms_enable_commit, diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index d27e17d7d18c..c16072630d40 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -17,7 +17,6 @@ #define POLLING_SLEEP_US 1000 #define POLLING_TIMEOUT_US 10000 -#define REFTIMER_DEFAULT_VALUE 0x20000 #define SCRAMBLER_RESET_COUNT_VALUE 0xFC #define DP_INTERRUPT_STATUS_ACK_SHIFT 1 @@ -746,35 +745,51 @@ void dp_catalog_ctrl_enable_irq(struct dp_catalog *dp_catalog, } } -void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog, bool en) +void dp_catalog_hpd_config_intr(struct dp_catalog *dp_catalog, + u32 intr_mask, bool en) { struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); - if (en) { - u32 reftimer = dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER); - - dp_write_aux(catalog, REG_DP_DP_HPD_INT_ACK, - DP_DP_HPD_PLUG_INT_ACK | - DP_DP_IRQ_HPD_INT_ACK | - DP_DP_HPD_REPLUG_INT_ACK | - DP_DP_HPD_UNPLUG_INT_ACK); - dp_write_aux(catalog, REG_DP_DP_HPD_INT_MASK, - DP_DP_HPD_PLUG_INT_MASK | - DP_DP_IRQ_HPD_INT_MASK | - DP_DP_HPD_REPLUG_INT_MASK | - DP_DP_HPD_UNPLUG_INT_MASK); - - /* Configure REFTIMER */ - reftimer |= REFTIMER_DEFAULT_VALUE; - dp_write_aux(catalog, REG_DP_DP_HPD_REFTIMER, reftimer); - /* Enable HPD */ - dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, - DP_DP_HPD_CTRL_HPD_EN); - } else { - /* Disable HPD */ - dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, 0x0); - } + u32 config = dp_read_aux(catalog, REG_DP_DP_HPD_INT_MASK); + + config = (en ? config | intr_mask : config & ~intr_mask); + + dp_write_aux(catalog, REG_DP_DP_HPD_INT_MASK, + config & DP_DP_HPD_INT_MASK); +} + +void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog) +{ + struct dp_catalog_private *catalog = container_of(dp_catalog, + struct dp_catalog_private, dp_catalog); + + u32 reftimer = dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER); + + /* enable HPD interrupts */ + dp_catalog_hpd_config_intr(dp_catalog, + DP_DP_HPD_PLUG_INT_MASK | DP_DP_IRQ_HPD_INT_MASK + | DP_DP_HPD_UNPLUG_INT_MASK, true); + + /* Configure REFTIMER and enable it */ + reftimer |= DP_DP_HPD_REFTIMER_ENABLE; + dp_write_aux(catalog, REG_DP_DP_HPD_REFTIMER, reftimer); + + /* Enable HPD */ + dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_EN); +} + +u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog) +{ + struct dp_catalog_private *catalog = container_of(dp_catalog, + struct dp_catalog_private, dp_catalog); + int isr = 0; + + isr = dp_read_aux(catalog, REG_DP_DP_HPD_INT_STATUS); + dp_write_aux(catalog, REG_DP_DP_HPD_INT_ACK, + (isr & DP_DP_HPD_INT_MASK)); + + return isr; } int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h index 012570be1635..35c90b248b5d 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -76,7 +76,10 @@ void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_usb_reset(struct dp_catalog *dp_catalog, bool flip); bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_enable_irq(struct dp_catalog *dp_catalog, bool enable); -void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog, bool enable); +void dp_catalog_hpd_config_intr(struct dp_catalog *dp_catalog, + u32 intr_mask, bool en); +void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog); +u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_phy_lane_cfg(struct dp_catalog *dp_catalog, bool flipped, u8 lane_cnt); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 9a06cbf40af1..ae07e43b541b 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -1563,7 +1563,6 @@ int dp_ctrl_on(struct dp_ctrl *dp_ctrl) rate = ctrl->panel->link_info.rate; dp_power_clk_enable(ctrl->power, DP_CORE_PM, true); - dp_catalog_ctrl_hpd_config(ctrl->catalog, true); if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { DRM_DEBUG_DP("using phy test link parameters\n"); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index c8851f4bbf72..925c89720a16 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -17,6 +17,7 @@ #include "dp_power.h" #include "dp_catalog.h" #include "dp_aux.h" +#include "dp_reg.h" #include "dp_link.h" #include "dp_panel.h" #include "dp_ctrl.h" @@ -36,6 +37,7 @@ struct dp_display_private { bool power_on; bool hpd_irq_on; bool audio_supported; + atomic_t hpd_isr_status; struct platform_device *pdev; struct dentry *root; @@ -54,6 +56,8 @@ struct dp_display_private { struct dp_usbpd_cb usbpd_cb; struct dp_display_mode dp_mode; struct msm_dp dp_display; + + struct delayed_work config_hpd_work; }; static const struct of_device_id dp_dt_match[] = { @@ -64,6 +68,20 @@ static const struct of_device_id dp_dt_match[] = { static irqreturn_t dp_display_irq(int irq, void *dev_id) { struct dp_display_private *dp = dev_id; + irqreturn_t ret = IRQ_HANDLED; + u32 hpd_isr_status; + + if (!dp) { + DRM_ERROR("invalid data\n"); + return IRQ_NONE; + } + + hpd_isr_status = dp_catalog_hpd_get_intr_status(dp->catalog); + + if (hpd_isr_status & DP_DP_HPD_INT_MASK) { + atomic_set(&dp->hpd_isr_status, hpd_isr_status); + ret = IRQ_WAKE_THREAD; + } /* DP controller isr */ dp_ctrl_isr(dp->ctrl); @@ -71,6 +89,54 @@ static irqreturn_t dp_display_irq(int irq, void *dev_id) /* DP aux isr */ dp_aux_isr(dp->aux); + return ret; +} + +static irqreturn_t dp_display_hpd_isr_work(int irq, void *data) +{ + struct dp_display_private *dp; + struct dp_usbpd *hpd; + u32 isr = 0; + + dp = (struct dp_display_private *)data; + if (!dp) + return IRQ_NONE; + + isr = atomic_read(&dp->hpd_isr_status); + + /* reset to default */ + atomic_set(&dp->hpd_isr_status, 0); + + hpd = dp->usbpd; + if (!hpd) + return IRQ_NONE; + + if (isr & DP_DP_HPD_PLUG_INT_MASK && + isr & DP_DP_HPD_STATE_STATUS_CONNECTED) { + hpd->hpd_high = 1; + dp->usbpd_cb.configure(&dp->pdev->dev); + } else if (isr & DP_DP_HPD_UNPLUG_INT_MASK && + (isr & DP_DP_HPD_STATE_STATUS_MASK) == + DP_DP_HPD_STATE_STATUS_DISCONNECTED) { + + /* disable HPD plug interrupt until disconnect is done + */ + dp_catalog_hpd_config_intr(dp->catalog, + DP_DP_HPD_PLUG_INT_MASK | DP_DP_IRQ_HPD_INT_MASK, + false); + + hpd->hpd_high = 0; + + /* We don't need separate work for disconnect as + * connect/attention interrupts are disabled + */ + dp->usbpd_cb.disconnect(&dp->pdev->dev); + + dp_catalog_hpd_config_intr(dp->catalog, + DP_DP_HPD_PLUG_INT_MASK | DP_DP_IRQ_HPD_INT_MASK, + true); + } + return IRQ_HANDLED; } @@ -212,8 +278,6 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp) int rc = 0; struct edid *edid; - dp_aux_init(dp->aux); - if (dp->link->psm_enabled) goto notify; @@ -270,10 +334,6 @@ static void dp_display_host_deinit(struct dp_display_private *dp) return; } - dp_ctrl_host_deinit(dp->ctrl); - dp_aux_deinit(dp->aux); - dp_power_deinit(dp->power); - disable_irq(dp->irq); dp->core_initialized = false; } @@ -630,7 +690,8 @@ int dp_display_request_irq(struct msm_dp *dp_display) return rc; } - rc = devm_request_irq(&dp->pdev->dev, dp->irq, dp_display_irq, + rc = devm_request_threaded_irq(&dp->pdev->dev, dp->irq, + dp_display_irq, dp_display_hpd_isr_work, IRQF_TRIGGER_HIGH, "dp_display_isr", dp); if (rc < 0) { DRM_ERROR("failed to request IRQ%u: %d\n", @@ -829,6 +890,39 @@ void __exit msm_dp_unregister(void) platform_driver_unregister(&dp_display_driver); } +static void dp_display_config_hpd_work(struct work_struct *work) +{ + struct dp_display_private *dp; + struct delayed_work *dw = to_delayed_work(work); + + dp = container_of(dw, struct dp_display_private, config_hpd_work); + + dp_display_host_init(dp); + dp_catalog_ctrl_hpd_config(dp->catalog); + + /* set default to 0 */ + atomic_set(&dp->hpd_isr_status, 0); + + /* Enable interrupt first time + * we are leaving dp clocks on during disconnect + * and never disable interrupt + */ + enable_irq(dp->irq); +} + +void msm_dp_irq_postinstall(struct msm_dp *dp_display) +{ + struct dp_display_private *dp; + + if (!dp_display) + return; + + dp = container_of(dp_display, struct dp_display_private, dp_display); + + INIT_DELAYED_WORK(&dp->config_hpd_work, dp_display_config_hpd_work); + queue_delayed_work(system_wq, &dp->config_hpd_work, HZ * 10); +} + int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, struct drm_encoder *encoder) { diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h index 893fc3250c3e..721c0cc69296 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -54,10 +54,22 @@ #define DP_DP_IRQ_HPD_INT_MASK (0x00000002) #define DP_DP_HPD_REPLUG_INT_MASK (0x00000004) #define DP_DP_HPD_UNPLUG_INT_MASK (0x00000008) +#define DP_DP_HPD_INT_MASK (DP_DP_HPD_PLUG_INT_MASK | \ + DP_DP_IRQ_HPD_INT_MASK | \ + DP_DP_HPD_REPLUG_INT_MASK | \ + DP_DP_HPD_UNPLUG_INT_MASK) +#define DP_DP_HPD_STATE_STATUS_CONNECTED (0x40000000) +#define DP_DP_HPD_STATE_STATUS_PENDING (0x20000000) +#define DP_DP_HPD_STATE_STATUS_DISCONNECTED (0x00000000) +#define DP_DP_HPD_STATE_STATUS_MASK (0xE0000000) #define REG_DP_DP_HPD_REFTIMER (0x00000018) +#define DP_DP_HPD_REFTIMER_ENABLE (1 << 16) + #define REG_DP_DP_HPD_EVENT_TIME_0 (0x0000001C) #define REG_DP_DP_HPD_EVENT_TIME_1 (0x00000020) +#define DP_DP_HPD_EVENT_TIME_0_VAL (0x3E800FA) +#define DP_DP_HPD_EVENT_TIME_1_VAL (0x1F407D0) #define REG_DP_AUX_CTRL (0x00000030) #define DP_AUX_CTRL_ENABLE (0x00000001) diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index ff165dafa6c6..f898a4121ce9 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -395,6 +395,7 @@ int msm_dp_display_disable(struct msm_dp *dp, struct drm_encoder *encoder); void msm_dp_display_mode_set(struct msm_dp *dp, struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode); +void msm_dp_irq_postinstall(struct msm_dp *dp_display); #else static inline int __init msm_dp_register(void) @@ -426,6 +427,11 @@ static inline void msm_dp_display_mode_set(struct msm_dp *dp, struct drm_display_mode *adjusted_mode) { } + +static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display) +{ +} + #endif void __init msm_mdp_register(void); -- cgit v1.2.3 From 8ede2ecc3e5ee327923f6e3cfe52761ce73607d1 Mon Sep 17 00:00:00 2001 From: Kuogee Hsieh Date: Fri, 11 Sep 2020 20:36:42 +0000 Subject: drm/msm/dp: Add DP compliance tests on Snapdragon Chipsets add event thread to execute events serially from event queue. Also timeout mode is supported which allow an event be deferred to be executed at later time. Both link and phy compliant tests had been done successfully. Changes in v2: -- Fix potential deadlock by removing redundant connect_mutex -- Check and enable link clock during modeset -- Drop unused code and fix function prototypes. -- set sink power to normal operation state (D0) before DPCD read Changes in v3: -- push idle pattern at main link before timing generator off -- add timeout handles for both connect and disconnect Changes in v4: -- add ST_SUSPEND_PENDING to handles suspend/modeset test operations -- clear dp phy aux interrupt status when ERR_DPPHY_AUX error -- send segment addr during edid read -- clear bpp depth before MISC register write Changes in v5: -- add ST_SUSPENDED to fix crash at resume Changes in v6: -- at msm_dp_display_enable() do not return until resume_done to avoid kms commit timeout Signed-off-by: Kuogee Hsieh Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 + drivers/gpu/drm/msm/dp/dp_aux.c | 1 + drivers/gpu/drm/msm/dp/dp_catalog.c | 77 ++- drivers/gpu/drm/msm/dp/dp_ctrl.c | 370 +++++++++---- drivers/gpu/drm/msm/dp/dp_ctrl.h | 3 +- drivers/gpu/drm/msm/dp/dp_display.c | 828 +++++++++++++++++++--------- drivers/gpu/drm/msm/dp/dp_display.h | 1 - drivers/gpu/drm/msm/dp/dp_drm.c | 4 - drivers/gpu/drm/msm/dp/dp_hpd.c | 2 +- drivers/gpu/drm/msm/dp/dp_hpd.h | 1 + drivers/gpu/drm/msm/dp/dp_link.c | 22 +- drivers/gpu/drm/msm/dp/dp_panel.c | 78 ++- drivers/gpu/drm/msm/dp/dp_panel.h | 9 +- drivers/gpu/drm/msm/dp/dp_parser.c | 42 +- drivers/gpu/drm/msm/dp/dp_parser.h | 2 + drivers/gpu/drm/msm/dp/dp_power.c | 46 +- drivers/gpu/drm/msm/dp/dp_power.h | 13 + drivers/gpu/drm/msm/dp/dp_reg.h | 1 + drivers/gpu/drm/msm/msm_drv.h | 1 + 19 files changed, 1050 insertions(+), 457 deletions(-) (limited to 'drivers/gpu/drm/msm/dp/dp_ctrl.c') diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 1d12e7cd11fe..702a29040958 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1225,6 +1225,11 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) /* wait for idle */ dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE); + if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && priv->dp) { + if (msm_dp_display_pre_disable(priv->dp, drm_enc)) + DPU_ERROR_ENC(dpu_enc, "dp display push idle failed\n"); + } + dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP); for (i = 0; i < dpu_enc->num_phys_encs; i++) { @@ -1234,6 +1239,7 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) phys->ops.disable(phys); } + /* after phys waits for frame-done, should be no more frames pending */ if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id); diff --git a/drivers/gpu/drm/msm/dp/dp_aux.c b/drivers/gpu/drm/msm/dp/dp_aux.c index 6bf3a5712968..d742b4d870b3 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.c +++ b/drivers/gpu/drm/msm/dp/dp_aux.c @@ -384,6 +384,7 @@ static ssize_t dp_aux_transfer(struct drm_dp_aux *dp_aux, PHY_AUX_CFG1); dp_catalog_aux_reset(aux->catalog); } + usleep_range(400, 500); /* at least 400us to next try */ goto unlock_exit; } diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index c16072630d40..67abb90953e4 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -536,16 +536,21 @@ void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, * To make sure link reg writes happens before other operation, * dp_write_link() function uses writel() */ - dp_write_link(catalog, REG_DP_MAINLINK_CTRL, - DP_MAINLINK_FB_BOUNDARY_SEL); - dp_write_link(catalog, REG_DP_MAINLINK_CTRL, - DP_MAINLINK_FB_BOUNDARY_SEL | - DP_MAINLINK_CTRL_RESET); - dp_write_link(catalog, REG_DP_MAINLINK_CTRL, + mainlink_ctrl = dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + + mainlink_ctrl &= ~(DP_MAINLINK_CTRL_RESET | + DP_MAINLINK_CTRL_ENABLE); + dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + + mainlink_ctrl |= DP_MAINLINK_CTRL_RESET; + dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + + mainlink_ctrl &= ~DP_MAINLINK_CTRL_RESET; + dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + + mainlink_ctrl |= (DP_MAINLINK_CTRL_ENABLE | DP_MAINLINK_FB_BOUNDARY_SEL); - dp_write_link(catalog, REG_DP_MAINLINK_CTRL, - DP_MAINLINK_FB_BOUNDARY_SEL | - DP_MAINLINK_CTRL_ENABLE); + dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } else { mainlink_ctrl = dp_read_link(catalog, REG_DP_MAINLINK_CTRL); mainlink_ctrl &= ~DP_MAINLINK_CTRL_ENABLE; @@ -644,7 +649,7 @@ int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog, bit = BIT(pattern - 1); DRM_DEBUG_DP("hw: bit=%d train=%d\n", bit, pattern); - dp_write_link(catalog, REG_DP_STATE_CTRL, bit); + dp_catalog_ctrl_state_ctrl(dp_catalog, bit); bit = BIT(pattern - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; @@ -769,7 +774,7 @@ void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog) /* enable HPD interrupts */ dp_catalog_hpd_config_intr(dp_catalog, DP_DP_HPD_PLUG_INT_MASK | DP_DP_IRQ_HPD_INT_MASK - | DP_DP_HPD_UNPLUG_INT_MASK, true); + | DP_DP_HPD_UNPLUG_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, true); /* Configure REFTIMER and enable it */ reftimer |= DP_DP_HPD_REFTIMER_ENABLE; @@ -881,15 +886,27 @@ void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog *dp_catalog, dp_write_link(catalog, REG_DP_STATE_CTRL, 0x0); switch (pattern) { - case DP_LINK_QUAL_PATTERN_D10_2: + case DP_PHY_TEST_PATTERN_D10_2: dp_write_link(catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_TRAINING_PATTERN1); - return; - case DP_LINK_QUAL_PATTERN_PRBS7: + break; + case DP_PHY_TEST_PATTERN_ERROR_COUNT: + value &= ~(1 << 16); + dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); + value |= SCRAMBLER_RESET_COUNT_VALUE; + dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); + dp_write_link(catalog, REG_DP_MAINLINK_LEVELS, + DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); + dp_write_link(catalog, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); + break; + case DP_PHY_TEST_PATTERN_PRBS7: dp_write_link(catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_PRBS7); - return; - case DP_LINK_QUAL_PATTERN_80BIT_CUSTOM: + break; + case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: dp_write_link(catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN); /* 00111110000011111000001111100000 */ @@ -901,14 +918,15 @@ void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog *dp_catalog, /* 1111100000111110 */ dp_write_link(catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, 0x0000F83E); - return; - case DP_LINK_QUAL_PATTERN_HBR2_EYE: - case DP_LINK_QUAL_PATTERN_ERROR_RATE: - value &= ~DP_HBR2_ERM_PATTERN; - if (pattern == DP_LINK_QUAL_PATTERN_HBR2_EYE) - value = DP_HBR2_ERM_PATTERN; + break; + case DP_PHY_TEST_PATTERN_CP2520: + value = dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + value &= ~DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER; + dp_write_link(catalog, REG_DP_MAINLINK_CTRL, value); + + value = DP_HBR2_ERM_PATTERN; dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); + value); value |= SCRAMBLER_RESET_COUNT_VALUE; dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value); @@ -916,10 +934,19 @@ void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog *dp_catalog, DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); dp_write_link(catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); - return; + value = dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + value |= DP_MAINLINK_CTRL_ENABLE; + dp_write_link(catalog, REG_DP_MAINLINK_CTRL, value); + break; + case DP_PHY_TEST_PATTERN_SEL_MASK: + dp_write_link(catalog, REG_DP_MAINLINK_CTRL, + DP_MAINLINK_CTRL_ENABLE); + dp_write_link(catalog, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_TRAINING_PATTERN4); + break; default: DRM_DEBUG_DP("No valid test pattern requested:0x%x\n", pattern); - return; + break; } } diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index ae07e43b541b..70b0e06953f6 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -26,6 +26,13 @@ #define MR_LINK_SYMBOL_ERM 0x80 #define MR_LINK_PRBS7 0x100 #define MR_LINK_CUSTOM80 0x200 +#define MR_LINK_TRAINING4 0x40 + +enum { + DP_TRAINING_NONE, + DP_TRAINING_1, + DP_TRAINING_2, +}; struct dp_tu_calc_input { u64 lclk; /* 162, 270, 540 and 810 */ @@ -58,7 +65,6 @@ struct dp_vc_tu_mapping_table { struct dp_ctrl_private { struct dp_ctrl dp_ctrl; - struct device *dev; struct drm_dp_aux *aux; struct dp_panel *panel; @@ -68,10 +74,16 @@ struct dp_ctrl_private { struct dp_catalog *catalog; struct completion idle_comp; - struct mutex push_idle_mutex; struct completion video_comp; }; +struct dp_cr_status { + u8 lane_0_1; + u8 lane_2_3; +}; + +#define DP_LANE0_1_CR_DONE 0x11 + static int dp_aux_link_configure(struct drm_dp_aux *aux, struct dp_link_info *link) { @@ -97,8 +109,6 @@ void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl) ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); - mutex_lock(&ctrl->push_idle_mutex); - reinit_completion(&ctrl->idle_comp); dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE); @@ -106,7 +116,6 @@ void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl) IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) pr_warn("PUSH_IDLE pattern timedout\n"); - mutex_unlock(&ctrl->push_idle_mutex); pr_debug("mainlink off done\n"); } @@ -979,7 +988,7 @@ static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl) if (!wait_for_completion_timeout(&ctrl->video_comp, WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES)) { - DRM_ERROR("Link Train timedout\n"); + DRM_ERROR("wait4video timedout\n"); ret = -ETIMEDOUT; } return ret; @@ -1000,13 +1009,13 @@ static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl) if (ret) return ret; - if (voltage_swing_level > DP_TRAIN_VOLTAGE_SWING_MAX) { + if (voltage_swing_level >= DP_TRAIN_VOLTAGE_SWING_MAX) { DRM_DEBUG_DP("max. voltage swing level reached %d\n", voltage_swing_level); max_level_reached |= DP_TRAIN_MAX_SWING_REACHED; } - if (pre_emphasis_level == DP_TRAIN_PRE_EMPHASIS_MAX) { + if (pre_emphasis_level >= DP_TRAIN_PRE_EMPHASIS_MAX) { DRM_DEBUG_DP("max. pre-emphasis level reached %d\n", pre_emphasis_level); max_level_reached |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; @@ -1038,8 +1047,11 @@ static bool dp_ctrl_train_pattern_set(struct dp_ctrl_private *ctrl, DRM_DEBUG_DP("sink: pattern=%x\n", pattern); buf = pattern; - ret = drm_dp_dpcd_writeb(ctrl->aux, - DP_TRAINING_PATTERN_SET, buf); + + if (pattern && pattern != DP_TRAINING_PATTERN_4) + buf |= DP_LINK_SCRAMBLING_DISABLE; + + ret = drm_dp_dpcd_writeb(ctrl->aux, DP_TRAINING_PATTERN_SET, buf); return ret == 1; } @@ -1065,19 +1077,23 @@ static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl, return -ETIMEDOUT; } -static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl) +static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl, + struct dp_cr_status *cr, int *training_step) { int tries, old_v_level, ret = 0; u8 link_status[DP_LINK_STATUS_SIZE]; - int const maximum_retries = 5; + int const maximum_retries = 4; dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); + *training_step = DP_TRAINING_1; + ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, DP_TRAINING_PATTERN_1); if (ret) return ret; dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE); + ret = dp_ctrl_update_vx_px(ctrl); if (ret) return ret; @@ -1091,12 +1107,15 @@ static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl) if (ret) return ret; + cr->lane_0_1 = link_status[0]; + cr->lane_2_3 = link_status[1]; + if (drm_dp_clock_recovery_ok(link_status, ctrl->link->link_params.num_lanes)) { - return ret; + return 0; } - if (ctrl->link->phy_params.v_level > + if (ctrl->link->phy_params.v_level >= DP_TRAIN_VOLTAGE_SWING_MAX) { DRM_ERROR_RATELIMITED("max v_level reached\n"); return -EAGAIN; @@ -1119,8 +1138,10 @@ static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl) return -ETIMEDOUT; } -static void dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl) +static int dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl) { + int ret = 0; + switch (ctrl->link->link_params.rate) { case 810000: ctrl->link->link_params.rate = 540000; @@ -1129,13 +1150,33 @@ static void dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl) ctrl->link->link_params.rate = 270000; break; case 270000: + ctrl->link->link_params.rate = 162000; + break; case 162000: default: - ctrl->link->link_params.rate = 162000; + ret = -EINVAL; break; }; - DRM_DEBUG_DP("new rate=0x%x\n", ctrl->link->link_params.rate); + if (!ret) + DRM_DEBUG_DP("new rate=0x%x\n", ctrl->link->link_params.rate); + + return ret; +} + +static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl) +{ + + if (ctrl->link->link_params.num_lanes == 1) + return -1; + + ctrl->link->link_params.num_lanes /= 2; + ctrl->link->link_params.rate = ctrl->panel->link_info.rate; + + ctrl->link->phy_params.p_level = 0; + ctrl->link->phy_params.v_level = 0; + + return 0; } static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl) @@ -1144,7 +1185,8 @@ static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl) drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd); } -static int dp_ctrl_link_training_2(struct dp_ctrl_private *ctrl) +static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, + struct dp_cr_status *cr, int *training_step) { int tries = 0, ret = 0; char pattern; @@ -1153,6 +1195,8 @@ static int dp_ctrl_link_training_2(struct dp_ctrl_private *ctrl) dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); + *training_step = DP_TRAINING_2; + if (drm_dp_tps3_supported(ctrl->panel->dpcd)) pattern = DP_TRAINING_PATTERN_3; else @@ -1174,10 +1218,13 @@ static int dp_ctrl_link_training_2(struct dp_ctrl_private *ctrl) ret = dp_ctrl_read_link_status(ctrl, link_status); if (ret) return ret; + cr->lane_0_1 = link_status[0]; + cr->lane_2_3 = link_status[1]; if (drm_dp_channel_eq_ok(link_status, - ctrl->link->link_params.num_lanes)) - return ret; + ctrl->link->link_params.num_lanes)) { + return 0; + } dp_link_adjust_levels(ctrl->link, link_status); ret = dp_ctrl_update_vx_px(ctrl); @@ -1189,15 +1236,15 @@ static int dp_ctrl_link_training_2(struct dp_ctrl_private *ctrl) return -ETIMEDOUT; } -static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl) +static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl); + +static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, + struct dp_cr_status *cr, int *training_step) { int ret = 0; u8 encoding = DP_SET_ANSI_8B10B; struct dp_link_info link_info = {0}; - ctrl->link->phy_params.p_level = 0; - ctrl->link->phy_params.v_level = 0; - dp_ctrl_config_ctrl(ctrl); link_info.num_lanes = ctrl->link->link_params.num_lanes; @@ -1208,7 +1255,7 @@ static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl) drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, &encoding, 1); - ret = dp_ctrl_link_train_1(ctrl); + ret = dp_ctrl_link_train_1(ctrl, cr, training_step); if (ret) { DRM_ERROR("link training #1 failed. ret=%d\n", ret); goto end; @@ -1217,7 +1264,7 @@ static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl) /* print success info as this is a result of user initiated action */ DRM_DEBUG_DP("link training #1 successful\n"); - ret = dp_ctrl_link_training_2(ctrl); + ret = dp_ctrl_link_train_2(ctrl, cr, training_step); if (ret) { DRM_ERROR("link training #2 failed. ret=%d\n", ret); goto end; @@ -1229,58 +1276,36 @@ static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl) end: dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); - dp_ctrl_clear_training_pattern(ctrl); return ret; } -static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl, bool train) +static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl, + struct dp_cr_status *cr, int *training_step) { - bool mainlink_ready = false; int ret = 0; dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); - ret = dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, false); - if (ret) - return ret; - if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) return ret; - if (train) { - /* - * As part of previous calls, DP controller state might have - * transitioned to PUSH_IDLE. In order to start transmitting - * a link training pattern, we have to first do soft reset. - */ - dp_catalog_ctrl_reset(ctrl->catalog); - - ret = dp_ctrl_link_train(ctrl); - if (ret) - return ret; - } - /* - * Set up transfer unit values and set controller state to send - * video. + * As part of previous calls, DP controller state might have + * transitioned to PUSH_IDLE. In order to start transmitting + * a link training pattern, we have to first do soft reset. */ - dp_ctrl_setup_tr_unit(ctrl); - dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); + dp_catalog_ctrl_reset(ctrl->catalog); - ret = dp_ctrl_wait4video_ready(ctrl); - if (ret) - return ret; + ret = dp_ctrl_link_train(ctrl, cr, training_step); - mainlink_ready = dp_catalog_ctrl_mainlink_ready(ctrl->catalog); - DRM_DEBUG_DP("mainlink %s\n", mainlink_ready ? "READY" : "NOT READY"); return ret; } static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl, - char *name, u32 rate) + enum dp_pm_type module, char *name, u32 rate) { - u32 num = ctrl->parser->mp[DP_CTRL_PM].num_clk; - struct dss_clk *cfg = ctrl->parser->mp[DP_CTRL_PM].clk_config; + u32 num = ctrl->parser->mp[module].num_clk; + struct dss_clk *cfg = ctrl->parser->mp[module].clk_config; while (num && strcmp(cfg->clk_name, name)) { num--; @@ -1302,16 +1327,33 @@ static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) dp_power_set_link_clk_parent(ctrl->power); - dp_ctrl_set_clock_rate(ctrl, "ctrl_link", + dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link", ctrl->link->link_params.rate); - dp_ctrl_set_clock_rate(ctrl, "stream_pixel", - ctrl->dp_ctrl.pixel_rate); - ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true); if (ret) DRM_ERROR("Unable to start link clocks. ret=%d\n", ret); + DRM_DEBUG_DP("link rate=%d pixel_clk=%d\n", + ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate); + + return ret; +} + +static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl) +{ + int ret = 0; + + dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", + ctrl->dp_ctrl.pixel_rate); + + ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true); + if (ret) + DRM_ERROR("Unabled to start pixel clocks. ret=%d\n", ret); + + DRM_DEBUG_DP("link rate=%d pixel_clk=%d\n", + ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate); + return ret; } @@ -1401,37 +1443,30 @@ static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl) return ret; } - dp_ctrl_configure_source_params(ctrl); - dp_catalog_ctrl_config_msa(ctrl->catalog, - ctrl->link->link_params.rate, - ctrl->dp_ctrl.pixel_rate, dp_ctrl_use_fixed_nvid(ctrl)); - reinit_completion(&ctrl->idle_comp); - return ret; } static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl) { int ret = 0; - int tries; + struct dp_cr_status cr; + int training_step = DP_TRAINING_NONE; dp_ctrl_push_idle(&ctrl->dp_ctrl); dp_catalog_ctrl_reset(ctrl->catalog); ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; - for (tries = 0; tries < 10; tries++) { - ret = dp_ctrl_reinitialize_mainlink(ctrl); - if (ret) { - DRM_ERROR("Failed to reinitialize mainlink. ret=%d\n", - ret); - break; - } + ret = dp_ctrl_setup_main_link(ctrl, &cr, &training_step); + if (ret) + goto end; - ret = dp_ctrl_setup_main_link(ctrl, true); - if (ret == -EAGAIN) /* try with lower link rate */ - dp_ctrl_link_rate_down_shift(ctrl); - } + dp_ctrl_clear_training_pattern(ctrl); + + dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); + + ret = dp_ctrl_wait4video_ready(ctrl); +end: return ret; } @@ -1444,22 +1479,22 @@ static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl) return ret; } - dp_ctrl_push_idle(&ctrl->dp_ctrl); /* * The global reset will need DP link related clocks to be * running. Add the global reset just before disabling the * link clocks and core clocks. */ - dp_catalog_ctrl_reset(ctrl->catalog); ret = dp_ctrl_off(&ctrl->dp_ctrl); if (ret) { DRM_ERROR("failed to disable DP controller\n"); return ret; } - ret = dp_ctrl_on(&ctrl->dp_ctrl); - if (ret) - DRM_ERROR("failed to enable DP controller\n"); + ret = dp_ctrl_on_link(&ctrl->dp_ctrl); + if (!ret) + ret = dp_ctrl_on_stream(&ctrl->dp_ctrl); + else + DRM_ERROR("failed to enable DP link controller\n"); return ret; } @@ -1479,27 +1514,33 @@ static bool dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl) return false; } dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested); + dp_ctrl_update_vx_px(ctrl); dp_link_send_test_response(ctrl->link); pattern_sent = dp_catalog_ctrl_read_phy_pattern(ctrl->catalog); switch (pattern_sent) { case MR_LINK_TRAINING1: - success = pattern_requested == - DP_LINK_QUAL_PATTERN_D10_2; + success = (pattern_requested == + DP_PHY_TEST_PATTERN_D10_2); break; case MR_LINK_SYMBOL_ERM: - success = (pattern_requested == - DP_LINK_QUAL_PATTERN_ERROR_RATE) - || (pattern_requested == - DP_LINK_QUAL_PATTERN_HBR2_EYE); + success = ((pattern_requested == + DP_PHY_TEST_PATTERN_ERROR_COUNT) || + (pattern_requested == + DP_PHY_TEST_PATTERN_CP2520)); break; case MR_LINK_PRBS7: - success = pattern_requested == DP_LINK_QUAL_PATTERN_PRBS7; + success = (pattern_requested == + DP_PHY_TEST_PATTERN_PRBS7); break; case MR_LINK_CUSTOM80: - success = pattern_requested == - DP_LINK_QUAL_PATTERN_80BIT_CUSTOM; + success = (pattern_requested == + DP_PHY_TEST_PATTERN_80BIT_CUSTOM); + break; + case MR_LINK_TRAINING4: + success = (pattern_requested == + DP_PHY_TEST_PATTERN_SEL_MASK); break; default: success = false; @@ -1531,12 +1572,12 @@ void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl) } } - if (sink_request & DP_LINK_STATUS_UPDATED) + if (sink_request & DP_LINK_STATUS_UPDATED) { if (dp_ctrl_link_maintenance(ctrl)) { - DRM_ERROR("LM failed: STATUS_UPDATED\n"); + DRM_ERROR("LM failed: TEST_LINK_TRAINING\n"); return; } - + } if (sink_request & DP_TEST_LINK_TRAINING) { dp_link_send_test_response(ctrl->link); @@ -1547,13 +1588,15 @@ void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl) } } -int dp_ctrl_on(struct dp_ctrl *dp_ctrl) +int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl) { int rc = 0; struct dp_ctrl_private *ctrl; u32 rate = 0; - u32 link_train_max_retries = 10; + int link_train_max_retries = 5; u32 const phy_cts_pixel_clk_khz = 148500; + struct dp_cr_status cr; + unsigned int training_step; if (!dp_ctrl) return -EINVAL; @@ -1587,6 +1630,9 @@ int dp_ctrl_on(struct dp_ctrl *dp_ctrl) if (rc) return rc; + ctrl->link->phy_params.p_level = 0; + ctrl->link->phy_params.v_level = 0; + while (--link_train_max_retries && !atomic_read(&ctrl->dp_ctrl.aborted)) { rc = dp_ctrl_reinitialize_mainlink(ctrl); @@ -1595,19 +1641,125 @@ int dp_ctrl_on(struct dp_ctrl *dp_ctrl) rc); break; } - rc = dp_ctrl_setup_main_link(ctrl, true); - if (!rc) + + training_step = DP_TRAINING_NONE; + rc = dp_ctrl_setup_main_link(ctrl, &cr, &training_step); + if (rc == 0) { + /* training completed successfully */ break; - /* try with lower link rate */ - dp_ctrl_link_rate_down_shift(ctrl); + } else if (training_step == DP_TRAINING_1) { + /* link train_1 failed */ + rc = dp_ctrl_link_rate_down_shift(ctrl); + if (rc < 0) { /* already in RBR = 1.6G */ + if (cr.lane_0_1 & DP_LANE0_1_CR_DONE) { + /* + * some lanes are ready, + * reduce lane number + */ + rc = dp_ctrl_link_lane_down_shift(ctrl); + if (rc < 0) { /* lane == 1 already */ + /* end with failure */ + break; + } + } else { + /* end with failure */ + break; /* lane == 1 already */ + } + } + } else if (training_step == DP_TRAINING_2) { + /* link train_2 failed, lower lane rate */ + rc = dp_ctrl_link_lane_down_shift(ctrl); + if (rc < 0) { + /* end with failure */ + break; /* lane == 1 already */ + } + } } if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) - dp_ctrl_send_phy_test_pattern(ctrl); + return rc; + + /* stop txing train pattern */ + dp_ctrl_clear_training_pattern(ctrl); + + /* + * keep transmitting idle pattern until video ready + * to avoid main link from loss of sync + */ + if (rc == 0) /* link train successfully */ + dp_ctrl_push_idle(dp_ctrl); return rc; } +int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl) +{ + u32 rate = 0; + int ret = 0; + bool mainlink_ready = false; + struct dp_ctrl_private *ctrl; + + if (!dp_ctrl) + return -EINVAL; + + ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); + + rate = ctrl->panel->link_info.rate; + + ctrl->link->link_params.rate = rate; + ctrl->link->link_params.num_lanes = ctrl->panel->link_info.num_lanes; + ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; + + DRM_DEBUG_DP("rate=%d, num_lanes=%d, pixel_rate=%d\n", + ctrl->link->link_params.rate, + ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate); + + if (!dp_power_clk_status(ctrl->power, DP_CTRL_PM)) { /* link clk is off */ + ret = dp_ctrl_enable_mainlink_clocks(ctrl); + if (ret) { + DRM_ERROR("Failed to start link clocks. ret=%d\n", ret); + goto end; + } + } + + ret = dp_ctrl_enable_stream_clocks(ctrl); + if (ret) { + DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); + goto end; + } + + if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { + dp_ctrl_send_phy_test_pattern(ctrl); + return 0; + } + + /* + * Set up transfer unit values and set controller state to send + * video. + */ + dp_ctrl_configure_source_params(ctrl); + + dp_catalog_ctrl_config_msa(ctrl->catalog, + ctrl->link->link_params.rate, + ctrl->dp_ctrl.pixel_rate, dp_ctrl_use_fixed_nvid(ctrl)); + + reinit_completion(&ctrl->video_comp); + + dp_ctrl_setup_tr_unit(ctrl); + + dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); + + ret = dp_ctrl_wait4video_ready(ctrl); + if (ret) + return ret; + + mainlink_ready = dp_catalog_ctrl_mainlink_ready(ctrl->catalog); + DRM_DEBUG_DP("mainlink %s\n", mainlink_ready ? "READY" : "NOT READY"); + +end: + return ret; +} + int dp_ctrl_off(struct dp_ctrl *dp_ctrl) { struct dp_ctrl_private *ctrl; @@ -1619,11 +1771,16 @@ int dp_ctrl_off(struct dp_ctrl *dp_ctrl) ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); + dp_catalog_ctrl_reset(ctrl->catalog); + + ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false); + if (ret) + DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret); + ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); if (ret) { - DRM_ERROR("Failed to disable clocks. ret=%d\n", ret); - return ret; + DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); } DRM_DEBUG_DP("DP off done\n"); @@ -1674,7 +1831,6 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link, init_completion(&ctrl->idle_comp); init_completion(&ctrl->video_comp); - mutex_init(&ctrl->push_idle_mutex); /* in parameters */ ctrl->parser = parser; diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h index 94713a0daff0..f60ba93c8678 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -21,7 +21,8 @@ struct dp_ctrl { int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip); void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl); -int dp_ctrl_on(struct dp_ctrl *dp_ctrl); +int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl); +int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl); int dp_ctrl_off(struct dp_ctrl *dp_ctrl); void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl); void dp_ctrl_isr(struct dp_ctrl *dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 925c89720a16..18ca5eac8e20 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -9,6 +9,7 @@ #include #include #include +#include #include "msm_drv.h" #include "msm_kms.h" @@ -28,6 +29,52 @@ static struct msm_dp *g_dp_display; #define HPD_STRING_SIZE 30 +enum { + ISR_DISCONNECTED, + ISR_CONNECT_PENDING, + ISR_CONNECTED, + ISR_HPD_REPLUG_COUNT, + ISR_IRQ_HPD_PULSE_COUNT, + ISR_HPD_LO_GLITH_COUNT, +}; + +/* event thread connection state */ +enum { + ST_DISCONNECTED, + ST_CONNECT_PENDING, + ST_CONNECTED, + ST_DISCONNECT_PENDING, + ST_SUSPEND_PENDING, + ST_SUSPENDED, +}; + +enum { + EV_NO_EVENT, + /* hpd events */ + EV_HPD_INIT_SETUP, + EV_HPD_PLUG_INT, + EV_IRQ_HPD_INT, + EV_HPD_REPLUG_INT, + EV_HPD_UNPLUG_INT, + EV_USER_NOTIFICATION, + EV_CONNECT_PENDING_TIMEOUT, + EV_DISCONNECT_PENDING_TIMEOUT, +}; + +#define EVENT_TIMEOUT (HZ/10) /* 100ms */ +#define DP_EVENT_Q_MAX 8 + +#define DP_TIMEOUT_5_SECOND (5000/EVENT_TIMEOUT) +#define DP_TIMEOUT_NONE 0 + +#define WAIT_FOR_RESUME_TIMEOUT_JIFFIES (HZ / 2) + +struct dp_event { + u32 event_id; + u32 data; + u32 delay; +}; + struct dp_display_private { char *name; int irq; @@ -37,11 +84,9 @@ struct dp_display_private { bool power_on; bool hpd_irq_on; bool audio_supported; - atomic_t hpd_isr_status; struct platform_device *pdev; struct dentry *root; - struct completion notification_comp; struct dp_usbpd *usbpd; struct dp_parser *parser; @@ -52,12 +97,22 @@ struct dp_display_private { struct dp_link *link; struct dp_panel *panel; struct dp_ctrl *ctrl; + struct dp_debug *debug; struct dp_usbpd_cb usbpd_cb; struct dp_display_mode dp_mode; struct msm_dp dp_display; - struct delayed_work config_hpd_work; + /* event related only access by event thread */ + struct mutex event_mutex; + wait_queue_head_t event_q; + atomic_t hpd_state; + u32 event_pndx; + u32 event_gndx; + struct dp_event event_list[DP_EVENT_Q_MAX]; + spinlock_t event_lock; + + struct completion resume_comp; }; static const struct of_device_id dp_dt_match[] = { @@ -65,79 +120,58 @@ static const struct of_device_id dp_dt_match[] = { {} }; -static irqreturn_t dp_display_irq(int irq, void *dev_id) +static int dp_add_event(struct dp_display_private *dp_priv, u32 event, + u32 data, u32 delay) { - struct dp_display_private *dp = dev_id; - irqreturn_t ret = IRQ_HANDLED; - u32 hpd_isr_status; - - if (!dp) { - DRM_ERROR("invalid data\n"); - return IRQ_NONE; - } - - hpd_isr_status = dp_catalog_hpd_get_intr_status(dp->catalog); - - if (hpd_isr_status & DP_DP_HPD_INT_MASK) { - atomic_set(&dp->hpd_isr_status, hpd_isr_status); - ret = IRQ_WAKE_THREAD; + unsigned long flag; + struct dp_event *todo; + int pndx; + + spin_lock_irqsave(&dp_priv->event_lock, flag); + pndx = dp_priv->event_pndx + 1; + pndx %= DP_EVENT_Q_MAX; + if (pndx == dp_priv->event_gndx) { + pr_err("event_q is full: pndx=%d gndx=%d\n", + dp_priv->event_pndx, dp_priv->event_gndx); + spin_unlock_irqrestore(&dp_priv->event_lock, flag); + return -EPERM; } + todo = &dp_priv->event_list[dp_priv->event_pndx++]; + dp_priv->event_pndx %= DP_EVENT_Q_MAX; + todo->event_id = event; + todo->data = data; + todo->delay = delay; + wake_up(&dp_priv->event_q); + spin_unlock_irqrestore(&dp_priv->event_lock, flag); - /* DP controller isr */ - dp_ctrl_isr(dp->ctrl); - - /* DP aux isr */ - dp_aux_isr(dp->aux); - - return ret; + return 0; } -static irqreturn_t dp_display_hpd_isr_work(int irq, void *data) +static int dp_del_event(struct dp_display_private *dp_priv, u32 event) { - struct dp_display_private *dp; - struct dp_usbpd *hpd; - u32 isr = 0; - - dp = (struct dp_display_private *)data; - if (!dp) - return IRQ_NONE; - - isr = atomic_read(&dp->hpd_isr_status); - - /* reset to default */ - atomic_set(&dp->hpd_isr_status, 0); - - hpd = dp->usbpd; - if (!hpd) - return IRQ_NONE; - - if (isr & DP_DP_HPD_PLUG_INT_MASK && - isr & DP_DP_HPD_STATE_STATUS_CONNECTED) { - hpd->hpd_high = 1; - dp->usbpd_cb.configure(&dp->pdev->dev); - } else if (isr & DP_DP_HPD_UNPLUG_INT_MASK && - (isr & DP_DP_HPD_STATE_STATUS_MASK) == - DP_DP_HPD_STATE_STATUS_DISCONNECTED) { - - /* disable HPD plug interrupt until disconnect is done - */ - dp_catalog_hpd_config_intr(dp->catalog, - DP_DP_HPD_PLUG_INT_MASK | DP_DP_IRQ_HPD_INT_MASK, - false); - - hpd->hpd_high = 0; - - /* We don't need separate work for disconnect as - * connect/attention interrupts are disabled - */ - dp->usbpd_cb.disconnect(&dp->pdev->dev); + unsigned long flag; + struct dp_event *todo; + u32 gndx; + + spin_lock_irqsave(&dp_priv->event_lock, flag); + if (dp_priv->event_pndx == dp_priv->event_gndx) { + spin_unlock_irqrestore(&dp_priv->event_lock, flag); + return -ENOENT; + } - dp_catalog_hpd_config_intr(dp->catalog, - DP_DP_HPD_PLUG_INT_MASK | DP_DP_IRQ_HPD_INT_MASK, - true); + gndx = dp_priv->event_gndx; + while (dp_priv->event_pndx != gndx) { + todo = &dp_priv->event_list[gndx]; + if (todo->event_id == event) { + todo->event_id = EV_NO_EVENT; /* deleted */ + todo->delay = 0; + } + gndx++; + gndx %= DP_EVENT_Q_MAX; } + spin_unlock_irqrestore(&dp_priv->event_lock, flag); - return IRQ_HANDLED; + return 0; } static int dp_display_bind(struct device *dev, struct device *master, @@ -178,7 +212,6 @@ static int dp_display_bind(struct device *dev, struct device *master, DRM_ERROR("Power client create failed\n"); goto end; } - end: return rc; } @@ -237,11 +270,9 @@ static int dp_display_send_hpd_notification(struct dp_display_private *dp, struct msm_drm_private *priv = dp->dp_display.drm_dev->dev_private; struct msm_kms *kms = priv->kms; - mutex_lock(&dp->dp_display.connect_mutex); if ((hpd && dp->dp_display.is_connected) || (!hpd && !dp->dp_display.is_connected)) { DRM_DEBUG_DP("HPD already %s\n", (hpd ? "on" : "off")); - mutex_unlock(&dp->dp_display.connect_mutex); return 0; } @@ -250,7 +281,6 @@ static int dp_display_send_hpd_notification(struct dp_display_private *dp, dp->panel->video_test = false; dp->dp_display.is_connected = hpd; - reinit_completion(&dp->notification_comp); if (dp->dp_display.is_connected && dp->dp_display.encoder && !encoder_mode_set @@ -263,13 +293,6 @@ static int dp_display_send_hpd_notification(struct dp_display_private *dp, dp_display_send_hpd_event(&dp->dp_display); - if (!wait_for_completion_timeout(&dp->notification_comp, HZ * 2)) { - pr_warn("%s timeout\n", hpd ? "connect" : "disconnect"); - mutex_unlock(&dp->dp_display.connect_mutex); - return -EINVAL; - } - - mutex_unlock(&dp->dp_display.connect_mutex); return 0; } @@ -278,23 +301,14 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp) int rc = 0; struct edid *edid; - if (dp->link->psm_enabled) - goto notify; - dp->panel->max_dp_lanes = dp->parser->max_dp_lanes; rc = dp_panel_read_sink_caps(dp->panel, dp->dp_display.connector); if (rc) - goto notify; + goto end; dp_link_process_request(dp->link); - if (dp_display_is_sink_count_zero(dp)) { - DRM_DEBUG_DP("no downstream devices connected\n"); - rc = -EINVAL; - goto end; - } - edid = dp->panel->edid; dp->audio_supported = drm_detect_monitor_audio(edid); @@ -302,8 +316,15 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp) dp->dp_display.max_pclk_khz = DP_MAX_PIXEL_CLK_KHZ; dp->dp_display.max_dp_lanes = dp->parser->max_dp_lanes; -notify: - dp_display_send_hpd_notification(dp, true); + + rc = dp_ctrl_on_link(dp->ctrl); + if (rc) { + DRM_ERROR("failed to complete DP link training\n"); + goto end; + } + + dp_add_event(dp, EV_USER_NOTIFICATION, true, 0); + end: return rc; @@ -327,23 +348,6 @@ static void dp_display_host_init(struct dp_display_private *dp) dp->core_initialized = true; } -static void dp_display_host_deinit(struct dp_display_private *dp) -{ - if (!dp->core_initialized) { - DRM_DEBUG_DP("DP core already off\n"); - return; - } - - dp->core_initialized = false; -} - -static void dp_display_process_hpd_low(struct dp_display_private *dp) -{ - dp_display_send_hpd_notification(dp, false); - - dp_aux_deinit(dp->aux); -} - static int dp_display_usbpd_configure_cb(struct device *dev) { int rc = 0; @@ -364,18 +368,16 @@ static int dp_display_usbpd_configure_cb(struct device *dev) dp_display_host_init(dp); - if (dp->usbpd->hpd_high) - dp_display_process_hpd_high(dp); + /* + * set sink to normal operation mode -- D0 + * before dpcd read + */ + dp_link_psm_config(dp->link, &dp->panel->link_info, false); + rc = dp_display_process_hpd_high(dp); end: return rc; } -static void dp_display_clean(struct dp_display_private *dp) -{ - dp_ctrl_push_idle(dp->ctrl); - dp_ctrl_off(dp->ctrl); -} - static int dp_display_usbpd_disconnect_cb(struct device *dev) { int rc = 0; @@ -383,16 +385,8 @@ static int dp_display_usbpd_disconnect_cb(struct device *dev) dp = dev_get_drvdata(dev); - rc = dp_display_send_hpd_notification(dp, false); + dp_add_event(dp, EV_USER_NOTIFICATION, false, 0); - /* if cable is disconnected, reset psm_enabled flag */ - if (!dp->usbpd->alt_mode_cfg_done) - dp->link->psm_enabled = false; - - if ((rc < 0) && dp->power_on) - dp_display_clean(dp); - - dp_display_host_deinit(dp); return rc; } @@ -407,11 +401,14 @@ static void dp_display_handle_video_request(struct dp_display_private *dp) } } -static int dp_display_handle_hpd_irq(struct dp_display_private *dp) +static int dp_display_handle_irq_hpd(struct dp_display_private *dp) { - if (dp->link->sink_request & DS_PORT_STATUS_CHANGED) { - dp_display_send_hpd_notification(dp, false); + u32 sink_request; + + sink_request = dp->link->sink_request; + if (sink_request & DS_PORT_STATUS_CHANGED) { + dp_add_event(dp, EV_USER_NOTIFICATION, false, 0); if (dp_display_is_sink_count_zero(dp)) { DRM_DEBUG_DP("sink count is zero, nothing to do\n"); return 0; @@ -422,7 +419,8 @@ static int dp_display_handle_hpd_irq(struct dp_display_private *dp) dp_ctrl_handle_sink_request(dp->ctrl); - dp_display_handle_video_request(dp); + if (dp->link->sink_request & DP_TEST_LINK_VIDEO_PATTERN) + dp_display_handle_video_request(dp); return 0; } @@ -443,27 +441,174 @@ static int dp_display_usbpd_attention_cb(struct device *dev) return -ENODEV; } - if (dp->usbpd->hpd_irq) { - dp->hpd_irq_on = true; + /* check for any test request issued by sink */ + rc = dp_link_process_request(dp->link); + if (!rc) + dp_display_handle_irq_hpd(dp); - rc = dp_link_process_request(dp->link); - /* check for any test request issued by sink */ - if (!rc) - dp_display_handle_hpd_irq(dp); + return rc; +} - dp->hpd_irq_on = false; - goto end; +static int dp_hpd_plug_handle(struct dp_display_private *dp, u32 data) +{ + struct dp_usbpd *hpd = dp->usbpd; + u32 state; + u32 tout = DP_TIMEOUT_5_SECOND; + int ret; + + if (!hpd) + return 0; + + mutex_lock(&dp->event_mutex); + + state = atomic_read(&dp->hpd_state); + if (state == ST_SUSPEND_PENDING) { + mutex_unlock(&dp->event_mutex); + return 0; } - if (!dp->usbpd->hpd_high) { - dp_display_process_hpd_low(dp); - goto end; + if (state == ST_CONNECT_PENDING || state == ST_CONNECTED) { + mutex_unlock(&dp->event_mutex); + return 0; } - if (dp->usbpd->alt_mode_cfg_done) - dp_display_process_hpd_high(dp); -end: - return rc; + if (state == ST_DISCONNECT_PENDING) { + /* wait until ST_DISCONNECTED */ + dp_add_event(dp, EV_HPD_PLUG_INT, 0, 1); /* delay = 1 */ + mutex_unlock(&dp->event_mutex); + return 0; + } + + if (state == ST_SUSPENDED) + tout = DP_TIMEOUT_NONE; + + atomic_set(&dp->hpd_state, ST_CONNECT_PENDING); + + hpd->hpd_high = 1; + + ret = dp_display_usbpd_configure_cb(&dp->pdev->dev); + if (ret) { /* failed */ + hpd->hpd_high = 0; + atomic_set(&dp->hpd_state, ST_DISCONNECTED); + } + + /* start sanity checking */ + dp_add_event(dp, EV_CONNECT_PENDING_TIMEOUT, 0, tout); + + mutex_unlock(&dp->event_mutex); + + /* uevent will complete connection part */ + return 0; +}; + +static int dp_display_enable(struct dp_display_private *dp, u32 data); +static int dp_display_disable(struct dp_display_private *dp, u32 data); + +static int dp_connect_pending_timeout(struct dp_display_private *dp, u32 data) +{ + u32 state; + + mutex_lock(&dp->event_mutex); + + state = atomic_read(&dp->hpd_state); + if (state == ST_CONNECT_PENDING) { + dp_display_enable(dp, 0); + atomic_set(&dp->hpd_state, ST_CONNECTED); + } + + mutex_unlock(&dp->event_mutex); + + return 0; +} + +static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) +{ + struct dp_usbpd *hpd = dp->usbpd; + u32 state; + + if (!hpd) + return 0; + + mutex_lock(&dp->event_mutex); + + state = atomic_read(&dp->hpd_state); + if (state == ST_SUSPEND_PENDING) { + mutex_unlock(&dp->event_mutex); + return 0; + } + + if (state == ST_DISCONNECT_PENDING || state == ST_DISCONNECTED) { + mutex_unlock(&dp->event_mutex); + return 0; + } + + if (state == ST_CONNECT_PENDING) { + /* wait until CONNECTED */ + dp_add_event(dp, EV_HPD_UNPLUG_INT, 0, 1); /* delay = 1 */ + mutex_unlock(&dp->event_mutex); + return 0; + } + + atomic_set(&dp->hpd_state, ST_DISCONNECT_PENDING); + + /* disable HPD plug interrupt until disconnect is done */ + dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK + | DP_DP_IRQ_HPD_INT_MASK, false); + + hpd->hpd_high = 0; + + /* + * We don't need separate work for disconnect as + * connect/attention interrupts are disabled + */ + dp_display_usbpd_disconnect_cb(&dp->pdev->dev); + + /* start sanity checking */ + dp_add_event(dp, EV_DISCONNECT_PENDING_TIMEOUT, 0, DP_TIMEOUT_5_SECOND); + + dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK | + DP_DP_IRQ_HPD_INT_MASK, true); + + /* uevent will complete disconnection part */ + mutex_unlock(&dp->event_mutex); + return 0; +} + +static int dp_disconnect_pending_timeout(struct dp_display_private *dp, u32 data) +{ + u32 state; + + mutex_lock(&dp->event_mutex); + + state = atomic_read(&dp->hpd_state); + if (state == ST_DISCONNECT_PENDING) { + dp_display_disable(dp, 0); + atomic_set(&dp->hpd_state, ST_DISCONNECTED); + } + + mutex_unlock(&dp->event_mutex); + + return 0; +} + +static int dp_irq_hpd_handle(struct dp_display_private *dp, u32 data) +{ + u32 state; + + mutex_lock(&dp->event_mutex); + + /* irq_hpd can happen at either connected or disconnected state */ + state = atomic_read(&dp->hpd_state); + if (state == ST_SUSPEND_PENDING) { + mutex_unlock(&dp->event_mutex); + return 0; + } + + dp_display_usbpd_attention_cb(&dp->pdev->dev); + + mutex_unlock(&dp->event_mutex); + + return 0; } static void dp_display_deinit_sub_modules(struct dp_display_private *dp) @@ -599,106 +744,39 @@ static int dp_display_prepare(struct msm_dp *dp) return 0; } -static void dp_display_dump(struct msm_dp *dp_display) -{ - struct dp_display_private *dp; - - dp = container_of(dp_display, struct dp_display_private, dp_display); - - dp_panel_dump_regs(dp->panel); -} - -static int dp_display_enable(struct msm_dp *dp_display) +static int dp_display_enable(struct dp_display_private *dp, u32 data) { int rc = 0; - struct dp_display_private *dp; - bool dump_dp = false; - - dp = container_of(dp_display, struct dp_display_private, dp_display); if (dp->power_on) { DRM_DEBUG_DP("Link already setup, return\n"); return 0; } - rc = dp_ctrl_on(dp->ctrl); + rc = dp_ctrl_on_stream(dp->ctrl); if (!rc) dp->power_on = true; - if (dump_dp != false) - dp_display_dump(dp_display); - + /* complete resume_comp regardless it is armed or not */ + complete(&dp->resume_comp); return rc; } static int dp_display_post_enable(struct msm_dp *dp_display) { - struct dp_display_private *dp; - - dp = container_of(dp_display, struct dp_display_private, dp_display); - - complete_all(&dp->notification_comp); - return 0; -} - -static int dp_display_pre_disable(struct msm_dp *dp_display) -{ - struct dp_display_private *dp; - - dp = container_of(dp_display, struct dp_display_private, dp_display); - - if (dp->usbpd->alt_mode_cfg_done) - dp_link_psm_config(dp->link, &dp->panel->link_info, true); - - dp_ctrl_push_idle(dp->ctrl); return 0; } -static int dp_display_disable(struct msm_dp *dp_display) +static int dp_display_disable(struct dp_display_private *dp, u32 data) { - struct dp_display_private *dp; - - dp = container_of(dp_display, struct dp_display_private, dp_display); - - if (!dp->power_on || !dp->core_initialized) + if (!dp->power_on) return -EINVAL; dp_ctrl_off(dp->ctrl); - dp->power_on = false; - - complete_all(&dp->notification_comp); - return 0; -} - -int dp_display_request_irq(struct msm_dp *dp_display) -{ - int rc = 0; - struct dp_display_private *dp; - - if (!dp_display) { - DRM_ERROR("invalid input\n"); - return -EINVAL; - } - - dp = container_of(dp_display, struct dp_display_private, dp_display); - - dp->irq = irq_of_parse_and_map(dp->pdev->dev.of_node, 0); - if (dp->irq < 0) { - rc = dp->irq; - DRM_ERROR("failed to get irq: %d\n", rc); - return rc; - } + dp->core_initialized = false; - rc = devm_request_threaded_irq(&dp->pdev->dev, dp->irq, - dp_display_irq, dp_display_hpd_isr_work, - IRQF_TRIGGER_HIGH, "dp_display_isr", dp); - if (rc < 0) { - DRM_ERROR("failed to request IRQ%u: %d\n", - dp->irq, rc); - return rc; - } - disable_irq(dp->irq); + dp->power_on = false; return 0; } @@ -783,6 +861,192 @@ int dp_display_get_test_bpp(struct msm_dp *dp) dp_display->link->test_video.test_bit_depth); } +static void dp_display_config_hpd(struct dp_display_private *dp) +{ + + dp_display_host_init(dp); + dp_catalog_ctrl_hpd_config(dp->catalog); + + /* Enable interrupt first time + * we are leaving dp clocks on during disconnect + * and never disable interrupt + */ + enable_irq(dp->irq); +} + +static int hpd_event_thread(void *data) +{ + struct dp_display_private *dp_priv; + unsigned long flag; + struct dp_event *todo; + int timeout_mode = 0; + + dp_priv = (struct dp_display_private *)data; + + while (1) { + if (timeout_mode) { + wait_event_timeout(dp_priv->event_q, + (dp_priv->event_pndx == dp_priv->event_gndx), + EVENT_TIMEOUT); + } else { + wait_event_timeout(dp_priv->event_q, + (dp_priv->event_pndx != dp_priv->event_gndx), + EVENT_TIMEOUT); + } + spin_lock_irqsave(&dp_priv->event_lock, flag); + todo = &dp_priv->event_list[dp_priv->event_gndx]; + if (todo->delay) { + struct dp_event *todo_next; + + dp_priv->event_gndx++; + dp_priv->event_gndx %= DP_EVENT_Q_MAX; + + /* re enter delay event into q */ + todo_next = &dp_priv->event_list[dp_priv->event_pndx++]; + dp_priv->event_pndx %= DP_EVENT_Q_MAX; + todo_next->event_id = todo->event_id; + todo_next->data = todo->data; + todo_next->delay = todo->delay - 1; + + /* clean up older event */ + todo->event_id = EV_NO_EVENT; + todo->delay = 0; + + /* switch to timeout mode */ + timeout_mode = 1; + spin_unlock_irqrestore(&dp_priv->event_lock, flag); + continue; + } + + /* timeout with no events in q */ + if (dp_priv->event_pndx == dp_priv->event_gndx) { + spin_unlock_irqrestore(&dp_priv->event_lock, flag); + continue; + } + + dp_priv->event_gndx++; + dp_priv->event_gndx %= DP_EVENT_Q_MAX; + timeout_mode = 0; + spin_unlock_irqrestore(&dp_priv->event_lock, flag); + + switch (todo->event_id) { + case EV_HPD_INIT_SETUP: + dp_display_config_hpd(dp_priv); + break; + case EV_HPD_PLUG_INT: + dp_hpd_plug_handle(dp_priv, todo->data); + break; + case EV_HPD_UNPLUG_INT: + dp_hpd_unplug_handle(dp_priv, todo->data); + break; + case EV_IRQ_HPD_INT: + dp_irq_hpd_handle(dp_priv, todo->data); + break; + case EV_HPD_REPLUG_INT: + /* do nothing */ + break; + case EV_USER_NOTIFICATION: + dp_display_send_hpd_notification(dp_priv, + todo->data); + break; + case EV_CONNECT_PENDING_TIMEOUT: + dp_connect_pending_timeout(dp_priv, + todo->data); + break; + case EV_DISCONNECT_PENDING_TIMEOUT: + dp_disconnect_pending_timeout(dp_priv, + todo->data); + break; + default: + break; + } + } + + return 0; +} + +static void dp_hpd_event_setup(struct dp_display_private *dp_priv) +{ + init_waitqueue_head(&dp_priv->event_q); + spin_lock_init(&dp_priv->event_lock); + + kthread_run(hpd_event_thread, dp_priv, "dp_hpd_handler"); +} + +static irqreturn_t dp_display_irq_handler(int irq, void *dev_id) +{ + struct dp_display_private *dp = dev_id; + irqreturn_t ret = IRQ_HANDLED; + u32 hpd_isr_status; + + if (!dp) { + DRM_ERROR("invalid data\n"); + return IRQ_NONE; + } + + hpd_isr_status = dp_catalog_hpd_get_intr_status(dp->catalog); + + if (hpd_isr_status & 0x0F) { + /* hpd related interrupts */ + if (hpd_isr_status & DP_DP_HPD_PLUG_INT_MASK || + hpd_isr_status & DP_DP_HPD_REPLUG_INT_MASK) { + dp_add_event(dp, EV_HPD_PLUG_INT, 0, 0); + } + + if (hpd_isr_status & DP_DP_IRQ_HPD_INT_MASK) { + /* delete connect pending event first */ + dp_del_event(dp, EV_CONNECT_PENDING_TIMEOUT); + dp_add_event(dp, EV_IRQ_HPD_INT, 0, 0); + } + + if (hpd_isr_status & DP_DP_HPD_REPLUG_INT_MASK) + dp_add_event(dp, EV_HPD_REPLUG_INT, 0, 0); + + if (hpd_isr_status & DP_DP_HPD_UNPLUG_INT_MASK) + dp_add_event(dp, EV_HPD_UNPLUG_INT, 0, 0); + } + + /* DP controller isr */ + dp_ctrl_isr(dp->ctrl); + + /* DP aux isr */ + dp_aux_isr(dp->aux); + + return ret; +} + +int dp_display_request_irq(struct msm_dp *dp_display) +{ + int rc = 0; + struct dp_display_private *dp; + + if (!dp_display) { + DRM_ERROR("invalid input\n"); + return -EINVAL; + } + + dp = container_of(dp_display, struct dp_display_private, dp_display); + + dp->irq = irq_of_parse_and_map(dp->pdev->dev.of_node, 0); + if (dp->irq < 0) { + rc = dp->irq; + DRM_ERROR("failed to get irq: %d\n", rc); + return rc; + } + + rc = devm_request_irq(&dp->pdev->dev, dp->irq, + dp_display_irq_handler, + IRQF_TRIGGER_HIGH, "dp_display_isr", dp); + if (rc < 0) { + DRM_ERROR("failed to request IRQ%u: %d\n", + dp->irq, rc); + return rc; + } + disable_irq(dp->irq); + + return 0; +} + static int dp_display_probe(struct platform_device *pdev) { int rc = 0; @@ -797,8 +1061,6 @@ static int dp_display_probe(struct platform_device *pdev) if (!dp) return -ENOMEM; - init_completion(&dp->notification_comp); - dp->pdev = pdev; dp->name = "drm_dp"; @@ -810,7 +1072,8 @@ static int dp_display_probe(struct platform_device *pdev) platform_set_drvdata(pdev, dp); - mutex_init(&dp->dp_display.connect_mutex); + mutex_init(&dp->event_mutex); + init_completion(&dp->resume_comp); g_dp_display = &dp->dp_display; rc = component_add(&pdev->dev, &dp_display_comp_ops); @@ -843,6 +1106,16 @@ static int dp_pm_resume(struct device *dev) static int dp_pm_suspend(struct device *dev) { + struct platform_device *pdev = to_platform_device(dev); + struct dp_display_private *dp = platform_get_drvdata(pdev); + + if (!dp) { + DRM_ERROR("DP driver bind failed. Invalid driver data\n"); + return -EINVAL; + } + + atomic_set(&dp->hpd_state, ST_SUSPENDED); + return 0; } @@ -890,26 +1163,6 @@ void __exit msm_dp_unregister(void) platform_driver_unregister(&dp_display_driver); } -static void dp_display_config_hpd_work(struct work_struct *work) -{ - struct dp_display_private *dp; - struct delayed_work *dw = to_delayed_work(work); - - dp = container_of(dw, struct dp_display_private, config_hpd_work); - - dp_display_host_init(dp); - dp_catalog_ctrl_hpd_config(dp->catalog); - - /* set default to 0 */ - atomic_set(&dp->hpd_isr_status, 0); - - /* Enable interrupt first time - * we are leaving dp clocks on during disconnect - * and never disable interrupt - */ - enable_irq(dp->irq); -} - void msm_dp_irq_postinstall(struct msm_dp *dp_display) { struct dp_display_private *dp; @@ -919,8 +1172,9 @@ void msm_dp_irq_postinstall(struct msm_dp *dp_display) dp = container_of(dp_display, struct dp_display_private, dp_display); - INIT_DELAYED_WORK(&dp->config_hpd_work, dp_display_config_hpd_work); - queue_delayed_work(system_wq, &dp->config_hpd_work, HZ * 10); + dp_hpd_event_setup(dp); + + dp_add_event(dp, EV_HPD_INIT_SETUP, 0, 100); } int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, @@ -956,10 +1210,24 @@ int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, return 0; } +static int dp_display_wait4resume_done(struct dp_display_private *dp) +{ + int ret = 0; + + reinit_completion(&dp->resume_comp); + if (!wait_for_completion_timeout(&dp->resume_comp, + WAIT_FOR_RESUME_TIMEOUT_JIFFIES)) { + DRM_ERROR("wait4resume_done timedout\n"); + ret = -ETIMEDOUT; + } + return ret; +} + int msm_dp_display_enable(struct msm_dp *dp, struct drm_encoder *encoder) { int rc = 0; struct dp_display_private *dp_display; + u32 state; dp_display = container_of(dp, struct dp_display_private, dp_display); if (!dp_display->dp_mode.drm_mode.clock) { @@ -967,54 +1235,96 @@ int msm_dp_display_enable(struct msm_dp *dp, struct drm_encoder *encoder) return -EINVAL; } + mutex_lock(&dp_display->event_mutex); + rc = dp_display_set_mode(dp, &dp_display->dp_mode); if (rc) { DRM_ERROR("Failed to perform a mode set, rc=%d\n", rc); + mutex_unlock(&dp_display->event_mutex); return rc; } rc = dp_display_prepare(dp); if (rc) { DRM_ERROR("DP display prepare failed, rc=%d\n", rc); + mutex_unlock(&dp_display->event_mutex); return rc; } - rc = dp_display_enable(dp); - if (rc) { - DRM_ERROR("DP display enable failed, rc=%d\n", rc); - dp_display_unprepare(dp); - return rc; + state = atomic_read(&dp_display->hpd_state); + if (state == ST_SUSPENDED) { + /* start link training */ + dp_add_event(dp_display, EV_HPD_PLUG_INT, 0, 0); + mutex_unlock(&dp_display->event_mutex); + + /* wait until dp interface is up */ + goto resume_done; } + dp_display_enable(dp_display, 0); + rc = dp_display_post_enable(dp); if (rc) { DRM_ERROR("DP display post enable failed, rc=%d\n", rc); - dp_display_disable(dp); + dp_display_disable(dp_display, 0); dp_display_unprepare(dp); } + + dp_del_event(dp_display, EV_CONNECT_PENDING_TIMEOUT); + + if (state == ST_SUSPEND_PENDING) + dp_add_event(dp_display, EV_IRQ_HPD_INT, 0, 0); + + /* completed connection */ + atomic_set(&dp_display->hpd_state, ST_CONNECTED); + + mutex_unlock(&dp_display->event_mutex); + return rc; + +resume_done: + dp_display_wait4resume_done(dp_display); + return rc; +} + +int msm_dp_display_pre_disable(struct msm_dp *dp, struct drm_encoder *encoder) +{ + struct dp_display_private *dp_display; + + dp_display = container_of(dp, struct dp_display_private, dp_display); + + dp_ctrl_push_idle(dp_display->ctrl); + + return 0; } int msm_dp_display_disable(struct msm_dp *dp, struct drm_encoder *encoder) { int rc = 0; + u32 state; + struct dp_display_private *dp_display; - rc = dp_display_pre_disable(dp); - if (rc) { - DRM_ERROR("DP display pre disable failed, rc=%d\n", rc); - return rc; - } + dp_display = container_of(dp, struct dp_display_private, dp_display); - rc = dp_display_disable(dp); - if (rc) { - DRM_ERROR("DP display disable failed, rc=%d\n", rc); - return rc; - } + mutex_lock(&dp_display->event_mutex); + + dp_display_disable(dp_display, 0); rc = dp_display_unprepare(dp); if (rc) DRM_ERROR("DP display unprepare failed, rc=%d\n", rc); + dp_del_event(dp_display, EV_DISCONNECT_PENDING_TIMEOUT); + + state = atomic_read(&dp_display->hpd_state); + if (state == ST_DISCONNECT_PENDING) { + /* completed disconnection */ + atomic_set(&dp_display->hpd_state, ST_DISCONNECTED); + } else { + atomic_set(&dp_display->hpd_state, ST_SUSPEND_PENDING); + } + + mutex_unlock(&dp_display->event_mutex); return rc; } diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index 4c53ed55d1cc..2f2d1279dfc6 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -13,7 +13,6 @@ struct msm_dp { struct drm_connector *connector; struct drm_encoder *encoder; bool is_connected; - struct mutex connect_mutex; u32 max_pclk_khz; u32 max_dp_lanes; }; diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c index e58906f4ae1e..764f4b81017e 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -58,7 +58,6 @@ static int dp_connector_get_modes(struct drm_connector *connector) if (!dp_mode) return 0; - mutex_lock(&dp->connect_mutex); /* pluggable case assumes EDID is read when HPD */ if (dp->is_connected) { /* @@ -71,7 +70,6 @@ static int dp_connector_get_modes(struct drm_connector *connector) if (rc <= 0) { DRM_ERROR("failed to get DP sink modes, rc=%d\n", rc); kfree(dp_mode); - mutex_unlock(&dp->connect_mutex); return rc; } if (dp_mode->drm_mode.clock) { /* valid DP mode */ @@ -83,7 +81,6 @@ static int dp_connector_get_modes(struct drm_connector *connector) drm_mode.hdisplay, drm_mode.vdisplay); kfree(dp_mode); - mutex_unlock(&dp->connect_mutex); return 0; } drm_mode_probed_add(connector, m); @@ -91,7 +88,6 @@ static int dp_connector_get_modes(struct drm_connector *connector) } else { DRM_DEBUG_DP("No sink connected\n"); } - mutex_unlock(&dp->connect_mutex); kfree(dp_mode); return rc; } diff --git a/drivers/gpu/drm/msm/dp/dp_hpd.c b/drivers/gpu/drm/msm/dp/dp_hpd.c index 5b08ce580702..5b8fe32022b5 100644 --- a/drivers/gpu/drm/msm/dp/dp_hpd.c +++ b/drivers/gpu/drm/msm/dp/dp_hpd.c @@ -24,7 +24,7 @@ struct dp_hpd_private { struct dp_usbpd dp_usbpd; }; -static int dp_hpd_connect(struct dp_usbpd *dp_usbpd, bool hpd) +int dp_hpd_connect(struct dp_usbpd *dp_usbpd, bool hpd) { int rc = 0; struct dp_hpd_private *hpd_priv; diff --git a/drivers/gpu/drm/msm/dp/dp_hpd.h b/drivers/gpu/drm/msm/dp/dp_hpd.h index c0178524bec7..5bc5bb64680f 100644 --- a/drivers/gpu/drm/msm/dp/dp_hpd.h +++ b/drivers/gpu/drm/msm/dp/dp_hpd.h @@ -75,5 +75,6 @@ struct dp_usbpd *dp_hpd_get(struct device *dev, struct dp_usbpd_cb *cb); int dp_hpd_register(struct dp_usbpd *dp_usbpd); void dp_hpd_unregister(struct dp_usbpd *dp_usbpd); +int dp_hpd_connect(struct dp_usbpd *dp_usbpd, bool hpd); #endif /* _DP_HPD_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_link.c index 9156a7f3dbf8..3cbae92deff0 100644 --- a/drivers/gpu/drm/msm/dp/dp_link.c +++ b/drivers/gpu/drm/msm/dp/dp_link.c @@ -38,7 +38,6 @@ struct dp_link_private { struct dp_link dp_link; struct dp_link_request request; - struct mutex test_response_mutex; struct mutex psm_mutex; u8 link_status[DP_LINK_STATUS_SIZE]; }; @@ -580,17 +579,18 @@ static int dp_link_parse_phy_test_params(struct dp_link_private *link) return rlen; } - link->dp_link.phy_params.phy_test_pattern_sel = data; + link->dp_link.phy_params.phy_test_pattern_sel = data & 0x07; DRM_DEBUG_DP("phy_test_pattern_sel = 0x%x\n", data); switch (data) { - case DP_LINK_QUAL_PATTERN_DISABLE: - case DP_LINK_QUAL_PATTERN_D10_2: - case DP_LINK_QUAL_PATTERN_ERROR_RATE: - case DP_LINK_QUAL_PATTERN_PRBS7: - case DP_LINK_QUAL_PATTERN_80BIT_CUSTOM: - case DP_LINK_QUAL_PATTERN_HBR2_EYE: + case DP_PHY_TEST_PATTERN_SEL_MASK: + case DP_PHY_TEST_PATTERN_NONE: + case DP_PHY_TEST_PATTERN_D10_2: + case DP_PHY_TEST_PATTERN_ERROR_COUNT: + case DP_PHY_TEST_PATTERN_PRBS7: + case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: + case DP_PHY_TEST_PATTERN_CP2520: return 0; default: return -EINVAL; @@ -661,7 +661,6 @@ static int dp_link_parse_request(struct dp_link_private *link) DRM_DEBUG_DP("Test:(0x%x) requested\n", data); link->request.test_requested = data; - if (link->request.test_requested == DP_TEST_LINK_PHY_TEST_PATTERN) { ret = dp_link_parse_phy_test_params(link); if (ret) @@ -789,10 +788,8 @@ bool dp_link_send_test_response(struct dp_link *dp_link) link = container_of(dp_link, struct dp_link_private, dp_link); - mutex_lock(&link->test_response_mutex); ret = drm_dp_dpcd_writeb(link->aux, DP_TEST_RESPONSE, dp_link->test_response); - mutex_unlock(&link->test_response_mutex); return ret == 1; } @@ -1028,11 +1025,9 @@ int dp_link_process_request(struct dp_link *dp_link) link = container_of(dp_link, struct dp_link_private, dp_link); - mutex_lock(&link->test_response_mutex); dp_link_reset_data(link); dp_link_parse_sink_status_field(link); - mutex_unlock(&link->test_response_mutex); if (link->request.test_requested == DP_TEST_LINK_EDID_READ) { dp_link->sink_request |= DP_TEST_LINK_EDID_READ; @@ -1206,7 +1201,6 @@ struct dp_link *dp_link_get(struct device *dev, struct drm_dp_aux *aux) link->dev = dev; link->aux = aux; - mutex_init(&link->test_response_mutex); mutex_init(&link->psm_mutex); dp_link = &link->dp_link; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index 5ac4b017da8f..7cdf37c525d8 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -8,8 +8,6 @@ #include #include -#define DP_MAX_DS_PORT_COUNT 1 - struct dp_panel_private { struct device *dev; struct dp_panel dp_panel; @@ -23,26 +21,32 @@ struct dp_panel_private { static int dp_panel_read_dpcd(struct dp_panel *dp_panel) { int rc = 0; - size_t rlen; + size_t len; + ssize_t rlen; struct dp_panel_private *panel; struct dp_link_info *link_info; u8 *dpcd, major = 0, minor = 0, temp; - u32 dfp_count = 0, offset = DP_DPCD_REV; + u32 offset = DP_DPCD_REV; dpcd = dp_panel->dpcd; panel = container_of(dp_panel, struct dp_panel_private, dp_panel); link_info = &dp_panel->link_info; - rlen = drm_dp_dpcd_read(panel->aux, - DP_TRAINING_AUX_RD_INTERVAL, &temp, 1); - if (rlen < 0) { - DRM_ERROR("err reading DP_TRAINING_AUX_RD_INTERVAL,rlen=%zd\n", - rlen); - rc = -EINVAL; + rlen = drm_dp_dpcd_read(panel->aux, offset, + dpcd, (DP_RECEIVER_CAP_SIZE + 1)); + if (rlen < (DP_RECEIVER_CAP_SIZE + 1)) { + DRM_ERROR("dpcd read failed, rlen=%zd\n", rlen); + if (rlen == -ETIMEDOUT) + rc = rlen; + else + rc = -EINVAL; + goto end; } + temp = dpcd[DP_TRAINING_AUX_RD_INTERVAL]; + /* check for EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT */ if (temp & BIT(7)) { DRM_DEBUG_DP("using EXTENDED_RECEIVER_CAPABILITY_FIELD\n"); @@ -61,9 +65,6 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel) goto end; } - print_hex_dump(KERN_DEBUG, "[drm-dp] SINK DPCD: ", - DUMP_PREFIX_NONE, 8, 1, dp_panel->dpcd, rlen, false); - link_info->revision = dpcd[DP_DPCD_REV]; major = (link_info->revision >> 4) & 0x0f; minor = link_info->revision & 0x0f; @@ -85,14 +86,23 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel) if (drm_dp_enhanced_frame_cap(dpcd)) link_info->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING; - dfp_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & - DP_DOWN_STREAM_PORT_COUNT; + dp_panel->dfp_present = dpcd[DP_DOWNSTREAMPORT_PRESENT]; + dp_panel->dfp_present &= DP_DWN_STRM_PORT_PRESENT; - if (dfp_count > DP_MAX_DS_PORT_COUNT) { - DRM_ERROR("DS port count %d greater that max (%d) supported\n", - dfp_count, DP_MAX_DS_PORT_COUNT); - return -EINVAL; + if (dp_panel->dfp_present && (dpcd[DP_DPCD_REV] > 0x10)) { + dp_panel->ds_port_cnt = dpcd[DP_DOWN_STREAM_PORT_COUNT]; + dp_panel->ds_port_cnt &= DP_PORT_COUNT_MASK; + len = DP_DOWNSTREAM_PORTS * DP_DOWNSTREAM_CAP_SIZE; + + rlen = drm_dp_dpcd_read(panel->aux, + DP_DOWNSTREAM_PORT_0, dp_panel->ds_cap_info, len); + if (rlen < len) { + DRM_ERROR("ds port status failed, rlen=%zd\n", rlen); + rc = -EINVAL; + goto end; + } } + end: return rc; } @@ -185,6 +195,7 @@ int dp_panel_read_sink_caps(struct dp_panel *dp_panel, struct drm_connector *connector) { int rc = 0, bw_code; + int rlen, count; struct dp_panel_private *panel; if (!dp_panel || !connector) { @@ -202,11 +213,19 @@ int dp_panel_read_sink_caps(struct dp_panel *dp_panel, DRM_ERROR("read dpcd failed %d\n", rc); return rc; } - rc = drm_dp_read_desc(panel->aux, &dp_panel->desc, - drm_dp_is_branch(dp_panel->dpcd)); - if (rc) { - DRM_ERROR("read sink/branch descriptor failed %d\n", rc); - return rc; + + if (dp_panel->dfp_present) { + rlen = drm_dp_dpcd_read(panel->aux, DP_SINK_COUNT, + &count, 1); + if (rlen == 1) { + count = DP_GET_SINK_COUNT(count); + if (!count) { + DRM_ERROR("no downstream ports connected\n"); + panel->link->sink_count = 0; + rc = -ENOTCONN; + goto end; + } + } } kfree(dp_panel->edid); @@ -216,7 +235,12 @@ int dp_panel_read_sink_caps(struct dp_panel *dp_panel, &panel->aux->ddc); if (!dp_panel->edid) { DRM_ERROR("panel edid read failed\n"); - return -EINVAL; + + /* fail safe edid */ + mutex_lock(&connector->dev->mode_config.mutex); + if (drm_add_modes_noedid(connector, 640, 480)) + drm_set_preferred_mode(connector, 640, 480); + mutex_unlock(&connector->dev->mode_config.mutex); } if (panel->aux_cfg_update_done) { @@ -231,8 +255,8 @@ int dp_panel_read_sink_caps(struct dp_panel *dp_panel, } panel->aux_cfg_update_done = false; } - - return 0; +end: + return rc; } u32 dp_panel_get_mode_bpp(struct dp_panel *dp_panel, diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index f6f417eef2e9..9023e5bb4b8b 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -14,8 +14,10 @@ struct edid; -#define DP_MAX_DOWNSTREAM_PORTS 0x10 -#define DPRX_EXTENDED_DPCD_FIELD 0x2200 +#define DPRX_EXTENDED_DPCD_FIELD 0x2200 + +#define DP_DOWNSTREAM_PORTS 4 +#define DP_DOWNSTREAM_CAP_SIZE 4 struct dp_display_mode { struct drm_display_mode drm_mode; @@ -35,6 +37,9 @@ struct dp_panel_in { struct dp_panel { /* dpcd raw data */ u8 dpcd[DP_RECEIVER_CAP_SIZE + 1]; + u8 ds_cap_info[DP_DOWNSTREAM_PORTS * DP_DOWNSTREAM_CAP_SIZE]; + u32 ds_port_cnt; + u32 dfp_present; struct dp_link_info link_info; struct drm_dp_desc desc; diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index 1e480d01ddbb..255a800535d5 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -103,11 +103,12 @@ static inline bool dp_parser_check_prefix(const char *clk_prefix, static int dp_parser_init_clk_data(struct dp_parser *parser) { int num_clk, i, rc; - int core_clk_count = 0, ctrl_clk_count = 0; + int core_clk_count = 0, ctrl_clk_count = 0, stream_clk_count = 0; const char *clk_name; struct device *dev = &parser->pdev->dev; struct dss_module_power *core_power = &parser->mp[DP_CORE_PM]; struct dss_module_power *ctrl_power = &parser->mp[DP_CTRL_PM]; + struct dss_module_power *stream_power = &parser->mp[DP_STREAM_PM]; num_clk = of_property_count_strings(dev->of_node, "clock-names"); if (num_clk <= 0) { @@ -128,7 +129,7 @@ static int dp_parser_init_clk_data(struct dp_parser *parser) ctrl_clk_count++; if (dp_parser_check_prefix("stream", clk_name)) - ctrl_clk_count++; + stream_clk_count++; } /* Initialize the CORE power module */ @@ -159,6 +160,21 @@ static int dp_parser_init_clk_data(struct dp_parser *parser) return -EINVAL; } + /* Initialize the STREAM power module */ + if (stream_clk_count == 0) { + DRM_ERROR("no stream (pixel) clocks are defined\n"); + return -EINVAL; + } + + stream_power->num_clk = stream_clk_count; + stream_power->clk_config = devm_kzalloc(dev, + sizeof(struct dss_clk) * stream_power->num_clk, + GFP_KERNEL); + if (!stream_power->clk_config) { + stream_power->num_clk = 0; + return -EINVAL; + } + return 0; } @@ -166,15 +182,13 @@ static int dp_parser_clock(struct dp_parser *parser) { int rc = 0, i = 0; int num_clk = 0; - int core_clk_index = 0, ctrl_clk_index = 0; - int core_clk_count = 0, ctrl_clk_count = 0; + int core_clk_index = 0, ctrl_clk_index = 0, stream_clk_index = 0; + int core_clk_count = 0, ctrl_clk_count = 0, stream_clk_count = 0; const char *clk_name; struct device *dev = &parser->pdev->dev; struct dss_module_power *core_power = &parser->mp[DP_CORE_PM]; struct dss_module_power *ctrl_power = &parser->mp[DP_CTRL_PM]; - - core_power = &parser->mp[DP_CORE_PM]; - ctrl_power = &parser->mp[DP_CTRL_PM]; + struct dss_module_power *stream_power = &parser->mp[DP_STREAM_PM]; rc = dp_parser_init_clk_data(parser); if (rc) { @@ -184,8 +198,9 @@ static int dp_parser_clock(struct dp_parser *parser) core_clk_count = core_power->num_clk; ctrl_clk_count = ctrl_power->num_clk; + stream_clk_count = stream_power->num_clk; - num_clk = core_clk_count + ctrl_clk_count; + num_clk = core_clk_count + ctrl_clk_count + stream_clk_count; for (i = 0; i < num_clk; i++) { rc = of_property_read_string_index(dev->of_node, "clock-names", @@ -201,14 +216,19 @@ static int dp_parser_clock(struct dp_parser *parser) strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name)); clk->type = DSS_CLK_AHB; core_clk_index++; - } else if ((dp_parser_check_prefix("ctrl", clk_name) || - dp_parser_check_prefix("stream", clk_name)) && + } else if (dp_parser_check_prefix("stream", clk_name) && + stream_clk_index < stream_clk_count) { + struct dss_clk *clk = + &stream_power->clk_config[stream_clk_index]; + strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name)); + clk->type = DSS_CLK_PCLK; + stream_clk_index++; + } else if (dp_parser_check_prefix("ctrl", clk_name) && ctrl_clk_index < ctrl_clk_count) { struct dss_clk *clk = &ctrl_power->clk_config[ctrl_clk_index]; strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name)); ctrl_clk_index++; - if (dp_parser_check_prefix("ctrl_link", clk_name) || dp_parser_check_prefix("stream_pixel", clk_name)) clk->type = DSS_CLK_PCLK; diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h index aa0380b6a280..841e776124c4 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.h +++ b/drivers/gpu/drm/msm/dp/dp_parser.h @@ -19,6 +19,7 @@ enum dp_pm_type { DP_CORE_PM, DP_CTRL_PM, + DP_STREAM_PM, DP_PHY_PM, DP_MAX_PM }; @@ -33,6 +34,7 @@ static inline const char *dp_parser_pm_name(enum dp_pm_type module) switch (module) { case DP_CORE_PM: return "DP_CORE_PM"; case DP_CTRL_PM: return "DP_CTRL_PM"; + case DP_STREAM_PM: return "DP_STREAM_PM"; case DP_PHY_PM: return "DP_PHY_PM"; default: return "???"; } diff --git a/drivers/gpu/drm/msm/dp/dp_power.c b/drivers/gpu/drm/msm/dp/dp_power.c index 8b0a276d34a4..34fdb2e5d644 100644 --- a/drivers/gpu/drm/msm/dp/dp_power.c +++ b/drivers/gpu/drm/msm/dp/dp_power.c @@ -95,11 +95,12 @@ static int dp_power_regulator_init(struct dp_power_private *power) static int dp_power_clk_init(struct dp_power_private *power) { int rc = 0; - struct dss_module_power *core, *ctrl; + struct dss_module_power *core, *ctrl, *stream; struct device *dev = &power->pdev->dev; core = &power->parser->mp[DP_CORE_PM]; ctrl = &power->parser->mp[DP_CTRL_PM]; + stream = &power->parser->mp[DP_STREAM_PM]; if (power->parser->pll && power->parser->pll->get_provider) { rc = power->parser->pll->get_provider(power->parser->pll, @@ -126,21 +127,33 @@ static int dp_power_clk_init(struct dp_power_private *power) return -ENODEV; } + rc = msm_dss_get_clk(dev, stream->clk_config, stream->num_clk); + if (rc) { + DRM_ERROR("failed to get %s clk. err=%d\n", + dp_parser_pm_name(DP_CTRL_PM), rc); + msm_dss_put_clk(core->clk_config, core->num_clk); + return -ENODEV; + } + return 0; } static int dp_power_clk_deinit(struct dp_power_private *power) { - struct dss_module_power *core, *ctrl; + struct dss_module_power *core, *ctrl, *stream; core = &power->parser->mp[DP_CORE_PM]; ctrl = &power->parser->mp[DP_CTRL_PM]; + stream = &power->parser->mp[DP_STREAM_PM]; - if (!core || !ctrl) + if (!core || !ctrl || !stream) { + DRM_ERROR("invalid power_data\n"); return -EINVAL; + } msm_dss_put_clk(ctrl->clk_config, ctrl->num_clk); msm_dss_put_clk(core->clk_config, core->num_clk); + msm_dss_put_clk(stream->clk_config, stream->num_clk); return 0; } @@ -167,6 +180,20 @@ static int dp_power_clk_set_rate(struct dp_power_private *power, return 0; } +int dp_power_clk_status(struct dp_power *dp_power, enum dp_pm_type pm_type) +{ + if (pm_type == DP_CORE_PM) + return dp_power->core_clks_on; + + if (pm_type == DP_CTRL_PM) + return dp_power->link_clks_on; + + if (pm_type == DP_STREAM_PM) + return dp_power->stream_clks_on; + + return 0; +} + int dp_power_clk_enable(struct dp_power *dp_power, enum dp_pm_type pm_type, bool enable) { @@ -175,7 +202,8 @@ int dp_power_clk_enable(struct dp_power *dp_power, power = container_of(dp_power, struct dp_power_private, dp_power); - if (pm_type != DP_CORE_PM && pm_type != DP_CTRL_PM) { + if (pm_type != DP_CORE_PM && pm_type != DP_CTRL_PM && + pm_type != DP_STREAM_PM) { DRM_ERROR("unsupported power module: %s\n", dp_parser_pm_name(pm_type)); return -EINVAL; @@ -192,6 +220,11 @@ int dp_power_clk_enable(struct dp_power *dp_power, return 0; } + if (pm_type == DP_STREAM_PM && dp_power->stream_clks_on) { + DRM_DEBUG_DP("pixel clks already enabled\n"); + return 0; + } + if ((pm_type == DP_CTRL_PM) && (!dp_power->core_clks_on)) { DRM_DEBUG_DP("Enable core clks before link clks\n"); @@ -215,13 +248,16 @@ int dp_power_clk_enable(struct dp_power *dp_power, if (pm_type == DP_CORE_PM) dp_power->core_clks_on = enable; + else if (pm_type == DP_STREAM_PM) + dp_power->stream_clks_on = enable; else dp_power->link_clks_on = enable; DRM_DEBUG_DP("%s clocks for %s\n", enable ? "enable" : "disable", dp_parser_pm_name(pm_type)); - DRM_DEBUG_DP("link_clks:%s core_clks:%s\n", + DRM_DEBUG_DP("strem_clks:%s link_clks:%s core_clks:%s\n", + dp_power->stream_clks_on ? "on" : "off", dp_power->link_clks_on ? "on" : "off", dp_power->core_clks_on ? "on" : "off"); diff --git a/drivers/gpu/drm/msm/dp/dp_power.h b/drivers/gpu/drm/msm/dp/dp_power.h index 756341e290ed..5333a97d5c35 100644 --- a/drivers/gpu/drm/msm/dp/dp_power.h +++ b/drivers/gpu/drm/msm/dp/dp_power.h @@ -19,6 +19,7 @@ struct dp_power { bool core_clks_on; bool link_clks_on; + bool stream_clks_on; }; /** @@ -43,6 +44,18 @@ int dp_power_init(struct dp_power *power, bool flip); */ int dp_power_deinit(struct dp_power *power); +/** + * dp_power_clk_status() - display controller clocks status + * + * @power: instance of power module + * @pm_type: type of pm, core/ctrl/phy + * return: status of power clocks + * + * This API return status of DP clocks + */ + +int dp_power_clk_status(struct dp_power *dp_power, enum dp_pm_type pm_type); + /** * dp_power_clk_enable() - enable display controller clocks * diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h index 721c0cc69296..de32f6204a50 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -101,6 +101,7 @@ #define REG_DP_MAINLINK_CTRL (0x00000000) #define DP_MAINLINK_CTRL_ENABLE (0x00000001) #define DP_MAINLINK_CTRL_RESET (0x00000002) +#define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER (0x00000010) #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000) #define REG_DP_STATE_CTRL (0x00000004) diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index f898a4121ce9..4dbdf5b0f5f7 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -392,6 +392,7 @@ int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, struct drm_encoder *encoder); int msm_dp_display_enable(struct msm_dp *dp, struct drm_encoder *encoder); int msm_dp_display_disable(struct msm_dp *dp, struct drm_encoder *encoder); +int msm_dp_display_pre_disable(struct msm_dp *dp, struct drm_encoder *encoder); void msm_dp_display_mode_set(struct msm_dp *dp, struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode); -- cgit v1.2.3 From 937f941ca06f2f3ab64baebf31be2c16d57ae7b8 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 9 Sep 2020 17:49:02 -0700 Subject: drm/msm/dp: Use qmp phy for DP PLL and PHY Make the necessary changes to the DP driver to use the qmp phy from the common phy framework instead of rolling our own in the drm subsystem. This also removes the PLL code and adds proper includes so things build. Cc: Jeykumar Sankaran Cc: Chandan Uddaraju Cc: Vara Reddy Cc: Tanmay Shah Cc: Bjorn Andersson Cc: Manu Gautam Cc: Sandeep Maheswaram Cc: Douglas Anderson Cc: Sean Paul Cc: Jonathan Marek Cc: Dmitry Baryshkov Cc: Rob Clark Signed-off-by: Stephen Boyd Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/Makefile | 2 - drivers/gpu/drm/msm/dp/dp_aux.c | 7 +- drivers/gpu/drm/msm/dp/dp_catalog.c | 287 +--------- drivers/gpu/drm/msm/dp/dp_catalog.h | 9 +- drivers/gpu/drm/msm/dp/dp_ctrl.c | 48 +- drivers/gpu/drm/msm/dp/dp_display.c | 17 - drivers/gpu/drm/msm/dp/dp_display.h | 3 - drivers/gpu/drm/msm/dp/dp_link.c | 2 + drivers/gpu/drm/msm/dp/dp_panel.c | 1 + drivers/gpu/drm/msm/dp/dp_parser.c | 12 +- drivers/gpu/drm/msm/dp/dp_parser.h | 12 +- drivers/gpu/drm/msm/dp/dp_pll.c | 99 ---- drivers/gpu/drm/msm/dp/dp_pll.h | 61 --- drivers/gpu/drm/msm/dp/dp_pll_10nm.c | 930 -------------------------------- drivers/gpu/drm/msm/dp/dp_pll_private.h | 89 --- drivers/gpu/drm/msm/dp/dp_power.c | 39 +- drivers/gpu/drm/msm/dp/dp_power.h | 9 - drivers/gpu/drm/msm/dp/dp_reg.h | 213 -------- 18 files changed, 78 insertions(+), 1762 deletions(-) delete mode 100644 drivers/gpu/drm/msm/dp/dp_pll.c delete mode 100644 drivers/gpu/drm/msm/dp/dp_pll.h delete mode 100644 drivers/gpu/drm/msm/dp/dp_pll_10nm.c delete mode 100644 drivers/gpu/drm/msm/dp/dp_pll_private.h (limited to 'drivers/gpu/drm/msm/dp/dp_ctrl.c') diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 99658a6bf698..340682cd0f32 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -111,8 +111,6 @@ msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \ dp/dp_panel.o \ dp/dp_parser.o \ dp/dp_power.o \ - dp/dp_pll.o \ - dp/dp_pll_10nm.o \ dp/dp_audio.o msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o diff --git a/drivers/gpu/drm/msm/dp/dp_aux.c b/drivers/gpu/drm/msm/dp/dp_aux.c index d742b4d870b3..19b35ae3e927 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.c +++ b/drivers/gpu/drm/msm/dp/dp_aux.c @@ -4,6 +4,7 @@ */ #include +#include #include "dp_reg.h" #include "dp_aux.h" @@ -380,8 +381,7 @@ static ssize_t dp_aux_transfer(struct drm_dp_aux *dp_aux, if (aux->native) { aux->retry_cnt++; if (!(aux->retry_cnt % retry_count)) - dp_catalog_aux_update_cfg(aux->catalog, - PHY_AUX_CFG1); + dp_catalog_aux_update_cfg(aux->catalog); dp_catalog_aux_reset(aux->catalog); } usleep_range(400, 500); /* at least 400us to next try */ @@ -438,7 +438,7 @@ void dp_aux_reconfig(struct drm_dp_aux *dp_aux) aux = container_of(dp_aux, struct dp_aux_private, dp_aux); - dp_catalog_aux_update_cfg(aux->catalog, PHY_AUX_CFG1); + dp_catalog_aux_update_cfg(aux->catalog); dp_catalog_aux_reset(aux->catalog); } @@ -453,7 +453,6 @@ void dp_aux_init(struct drm_dp_aux *dp_aux) aux = container_of(dp_aux, struct dp_aux_private, dp_aux); - dp_catalog_aux_setup(aux->catalog); dp_catalog_aux_enable(aux->catalog, true); aux->retry_cnt = 0; } diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index 393e3d443139..b15b4ce4ba35 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -8,8 +8,11 @@ #include #include #include +#include +#include #include #include +#include #include "dp_catalog.h" #include "dp_reg.h" @@ -52,41 +55,6 @@ #define DP_INTERRUPT_STATUS2_MASK \ (DP_INTERRUPT_STATUS2 << DP_INTERRUPT_STATUS_MASK_SHIFT) -static u8 const vm_pre_emphasis_hbr_rbr[4][4] = { - {0x00, 0x0C, 0x14, 0x19}, - {0x00, 0x0B, 0x12, 0xFF}, - {0x00, 0x0B, 0xFF, 0xFF}, - {0x04, 0xFF, 0xFF, 0xFF} -}; - -static u8 const vm_voltage_swing_hbr_rbr[4][4] = { - {0x08, 0x0F, 0x16, 0x1F}, - {0x11, 0x1E, 0x1F, 0xFF}, - {0x19, 0x1F, 0xFF, 0xFF}, - {0x1F, 0xFF, 0xFF, 0xFF} -}; - -/* AUX look-up-table configurations - * Pair of offset and config values for each LUT - */ -static u8 const aux_lut_offset[] = { - 0x20, 0x24, 0x28, 0x2C, 0x30, 0x34, 0x38, 0x3C, 0x40, 0x44 -}; - -static u8 const -aux_lut_value[PHY_AUX_CFG_MAX][DP_AUX_CFG_MAX_VALUE_CNT] = { - { 0x00, 0x00, 0x00, }, - { 0x13, 0x23, 0x1d, }, - { 0x24, 0x00, 0x00, }, - { 0x00, 0x00, 0x00, }, - { 0x0A, 0x00, 0x00, }, - { 0x26, 0x00, 0x00, }, - { 0x0A, 0x00, 0x00, }, - { 0x03, 0x00, 0x00, }, - { 0xBB, 0x00, 0x00, }, - { 0x03, 0x00, 0x00, } -}; - struct dp_catalog_private { struct device *dev; struct dp_io *io; @@ -129,83 +97,6 @@ static inline void dp_write_ahb(struct dp_catalog_private *catalog, writel(data, catalog->io->dp_controller.base + offset); } -static inline void dp_write_phy(struct dp_catalog_private *catalog, - u32 offset, u32 data) -{ - offset += DP_PHY_REG_OFFSET; - /* - * To make sure phy reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() - */ - writel(data, catalog->io->phy_reg.base + offset); -} - -static inline u32 dp_read_phy(struct dp_catalog_private *catalog, - u32 offset) -{ - offset += DP_PHY_REG_OFFSET; - /* - * To make sure phy reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() - */ - return readl_relaxed(catalog->io->phy_reg.base + offset); -} - -static inline void dp_write_pll(struct dp_catalog_private *catalog, - u32 offset, u32 data) -{ - offset += DP_PHY_PLL_OFFSET; - writel_relaxed(data, catalog->io->phy_reg.base + offset); -} - -static inline void dp_write_ln_tx0(struct dp_catalog_private *catalog, - u32 offset, u32 data) -{ - offset += DP_PHY_LN_TX0_OFFSET; - writel_relaxed(data, catalog->io->phy_reg.base + offset); -} - -static inline void dp_write_ln_tx1(struct dp_catalog_private *catalog, - u32 offset, u32 data) -{ - offset += DP_PHY_LN_TX1_OFFSET; - writel_relaxed(data, catalog->io->phy_reg.base + offset); -} - -static inline u32 dp_read_ln_tx0(struct dp_catalog_private *catalog, - u32 offset) -{ - offset += DP_PHY_LN_TX0_OFFSET; - return readl_relaxed(catalog->io->phy_reg.base + offset); -} - -static inline u32 dp_read_ln_tx1(struct dp_catalog_private *catalog, - u32 offset) -{ - offset += DP_PHY_LN_TX1_OFFSET; - return readl_relaxed(catalog->io->phy_reg.base + offset); -} - -static inline void dp_write_usb_cm(struct dp_catalog_private *catalog, - u32 offset, u32 data) -{ - /* - * To make sure usb reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() - */ - writel(data, catalog->io->usb3_dp_com.base + offset); -} - -static inline u32 dp_read_usb_cm(struct dp_catalog_private *catalog, - u32 offset) -{ - /* - * To make sure usb reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() - */ - return readl_relaxed(catalog->io->usb3_dp_com.base + offset); -} - static inline void dp_write_p0(struct dp_catalog_private *catalog, u32 offset, u32 data) { @@ -335,27 +226,14 @@ void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable) dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl); } -void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog, - enum dp_phy_aux_config_type type) +void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog) { struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); - u32 new_index = 0, current_index = 0; + struct dp_io *dp_io = catalog->io; + struct phy *phy = dp_io->phy; - if (type >= PHY_AUX_CFG_MAX) { - DRM_ERROR("invalid input\n"); - return; - } - - current_index = catalog->aux_lut_cfg_index[type]; - new_index = (current_index + 1) % DP_AUX_CFG_MAX_VALUE_CNT; - DRM_DEBUG_DP("Updating PHY_AUX_CFG%d from 0x%08x to 0x%08x\n", - type, aux_lut_value[type][current_index], - aux_lut_value[type][new_index]); - - dp_write_phy(catalog, aux_lut_offset[type], - aux_lut_value[type][new_index]); - catalog->aux_lut_cfg_index[type] = new_index; + phy_calibrate(phy); } static void dump_regs(void __iomem *base, int len) @@ -401,64 +279,6 @@ void dp_catalog_dump_regs(struct dp_catalog *dp_catalog) offset = MSM_DP_CONTROLLER_P0_OFFSET; len = MSM_DP_CONTROLLER_P0_SIZE; dump_regs(catalog->io->dp_controller.base + offset, len); - - pr_info("USB3 DP COM regs\n"); - dump_regs(catalog->io->usb3_dp_com.base, catalog->io->usb3_dp_com.len); - - pr_info("LN TX0 regs\n"); - dump_regs(catalog->io->phy_reg.base + DP_PHY_LN_TX0_OFFSET, - DP_PHY_LN_TX0_SIZE); - - pr_info("LN TX1 regs\n"); - dump_regs(catalog->io->phy_reg.base + DP_PHY_LN_TX1_OFFSET, - DP_PHY_LN_TX1_SIZE); - - pr_info("DP PHY regs\n"); - dump_regs(catalog->io->phy_reg.base + DP_PHY_REG_OFFSET, - DP_PHY_REG_SIZE); -} - -void dp_catalog_aux_setup(struct dp_catalog *dp_catalog) -{ - struct dp_catalog_private *catalog = container_of(dp_catalog, - struct dp_catalog_private, dp_catalog); - int i = 0; - - dp_write_phy(catalog, REG_DP_PHY_PD_CTL, DP_PHY_PD_CTL_PWRDN | - DP_PHY_PD_CTL_AUX_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | - DP_PHY_PD_CTL_DP_CLAMP_EN); - - /* Turn on BIAS current for PHY/PLL */ - dp_write_pll(catalog, - QSERDES_COM_BIAS_EN_CLKBUFLR_EN, QSERDES_COM_BIAS_EN | - QSERDES_COM_BIAS_EN_MUX | QSERDES_COM_CLKBUF_L_EN | - QSERDES_COM_EN_SYSCLK_TX_SEL); - - dp_write_phy(catalog, REG_DP_PHY_PD_CTL, DP_PHY_PD_CTL_PSR_PWRDN); - - dp_write_phy(catalog, REG_DP_PHY_PD_CTL, DP_PHY_PD_CTL_PWRDN | - DP_PHY_PD_CTL_AUX_PWRDN | DP_PHY_PD_CTL_LANE_0_1_PWRDN - | DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN - | DP_PHY_PD_CTL_DP_CLAMP_EN); - - dp_write_pll(catalog, - QSERDES_COM_BIAS_EN_CLKBUFLR_EN, QSERDES_COM_BIAS_EN | - QSERDES_COM_BIAS_EN_MUX | QSERDES_COM_CLKBUF_R_EN | - QSERDES_COM_CLKBUF_L_EN | QSERDES_COM_EN_SYSCLK_TX_SEL | - QSERDES_COM_CLKBUF_RX_DRIVE_L); - - /* DP AUX CFG register programming */ - for (i = 0; i < PHY_AUX_CFG_MAX; i++) { - DRM_DEBUG_DP("PHY_AUX_CFG%ds: offset=0x%08x, value=0x%08x\n", - i, aux_lut_offset[i], aux_lut_value[i][0]); - dp_write_phy(catalog, aux_lut_offset[i], - aux_lut_value[i][0]); - } - - dp_write_phy(catalog, REG_DP_PHY_AUX_INTERRUPT_MASK, - PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | - PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | - PHY_AUX_REQ_ERR_MASK); } int dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog) @@ -585,7 +405,7 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, bool fixed_nvid) { u32 pixel_m, pixel_n; - u32 mvid, nvid, div, pixel_div = 0, dispcc_input_rate; + u32 mvid, nvid, pixel_div = 0, dispcc_input_rate; u32 const nvid_fixed = DP_LINK_CONSTANT_N_VALUE; u32 const link_rate_hbr2 = 540000; u32 const link_rate_hbr3 = 810000; @@ -594,14 +414,11 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); - div = dp_read_phy(catalog, REG_DP_PHY_VCO_DIV); - div &= 0x03; - - if (div == 0) + if (rate == link_rate_hbr3) pixel_div = 6; - else if (div == 1) + else if (rate == 1620000 || rate == 270000) pixel_div = 2; - else if (div == 2) + else if (rate == link_rate_hbr2) pixel_div = 4; else DRM_ERROR("Invalid pixel mux divider\n"); @@ -667,36 +484,6 @@ int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog, return 0; } -void dp_catalog_ctrl_usb_reset(struct dp_catalog *dp_catalog, bool flip) -{ - struct dp_catalog_private *catalog = container_of(dp_catalog, - struct dp_catalog_private, dp_catalog); - u32 typec_ctrl; - - dp_write_usb_cm(catalog, REG_USB3_DP_COM_RESET_OVRD_CTRL, - USB3_DP_COM_OVRD_CTRL_SW_DPPHY_RESET_MUX | - USB3_DP_COM_OVRD_CTRL_SW_USB3PHY_RESET_MUX); - dp_write_usb_cm(catalog, REG_USB3_DP_COM_PHY_MODE_CTRL, - USB3_DP_COM_PHY_MODE_DP); - dp_write_usb_cm(catalog, REG_USB3_DP_COM_SW_RESET, - USB3_DP_COM_SW_RESET_SET); - - /* Default configuration i.e CC1 */ - typec_ctrl = USB3_DP_COM_TYPEC_CTRL_PORTSEL_MUX; - if (flip) - typec_ctrl |= USB3_DP_COM_TYPEC_CTRL_PORTSEL; - - dp_write_usb_cm(catalog, REG_USB3_DP_COM_TYPEC_CTRL, typec_ctrl); - - dp_write_usb_cm(catalog, REG_USB3_DP_COM_SWI_CTRL, 0x00); - dp_write_usb_cm(catalog, REG_USB3_DP_COM_SW_RESET, 0x00); - - dp_write_usb_cm(catalog, REG_USB3_DP_COM_POWER_DOWN_CTRL, - USB3_DP_COM_POWER_DOWN_CTRL_SW_PWRDN); - dp_write_usb_cm(catalog, REG_USB3_DP_COM_RESET_OVRD_CTRL, 0x00); - -} - void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog) { u32 sw_reset; @@ -820,58 +607,26 @@ void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog) struct dp_catalog_private, dp_catalog); dp_write_ahb(catalog, REG_DP_PHY_CTRL, - DP_PHY_CTRL_SW_RESET_PLL | DP_PHY_CTRL_SW_RESET); + DP_PHY_CTRL_SW_RESET | DP_PHY_CTRL_SW_RESET_PLL); usleep_range(1000, 1100); /* h/w recommended delay */ dp_write_ahb(catalog, REG_DP_PHY_CTRL, 0x0); } -void dp_catalog_ctrl_phy_lane_cfg(struct dp_catalog *dp_catalog, - bool flipped, u8 ln_cnt) -{ - u32 info; - struct dp_catalog_private *catalog = container_of(dp_catalog, - struct dp_catalog_private, dp_catalog); - u8 orientation = BIT(!!flipped); - - info = ln_cnt & DP_PHY_SPARE0_MASK; - info |= (orientation & DP_PHY_SPARE0_MASK) - << DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT; - DRM_DEBUG_DP("Shared Info = 0x%x\n", info); - - dp_write_phy(catalog, REG_DP_PHY_SPARE0, info); -} - int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog, u8 v_level, u8 p_level) { struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); - u8 voltage_swing_cfg, pre_emphasis_cfg; - - DRM_DEBUG_DP("hw: v=%d p=%d\n", v_level, p_level); - - voltage_swing_cfg = vm_voltage_swing_hbr_rbr[v_level][p_level]; - pre_emphasis_cfg = vm_pre_emphasis_hbr_rbr[v_level][p_level]; - - if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) { - DRM_ERROR("invalid vx (0x%x=0x%x), px (0x%x=0x%x\n", - v_level, voltage_swing_cfg, p_level, pre_emphasis_cfg); - return -EINVAL; - } + struct dp_io *dp_io = catalog->io; + struct phy *phy = dp_io->phy; + struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; - /* Enable MUX to use Cursor values from these registers */ - voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; - pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; - - /* Configure host and panel only if both values are allowed */ - dp_write_ln_tx0(catalog, REG_DP_PHY_TXn_TX_DRV_LVL, voltage_swing_cfg); - dp_write_ln_tx1(catalog, REG_DP_PHY_TXn_TX_DRV_LVL, voltage_swing_cfg); - dp_write_ln_tx0(catalog, REG_DP_PHY_TXn_TX_EMP_POST1_LVL, - pre_emphasis_cfg); - dp_write_ln_tx1(catalog, REG_DP_PHY_TXn_TX_EMP_POST1_LVL, - pre_emphasis_cfg); - DRM_DEBUG_DP("hw: vx_value=0x%x px_value=0x%x\n", - voltage_swing_cfg, pre_emphasis_cfg); + /* TODO: Update for all lanes instead of just first one */ + opts_dp->voltage[0] = v_level; + opts_dp->pre[0] = p_level; + opts_dp->set_voltages = 1; + phy_configure(phy, &dp_io->phy_opts); + opts_dp->set_voltages = 0; return 0; } diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h index edb68a65b0fa..4b7666f1fe6f 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -6,6 +6,8 @@ #ifndef _DP_CATALOG_H_ #define _DP_CATALOG_H_ +#include + #include "dp_parser.h" /* interrupts */ @@ -77,9 +79,7 @@ int dp_catalog_aux_clear_trans(struct dp_catalog *dp_catalog, bool read); int dp_catalog_aux_clear_hw_interrupts(struct dp_catalog *dp_catalog); void dp_catalog_aux_reset(struct dp_catalog *dp_catalog); void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable); -void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog, - enum dp_phy_aux_config_type type); -void dp_catalog_aux_setup(struct dp_catalog *dp_catalog); +void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog); int dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog); /* DP Controller APIs */ @@ -92,7 +92,6 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate, u32 stream_rate_khz, bool fixed_nvid); int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog, u32 pattern); void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog); -void dp_catalog_ctrl_usb_reset(struct dp_catalog *dp_catalog, bool flip); bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_enable_irq(struct dp_catalog *dp_catalog, bool enable); void dp_catalog_hpd_config_intr(struct dp_catalog *dp_catalog, @@ -100,8 +99,6 @@ void dp_catalog_hpd_config_intr(struct dp_catalog *dp_catalog, void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog); u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog); -void dp_catalog_ctrl_phy_lane_cfg(struct dp_catalog *dp_catalog, bool flipped, - u8 lane_cnt); int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog, u8 v_level, u8 p_level); int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 70b0e06953f6..2e3e1917351f 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -8,8 +8,11 @@ #include #include #include +#include +#include #include #include +#include #include "dp_reg.h" #include "dp_ctrl.h" @@ -1302,7 +1305,7 @@ static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl, } static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl, - enum dp_pm_type module, char *name, u32 rate) + enum dp_pm_type module, char *name, unsigned long rate) { u32 num = ctrl->parser->mp[module].num_clk; struct dss_clk *cfg = ctrl->parser->mp[module].clk_config; @@ -1312,23 +1315,29 @@ static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl, cfg++; } - DRM_DEBUG_DP("setting rate=%d on clk=%s\n", rate, name); + DRM_DEBUG_DP("setting rate=%lu on clk=%s\n", rate, name); if (num) cfg->rate = rate; else - DRM_ERROR("%s clock doesn't exit to set rate %d\n", + DRM_ERROR("%s clock doesn't exit to set rate %lu\n", name, rate); } static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) { int ret = 0; + struct dp_io *dp_io = &ctrl->parser->io; + struct phy *phy = dp_io->phy; + struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; - dp_power_set_link_clk_parent(ctrl->power); - + opts_dp->lanes = ctrl->link->link_params.num_lanes; + opts_dp->link_rate = ctrl->link->link_params.rate / 100; dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link", - ctrl->link->link_params.rate); + ctrl->link->link_params.rate * 1000); + + phy_configure(phy, &dp_io->phy_opts); + phy_power_on(phy); ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true); if (ret) @@ -1345,7 +1354,7 @@ static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl) int ret = 0; dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", - ctrl->dp_ctrl.pixel_rate); + ctrl->dp_ctrl.pixel_rate * 1000); ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true); if (ret) @@ -1360,6 +1369,8 @@ static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl) int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip) { struct dp_ctrl_private *ctrl; + struct dp_io *dp_io; + struct phy *phy; if (!dp_ctrl) { DRM_ERROR("Invalid input data\n"); @@ -1367,11 +1378,13 @@ int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip) } ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); + dp_io = &ctrl->parser->io; + phy = dp_io->phy; ctrl->dp_ctrl.orientation = flip; - dp_catalog_ctrl_usb_reset(ctrl->catalog, flip); dp_catalog_ctrl_phy_reset(ctrl->catalog); + phy_init(phy); dp_catalog_ctrl_enable_irq(ctrl->catalog, true); return 0; @@ -1420,10 +1433,13 @@ static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl) static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl) { int ret = 0; + struct dp_io *dp_io = &ctrl->parser->io; + struct phy *phy = dp_io->phy; + struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); - dp_catalog_ctrl_phy_lane_cfg(ctrl->catalog, - ctrl->dp_ctrl.orientation, ctrl->link->link_params.num_lanes); + opts_dp->lanes = ctrl->link->link_params.num_lanes; + phy_configure(phy, &dp_io->phy_opts); /* * Disable and re-enable the mainlink clock since the * link clock might have been adjusted as part of the @@ -1434,6 +1450,7 @@ static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl) DRM_ERROR("Failed to disable clocks. ret=%d\n", ret); return ret; } + phy_power_off(phy); /* hw recommended delay before re-enabling clocks */ msleep(20); @@ -1622,10 +1639,6 @@ int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl) ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate); - dp_catalog_ctrl_phy_lane_cfg(ctrl->catalog, - ctrl->dp_ctrl.orientation, - ctrl->link->link_params.num_lanes); - rc = dp_ctrl_enable_mainlink_clocks(ctrl); if (rc) return rc; @@ -1763,12 +1776,16 @@ end: int dp_ctrl_off(struct dp_ctrl *dp_ctrl) { struct dp_ctrl_private *ctrl; + struct dp_io *dp_io; + struct phy *phy; int ret = 0; if (!dp_ctrl) return -EINVAL; ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); + dp_io = &ctrl->parser->io; + phy = dp_io->phy; dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); @@ -1783,6 +1800,9 @@ int dp_ctrl_off(struct dp_ctrl *dp_ctrl) DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); } + phy_power_off(phy); + phy_exit(phy); + DRM_DEBUG_DP("DP off done\n"); return ret; } diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 94b05e4a2574..05a97e097edf 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -24,7 +24,6 @@ #include "dp_ctrl.h" #include "dp_display.h" #include "dp_drm.h" -#include "dp_pll.h" #include "dp_audio.h" #include "dp_debug.h" @@ -91,7 +90,6 @@ struct dp_display_private { struct dp_usbpd *usbpd; struct dp_parser *parser; - struct msm_dp_pll *pll; struct dp_power *power; struct dp_catalog *catalog; struct drm_dp_aux *aux; @@ -659,7 +657,6 @@ static void dp_display_deinit_sub_modules(struct dp_display_private *dp) dp_ctrl_put(dp->ctrl); dp_panel_put(dp->panel); dp_aux_put(dp->aux); - dp_pll_put(dp->pll); dp_audio_put(dp->audio); } @@ -671,9 +668,6 @@ static int dp_init_sub_modules(struct dp_display_private *dp) struct dp_panel_in panel_in = { .dev = dev, }; - struct dp_pll_in pll_in = { - .pdev = dp->pdev, - }; /* Callback APIs used for cable status change event */ cb->configure = dp_display_usbpd_configure_cb; @@ -704,17 +698,6 @@ static int dp_init_sub_modules(struct dp_display_private *dp) goto error; } - pll_in.parser = dp->parser; - dp->pll = dp_pll_get(&pll_in); - if (IS_ERR_OR_NULL(dp->pll)) { - rc = -EINVAL; - DRM_ERROR("failed to initialize pll, rc = %d\n", rc); - dp->pll = NULL; - goto error; - } - - dp->parser->pll = dp->pll; - dp->power = dp_power_get(dp->parser); if (IS_ERR(dp->power)) { rc = PTR_ERR(dp->power); diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index 8b78b40bbd6c..6092ba1ed85e 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -36,7 +36,4 @@ bool dp_display_check_video_test(struct msm_dp *dp_display); int dp_display_get_test_bpp(struct msm_dp *dp_display); void dp_display_signal_audio_complete(struct msm_dp *dp_display); -void __init msm_dp_pll_driver_register(void); -void __exit msm_dp_pll_driver_unregister(void); - #endif /* _DP_DISPLAY_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_link.c index ac0e1daea913..c811da515fb3 100644 --- a/drivers/gpu/drm/msm/dp/dp_link.c +++ b/drivers/gpu/drm/msm/dp/dp_link.c @@ -5,6 +5,8 @@ #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__ +#include + #include "dp_link.h" #include "dp_panel.h" diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index 4e5af59db6ba..18cec4fc5e0b 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -7,6 +7,7 @@ #include #include +#include struct dp_panel_private { struct device *dev; diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index 255a800535d5..0519dd3ac3c3 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -4,6 +4,9 @@ */ #include +#include + +#include #include "dp_parser.h" #include "dp_reg.h" @@ -53,8 +56,6 @@ static void dp_parser_unmap_io_resources(struct dp_parser *parser) struct dp_io *io = &parser->io; msm_dss_iounmap(&io->dp_controller); - msm_dss_iounmap(&io->phy_reg); - msm_dss_iounmap(&io->usb3_dp_com); } static int dp_parser_ctrl_res(struct dp_parser *parser) @@ -69,6 +70,12 @@ static int dp_parser_ctrl_res(struct dp_parser *parser) goto err; } + io->phy = devm_phy_get(&pdev->dev, "dp"); + if (IS_ERR(io->phy)) { + rc = PTR_ERR(io->phy); + goto err; + } + return 0; err: dp_parser_unmap_io_resources(parser); @@ -90,7 +97,6 @@ static int dp_parser_misc(struct dp_parser *parser) } parser->max_dp_lanes = len; - return 0; } diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h index 841e776124c4..34b49628bbaf 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.h +++ b/drivers/gpu/drm/msm/dp/dp_parser.h @@ -7,10 +7,11 @@ #define _DP_PARSER_H_ #include +#include +#include #include "dpu_io_util.h" #include "msm_drv.h" -#include "dp_pll.h" #define DP_LABEL "MDSS DP DISPLAY" #define DP_MAX_PIXEL_CLK_KHZ 675000 @@ -62,15 +63,11 @@ struct dp_display_data { * * @dp_controller: Display Port controller mapped memory address * @phy_io: phy's mapped memory address - * @ln_tx0_io: USB-DP lane TX0's mapped memory address - * @ln_tx1_io: USB-DP lane TX1's mapped memory address - * @dp_pll_io: DP PLL mapped memory address - * @usb3_dp_com: USB3 DP PHY combo mapped memory address */ struct dp_io { struct dss_io_data dp_controller; - struct dss_io_data phy_reg; - struct dss_io_data usb3_dp_com; + struct phy *phy; + union phy_configure_opts phy_opts; }; /** @@ -117,7 +114,6 @@ struct dp_parser { struct dp_pinctrl pinctrl; struct dp_io io; struct dp_display_data disp_data; - struct msm_dp_pll *pll; const struct dp_regulator_cfg *regulator_cfg; u32 max_dp_lanes; diff --git a/drivers/gpu/drm/msm/dp/dp_pll.c b/drivers/gpu/drm/msm/dp/dp_pll.c deleted file mode 100644 index 53f82cd97027..000000000000 --- a/drivers/gpu/drm/msm/dp/dp_pll.c +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. - */ - -#include - -#include "dp_parser.h" -#include "dp_pll.h" -#include "dp_pll_private.h" - -static int dp_pll_get_phy_io(struct dp_parser *parser) -{ - struct dp_io *io = &parser->io; - - io->usb3_dp_com.base = ioremap(REG_USB3_DP_COM_REGION_BASE, - REG_USB3_DP_COM_REGION_SIZE); - if (!io->usb3_dp_com.base) { - DRM_ERROR("unable to map USB3 DP COM IO\n"); - return -EIO; - } - - /* ToDo(user): DP PLL and DP PHY will not be part of - * DP driver eventually so for now Hardcode Base and offsets - * of PHY registers so we can remove them from dts and bindings - */ - io->phy_reg.base = ioremap(REG_DP_PHY_REGION_BASE, - REG_DP_PHY_REGION_SIZE); - if (!io->phy_reg.base) { - DRM_ERROR("DP PHY io region mapping failed\n"); - return -EIO; - } - io->phy_reg.len = REG_DP_PHY_REGION_SIZE; - - return 0; -} - -static int msm_dp_pll_init(struct msm_dp_pll *pll, - enum msm_dp_pll_type type, int id) -{ - struct device *dev = &pll->pdev->dev; - int ret = 0; - - switch (type) { - case MSM_DP_PLL_10NM: - ret = msm_dp_pll_10nm_init(pll, id); - break; - default: - DRM_DEV_ERROR(dev, "%s: Wrong PLL type %d\n", __func__, type); - return -ENXIO; - } - - if (ret) { - DRM_DEV_ERROR(dev, "%s: failed to init DP PLL\n", __func__); - return ret; - } - - pll->type = type; - - DRM_DEBUG_DP("DP:%d PLL registered", id); - - return ret; -} - -struct msm_dp_pll *dp_pll_get(struct dp_pll_in *pll_in) -{ - struct msm_dp_pll *dp_pll; - struct dp_parser *parser = pll_in->parser; - struct dp_io_pll *pll_io; - int ret; - - dp_pll = devm_kzalloc(&pll_in->pdev->dev, sizeof(*dp_pll), GFP_KERNEL); - if (!dp_pll) - return ERR_PTR(-ENOMEM); - - pll_io = &dp_pll->pll_io; - dp_pll->pdev = pll_in->pdev; - - dp_pll_get_phy_io(parser); - - pll_io->pll_base = parser->io.phy_reg.base + DP_PHY_PLL_OFFSET; - pll_io->phy_base = parser->io.phy_reg.base + DP_PHY_REG_OFFSET; - pll_io->ln_tx0_base = parser->io.phy_reg.base + DP_PHY_LN_TX0_OFFSET; - pll_io->ln_tx1_base = parser->io.phy_reg.base + DP_PHY_LN_TX1_OFFSET; - - ret = msm_dp_pll_init(dp_pll, MSM_DP_PLL_10NM, 0); - if (ret) { - kfree(dp_pll); - return ERR_PTR(ret); - } - - return dp_pll; -} - -void dp_pll_put(struct msm_dp_pll *dp_pll) -{ - if (dp_pll->type == MSM_DP_PLL_10NM) - msm_dp_pll_10nm_deinit(dp_pll); -} diff --git a/drivers/gpu/drm/msm/dp/dp_pll.h b/drivers/gpu/drm/msm/dp/dp_pll.h deleted file mode 100644 index 5a10c8f3cfea..000000000000 --- a/drivers/gpu/drm/msm/dp/dp_pll.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DP_PLL_H -#define __DP_PLL_H - -#include -#include -#include - -#include "dpu_io_util.h" -#include "msm_drv.h" -#include "dp_parser.h" - -#define PLL_REG_W(base, offset, data) \ - writel((data), (base) + (offset)) -#define PLL_REG_R(base, offset) readl((base) + (offset)) - -enum msm_dp_pll_type { - MSM_DP_PLL_10NM, - MSM_DP_PLL_MAX -}; - -struct dp_pll_in { - struct platform_device *pdev; - struct dp_parser *parser; -}; - -struct dp_io_pll { - void __iomem *pll_base; - void __iomem *phy_base; - void __iomem *ln_tx0_base; - void __iomem *ln_tx1_base; -}; - -struct msm_dp_pll { - enum msm_dp_pll_type type; - bool pll_on; - - struct dp_io_pll pll_io; - - /* clock-provider: */ - struct clk_hw_onecell_data *hw_data; - - struct platform_device *pdev; - void *priv; - - /* Pll specific resources like GPIO, power supply, clocks, etc*/ - struct dss_module_power mp; - int (*get_provider)(struct msm_dp_pll *pll, - struct clk **link_clk_provider, - struct clk **pixel_clk_provider); -}; - -struct msm_dp_pll *dp_pll_get(struct dp_pll_in *pll_in); - -void dp_pll_put(struct msm_dp_pll *dp_pll); - -#endif /* __DP_PLL_H */ diff --git a/drivers/gpu/drm/msm/dp/dp_pll_10nm.c b/drivers/gpu/drm/msm/dp/dp_pll_10nm.c deleted file mode 100644 index a2bf2fc24d6a..000000000000 --- a/drivers/gpu/drm/msm/dp/dp_pll_10nm.c +++ /dev/null @@ -1,930 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. - */ - -/* - * Display Port PLL driver block diagram for branch clocks - * - * +------------------------------+ - * | DP_VCO_CLK | - * | | - * | +-------------------+ | - * | | (DP PLL/VCO) | | - * | +---------+---------+ | - * | v | - * | +----------+-----------+ | - * | | hsclk_divsel_clk_src | | - * | +----------+-----------+ | - * +------------------------------+ - * | - * +---------<---------v------------>----------+ - * | | - * +--------v---------+ | - * | dp_phy_pll | | - * | link_clk | | - * +--------+---------+ | - * | | - * | | - * v v - * Input to DISPCC block | - * for link clk, crypto clk | - * and interface clock | - * | - * | - * +--------<------------+-----------------+---<---+ - * | | | - * +----v---------+ +--------v-----+ +--------v------+ - * | vco_divided | | vco_divided | | vco_divided | - * | _clk_src | | _clk_src | | _clk_src | - * | | | | | | - * |divsel_six | | divsel_two | | divsel_four | - * +-------+------+ +-----+--------+ +--------+------+ - * | | | - * v---->----------v-------------<------v - * | - * +----------+---------+ - * | dp_phy_pll_vco | - * | div_clk | - * +---------+----------+ - * | - * v - * Input to DISPCC block - * for DP pixel clock - * - */ - -#include -#include -#include -#include -#include -#include - -#include "dp_hpd.h" -#include "dp_pll.h" -#include "dp_pll_private.h" - -#define NUM_PROVIDED_CLKS 2 - -#define DP_LINK_CLK_SRC 0 -#define DP_PIXEL_CLK_SRC 1 - - -static int dp_vco_set_rate_10nm(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate); - -static unsigned long dp_vco_recalc_rate_10nm(struct clk_hw *hw, - unsigned long parent_rate); - -static long dp_vco_round_rate_10nm(struct clk_hw *hw, - unsigned long rate, unsigned long *parent_rate); - -static int dp_vco_prepare_10nm(struct clk_hw *hw); -static void dp_vco_unprepare_10nm(struct clk_hw *hw); - -static struct dp_pll_db *dp_pdb; - -static const struct clk_ops dp_10nm_vco_clk_ops = { - .recalc_rate = dp_vco_recalc_rate_10nm, - .set_rate = dp_vco_set_rate_10nm, - .round_rate = dp_vco_round_rate_10nm, - .prepare = dp_vco_prepare_10nm, - .unprepare = dp_vco_unprepare_10nm, -}; - -struct dp_pll_10nm_pclksel { - struct clk_hw hw; - - /* divider params */ - u8 shift; - u8 width; - u8 flags; /* same flags as used by clk_divider struct */ - - struct dp_pll_db *pll; -}; - -#define to_pll_10nm_pclksel(_hw) \ - container_of(_hw, struct dp_pll_10nm_pclksel, hw) - -static const struct clk_parent_data disp_cc_parent_data_0[] = { - { .fw_name = "bi_tcxo" }, - { .fw_name = "dp_phy_pll_link_clk", .name = "dp_phy_pll_link_clk" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, -}; - -static struct dp_pll_vco_clk dp_vco_clk = { - .min_rate = DP_VCO_HSCLK_RATE_1620MHZDIV1000, - .max_rate = DP_VCO_HSCLK_RATE_8100MHZDIV1000, -}; - -static int dp_pll_mux_set_parent_10nm(struct clk_hw *hw, u8 val) -{ - struct dp_pll_10nm_pclksel *pclksel = to_pll_10nm_pclksel(hw); - struct dp_pll_db *dp_res = pclksel->pll; - struct dp_io_pll *pll_io = &dp_res->base->pll_io; - u32 auxclk_div; - - auxclk_div = PLL_REG_R(pll_io->phy_base, REG_DP_PHY_VCO_DIV); - auxclk_div &= ~0x03; - - if (val == 0) - auxclk_div |= 1; - else if (val == 1) - auxclk_div |= 2; - else if (val == 2) - auxclk_div |= 0; - - PLL_REG_W(pll_io->phy_base, - REG_DP_PHY_VCO_DIV, auxclk_div); - DRM_DEBUG_DP("%s: mux=%d auxclk_div=%x\n", __func__, val, auxclk_div); - - return 0; -} - -static u8 dp_pll_mux_get_parent_10nm(struct clk_hw *hw) -{ - u32 auxclk_div = 0; - struct dp_pll_10nm_pclksel *pclksel = to_pll_10nm_pclksel(hw); - struct dp_pll_db *dp_res = pclksel->pll; - struct dp_io_pll *pll_io = &dp_res->base->pll_io; - u8 val = 0; - - auxclk_div = PLL_REG_R(pll_io->phy_base, REG_DP_PHY_VCO_DIV); - auxclk_div &= 0x03; - - if (auxclk_div == 1) /* Default divider */ - val = 0; - else if (auxclk_div == 2) - val = 1; - else if (auxclk_div == 0) - val = 2; - - DRM_DEBUG_DP("%s: auxclk_div=%d, val=%d\n", __func__, auxclk_div, val); - - return val; -} - -static int dp_pll_clk_mux_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - unsigned long rate = 0; - - rate = clk_get_rate(hw->clk); - - if (rate <= 0) { - DRM_ERROR("Rate is not set properly\n"); - return -EINVAL; - } - - req->rate = rate; - - DRM_DEBUG_DP("%s: rate=%ld\n", __func__, req->rate); - return 0; -} - -static unsigned long dp_pll_mux_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_hw *div_clk_hw = NULL, *vco_clk_hw = NULL; - struct dp_pll_vco_clk *vco; - - div_clk_hw = clk_hw_get_parent(hw); - if (!div_clk_hw) - return 0; - - vco_clk_hw = clk_hw_get_parent(div_clk_hw); - if (!vco_clk_hw) - return 0; - - vco = to_dp_vco_hw(vco_clk_hw); - if (!vco) - return 0; - - if (vco->rate == DP_VCO_HSCLK_RATE_8100MHZDIV1000) - return (vco->rate / 6); - else if (vco->rate == DP_VCO_HSCLK_RATE_5400MHZDIV1000) - return (vco->rate / 4); - else - return (vco->rate / 2); -} - -static int dp_pll_10nm_get_provider(struct msm_dp_pll *pll, - struct clk **link_clk_provider, - struct clk **pixel_clk_provider) -{ - struct clk_hw_onecell_data *hw_data = pll->hw_data; - - if (link_clk_provider) - *link_clk_provider = hw_data->hws[DP_LINK_CLK_SRC]->clk; - if (pixel_clk_provider) - *pixel_clk_provider = hw_data->hws[DP_PIXEL_CLK_SRC]->clk; - - return 0; -} - -static const struct clk_ops dp_10nm_pclksel_clk_ops = { - .get_parent = dp_pll_mux_get_parent_10nm, - .set_parent = dp_pll_mux_set_parent_10nm, - .recalc_rate = dp_pll_mux_recalc_rate, - .determine_rate = dp_pll_clk_mux_determine_rate, -}; - -static struct clk_hw *dp_pll_10nm_pixel_clk_sel(struct dp_pll_db *pll_10nm) -{ - struct device *dev = &pll_10nm->pdev->dev; - struct dp_pll_10nm_pclksel *pll_pclksel; - struct clk_init_data pclksel_init = { - .parent_data = disp_cc_parent_data_0, - .num_parents = 3, - .name = "dp_phy_pll_vco_div_clk", - .ops = &dp_10nm_pclksel_clk_ops, - }; - int ret; - - pll_pclksel = devm_kzalloc(dev, sizeof(*pll_pclksel), GFP_KERNEL); - if (!pll_pclksel) - return ERR_PTR(-ENOMEM); - - pll_pclksel->pll = pll_10nm; - pll_pclksel->shift = 0; - pll_pclksel->width = 4; - pll_pclksel->hw.init = &pclksel_init; - - ret = clk_hw_register(dev, &pll_pclksel->hw); - if (ret) - return ERR_PTR(ret); - - return &pll_pclksel->hw; -} - -static void dp_pll_10nm_unregister(struct dp_pll_db *pll_10nm) -{ - int i = 0; - struct clk_hw **hws; - - hws = pll_10nm->hws; - - for (i = 0; i < pll_10nm->num_hws; i++) { - if (pll_10nm->fixed_factor_clk[i] == true) - clk_hw_unregister_fixed_factor(hws[i]); - else - clk_hw_unregister(hws[i]); - } -} - -static int dp_pll_10nm_register(struct dp_pll_db *pll_10nm) -{ - struct clk_hw_onecell_data *hw_data; - int ret = 0; - struct clk_hw *hw; - - struct msm_dp_pll *pll = pll_10nm->base; - struct device *dev = &pll_10nm->pdev->dev; - struct clk_hw **hws = pll_10nm->hws; - int num = 0; - - struct clk_init_data vco_init = { - .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", - }, - .num_parents = 1, - .name = "dp_vco_clk", - .ops = &dp_10nm_vco_clk_ops, - }; - - if (!dev) { - DRM_ERROR("DP dev node not available\n"); - return 0; - } - - DRM_DEBUG_DP("DP->id = %d", pll_10nm->id); - - hw_data = devm_kzalloc(dev, sizeof(*hw_data) + - NUM_PROVIDED_CLKS * sizeof(struct clk_hw *), - GFP_KERNEL); - if (!hw_data) - return -ENOMEM; - - dp_vco_clk.hw.init = &vco_init; - ret = clk_hw_register(dev, &dp_vco_clk.hw); - if (ret) - return ret; - hws[num++] = &dp_vco_clk.hw; - - hw = clk_hw_register_fixed_factor(dev, "dp_phy_pll_link_clk", - "dp_vco_clk", CLK_SET_RATE_PARENT, 1, 10); - if (IS_ERR(hw)) - return PTR_ERR(hw); - - pll_10nm->fixed_factor_clk[num] = true; - hws[num++] = hw; - hw_data->hws[DP_LINK_CLK_SRC] = hw; - - hw = clk_hw_register_fixed_factor(dev, "dp_vco_divsel_two_clk_src", - "dp_vco_clk", 0, 1, 2); - if (IS_ERR(hw)) - return PTR_ERR(hw); - - pll_10nm->fixed_factor_clk[num] = true; - hws[num++] = hw; - - hw = clk_hw_register_fixed_factor(dev, "dp_vco_divsel_four_clk_src", - "dp_vco_clk", 0, 1, 4); - if (IS_ERR(hw)) - return PTR_ERR(hw); - - pll_10nm->fixed_factor_clk[num] = true; - hws[num++] = hw; - - hw = clk_hw_register_fixed_factor(dev, "dp_vco_divsel_six_clk_src", - "dp_vco_clk", 0, 1, 6); - if (IS_ERR(hw)) - return PTR_ERR(hw); - - pll_10nm->fixed_factor_clk[num] = true; - hws[num++] = hw; - - hw = dp_pll_10nm_pixel_clk_sel(pll_10nm); - if (IS_ERR(hw)) - return PTR_ERR(hw); - - hws[num++] = hw; - hw_data->hws[DP_PIXEL_CLK_SRC] = hw; - - pll_10nm->num_hws = num; - - hw_data->num = NUM_PROVIDED_CLKS; - pll->hw_data = hw_data; - - ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, - pll->hw_data); - if (ret) { - DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", - ret); - return ret; - } - - return ret; -} - -void msm_dp_pll_10nm_deinit(struct msm_dp_pll *pll) -{ - dp_pll_10nm_unregister(pll->priv); -} - -int msm_dp_pll_10nm_init(struct msm_dp_pll *pll, int id) -{ - struct dp_pll_db *dp_10nm_pll; - struct platform_device *pdev = pll->pdev; - int ret; - - dp_10nm_pll = devm_kzalloc(&pdev->dev, - sizeof(*dp_10nm_pll), GFP_KERNEL); - if (!dp_10nm_pll) - return -ENOMEM; - - DRM_DEBUG_DP("DP PLL%d", id); - - dp_10nm_pll->base = pll; - dp_10nm_pll->pdev = pll->pdev; - dp_10nm_pll->id = id; - dp_pdb = dp_10nm_pll; - pll->priv = (void *)dp_10nm_pll; - dp_vco_clk.priv = pll; - dp_10nm_pll->index = 0; - - ret = dp_pll_10nm_register(dp_10nm_pll); - if (ret) { - DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); - return ret; - } - - pll->get_provider = dp_pll_10nm_get_provider; - - return ret; -} - -static int dp_vco_pll_init_db_10nm(struct msm_dp_pll *pll, - unsigned long rate) -{ - u32 spare_value = 0; - struct dp_io_pll *pll_io; - struct dp_pll_db *dp_res = to_dp_pll_db(pll); - - pll_io = &pll->pll_io; - spare_value = PLL_REG_R(pll_io->phy_base, REG_DP_PHY_SPARE0); - dp_res->lane_cnt = spare_value & 0x0F; - dp_res->orientation = (spare_value & 0xF0) >> 4; - - DRM_DEBUG_DP("%s: spare_value=0x%x, ln_cnt=0x%x, orientation=0x%x\n", - __func__, spare_value, dp_res->lane_cnt, - dp_res->orientation); - - switch (rate) { - case DP_VCO_HSCLK_RATE_1620MHZDIV1000: - DRM_DEBUG_DP("%s: VCO rate: %ld\n", __func__, - DP_VCO_RATE_9720MHZDIV1000); - dp_res->hsclk_sel = 0x0c; - dp_res->dec_start_mode0 = 0x69; - dp_res->div_frac_start1_mode0 = 0x00; - dp_res->div_frac_start2_mode0 = 0x80; - dp_res->div_frac_start3_mode0 = 0x07; - dp_res->integloop_gain0_mode0 = 0x3f; - dp_res->integloop_gain1_mode0 = 0x00; - dp_res->vco_tune_map = 0x00; - dp_res->lock_cmp1_mode0 = 0x6f; - dp_res->lock_cmp2_mode0 = 0x08; - dp_res->lock_cmp3_mode0 = 0x00; - dp_res->phy_vco_div = 0x1; - dp_res->lock_cmp_en = 0x00; - break; - case DP_VCO_HSCLK_RATE_2700MHZDIV1000: - DRM_DEBUG_DP("%s: VCO rate: %ld\n", __func__, - DP_VCO_RATE_10800MHZDIV1000); - dp_res->hsclk_sel = 0x04; - dp_res->dec_start_mode0 = 0x69; - dp_res->div_frac_start1_mode0 = 0x00; - dp_res->div_frac_start2_mode0 = 0x80; - dp_res->div_frac_start3_mode0 = 0x07; - dp_res->integloop_gain0_mode0 = 0x3f; - dp_res->integloop_gain1_mode0 = 0x00; - dp_res->vco_tune_map = 0x00; - dp_res->lock_cmp1_mode0 = 0x0f; - dp_res->lock_cmp2_mode0 = 0x0e; - dp_res->lock_cmp3_mode0 = 0x00; - dp_res->phy_vco_div = 0x1; - dp_res->lock_cmp_en = 0x00; - break; - case DP_VCO_HSCLK_RATE_5400MHZDIV1000: - DRM_DEBUG_DP("%s: VCO rate: %ld\n", __func__, - DP_VCO_RATE_10800MHZDIV1000); - dp_res->hsclk_sel = 0x00; - dp_res->dec_start_mode0 = 0x8c; - dp_res->div_frac_start1_mode0 = 0x00; - dp_res->div_frac_start2_mode0 = 0x00; - dp_res->div_frac_start3_mode0 = 0x0a; - dp_res->integloop_gain0_mode0 = 0x3f; - dp_res->integloop_gain1_mode0 = 0x00; - dp_res->vco_tune_map = 0x00; - dp_res->lock_cmp1_mode0 = 0x1f; - dp_res->lock_cmp2_mode0 = 0x1c; - dp_res->lock_cmp3_mode0 = 0x00; - dp_res->phy_vco_div = 0x2; - dp_res->lock_cmp_en = 0x00; - break; - case DP_VCO_HSCLK_RATE_8100MHZDIV1000: - DRM_DEBUG_DP("%s: VCO rate: %ld\n", __func__, - DP_VCO_RATE_8100MHZDIV1000); - dp_res->hsclk_sel = 0x03; - dp_res->dec_start_mode0 = 0x69; - dp_res->div_frac_start1_mode0 = 0x00; - dp_res->div_frac_start2_mode0 = 0x80; - dp_res->div_frac_start3_mode0 = 0x07; - dp_res->integloop_gain0_mode0 = 0x3f; - dp_res->integloop_gain1_mode0 = 0x00; - dp_res->vco_tune_map = 0x00; - dp_res->lock_cmp1_mode0 = 0x2f; - dp_res->lock_cmp2_mode0 = 0x2a; - dp_res->lock_cmp3_mode0 = 0x00; - dp_res->phy_vco_div = 0x0; - dp_res->lock_cmp_en = 0x08; - break; - default: - return -EINVAL; - } - return 0; -} - -static int dp_config_vco_rate_10nm(struct dp_pll_vco_clk *vco, - unsigned long rate) -{ - u32 res = 0; - struct msm_dp_pll *pll = vco->priv; - struct dp_io_pll *pll_io = &pll->pll_io; - struct dp_pll_db *dp_res = to_dp_pll_db(pll); - - res = dp_vco_pll_init_db_10nm(pll, rate); - if (res) { - DRM_ERROR("VCO Init DB failed\n"); - return res; - } - - if (dp_res->lane_cnt != 4) { - if (dp_res->orientation == ORIENTATION_CC2) - PLL_REG_W(pll_io->phy_base, REG_DP_PHY_PD_CTL, 0x6d); - else - PLL_REG_W(pll_io->phy_base, REG_DP_PHY_PD_CTL, 0x75); - } else { - PLL_REG_W(pll_io->phy_base, REG_DP_PHY_PD_CTL, 0x7d); - } - - PLL_REG_W(pll_io->pll_base, QSERDES_COM_SVS_MODE_CLK_SEL, 0x01); - PLL_REG_W(pll_io->pll_base, QSERDES_COM_SYSCLK_EN_SEL, 0x37); - PLL_REG_W(pll_io->pll_base, QSERDES_COM_SYS_CLK_CTRL, 0x02); - PLL_REG_W(pll_io->pll_base, QSERDES_COM_CLK_ENABLE1, 0x0e); - PLL_REG_W(pll_io->pll_base, QSERDES_COM_SYSCLK_BUF_ENABLE, 0x06); - PLL_REG_W(pll_io->pll_base, QSERDES_COM_CLK_SEL, 0x30); - PLL_REG_W(pll_io->pll_base, QSERDES_COM_CMN_CONFIG, 0x02); - - /* Different for each clock rates */ - PLL_REG_W(pll_io->pll_base, - QSERDES_COM_HSCLK_SEL, dp_res->hsclk_sel); - PLL_REG_W(pll_io->pll_base, - QSERDES_COM_DEC_START_MODE0, dp_res->dec_start_mode0); - PLL_REG_W(pll_io->pll_base, - QSERDES_COM_DIV_FRAC_START1_MODE0, - dp_res->div_frac_start1_mode0); - PLL_REG_W(pll_io->pll_base, - QSERDES_COM_DIV_FRAC_START2_MODE0, - dp_res->div_frac_start2_mode0); - PLL_REG_W(pll_io->pll_base, - QSERDES_COM_DIV_FRAC_START3_MODE0, - dp_res->div_frac_start3_mode0); - PLL_REG_W(pll_io->pll_base, - QSERDES_COM_INTEGLOOP_GAIN0_MODE0, - dp_res->integloop_gain0_mode0); - PLL_REG_W(pll_io->pll_base, - QSERDES_COM_INTEGLOOP_GAIN1_MODE0, - dp_res->integloop_gain1_mode0); - PLL_REG_W(pll_io->pll_base, - QSERDES_COM_VCO_TUNE_MAP, dp_res->vco_tune_map); - PLL_REG_W(pll_io->pll_base, - QSERDES_COM_LOCK_CMP1_MODE0, dp_res->lock_cmp1_mode0); - PLL_REG_W(pll_io->pll_base, - QSERDES_COM_LOCK_CMP2_MODE0, dp_res->lock_cmp2_mode0); - PLL_REG_W(pll_io->pll_base, - QSERDES_COM_LOCK_CMP3_MODE0, dp_res->lock_cmp3_mode0); - - PLL_REG_W(pll_io->pll_base, QSERDES_COM_BG_TIMER, 0x0a); - PLL_REG_W(pll_io->pll_base, QSERDES_COM_CORECLK_DIV_MODE0, 0x0a); - PLL_REG_W(pll_io->pll_base, QSERDES_COM_VCO_TUNE_CTRL, 0x00); - PLL_REG_W(pll_io->pll_base, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3f); - PLL_REG_W(pll_io->pll_base, QSERDES_COM_CORE_CLK_EN, 0x1f); - PLL_REG_W(pll_io->pll_base, QSERDES_COM_PLL_IVCO, 0x07); - PLL_REG_W(pll_io->pll_base, - QSERDES_COM_LOCK_CMP_EN, dp_res->lock_cmp_en); - PLL_REG_W(pll_io->pll_base, QSERDES_COM_PLL_CCTRL_MODE0, 0x36); - PLL_REG_W(pll_io->pll_base, QSERDES_COM_PLL_RCTRL_MODE0, 0x16); - PLL_REG_W(pll_io->pll_base, QSERDES_COM_CP_CTRL_MODE0, 0x06); - - if (dp_res->orientation == ORIENTATION_CC2) - PLL_REG_W(pll_io->phy_base, REG_DP_PHY_MODE, 0x4c); - else - PLL_REG_W(pll_io->phy_base, REG_DP_PHY_MODE, 0x5c); - - /* TX Lane configuration */ - PLL_REG_W(pll_io->phy_base, - REG_DP_PHY_TX0_TX1_LANE_CTL, 0x05); - PLL_REG_W(pll_io->phy_base, - REG_DP_PHY_TX2_TX3_LANE_CTL, 0x05); - - /* TX-0 register configuration */ - PLL_REG_W(pll_io->ln_tx0_base, - REG_DP_PHY_TXn_TRANSCEIVER_BIAS_EN, 0x1a); - PLL_REG_W(pll_io->ln_tx0_base, - REG_DP_PHY_TXn_VMODE_CTRL1, 0x40); - PLL_REG_W(pll_io->ln_tx0_base, - REG_DP_PHY_TXn_PRE_STALL_LDO_BOOST_EN, 0x30); - PLL_REG_W(pll_io->ln_tx0_base, - REG_DP_PHY_TXn_INTERFACE_SELECT, 0x3d); - PLL_REG_W(pll_io->ln_tx0_base, - REG_DP_PHY_TXn_CLKBUF_ENABLE, 0x0f); - PLL_REG_W(pll_io->ln_tx0_base, - REG_DP_PHY_TXn_RESET_TSYNC_EN, 0x03); - PLL_REG_W(pll_io->ln_tx0_base, - REG_DP_PHY_TXn_TRAN_DRVR_EMP_EN, 0x03); - PLL_REG_W(pll_io->ln_tx0_base, - REG_DP_PHY_TXn_PARRATE_REC_DETECT_IDLE_EN, 0x00); - PLL_REG_W(pll_io->ln_tx0_base, - REG_DP_PHY_TXn_TX_INTERFACE_MODE, 0x00); - PLL_REG_W(pll_io->ln_tx0_base, REG_DP_PHY_TXn_TX_BAND, 0x4); - - /* TX-1 register configuration */ - PLL_REG_W(pll_io->ln_tx1_base, - REG_DP_PHY_TXn_TRANSCEIVER_BIAS_EN, 0x1a); - PLL_REG_W(pll_io->ln_tx1_base, - REG_DP_PHY_TXn_VMODE_CTRL1, 0x40); - PLL_REG_W(pll_io->ln_tx1_base, - REG_DP_PHY_TXn_PRE_STALL_LDO_BOOST_EN, 0x30); - PLL_REG_W(pll_io->ln_tx1_base, - REG_DP_PHY_TXn_INTERFACE_SELECT, 0x3d); - PLL_REG_W(pll_io->ln_tx1_base, - REG_DP_PHY_TXn_CLKBUF_ENABLE, 0x0f); - PLL_REG_W(pll_io->ln_tx1_base, - REG_DP_PHY_TXn_RESET_TSYNC_EN, 0x03); - PLL_REG_W(pll_io->ln_tx1_base, - REG_DP_PHY_TXn_TRAN_DRVR_EMP_EN, 0x03); - PLL_REG_W(pll_io->ln_tx1_base, - REG_DP_PHY_TXn_PARRATE_REC_DETECT_IDLE_EN, 0x00); - PLL_REG_W(pll_io->ln_tx1_base, - REG_DP_PHY_TXn_TX_INTERFACE_MODE, 0x00); - PLL_REG_W(pll_io->ln_tx1_base, - REG_DP_PHY_TXn_TX_BAND, 0x4); - - /* dependent on the vco frequency */ - PLL_REG_W(pll_io->phy_base, - REG_DP_PHY_VCO_DIV, dp_res->phy_vco_div); - - return res; -} - -static bool dp_10nm_pll_lock_status(struct dp_pll_db *dp_res) -{ - u32 status; - bool pll_locked; - struct dp_io_pll *pll_io = &dp_res->base->pll_io; - - /* poll for PLL lock status */ - if (readl_poll_timeout_atomic((pll_io->pll_base + - QSERDES_COM_C_READY_STATUS), - status, - ((status & BIT(0)) > 0), - DP_PHY_PLL_POLL_SLEEP_US, - DP_PHY_PLL_POLL_TIMEOUT_US)) { - DRM_ERROR("%s: C_READY status is not high. Status=%x\n", - __func__, status); - pll_locked = false; - } else { - pll_locked = true; - } - - return pll_locked; -} - -static bool dp_10nm_phy_rdy_status(struct dp_pll_db *dp_res) -{ - u32 status; - bool phy_ready = true; - struct dp_io_pll *pll_io = &dp_res->base->pll_io; - - /* poll for PHY ready status */ - if (readl_poll_timeout_atomic((pll_io->phy_base + - REG_DP_PHY_STATUS), - status, - ((status & (BIT(1))) > 0), - DP_PHY_PLL_POLL_SLEEP_US, - DP_PHY_PLL_POLL_TIMEOUT_US)) { - DRM_ERROR("%s: Phy_ready is not high. Status=%x\n", - __func__, status); - phy_ready = false; - } - - return phy_ready; -} - -static int dp_pll_enable_10nm(struct clk_hw *hw) -{ - int rc = 0; - u32 bias_en, drvr_en; - struct dp_io_pll *pll_io; - struct dp_pll_vco_clk *vco = to_dp_vco_hw(hw); - struct msm_dp_pll *pll = to_msm_dp_pll(vco); - struct dp_pll_db *dp_res = to_dp_pll_db(pll); - - pll_io = &pll->pll_io; - - PLL_REG_W(pll_io->phy_base, REG_DP_PHY_AUX_CFG2, 0x04); - PLL_REG_W(pll_io->phy_base, REG_DP_PHY_CFG, 0x01); - PLL_REG_W(pll_io->phy_base, REG_DP_PHY_CFG, 0x05); - PLL_REG_W(pll_io->phy_base, REG_DP_PHY_CFG, 0x01); - PLL_REG_W(pll_io->phy_base, REG_DP_PHY_CFG, 0x09); - - PLL_REG_W(pll_io->pll_base, QSERDES_COM_RESETSM_CNTRL, 0x20); - - if (!dp_10nm_pll_lock_status(dp_res)) { - rc = -EINVAL; - goto lock_err; - } - - PLL_REG_W(pll_io->phy_base, REG_DP_PHY_CFG, 0x19); - /* poll for PHY ready status */ - if (!dp_10nm_phy_rdy_status(dp_res)) { - rc = -EINVAL; - goto lock_err; - } - - DRM_DEBUG_DP("%s: PLL is locked\n", __func__); - - if (dp_res->lane_cnt == 1) { - bias_en = 0x3e; - drvr_en = 0x13; - } else { - bias_en = 0x3f; - drvr_en = 0x10; - } - - if (dp_res->lane_cnt != 4) { - if (dp_res->orientation == ORIENTATION_CC1) { - PLL_REG_W(pll_io->ln_tx1_base, - REG_DP_PHY_TXn_HIGHZ_DRVR_EN, drvr_en); - PLL_REG_W(pll_io->ln_tx1_base, - REG_DP_PHY_TXn_TRANSCEIVER_BIAS_EN, bias_en); - } else { - PLL_REG_W(pll_io->ln_tx0_base, - REG_DP_PHY_TXn_HIGHZ_DRVR_EN, drvr_en); - PLL_REG_W(pll_io->ln_tx0_base, - REG_DP_PHY_TXn_TRANSCEIVER_BIAS_EN, bias_en); - } - } else { - PLL_REG_W(pll_io->ln_tx0_base, - REG_DP_PHY_TXn_HIGHZ_DRVR_EN, drvr_en); - PLL_REG_W(pll_io->ln_tx0_base, - REG_DP_PHY_TXn_TRANSCEIVER_BIAS_EN, bias_en); - PLL_REG_W(pll_io->ln_tx1_base, - REG_DP_PHY_TXn_HIGHZ_DRVR_EN, drvr_en); - PLL_REG_W(pll_io->ln_tx1_base, - REG_DP_PHY_TXn_TRANSCEIVER_BIAS_EN, bias_en); - } - - PLL_REG_W(pll_io->ln_tx0_base, REG_DP_PHY_TXn_TX_POL_INV, 0x0a); - PLL_REG_W(pll_io->ln_tx1_base, REG_DP_PHY_TXn_TX_POL_INV, 0x0a); - PLL_REG_W(pll_io->phy_base, REG_DP_PHY_CFG, 0x18); - udelay(2000); - - PLL_REG_W(pll_io->phy_base, REG_DP_PHY_CFG, 0x19); - - /* poll for PHY ready status */ - if (!dp_10nm_phy_rdy_status(dp_res)) { - rc = -EINVAL; - goto lock_err; - } - - PLL_REG_W(pll_io->ln_tx0_base, REG_DP_PHY_TXn_TX_DRV_LVL, 0x38); - PLL_REG_W(pll_io->ln_tx1_base, REG_DP_PHY_TXn_TX_DRV_LVL, 0x38); - PLL_REG_W(pll_io->ln_tx0_base, REG_DP_PHY_TXn_TX_EMP_POST1_LVL, 0x20); - PLL_REG_W(pll_io->ln_tx1_base, REG_DP_PHY_TXn_TX_EMP_POST1_LVL, 0x20); - PLL_REG_W(pll_io->ln_tx0_base, - REG_DP_PHY_TXn_RES_CODE_LANE_OFFSET_TX, 0x06); - PLL_REG_W(pll_io->ln_tx1_base, - REG_DP_PHY_TXn_RES_CODE_LANE_OFFSET_TX, 0x06); - PLL_REG_W(pll_io->ln_tx0_base, - REG_DP_PHY_TXn_RES_CODE_LANE_OFFSET_RX, 0x07); - PLL_REG_W(pll_io->ln_tx1_base, - REG_DP_PHY_TXn_RES_CODE_LANE_OFFSET_RX, 0x07); - -lock_err: - return rc; -} - -static int dp_pll_disable_10nm(struct clk_hw *hw) -{ - int rc = 0; - struct dp_pll_vco_clk *vco = to_dp_vco_hw(hw); - struct msm_dp_pll *pll = to_msm_dp_pll(vco); - - /* Assert DP PHY power down */ - PLL_REG_W(pll->pll_io.phy_base, REG_DP_PHY_PD_CTL, 0x2); - - return rc; -} - - -static int dp_vco_prepare_10nm(struct clk_hw *hw) -{ - int rc = 0; - struct dp_pll_vco_clk *vco = to_dp_vco_hw(hw); - struct msm_dp_pll *pll = (struct msm_dp_pll *)vco->priv; - struct dp_pll_db *dp_res = to_dp_pll_db(pll); - - DRM_DEBUG_DP("%s: rate = %ld\n", __func__, vco->rate); - if ((dp_res->vco_cached_rate != 0) - && (dp_res->vco_cached_rate == vco->rate)) { - rc = dp_vco_set_rate_10nm(hw, - dp_res->vco_cached_rate, dp_res->vco_cached_rate); - if (rc) { - DRM_ERROR("index=%d vco_set_rate failed. rc=%d\n", - rc, dp_res->index); - goto error; - } - } - - rc = dp_pll_enable_10nm(hw); - if (rc) { - DRM_ERROR("ndx=%d failed to enable dp pll\n", - dp_res->index); - goto error; - } - - pll->pll_on = true; -error: - return rc; -} - -static void dp_vco_unprepare_10nm(struct clk_hw *hw) -{ - struct dp_pll_vco_clk *vco = to_dp_vco_hw(hw); - struct msm_dp_pll *pll = to_msm_dp_pll(vco); - struct dp_pll_db *dp_res = to_dp_pll_db(pll); - - if (!dp_res) { - DRM_ERROR("Invalid input parameter\n"); - return; - } - - if (!pll->pll_on) { - DRM_ERROR("pll resource can't be enabled\n"); - return; - } - dp_res->vco_cached_rate = vco->rate; - dp_pll_disable_10nm(hw); - - pll->pll_on = false; -} - -static int dp_vco_set_rate_10nm(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct dp_pll_vco_clk *vco = to_dp_vco_hw(hw); - int rc; - - DRM_DEBUG_DP("DP lane CLK rate=%ld\n", rate); - - rc = dp_config_vco_rate_10nm(vco, rate); - if (rc) - DRM_ERROR("%s: Failed to set clk rate\n", __func__); - - vco->rate = rate; - - return 0; -} - -static unsigned long dp_vco_recalc_rate_10nm(struct clk_hw *hw, - unsigned long parent_rate) -{ - u32 div, hsclk_div, link_clk_div = 0; - u64 vco_rate; - struct dp_io_pll *pll_io; - struct dp_pll_vco_clk *vco = to_dp_vco_hw(hw); - struct msm_dp_pll *pll = to_msm_dp_pll(vco); - struct dp_pll_db *dp_res = to_dp_pll_db(pll); - - pll_io = &pll->pll_io; - - div = PLL_REG_R(pll_io->pll_base, QSERDES_COM_HSCLK_SEL); - div &= 0x0f; - - if (div == 12) - hsclk_div = 6; /* Default */ - else if (div == 4) - hsclk_div = 4; - else if (div == 0) - hsclk_div = 2; - else if (div == 3) - hsclk_div = 1; - else { - DRM_DEBUG_DP("unknown divider. forcing to default\n"); - hsclk_div = 5; - } - - div = PLL_REG_R(pll_io->phy_base, REG_DP_PHY_AUX_CFG2); - div >>= 2; - - if ((div & 0x3) == 0) - link_clk_div = 5; - else if ((div & 0x3) == 1) - link_clk_div = 10; - else if ((div & 0x3) == 2) - link_clk_div = 20; - else - DRM_ERROR("%s: unsupported div. Phy_mode: %d\n", __func__, div); - - if (link_clk_div == 20) { - vco_rate = DP_VCO_HSCLK_RATE_2700MHZDIV1000; - } else { - if (hsclk_div == 6) - vco_rate = DP_VCO_HSCLK_RATE_1620MHZDIV1000; - else if (hsclk_div == 4) - vco_rate = DP_VCO_HSCLK_RATE_2700MHZDIV1000; - else if (hsclk_div == 2) - vco_rate = DP_VCO_HSCLK_RATE_5400MHZDIV1000; - else - vco_rate = DP_VCO_HSCLK_RATE_8100MHZDIV1000; - } - - DRM_DEBUG_DP("returning vco rate = %lu\n", (unsigned long)vco_rate); - - dp_res->vco_cached_rate = vco->rate = vco_rate; - return (unsigned long)vco_rate; -} - -long dp_vco_round_rate_10nm(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) -{ - unsigned long rrate = rate; - struct dp_pll_vco_clk *vco = to_dp_vco_hw(hw); - - if (rate <= vco->min_rate) - rrate = vco->min_rate; - else if (rate <= DP_VCO_HSCLK_RATE_2700MHZDIV1000) - rrate = DP_VCO_HSCLK_RATE_2700MHZDIV1000; - else if (rate <= DP_VCO_HSCLK_RATE_5400MHZDIV1000) - rrate = DP_VCO_HSCLK_RATE_5400MHZDIV1000; - else - rrate = vco->max_rate; - - DRM_DEBUG_DP("%s: rrate=%ld\n", __func__, rrate); - - *parent_rate = rrate; - return rrate; -} diff --git a/drivers/gpu/drm/msm/dp/dp_pll_private.h b/drivers/gpu/drm/msm/dp/dp_pll_private.h deleted file mode 100644 index 434abdc396f5..000000000000 --- a/drivers/gpu/drm/msm/dp/dp_pll_private.h +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DP_PLL_10NM_H -#define __DP_PLL_10NM_H - -#include "dp_pll.h" -#include "dp_reg.h" - -#define DP_VCO_HSCLK_RATE_1620MHZDIV1000 1620000UL -#define DP_VCO_HSCLK_RATE_2700MHZDIV1000 2700000UL -#define DP_VCO_HSCLK_RATE_5400MHZDIV1000 5400000UL -#define DP_VCO_HSCLK_RATE_8100MHZDIV1000 8100000UL - -#define NUM_DP_CLOCKS_MAX 6 - -#define DP_PHY_PLL_POLL_SLEEP_US 500 -#define DP_PHY_PLL_POLL_TIMEOUT_US 10000 - -#define DP_VCO_RATE_8100MHZDIV1000 8100000UL -#define DP_VCO_RATE_9720MHZDIV1000 9720000UL -#define DP_VCO_RATE_10800MHZDIV1000 10800000UL - -struct dp_pll_vco_clk { - struct clk_hw hw; - unsigned long rate; /* current vco rate */ - u64 min_rate; /* min vco rate */ - u64 max_rate; /* max vco rate */ - void *priv; -}; - -struct dp_pll_db { - struct msm_dp_pll *base; - - int id; - struct platform_device *pdev; - - /* private clocks: */ - bool fixed_factor_clk[NUM_DP_CLOCKS_MAX]; - struct clk_hw *hws[NUM_DP_CLOCKS_MAX]; - u32 num_hws; - - /* lane and orientation settings */ - u8 lane_cnt; - u8 orientation; - - /* COM PHY settings */ - u32 hsclk_sel; - u32 dec_start_mode0; - u32 div_frac_start1_mode0; - u32 div_frac_start2_mode0; - u32 div_frac_start3_mode0; - u32 integloop_gain0_mode0; - u32 integloop_gain1_mode0; - u32 vco_tune_map; - u32 lock_cmp1_mode0; - u32 lock_cmp2_mode0; - u32 lock_cmp3_mode0; - u32 lock_cmp_en; - - /* PHY vco divider */ - u32 phy_vco_div; - /* - * Certain pll's needs to update the same vco rate after resume in - * suspend/resume scenario. Cached the vco rate for such plls. - */ - unsigned long vco_cached_rate; - u32 cached_cfg0; - u32 cached_cfg1; - u32 cached_outdiv; - - uint32_t index; -}; - -static inline struct dp_pll_vco_clk *to_dp_vco_hw(struct clk_hw *hw) -{ - return container_of(hw, struct dp_pll_vco_clk, hw); -} - -#define to_msm_dp_pll(vco) ((struct msm_dp_pll *)vco->priv) - -#define to_dp_pll_db(x) ((struct dp_pll_db *)x->priv) - -int msm_dp_pll_10nm_init(struct msm_dp_pll *dp_pll, int id); -void msm_dp_pll_10nm_deinit(struct msm_dp_pll *dp_pll); - -#endif /* __DP_PLL_10NM_H */ diff --git a/drivers/gpu/drm/msm/dp/dp_power.c b/drivers/gpu/drm/msm/dp/dp_power.c index 34fdb2e5d644..17c1fc6a2d44 100644 --- a/drivers/gpu/drm/msm/dp/dp_power.c +++ b/drivers/gpu/drm/msm/dp/dp_power.c @@ -9,6 +9,7 @@ #include #include #include "dp_power.h" +#include "msm_drv.h" struct dp_power_private { struct dp_parser *parser; @@ -102,16 +103,6 @@ static int dp_power_clk_init(struct dp_power_private *power) ctrl = &power->parser->mp[DP_CTRL_PM]; stream = &power->parser->mp[DP_STREAM_PM]; - if (power->parser->pll && power->parser->pll->get_provider) { - rc = power->parser->pll->get_provider(power->parser->pll, - &power->link_provider, &power->pixel_provider); - if (rc) { - DRM_ERROR("%s:provider failed,don't set parent\n", - __func__); - return 0; - } - } - rc = msm_dss_get_clk(dev, core->clk_config, core->num_clk); if (rc) { DRM_ERROR("failed to get %s clk. err=%d\n", @@ -312,34 +303,6 @@ void dp_power_client_deinit(struct dp_power *dp_power) } -int dp_power_set_link_clk_parent(struct dp_power *dp_power) -{ - int rc = 0; - struct dp_power_private *power; - u32 num; - struct dss_clk *cfg; - char *name = "ctrl_link"; - - if (!dp_power) { - DRM_ERROR("invalid power data\n"); - rc = -EINVAL; - goto exit; - } - - power = container_of(dp_power, struct dp_power_private, dp_power); - - num = power->parser->mp[DP_CTRL_PM].num_clk; - cfg = power->parser->mp[DP_CTRL_PM].clk_config; - - while (num && strcmp(cfg->clk_name, name)) { - num--; - cfg++; - } - -exit: - return rc; -} - int dp_power_init(struct dp_power *dp_power, bool flip) { int rc = 0; diff --git a/drivers/gpu/drm/msm/dp/dp_power.h b/drivers/gpu/drm/msm/dp/dp_power.h index 5333a97d5c35..76743d755833 100644 --- a/drivers/gpu/drm/msm/dp/dp_power.h +++ b/drivers/gpu/drm/msm/dp/dp_power.h @@ -69,15 +69,6 @@ int dp_power_clk_status(struct dp_power *dp_power, enum dp_pm_type pm_type); int dp_power_clk_enable(struct dp_power *power, enum dp_pm_type pm_type, bool enable); -/** - * dp_power_set_link_clk_parent() - configures parent of link clocks - * - * @power: instance of power module - * return: 0 for success, error for failures - * - * This API will set the link clock parent source - */ -int dp_power_set_link_clk_parent(struct dp_power *power); /** * dp_power_client_init() - initialize clock and regulator modules diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h index de32f6204a50..43042ff90a19 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -6,22 +6,6 @@ #ifndef _DP_REG_H_ #define _DP_REG_H_ -/* DP PHY Register Regions */ -#define REG_DP_PHY_REGION_BASE (0x088ea000) -#define REG_DP_PHY_REGION_SIZE (0x00000C00) - -#define REG_USB3_DP_COM_REGION_BASE (0x088e8000) -#define REG_USB3_DP_COM_REGION_SIZE (0x00000020) - -#define DP_PHY_PLL_OFFSET (0x00000000) -#define DP_PHY_PLL_SIZE (0x00000200) -#define DP_PHY_REG_OFFSET (0x00000A00) -#define DP_PHY_REG_SIZE (0x00000200) -#define DP_PHY_LN_TX0_OFFSET (0x00000200) -#define DP_PHY_LN_TX0_SIZE (0x00000200) -#define DP_PHY_LN_TX1_OFFSET (0x00000600) -#define DP_PHY_LN_TX1_SIZE (0x00000200) - /* DP_TX Registers */ #define REG_DP_HW_VERSION (0x00000000) @@ -290,183 +274,10 @@ #define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000088) -/*DP PHY Register offsets */ -#define REG_DP_PHY_REVISION_ID0 (0x00000000) -#define REG_DP_PHY_REVISION_ID1 (0x00000004) -#define REG_DP_PHY_REVISION_ID2 (0x00000008) -#define REG_DP_PHY_REVISION_ID3 (0x0000000C) - -#define REG_DP_PHY_CFG (0x00000010) - -#define REG_DP_PHY_PD_CTL (0x00000018) -#define DP_PHY_PD_CTL_PWRDN (0x00000001) -#define DP_PHY_PD_CTL_PSR_PWRDN (0x00000002) -#define DP_PHY_PD_CTL_AUX_PWRDN (0x00000004) -#define DP_PHY_PD_CTL_LANE_0_1_PWRDN (0x00000008) -#define DP_PHY_PD_CTL_LANE_2_3_PWRDN (0x00000010) -#define DP_PHY_PD_CTL_PLL_PWRDN (0x00000020) -#define DP_PHY_PD_CTL_DP_CLAMP_EN (0x00000040) - -#define REG_DP_PHY_MODE (0x0000001C) - -#define REG_DP_PHY_AUX_CFG0 (0x00000020) -#define REG_DP_PHY_AUX_CFG1 (0x00000024) -#define REG_DP_PHY_AUX_CFG2 (0x00000028) -#define REG_DP_PHY_AUX_CFG3 (0x0000002C) -#define REG_DP_PHY_AUX_CFG4 (0x00000030) -#define REG_DP_PHY_AUX_CFG5 (0x00000034) -#define REG_DP_PHY_AUX_CFG6 (0x00000038) -#define REG_DP_PHY_AUX_CFG7 (0x0000003C) -#define REG_DP_PHY_AUX_CFG8 (0x00000040) -#define REG_DP_PHY_AUX_CFG9 (0x00000044) - -#define REG_DP_PHY_AUX_INTERRUPT_MASK (0x00000048) -#define PHY_AUX_STOP_ERR_MASK (0x00000001) -#define PHY_AUX_DEC_ERR_MASK (0x00000002) -#define PHY_AUX_SYNC_ERR_MASK (0x00000004) -#define PHY_AUX_ALIGN_ERR_MASK (0x00000008) -#define PHY_AUX_REQ_ERR_MASK (0x00000010) - - #define REG_DP_PHY_AUX_INTERRUPT_CLEAR (0x0000004C) #define REG_DP_PHY_AUX_BIST_CFG (0x00000050) #define REG_DP_PHY_AUX_INTERRUPT_STATUS (0x000000BC) -#define REG_DP_PHY_VCO_DIV 0x0064 -#define REG_DP_PHY_TX0_TX1_LANE_CTL 0x006C -#define REG_DP_PHY_TX2_TX3_LANE_CTL 0x0088 - -#define REG_DP_PHY_SPARE0 (0x00AC) -#define DP_PHY_SPARE0_MASK (0x000F) -#define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT (0x0004) - -#define REG_DP_PHY_STATUS (0x00C0) - -/* Tx registers */ -#define REG_DP_PHY_TXn_BIST_MODE_LANENO 0x0000 -#define REG_DP_PHY_TXn_CLKBUF_ENABLE 0x0008 - -#define REG_DP_PHY_TXn_TX_EMP_POST1_LVL 0x000C -#define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001F -#define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 - -#define REG_DP_PHY_TXn_TX_DRV_LVL 0x001C -#define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001F -#define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 - -#define REG_DP_PHY_TXn_RESET_TSYNC_EN 0x0024 -#define REG_DP_PHY_TXn_PRE_STALL_LDO_BOOST_EN 0x0028 -#define REG_DP_PHY_TXn_TX_BAND 0x002C -#define REG_DP_PHY_TXn_SLEW_CNTL 0x0030 -#define REG_DP_PHY_TXn_INTERFACE_SELECT 0x0034 - -#define REG_DP_PHY_TXn_RES_CODE_LANE_TX 0x003C -#define REG_DP_PHY_TXn_RES_CODE_LANE_RX 0x0040 -#define REG_DP_PHY_TXn_RES_CODE_LANE_OFFSET_TX 0x0044 -#define REG_DP_PHY_TXn_RES_CODE_LANE_OFFSET_RX 0x0048 - -#define REG_DP_PHY_TXn_DEBUG_BUS_SEL 0x0058 -#define REG_DP_PHY_TXn_TRANSCEIVER_BIAS_EN 0x005C -#define REG_DP_PHY_TXn_HIGHZ_DRVR_EN 0x0060 -#define REG_DP_PHY_TXn_TX_POL_INV 0x0064 -#define REG_DP_PHY_TXn_PARRATE_REC_DETECT_IDLE_EN 0x0068 - -#define REG_DP_PHY_TXn_LANE_MODE_1 0x008C - -#define REG_DP_PHY_TXn_TRAN_DRVR_EMP_EN 0x00C0 -#define REG_DP_PHY_TXn_TX_INTERFACE_MODE 0x00C4 - -#define REG_DP_PHY_TXn_VMODE_CTRL1 0x00F0 - -/* PLL register offset */ -#define QSERDES_COM_ATB_SEL1 0x0000 -#define QSERDES_COM_ATB_SEL2 0x0004 -#define QSERDES_COM_FREQ_UPDATE 0x0008 -#define QSERDES_COM_BG_TIMER 0x000C -#define QSERDES_COM_SSC_EN_CENTER 0x0010 -#define QSERDES_COM_SSC_ADJ_PER1 0x0014 -#define QSERDES_COM_SSC_ADJ_PER2 0x0018 -#define QSERDES_COM_SSC_PER1 0x001C -#define QSERDES_COM_SSC_PER2 0x0020 -#define QSERDES_COM_SSC_STEP_SIZE1 0x0024 -#define QSERDES_COM_SSC_STEP_SIZE2 0x0028 -#define QSERDES_COM_POST_DIV 0x002C -#define QSERDES_COM_POST_DIV_MUX 0x0030 - -#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x0034 -#define QSERDES_COM_BIAS_EN 0x0001 -#define QSERDES_COM_BIAS_EN_MUX 0x0002 -#define QSERDES_COM_CLKBUF_R_EN 0x0004 -#define QSERDES_COM_CLKBUF_L_EN 0x0008 -#define QSERDES_COM_EN_SYSCLK_TX_SEL 0x0010 -#define QSERDES_COM_CLKBUF_RX_DRIVE_L 0x0020 -#define QSERDES_COM_CLKBUF_RX_DRIVE_R 0x0040 - -#define QSERDES_COM_CLK_ENABLE1 0x0038 -#define QSERDES_COM_SYS_CLK_CTRL 0x003C -#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x0040 -#define QSERDES_COM_PLL_EN 0x0044 -#define QSERDES_COM_PLL_IVCO 0x0048 -#define QSERDES_COM_CMN_IETRIM 0x004C -#define QSERDES_COM_CMN_IPTRIM 0x0050 - -#define QSERDES_COM_CP_CTRL_MODE0 0x0060 -#define QSERDES_COM_CP_CTRL_MODE1 0x0064 -#define QSERDES_COM_PLL_RCTRL_MODE0 0x0068 -#define QSERDES_COM_PLL_RCTRL_MODE1 0x006C -#define QSERDES_COM_PLL_CCTRL_MODE0 0x0070 -#define QSERDES_COM_PLL_CCTRL_MODE1 0x0074 -#define QSERDES_COM_PLL_CNTRL 0x0078 -#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x007C -#define QSERDES_COM_SYSCLK_EN_SEL 0x0080 -#define QSERDES_COM_CML_SYSCLK_SEL 0x0084 -#define QSERDES_COM_RESETSM_CNTRL 0x0088 -#define QSERDES_COM_RESETSM_CNTRL2 0x008C -#define QSERDES_COM_LOCK_CMP_EN 0x0090 -#define QSERDES_COM_LOCK_CMP_CFG 0x0094 -#define QSERDES_COM_LOCK_CMP1_MODE0 0x0098 -#define QSERDES_COM_LOCK_CMP2_MODE0 0x009C -#define QSERDES_COM_LOCK_CMP3_MODE0 0x00A0 - -#define QSERDES_COM_DEC_START_MODE0 0x00B0 -#define QSERDES_COM_DEC_START_MODE1 0x00B4 -#define QSERDES_COM_DIV_FRAC_START1_MODE0 0x00B8 -#define QSERDES_COM_DIV_FRAC_START2_MODE0 0x00BC -#define QSERDES_COM_DIV_FRAC_START3_MODE0 0x00C0 -#define QSERDES_COM_DIV_FRAC_START1_MODE1 0x00C4 -#define QSERDES_COM_DIV_FRAC_START2_MODE1 0x00C8 -#define QSERDES_COM_DIV_FRAC_START3_MODE1 0x00CC -#define QSERDES_COM_INTEGLOOP_INITVAL 0x00D0 -#define QSERDES_COM_INTEGLOOP_EN 0x00D4 -#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x00D8 -#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x00DC -#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x00E0 -#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x00E4 -#define QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x00E8 -#define QSERDES_COM_VCO_TUNE_CTRL 0x00EC -#define QSERDES_COM_VCO_TUNE_MAP 0x00F0 - -#define QSERDES_COM_CMN_STATUS 0x0124 -#define QSERDES_COM_RESET_SM_STATUS 0x0128 - -#define QSERDES_COM_CLK_SEL 0x0138 -#define QSERDES_COM_HSCLK_SEL 0x013C - -#define QSERDES_COM_CORECLK_DIV_MODE0 0x0148 - -#define QSERDES_COM_SW_RESET 0x0150 -#define QSERDES_COM_CORE_CLK_EN 0x0154 -#define QSERDES_COM_C_READY_STATUS 0x0158 -#define QSERDES_COM_CMN_CONFIG 0x015C - -#define QSERDES_COM_SVS_MODE_CLK_SEL 0x0164 - -/* DP MMSS_CC registers */ -#define MMSS_DP_LINK_CMD_RCGR (0x0138) -#define MMSS_DP_LINK_CFG_RCGR (0x013C) -#define MMSS_DP_PIXEL_M (0x01B4) -#define MMSS_DP_PIXEL_N (0x01B8) - /* DP HDCP 1.3 registers */ #define DP_HDCP_CTRL (0x0A0) #define DP_HDCP_STATUS (0x0A4) @@ -492,28 +303,4 @@ #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA11 (0x01C) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA12 (0x020) -/* USB3 DP COM registers */ -#define REG_USB3_DP_COM_RESET_OVRD_CTRL (0x1C) -#define USB3_DP_COM_OVRD_CTRL_SW_DPPHY_RESET (0x01) -#define USB3_DP_COM_OVRD_CTRL_SW_DPPHY_RESET_MUX (0x02) -#define USB3_DP_COM_OVRD_CTRL_SW_USB3PHY_RESET (0x04) -#define USB3_DP_COM_OVRD_CTRL_SW_USB3PHY_RESET_MUX (0x08) - -#define REG_USB3_DP_COM_PHY_MODE_CTRL (0x00) -#define USB3_DP_COM_PHY_MODE_DP (0x03) - -#define REG_USB3_DP_COM_SW_RESET (0x04) -#define USB3_DP_COM_SW_RESET_SET (0x01) - -#define REG_USB3_DP_COM_TYPEC_CTRL (0x10) -#define USB3_DP_COM_TYPEC_CTRL_PORTSEL (0x01) -#define USB3_DP_COM_TYPEC_CTRL_PORTSEL_MUX (0x02) - -#define REG_USB3_DP_COM_SWI_CTRL (0x0c) - -#define REG_USB3_DP_COM_POWER_DOWN_CTRL (0x08) -#define USB3_DP_COM_POWER_DOWN_CTRL_SW_PWRDN (0x01) - - - #endif /* _DP_REG_H_ */ -- cgit v1.2.3