From e522c8466d6f8437cf02a34287c8707ef53081ed Mon Sep 17 00:00:00 2001 From: Graf Yang Date: Fri, 8 May 2009 07:42:12 +0000 Subject: Blackfin: work around anomaly 05000287 Make sure we work around anomaly 05000287 by configuring different port preferences for the data cache. Signed-off-by: Graf Yang Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/cplb-mpu/cacheinit.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/blackfin/kernel/cplb-mpu/cacheinit.c b/arch/blackfin/kernel/cplb-mpu/cacheinit.c index c6ff947f9d37..d5a86c3017f7 100644 --- a/arch/blackfin/kernel/cplb-mpu/cacheinit.c +++ b/arch/blackfin/kernel/cplb-mpu/cacheinit.c @@ -55,7 +55,14 @@ void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl) } ctrl = bfin_read_DMEM_CONTROL(); - ctrl |= DMEM_CNTR; + + /* + * Anomaly notes: + * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL + * register, so that the port preferences for DAG0 and DAG1 are set + * to port B + */ + ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0); bfin_write_DMEM_CONTROL(ctrl); SSYNC(); } -- cgit v1.2.3