From aca92be80c008bceeb6fb62fd1d450b5be5d0a4f Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 30 May 2018 14:26:08 +0930 Subject: ARM: dts: aspeed: Fix hwrng register address The register address should be the full address of the rng, not the offset from the start of the SCU. OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 4 ++-- arch/arm/boot/dts/aspeed-g5.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 9354ac92d928..4b2f5fb8aaaf 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -122,9 +122,9 @@ }; }; - rng: hwrng@78 { + rng: hwrng@1e6e2078 { compatible = "timeriomem_rng"; - reg = <0x78 0x4>; + reg = <0x1e6e2078 0x4>; period = <1>; quality = <100>; }; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index f7c33fbcdaee..622e69ef6456 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -163,9 +163,9 @@ }; }; - rng: hwrng@78 { + rng: hwrng@1e6e2078 { compatible = "timeriomem_rng"; - reg = <0x78 0x4>; + reg = <0x1e6e2078 0x4>; period = <1>; quality = <100>; }; -- cgit v1.2.3