From c822e73731fce3b49a4887140878d084d8a44c08 Mon Sep 17 00:00:00 2001
From: Tudor Laurentiu <b10716@freescale.com>
Date: Thu, 21 Aug 2014 12:33:53 +0300
Subject: powerpc/fsl_msi: spread msi ints across different MSIRs
Allocate msis such that each time a new interrupt is requested,
the SRS (MSIR register select) to be used is allocated in a
round-robin fashion.
The end result is that the msi interrupts will be spread across
distinct MSIRs with the main benefit that now users can set
affinity to each msi int through the mpic irq backing up the
MSIR register.
This is achieved with the help of a newly introduced msi bitmap
api that allows specifying the starting point when searching
for a free msi interrupt.
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Mihai Caraman <mihai.caraman@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
arch/powerpc/sysdev/fsl_msi.h | 5 +++++
1 file changed, 5 insertions(+)
(limited to 'arch/powerpc/sysdev/fsl_msi.h')
diff --git a/arch/powerpc/sysdev/fsl_msi.h b/arch/powerpc/sysdev/fsl_msi.h
index 420cfcbdac01..50ec4b04c732 100644
--- a/arch/powerpc/sysdev/fsl_msi.h
+++ b/arch/powerpc/sysdev/fsl_msi.h
@@ -15,6 +15,7 @@
#include <linux/of.h>
#include <asm/msi_bitmap.h>
+#include <asm/atomic.h>
#define NR_MSI_REG_MSIIR 8 /* MSIIR can index 8 MSI registers */
#define NR_MSI_REG_MSIIR1 16 /* MSIIR1 can index 16 MSI registers */
@@ -27,6 +28,8 @@
#define FSL_PIC_IP_IPIC 0x00000002
#define FSL_PIC_IP_VMPIC 0x00000003
+#define FSL_PIC_FTR_MPIC_4_3 0x00000010
+
struct fsl_msi_cascade_data;
struct fsl_msi {
@@ -37,6 +40,8 @@ struct fsl_msi {
u32 msiir_offset; /* Offset of MSIIR, relative to start of CCSR */
u32 ibs_shift; /* Shift of interrupt bit select */
u32 srs_shift; /* Shift of the shared interrupt register select */
+ u32 msir_num; /* Number of available MSIR regs */
+ atomic_t msi_alloc_cnt; /* Counter for MSI hwirq allocations */
void __iomem *msi_regs;
u32 feature;
struct fsl_msi_cascade_data *cascade_array[NR_MSI_REG_MAX];
--
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