From 119537c092638bf8a0672415024639353c773bb1 Mon Sep 17 00:00:00 2001 From: Thiemo Seufer Date: Mon, 19 Mar 2007 00:13:37 +0000 Subject: [MIPS] Misc fixes for plat_irq_dispatch functions o adds missing ST0_IM masks, which caused the logging of valid interrupts as spurious o stops pnx8550 to log every interrupt as spurious o adds cause register masks for ip22/ip32, which caused handling of masked interrupts o removes some superfluous parentheses in the SNI interrupt code Signed-Off-By: Thiemo Seufer Signed-off-by: Ralf Baechle --- arch/mips/sibyte/sb1250/irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips/sibyte/sb1250') diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index 148239446e6e..0e6a13c0bd0e 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c @@ -421,7 +421,7 @@ asmlinkage void plat_irq_dispatch(void) * blasting the high 32 bits. */ - pending = read_c0_cause() & read_c0_status(); + pending = read_c0_cause() & read_c0_status() & ST0_IM; #ifdef CONFIG_SIBYTE_SB1250_PROF if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */ -- cgit v1.2.3