From 24a1c023f3ff3082fee9c019c17e6a34e2ddfe6b Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Mon, 24 Aug 2020 18:32:47 +0200 Subject: MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config option Use a new config option to enable TX49XX I-cache index invalidate workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/mach-sibyte/war.h | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/mips/include/asm/mach-sibyte') diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h index 0e18f0753407..9e006fdcf38a 100644 --- a/arch/mips/include/asm/mach-sibyte/war.h +++ b/arch/mips/include/asm/mach-sibyte/war.h @@ -24,7 +24,6 @@ extern int sb1250_m3_workaround_needed(void); #endif -#define TX49XX_ICACHE_INDEX_INV_WAR 0 #define ICACHE_REFILLS_WORKAROUND_WAR 0 #define R10000_LLSC_WAR 0 #define MIPS34K_MISSED_ITLB_WAR 0 -- cgit v1.2.3