From 7a2aeb91757b12081e741b436466ec90e6d2c043 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Tue, 12 Jun 2018 13:28:42 -0500 Subject: arm64: dts: freescale: Update to use SPDX identifiers Replace license text with corresponding SPDX identifiers and update the format of existing SPDX identifiers to follow the new guideline Documentation/process/license-rules.rst. Note that some of the files mentioned X11 license previously but the license text actually matches MIT license. Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 39 +------------------------- 1 file changed, 1 insertion(+), 38 deletions(-) (limited to 'arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 136ebfa9b333..ed76325adffd 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -1,47 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Freescale Layerscape-1046A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. * * Mingkai Hu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include -- cgit v1.2.3 From 346f5976cc3200896d5fb873412a4fe9c0fc611e Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 25 May 2018 11:10:02 +0530 Subject: arm64: dts: freescale: Add missing cooling device properties for CPUs The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Do minor rearrangement as well to keep ordering consistent. Signed-off-by: Viresh Kumar Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 5 ++++- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +++ arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 4 ++++ arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++++ 5 files changed, 21 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 8f7ad1db525f..b9f5d2ff4ff2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -43,8 +43,8 @@ reg = <0x0>; clocks = <&clockgen 1 0>; next-level-cache = <&l2>; - #cooling-cells = <2>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -54,6 +54,7 @@ clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -63,6 +64,7 @@ clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -72,6 +74,7 @@ clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; l2: l2-cache { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index ed76325adffd..65ce1c3cb568 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -50,6 +50,7 @@ clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -59,6 +60,7 @@ clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -68,6 +70,7 @@ clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; l2: l2-cache { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 292f186c5ee2..a07f612ab56b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -40,6 +40,7 @@ reg = <0x1>; clocks = <&clockgen 1 0>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -48,6 +49,7 @@ reg = <0x2>; clocks = <&clockgen 1 0>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -56,6 +58,7 @@ reg = <0x3>; clocks = <&clockgen 1 0>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu4: cpu@100 { @@ -73,6 +76,7 @@ reg = <0x101>; clocks = <&clockgen 1 1>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu6: cpu@102 { @@ -81,6 +85,7 @@ reg = <0x102>; clocks = <&clockgen 1 1>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu7: cpu@103 { @@ -89,6 +94,7 @@ reg = <0x103>; clocks = <&clockgen 1 1>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; CPU_PH20: cpu-ph20 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 1292ab98ae9b..f9c1d30cf4a7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -29,6 +29,7 @@ clocks = <&clockgen 1 0>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster0_l2>; + #cooling-cells = <2>; }; cpu2: cpu@100 { @@ -48,6 +49,7 @@ clocks = <&clockgen 1 1>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster1_l2>; + #cooling-cells = <2>; }; cpu4: cpu@200 { @@ -67,6 +69,7 @@ clocks = <&clockgen 1 2>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster2_l2>; + #cooling-cells = <2>; }; cpu6: cpu@300 { @@ -86,6 +89,7 @@ clocks = <&clockgen 1 3>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster3_l2>; + #cooling-cells = <2>; }; cluster0_l2: l2-cache0 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi index d92ea6c11b8e..7c882da3f6b0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -29,6 +29,7 @@ clocks = <&clockgen 1 0>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster0_l2>; + #cooling-cells = <2>; }; cpu2: cpu@100 { @@ -48,6 +49,7 @@ clocks = <&clockgen 1 1>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster1_l2>; + #cooling-cells = <2>; }; cpu4: cpu@200 { @@ -67,6 +69,7 @@ clocks = <&clockgen 1 2>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster2_l2>; + #cooling-cells = <2>; }; cpu6: cpu@300 { @@ -86,6 +89,7 @@ clocks = <&clockgen 1 3>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster3_l2>; + #cooling-cells = <2>; }; cluster0_l2: l2-cache0 { -- cgit v1.2.3