From c9812d042a21eb492a36cfabf9f41107f5ecee3d Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 19 Jun 2009 19:08:26 -0600 Subject: OMAP3 clock: add a short delay when lowering CORE clk rate When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2 divider, add a short delay before returning to SDRAM to allow the SDRC time to stabilize. Without this delay, the system is prone to random panics upon re-entering SDRAM. This time delay varies based on MPU frequency. At 500MHz MPU frequency at room temperature, 64 loops seems to work okay; so add another 32 loops for environmental and process variation. Signed-off-by: Paul Walmsley --- arch/arm/plat-omap/include/mach/sram.h | 4 ++-- arch/arm/plat-omap/sram.c | 8 +++++--- 2 files changed, 7 insertions(+), 5 deletions(-) (limited to 'arch/arm/plat-omap') diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h index dca7c16ae903..c32fa0a220dc 100644 --- a/arch/arm/plat-omap/include/mach/sram.h +++ b/arch/arm/plat-omap/include/mach/sram.h @@ -24,7 +24,7 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, - u32 unlock_dll); + u32 unlock_dll, u32 f); /* Do not use these */ extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); @@ -62,7 +62,7 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz; extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, - u32 unlock_dll); + u32 unlock_dll, u32 f); extern unsigned long omap3_sram_configure_core_dpll_sz; #endif diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index a5b9bcd6b108..79c0f0254426 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -371,15 +371,17 @@ static inline int omap243x_sram_init(void) static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, - u32 m2, u32 unlock_dll); + u32 m2, u32 unlock_dll, + u32 f); u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, - u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll) + u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll, + u32 f) { BUG_ON(!_omap3_sram_configure_core_dpll); return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl, sdrc_actim_ctrla, sdrc_actim_ctrlb, m2, - unlock_dll); + unlock_dll, f); } /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ -- cgit v1.2.3 From d0ba3922ae241a87d22a1c3ffad72b96fe993c9a Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 19 Jun 2009 19:08:27 -0600 Subject: OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change Program the SDRC_MR_0 register as well during SDRC clock changes. This register allows selection of the memory CAS latency. Some SDRAM chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency at lower clock rates. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock34xx.c | 4 ++-- arch/arm/mach-omap2/sram34xx.S | 8 +++++++- arch/arm/plat-omap/include/mach/sram.h | 4 ++-- arch/arm/plat-omap/sram.c | 6 +++--- 4 files changed, 14 insertions(+), 8 deletions(-) (limited to 'arch/arm/plat-omap') diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 4bfa650bb34b..cf41ab55fa97 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -771,9 +771,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) /* REVISIT: SRAM code doesn't support other M2 divisors yet */ WARN_ON(new_div != 1 && new_div != 2); - /* REVISIT: Add SDRC_MR changing to this code also */ omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, - sp->actim_ctrlb, new_div, unlock_dll, c); + sp->actim_ctrlb, new_div, unlock_dll, c, + sp->mr); return 0; } diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 8d4a88c30718..d13f1cc4bd58 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -44,12 +44,14 @@ * SDRC rates < 83MHz * r5 = number of MPU cycles to wait for SDRC to stabilize after * reprogramming the SDRC when switching to a slower MPU speed + * r6 = SDRC_MR_0 register value * */ ENTRY(omap3_sram_configure_core_dpll) stmfd sp!, {r1-r12, lr} @ store regs to stack ldr r4, [sp, #52] @ pull extra args off the stack ldr r5, [sp, #56] @ load extra args from the stack + ldr r6, [sp, #60] @ load extra args from the stack dsb @ flush buffered writes to interconnect cmp r3, #0x2 blne configure_sdrc @@ -151,7 +153,9 @@ configure_sdrc: str r1, [r11] ldr r11, omap3_sdrc_actim_ctrlb str r2, [r11] - ldr r2, [r11] @ posted-write barrier for SDRC + ldr r11, omap3_sdrc_mr_0 + str r6, [r11] + ldr r6, [r11] @ posted-write barrier for SDRC bx lr omap3_sdrc_power: @@ -168,6 +172,8 @@ omap3_sdrc_actim_ctrla: .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0) omap3_sdrc_actim_ctrlb: .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0) +omap3_sdrc_mr_0: + .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0) omap3_sdrc_dlla_status: .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) omap3_sdrc_dlla_ctrl: diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h index c32fa0a220dc..4f87056a3677 100644 --- a/arch/arm/plat-omap/include/mach/sram.h +++ b/arch/arm/plat-omap/include/mach/sram.h @@ -24,7 +24,7 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, - u32 unlock_dll, u32 f); + u32 unlock_dll, u32 f, u32 sdrc_mr); /* Do not use these */ extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); @@ -62,7 +62,7 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz; extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, - u32 unlock_dll, u32 f); + u32 unlock_dll, u32 f, u32 sdrc_mr); extern unsigned long omap3_sram_configure_core_dpll_sz; #endif diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 79c0f0254426..7dadf1a59fb5 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -372,16 +372,16 @@ static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll, - u32 f); + u32 f, u32 sdrc_mr); u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll, - u32 f) + u32 f, u32 sdrc_mr) { BUG_ON(!_omap3_sram_configure_core_dpll); return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl, sdrc_actim_ctrla, sdrc_actim_ctrlb, m2, - unlock_dll, f); + unlock_dll, f, sdrc_mr); } /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ -- cgit v1.2.3 From 3afec6332e1e7cf2d74e0bf08160a68f43a59073 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 19 Jun 2009 19:08:29 -0600 Subject: OMAP3: Add support for DPLL3 divisor values higher than 2 Previously only 1 and 2 was supported. This is needed for DVFS VDD2 control. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clock34xx.c | 9 +++------ arch/arm/mach-omap2/sram34xx.S | 8 +++++--- arch/arm/plat-omap/include/mach/sram.h | 6 ++++-- arch/arm/plat-omap/sram.c | 6 +++--- 4 files changed, 15 insertions(+), 14 deletions(-) (limited to 'arch/arm/plat-omap') diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index cf41ab55fa97..045da923e75b 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -739,9 +739,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) sdrcrate = sdrc_ick.rate; if (rate > clk->rate) - sdrcrate <<= ((rate / clk->rate) - 1); + sdrcrate <<= ((rate / clk->rate) >> 1); else - sdrcrate >>= ((clk->rate / rate) - 1); + sdrcrate >>= ((clk->rate / rate) >> 1); sp = omap2_sdrc_get_params(sdrcrate); if (!sp) @@ -768,12 +768,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) pr_debug("clock: SDRC timing params used: %08x %08x %08x\n", sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb); - /* REVISIT: SRAM code doesn't support other M2 divisors yet */ - WARN_ON(new_div != 1 && new_div != 2); - omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb, new_div, unlock_dll, c, - sp->mr); + sp->mr, rate > clk->rate); return 0; } diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 16eb4efa8b74..487fa8609cde 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -70,6 +70,7 @@ * r5 = number of MPU cycles to wait for SDRC to stabilize after * reprogramming the SDRC when switching to a slower MPU speed * r6 = new SDRC_MR_0 register value + * r7 = increasing SDRC rate? (1 = yes, 0 = no) * */ ENTRY(omap3_sram_configure_core_dpll) @@ -77,9 +78,10 @@ ENTRY(omap3_sram_configure_core_dpll) ldr r4, [sp, #52] @ pull extra args off the stack ldr r5, [sp, #56] @ load extra args from the stack ldr r6, [sp, #60] @ load extra args from the stack + ldr r7, [sp, #64] @ load extra args from the stack dsb @ flush buffered writes to interconnect - cmp r3, #0x2 @ if increasing SDRC clk rate, - blne configure_sdrc @ program the SDRC regs early (for RFR) + cmp r7, #1 @ if increasing SDRC clk rate, + bleq configure_sdrc @ program the SDRC regs early (for RFR) cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state bleq unlock_dll blne lock_dll @@ -89,7 +91,7 @@ ENTRY(omap3_sram_configure_core_dpll) cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change bleq wait_dll_unlock blne wait_dll_lock - cmp r3, #0x1 @ if increasing SDRC clk rate, + cmp r7, #1 @ if increasing SDRC clk rate, beq return_to_sdram @ return to SDRAM code, otherwise, bl configure_sdrc @ reprogram SDRC regs now mov r12, r5 diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h index 4f87056a3677..4d53cc59d7a3 100644 --- a/arch/arm/plat-omap/include/mach/sram.h +++ b/arch/arm/plat-omap/include/mach/sram.h @@ -24,7 +24,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, - u32 unlock_dll, u32 f, u32 sdrc_mr); + u32 unlock_dll, u32 f, u32 sdrc_mr, + u32 inc); /* Do not use these */ extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); @@ -62,7 +63,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz; extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, - u32 unlock_dll, u32 f, u32 sdrc_mr); + u32 unlock_dll, u32 f, u32 sdrc_mr, + u32 inc); extern unsigned long omap3_sram_configure_core_dpll_sz; #endif diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 7dadf1a59fb5..65006df3f1b7 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -372,16 +372,16 @@ static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll, - u32 f, u32 sdrc_mr); + u32 f, u32 sdrc_mr, u32 inc); u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll, - u32 f, u32 sdrc_mr) + u32 f, u32 sdrc_mr, u32 inc) { BUG_ON(!_omap3_sram_configure_core_dpll); return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl, sdrc_actim_ctrla, sdrc_actim_ctrlb, m2, - unlock_dll, f, sdrc_mr); + unlock_dll, f, sdrc_mr, inc); } /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ -- cgit v1.2.3