From bc0ee9d24ad21a5c2b5944f66623a02e9c8831aa Mon Sep 17 00:00:00 2001 From: Jonathan Austin Date: Tue, 30 Aug 2016 17:31:22 +0100 Subject: ARM: 8607/1: V7M: Wire up caches for V7M processors with cache support. This patch does the plumbing required to invoke the V7M cache code added in earlier patches in this series, although there is no users for that yet. In order to honour the I/D cache disable config options, this patch changes the mechanism by which the CCR is set on boot, to be more like V7A/R. Signed-off-by: Jonathan Austin Signed-off-by: Vladimir Murzin Tested-by: Andras Szemzo Tested-by: Joachim Eastwood Tested-by: Alexandre TORGUE Signed-off-by: Russell King --- arch/arm/mm/proc-v7m.S | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'arch/arm/mm/proc-v7m.S') diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S index 7229d8d0be1a..11f5816e2680 100644 --- a/arch/arm/mm/proc-v7m.S +++ b/arch/arm/mm/proc-v7m.S @@ -118,9 +118,8 @@ __v7m_setup: @ Configure the System Control Register to ensure 8-byte stack alignment @ Note the STKALIGN bit is either RW or RAO. - ldr r12, [r0, V7M_SCB_CCR] @ system control register - orr r12, #V7M_SCB_CCR_STKALIGN - str r12, [r0, V7M_SCB_CCR] + ldr r0, [r0, V7M_SCB_CCR] @ system control register + orr r0, #V7M_SCB_CCR_STKALIGN ret lr ENDPROC(__v7m_setup) -- cgit v1.2.3