From 11f1ca10b668995a031aade5c2728f0a251aaec7 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 5 Jun 2014 14:31:56 +0900 Subject: ARM: shmobile: Update EMEV2 DTS to include CPU frequency Add CPU Frequency information to the EMEV2 DTS file. This will allow us to use the shared C code to on EMEV2 which reads out the clock frequency from DT and calculates the delay settings from there. Signed-off-by: Magnus Damm Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/emev2.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index e37985fa10e2..00eeed3721b6 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -31,11 +31,13 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clock-frequency = <533000000>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clock-frequency = <533000000>; }; }; -- cgit v1.2.3 From 005407fdf1c65a06fc0a9c588408f57e2eacef7c Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 6 Jun 2014 14:28:49 +0900 Subject: ARM: shmobile: Update r7s72100 DTS to include CPU frequency Add CPU Frequency information to the r7s72100 DTS file. This will allow us to use the shared C code on r7s72100 and Genmai which reads out the clock frequency from DT and calculates the delay settings from there. Signed-off-by: Magnus Damm Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index f50fbc8f3bd9..bdee22541189 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -144,6 +144,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clock-frequency = <400000000>; }; }; -- cgit v1.2.3 From e6dc195c1c69ea525f5001f72d666ac8342139e4 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 14 Feb 2014 10:26:15 +0100 Subject: ARM: integrator: get rid of The Integrator has a custom header defining the BUS_OFFSET for *_to_bus and bus_to_* operations as offset from 0x80000000. This switches the Integrator over to using the mechanism introduced for the Keystone to provide the same offset using the device tree, deletes and augments the Integrator device tree to provide the bus offset. Cc: Grygorii Strashko Cc: Will Deacon Cc: Jonathan Austin Cc: Russell King Acked-by: Santosh Shilimkar Signed-off-by: Linus Walleij --- arch/arm/Kconfig | 1 - arch/arm/boot/dts/integratorap.dts | 1 + arch/arm/mach-integrator/include/mach/memory.h | 34 -------------------------- 3 files changed, 1 insertion(+), 35 deletions(-) delete mode 100644 arch/arm/mach-integrator/include/mach/memory.h (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 245058b3b0ef..06aab1024305 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -320,7 +320,6 @@ config ARCH_INTEGRATOR select HAVE_TCM select ICST select MULTI_IRQ_HANDLER - select NEED_MACH_MEMORY_H select PLAT_VERSATILE select SPARSE_IRQ select USE_OF diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts index b10e6351da53..cf06e32ee108 100644 --- a/arch/arm/boot/dts/integratorap.dts +++ b/arch/arm/boot/dts/integratorap.dts @@ -8,6 +8,7 @@ / { model = "ARM Integrator/AP"; compatible = "arm,integrator-ap"; + dma-ranges = <0x80000000 0x0 0x80000000>; aliases { arm,timer-primary = &timer2; diff --git a/arch/arm/mach-integrator/include/mach/memory.h b/arch/arm/mach-integrator/include/mach/memory.h deleted file mode 100644 index 334d5e271889..000000000000 --- a/arch/arm/mach-integrator/include/mach/memory.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * arch/arm/mach-integrator/include/mach/memory.h - * - * Copyright (C) 1999 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -/* - * Physical DRAM offset. - */ -#define PLAT_PHYS_OFFSET UL(0x00000000) - -#define BUS_OFFSET UL(0x80000000) -#define __virt_to_bus(x) ((x) - PAGE_OFFSET + BUS_OFFSET) -#define __bus_to_virt(x) ((x) - BUS_OFFSET + PAGE_OFFSET) -#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - PHYS_OFFSET)) -#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - PHYS_OFFSET)) - -#endif -- cgit v1.2.3 From 07b9b3d9e429728c89586a54a2ed715b2a7b0edf Mon Sep 17 00:00:00 2001 From: "Andrii.Tseglytskyi" Date: Thu, 5 Jun 2014 20:11:12 -0500 Subject: ARM: dts: OMAP5: Add device nodes for ABB Add ABB device nodes for OMAP5 family of devices. Data is based on final production OMAP543x Technical Reference Manual revision Z (April 2013). Final production Data Manual for OMAP5432 SWPS050F(APRIL 2014). [nm@ti.com: co-developer and updates to latest documentation] Signed-off-by: Nishanth Menon Signed-off-by: Andrii.Tseglytskyi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5.dtsi | 60 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index a4ed54988866..8eee6fbef7ad 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -985,6 +985,66 @@ dma-names = "audio_tx"; }; }; + + abb_mpu: regulator-abb-mpu { + compatible = "ti,abb-v2"; + regulator-name = "abb_mpu"; + #address-cells = <0>; + #size-cells = <0>; + clocks = <&sys_clkin>; + ti,settling-time = <50>; + ti,clock-cycles = <16>; + + reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>, + <0x4a0021c4 0x8>, <0x4ae0c318 0x4>; + reg-names = "base-address", "int-address", + "efuse-address", "ldo-address"; + ti,tranxdone-status-mask = <0x80>; + /* LDOVBBMPU_MUX_CTRL */ + ti,ldovbb-override-mask = <0x400>; + /* LDOVBBMPU_VSET_OUT */ + ti,ldovbb-vset-mask = <0x1F>; + + /* + * NOTE: only FBB mode used but actual vset will + * determine final biasing + */ + ti,abb_info = < + /*uV ABB efuse rbb_m fbb_m vset_m*/ + 1060000 0 0x0 0 0x02000000 0x01F00000 + 1250000 0 0x4 0 0x02000000 0x01F00000 + >; + }; + + abb_mm: regulator-abb-mm { + compatible = "ti,abb-v2"; + regulator-name = "abb_mm"; + #address-cells = <0>; + #size-cells = <0>; + clocks = <&sys_clkin>; + ti,settling-time = <50>; + ti,clock-cycles = <16>; + + reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>, + <0x4a0021a4 0x8>, <0x4ae0c314 0x4>; + reg-names = "base-address", "int-address", + "efuse-address", "ldo-address"; + ti,tranxdone-status-mask = <0x80000000>; + /* LDOVBBMM_MUX_CTRL */ + ti,ldovbb-override-mask = <0x400>; + /* LDOVBBMM_VSET_OUT */ + ti,ldovbb-vset-mask = <0x1F>; + + /* + * NOTE: only FBB mode used but actual vset will + * determine final biasing + */ + ti,abb_info = < + /*uV ABB efuse rbb_m fbb_m vset_m*/ + 1025000 0 0x0 0 0x02000000 0x01F00000 + 1120000 0 0x4 0 0x02000000 0x01F00000 + >; + }; }; }; -- cgit v1.2.3 From 155dfc7b543345ed45521900bbd32c0db4ea266e Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Thu, 12 Jun 2014 18:36:38 +0300 Subject: soc/tegra: Add efuse and apbmisc bindings Add efuse and apbmisc bindings for Tegra20, Tegra30, Tegra114 and Tegra124. Signed-off-by: Peter De Schrijver Signed-off-by: Stephen Warren Signed-off-by: Thierry Reding --- .../bindings/fuse/nvidia,tegra20-fuse.txt | 40 ++++++++++++++++++++++ .../bindings/misc/nvidia,tegra20-apbmisc.txt | 13 +++++++ arch/arm/boot/dts/tegra114.dtsi | 15 ++++++++ arch/arm/boot/dts/tegra124.dtsi | 15 ++++++++ arch/arm/boot/dts/tegra20.dtsi | 15 ++++++++ arch/arm/boot/dts/tegra30.dtsi | 15 ++++++++ 6 files changed, 113 insertions(+) create mode 100644 Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt (limited to 'arch/arm/boot/dts') diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt new file mode 100644 index 000000000000..d8c98c7614d0 --- /dev/null +++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt @@ -0,0 +1,40 @@ +NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block. + +Required properties: +- compatible : should be: + "nvidia,tegra20-efuse" + "nvidia,tegra30-efuse" + "nvidia,tegra114-efuse" + "nvidia,tegra124-efuse" + Details: + nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data + due to a hardware bug. Tegra20 also lacks certain information which is + available in later generations such as fab code, lot code, wafer id,.. + nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse: + The differences between these SoCs are the size of the efuse array, + the location of the spare (OEM programmable) bits and the location of + the speedo data. +- reg: Should contain 1 entry: the entry gives the physical address and length + of the fuse registers. +- clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - fuse +- resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names: Must include the following entries: + - fuse + +Example: + + fuse@7000f800 { + compatible = "nvidia,tegra20-efuse"; + reg = <0x7000F800 0x400>, + <0x70000000 0x400>; + clocks = <&tegra_car TEGRA20_CLK_FUSE>; + clock-names = "fuse"; + resets = <&tegra_car 39>; + reset-names = "fuse"; + }; + + diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt new file mode 100644 index 000000000000..b97b8bef1fe5 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt @@ -0,0 +1,13 @@ +NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 apbmisc block + +Required properties: +- compatible : should be: + "nvidia,tegra20-apbmisc" + "nvidia,tegra30-apbmisc" + "nvidia,tegra114-apbmisc" + "nvidia,tegra124-apbmisc" +- reg: Should contain 2 entries: the first entry gives the physical address + and length of the registers which contain revision and debug features. + The second entry gives the physical address and length of the + registers indicating the strapping options. + diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index fdc559ab2db3..335a1d8047f2 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -220,6 +220,12 @@ interrupt-controller; }; + apbmisc@70000800 { + compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; + reg = <0x70000800 0x64 /* Chip revision */ + 0x70000008 0x04>; /* Strapping options */ + }; + pinmux: pinmux@70000868 { compatible = "nvidia,tegra114-pinmux"; reg = <0x70000868 0x148 /* Pad control registers */ @@ -485,6 +491,15 @@ clock-names = "pclk", "clk32k_in"; }; + fuse@7000f800 { + compatible = "nvidia,tegra114-efuse"; + reg = <0x7000f800 0x400>; + clocks = <&tegra_car TEGRA114_CLK_FUSE>; + clock-names = "fuse"; + resets = <&tegra_car 39>; + reset-names = "fuse"; + }; + iommu@70019010 { compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; reg = <0x70019010 0x02c diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 6e6bc4e8185c..226941c07d15 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -179,6 +179,12 @@ #dma-cells = <1>; }; + apbmisc@0,70000800 { + compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; + reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ + <0x0 0x7000E864 0x0 0x04>; /* Strapping options */ + }; + pinmux: pinmux@0,70000868 { compatible = "nvidia,tegra124-pinmux"; reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ @@ -449,6 +455,15 @@ clock-names = "pclk", "clk32k_in"; }; + fuse@0,7000f800 { + compatible = "nvidia,tegra124-efuse"; + reg = <0x0 0x7000f800 0x0 0x400>; + clocks = <&tegra_car TEGRA124_CLK_FUSE>; + clock-names = "fuse"; + resets = <&tegra_car 39>; + reset-names = "fuse"; + }; + sdhci@0,700b0000 { compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0000 0x0 0x200>; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index a7ddf70df50b..243d84cdbae8 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -236,6 +236,12 @@ interrupt-controller; }; + apbmisc@70000800 { + compatible = "nvidia,tegra20-apbmisc"; + reg = <0x70000800 0x64 /* Chip revision */ + 0x70000008 0x04>; /* Strapping options */ + }; + pinmux: pinmux@70000014 { compatible = "nvidia,tegra20-pinmux"; reg = <0x70000014 0x10 /* Tri-state registers */ @@ -545,6 +551,15 @@ #size-cells = <0>; }; + fuse@7000f800 { + compatible = "nvidia,tegra20-efuse"; + reg = <0x7000F800 0x400>; + clocks = <&tegra_car TEGRA20_CLK_FUSE>; + clock-names = "fuse"; + resets = <&tegra_car 39>; + reset-names = "fuse"; + }; + pcie-controller@80003000 { compatible = "nvidia,tegra20-pcie"; device_type = "pci"; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index dec4fc823901..0b1ede940d1f 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -335,6 +335,12 @@ interrupt-controller; }; + apbmisc@70000800 { + compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; + reg = <0x70000800 0x64 /* Chip revision */ + 0x70000008 0x04>; /* Strapping options */ + }; + pinmux: pinmux@70000868 { compatible = "nvidia,tegra30-pinmux"; reg = <0x70000868 0xd4 /* Pad control registers */ @@ -631,6 +637,15 @@ nvidia,ahb = <&ahb>; }; + fuse@7000f800 { + compatible = "nvidia,tegra30-efuse"; + reg = <0x7000f800 0x400>; + clocks = <&tegra_car TEGRA30_CLK_FUSE>; + clock-names = "fuse"; + resets = <&tegra_car 39>; + reset-names = "fuse"; + }; + ahub@70080000 { compatible = "nvidia,tegra30-ahub"; reg = <0x70080000 0x200 -- cgit v1.2.3