From b89c429c1b4c176fee1912114ec7b2785949783b Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Thu, 1 Oct 2015 17:42:20 +0200 Subject: ARM: dts: Fix RGMII pinctrl timings These new re-timing values provides a better stability on Ethernet link. Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih407-pinctrl.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index 8fe542aa1fa4..a538ae52d32b 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -216,9 +216,9 @@ rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>; rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>; rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 500 CLK_A>; + rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT4 OUT NICLK 1750 CLK_B>; + phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>; }; }; -- cgit v1.2.3 From ab511d7df1a0f73c4ccccd5655c84efdb7f816c1 Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Thu, 1 Oct 2015 17:44:41 +0200 Subject: ARM: dts: Add Ethernet node to STiH407 family STiH407 family uses the Synopsys IP. Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih407-family.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 582154bbe3f3..c944d3a5906d 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -653,5 +653,32 @@ clocks = <&clk_sysin>; status = "okay"; }; + + ethernet0: dwmac@9630000 { + device_type = "network"; + status = "disabled"; + compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; + reg = <0x9630000 0x8000>, <0x80 0x4>; + reg-names = "stmmaceth", "sti-ethconf"; + + st,syscon = <&syscfg_sbc_reg 0x80>; + st,gmac_en; + resets = <&softreset STIH407_ETH1_SOFTRESET>; + reset-names = "stmmaceth"; + + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + + /* DMA Bus Mode */ + snps,pbl = <8>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>; + + clock-names = "stmmaceth", "sti-ethclk"; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>, + <&clk_s_c0_flexgen CLK_ETH_PHY>; + }; }; }; -- cgit v1.2.3 From 60dfa24588ee76b85f48c2adab5cdf9b868dc629 Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Thu, 1 Oct 2015 17:45:46 +0200 Subject: ARM: dts: Enable Ethernet on STi's B2120 boards These boards are mounted with Realtek RTL8367 switch. We consider the bootloader will have intiliazed the switch before jumping into the kernel, so we declare it as a fixed link. Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih407-b2120.dts | 1 + arch/arm/boot/dts/stih410-b2120.dts | 1 + arch/arm/boot/dts/stihxxx-b2120.dtsi | 6 ++++++ 3 files changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts index 6d93475be554..c8ad905d0309 100644 --- a/arch/arm/boot/dts/stih407-b2120.dts +++ b/arch/arm/boot/dts/stih407-b2120.dts @@ -25,6 +25,7 @@ aliases { ttyAS0 = &sbc_serial0; + ethernet0 = ðernet0; }; }; diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts index 8af1e73c0532..118ac284fc4b 100644 --- a/arch/arm/boot/dts/stih410-b2120.dts +++ b/arch/arm/boot/dts/stih410-b2120.dts @@ -25,6 +25,7 @@ aliases { ttyAS0 = &sbc_serial0; + ethernet0 = ðernet0; }; soc { diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi index ab029f7239b2..ad21a4293a33 100644 --- a/arch/arm/boot/dts/stihxxx-b2120.dtsi +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi @@ -87,5 +87,11 @@ status = "okay"; }; + ethernet0: dwmac@9630000 { + st,tx-retime-src = "clkgen"; + status = "okay"; + phy-mode = "rgmii"; + fixed-link = <0 1 1000 0 0>; + }; }; }; -- cgit v1.2.3 From 69e7c854c7d4ea30c4e17cfa890946e16c5a36f0 Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Thu, 1 Oct 2015 17:48:19 +0200 Subject: ARM: dts: Enable Ethernet on STi's B2199 board The B2199 board is mounted with Realtek RTL8367 switch. We consider the bootloader will have intiliazed the switch before jumping into the kernel, so we declare it as a fixed link. Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih418-b2199.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts index 82eee39ccb31..772d2bb07e5f 100644 --- a/arch/arm/boot/dts/stih418-b2199.dts +++ b/arch/arm/boot/dts/stih418-b2199.dts @@ -24,6 +24,7 @@ aliases { ttyAS0 = &sbc_serial0; + ethernet0 = ðernet0; }; soc { @@ -101,5 +102,12 @@ st_dwc3: dwc3@8f94000 { status = "okay"; }; + + ethernet0: dwmac@9630000 { + st,tx-retime-src = "clkgen"; + status = "okay"; + phy-mode = "rgmii"; + fixed-link = <0 1 1000 0 0>; + }; }; }; -- cgit v1.2.3 From 848dd6a87a10bd24b5a4c8b84eaba3cdd0ec7a19 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Wed, 7 Oct 2015 11:08:00 +0200 Subject: ARM: STi: DT: Add support for stih418 A9 pll Add support for new PLL-type for stih418 A9-PLL. Signed-off-by: Gabriel Fernandez Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih418-clock.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi index 148e1772465f..ae6d9978ea19 100644 --- a/arch/arm/boot/dts/stih418-clock.dtsi +++ b/arch/arm/boot/dts/stih418-clock.dtsi @@ -44,7 +44,7 @@ clockgen_a9_pll: clockgen-a9-pll { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"; + compatible = "st,stih418-plls-c28-a9", "st,clkgen-plls-c32"; clocks = <&clk_sysin>; -- cgit v1.2.3