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2017-05-29clk: meson-gxbb: expose spdif master clockJerome Brunet1-0/+2
Expose the spdif master clock and the mux to select the appropriate spdif clock parent depending on the data source. Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-05-29clk: meson-gxbb: expose i2s master clockJerome Brunet1-0/+1
Expose cts_amclk in the device tree bindings Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-05-29clk: meson-gxbb: expose spdif clock gatesJerome Brunet1-0/+2
Expose the clock gates required for the spdif output Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-05-24clk: renesas: Add r8a7794 CPG Core Clock DefinitionsGeert Uytterhoeven1-0/+47
Add all R-Car E2 Clock Pulse Generator Core Clock Outputs, as listed in Table 7.2d ("List of Clocks [R-Car E2]") of the R-Car Gen2 Hardware User's Manual rev. 2.00. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2017-05-24clk: renesas: Add r8a7793 CPG Core Clock DefinitionsGeert Uytterhoeven1-0/+48
Add all R-Car M2-N Clock Pulse Generator Core Clock Outputs, as listed in Table 7.2b ("List of Clocks [R-Car M2-W/M2-N]") of the R-Car Gen2 Hardware User's Manual rev. 2.00. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2017-05-24clk: renesas: Add r8a7792 CPG Core Clock DefinitionsGeert Uytterhoeven1-0/+43
Add all R-Car V2H Clock Pulse Generator Core Clock Outputs, as listed in Table 7.2c ("List of Clocks [R-Car V2H]") of the R-Car Gen2 Hardware User's Manual rev. 2.00. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2017-05-24clk: renesas: Add r8a7791 CPG Core Clock DefinitionsGeert Uytterhoeven1-0/+48
Add all R-Car M2-W Clock Pulse Generator Core Clock Outputs, as listed in Table 7.2b ("List of Clocks [R-Car M2-W/M2-N]") of the R-Car Gen2 Hardware User's Manual rev. 2.00. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2017-05-24clk: renesas: Add r8a7790 CPG Core Clock DefinitionsGeert Uytterhoeven1-0/+52
Add all R-Car H2 Clock Pulse Generator Core Clock Outputs, as listed in Table 7.2a ("List of Clocks [R-Car H2]") of the R-Car Gen2 Hardware User's Manual rev. 2.00. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2017-05-17clk: rockchip: add clock-ids for more rk3228 clocksElaine Zhang1-0/+47
This patch exports related BUS/VPU/RGA/HDCP/IEP/TSP/WIFI/ VIO/USB/EFUSE/GPU/CRYPTO clocks for dts reference. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-05-17clk: rockchip: add ids for camera on rk3399Eddie Cai1-0/+2
we use SCLK_TESTCLKOUT1 and SCLK_TESTCLKOUT2 for camera, so add those ids. Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-05-15ARM: dts: r7s72100: add USB bit definitionsChris Brandt1-0/+2
Add the bit locations that correspond to the USB clocks. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-05-15ARM: dts: r8a7791: add GyroADC clockMarek Vasut1-0/+1
Add the GyroADC clock to the R8A7791 device tree. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-05-10Merge tag 'clk-for-linus' of ↵Linus Torvalds12-27/+395
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Sort of on the quieter side this time, which is probably due more to me not catching up as quickly on patch review than anything else. Overall it seems normal though, a few small changes to the core, mostly small non-critical fixes here and there as well as driver updates for new and existing hardware support. The biggest things are the TI clk driver rework to lay the groundwork for clkctrl support in the next merge window and the AmLogic audio/graphics clk support. Core: - clk_possible_parents debugfs file so we know which parents a clk could possibly have - Fix to make clk rate change notifiers stop on the first failure instead of continuing New Drivers: - Mediatek MT6797 SoCs - hi655x PMIC clks - AmLogic Meson SoC i2s and spdif audio clks and Mali graphics clks - Allwinner H5 SoCs and PRCM hardware Updates: - Nvidia Tegra T210 cleanups and non-critical fixes - TI OMAP cleanups in preparation for clkctrl support - trivial fixes like kcalloc(), devm_* conversions, and seq_puts() - ZTE zx296718 SoC VGA clks - Rockchip clk-ids, fixups, and rename of rk1108 to rv1108 - IDT VersaClock 5P49V5935 support - Renesas R-Car H3 and M3-W IMR clks and ES2.0 rev of R-Car H3 support" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (151 commits) clk: x86: pmc-atom: Checking for IS_ERR() instead of NULL clk: ti: divider: try to fix ti_clk_register_divider clk: mvebu: Use kcalloc() in two functions clk: mvebu: Use kcalloc() in of_cpu_clk_setup() clk: nomadik: Delete error messages for a failed memory allocation in two functions clk: nomadik: Use seq_puts() in nomadik_src_clk_show() clk: Improve a size determination in two functions clk: Replace four seq_printf() calls by seq_putc() clk: si5351: Delete an error message for a failed memory allocation in si5351_i2c_probe() clk: si5351: Use devm_kcalloc() in si5351_i2c_probe() clk: at91: Use kcalloc() in of_at91_clk_pll_get_characteristics() reset: mediatek: Add MT2701 ethsys reset controller include file clk: mediatek: add mt2701 ethernet reset clk: hi6220: Add the hi655x's pmic clock clk: ti: fix building without legacy omap3 clk: ti: fix linker error with !SOC_OMAP4 clk: hi3620: Fix a typo in one variable name clk: hi3620: Delete error messages for a failed memory allocation in two functions clk: hi3620: Use kcalloc() in hi3620_mmc_clk_init() clk: hisilicon: Delete error messages for failed memory allocations in hisi_clk_init() ...
2017-05-09Merge tag 'armsoc-dt64' of ↵Linus Torvalds1-0/+11
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM 64-bit DT updates from Olof Johansson: "Device-tree updates for arm64 platforms. Just as with 32-bit, a bunch of smaller changes, but also some new platforms that are worth mentioning: - Rockchip RK3399 platforms for Chromebooks, including Samsung Chromebook Plus (Kevin) - Orange Pi PC2 (Allwinner H5) - Freescale LS2088A and LS1088A SoCs - Expanded support for Nvidia Tegra186 (and Jetson TX2)" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (180 commits) arm64: dts: Add basic DT to support Spreadtrum's SP9860G arm64: dts: exynos: Use - instead of @ for DT OPP entries arm64: dts: exynos: Add support for s6e3hf2 panel device on TM2e board arm64: dts: juno: add information about L1 and L2 caches arm64: dts: juno: fix few unit address format warnings arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB arm64: marvell: dts: add crypto engine description for 7k/8k arm64: dts: marvell: add sdhci support for Armada 7K/8K arm64: dts: marvell: add eMMC support for Armada 37xx arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board arm64: dts: hisi: add SAS nodes for the hip07 SoC arm64: dts: hisi: add RoCE nodes for the hip07 SoC arm64: dts: hisi: add network related nodes for the hip07 SoC arm64: dts: hisi: add mbigen nodes for the hip07 SoC arm64: dts: rockchip: fix the memory size of PX5 Evaluation board arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board ...
2017-05-09Merge tag 'armsoc-dt' of ↵Linus Torvalds7-5/+16
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM Device-tree updates from Olof Johansson: "Device-tree continues to see lots of updates. The majority of patches here are smaller changes for new hardware on existing platforms, and there are a few larger changes worth pointing out. Major new platforms: - Gemini has been ported to DT, so a handful of "new" platforms moved over from board files - Rockchip RK3288 support for Tinkerboard and Phytec phyCORE-RK3288 SoM and RDK - A bunch of embedded platforms, several Linksys platforms, Synology DS116, - Motorola Droid4 (really old OMAP-based phone) support is added. Some refactorings, i.e. Allwinner H3/H5 support is commonalized. And lots of smaller changes, cleanups, etc. See shortlog for more description We're adding ability to cross-include DT files between arm and arm64, by creating appropriate links in the dt-include directory, and using arm/ and arm64/ as include prefixes. This will avoid other local hacks such as per-file links between the two arch trees (this broke for external mirroring of DT contents). Now they can just provide their own appropriate dt-include hierarcy per platform" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (349 commits) ARM: dts: exynos: Use - instead of @ for DT OPP entries arm: spear6xx: add DT description of the ADC on SPEAr600 arm: spear6xx: remove unneeded pinctrl properties in spear600-evb arm: spear6xx: switch spear600-evb to the new flash partition DT binding arm: spear6xx: fix spaces in spear600-evb.dts arm: spear6xx: use node labels in spear600-evb.dts arm: spear6xx: add labels to various nodes in spear600.dtsi ARM: dts: vexpress: fix few unit address format warnings ARM: dts: at91: sama5d3_xplained: not all ADC channels are available ARM: dts: at91: sama5d3_xplained: fix ADC vref ARM: dts: at91: add envelope detector mux to the Axentia TSE-850 ARM: dts: armada-38x: label USB and SATA nodes ARM: dts: imx6q-utilite-pro: add hpd gpio ARM: dts: imx6qp-sabresd: Set reg_arm regulator supply ARM: dts: imx6qdl-sabresd: Set LDO regulator supply ARM: dts: imx: add Gateworks Ventana GW5903 support ARM: dts: i.MX25: add AIPS control registers ARM: dts: imx7-colibri: add Carrier Board 3.3V/5V regulators ARM: dts: imx7-colibri: remove 1.8V fixed regulator ARM: dts: imx7-colibri: allow to disable Ethernet rail ...
2017-04-19Merge branch 'clk-mt6797' into clk-nextStephen Boyd1-0/+281
* clk-mt6797: clk: mediatek: add mt6797 clock IDs
2017-04-19clk: mediatek: add mt6797 clock IDsMars Cheng1-0/+281
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19Merge tag 'sunxi-clk-for-4.12' of ↵Stephen Boyd2-1/+63
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next Pull Allwinner clock patches for 4.12 from Maxime Ripard: Support for the new H5 SoC and the PRCM block found in a number of SoCs as well, plus the usual chunk of fixes and minor enhancements. * tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: Display index when clock registration fails clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocks clk: sunxi-ng: mult: Support PLL lock detection clk: sunxi-ng: add support for PRCM CCUs dt-bindings: update device tree binding for Allwinner PRCM CCUs clk: sunxi-ng: sun5i: Fix mux width for csi clock clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver clk: sunxi-ng: gate: Support common pre-dividers
2017-04-12Merge tag 'amlogic-clk' of ↵Michael Turquette1-0/+11
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into clk-next Same great taste as the previous pull request, but now with 50% less DT bikeshedding! Amlogic clock driver updates for v4.12 - meson8: add some new PLLs - new clocks for Mali - misc fixes.
2017-04-12Merge tag 'tegra-for-4.12-clk' of ↵Michael Turquette4-15/+24
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next Pull Tegra clk driver updates from Thierry Reding: This contains a bunch of fixes and cleanups, mostly to the Tegra210 clock driver. * tag 'tegra-for-4.12-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (24 commits) clk: tegra: Don't reset PLL-CX if it is already enabled clk: tegra: Add missing Tegra210 clocks clk: tegra: Propagate clk_out_x rate to parent clk: tegra: Fix build warnings on Tegra20/Tegra30 clk: tegra: Mark TEGRA210_CLK_DBGAPB as always on clk: tegra: Add SATA seq input control clk: tegra: Add Tegra210 special resets clk: tegra: Rework pll_u clk: tegra: Implement reset control reset clk: tegra: Fix disable unused for clocks sharing enable bit clk: tegra: Handle UTMIPLL IDDQ clk: tegra: Add aclk clk: tegra: Add super clock mux/divider clk: tegra: Define Tegra210 DMIC clocks clk: tegra: Fix constness for peripheral clocks clk: tegra: Define Tegra210 DMIC sync clocks clk: tegra: Add CEC clock clk: tegra: Fix type for m field clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculation clk: tegra: Don't warn for PLL defaults unnecessarily ...
2017-04-12Merge tag 'v4.12-rockchip-clk1' of ↵Michael Turquette3-10/+16
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk driver updates from Heiko Stuebner: General rockchip clock changes for 4.12. Contains some new clock-ids as well as fixups of the clock-ids on rk3368 timers, which were unused and completely wrong (more and differently named timers). Also there is one new clock on rk3328 using the muxgrf type, a fix for pll enablement which should wait for the pll to lock before continuing, some more critical clocks and the rename of the rk1108 to rv1108, as the soc seems to have been using a preliminary name before its actual release. The plan is to have the driver changes (pinctrl, clk) go through the respective maintainer trees and once everything landed in mainline do the rename of the devicetree files. With the dts-include change in the clock rename, we also keep everything compiling and thus bisectability. * tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: add pll_wait_lock for pll_enable clk: rockchip: rename RK1108 to RV1108 dt-bindings: rk1108-cru: rename RK1108 to RV1108 clk: rockchip: mark some rk3368 core-clks as critical clk: rockchip: export SCLK_TIMERXX id for timers on rk3368 clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328 clk: rockchip: add clock ids for timer10-15 of RK3368 SoCs clk: rockchip: fix up rk3368 timer-ids clk: rockchip: add rk3328 clk_mac2io_ext ID clk: rockchip: Set "ignore unused" for PMU M0 clocks on rk3399
2017-04-12Merge tag 'clk-renesas-for-v4.12-tag2' of ↵Michael Turquette1-0/+7
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull Renesas clk driver updates from Geert Uytterhoeven: - Add support for the Clock Pulse Generator / Module Standby and Software Reset module on revision ES2.0 of the R-Car H3 SoC, which differs from ES1.x in some areas. - Add IMR clocks for R-Car H3 and M3-W, - Add workaround for PLL0/2/4 errata on R-Car H3 ES1.0, - Small fixes and cleanups. * tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0 clk: renesas: r8a7795: Add support for R-Car H3 ES2.0 clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions clk: renesas: cpg-mssr: Add support for fixing up clock tables clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0 clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init() clk: renesas: r8a7796: Reformat core clock table clk: renesas: r8a7795: Reformat core clock table clk: renesas: r8a7796: Correct name of watchdog clock clk: renesas: r8a7795: Correct name of watchdog clock clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACs clk: renesas: r8a7796: Add IMR clocks clk: renesas: r8a7795: Add IMR clocks
2017-04-12clk: hi6220: add debug APB clockLeo Yan1-1/+4
The debug APB clock is absent in hi6220 driver, so this patch is to add support for it. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2017-04-04clk: meson-gxbb: Expose GP0 dt-bindings clock idNeil Armstrong1-0/+1
This patch exposes the GP0 PLL clock id in the dt bindings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1490178747-14837-5-git-send-email-narmstrong@baylibre.com
2017-04-04clk: meson-gxbb: Add MALI clock IDSNeil Armstrong1-0/+5
Add missing MALI clock IDs and expose the muxes and gates in the dt-bindings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1490177935-9646-2-git-send-email-narmstrong@baylibre.com
2017-04-04dt-bindings: clk: gxbb: expose i2s output clock gatesJerome Brunet1-0/+5
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-10-jbrunet@baylibre.com
2017-04-04ARM: dts: r7s72100: add rtc clock to device treeChris Brandt1-0/+3
Add the realtime clock functional clock source. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-04-04clk: sunxi-ng: add support for PRCM CCUsIcenowy Zheng1-0/+59
SoCs after A31 has a clock controller module in the PRCM part. Support the clock controller module on H3/5 and A64 now. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-04clk: tegra: Add missing Tegra210 clocksPeter De Schrijver1-8/+8
iqc1, iqc2, tegra_clk_pll_a_out_adsp, tegra_clk_pll_a_out0_out_adsp, adsp and adsp neon were not modelled. dp2 wasn't modelled for Tegra210. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-04-03ARM: dts: r8a7792: Correct Z clockGeert Uytterhoeven1-1/+0
Unlike other R-Car Gen2 SoCs with Cortex-A15 CPU cores, R-Car V2H does not have a programmable Z clock (Cortex-A15 CPU core clock), but uses a fixed divider. This is similar to the Z2 clock (Cortex-A7 CPU core clock) on R-Car E2. Hence: - Remove the Z clock output from the cpg_clocks node, as this implied a programmable clock, - Add the Z clock as a fixed factor clock, - Let the first CPU node point to the new Z clock, - Remove the Z clock index from the bindings (this definition was used by r8a7792.dtsi only, and was not a contract between DT and driver). Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-03-30clk: renesas: Add r8a7795 ES2.0 CPG Core Clock DefinitionsGeert Uytterhoeven1-0/+7
Add all R-Car H3 ES2.0 Clock Pulse Generator Core Clock Outputs, as listed in Table 8.2a ("List of Clocks [R-Car H3]") of the R-Car Gen3 Hardware User's Manual rev. 0.53E. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-28ARM: dts: r8a7794: Add DU1 clock to device treeGeert Uytterhoeven1-0/+1
Add the missing module clock for the second channel of the display unit. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-03-22clk: rockchip: rename RK1108 to RV1108Andy Yan1-3/+3
Rockchip finally named the SOC as RV1108, so change it. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> [include rename in rk1108.dtsi to prevent compile errors] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-03-20clk: tegra: Add aclkPeter De Schrijver1-0/+2
This clock clocks the ADSP Cortex-A9. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20clk: tegra: Define Tegra210 DMIC sync clocksPeter De Schrijver1-1/+8
Tegra210 has 3 DMIC inputs which can be clocked from the recovered clock of several other audio inputs (eg. i2s0, i2s1, ...). To model this, we add a 3 new clocks similar to the audio* clocks which handle the same function for the I2S and SPDIF clocks. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20clk: tegra: Add CEC clockPeter De Schrijver4-4/+4
This clock is used to clock the HDMI CEC interface. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20clk: tegra: Fix ISP clock modellingPeter De Schrijver1-2/+2
The 2 ISP clocks (ispa and ispb) share a mux/divider control. So model this as 1 mux/divider clock and child gate clocks. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-16clk: meson-gxbb: expose clock CLKID_RNG0Heiner Kallweit1-1/+2
Expose clock CLKID_RNG0 which is needed for the HW random number generator. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-03-13ARM: dts: r8a7793: Add INTC-SYS clock to device treeGeert Uytterhoeven1-2/+3
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always on" PM Domain, so it can be power managed using that clock. Note that currently the GIC-400 driver doesn't support module clocks nor Runtime PM, so this must be handled as a critical clock. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-03-10clk: rockchip: add clock ids for timer10-15 of RK3368 SoCsElaine Zhang1-0/+6
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-03-10clk: rockchip: fix up rk3368 timer-idsElaine Zhang1-7/+6
The timer-ids are wrong compared to the manual, probably due a simple copy-paste mistake from the otherwise very similar rk3288. And there are even more timers in the system than the ones wrongly listed here. Timer-Ids were unused both in clock-driver as well as devicetree till now, so fixing them won't break anything. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-03-10clk: rockchip: add rk3328 clk_mac2io_ext IDElaine Zhang1-0/+1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-03-10ARM: dts: r8a7794: Add INTC-SYS clock to device treeGeert Uytterhoeven1-0/+1
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always on" PM Domain, so it can be power managed using that clock. Note that currently the GIC-400 driver doesn't support module clocks nor Runtime PM, so this must be handled as a critical clock. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-03-10ARM: dts: r8a7792: Add INTC-SYS clock to device treeGeert Uytterhoeven1-0/+1
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always on" PM Domain, so it can be power managed using that clock. Note that currently the GIC-400 driver doesn't support module clocks nor Runtime PM, so this must be handled as a critical clock. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-03-10ARM: dts: r8a7791: Add INTC-SYS clock to device treeGeert Uytterhoeven1-0/+1
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always on" PM Domain, so it can be power managed using that clock. Note that currently the GIC-400 driver doesn't support module clocks nor Runtime PM, so this must be handled as a critical clock. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-03-10ARM: dts: r8a7790: Add INTC-SYS clock to device treeGeert Uytterhoeven1-0/+1
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always on" PM Domain, so it can be power managed using that clock. Note that currently the GIC-400 driver doesn't support module clocks nor Runtime PM, so this must be handled as a critical clock. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-03-10ARM: dts: r8a73a4: Add INTC-SYS clock to device treeGeert Uytterhoeven1-0/+1
Link the ARM GIC to the INTC-SYS module clock and the C4 power domain, so it can be power managed using that clock in the future. Note that currently the GIC-400 driver doesn't support module clocks nor Runtime PM, so this must be handled as a critical clock. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-03-06clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driverIcenowy Zheng1-1/+4
Allwinner H5 is a SoC that features a design which keeps the peripheral compatible with H3, so that it have also a CCU like the one on H3 -- only one bus gate/reset is added, and the mmc sample/output phases are removed because of MMC controller update. Add its support in our existing H3 CCU driver. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-06ARM: dts: r7s72100: update sdhi clock bindingsChris Brandt1-2/+4
The SDHI controller in the RZ/A1 has 2 clock sources per channel and both need to be enabled/disabled for proper operation. This fixes the fact that the define for R7S72100_CLK_SDHI1 was not correct to begin with (typo), and that all 4 clock sources need to be defined an used. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-03-04Merge tag 'armsoc-late' of ↵Linus Torvalds1-0/+6
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late DT updates from Arnd Bergmann: "These updates have been kept in a separate branch mostly because they rely on updates to the respective clk drivers to keep the shared header files in sync. This includes two branches for arm64 dt updates, both following up on earlier changes for the same platforms that are already merged: Samsung: - add USB3 support in Exynos7 - minor PM related updates Amlogic: - new machines: WeTek Set-top-boxes - various devices added to DT There are also a couple of bugfixes that trickled in since the start of the merge window: - The moxart_defconfig was not building the intended platform - CPU-hotplug was broken on ux500 - Coresight was broken on Juno (never worked)" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (26 commits) ARM: deconfig: fix the moxart defconfig ARM: ux500: resume the second core properly arm64: dts: juno: update definition for programmable replicator arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost arm64: dts: exynos: Add USB 3.0 controller node for Exynos7 arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7 pinctrl: dt-bindings: samsung: Add Exynos7 specific pinctrl macro definitions arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e ARM64: dts: meson-gxbb-p200: add ADC laddered keys ARM64: dts: meson: meson-gx: add the SAR ADC ARM64: dts: meson-gxl: add the pwm_ao_b pin ARM64: dts: meson-gx: add the missing pwm_AO_ab node clk: gxbb: fix CLKID_ETH defined twice ARM64: dts: meson-gxl: rename Nexbox A95x for consistency clk: gxbb: add the SAR ADC clocks and expose them dt-bindings: amlogic: Add WeTek boards ARM64: dts: meson-gxbb: Add support for WeTek Hub and Play dt-bindings: vendor-prefix: Add wetek vendor prefix ARM64: dts: meson-gxm: Rename q200 and q201 DT files for consistency ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodes ...
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