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2019-07-10pinctrl: aspeed: Strip moved macros and structs from private headerAndrew Jeffery1-498/+0
Further cleanup from the SPDX fixup fallout for the recent ASPEED series. aspeed_g4_defconfig, aspeed_g5_defconfig and multi_v5_defconfig now compile. Smoke tested the g4 and g5 kernels under QEMU's palmetto-bmc and romulus-bmc machines respectively. Fixes: 35d8510ea3ad ("pinctrl: aspeed: Fix missed include") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190710032216.4088-1-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-10pinctrl: aspeed: Fix missed includeLinus Walleij1-0/+2
Some SPDX churn made my fixes drop an important include from the Aspeed pinctrl header. Fix it up. Cc: Andrew Jeffery <andrew@aj.id.au> Reported-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-04pinctrl: baytrail: Use GENMASK() consistentlyAndy Shevchenko1-9/+7
Use GENMASK() macro for all definitions where it's appropriate. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20190703151554.30454-1-andriy.shevchenko@linux.intel.com Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-04pinctrl: baytrail: Re-use data structures from pinctrl-intel.hAndy Shevchenko1-239/+60
We have some data structures duplicated across the drivers. Let's deduplicate them by using ones that being provided by pinctrl-intel.h. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20190703003018.75186-2-andriy.shevchenko@linux.intel.com Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-04pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux()Andy Shevchenko1-3/+4
By the fact byt_get_gpio_mux() returns a value of mux settings as it is represented in hardware. Use defined macro instead of magic numbers to clarify this. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20190703003018.75186-1-andriy.shevchenko@linux.intel.com Reviewed-By: Enrico Weigelt <info@metux.net> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-04pinctrl: qcom: Add SM8150 pinctrl driverPrasad Sodagudi3-0/+1558
Add initial pinctrl driver to support pin configuration with pinctrl framework for SM8150 Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org> Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org> [vkoul: modify to use upstream tile support use upstream code style order the functions and squash functions] Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20190702105045.27646-4-vkoul@kernel.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-03pinctrl: aspeed: Add implementation-related documentationAndrew Jeffery1-4/+200
The ASPEED pinctrl driver implementations make heavy use of macros to minimise tedium of implementation and maximise the chance that the compiler will catch errors in defining signal and pin configurations. While the goal of minimising errors is achieved, it is at the cost of the complexity of the macros. Document examples of the expanded form of pin declarations to demonstrate the operation of the macros. Cc: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190628023838.15426-9-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-03pinctrl: aspeed: Split out pinmux from general pinctrlAndrew Jeffery7-255/+888
ASPEED have completely rearranged the System Control Unit register layout with the AST2600. The existing code took advantage of the fact that the AST2400 and AST2500 had layouts that were similar enough to have little impact on the pinmux infrastructure (though there is a wart with read-modify-write vs write-1-clear semantics of the hardware strapping registers between the two). Given that any similarity has been thrown out with the AST2600, separate out the function applying an expression state to be driver-specific. With it, extract out the pinmux macro jungle to its own header and implementation so the pieces can be composed without dependency cycles. Cc: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190628023838.15426-8-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-03pinctrl: aspeed: Clarify comment about strapping W1CAndrew Jeffery1-1/+1
Writes of 1 to SCU7C clear set bits in SCU70, the hardware strapping register. The information was correct if you squinted while reading, but hopefully switching the order of the registers as listed conveys it better. Cc: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20190628023838.15426-7-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-03pinctrl: aspeed: Correct comment that is no longer trueAndrew Jeffery1-2/+1
We have handled the GFX register case for quite some time now. Cc: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20190628023838.15426-6-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-03pinctrl: qcom: Add irq_enable callback for msm gpioSrinivas Ramana1-1/+24
Introduce the irq_enable callback which will be same as irq_unmask except that it will also clear the status bit before unmask. This will help in clearing any erroneous interrupts that would have got latched when the interrupt is not in use. There may be devices like UART which can use the same gpio line for data rx as well as a wakeup gpio when in suspend. The data that was flowing on the line may latch the interrupt and when we enable the interrupt before going to suspend, this would trigger the unexpected interrupt. This change helps clearing the interrupt so that these unexpected interrupts gets cleared. Signed-off-by: Srinivas Ramana <sramana@codeaurora.org> Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org> Link: https://lore.kernel.org/r/1561472086-23360-1-git-send-email-neeraju@codeaurora.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-26pinctrl: madera: Fixup SPDX headersCharles Keepax5-25/+5
GPL-2.0-only is the preferred way of expressing v2 of the GPL, so switch to that. Remove some redundant copyright notices and correct some instances where the wrong comment type has been used in header files. Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-25pinctrl: qcom: sdm845: Fix CONFIG preprocessor guardNathan Chancellor1-1/+1
Clang warns when CONFIG_ACPI is unset: drivers/pinctrl/qcom/pinctrl-sdm845.c:1320:5: warning: 'CONFIG_ACPI' is not defined, evaluates to 0 [-Wundef] #if CONFIG_ACPI ^ 1 warning generated. Use ifdef instead of if to resolve this. Fixes: a229105d7a1e ("pinctrl: qcom: sdm845: Provide ACPI support") Link: https://github.com/ClangBuiltLinux/linux/issues/569 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-25pinctrl: tegra: Add bitmask support for parked bitsThierry Reding8-47/+57
Some pin groups have park bits for multiple pins in one register. Support this by turning the parked bit field into a parked bitmask field. If no parked bits are supported, the bitmask can be 0. Update the pingroup table on Tegra210, which is the only generation where this is supported, with the parked bitmask. Signed-off-by: Thierry Reding <treding@nvidia.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-25pinctrl: tegra: Set specific GPIO compatible stringThierry Reding3-3/+3
Rather than reuse the nvidia,tegra30-gpio compatible string to find the GPIO controller on Tegra30, Tegra114, Tegra124 and Tegra210, use the most specific compatible string for each SoC generation for consistency. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-25pinctrl: mvebu: Add support for MV98DX1135Chris Packham1-279/+297
The 98DX1135 is a switch chip with an integrated CPU. This is similar to the 98DX4122 except the MPP assignments differ. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-25pinctrl: freescale: Add i.MX8MN pinctrl driver supportAnson Huang3-0/+356
Add the pinctrl driver support for i.MX8MN. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-20pinctrl: Minimize SPDX hamming distanceLinus Walleij3-3/+2
OK so some automatic scripts were fixing the SPDX tags in the mainline branch while we were patching other stuff, and yeah it is more correct to have "GPL-2.0-only" rather than "GPL-2.0" so let's conform to what is already upstream so we don't end up getting the wrong license on the merged result later. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-12Merge branch 'ib-qcom-acpi' into develLinus Walleij4-2/+55
2019-06-12pinctrl: qcom: sdm845: Provide ACPI supportLee Jones2-2/+36
This patch provides basic support for booting with ACPI instead of the currently supported Device Tree. When doing so there are a couple of differences which we need to taken into consideration. Firstly, the SDM850 ACPI tables omit information pertaining to the 4 reserved GPIOs on the platform. If Linux attempts to touch/ initialise any of these lines, the firmware will restart the platform. Secondly, when booting with ACPI, it is expected that the firmware will set-up things like; Regulators, Clocks, Pin Functions, etc in their ideal configuration. Thus, the possible Pin Functions available to this platform are not advertised when providing the higher GPIOD/Pinctrl APIs with pin information. Signed-off-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-12pinctrl: msm: Add ability for drivers to supply a reserved GPIO listLee Jones2-0/+19
When booting MSM based platforms with Device Tree or some ACPI implementations, it is possible to provide a list of reserved pins via the 'gpio-reserved-ranges' and 'gpios' properties respectively. However some ACPI tables are not populated with this information, thus it has to come from a knowledgable device driver instead. Here we provide the MSM common driver with additional support to parse this informtion and correctly populate the widely used 'valid_mask'. Signed-off-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-12pinctrl: remove unused pin_is_valid()Masahiro Yamada1-23/+0
This function was used by pin_request() to pointlessly double-check the pin validity, and it was the only user ever. Since commit d2f6a1c6fb0e ("pinctrl: remove double pin validity check."), no one has ever used it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-12pinctrl: remove unneeded initializer for list_for_each_entry() iteratorMasahiro Yamada1-4/+4
The iterator is initialized in list_for_each_entry(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-08Merge tag 'sh-pfc-for-v5.3-tag1' of ↵Linus Walleij23-1059/+1245
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v5.3 - Add more checks for pinctrl table validation, - Add TPU (Timer Pulse Unit / PWM) pin groups on R-Car H3, M3-W, and M3-N, - Rework description of pins without GPIO functionality, - Small fixes and cleanups.
2019-06-08pinctrl: nomadik: Fix SPDX tagsLinus Walleij5-17/+6
Some files were missing the appropriate SPDX tags so fixed it up. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-08pinctrl: tb10x: Use flexible-array member and struct_size() helperGustavo A. R. Silva1-7/+5
Update the code to use a flexible array member instead of a pointer in structure tb10x_pinctrl and use the struct_size() helper: struct tb10x_pinctrl { ... struct tb10x_of_pinfunc pinfuncs[]; }; Also, make use of the struct_size() helper instead of an open-coded version in order to avoid any potential type mistakes. So, replace the following form: sizeof(struct tb10x_pinctrl) + of_get_child_count(of_node) * sizeof(struct tb10x_of_pinfunc) with: struct_size(state, pinfuncs, of_get_child_count(of_node)) This code was detected with the help of Coccinelle. Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-08pinctrl: aspeed: Add SGPM pinmuxHongwei Zhang1-0/+4
Add SGPM pinmux to ast2500-pinctrl function and group, to prepare for supporting SGPIO in AST2500 SoC. Signed-off-by: Hongwei Zhang <hongweiz@ami.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-08pinctrl: qcom: sdm845: Expose ufs_reset as gpioBjorn Andersson1-6/+6
The ufs_reset pin is expected to be wired to the reset pin of the primary UFS memory but is pretty much just a general purpose output pinr Reorder the pins and expose it as gpio 150, so that the UFS driver can toggle it. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-08pinctrl: Add drive strength support for BM1880 SoCManivannan Sadhasivam1-3/+287
Add drive strength support for Bitmain BM1880 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-08pinctrl: ns2: Fix potential NULL dereferenceYoung Xiao1-0/+2
platform_get_resource() may fail and return NULL, so we should better check it's return value to avoid a NULL pointer dereference a bit later in the code. Signed-off-by: Young Xiao <92siuyang@gmail.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-08pinctrl: u300: Fix SPDX tagsLinus Walleij2-1/+2
Some files were missing the appropriate SPDX tags so fixed it up. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-04pinctrl: sh-pfc: Remove obsolete SH_PFC_PIN_NAMED*() macrosGeert Uytterhoeven1-16/+0
Now all Renesas pin control drivers have been converted to use the new non-GPIO helper macros, SH_PFC_PIN_NAMED() and SH_PFC_PIN_NAMED_CFG() are no longer used. Remove them. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04pinctrl: sh-pfc: sh73a0: Use new macros for non-GPIO pinsGeert Uytterhoeven1-7/+12
Update the SH-Mobile AG5 pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the SH-Mobile AG5 SoC (in 34x34 BGA package) by symbolic enum values, referring to signal names. Note that the user-visible names of these pins are still based on pin numbers instead of signal names, to preserve DT backwards compatibility. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04pinctrl: sh-pfc: r8a77990: Use new macros for non-GPIO pinsGeert Uytterhoeven1-46/+41
Update the R-Car E3 pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car E3 SoC (in 25x25 FCBGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04pinctrl: sh-pfc: r8a77965: Use new macros for non-GPIO pinsGeert Uytterhoeven1-156/+151
Update the R-Car M3-N pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car M3-N SiP (in 39x39 BGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04pinctrl: sh-pfc: r8a7796: Use new macros for non-GPIO pinsGeert Uytterhoeven1-156/+151
Update the R-Car M3-W pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car M3-W SiP (in 39x39 BGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04pinctrl: sh-pfc: r8a7795: Use new macros for non-GPIO pinsGeert Uytterhoeven1-159/+154
Update the R-Car H3 ES2.0 and later pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car H3 ES2.0 SiP (in 39x39 BGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04pinctrl: sh-pfc: r8a7795-es1: Use new macros for non-GPIO pinsGeert Uytterhoeven1-170/+163
Update the R-Car H3 ES1.x pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car H3 ES1.x SiP (in 39x39 BGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04pinctrl: sh-pfc: r8a7790: Use new macros for non-GPIO pinsGeert Uytterhoeven1-15/+19
Update the R-Car H2 pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car H2 SoC (in 31x31 FCBGA package) by symbolic enum values, referring to signal names. Note that the user-visible names of these pins are still based on pin numbers instead of signal names, to preserve DT backwards compatibility. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04pinctrl: sh-pfc: r8a7778: Use new macros for non-GPIO pinsGeert Uytterhoeven1-13/+16
Update the R-Car M1A pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car M1A SoC (in 25x25 FCBGA package) by symbolic enum values, referring to signal names. Note that the user-visible names of these pins are still based on pin numbers instead of signal names, to preserve DT backwards compatibility. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04pinctrl: sh-pfc: emev2: Use new macros for non-GPIO pinsGeert Uytterhoeven1-36/+34
Update the EMMA Mobile EV2 pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the EMMA Mobile EV2 SoC (in 23x23 BGA package) by symbolic enum values, referring to signal names. Note that the user-visible names of these pins are still based on pin numbers instead of signal names, to preserve DT backwards compatibility. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04pinctrl: sh-pfc: Add new non-GPIO helper macrosGeert Uytterhoeven1-0/+56
Add new macros for describing pins without GPIO functionality: - NOGP_ALL() expands to a list of PIN_id values, to be used for generating symbolic enum values, - PINMUX_NOGP_ALL() expands to a list of sh_pfc_pin entries, to list all pins and their capabilities. Both macros depend on an SoC-specific CPU_ALL_NOGP() macro, to be provided by each individual SoC pin control driver. The new macros offer two advantages over the existing SH_PFC_PIN_NAMED() and SH_PFC_PIN_NAMED_CFG() macros: 1. They do not rely on PIN_NUMBER() macros and physical pin numbering, hence do not suffer from pin numbering confusion among different SoC/SiP packages. 2. They are similar in spirit to the existing scheme for handling pins with GPIO functionality. Note that internal to the driver, non-GPIO pins use a sequential numbering scheme which starts after the highest GPIO pin number in use. This value is calculated automatically, using two new helper macros, for systems with either 32-port bank (GP port style) or linear (PORT style) pin space. Sample expansion: GP_LAST = sizeof(union { char dummy[0] __attribute__((deprecated, deprecated)); char GP_0_0[(0 * 32) + 0] __attribute__((deprecated, deprecated)); char GP_0_1[(0 * 32) + 1] __attribute__((deprecated, deprecated)); ... char GP_7_3[(7 * 32) + 3] __attribute__((deprecated, deprecated)); }) Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-02pinctrl: bcm2835: Fix build error without CONFIG_OFYueHaibing1-1/+1
drivers/pinctrl/bcm/pinctrl-bcm2835.c: In function bcm2835_pctl_dt_node_to_map: drivers/pinctrl/bcm/pinctrl-bcm2835.c:720:8: error: implicit declaration of function pinconf_generic_dt_node_to_map_all; drivers/pinctrl/bcm/pinctrl-bcm2835.c: In function bcm2835_pinctrl_probe: drivers/pinctrl/bcm/pinctrl-bcm2835.c:1022:15: error: struct gpio_chip has no member named of_node pc->gpio_chip.of_node = np; Reported-by: Hulk Robot <hulkci@huawei.com> Fixes: 0de704955ee4 ("pinctrl: bcm2835: Add support for generic pinctrl binding") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-01pinctrl: stm32: Add links to consumersLinus Walleij1-0/+1
Using STM32 as guinea pig after Alex's initial positive test to see if this is something we should encourage in general and make default behaviour. Cc: Benjamin Gaignard <benjamin.gaignard@st.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-01pinctrl: mediatek: mt8183: Add pm_opsNicolas Boichat1-0/+1
Setting this up will configure wake from suspend properly, and wake only for the interrupts that are setup in wake_mask, not all interrupts. Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Acked-by: Sean Wang <sean.wang@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-01pinctrl: mediatek: Add pm_ops to pinctrl-parisNicolas Boichat2-0/+21
pinctrl variants that include pinctrl-paris.h (and not pinctrl-mtk-common.h) also need to use pm_ops to setup wake mask properly, so copy over the pm_ops from common to paris variant. It is not easy to merge the 2 copies (or move mtk_eint_suspend/resume to mtk-eint.c), as we need to dereference pctrl->eint, and struct mtk_pinctrl *pctl has a different structure definition for v1 and v2 (which is what paris variant uses). Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Acked-by: Sean Wang <sean.wang@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-01pinctrl: meson: update with SPDX Licence identifierNeil Armstrong8-56/+8
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-01pinctrl: tegra: Add Tegra194 pinmux driverKrishna Yarlagadda3-0/+175
Tegra194 has PCIE L5 rst and clkreq pins which need to be controlled dynamically at runtime. This driver supports change pinmux for these pins. Pinmux for rest of the pins is set statically by bootloader and will not be changed by this driver Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com> Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-01pinctrl: tegra: Support 32 bit register accessKrishna Yarlagadda2-8/+8
Tegra194 chip has 32 bit pinctrl registers. Existing register defines in header are only 16 bit. Modified common pinctrl-tegra driver to support 32 bit registers of Tegra 194 and later chips. Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-24pinctrl: Add pinconf support for BM1880 SoCManivannan Sadhasivam1-0/+134
Add pinconf support for Bitmain BM1880 SoC. Pinconf support includes pin bias, slew rate and schmitt trigger. Drive strength support will be added later. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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