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2017-08-22pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller supportMika Westerberg1-1/+423
This is desktop version Intel Cannon Lake PCH. The GPIO hardware is the same but pin list differs a bit. Add support for this to the existing Cannon Lake pin controller driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22Merge tag 'sh-pfc-for-v4.14-tag1' of ↵Linus Walleij9-122/+2977
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.14 - Propagate errors on group config, now r8a7740-armadillo800eva.dts is fixed, - Add MSIOF and USB2.0 pin groups on R-Car H3 ES2.0, - Add USB2.0 and USB3.0 pin groups on R-Car M3-W, - Add a missing MMC pin group on R-Car M2-W and RZ/G1M, - Add initial support for R-Car D3, - Small fixes and cleanups.
2017-08-22pinctrl: aspeed: Fix ast2500 strap register write logicYong Li2-2/+18
On AST2500, the hardware strap register(SCU70) only accepts write ‘1’, to clear it to ‘0’, must set bits(write ‘1’) to SCU7C Signed-off-by: Yong Li <sdliyong@gmail.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Tested-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: sunxi: fix wrong irq_banks number for H5 pinctrlIcenowy Zheng1-3/+23
The pin controller of Allwinner H5 has three IRQ banks, however in old versions of drivers and device trees, only two are set, which makes PG bank IRQ not available. If it's directly set to 3, the old device trees will fail to boot. Add a workaround (and a warning) for older device trees, and allow new device trees to use correct 3 IRQ banks. Fixes: 838adb576d4a ("drivers: pinctrl: add driver for Allwinner H5 SoC") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: intel: Disable GPIO pin interrupts in suspendRushikesh S Kadam1-0/+1
The fix prevents unintended wakes from second level GPIO pin interrupts. On some Intel Kabylake platforms, it is observed that GPIO pin interrupts can wake the platform from suspend-to-idle, even though the IRQ is not configured as IRQF_NO_SUSPEND or enable_irq_wake(). This can cause undesired wakes on Mobile devices such as Laptops and Chromebook devices. For example a headset jack insertion is not a desired wake source on Chromebook devices. The pinctrl-intel (GPIO controller) driver implements a "Shared IRQ" model. All GPIO pin interrupts are OR'ed and mapped to a first level IRQ14 (or IRQ15). The driver registers an irq_chip struct and maps an irq_domain for the GPIO pin interrupts. The IRQ14 handler demuxes and calls the second level IRQ for the respective pin. In the suspend entry flow, at suspend_noirq stage, the kernel disables IRQs that are not marked for wake. The pinctrl-intel driver does not implement a irq_disable() callback (to take advantage of lazy disabling). The pinctrl-intel GPIO interrupts are not disabled in hardware during suspend entry, and thus are able to wake the SoC out of suspend-to-idle. This patch sets the IRQCHIP_MASK_ON_SUSPEND flag for the GPIO irq_chip, to disable the second level interrupts at suspend_noirq stage via the irq_mask callbacks. The irq_mask callback disables the IRQs in hardware by programming the corresponding GPIO pad registers. Only IRQs that are not marked for wake are disabled. Signed-off-by: Rushikesh S Kadam <rushikesh.s.kadam@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-and-tested-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: vt8500: constify pinconf_ops, pinctrl_ops, and pinmux_ops structuresJulia Lawall1-3/+3
These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: ti-iodelay: constify pinconf_ops, pinctrl_ops, and pinmux_ops ↵Julia Lawall1-2/+2
structures These structures are only stored in fields of a pinctrl_desc structure (confops and pctlops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: tz1090: constify pinconf_ops, pinctrl_ops, and pinmux_ops structuresJulia Lawall1-3/+3
These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: tz1090-pdc: constify pinconf_ops, pinctrl_ops, and pinmux_ops ↵Julia Lawall1-3/+3
structures These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: tb10x: constify pinconf_ops, pinctrl_ops, and pinmux_ops structuresJulia Lawall1-2/+2
These structures are only stored in fields of a pinctrl_desc structure (pctlops and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: rza1: constify pinconf_ops, pinctrl_ops, and pinmux_ops structuresJulia Lawall1-1/+1
This pinmux_ops structure is only stored in the const pmxops field of a pinctrl_desc structure. Make the pinmux_ops structure const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: ingenic: constify pinconf_ops, pinctrl_ops, and pinmux_ops structuresJulia Lawall1-3/+3
These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: adi2: constify pinconf_ops, pinctrl_ops, and pinmux_ops structuresJulia Lawall1-2/+2
These structures are only stored in fields of a pinctrl_desc structure (pctlops and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: aspeed: g5: constify pinconf_ops, pinctrl_ops, and pinmux_ops ↵Julia Lawall1-3/+3
structures These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: aspeed: g4: constify pinconf_ops, pinctrl_ops, and pinmux_ops ↵Julia Lawall1-2/+2
structures These structures are only stored in fields of a pinctrl_desc structure (pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: digicolor: constify pinconf_ops, pinctrl_ops, and pinmux_ops structuresJulia Lawall1-2/+2
These structures are only stored in fields of a pinctrl_desc structure (pctlops and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Acked-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: sirf: constify pinconf_ops, pinctrl_ops, and pinmux_ops structuresJulia Lawall1-2/+2
These structures are only stored in fields of a pinctrl_desc structure (pctlops and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: sirf: atlas7: constify pinconf_ops, pinctrl_ops, and pinmux_ops ↵Julia Lawall1-1/+1
structures This pinmux_ops structure is only stored in the const pmxops field of a pinctrl_desc structure. Make the pinmux_ops structure const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: st: constify pinconf_ops, pinctrl_ops, and pinmux_ops structuresJulia Lawall1-3/+3
These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: armada-37xx: constify pinconf_ops, pinctrl_ops, and pinmux_ops ↵Julia Lawall1-1/+1
structures This pinconf_ops structure is only stored in the const pinconf_ops field of a pinctrl_desc structure. Make the pinconf_ops structure const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: artpec6: constify pinconf_ops, pinctrl_ops, and pinmux_ops structuresJulia Lawall1-1/+1
This pinctrl_ops structure is only stored in the const pctlops field of a pinctrl_desc structure. Make the pinctrl_ops structure const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Acked-by: Lars Persson <lars.persson@axis.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: bcm281xx: constify pinconf_ops, pinctrl_ops, and pinmux_ops structuresJulia Lawall1-1/+1
This pinconf_ops structure is only stored in the const confops field of a pinctrl_desc structure. Make the pinconf_ops structure const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: uniphier: add Audio out pin-mux settingsKatsuhiro Suzuki2-0/+10
The UniPhier LD11/20 SoC audio core use following 8 pins: AO1IEC, AO1ARC, AO1DACCK, AO1BCK, AO1LRCK, AO1D[0-2] Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: amd: fix error return code in amd_gpio_probe()Gustavo A. R. Silva1-2/+2
platform_get_irq() returns an error code, but the pinctrl-amd driver ignores it and always returns -EINVAL. This is not correct and, prevents -EPROBE_DEFER from being propagated properly. Print and propagate the return value of platform_get_irq on failure. This issue was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-16pinctrl: sh-pfc: r8a77995: Add voltage switch operations for MMCTakeshi Kihara1-1/+18
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: r8a77995: Add MMC pins, groups and functionsTakeshi Kihara1-0/+50
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: r8a77995: Add I2C pins, groups and functionsTakeshi Kihara1-0/+71
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: r8a77995: Add SCIF pins, groups and functionsTakeshi Kihara1-0/+262
This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A77995 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> [geert: Fix swapped RX3_B and SCK3_B pins] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: Initial R8A77995 PFC supportTakeshi Kihara5-0/+1425
This patch adds initial pinctrl driver to support for the R8A77995 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> [geert: whitespace] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: Add PORT_GP_{10,2[01]} helper macrosYoshihiro Shimoda1-5/+17
This follows the style of existion PORT_GP_X macros and will be used by a follow-up patch for the r8a77995 SoC. Extracted from the initial r8a77995 patch in the BSP by Takeshi Kihara. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: r8a7796: Add USB3.0 host pins, groups and functionsTakeshi Kihara1-0/+15
This patch adds USB30 (USB3.0 host) pin, group and function to R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: r8a7796: Add USB2.0 host pins, groups and functionsTakeshi Kihara1-0/+29
This patch adds USB{0,1} (USB2.0 host) pins, groups and functions to R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: r8a7795: Fix to reserved MOD_SEL2 bit22Takeshi Kihara1-9/+9
This is a correction because MOD_SEL register specification for R8A7795 ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.54E. Fixes: b205914c8f822ef2 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: r8a7795: Rename CS1# pin function definitionsTakeshi Kihara1-4/+4
This patch renames the pin function macro definitions of the GPSR1 and IPSR4 registers value for the CS1# pin. This is a correction because GPSR and IPSR register specification for R8A7795 ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.54E. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: r8a7795: Fix to delete FSCLKST pin and IPSR7 bit[15:12] ↵Takeshi Kihara1-5/+2
register definitions This patch fixes the macro definitions of FSCLKST pins function and IPSR7 bit[15:12] register deleted. This is a correction because IPSR register specification for R8A7795 ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E or later. Fixes: b205914c8f822ef2 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: r8a7795: Fix MOD_SEL register pin assignment for ↵Takeshi Kihara1-5/+5
TCLK{1,2}_{A,B} pins group This patch fixes to set MOD_SEL2 bit19 when using TCLK2_A pin function is selected for IPSR16 bit[23:20] or using TCLK2_B pin function is selected for IPSR17 bit[27:24]. And renames MOD_SEL2 bit26 value definition name to SEL_TIMER_TMU1. This is a correction because MOD_SEL register specification for R8A7795 ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E. Fixes: b205914c8f822ef2 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: r8a7795: Fix NFDATA{0..13} and NF{ALE,CLE,WE_N,RE_N} pin ↵Takeshi Kihara1-18/+18
function definitions This patch fixes the implementation incorrect of IPSR register value definitions for NFDATA{0..13} and NF{ALE,CLE,WE_N,RE_N} pins function. This is a correction to the incorrect implementation of IPSR register pin assignment of the specifications updated for R8A7795 ES2.0 SoC in R-Car Gen3 Hardware User's Manual Rev.0.53E. Fixes: b205914c8f822ef2 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: r8a7795: Fix FMCLK{_C,_D} and FMIN{_C,_D} pin function ↵Takeshi Kihara1-2/+2
definitions This patch fixes the implementation incorrect of IPSR register value definitions for FMCLK{_C,_D} and FMIN{_C,_D} pins function. This is a correction to the incorrect implementation of IPSR register pin assignment of the specifications updated for R8A7795 ES2.0 SoC in R-Car Gen3 Hardware User's Manual Rev.0.53E. Fixes: b205914c8f822ef2 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: r8a7795: Fix SCIF_CLK_{A,B} pin's MOD_SEL assignment to ↵Takeshi Kihara1-3/+3
MOD_SEL1 bit10 This patch fixes SCIF_CLK_{A,B} pin's MOD_SEL assignment from MOD_SEL1 bit11 to MOD_SEL1 bit10. This is a correction to the incorrect implementation of IPSR register pin assignment for R8A7795 ES2.0 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.53E or later. Fixes: b205914c8f822ef2 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: r8a7795: Fix MOD_SEL2 bit26 to 0x0 when using SCK5_ATakeshi Kihara1-1/+1
This patch fixes the implementation incorrect of MOD_SEL2 bit26 value when SCK5_A pin function is selected for IPSR16 bit[31:28]. This is a correction to the incorrect implementation of MOD_SEL register pin assignment for R8A7795 ES2.0 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: b205914c8f822ef2 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: r8a7795: Fix MOD_SEL1 bit[25:24] to 0x3 when using STP_ISEN_1_DTakeshi Kihara1-1/+1
This patch fixes the implementation incorrect of MOD_SEL1 bit[25:24] value when STP_ISEN_1_D pin function is selected for IPSR17 bit[27:24]. This is a correction to the incorrect implementation of MOD_SEL register pin assignment for R8A7795 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: 0b0ffc96dbe30fa9 ("pinctrl: sh-pfc: Initial R8A7795 PFC support") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: r8a7795: Add USB 2.0 pins, groups and functionsYoshihiro Shimoda1-0/+57
Add pins, groups, and functions for USB 2.0 on R-Car H3 ES2.0. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: r8a7795: Change USB3_{OVC,PWEN} definitionsYoshihiro Shimoda1-10/+10
Since the latest datasheet revises the names, this patch changes the definitions from USB3_{OVC,PWEN} to USB2_CH3_{OVC,PWEN}. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-15pinctrl: qcom: spmi-gpio: Add dtest route for digital inputFenglin Wu1-0/+50
Add property "qcom,dtest-buffer" to specify which dtest rail to feed when the pin is configured as a digital input. Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-15pinctrl: qcom: spmi-gpio: Add support for GPIO LV/MV subtypeFenglin Wu1-49/+232
GPIO LV (low voltage)/MV (medium voltage) subtypes have different features and register mappings than 4CH/8CH subtypes. Add support for LV and MV subtypes. Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14Merge tag 'samsung-pinctrl-4.14' of ↵Linus Walleij6-68/+69
git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl driver changes for v4.14: 1. Fix NULL pointer dereference on S3C24XX. This was reported some time ago and unfortunately it took few releases to fix. 2. Fix invalid register offset used for external interrupts on Exynos5433. This was caused by the same commit as above, although on different path. 3. Consolidate between drivers and bindings the defines for pin mux functions. 4. Minor code improvements.
2017-08-14pinctrl: add a Gemini SoC pin controllerLinus Walleij3-0/+2367
This adds a pin control (only multiplexing) driver for the Gemini SoC so we can sort out this complex platform in an orderly manner. This driver will detect the chip/package version as SL3512 or SL3516 (also known as CS3512 and CS3516 etc) and register the apropriate pin set. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: check ops->pin_config_set in pinconf_set_config()Masahiro Yamada1-1/+1
pinconf_set_config() is called by pinctrl_gpio_set_config(). If a GPIO driver is backed by a pinctrl driver and it does not support .pin_config_set() hook, it causes NULL pointer dereference. Fixes: 15381bc7c7f5 ("pinctrl: Allow configuration of pins from gpiolib based drivers") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: intel: Add Intel Denverton pin controller supportMika Westerberg3-0/+311
This driver adds pinctrl/GPIO support for Intel Denverton SoC. The GPIO controller is based on the same hardware design that is already used in Intel Sunrisepoint so we leverage the core driver here. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: add __rcu annotations to fix sparse warningsMasahiro Yamada2-2/+2
Sparse reports "warning: incorrect type in assignment (different address spaces)". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-01-24 08:53:37 +0300