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2019-09-16mfd: intel-peci-client: Add PECI client MFD driverJae Hyun Yoo3-0/+165
This commit adds PECI client MFD driver. OpenBMC-Staging-Count: 5 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16peci: Add a PECI adapter driver for Aspeed AST24xx/AST25xxJae Hyun Yoo3-0/+535
This commit adds PECI adapter driver implementation for Aspeed AST24xx/AST25xx SoCs. OpenBMC-Staging-Count: 5 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com> Reviewed-by: James Feist <james.feist@linux.intel.com> Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16peci: Add support for PECI bus driver coreJae Hyun Yoo5-0/+1548
This commit adds driver implementation for PECI bus core into linux driver framework. PECI (Platform Environment Control Interface) is a one-wire bus interface that provides a communication channel from Intel processors and chipset components to external monitoring or control devices. PECI is designed to support the following sideband functions: * Processor and DRAM thermal management - Processor fan speed control is managed by comparing Digital Thermal Sensor (DTS) thermal readings acquired via PECI against the processor-specific fan speed control reference point, or TCONTROL. Both TCONTROL and DTS thermal readings are accessible via the processor PECI client. These variables are referenced to a common temperature, the TCC activation point, and are both defined as negative offsets from that reference. - PECI based access to the processor package configuration space provides a means for Baseboard Management Controllers (BMC) or other platform management devices to actively manage the processor and memory power and thermal features. * Platform Manageability - Platform manageability functions including thermal, power, and error monitoring. Note that platform 'power' management includes monitoring and control for both the processor and DRAM subsystem to assist with data center power limiting. - PECI allows read access to certain error registers in the processor MSR space and status monitoring registers in the PCI configuration space within the processor and downstream devices. - PECI permits writes to certain registers in the processor PCI configuration space. * Processor Interface Tuning and Diagnostics - Processor interface tuning and diagnostics capabilities (Intel Interconnect BIST). The processors Intel Interconnect Built In Self Test (Intel IBIST) allows for infield diagnostic capabilities in the Intel UPI and memory controller interfaces. PECI provides a port to execute these diagnostics via its PCI Configuration read and write capabilities. * Failure Analysis - Output the state of the processor after a failure for analysis via Crashdump. PECI uses a single wire for self-clocking and data transfer. The bus requires no additional control lines. The physical layer is a self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle level near zero volts. The duration of the signal driven high depends on whether the bit value is a logic '0' or logic '1'. PECI also includes variable data transfer rate established with every message. In this way, it is highly flexible even though underlying logic is simple. The interface design was optimized for interfacing between an Intel processor and chipset components in both single processor and multiple processor environments. The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components. Bus speed, error checking, and low protocol overhead provides adequate link bandwidth and reliability to transfer critical device operating conditions and configuration information. This implementation provides the basic framework to add PECI extensions to the Linux bus and device models. A hardware specific 'Adapter' driver can be attached to the PECI bus to provide sideband functions described above. It is also possible to access all devices on an adapter from userspace through the /dev interface. A device specific 'Client' driver also can be attached to the PECI bus so each processor client's features can be supported by the 'Client' driver through an adapter connection in the bus. OpenBMC-Staging-Count: 5 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com> Reviewed-by: James Feist <james.feist@linux.intel.com> Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com> [joel: Fix access_ok usage for 5.0] Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16/dev/mem: add a devmem kernel parameter to activate the deviceCédric Le Goater2-0/+21
For security reasons, some configuration needs to run without /dev/mem but on some occasions, to debug HW for instance, it's still useful to be able to reboot the system with access to physical memory. Add a kernel parameter which activates the /dev/mem device only when 'mem.devmem' is enabled. OpenBMC-Staging-Count: 6 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16mtd: spi-nor: fix options for mx66l51235fAlexander Amelkin1-1/+1
Currently in driver spi-nor there is a line for mx66l51235l. According to Macronix site there is no such part number. The chip detected as such is actually mx66l51235f. According to the datasheet for mx66l51235f, "The device default is in 24-bit address mode" (section 9-10). Hence we removed SPI_NOR_4B_OPCODES option with this commit. OpenBMC-Staging-Count: 7 Fixes: d342b6a973af ("mtd: spi-nor: enable 4B opcodes for mx66l51235l") Signed-off-by: Alexander Soldatov <a.soldatov@yadro.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Lei YU <mine260309@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16soc: aspeed: Miscellaneous control interfacesAndrew Jeffery3-0/+199
The ASPEED BMC SoCs have many knobs and switches that are sometimes design-specific and often defy any approach to unify them under an existing subsystem. Add a driver to translate a devicetree table into sysfs entries to expose bits and fields for manipulation from userspace. This encompasses concepts from scratch registers to boolean conditions to enable or disable host interface features. OpenBMC-Staging-Count: 8 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16pmbus (max31785): Wrap all I2C accessors in one-shot failure handlersAndrew Jeffery1-42/+165
The MAX31785(A) has shown erratic behaviour across multiple system designs, unexpectedly clock stretching and NAKing transactions. Perform a one-shot retry if necessary for all access attempts. OpenBMC-Staging-Count: 9 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Tested-by: George Keishing <gkeishin@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16pmbus (core): Use driver callbacks in pmbus_get_fan_rate()Andrew Jeffery1-4/+4
The driver may have overridden the pmbus_read_byte_data() callback, so make sure we use that to achieve expected behaviour. This helps in the MAX31785 case where we may need to perform a one-shot retry of transfers in the face of a failure. OpenBMC-Staging-Count: 9 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Eddie James <eajames@linux.vnet.ibm.com> Tested-by: George Keishing <gkeishin@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16pmbus (core): One-shot retries for failure to set pageAndrew Jeffery1-2/+10
Work around the shonky behaviour seen with the MAX31785 where we fail to set the page register in some circumstances. There's no real elegant way to do this. We can propagate the error up, but that forces us to retry the operation way up the call tree in any number of places. It also forces callers to split out pmbus_set_page() from the pmbus_{read,write}_{byte,word}_data() functions in order to differentiate between a failure to set the page and a failure to read a register (that might not exist, in which case an error is anticiptated). OpenBMC-Staging-Count: 9 Cc: Eddie James <eajames@linux.vnet.ibm.com> Cc: Matt Spinler <mspinler@linux.vnet.ibm.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Eddie James <eajames@linux.vnet.ibm.com> Tested-by: George Keishing <gkeishin@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16pmbus (max31785): Add support for devicetree configurationAndrew Jeffery1-0/+318
OpenBMC-Staging-Count: 9 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Tested-by: George Keishing <gkeishin@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16mtd: spi-nor: aspeed: limit the maximum SPI frequencyCédric Le Goater1-4/+13
The optimize read algo can choose a 100MHz SPI frequency which might be a bit too high for dual output IO on some chips, for the W25Q256 on palmetto for instance. The MX66L1G45G on witherspoon should be fine though. Also, the second chip of the FMC controller does not get any optimize settings for reads. Only the first is configured by U-Boot. To fix these two issues, we introduce a "spi-max-frequency" property in the device tree which will be used to cap the optimize read algorithm and we run the algo on the FMC controller chips as well. By default, the frequency setting is 50MHz. OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16mtd: spi-nor: aspeed: optimize read modeCédric Le Goater1-0/+191
This is only for SPI controllers as U-Boot should have done it already for the FMC controller using DMAs. The algo is based on the one found in the OpenPOWER pflash tool. It first reads a golden buffer at low speed and then performs reads with different clocks and delay cycles settings to find the fastest configuration for the chip. It can be deactivated at boot time with the kernel parameter : aspeed_smc.optimize_read=0 OpenBMC-Staging-Count: 8 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Alexander Soldatov <a.soldatov@yadro.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16mtd: spi-nor: aspeed: link controller with the ahb clockCédric Le Goater1-0/+10
We will need the AHB frequency to set the HCLK settings in the SMC controller to optimize the reads. OpenBMC-Staging-Count: 8 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16mtd: spi-nor: aspeed: add support for SPI dual IO read modeCédric Le Goater1-11/+43
Implements support for the dual IO read mode on aspeed SMC/FMC controllers which uses both MISO and MOSI lines for data during a read to double the read bandwidth. Still to be done SNOR_PROTO_1_2_2 Based on work from Robert Lippert <roblip@gmail.com> OpenBMC-Staging-Count: 8 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16mtd: spi-nor: aspeed: use command mode for readsCédric Le Goater1-1/+27
When reading flash contents, try to use the "command mode" if the AHB window configured for the flash module is big enough. Else, just fall back to the "user mode" to perform the read. OpenBMC-Staging-Count: 8 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16pmbus: (ibm-cffps) Add support for version 2 of the PSUEddie James1-22/+88
Version 2 of the PSU supports a second page of data and changes the format of the FW version. Use the devicetree binding to differentiate between the version the driver should use. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/1567192263-15065-4-git-send-email-eajames@linux.ibm.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> (cherry picked from commit 2f8a855efe8a6faf962c53af406e5ea4791b3877) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16mmc: sdhci-of-aspeed: Depend on CONFIG_OF_ADDRESSAndrew Jeffery1-1/+1
Resolves the following build error reported by the 0-day bot: ERROR: "of_platform_device_create" [drivers/mmc/host/sdhci-of-aspeed.ko] undefined! SPARC does not set CONFIG_OF_ADDRESS so the symbol is missing. Depend on CONFIG_OF_ADDRESS to ensure the driver is only built for supported configurations. Fixes: 2d28dbe042f4 ("mmc: sdhci-of-aspeed: Add support for the ASPEED SD controller") Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 72976643aef55a2a3eec85e5342a3c3608f66e64) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16mmc: sdhci-of-aspeed: Allow max-frequency limitation of SDCLKAndrew Jeffery1-2/+18
Add a get_max_clock() handler to sdhci-of-aspeed to report f_max as the maximum clock rate if it is set. This enables artificial limitation of the bus speed via max-frequency in the devicetree for e.g. the AST2600 evaluation board where I was seeing errors at 200MHz. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 0a0e8d7501cda79c9b20f6011814e2ec9b473ade) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16mmc: sdhci-of-aspeed: Uphold clocks-on post-condition of set_clock()Andrew Jeffery1-3/+0
The early-exit didn't seem to matter on the AST2500, but on the AST2600 the SD clock genuinely may not be running on entry to aspeed_sdhci_set_clock(). Remove the early exit to ensure we always run sdhci_enable_clk(). Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 7b954cdf33da3d3bd8046c499426b7433724f82e) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16mmc: sdhci-of-aspeed: Drop redundant assignment to host->clockAndrew Jeffery1-4/+1
host->clock is already managed by sdhci_set_ios(). Suggested-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit bf290432a4d7d79dff757110b8e6629cefdd4dad) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16mmc: sdhci-of-aspeed: Fix return value check in aspeed_sdc_probe()Wei Yongjun1-2/+2
In case of error, the function of_platform_device_create() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit f70d9a2440346d942f1f9dbda31da5a77510a05f) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16mmc: sdhci-of-aspeed: Add support for the ASPEED SD controllerAndrew Jeffery3-0/+345
Add a minimal driver for ASPEED's SD controller, which exposes two SDHCIs. The ASPEED design implements a common register set for the SDHCIs, and moves some of the standard configuration elements out to this common area (e.g. 8-bit mode, and card detect configuration which is not currently supported). The SD controller has a dedicated hardware interrupt that is shared between the slots. The common register set exposes information on which slot triggered the interrupt; early revisions of the patch introduced an irqchip for the register, but reality is it doesn't behave as an irqchip, and the result fits awkwardly into the irqchip APIs. Instead I've taken the simple approach of using the IRQ as a shared IRQ with some minor performance impact for the second slot. Ryan was the original author of the patch - I've taken his work and massaged it to drop the irqchip support and rework the devicetree integration. The driver has been smoke tested under qemu against a minimal SD controller model and lightly tested on an ast2500-evb. Signed-off-by: Ryan Chen <ryanchen.aspeed@gmail.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit bb7b8ec62dfb9b255027c3a54d01f12fc3bd1d2c) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16pinctrl: aspeed: g6: Remove const specifier from aspeed_g6_sig_expr_set's ↵Nathan Chancellor1-1/+1
ctx parameter clang errors: drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c:2325:9: error: incompatible pointer types initializing 'int (*)(struct aspeed_pinmux_data *, const struct aspeed_sig_expr *, bool)' with an expression of type 'int (const struct aspeed_pinmux_data *, const struct aspeed_sig_expr *, bool)' [-Werror,-Wincompatible-pointer-types] .set = aspeed_g6_sig_expr_set, ^~~~~~~~~~~~~~~~~~~~~~ 1 error generated. Commit 674fa8daa8c9 ("pinctrl: aspeed-g5: Delay acquisition of regmaps") changed the set function pointer declaration and the g6 one wasn't updated (I assume because it wasn't merged yet). Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") Link: https://github.com/ClangBuiltLinux/linux/issues/632 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Link: https://lore.kernel.org/r/20190807003037.48457-1-natechancellor@gmail.com Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> (cherry picked from commit 21b2920fb587e570b43973300a11b921c3a61d3e) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16pinctrl: aspeed: Document existence of deprecated compatiblesAndrew Jeffery2-0/+8
Otherwise they look odd in the face of not being listed in the bindings documents. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190724081313.12934-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org> (cherry picked from commit 73c732c5714955514bb237f01b14e9e5aa7db47e) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16pinctrl: aspeed: Add AST2600 pinmux supportAndrew Jeffery3-0/+2404
The AST2600 pinmux is fairly similar to the previous generations of ASPEED BMC SoCs in terms of architecture, though differ in some of the design details. The complexity of the pin expressions is largely reduced (e.g. there are no-longer signals with multiple expressions muxing them to the associated pin), and there are now signals and buses with multiple pin groups. The driver implements pinmux support for all 244 GPIO-capable pins plus a further four pins that are not GPIO capable but which expose multiple signals. pinconf will be implemented in a follow-up patch. The implementation has been smoke-tested under qemu, and run on hardware by ASPEED. Debugged-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190711041942.23202-7-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org> (cherry picked from commit 2eda1cdec49f8ae7878e60d1b06bd8157a95424f) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16pinctrl: aspeed: Add SIG_DESC_CLEAR() helperAndrew Jeffery1-0/+1
The complement of SIG_DESC_SET(). Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-6-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org> (cherry picked from commit 86392fac9a9c92f36c0a422a3075865a0fe959f9) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16pinctrl: aspeed: Add multiple pin group support for functionsAndrew Jeffery3-1489/+1789
The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org> (cherry picked from commit e7a96b0b7d1669e95aa77c007e71e3c88c531cc4) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16pinctrl: aspeed: Add PIN_DECL_3() helperAndrew Jeffery1-32/+40
This case is common in the AST2600, so add to the collection. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-4-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org> (cherry picked from commit 27d1f73670774e3ea3e304f989f0e1176b57cd7c) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16pinctrl: aspeed: Rename pin declaration macrosAndrew Jeffery3-405/+405
Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org> (cherry picked from commit 7b38897081666532b434e067bdfa85789f42fa4e) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16net: ftgmac100: Select ASPEED MDIO driver for the AST2600Andrew Jeffery1-0/+1
Ensures we can talk to a PHY via MDIO on the AST2600, as the MDIO controller is now separate from the MAC. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net> (cherry picked from commit 82f151def2153f34a1f6f58499f22ceb2bc94042) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16net: ftgmac100: Add support for DT phy-handle propertyAndrew Jeffery1-4/+33
phy-handle is necessary for the AST2600 which separates the MDIO controllers from the MAC. I've tried to minimise the intrusion of supporting the AST2600 to the FTGMAC100 by leaving in place the existing MDIO support for the embedded MDIO interface. The AST2400 and AST2500 continue to be supported this way, as it avoids breaking/reworking existing devicetrees. The AST2600 support by contrast requires the presence of the phy-handle property in the MAC devicetree node to specify the appropriate PHY to associate with the MAC. In the event that someone wants to specify the MDIO bus topology under the MAC node on an AST2400 or AST2500, the current auto-probe approach is done conditional on the absence of an "mdio" child node of the MAC. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net> (cherry picked from commit 39bfab8844a0fabea812f99dc6aa88734323a920) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16net: phy: Add mdio-aspeedAndrew Jeffery3-0/+171
The AST2600 design separates the MDIO controllers from the MAC, which is where they were placed in the AST2400 and AST2500. Further, the register interface is reworked again, so now we have three possible different interface implementations, however this driver only supports the interface provided by the AST2600. The AST2400 and AST2500 will continue to be supported by the MDIO support embedded in the FTGMAC100 driver. The hardware supports both C22 and C45 mode, but for the moment only C22 support is implemented. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net> (cherry picked from commit f160e99462c68ab5b9e2b9097a4867459730b49a) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16ftgmac100: Fix build.David S. Miller1-1/+1
drivers/net/ethernet/faraday/ftgmac100.c:777:13: error: 'skb_frag_t {aka struct bio_vec}' has no member named 'size' Fallout from the skb_frag_t conversion to bio_vec, simply use skb_frag_size(). Fixes: b8b576a16f79 ("net: Rename skb_frag_t size to bv_len") Reported-by: René van Dorst <opensource@vdorst.com> Signed-off-by: David S. Miller <davem@davemloft.net> (cherry picked from commit 084323f62b0b976c9fd931d86c5d2553af5eb9f7) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16gpio: aspeed: Add in ast2600 details to Aspeed driverRashmica Gupta1-2/+20
The ast2600 is a new generation of SoC from ASPEED. Similarly to the ast2400 and ast2500, it has a GPIO controller for it's 3.3V GPIO pins. Additionally, it has a GPIO controller for 1.8V GPIO pins. As the register names for both controllers are the same and the 36 1.8V GPIOs and the first 36 of the 3.3V GPIOs are all bidirectional, we can use the same configuration struct and use the ngpio property to differentiate between the two sets of GPIOs. Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com> Link: https://lore.kernel.org/r/20190906063737.15428-1-rashmica.g@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> (cherry picked from commit ab4a85534c3ee67e9f54d3d5dda6e36072fbed89) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16gpio: aspeed: Use ngpio property from device tree if availableRashmica Gupta1-7/+11
Use the ngpio property from the device tree if it exists. If it doesn't then fallback to the hardcoded value in the config. This is in preparation for adding ast2600 support. The ast2600 SoC has two GPIO controllers and so requires two instances of the GPIO driver. We use the ngpio property to different between them as they have different numbers of GPIOs. Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com> Link: https://lore.kernel.org/r/20190906062727.13521-1-rashmica.g@gmail.com Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> (cherry picked from commit be2a7e2d5d98d288f00af4e9e2ba829aab1ebaef) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16gpio: aspeed: Setup irqchip dynamicallyRashmica Gupta1-9/+7
This is in preparation for adding ast2600 support. The ast2600 SoC requires two instances of the GPIO driver as it has two GPIO controllers. Each instance needs it's own irqchip. Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com> Link: https://lore.kernel.org/r/20190906062644.13445-1-rashmica.g@gmail.com Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> (cherry picked from commit 3d64a5a742ac95f2e6384605ea2825aa1c17e575) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16gpio/aspeed: Fix incorrect number of banksRashmica Gupta1-1/+1
The current calculation for the number of GPIO banks is only correct if the number of GPIOs is a multiple of 32 (if there were 31 GPIOs we would currently say there are 0 banks, which is incorrect). Fixes: 361b79119a4b7 ('gpio: Add Aspeed driver') Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190906062623.13354-1-rashmica.g@gmail.com Reviewed-by: Joel Stanley <joel@jms.d.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> (cherry picked from commit 3c4710ae6f883f9c6e3df5e27e274702a1221c57) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16gpio: Initialize the irqchip valid_mask with a callbackLinus Walleij7-50/+101
After changing the valid_mask for the struct gpio_chip to detect the need and presence of a valid mask with the presence of a .init_valid_mask() callback to fill it in, we augment the gpio_irq_chip to use the same logic. Switch all driver using the gpio_irq_chio valid_mask over to this new method. This makes sure the valid_mask for the gpio_irq_chip gets filled in when we add the gpio_chip, which makes it a little easier to switch over drivers using the old way of setting up gpio_irq_chip over to the new method of passing the gpio_irq_chip along with the gpio_chip. (See drivers/gpio/TODO for details.) Cc: Joel Stanley <joel@jms.id.au> Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Link: https://lore.kernel.org/r/20190904140104.32426-1-linus.walleij@linaro.org (cherry picked from commit 5fbe5b5883f847363ff1b7280e8b1d2980526b8e) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16gpio: tqmx86: Pass irqchip when adding gpiochipLinus Walleij1-17/+24
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Andrew Lunn <andrew@lunn.ch> Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20190809144045.26018-1-linus.walleij@linaro.org (cherry picked from commit 74639d66e1ec069d27eebb97b545916a86d983ea) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16gpio: aspeed: Pass irqchip when adding gpiochipLinus Walleij1-31/+29
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Joel Stanley <joel@jms.id.au> Cc: Andrew Jeffery <andrew@aj.id.au> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20190809125515.19094-1-linus.walleij@linaro.org Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Tested-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> (cherry picked from commit 8512ee31926296fd7d65c1b3c97bb20d67e7eb2a) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16spi: npcm-fiu: add NPCM FIU controller driverTomer Maimon3-0/+782
Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI master controller driver using SPI-MEM interface. The FIU supports single, dual or quad communication interface. the FIU controller can operate in following modes: - User Mode Access(UMA): provides flash access by using an indirect address/data mechanism. - direct rd/wr mode: maps the flash memory into the core address space. - SPI-X mode: used for an expansion bus to an ASIC or CPLD. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20190828142513.228556-3-tmaimon77@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org> (cherry picked from commit ace55c411b11d9b12f500c7433bf469c26130182) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16clk: Add support for AST2600 SoCJoel Stanley2-0/+705
The ast2600 is a new BMC SoC from ASPEED. It contains many more clocks than the previous iterations, so support is broken out into it's own driver. Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://lkml.kernel.org/r/20190825141848.17346-3-joel@jms.id.au [sboyd@kernel.org: Mark arrays const] Signed-off-by: Stephen Boyd <sboyd@kernel.org> (cherry picked from commit d3d04f6c330a60ce7170a1076b06f31c77ba7873) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16clk: aspeed: Move structures to headerJoel Stanley2-64/+85
They will be reused by the ast2600 driver. Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://lkml.kernel.org/r/20190825141848.17346-2-joel@jms.id.au Signed-off-by: Stephen Boyd <sboyd@kernel.org> (cherry picked from commit c1c4942eebdbb80d36d72df6f0ac19f82cf5dd9f) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16clk: aspeed: Add SDIO gateJoel Stanley1-3/+8
The clock divisor comes with an enable bit (gate). This was not implemented as we didn't have access to SD hardware when writing the driver. Now that we can test it, add the gate as a parent to the divisor. There is no reason to expose the gate separately, so users will enable it by turning on the ASPEED_CLK_SDIO divisor. Signed-off-by: Joel Stanley <joel@jms.id.au> [aj: Minor style cleanup] Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lkml.kernel.org/r/20190710141009.20651-1-andrew@aj.id.au Signed-off-by: Stephen Boyd <sboyd@kernel.org> (cherry picked from commit ebd5f82d32ade6f864917bf868bfa32f4d3c0486) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-15Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhostLinus Torvalds1-4/+2
Pull virtio fix from Michael Tsirkin: "A last minute revert The 32-bit build got broken by the latest defence in depth patch. Revert and we'll try again in the next cycle" * tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost: Revert "vhost: block speculation of translated descriptors"
2019-09-14Revert "vhost: block speculation of translated descriptors"Michael S. Tsirkin1-4/+2
This reverts commit a89db445fbd7f1f8457b03759aa7343fa530ef6b. I was hasty to include this patch, and it breaks the build on 32 bit. Defence in depth is good but let's do it properly. Cc: stable@vger.kernel.org Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2019-09-14Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netLinus Torvalds28-137/+246
Pull networking fixes from David Miller: 1) Don't corrupt xfrm_interface parms before validation, from Nicolas Dichtel. 2) Revert use of usb-wakeup in btusb, from Mario Limonciello. 3) Block ipv6 packets in bridge netfilter if ipv6 is disabled, from Leonardo Bras. 4) IPS_OFFLOAD not honored in ctnetlink, from Pablo Neira Ayuso. 5) Missing ULP check in sock_map, from John Fastabend. 6) Fix receive statistic handling in forcedeth, from Zhu Yanjun. 7) Fix length of SKB allocated in 6pack driver, from Christophe JAILLET. 8) ip6_route_info_create() returns an error pointer, not NULL. From Maciej Żenczykowski. 9) Only add RDS sock to the hashes after rs_transport is set, from Ka-Cheong Poon. 10) Don't double clean TX descriptors in ixgbe, from Ilya Maximets. 11) Presence of transmit IPSEC offload in an SKB is not tested for correctly in ixgbe and ixgbevf. From Steffen Klassert and Jeff Kirsher. 12) Need rcu_barrier() when register_netdevice() takes one of the notifier based failure paths, from Subash Abhinov Kasiviswanathan. 13) Fix leak in sctp_do_bind(), from Mao Wenan. * git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net: (72 commits) cdc_ether: fix rndis support for Mediatek based smartphones sctp: destroy bucket if failed to bind addr sctp: remove redundant assignment when call sctp_get_port_local sctp: change return type of sctp_get_port_local ixgbevf: Fix secpath usage for IPsec Tx offload sctp: Fix the link time qualifier of 'sctp_ctrlsock_exit()' ixgbe: Fix secpath usage for IPsec TX offload. net: qrtr: fix memort leak in qrtr_tun_write_iter net: Fix null de-reference of device refcount ipv6: Fix the link time qualifier of 'ping_v6_proc_exit_net()' tun: fix use-after-free when register netdev failed tcp: fix tcp_ecn_withdraw_cwr() to clear TCP_ECN_QUEUE_CWR ixgbe: fix double clean of Tx descriptors with xdp ixgbe: Prevent u8 wrapping of ITR value to something less than 10us mlx4: fix spelling mistake "veify" -> "verify" net: hns3: fix spelling mistake "undeflow" -> "underflow" net: lmc: fix spelling mistake "runnin" -> "running" NFC: st95hf: fix spelling mistake "receieve" -> "receive" net/rds: An rds_sock is added too early to the hash table mac80211: Do not send Layer 2 Update frame before authorization ...
2019-09-14Merge tag 'mmc-v5.3-rc8' of ↵Linus Torvalds7-29/+17
git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc Pull MMC fixes from Ulf Hansson: - tmio: Fixup runtime PM management during probe and remove - sdhci-pci-o2micro: Fix eMMC initialization for an AMD SoC - bcm2835: Prevent lockups when terminating work * tag 'mmc-v5.3-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: mmc: tmio: Fixup runtime PM management during remove mmc: tmio: Fixup runtime PM management during probe Revert "mmc: tmio: move runtime PM enablement to the driver implementations" Revert "mmc: sdhci: Remove unneeded quirk2 flag of O2 SD host controller" Revert "mmc: bcm2835: Terminate timeout work synchronously"
2019-09-14Merge tag 'drm-fixes-2019-09-13' of git://anongit.freedesktop.org/drm/drmLinus Torvalds4-8/+11
Pull drm fixes from Dave Airlie: "From the maintainer summit, just some last minute fixes for final: lima: - fix gem_wait ioctl core: - constify modes list i915: - DP MST high color depth regression - GPU hangs on vulkan compute workloads" * tag 'drm-fixes-2019-09-13' of git://anongit.freedesktop.org/drm/drm: drm/lima: fix lima_gem_wait() return value drm/i915: Restore relaxed padding (OCL_OOB_SUPPRES_ENABLE) for skl+ drm/i915: Limit MST to <= 8bpc once again drm/modes: Make the whitelist more const
2019-09-13cdc_ether: fix rndis support for Mediatek based smartphonesBjørn Mork1-1/+9
A Mediatek based smartphone owner reports problems with USB tethering in Linux. The verbose USB listing shows a rndis_host interface pair (e0/01/03 + 10/00/00), but the driver fails to bind with [ 355.960428] usb 1-4: bad CDC descriptors The problem is a failsafe test intended to filter out ACM serial functions using the same 02/02/ff class/subclass/protocol as RNDIS. The serial functions are recognized by their non-zero bmCapabilities. No RNDIS function with non-zero bmCapabilities were known at the time this failsafe was added. But it turns out that some Wireless class RNDIS functions are using the bmCapabilities field. These functions are uniquely identified as RNDIS by their class/subclass/protocol, so the failing test can safely be disabled. The same applies to the two types of Misc class RNDIS functions. Applying the failsafe to Communication class functions only retains the original functionality, and fixes the problem for the Mediatek based smartphone. Tow examples of CDC functional descriptors with non-zero bmCapabilities from Wireless class RNDIS functions are: 0e8d:000a Mediatek Crosscall Spider X5 3G Phone CDC Header: bcdCDC 1.10 CDC ACM: bmCapabilities 0x0f connection notifications sends break line coding and serial state get/set/clear comm features CDC Union: bMasterInterface 0 bSlaveInterface 1 CDC Call Management: bmCapabilities 0x03 call management use DataInterface bDataInterface 1 and 19d2:1023 ZTE K4201-z CDC Header: bcdCDC 1.10 CDC ACM: bmCapabilities 0x02 line coding and serial state CDC Call Management: bmCapabilities 0x03 call management use DataInterface bDataInterface 1 CDC Union: bMasterInterface 0 bSlaveInterface 1 The Mediatek example is believed to apply to most smartphones with Mediatek firmware. The ZTE example is most likely also part of a larger family of devices/firmwares. Suggested-by: Lars Melin <larsm17@gmail.com> Signed-off-by: Bjørn Mork <bjorn@mork.no> Signed-off-by: David S. Miller <davem@davemloft.net>
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