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2019-05-07drm: aspeed: Clean up Kconfig optionsJoel Stanley1-3/+3
The GFX IP is inside of the ASPEED BMC SoC so there is little use enabling it on a kernel that does not support ASPEED. When building with COMPILE_TEST the architecture many not have CMA support, so to avoid breaking the build we only select these options if the architecture supports the contiguous allocator. I suspect the DRM_PANEL came from a cut/paste error. Fixes: 4f2a8f5898ec ("drm: Add ASPEED GFX driver") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190405081117.27339-1-joel@jms.id.au (cherry picked from commit 76356a966e332fa0f70d10fd74a66d518af8ce0a) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-07drm: Add ASPEED GFX driverJoel Stanley8-0/+676
This driver is for the ASPEED BMC SoC's GFX display hardware. This driver runs on the ARM based BMC systems, unlike the ast driver which runs on a host CPU and is is for a PCI graphics device. Signed-off-by: Joel Stanley <joel@jms.id.au> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190403001909.31637-3-joel@jms.id.au (cherry picked from commit 4f2a8f5898ecd806cc0ccece1df4c0f143f80a74) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-07media: aspeed: refine interrupt handling logicJae Hyun Yoo1-3/+4
There are cases that interrupt bits are cleared by a 500ms delayed work which causes unnecessary irq calls. Also, the current interrupt handler returns IRQ_HANDLED always but it should return IRQ_NONE if there is any unhandled interrupt. So this commit refines the interrupt handling logic to fix these issues. OpenBMC-Staging-Count: 2 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-07media: aspeed: remove checking of VE_INTERRUPT_CAPTURE_COMPLETEJae Hyun Yoo1-8/+4
VE_INTERRUPT_CAPTURE_COMPLETE and VE_INTERRUPT_COMP_COMPLETE are not set at the same time but the current interrupt handling mechanism of this driver doesn't clear the interrupt flag until both two are set, and this behavior causes unnecessary interrupt handler calls. In fact, this driver provides JPEG format only so taking care of the VE_INTERRUPT_COMP_COMPLETE is enough for getting compressed image frame so this commit gets rid of the VE_INTERRUPT_CAPTURE_COMPLETE checking logic to simplify the logic. Handling of VE_INTERRUPT_CAPTURE_COMPLETE could be added back later when it's actually needed. OpenBMC-Staging-Count: 2 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-07media: aspeed: reduce noisy log printing outsJae Hyun Yoo1-5/+5
Currently, this driver prints out too much log messages when a mode change happens, video turned off by screen saver and etc. Actually, all cases are reported to user space properly. Also, these are not critical errors but recoverable things, so this commit changes the log level of some noisy printing outs. OpenBMC-Staging-Count: 2 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-07media: aspeed: remove IRQF_SHARED flagJae Hyun Yoo1-2/+1
Video Engine has a dedicated interrupt line so this driver doesn't need to use IRQF_SHARED flag so remove it. Also, it'd be good for following what Thomas recommended in the IRQF_ONESHOT support patch like below: "Note that for now IRQF_ONESHOT cannot be used with IRQF_SHARED to avoid complex accounting mechanisms." OpenBMC-Staging-Count: 2 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-07misc: aspeed-lpc-ctrl: make parameter optionalVijay Khemka1-22/+36
Makiing memory-region and flash as optional parameter in device tree if user needs to use these parameter through ioctl then need to define in devicetree. OpenBMC-Staging-Count: 2 Signed-off-by: Vijay Khemka <vijaykhemka@fb.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-07drivers/misc: Add Aspeed P2A control driverPatrick Venture3-0/+453
The ASPEED AST2400, and AST2500 in some configurations include a PCI-to-AHB MMIO bridge. This bridge allows a server to read and write in the BMC's physical address space. This feature is especially useful when using this bridge to send large files to the BMC. The host may use this to send down a firmware image by staging data at a specific memory address, and in a coordinated effort with the BMC's software stack and kernel, transmit the bytes. This driver enables the BMC to unlock the PCI bridge on demand, and configure it via ioctl to allow the host to write bytes to an agreed upon location. In the primary use-case, the region to use is known apriori on the BMC, and the host requests this information. Once this request is received, the BMC's software stack will enable the bridge and the region and then using some software flow control (possibly via IPMI packets), copy the bytes down. Once the process is complete, the BMC will disable the bridge and unset any region involved. The default behavior of this bridge when present is: enabled and all regions marked read-write. This driver will fix the regions to be read-only and then disable the bridge entirely. The memory regions protected are: * BMC flash MMIO window * System flash MMIO windows * SOC IO (peripheral MMIO) * DRAM The DRAM region itself is all of DRAM and cannot be further specified. Once the PCI bridge is enabled, the host can read all of DRAM, and if the DRAM section is write-enabled, then it can write to all of it. Signed-off-by: Patrick Venture <venture@google.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commit 01c60dcea9f7a97ed0e94245e425002a8ddd6c17) Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-07pmbus: support for custom sysfs attributeskrzysztof.adamski@nokia.com2-1/+15
This patch makes it possible to pass custom struct attribute_group array via the pmbus_driver_info struct so that those can be added to the attribute groups passed to hwmon_device_register_with_groups(). This makes it possible to register custom sysfs attributes by PMBUS drivers similar to how you can do this with most other busses/classes. OpenBMC-Staging-Count: 2 Signed-off-by: Krzysztof Adamski <krzysztof.adamski@nokia.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2019-05-07hwmon (occ): Add temp sensor value checkAlexander Soldatov1-0/+6
The occ driver supports two formats for the temp sensor value. The OCC firmware for P8 supports only the first format, for which no range checking or error processing is performed in the driver. Inspecting the OCC sources for P8 reveals that OCC may send a special value 0xFFFF to indicate that a sensor read timeout has occurred, see https://github.com/open-power/occ/blob/master_p8/src/occ/cmdh/cmdh_fsp_cmds.c#L395 That situation wasn't handled in the driver. This patch adds invalid temp value check for the sensor data format 1 and handles it the same way as it is done for the format 2, where EREMOTEIO is reported for this case. OpenBMC-Staging-Count: 2 Signed-off-by: Alexander Soldatov <a.soldatov@yadro.com> Signed-off-by: Alexander Amelkin <a.amelkin@yadro.com> Reviewed-by: Alexander Amelkin <a.amelkin@yadro.com> Cc: Edward A. James <eajames@us.ibm.com> Cc: Joel Stanley <joel@jms.id.au> Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-07mtd: spi-nor: aspeed: add support for the 4B opcodesCédric Le Goater1-2/+9
Switch the default controller value to use the read mode in order to customize the command and use SPINOR_OP_READ_4B (0x13) when the chip supports 4B opcodes. OpenBMC-Staging-Count: 2 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2019-05-07mtd: spi-nor: aspeed: use memcpy_fromio() to capture the optimization bufferCédric Le Goater1-4/+2
aspeed_smc_read_from_ahb() only reads the first word which is not what we want. We want to capture a CALIBRATE_BUF_SIZE size window of the flash contents to optimize the read. OpenBMC-Staging-Count: 2 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2019-05-07mtd: spi-nor: aspeed: clarify 4BYTE address mode maskCédric Le Goater1-1/+9
OpenBMC-Staging-Count: 2 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2019-05-07mtd: spi-nor: aspeed: introduce a aspeed_smc_default_read() helperCédric Le Goater1-7/+12
OpenBMC-Staging-Count: 2 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2019-05-07hwmon (occ): Prevent sysfs error attribute from returning errorEddie James1-6/+13
The error sysfs attribute returns the stored error state of the OCC and doesn't depend on the OCC poll response. Therefore, split the error attribute into it's own function to avoid failing out of the function if the poll response fails. OpenBMC-Staging-Count: 2 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2019-05-07hwmon (occ): Store error condition for rate-limited pollsEddie James2-1/+6
The OCC driver limits the rate of sending poll commands to the OCC. If a user reads a hwmon entry after a poll response resulted in an error and is rate-limited, the error is invisible to the user. Fix this by storing the last error and returning that in the rate-limited case. OpenBMC-Staging-Count: 2 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2019-05-07hwmon (occ): Fix extended status bitsLei YU1-4/+4
The occ's extended status is checked and shown as sysfs attributes. But the code was incorrectly checking the "status" bits. Fix it by checking the "ext_status" bits. OpenBMC-Staging-Count: 2 Signed-off-by: Lei YU <mine260309@gmail.com> Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2019-05-06hwmon: (pmbus/ir38064): Add driver for Infineon IR38064 Voltage RegulatorMaxim Sloyko3-0/+70
Add the pmbus driver for the Infineon ir38064 voltage regulator. OpenBMC-Staging-Count: 2 Signed-off-by: Maxim Sloyko <maxims@google.com> Signed-off-by: Patrick Vtenture <venture@google.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06peci: npcm: add NPCM PECI driverTomer Maimon3-0/+422
Add support for the Nuvoton NPCM BMC hardware to the Platform Environment Control Interface (PECI) subsystem. OpenBMC-Staging-Count: 2 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06media: platform: aspeed: change irq to threaded irqJae Hyun Yoo1-2/+3
Differently fron other Aspeed drivers, this driver calls clock control APIs in interrupt context. Since ECLK is coupled with a reset bit in clk-aspeed module, aspeed_clk_enable will make 10ms of busy waiting delay for triggering the reset and it will eventually disturb other drivers' interrupt handling. To fix this issue, this commit changes this driver's irq to threaded irq so that the delay can be happened in a thread context. OpenBMC-Staging-Count: 2 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06media: platform: aspeed: refine clock control logicJae Hyun Yoo1-9/+29
Currently, this driver calls clk_prepare and clk_unprepare from interrupt context too but these should be called from sleepable context only. To fix this issue, this commit splits out clk_enable/disable and clk_prepare/unprepare, and it places clk_prepare/unprepare calls into the module probe/remove function. OpenBMC-Staging-Count: 2 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06media: platform: aspeed: fix a kernel warning on clk controlJae Hyun Yoo1-3/+29
Video engine clock control functions in the Aspeed video engine driver are being called from multiple context without any protection so video clocks can be double disabled and eventually it causes a kernel warning with stack dump printing out like below: [ 515.540498] ------------[ cut here ]------------ [ 515.545174] WARNING: CPU: 0 PID: 1310 at drivers/clk/clk.c:684 clk_core_unprepare+0x13c/0x170 [ 515.553806] vclk-gate already unprepared [ 515.557841] CPU: 0 PID: 1310 Comm: obmc-ikvm Tainted: G W 5.0.6-df66fbc97853fbba90a0bfa44de32f3d5f7602b4 #1 [ 515.568973] Hardware name: Generic DT based system [ 515.573777] Backtrace: [ 515.576272] [<80107cdc>] (dump_backtrace) from [<80107f10>] (show_stack+0x20/0x24) [ 515.583930] r7:803a5614 r6:00000009 r5:00000000 r4:9d88fe1c [ 515.589712] [<80107ef0>] (show_stack) from [<80690184>] (dump_stack+0x20/0x28) [ 515.597053] [<80690164>] (dump_stack) from [<80116044>] (__warn.part.3+0xb4/0xdc) [ 515.604557] [<80115f90>] (__warn.part.3) from [<801160d8>] (warn_slowpath_fmt+0x6c/0x90) [ 515.612734] r6:000002ac r5:8080befc r4:80a07008 [ 515.617463] [<80116070>] (warn_slowpath_fmt) from [<803a5614>] (clk_core_unprepare+0x13c/0x170) [ 515.626167] r3:8080cdf4 r2:8080bfc0 [ 515.629834] r7:98d682a8 r6:9d8a9200 r5:9e5151a0 r4:97abd620 [ 515.635530] [<803a54d8>] (clk_core_unprepare) from [<803a76a4>] (clk_unprepare+0x34/0x3c) [ 515.643812] r5:9e5151a0 r4:97abd620 [ 515.647529] [<803a7670>] (clk_unprepare) from [<804f36ec>] (aspeed_video_off+0x38/0x50) [ 515.655539] r5:9e5151a0 r4:9e504000 [ 515.659242] [<804f36b4>] (aspeed_video_off) from [<804f4358>] (aspeed_video_release+0x90/0x114) [ 515.668036] r5:9e5044b0 r4:9e504000 [ 515.671643] [<804f42c8>] (aspeed_video_release) from [<804d302c>] (v4l2_release+0xd4/0xe8) [ 515.679999] r7:98d682a8 r6:9d087810 r5:9d8a9200 r4:9e504318 [ 515.685695] [<804d2f58>] (v4l2_release) from [<80236454>] (__fput+0x98/0x1c4) [ 515.692914] r5:9e51b608 r4:9d8a9200 [ 515.696597] [<802363bc>] (__fput) from [<802365e8>] (____fput+0x18/0x1c) [ 515.703315] r9:80a0700c r8:801011e4 r7:00000000 r6:80a64b9c r5:9d8e35a0 r4:9d8e38dc [ 515.711167] [<802365d0>] (____fput) from [<80131ca4>] (task_work_run+0x7c/0xa0) [ 515.718596] [<80131c28>] (task_work_run) from [<80106884>] (do_work_pending+0x4a8/0x578) [ 515.726777] r7:801011e4 r6:80a07008 r5:9d88ffb0 r4:ffffe000 [ 515.732466] [<801063dc>] (do_work_pending) from [<8010106c>] (slow_work_pending+0xc/0x20) [ 515.740727] Exception stack(0x9d88ffb0 to 0x9d88fff8) [ 515.745840] ffa0: 00000000 76f18094 00000000 00000000 [ 515.754122] ffc0: 00000007 00176778 7eda4c20 00000006 00000000 00000000 48e20fa4 00000000 [ 515.762386] ffe0: 00000002 7eda4b08 00000000 48f91efc 80000010 00000007 [ 515.769097] r10:00000000 r9:9d88e000 r8:801011e4 r7:00000006 r6:7eda4c20 r5:00176778 [ 515.777006] r4:00000007 [ 515.779558] ---[ end trace 12c04aadef8afbbb ]--- [ 515.784176] ------------[ cut here ]------------ [ 515.788817] WARNING: CPU: 0 PID: 1310 at drivers/clk/clk.c:825 clk_core_disable+0x18c/0x204 [ 515.797161] eclk-gate already disabled [ 515.800916] CPU: 0 PID: 1310 Comm: obmc-ikvm Tainted: G W 5.0.6-df66fbc97853fbba90a0bfa44de32f3d5f7602b4 #1 [ 515.811945] Hardware name: Generic DT based system [ 515.816730] Backtrace: [ 515.819210] [<80107cdc>] (dump_backtrace) from [<80107f10>] (show_stack+0x20/0x24) [ 515.826782] r7:803a5900 r6:00000009 r5:00000000 r4:9d88fe04 [ 515.832454] [<80107ef0>] (show_stack) from [<80690184>] (dump_stack+0x20/0x28) [ 515.839687] [<80690164>] (dump_stack) from [<80116044>] (__warn.part.3+0xb4/0xdc) [ 515.847170] [<80115f90>] (__warn.part.3) from [<801160d8>] (warn_slowpath_fmt+0x6c/0x90) [ 515.855247] r6:00000339 r5:8080befc r4:80a07008 [ 515.859868] [<80116070>] (warn_slowpath_fmt) from [<803a5900>] (clk_core_disable+0x18c/0x204) [ 515.868385] r3:8080cdd0 r2:8080c00c [ 515.871957] r7:98d682a8 r6:9d8a9200 r5:97abd560 r4:97abd560 [ 515.877615] [<803a5774>] (clk_core_disable) from [<803a59a0>] (clk_core_disable_lock+0x28/0x34) [ 515.886301] r7:98d682a8 r6:9d8a9200 r5:97abd560 r4:a0000013 [ 515.891960] [<803a5978>] (clk_core_disable_lock) from [<803a7714>] (clk_disable+0x2c/0x30) [ 515.900216] r5:9e5151a0 r4:9e515f60 [ 515.903816] [<803a76e8>] (clk_disable) from [<804f36f8>] (aspeed_video_off+0x44/0x50) [ 515.911656] [<804f36b4>] (aspeed_video_off) from [<804f4358>] (aspeed_video_release+0x90/0x114) [ 515.920341] r5:9e5044b0 r4:9e504000 [ 515.923921] [<804f42c8>] (aspeed_video_release) from [<804d302c>] (v4l2_release+0xd4/0xe8) [ 515.932184] r7:98d682a8 r6:9d087810 r5:9d8a9200 r4:9e504318 [ 515.937851] [<804d2f58>] (v4l2_release) from [<80236454>] (__fput+0x98/0x1c4) [ 515.944980] r5:9e51b608 r4:9d8a9200 [ 515.948559] [<802363bc>] (__fput) from [<802365e8>] (____fput+0x18/0x1c) [ 515.955257] r9:80a0700c r8:801011e4 r7:00000000 r6:80a64b9c r5:9d8e35a0 r4:9d8e38dc [ 515.963008] [<802365d0>] (____fput) from [<80131ca4>] (task_work_run+0x7c/0xa0) [ 515.970333] [<80131c28>] (task_work_run) from [<80106884>] (do_work_pending+0x4a8/0x578) [ 515.978421] r7:801011e4 r6:80a07008 r5:9d88ffb0 r4:ffffe000 [ 515.984086] [<801063dc>] (do_work_pending) from [<8010106c>] (slow_work_pending+0xc/0x20) [ 515.992247] Exception stack(0x9d88ffb0 to 0x9d88fff8) [ 515.997296] ffa0: 00000000 76f18094 00000000 00000000 [ 516.005473] ffc0: 00000007 00176778 7eda4c20 00000006 00000000 00000000 48e20fa4 00000000 [ 516.013642] ffe0: 00000002 7eda4b08 00000000 48f91efc 80000010 00000007 [ 516.020257] r10:00000000 r9:9d88e000 r8:801011e4 r7:00000006 r6:7eda4c20 r5:00176778 [ 516.028072] r4:00000007 [ 516.030606] ---[ end trace 12c04aadef8afbbc ]--- To prevent this issue, this commit adds spinlock protection and clock status checking logic into the Aspeed video engine driver. OpenBMC-Staging-Count: 2 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06clk: Aspeed: Setup video engine clockingEddie James1-3/+39
Add eclk mux and clock divider table. Also change the video engine reset to the correct clock; it was previously on the video capture but needs to be on the video engine clock. OpenBMC-Staging-Count: 2 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06media: platform: Aspeed: Make reserved memory optionalEddie James1-5/+1
Reserved memory doesn't need to be required; system memory would work fine. OpenBMC-Staging-Count: 2 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06media: platform: Aspeed: Remove use of reset lineEddie James1-22/+5
The reset line is toggled by enabling the clocks, so it's not necessary to manually toggle the reset as well. OpenBMC-Staging-Count: 2 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06net: npcm: use bitmap functions on link mode paramsBenjamin Fair1-2/+2
This fixes a compilation error caused by the phy_device "supported" and "advertising" parameters switching from u32 to bitmap. Fixes: 35998b5c4073 ("net: npcm: add NPCM7xx Ethernet MAC controller") OpenBMC-Staging-Count: 2 Signed-off-by: Benjamin Fair <benjaminfair@google.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06net: npcm: add NPCM7xx Ethernet MAC controllerTomer Maimon3-1/+2109
Add Nuvoton BMC NPCM7xx Ethernet MAC controller (EMC) driver. OpenBMC-Staging-Count: 3 Signed-off-by: Avi Fishman <avifishman70@gmail.com> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06misc: mbox: add npcm7xx pci mailbox driverTomer Maimon3-0/+296
Add Nuvoton BMC NPCM7XX PCI Mailbox driver. OpenBMC-Staging-Count: 3 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> [v5.0: Fix access_ok for API change] Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06misc: npcm7xx-lpc-bpc: add NPCM7xx BIOS post code driverTomer Maimon3-0/+403
Add NPCM7xx BIOS post code (BPC) driver, the BPC monitoring two I/O address written by the host on the LPC. OpenBMC-Staging-Count: 3 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06i2c: npcm: driver for Poleg i2c controllerTomer Maimon3-0/+2030
OpenBMC-Staging-Count: 3 Signed-off-by: Tali Perry <tali.perry1@gmail.com> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> [joel: select CRC8 to fix build error] Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06mtd: spi-nor: add NPCM FIU controller driverTomer Maimon3-0/+938
Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI-NOR controller driver The FIU supports single, dual or quad communication interface. the FIU controller can operate in following modes: - User Mode Access(UMA): provides flash access by using an indirect address/data mechanism. - direct rd/wr mode: maps the flash memory into the core address space. - SPI-X mode: used for an expansion bus to an ASIC or CPLD. OpenBMC-Staging-Count: 3 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> [v5.0: Remove asm/size.h include to fix build] Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06hwmon: Add PECI dimmtemp driverJae Hyun Yoo3-0/+299
This commit adds PECI dimmtemp hwmon driver. OpenBMC-Staging-Count: 3 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com> Reviewed-by: James Feist <james.feist@linux.intel.com> Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06hwmon: Add PECI cputemp driverJae Hyun Yoo4-0/+458
This commit adds PECI cputemp hwmon driver. OpenBMC-Staging-Count: 3 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com> Reviewed-by: James Feist <james.feist@linux.intel.com> Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06mfd: intel-peci-client: Add PECI client MFD driverJae Hyun Yoo3-0/+165
This commit adds PECI client MFD driver. OpenBMC-Staging-Count: 3 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06peci: Add a PECI adapter driver for Aspeed AST24xx/AST25xxJae Hyun Yoo3-0/+535
This commit adds PECI adapter driver implementation for Aspeed AST24xx/AST25xx SoCs. OpenBMC-Staging-Count: 3 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com> Reviewed-by: James Feist <james.feist@linux.intel.com> Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06peci: Add support for PECI bus driver coreJae Hyun Yoo5-0/+1548
This commit adds driver implementation for PECI bus core into linux driver framework. PECI (Platform Environment Control Interface) is a one-wire bus interface that provides a communication channel from Intel processors and chipset components to external monitoring or control devices. PECI is designed to support the following sideband functions: * Processor and DRAM thermal management - Processor fan speed control is managed by comparing Digital Thermal Sensor (DTS) thermal readings acquired via PECI against the processor-specific fan speed control reference point, or TCONTROL. Both TCONTROL and DTS thermal readings are accessible via the processor PECI client. These variables are referenced to a common temperature, the TCC activation point, and are both defined as negative offsets from that reference. - PECI based access to the processor package configuration space provides a means for Baseboard Management Controllers (BMC) or other platform management devices to actively manage the processor and memory power and thermal features. * Platform Manageability - Platform manageability functions including thermal, power, and error monitoring. Note that platform 'power' management includes monitoring and control for both the processor and DRAM subsystem to assist with data center power limiting. - PECI allows read access to certain error registers in the processor MSR space and status monitoring registers in the PCI configuration space within the processor and downstream devices. - PECI permits writes to certain registers in the processor PCI configuration space. * Processor Interface Tuning and Diagnostics - Processor interface tuning and diagnostics capabilities (Intel Interconnect BIST). The processors Intel Interconnect Built In Self Test (Intel IBIST) allows for infield diagnostic capabilities in the Intel UPI and memory controller interfaces. PECI provides a port to execute these diagnostics via its PCI Configuration read and write capabilities. * Failure Analysis - Output the state of the processor after a failure for analysis via Crashdump. PECI uses a single wire for self-clocking and data transfer. The bus requires no additional control lines. The physical layer is a self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle level near zero volts. The duration of the signal driven high depends on whether the bit value is a logic '0' or logic '1'. PECI also includes variable data transfer rate established with every message. In this way, it is highly flexible even though underlying logic is simple. The interface design was optimized for interfacing between an Intel processor and chipset components in both single processor and multiple processor environments. The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components. Bus speed, error checking, and low protocol overhead provides adequate link bandwidth and reliability to transfer critical device operating conditions and configuration information. This implementation provides the basic framework to add PECI extensions to the Linux bus and device models. A hardware specific 'Adapter' driver can be attached to the PECI bus to provide sideband functions described above. It is also possible to access all devices on an adapter from userspace through the /dev interface. A device specific 'Client' driver also can be attached to the PECI bus so each processor client's features can be supported by the 'Client' driver through an adapter connection in the bus. OpenBMC-Staging-Count: 3 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com> Reviewed-by: James Feist <james.feist@linux.intel.com> Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com> [joel: Fix access_ok usage for 5.0] Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06/dev/mem: add a devmem kernel parameter to activate the deviceCédric Le Goater2-0/+21
For security reasons, some configuration needs to run without /dev/mem but on some occasions, to debug HW for instance, it's still useful to be able to reboot the system with access to physical memory. Add a kernel parameter which activates the /dev/mem device only when 'mem.devmem' is enabled. OpenBMC-Staging-Count: 4 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06mtd: spi-nor: fix options for mx66l51235fAlexander Amelkin1-1/+1
Currently in driver spi-nor there is a line for mx66l51235l. According to Macronix site there is no such part number. The chip detected as such is actually mx66l51235f. According to the datasheet for mx66l51235f, "The device default is in 24-bit address mode" (section 9-10). Hence we removed SPI_NOR_4B_OPCODES option with this commit. OpenBMC-Staging-Count: 5 Fixes: d342b6a973af ("mtd: spi-nor: enable 4B opcodes for mx66l51235l") Signed-off-by: Alexander Soldatov <a.soldatov@yadro.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Lei YU <mine260309@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06soc: aspeed: Miscellaneous control interfacesAndrew Jeffery5-0/+204
The ASPEED BMC SoCs have many knobs and switches that are sometimes design-specific and often defy any approach to unify them under an existing subsystem. Add a driver to translate a devicetree table into sysfs entries to expose bits and fields for manipulation from userspace. This encompasses concepts from scratch registers to boolean conditions to enable or disable host interface features. OpenBMC-Staging-Count: 6 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06pmbus (max31785): Wrap all I2C accessors in one-shot failure handlersAndrew Jeffery1-42/+165
The MAX31785(A) has shown erratic behaviour across multiple system designs, unexpectedly clock stretching and NAKing transactions. Perform a one-shot retry if necessary for all access attempts. OpenBMC-Staging-Count: 7 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Tested-by: George Keishing <gkeishin@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06pmbus (core): Use driver callbacks in pmbus_get_fan_rate()Andrew Jeffery1-4/+4
The driver may have overridden the pmbus_read_byte_data() callback, so make sure we use that to achieve expected behaviour. This helps in the MAX31785 case where we may need to perform a one-shot retry of transfers in the face of a failure. OpenBMC-Staging-Count: 7 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Eddie James <eajames@linux.vnet.ibm.com> Tested-by: George Keishing <gkeishin@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06pmbus (core): One-shot retries for failure to set pageAndrew Jeffery1-2/+10
Work around the shonky behaviour seen with the MAX31785 where we fail to set the page register in some circumstances. There's no real elegant way to do this. We can propagate the error up, but that forces us to retry the operation way up the call tree in any number of places. It also forces callers to split out pmbus_set_page() from the pmbus_{read,write}_{byte,word}_data() functions in order to differentiate between a failure to set the page and a failure to read a register (that might not exist, in which case an error is anticiptated). OpenBMC-Staging-Count: 7 Cc: Eddie James <eajames@linux.vnet.ibm.com> Cc: Matt Spinler <mspinler@linux.vnet.ibm.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Eddie James <eajames@linux.vnet.ibm.com> Tested-by: George Keishing <gkeishin@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06pmbus (max31785): Add support for devicetree configurationAndrew Jeffery1-0/+318
OpenBMC-Staging-Count: 7 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Tested-by: George Keishing <gkeishin@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06iio: dps310: Temperature measurement errataChristopher Bostic1-1/+48
Add a manufacturer's suggested workaround to deal with early revisions of chip that don't indicate correct temperature. Readings can be in the ~60C range when they should be in the ~20's. OpenBMC-Staging-Count: 7 Signed-off-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06iio: Add driver for Infineon DPS310Joel Stanley3-0/+435
The DPS310 is a temperature and pressure sensor. It can be accessed over i2c and SPI. This driver supports polled measurement of temperature over i2c only. OpenBMC-Staging-Count: 7 Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06misc: Add ASPEED mbox driverCyril Bur3-0/+342
This provides access to the mbox registers on the ast2400 and ast2500 SoCs. This driver allows arbitrary reads and writes to the 16 data registers as the other end may have configured the mbox hardware to provide an interrupt when a specific register gets written to. OpenBMC-Staging-Count: 7 [joel: move to drivers/misc as this isn't a mailbox driver] Signed-off-by: Cyril Bur <cyrilbur@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06mtd: spi-nor: aspeed: limit the maximum SPI frequencyCédric Le Goater1-4/+13
The optimize read algo can choose a 100MHz SPI frequency which might be a bit too high for dual output IO on some chips, for the W25Q256 on palmetto for instance. The MX66L1G45G on witherspoon should be fine though. Also, the second chip of the FMC controller does not get any optimize settings for reads. Only the first is configured by U-Boot. To fix these two issues, we introduce a "spi-max-frequency" property in the device tree which will be used to cap the optimize read algorithm and we run the algo on the FMC controller chips as well. By default, the frequency setting is 50MHz. OpenBMC-Staging-Count: 5 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06mtd: spi-nor: aspeed: optimize read modeCédric Le Goater1-0/+191
This is only for SPI controllers as U-Boot should have done it already for the FMC controller using DMAs. The algo is based on the one found in the OpenPOWER pflash tool. It first reads a golden buffer at low speed and then performs reads with different clocks and delay cycles settings to find the fastest configuration for the chip. It can be deactivated at boot time with the kernel parameter : aspeed_smc.optimize_read=0 OpenBMC-Staging-Count: 6 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Alexander Soldatov <a.soldatov@yadro.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06mtd: spi-nor: aspeed: link controller with the ahb clockCédric Le Goater1-0/+10
We will need the AHB frequency to set the HCLK settings in the SMC controller to optimize the reads. OpenBMC-Staging-Count: 6 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-05-06mtd: spi-nor: aspeed: add support for SPI dual IO read modeCédric Le Goater1-11/+43
Implements support for the dual IO read mode on aspeed SMC/FMC controllers which uses both MISO and MOSI lines for data during a read to double the read bandwidth. Still to be done SNOR_PROTO_1_2_2 Based on work from Robert Lippert <roblip@gmail.com> OpenBMC-Staging-Count: 6 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>