summaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Collapse)AuthorFilesLines
2017-02-06pinctrl: aspeed-g5: Add mux configuration for all pinsAndrew Jeffery2-4/+1475
The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> (cherry picked from commit f1337856dd88858bf58bd062306ccbfb63303085) Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-02-06pinctrl: aspeed-g4: Add mux configuration for all pinsAndrew Jeffery1-13/+1084
The patch introducing the g4 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Cc: Timothy Pearson <tpearson@raptorengineering.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> (cherry picked from commit 6d329f14a75f3858a1254abca8b94d4fab556a9a) Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-02-06pinctrl: aspeed: Read and write bits in LPC and GFX controllersAndrew Jeffery4-88/+171
The System Control Unit IP block in the Aspeed SoCs is typically where the pinmux configuration is found, but not always. A number of pins depend on state in one of LPC Host Control (LHC) or SoC Display Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the means to adjust these as necessary. We use syscon to cast a regmap over the GFX and LPC blocks, which is used as an arbitration layer between the relevant driver and the pinctrl subsystem. The regmaps are then exposed to the SoC-specific pinctrl drivers by phandles in the devicetree, and are selected during a mux request by querying a new 'ip' member in struct aspeed_sig_desc. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> (cherry picked from commit 7d29ed88acbbf00e2056634bd4c0172d55d2568c) Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-02-06pinctrl: aspeed: Reset to mainlineAndrew Jeffery4-2640/+28
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-02-06gpio: aspeed: Remove dependence on GPIOF_* macrosAndrew Jeffery1-3/+2
commit 1736f75d35e4 ("gpio: aspeed: Add banks Y, Z, AA, AB and AC") is a (v2) patch which had unresolved review comments[1]. Address the comments by removing the use of macros from the consumer header (this patch represents the diff between v2 and v3[2]). [1] https://lkml.org/lkml/2017/1/26/337 [2] https://lkml.org/lkml/2017/1/26/786 Applied with a commit message tweak from: https://patchwork.kernel.org/patch/9550977/ Fixes: 1736f75d35e4 ("gpio: aspeed: Add banks Y, Z, AA, AB and AC") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-02-06gpio: aspeed: Add banks Y, Z, AA, AB and ACAndrew Jeffery1-14/+135
This is less straight-forward than one would hope, as some banks only have 4 pins rather than 8, others are output only, yet more (W and X, already supported) are input-only, and in the case of the g4 SoC bank AC doesn't exist. Add some structs to describe the varying properties of different banks and integrate mechanisms to deny requests for unsupported configurations. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> (cherry picked from commit 1736f75d35e47409ad776273133d0f558a4c8253) [AJ: Drop irq valid code as it's not present in 4.7] Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-02-06gpio: aspeed: Make bank names stringsJoel Stanley1-7/+7
The Aspeed SoCs have more GPIOs than can be represented with A-Z. The documentation uses two letter names such as AA and AB, so make the names a three-character array in the bank struct to accommodate this. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> (cherry picked from commit 7153f8ef679d5fcb2d9c69a19613399194600f5b) Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-02-06gpio: aspeed: Reset to mainlineAndrew Jeffery2-81/+69
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-02-03drivers: fsi: Fix compilation warningsJoel Stanley1-9/+7
The i2c driver didn't compile cleanly. Silence the warnings. Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-02-03drivers: fsi: i2c: boe engineEdward A. James3-1/+1778
Signed-off-by: Edward A. James <eajames@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-02-03drivers: fsi: i2c: add driver file operations and bus lockingEdward A. James3-1/+2274
Signed-off-by: Edward A. James <eajames@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-02-03drivers: fsi: i2c: probe fsi device for i2c clientEdward A. James3-2/+893
Signed-off-by: Edward A. James <eajames@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-02-03drivers: fsi: i2c: Add engine access wrappersEdward A. James3-0/+486
Signed-off-by: Edward A. James <eajames@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-02-03drivers: fsi: Add i2c client driverEdward A. James6-0/+283
stub for I2C driver over FSI Signed-off-by: Edward A. James <eajames@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-02-03drivers/fsi: Add sysfs file to adjust i-poll periodChristopher Bostic1-0/+26
Create a sysfs file that can read and modify the period for interrupt polling of connected CFAMs. Signed-off-by: Eddie James <eajames@us.ibm.com> Signed-off-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-02-03drivers/fsi: Add Client IRQ Enable / DisableChristopher Bostic1-0/+45
Allow FSI client drivers to enable and disable their engine IRQ's via the exported interfaces fsi_enable_irq and fsi_disable_irq Signed-off-by: Eddie James <eajames@us.ibm.com> Signed-off-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-02-03drivers/fsi: Add slave interrupt pollingChristopher Bostic3-0/+102
Scan slaves present for asserting interrupt signals in the si1s register and call a registered client's interrupt handler as appropriate. Signed-off-by: Eddie James <eajames@us.ibm.com> Signed-off-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-01-16drivers/mailbox: Add Aspeed mailbox driverCyril Bur3-0/+345
This provides access to the mailbox registers on the ast2400 and ast2500 system on chips. This driver allows arbitrary reads and writes to the 16 data registers as the other end may have configured the mbox hardware to provide an interrupt when a specific register gets written to. Signed-off-by: Cyril Bur <cyrilbur@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-01-16drivers/misc: Add Aspeed LPC control driverCyril Bur3-0/+273
In order to manage server systems, there is typically another processor known as a BMC (Baseboard Management Controller) which is responsible for powering the server and other various elements, sometimes fans, often the system flash. The Aspeed BMC family which is what is used on OpenPOWER machines and a number of x86 as well is typically connected to the host via an LPC (Low Pin Count) bus (among others). The LPC bus is an ISA bus on steroids. It's generally used by the BMC chip to provide the host with access to the system flash (via MEM/FW cycles) that contains the BIOS or other host firmware along with a number of SuperIO-style IOs (via IO space) such as UARTs, IPMI controllers. On the BMC chip side, this is all configured via a bunch of registers whose content is related to a given policy of what devices are exposed at a per system level, which is system/vendor specific, so we don't want to bolt that into the BMC kernel. This started with a need to provide something nicer than /dev/mem for user space to configure these things. One important aspect of the configuration is how the MEM/FW space is exposed to the host (ie, the x86 or POWER). Some registers in that bridge can define a window remapping all or portion of the LPC MEM/FW space to a portion of the BMC internal bus, with no specific limits imposed in HW. I think it makes sense to ensure that this window is configured by a kernel driver that can apply some serious sanity checks on what it is configured to map. In practice, user space wants to control this by flipping the mapping between essentially two types of portions of the BMC address space: - The flash space. This is a region of the BMC MMIO space that more/less directly maps the system flash (at least for reads, writes are somewhat more complicated). - One (or more) reserved area(s) of the BMC physical memory. The latter is needed for a number of things, such as avoiding letting the host manipulate the innards of the BMC flash controller via some evil backdoor, we want to do flash updates by routing the window to a portion of memory (under control of a mailbox protocol via some separate set of registers) which the host can use to write new data in bulk and then request the BMC to flash it. There are other uses, such as allowing the host to boot from an in-memory flash image rather than the one in flash (very handy for continuous integration and test, the BMC can just download new images). It is important to note that due to the way the ASpeed chip lets the kernel configure the mapping between host LPC addresses and BMC ram addresses the offset within the window must be a multiple of size. Not doing so will fragment the accessible space rather than simply moving 'zero' upwards. This is caused by the nature of HICR8 being a mask and the way host LPC addresses are translated. Signed-off-by: Cyril Bur <cyrilbur@gmail.com> [joel: Apply v3 from http://patchwork.ozlabs.org/patch/715545/ with small fixes] Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-01-13mtd: spi-nor: aspeed: fix DMA access on AST2500Robert Lippert1-1/+1
AST2500 has additional bits in the dma_addr field. Its easier to just write the full address into the register as the hardware will handle the masking properly. Signed-off-by: Robert Lippert <rlippert@google.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-01-13mtd: spi-nor: aspeed: add support for SPI dual IO read modeRobert Lippert1-7/+23
Implements support for the dual IO read mode on aspeed SMC/FMC controllers which uses both MISO and MOSI lines for data during a read to double the read bandwidth. Signed-off-by: Robert Lippert <rlippert@google.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-01-13mtd: spi-nor: add SPI_NOR_DUAL_READ to mx66l51235lRobert Lippert1-1/+1
Signed-off-by: Robert Lippert <rlippert@google.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-12-08fsi: require ->dev to be set on fsi master registrationJeremy Kerr2-0/+4
Currenly, the fsi GPIO master does not populate ->dev, so we end up with its slaves appearing at the base of the Linux device heirachy. This change fixes the null pointer, and adds a check in the core to disallow this for future masters. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-12-08fsi: skip slaves with no registersJeremy Kerr1-1/+1
Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-12-08fsi: Add 'raw' file for direct slave address-space accessesJeremy Kerr1-0/+52
Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-12-08drivers/fsi: Add SCOM FSI client device driverChris Bostic3-0/+247
Create a simple SCOM engine device driver that reads and writes its control registers via an FSI bus. Signed-off-by: Chris Bostic <cbostic@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-12-08drivers/fsi: Add client driver register utilitiesChris Bostic1-0/+17
Add driver_register and driver_unregister wrappers for FSI. Signed-off-by: Chris Bostic <cbostic@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-12-08drivers/fsi: Add GPIO based FSI masterChris Bostic3-0/+564
Implement a FSI master using GPIO. Will generate FSI protocol for read and write commands to particular addresses. Sends master command and waits for and decodes a slave response. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Chris Bostic <cbostic@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-12-08drivers/fsi: Add master unscanChris Bostic2-1/+37
Allow a master to undo a previous scan. Should a master scan a bus twice it will need to ensure it doesn't double register any previously detected device. Signed-off-by: Chris Bostic <cbostic@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-12-08drivers/fsi: Set slave SMODE to init communicationChris Bostic1-1/+89
Set CFAM to appropriate ID so that the controlling master can manage link memory ranges. Add slave engine register definitions. Signed-off-by: Chris Bostic <cbostic@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-12-08drivers/fsi: Set up links for slave communicationChris Bostic2-3/+38
Enable each link and send a break command in preparation for scanning each link for slaves. Signed-off-by: Chris Bostic <cbostic@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-12-08drivers/fsi: Add device read/write/peek functionsJeremy Kerr1-0/+47
This change introduces the fsi device API: simple read, write and peek accessors for the devices' address spaces. Includes contributions from Chris Bostic <cbostic@us.ibm.com> Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Chris Bostic <cbostic@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-12-08drivers/fsi: scan slaves & register devicesJeremy Kerr1-4/+132
Now that we have fsi_slave devices, scan each for endpoints, and register them on the fsi bus. Includes contributions from Chris Bostic <cbostic@us.ibm.com> Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Chris Bostic <cbostic@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-12-08drivers/fsi: Implement slave initialisationJeremy Kerr1-2/+53
Create fsi_slave devices during the master scan. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Chris Bostic <cbostic@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-12-08drivers/fsi: Add crc4 helpersJeremy Kerr2-0/+42
Add some helpers for the crc checks for the slave configuration table. This works 4-bits-at-a-time, using a simple table approach. We will need this in the FSI core code, as well as any master implementations that need to calculate CRCs in software. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Chris Bostic <cbostic@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-12-08drivers/fsi: Add empty master scanJeremy Kerr1-0/+24
When a new fsi master is added, we will need to scan its links, and slaves attached to those links. This change introduces a little shell to iterate the links, which we will populate with the actual slave scan in a later change. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Chris Bostic <cbostic@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-12-08drivers/fsi: Add slave definitionJeremy Kerr1-0/+9
Add the initial fsi slave device, which is private to the core code. This will be a child of the master, and parent to endpoint devices. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Chris Bostic <cbostic@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-12-08drivers/fsi: Add fsi master definitionJeremy Kerr2-0/+57
Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Chris Bostic <cbostic@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-12-08drivers/fsi: add driver to device matchesJeremy Kerr1-0/+21
Driver bind to devices based on the engine types & (optional) versions. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Chris Bostic <cbostic@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-12-08drivers/fsi: Add empty fsi bus definitionsJeremy Kerr5-0/+55
This change adds the initial (empty) fsi bus definition, and introduces drivers/fsi/. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Chris Bostic <cbostic@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-11-22pinctrl: aspeed: Add parentheses to HW_STRAP testAndrew Jeffery1-1/+1
Squashes a warning: drivers/pinctrl/aspeed/pinctrl-aspeed.c: In function ‘aspeed_sig_expr_set’: drivers/pinctrl/aspeed/pinctrl-aspeed.c:210:24: warning: suggest parentheses around ‘&&’ within ‘||’ [-Wparentheses] offset == HW_STRAP1 && !(desc->mask & SPI1_REG_MASK))) ~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-11-10ipmi/bt-bmc: Add comaptible node for ast2500Joel Stanley1-0/+1
The register layout did not change for the ast2500, so add a compatible string for ast2500 SoCs to use. Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-11-10ipmi/bt-bmc: change compatible node to 'aspeed, ast2400-ibt-bmc'Cédric Le Goater1-2/+2
The Aspeed SoCs have two BT interfaces : one is IPMI compliant and the other is H8S/2168 compliant. The current ipmi/bt-bmc driver implements the IPMI version and we should reflect its nature in the compatible node name using 'aspeed,ast2400-ibt-bmc' instead of 'aspeed,ast2400-bt-bmc'. The latter should be used for a H8S interface driver if it is implemented one day. Signed-off-by: Cédric Le Goater <clg@kaod.org> Acked-by: Corey Minyard <cminyard@mvista.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Joel Stanley <joel@jms.id.au> [we do not have the bindings in dev-4.7, so that hunk was dropped] Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-11-10ipmi: add an Aspeed BT IPMI BMC driverCédric Le Goater4-1/+515
Backport from mainline of the main IPMI BMC driver patch plus fixes : - commit d94655b405ba ("ipmi/bt-bmc: remove redundant return value check of platform_get_resource()") - commit a3e6061bad62 ("ipmi/bt-bmc: add a dependency on ARCH_ASPEED") - commit 1a377a79211a ("ipmi: Fix ioremap error handling in bt-bmc") - commit 54f9c4d0778b ("ipmi: add an Aspeed BT IPMI BMC driver") Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-11-10Revert "misc: Add Aspeed BT IPMI host driver"Cédric Le Goater3-433/+0
This reverts commit f7b4775fdf656f00f1b692bf3db97b3a8088c057. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-11-10clk: add a ahb clock for aspeed g4Cédric Le Goater2-1/+51
and fix g5 ahb clock which has a 3bits ratio. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-11-10mtd: spi-nor: aspeed: rework io routinesCédric Le Goater1-74/+38
The io accessors from pflash are shorter and simpler. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-11-10mtd: spi-nor: aspeed: prepare for fast readCédric Le Goater1-5/+34
Include dummy cycle in the control register value which will be required for fast read. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-11-10mtd: spi-nor: aspeed: use smc_read mode when doing DMAsCédric Le Goater1-2/+2
smc_base is to send commands. smc_read is for flash content accesses. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-11-10mtd: spi-nor: aspeed: add some loggingCédric Le Goater1-4/+5
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-02 05:01:12 +0300