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path: root/drivers/spi/spi-cadence.c
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2018-04-18spi: cadence: Add usleep_range() for cdns_spi_fill_tx_fifo()sxauwsk1-0/+8
In case of xspi work in busy condition, may send bytes failed. once something wrong, spi controller did't work any more My test found this situation appear in both of read/write process. so when TX FIFO is full, add one byte delay before send data; Signed-off-by: sxauwsk <sxauwsk@163.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-08-08spi: cadence: Add support for context lossShubhrajyoti Datta1-0/+2
Context could be lost across the suspend and resume. Reinit the driver to tide over. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-08-08spi: cadence: change sequence of calling runtime_enableNaga Sureshkumar Relli1-1/+1
call pm_runtime_enable after set_active other wise it will enable clock always. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-04-26spi: cadence: Allow for GPIO pins to be used as chipselectsMoritz Fischer1-0/+65
This adds support for using GPIOs for chipselects as described by the default dt-bindings. Signed-off-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-04-18spi: cadence: mark pm functions __maybe_unusedArnd Bergmann1-2/+2
The newly added runtime PM support for the cadence spi driver causes harmless warnings when PM is disabled: drivers/spi/spi-cadence.c:681:12: warning: 'cnds_runtime_suspend' defined but not used drivers/spi/spi-cadence.c:652:12: warning: 'cnds_runtime_resume' defined but not used This adds __maybe_unused annotations to the respective functions to shut up the warnings, while leaving the code in place for compile testing and avoiding ugly #ifdefs. Fixes: d36ccd9f7ea4 ("spi: cadence: Runtime pm adaptation") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-04-06spi: cadence: Fix some checkpatch warningsShubhrajyoti Datta1-2/+4
No functional change. Fixing some style related issues CHECK: multiple assignments should be avoided + new_ctrl_reg = ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); CHECK: Alignment should match open parenthesis +static void cdns_spi_config_clock_freq(struct spi_device *spi, + struct spi_transfer *transfer) CHECK: Please use a blank line after function/struct/union/enum declarations +} +static int cdns_prepare_message(struct spi_master *master, Signed-off-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-04-05spi: cadence: Return the error code for cdns_spi_suspend and cdns_spi_resumeShubhrajyoti Datta1-7/+3
Return the error code for cdns_spi_suspend and cdns_spi_resume. Also fixes a comment where which claims that the error code is returned. Signed-off-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-04-05spi: cadence: Remove the clock enable and disable from suspend and resumeShubhrajyoti Datta1-19/+0
Now that the clocks are enabled and disabled per transaction , remove the clock enable and disable from resume and suspend hooks. Signed-off-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-04-05spi: cadence: Runtime pm adaptationShubhrajyoti Datta1-2/+68
Currently the clocks are enabled at probe and disabled at remove. This patch moves the clock enable to the start of transaction and disables at the end. Signed-off-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-04-05spi: cadance: Fix the DocumentationShubhrajyoti Datta1-1/+1
cdns_spi_chipselect has parameter is_high however the comment describes it as is_on. Also fixes the below warning. drivers/spi/spi-cadence.c:182: warning: No description found for parameter 'is_high' drivers/spi/spi-cadence.c:182: warning: Excess function parameter 'is_on' description in 'cdns_spi_chipselect' Signed-off-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-04-05spi: cadence: Fix probe error handlingShubhrajyoti Datta1-2/+2
The clock disabling is missed out in some error cases at probe. Fix the same. Signed-off-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-04-05spi: cadence: Remove _MASK and _OFFSET suffixShubhrajyoti Datta1-87/+74
Remove the _MASK and _OFFSET from the macros. It improves readability, removes some checkpatch error for exceeding 80 chars and also prevents some linebreaks. Signed-off-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-04-05spi: cadence: Fix a check patch warningShubhrajyoti Datta1-1/+1
CHECK: Comparison to NULL could be written "!master" + if (master == NULL) Signed-off-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-01-05spi: cadence: use to_platform_device()Geliang Tang1-4/+2
Use to_platform_device() instead of open-coding it. Signed-off-by: Geliang Tang <geliangtang@163.com> Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-12-08Merge remote-tracking branches 'spi/topic/atmel', 'spi/topic/cadence', ↵Mark Brown1-13/+11
'spi/topic/dw' and 'spi/topic/fsl-cpm' into spi-next
2014-11-28spi: cadence: Fix 3-to-8 mux modeLars-Peter Clausen1-2/+7
In 3-to-8 mux mode for the CS pins we need to set the PERI_SEL bit in the control register. Currently the driver never sets this bit even when configured for 3-to-8 mux mode. This patch adds code which sets the bit during device initialization when necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-11-28spi: cadence: Init HW after reading devicetree attributesPaul Cercueil1-13/+11
This will make it possible to use the settings specified in the devicetree to configure the hardware. Signed-off-by: Paul Cercueil <paul.cercueil@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-08-17spi: cadence: Remove .owner field for driverMichal Simek1-1/+0
There is no need to init .owner field. Based on the patch from Peter Griffin <peter.griffin@linaro.org> "mmc: remove .owner field for drivers using module_platform_driver" This patch removes the superflous .owner field for drivers which use the module_platform_driver API, as this is overriden in platform_driver_register anyway." Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2014-08-04Merge remote-tracking branches 'spi/topic/adi-v3', 'spi/topic/atmel', ↵Mark Brown1-1/+1
'spi/topic/cleanup' and 'spi/topic/davinci' into spi-next
2014-07-11spi: cadence: Configure SPI clock in the prepare_message() callbackLars-Peter Clausen1-2/+7
Currently the cadence SPI driver does the SPI clock configuration (setup CPOL and CPHA) in the prepare_transfer_hardware() callback. The prepare_transfer_hardware() callback is only called though when the controller transitions from a idle state to a non-idle state. Such a transitions happens when the message queue goes from empty to non-empty. If multiple messages from different SPI slaves with different clock settings are in the message queue the clock settings will not be properly updated when switching from one slave device to another. Instead do the updating of the clock configuration in the prepare_message() callback which will be called for each individual message. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@linaro.org>
2014-07-11spi: cadence: Make sure that clock polarity changes are appliedLars-Peter Clausen1-7/+19
It seems that the cadence SPI controller does not immediately change the clock polarity setting when writing the CR register. Instead the change is delayed until the next transfer starts. This happens after the chip select line has already been asserted. As a result the first transfer after a clock polarity change will generate spurious clock transitions which typically results in the SPI slave not being able to properly understand the message. Toggling the ER register seems to cause the SPI controller to apply the clock polarity changes, so implement this as a workaround to fix the issue. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@linaro.org>
2014-06-06spi: cadence: Make of_device_id array constJingoo Han1-1/+1
Make of_device_id array const, because all OF functions handle it as const. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2014-04-15spi: Add driver for Cadence SPI controllerHarini Katakam1-0/+673
Add driver for Cadence SPI controller. This is used in Xilinx Zynq. Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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