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path: root/drivers/pinctrl
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2016-01-05pinctrl: lantiq: 2 pins have the wrong mux listJohn Crispin1-2/+2
The latest vendor SDK contained this patch. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-25pinctrl: qcom: make PMIC drivers boolLinus Walleij1-2/+2
commit ab4256cfeab91569e1d96e7f0014538fe0845259 "pinctrl: qcom: pmic-gpio/mpp: of_irq_count() == npins" made the Qualcomm PMIC pin control drivers make use of of_irq_count() which is not an exported function, making modular builds fail. Fix this by marking the drivers as compiled-in/bool. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Andy Gross <andy.gross@linaro.org> Cc: Mark Brown <broonie@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-24pinctrl: nsp-gpio: forever loop in nsp_gpio_get_strength()Dan Carpenter1-1/+2
There is a signedness bug here so the loop will never exit. Fixes: 8bfcbbbcabe0 ('pinctrl: nsp: add gpio-a driver support for Broadcom NSP SoC') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-24Merge tag 'samsung-drivers-4.5' of ↵Linus Walleij3-0/+106
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into devel Exynos-specific drivers for 4.5: 1. Add a pinctrl driver for Exynos5410.
2015-12-22pinctrl: mediatek: convert to arch_initcallDaniel Kurtz3-3/+3
Move pinctrl initialization earlier in boot so that real devices can find their pctldev without probe deferring. Note: We don't change mt6397 probe order in this patch, since MT6397 is mfd PMIC, which depends on pwrap on main AP to work. Since pmic-wrap itself is module_platform_driver, we keep it as module_init. A later patch will convert both pmic-wrap, and all functions of the MT6397 mfd to arch_initcall. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-22pinctrl: bcm2835: Fix memory leak in error pathStefan Wahren1-1/+1
In case of an invalid pin value bcm2835_pctl_dt_node_to_map() would leak the pull configs of already assigned pins. So avoid this by calling the free map function in error case. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Fixes: e1b2dc70cd5b ("pinctrl: add bcm2835 driver") Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-22pinctrl: mediatek: add missing of_node_putJulia Lawall1-0/+1
for_each_child_of_node performs an of_node_get on each iteration, so a return from the loop requires an of_node_put. A simplified version of the semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ local idexpression n; expression e,e1; @@ for_each_child_of_node(e1,n) { ... ( of_node_put(n); | e = n | return n; | + of_node_put(n); ? return ...; ) ... } // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-22pinctrl: rockchip: add missing of_node_putJulia Lawall1-1/+4
for_each_child_of_node performs an of_node_get on each iteration, so a return from the loop requires an of_node_put. A simplified version of the semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ local idexpression n; expression e,e1; @@ for_each_child_of_node(e1,n) { ... ( of_node_put(n); | e = n | return n; | + of_node_put(n); ? return ...; ) ... } // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-22pinctrl: sh-pfc: add missing of_node_putJulia Lawall1-1/+3
for_each_child_of_node performs an of_node_get on each iteration, so a goto out of the loop requires an of_node_put. A simplified version of the semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ local idexpression n; expression e,e1; identifier l; @@ for_each_child_of_node(e1,n) { ... ( of_node_put(n); | e = n | return n; | + of_node_put(n); ? goto l; ) ... } l: ... when != n // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-22pinctrl: sirf: add missing of_node_putJulia Lawall1-2/+6
for_each_child_of_node performs an of_node_get on each iteration, so a return from the loop requires an of_node_put. A simplified version of the semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ local idexpression n; expression e,e1; @@ for_each_child_of_node(e1,n) { ... ( of_node_put(n); | e = n | return n; | + of_node_put(n); ? return ...; ) ... } // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-22pinctrl-tegra: add missing of_node_putJulia Lawall2-1/+4
for_each_child_of_node performs an of_node_get on each iteration, so a return from the loop requires an of_node_put. A simplified version of the semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ local idexpression n; expression e,e1; @@ for_each_child_of_node(e1,n) { ... ( of_node_put(n); | e = n | return n; | + of_node_put(n); ? return ...; ) ... } // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-22pinctrl: sunxi: Add A80 special pin controllerMaxime Ripard3-0/+187
Like the previous designs, the A80 has a special pin controller for the critical pins, like the PMIC bus. Add a driver for this controller. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> [wens: Add A80 compatible strings to bindings doc; fix pin function names based on v1.3 datasheet; constify of_device_id table] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-22Merge branch 'sh-pfc-for-v4.5' of ↵Linus Walleij5-0/+478
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
2015-12-21pinctrl: bcm/cygnys/iproc: fixup rebase issueLinus Walleij1-1/+1
Somehow this variable name screwed up in some rebase, fixed it. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Reported-by: Pramod Kumar <pramodku@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-17Merge tag 'v4.4-rc5' into develLinus Walleij4-16/+13
Linux 4.4-rc5
2015-12-17pinctrl: fixup problematic flagLinus Walleij1-1/+0
This removes the set_irq_flags() call that unfortunately slipped into the BCM NSP driver. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Yendapally Reddy Dhananjaya Reddy <yrdreddy@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-16pinctrl: sh-pfc: r8a7791: add EtherAVB pin groupsSergei Shtylyov1-0/+93
Add the EtherAVB pin groups to the R8A7791 PFC driver. Also add the copyright for all the Cogent Embedded's past work on this file. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-12-16pinctrl: sh-pfc: r8a7795: Add SATA supportTakeshi Kihara1-0/+24
This patch adds SATA0 pinmux support to r8a7795 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [uli: adjusted for new PFC driver] Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-12-16pinctrl: sh-pfc: r8a7795: Add SDHI supportTakeshi Kihara1-0/+274
Add SDHI[0-3] pinmux support to r8a7795 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Dirk Behme <dirk.behme@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-12-16pinctrl: sh-pfc: r8a7794: Add SCIF_CLK supportGeert Uytterhoeven1-0/+23
Add pins, groups, and a function for SCIF_CLK, which is the external clock source for the Baud Rate Generator for External Clock (BRG) on (H)SCIF. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-16pinctrl: sh-pfc: r8a7790: Add SCIF_CLK supportGeert Uytterhoeven1-0/+23
Add pins, groups, and a function for SCIF_CLK, which is the external clock source for the Baud Rate Generator for External Clock (BRG) on (H)SCIF. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-16pinctrl: sh-pfc: r8a7779: Add SCIF_CLK supportGeert Uytterhoeven1-0/+41
Add pins, groups, and a function for SCIF_CLK, which is the external clock source for the Baud Rate Generator for External Clock (BRG) on SCIF. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-15pinctrl: pxa: pxa2xx: add pin control skeletonRobert Jarzmik1-2/+2
The wrong free functions were used to release temporary buffers. This didn't show up in the normal driver's life. Yet in suspend to RAM, the managed resource list is walked, and as memory was released, the list is corrupted and make the kernel Oops. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-11pinctrl: rockchip: add support for the rk3228Jeffy Chen1-0/+53
The pinctrl of rk3228 is much the same as rk3288's, but without pmu. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-11pinctrl: sunxi: Add H3 PIO controller supportJens Kuske3-0/+520
The H3 uses the same pin controller as previous SoC's from Allwinner. Add support for the pins controlled by the main PIO controller. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-11pinctrl: bcm: Default PINCTRL_BCM281XX to y for ARCH_BCM_MOBILEFlorian Fainelli1-0/+1
This driver is mandatory for proper operation on the platforms covered by the ARCH_BCM_MOBILE Kconfig symbol, make sure we do that driver on for these platforms. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-11pinctrl: at91: Use platform_register/unregister_drivers()Thierry Reding1-7/+7
These new helpers simplify implementing multi-driver modules and properly handle failure to register one driver by unregistering all previously registered drivers. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-11pinctrl: adi2: Use platform_register/unregister_drivers()Thierry Reding1-16/+8
These new helpers simplify implementing multi-driver modules and properly handle failure to register one driver by unregistering all previously registered drivers. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-11Revert "pinctrl: intel: fix bug of register offset calculation"Linus Walleij4-20/+17
This reverts commit c5cdcba3d54b9bd2443bd0afe9f4828f802a944f.
2015-12-10Merge branch 'bcm-nsp' into develLinus Walleij3-0/+767
2015-12-10pinctrl: nsp: add gpio-a driver support for Broadcom NSP SoCYendapally Reddy Dhananjaya Reddy3-0/+767
This adds the initial support of the Broadcom NSP gpio-a driver. Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yrdreddy@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: at91-pio4: fix memleak after using dt mapLudovic Desroches1-6/+9
configs is allocated by pinconf_generic_parse_dt_config(), pinctrl_utils_add_map_configs() duplicates configs so it can and has to be freed to prevent memory leaks. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Reported-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: atlas7: add pulse conter pin group without direction pinGuoying Zhang1-0/+13
DR needs use the pulse counter direction pin as common gpio function. Signed-off-by: Guoying Zhang <Guoying.Zhang@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: atlas7: adjust vip pin groups for atlas7Wei Chen1-4/+10
The vip low 8bit mode and vip high 8 bit mode pin groups had missed 3 pins:vip_vsync, vip_hsync and vip_pxclk. Without these 3 pins, the vip could not work properly. Now we add these 3 pins into these two pin groups. Signed-off-by: Wei Chen <Wei.Chen@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: atlas7: adjust pin groups of atlas7 nanddiskWei Chen1-61/+27
Remove write-protect and chip-selector pins from nand pin group. And then create two separate pin groups for these two pin. So the nand driver can choose correct pin groups as board desgin: For example: 1. nand without wp&cs: nand@17050000 { pinctrl-0 = <&nd_df_basic_pmx>; }; 2. nand with wp nand@17050000 { pinctrl-0 = <&nd_df_basic_pmx &nd_df_wp_pmx>; }; 3. nand with cs: nand@17050000 { pinctrl-0 = <&nd_df_basic_pmx &nd_df_cs_pmx>; }; 4. nand with wp&cs: nand@17050000 { pinctrl-0 = <&nd_df_basic_pmx &nd_df_wp_pmx &nd_df_cs_pmx>; }; Signed-off-by: Wei Chen <Wei.Chen@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: altas7: add sd9 function mux supportYonghui Zhang1-8/+36
The sd9 pin mux with sd3 and it is selected by SYS2PCI_SDIO9SEL. This makes the codes ugly since the register is not in pinctrl module. Signed-off-by: Yonghui Zhang <yonghui.zhang@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: atlas7: add cs line for atlas7 nandWei Chen1-0/+29
The nand in atlas7 has two chip select line. But in most time, the nand only has one chip, so only one chip select line is enough. The nand driver select this new pin group can free one chip select line for other modules to avoid pin conflict. Signed-off-by: Wei Chen <Wei.Chen@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: activate pxa architectureRobert Jarzmik2-0/+2
As the pxa architecture, at least for pxa27x, supports pin control, activate it in the pinctrl tree. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: pxa: add pxa27x architectureRobert Jarzmik3-0/+576
Add the pxa27x architecture, which is a pxa2xx with 128 pins. The registers spacing, and pins logic is common to pxa2xx, only the pins and their alternate function are specific to pxa27x. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: pxa: pxa2xx: add pin configuration supportRobert Jarzmik1-0/+63
Add pin configuration for pxa2xx architectures. PXA doesn't provide any bias, push, pull capabilities. The only capability is to set a state for the pins when the platform enter sleep or deep sleep mode. The state of a pin is set by : - whether the GPIO direction was input or output - if it is output, a register set programs whether the pin should be held to ground or VccIO Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: pxa: pxa2xx: add pin muxingRobert Jarzmik1-0/+121
The driver is inspired from the sunxi driver. The pxa architecture specificities leading to the driver are : - each pin has 8 possible alternate functions - 4 of these are output kind - 4 of these are input kind - there is always a "gpio input" and "gpio output" function - the function matrix is very scattered : - some functions can be found on 5 different pads - the number of functions is greater than the number of pins - there is no "topology" grouping of pins (such as all SPI in one corner of the die) Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: pxa: pxa2xx: add pin control skeletonRobert Jarzmik3-0/+353
Add a pincontrol driver for pxa2xx architecture, encompassing all pxa25x and pxa27x variants. This is only the pin muxing part of the driver. One specific consideration is also the memory space (MMIO), which is intertwined with the GPIO registers. To make things worse, the GPIO direction register also affect pin muxing, as it chooses the "kind" of pin, ie. the 4 output functions or 4 input functions. The mapping between pinctrl notions and PXA Technical Reference Manual is as follows : - a pin is obviously a pin - a group is also a pin, ie. group P101 is the pin 101 - a mux function is an alternate function (ie. gpio-in, gpio-out, MMCLK, BTRTS, etc ...) The individual architecture (pxa27x, pxa25x) instantiate a pin control by providing a table of pins, each pin being provided a list of PXA_FUNCTION (alternate functions). Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10Merge branch 'sh-pfc-for-v4.5' of ↵Linus Walleij11-262/+1949
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
2015-12-09pinctrl: mvebu: complain about missing group after checking variantSebastian Hesselbarth1-13/+16
Common MVEBU pinctrl driver core gets an array of controls to modify a specific set of registers and an array of modes for each pingroup from each of the different SoC families of MVEBU. Some SoC families comprise different variants that differ in available pingroups and also controls, but to ease driver development, we can pass a variant mask to disable specific pingroups for some variants. However, controls are limited to the true number of pinctrl groups avaiable on a variant. Now, when pinctrl core driver parses over above arrays, it tries to match modes with available controls and complains about missing controls for modes that are passed to the core but actually are not avaiable on a variant with: kirkwood-pinctrl f1010000.pin-controller: unknown pinctrl group 36 This warning is a false-positive and annoying, so move the warning after we checked the variant mask for each mode setting. Also, if there is no supported setting for this variant, do not complain at all. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reported-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-08pinctrl: sh-pfc: r8a7795: Add SCIF_CLK supportGeert Uytterhoeven1-0/+24
Add pins, groups, and a function for SCIF_CLK, which is the external clock source for the Baud Rate Generator for External Clock (BRG) on (H)SCIF. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-08pinctrl: sh-pfc: r8a7791: Add SCIF_CLK supportGeert Uytterhoeven1-0/+25
Add pins, groups, and a function for SCIF_CLK, which is the external clock source for the Baud Rate Generator for External Clock (BRG) on (H)SCIF. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-08pinctrl: sh-pfc: sh73a0: Add MSIOF supportGeert Uytterhoeven1-0/+546
Add pins, groups, and a function for the 4 MSIOF devices. Note that the pin function name of MSIOF3 is named BBIF1. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-12-08pinctrl: sh-pfc: sh73a0: Correct comment for LCD2 data pinsGeert Uytterhoeven1-1/+1
The 12 data pins of LCD2 are numbered 0..11, not 0..12. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-12-08pinctrl: sh-pfc: r8a7740: Correct comment for LCD1 data pinsGeert Uytterhoeven1-1/+1
The 12 data pins of LCD1 are numbered 0..11, not 0..12. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-12-08pinctrl: sh-pfc: emev2: Correct comment for CFI data pinsGeert Uytterhoeven1-1/+1
The 8 data pins of the Compact Flash Interface are numbered 0..7, not 0..8. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-05 07:43:33 +0300