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path: root/drivers/pinctrl
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2017-01-05pinctrl: Fix panic when pinctrl devices with hogs are unregisteredJon Hunter1-2/+6
Commit df61b366af26 ('pinctrl: core: Use delayed work for hogs') deferred part of the registration for pinctrl devices if the pinctrl device has hogs. This introduced a window where if the pinctrl device with hogs was sucessfully registered, but then unregistered again (which could be caused by parent device being probe deferred) before the delayed work has chanced to run, then this will cause a kernel panic to occur because: 1. The 'pctldev->p' has not yet been initialised and when unregistering the pinctrl device we only check to see if it is an error value, but now it could also be NULL. 2. The pinctrl device may not have been added to the 'pinctrldev_list' list and we don't check to see if it was added before removing. Fix up the above by checking to see if the 'pctldev->p' pointer is an error value or NULL before putting the pinctrl device and verifying that the pinctrl device is present in 'pinctrldev_list' before removing. Fixes: df61b366af26 ('pinctrl: core: Use delayed work for hogs') Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-03pinctrl: amd: fix compilation warningLinus Walleij1-0/+3
3bfd44306c65 ("pinctrl: amd: Add support for additional GPIO") created the following warning: drivers/pinctrl/pinctrl-amd.c: In function 'amd_gpio_dbg_show': drivers/pinctrl/pinctrl-amd.c:210:3: warning: 'pin_num' may be used uninitialized in this function [-Wmaybe-uninitialized] for (; i < pin_num; i++) { ^ drivers/pinctrl/pinctrl-amd.c:172:21: warning: 'i' may be used uninitialized in this function [-Wmaybe-uninitialized] unsigned int bank, i, pin_num; ^ Fix this by adding a guarding default case for illegal bank numbers. Cc: S-k Shyam-sundar <Shyam-sundar.S-k@amd.com> Cc: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-03pinctrl: imx: use generic pinmux helpers for managing functionsGary Bisson3-94/+18
Now using function_desc structure instead of imx_pmx_func. Also leveraging generic functions to retrieve functions count/name/groups. The imx_free_funcs function can be removed since it is now handled by the core driver during unregister. Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-03pinctrl: imx: use generic pinctrl helpers for managing groupsGary Bisson3-141/+69
Now using group_desc structure instead of imx_pin_group. Also leveraging generic functions to retrieve groups count/name/pins. The imx_free_pingroups function can be removed since it is now handled by the core driver during unregister. Finally the device tree parsing is moved after the pinctrl driver registration since this latter initializes the radix trees. Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-03pinctrl: qcom: msm8660: rename some SDC1->SDC4Linus Walleij1-3/+3
These four pins are for SDC4, not SDC1. They are grouped for SDC4 later in the file so this must be a typo. Reviewed-by: Björn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-03pinctrl: single: Use generic pinmux helpers for managing functionsTony Lindgren2-117/+19
We can now drop the driver specific code for managing functions. Signed-off-by: Tony Lindgren <tony@atomide.com> [Replaces GENERIC_PINMUX with GENERIC_PINMUX_FUNCTIONS] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-03pinctrl: single: Use generic pinctrl helpers for managing groupsTony Lindgren2-146/+12
We can now drop the driver specific code for managing groups. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-03pinctrl: core: Add generic pinctrl functions for managing groupsTony Lindgren5-0/+243
We can add generic helpers for function handling for cases where the pin controller driver does not need to use static arrays. Signed-off-by: Tony Lindgren <tony@atomide.com> [Renamed the Kconfig item and moved things around] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-03pinctrl: stricten up generic group codeLinus Walleij3-18/+22
Rename the symbol PINCTRL_GENERIC to PINCTRL_GENERIC_GROUPS since it all pertains to groups. Replace everywhere. ifdef out the radix tree and the struct when not using the generic groups. Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-03pinctrl: core: Add generic pinctrl functions for managing groupsTony Lindgren3-0/+228
We can add generic helpers for pin group handling for cases where the pin controller driver does not need to use static arrays. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-03pinctrl: add some comments to the hog/late init codeLinus Walleij1-0/+12
It confused me a bit so it may confuse others. Make it crystal clear what is going on here for any future readers. Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-03pinctrl: core: Use delayed work for hogsTony Lindgren4-39/+93
Having the pin control framework call pin controller functions before it's probe has finished is not nice as the pin controller device driver does not yet have struct pinctrl_dev handle. Let's fix this issue by adding deferred work for late init. This is needed to be able to add pinctrl generic helper functions that expect to know struct pinctrl_dev handle. Note that we now need to call create_pinctrl() directly as we don't want to add the pin controller to the list of controllers until the hogs are claimed. We also need to pass the pinctrl_dev to the device tree parser functions as they otherwise won't find the right controller at this point. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-30pinctrl: imx: use radix trees for groups and functionsGary Bisson2-28/+141
This change is inspired from the pinctrl-single architecture. The problem with current implementation is that it isn't possible to add/remove functions and/or groups dynamically. The radix tree offers an easy way to do so. The intent is to offer a follow-up patch later that will enable the use of pinctrl nodes in dt-overlays. Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-30pinctrl: imx: remove const qualifier of imx_pinctrl_soc_infoGary Bisson1-17/+17
Otherwise can't dynamically update fields such as ngroups which can change over time (with a dt-overlay for instance). Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-30pinctrl: single: fix spelling mistakes on "Ivalid"Colin Ian King1-1/+1
Trivial fixe to spelling mistake "Ivalid" to "Invalid" in dev_err error message. Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-30pinctrl: simplify check for pin request conflictsVladimir Zapolskiy1-28/+15
This is a non-functional change, which deletes code duplication in two of four if-if branches by reordering the checks. Functional identity of the code change can be shown by running through the whole truth table of boolean arguments. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-30pinctrl: update my email addressJohn Crispin6-6/+6
This patch updates my email address as I no longer have access to the old one. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-30pinctrl: sirf: atlas7: Improve code layoutChristophe JAILLET1-3/+3
Add some tab in order to improve indentation. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-30pinctrl: sirf: atlas7: Add missing 'of_node_put()'Christophe JAILLET1-3/+4
Reference to 'sys2pci_np' should be dropped in all cases here, not only in error handling path. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-30pinctrl: stm32: activate strict mux modeGabriel Fernandez1-0/+1
This activates strict mode muxing for the STM32 pin controllers, as these do not allow GPIO and functions to use the same pin simultaneously. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-28pinctrl: amd: Add support for additional GPIOShah, Nehal-bakulchandra2-13/+20
This patch adds support for new Bank and adds IRQCHIP_SKIP_SET_WAKE flag. Reviewed-by: S-k, Shyam-sundar <Shyam-sundar.S-k@amd.com> Signed-off-by: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-28pinctrl: aspeed: Fix kerneldoc return descriptionsAndrew Jeffery1-6/+6
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-28pinctrl: aspeed-g5: Add mux configuration for all pinsAndrew Jeffery2-4/+1475
The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-28pinctrl: aspeed-g4: Add mux configuration for all pinsAndrew Jeffery1-13/+1084
The patch introducing the g4 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Cc: Timothy Pearson <tpearson@raptorengineering.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-28pinctrl: aspeed: Read and write bits in LPC and GFX controllersAndrew Jeffery4-88/+171
The System Control Unit IP block in the Aspeed SoCs is typically where the pinmux configuration is found, but not always. A number of pins depend on state in one of LPC Host Control (LHC) or SoC Display Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the means to adjust these as necessary. We use syscon to cast a regmap over the GFX and LPC blocks, which is used as an arbitration layer between the relevant driver and the pinctrl subsystem. The regmaps are then exposed to the SoC-specific pinctrl drivers by phandles in the devicetree, and are selected during a mux request by querying a new 'ip' member in struct aspeed_sig_desc. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-16Merge tag 'armsoc-dt' of ↵Linus Torvalds1-6/+0
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together. We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board: - Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors These are commercially available consumer platforms we now support: - Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385 And a couple of new boards targeted at developers, makers or industrial integration: - Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module Other changes: - added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq - Continued fixes for W=1 dtc warnings - The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST - The exynos4415 dtsi file is removed as nothing uses it. - Intel PXA25x can now be booted using devicetree" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...
2016-12-13Merge tag 'pinctrl-v4.10-1' of ↵Linus Torvalds66-1345/+5688
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pinctrl updates from Linus Walleij: "Bulk pin control changes for the v4.10 kernel cycle: No core changes this time. Mainly gradual improvement and feature growth in the drivers. New drivers: - New driver for TI DA850/OMAP-L138/AM18XX pinconf - The SX150x was moved over from the GPIO subsystem and reimagined as a pin control driver with GPIO support in a joint effort by three independent users of this hardware. The result was amazingly good! - New subdriver for the Oxnas OX820 Improvements: - The sunxi driver now supports the generic pin control bindings rather than the sunxi-specific. Add debouncing support to the driver. - Simplifications in pinctrl-single adding a generic parser. - Two downstream fixes and move the Raspberry Pi BCM2835 over to use the generic GPIOLIB_IRQCHIP" * tag 'pinctrl-v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (92 commits) pinctrl: sx150x: use new nested IRQ infrastructure pinctrl: sx150x: handle missing 'advanced' reg in sx1504 and sx1505 pinctrl: sx150x: rename 'reg_advance' to 'reg_advanced' pinctrl: sx150x: access the correct bits in the 4-bit regs of sx150[147] pinctrl: mt8173: set GPIO16 to usb iddig mode pinctrl: bcm2835: switch to GPIOLIB_IRQCHIP pinctrl: New driver for TI DA850/OMAP-L138/AM18XX pinconf devicetree: bindings: pinctrl: Add binding for ti,da850-pupd Documentation: pinctrl: palmas: Add ti,palmas-powerhold-override property definition pinctrl: intel: set default handler to be handle_bad_irq() pinctrl: sx150x: add support for sx1501, sx1504, sx1505 and sx1507 pinctrl: sx150x: sort chips by part number pinctrl: sx150x: use correct registers for reg_sense (sx1502 and sx1508) pinctrl: imx: fix imx_pinctrl_desc initialization pinctrl: sx150x: support setting multiple pins at once pinctrl: sx150x: various spelling fixes and some white-space cleanup pinctrl: mediatek: use builtin_platform_driver pinctrl: stm32: use builtin_platform_driver pinctrl: sunxi: Testing the wrong variable pinctrl: nomadik: split up and comments MC0 pins ...
2016-12-13Merge tag 'gpio-v4.10-1' of ↵Linus Torvalds3-0/+1077
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull GPIO updates from Luinus Walleij: "Bulk GPIO changes for the v4.10 kernel cycle: Core changes: - Simplify threaded interrupt handling: instead of passing numbed parameters to gpiochip_irqchip_add_chained() we create a new call: gpiochip_irqchip_add_nested() so the two types are clearly semantically different. Also make sure that all nested chips call gpiochip_set_nested_irqchip() which is necessary for IRQ resend to work properly if it happens. - Return error on seek operations for the chardev. - Clamp values set as part of gpio[d]_direction_output() so that anything != 0 will be send down to the driver as "1" not the value passed in. - ACPI can now support naming of GPIO lines, hogs and holes in the GPIO lists. New drivers: - The SX150x driver was deemed unfit for the GPIO subsystem and was moved over to a combined GPIO+pinctrl driver in the pinctrl subsystem. New features: - Various cleanups to various drivers" * tag 'gpio-v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (49 commits) gpio: merrifield: Implement gpio_get_direction callback gpio: merrifield: Add support for hardware debouncer gpio: chardev: Return error for seek operations gpio: arizona: Tidy up probe error path gpio: arizona: Remove pointless set of platform drvdata gpio: pl061: delete platform data handling gpio: pl061: move platform data into driver gpio: pl061: rename variable from chip to pl061 gpio: pl061: rename state container struct gpio: pl061: use local state for parent IRQ storage gpio: set explicit nesting on drivers gpio: simplify adding threaded interrupts gpio: vf610: use builtin_platform_driver gpio: axp209: use correct register for GPIO input status gpio: stmpe: fix interrupt handling bug gpio: em: depnd on ARCH_SHMOBILE gpio: zx: depend on ARCH_ZX gpio: x86: update config dependencies for x86 specific hardware gpio: mb86s7x: use builtin_platform_driver gpio: etraxfs: use builtin_platform_driver ...
2016-12-07pinctrl: sx150x: use new nested IRQ infrastructureLinus Walleij1-3/+7
Use the new gpiochip_irqchip_add_nested() and gpiochip_set_nested_irqchip() calls to properly created a nested irqchip and mark all child irqs properly with their parent IRQ. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-07pinctrl: sx150x: handle missing 'advanced' reg in sx1504 and sx1505Peter Rosin1-0/+1
This fixes a problem where sx150x_regmap_reg_width() returns 8 for the data register (reg 0) for sx1504 where it should return 4, and return a correct 8 for sx1505 but for the wrong reason (both chips lack the 'advanced' register). This is not a real problem, since nothing depends on the function returning 4 or 8, and certainly not if it is returning 8 for the wrong reason. But fix this to avoid nasty surprises down the line. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-07pinctrl: sx150x: rename 'reg_advance' to 'reg_advanced'Peter Rosin1-10/+10
This matches the datasheets and is less confusing since the register has nothing to with advancing anything. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-07pinctrl: sx150x: access the correct bits in the 4-bit regs of sx150[147]Peter Rosin1-1/+2
The code assumes 8-bit or 16-bit width registers, but three of the chips (sx1501/sx1504/sx1507) are 4-bit. So, try to handle 4-bit chips as well, they leave the high part of each register unused. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-07pinctrl: mt8173: set GPIO16 to usb iddig modeChunfeng Yun1-1/+1
the default mode of GPIO16 pin is gpio, when set EINT16 to IRQ_TYPE_LEVEL_HIGH, no interrupt is triggered, it can be fixed when set its default mode as usb iddig. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-07pinctrl: bcm2835: switch to GPIOLIB_IRQCHIPLinus Walleij2-76/+65
It should be possible to use the GPIOLIB_IRQCHIP helper library with the BCM2835 driver since it is a pretty straight forward cascaded irqchip. The only difference from other drivers is that the BCM2835 has several banks for a single gpiochip, and each bank has a separate IRQ line. Instead of creating one gpiochip per bank, a single gpiochip covers all banks GPIO lines. This makes it necessary to resolve the bank ID in the IRQ handler. The GPIOLIB_IRQCHIP allows several IRQs to be cascaded off the same gpiochip by calling gpiochip_set_chained_irqchip() repeatedly, but we have been a bit short on examples for how this should be handled in practice, so this is intended as an example of how this can be achieved. The old code did not model the chip as a chained interrupt handler, but this patch also rectifies that situation. Cc: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Tested-by: Eric Anholt <eric@anholt.net> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-07pinctrl: New driver for TI DA850/OMAP-L138/AM18XX pinconfDavid Lechner3-0/+220
This adds a new driver for pinconf on TI DA850/OMAP-L138/AM18XX. These SoCs have a separate controller for controlling pullup/pulldown groups. Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-07pinctrl: intel: set default handler to be handle_bad_irq()Andy Shevchenko2-2/+2
We switch the default handler to be handle_bad_irq() instead of handle_simple_irq() (which was not correct anyway). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-30Merge tag 'arm-soc/for-4.10/devicetree' of ↵Arnd Bergmann1-6/+0
http://github.com/Broadcom/stblinux into next/dt Pull "Broadcom devicetree changes for 4.10" from Florian Fainelli: This pull request contains Broadcom ARM-based SoC Device Tree changes for 4.10, please pull the following: - Rafal adds support for the Netgear R8500 routers, adds basic support for the Tenda AC9 router which uses the new BCM53573 SoC (single core Cortex A7). He also enables the UART on the Netgear R8000 and restructures the include files a bit for the BCM47094 SoC, finally he adds USB 3.0 PHY nodes which enables USB 3.0 on BCM5301X devices that support it. Finally he adds support for the TP-LINK Archer C9 V1 router. - Kamal adds support for the QSPI controller on the Northstar Plus SoCs and updates the bcm958625k reference board to have it enabled - Dan adds support for the Luxul XAP-1510 (using a BCM4708) and XWR-3100 (using a BCM47094) - Scott fixes the pinctrl names in the Cygnus DTS files - Jonathan enables the Broadcom iProc mailbox controller for Broadcom Cygnus/iProc SoCs, he adds interrupt support for the GPIO CRMU hardware block and finally adds the node for the OTP controller found on Cygnus SoCs - Dhananjay enables the GPIO B controller on Norstarh Plus SoCs - Eric defines standard pinctrl groups in the BCM2835 GPIO node - Gerd adds definitions for the pinctrl groups and updates the PWM, I2C and SDHCI nodes to use their appropriate pinctrl functions - Linus adds names for the Raspberry Pi GPIO lines based on the datasheet - Martin adds the DT binding and nodes for the Raspberry Pi firmware thermal block - Stefan fixes a few typos with respect to the BCM2835 mailbox binding example and Device Tree nodes he also fixes the Raspberry Pi GPIO lines names and finally adds names for the Raspberry Zero GPIO lines * tag 'arm-soc/for-4.10/devicetree' of http://github.com/Broadcom/stblinux: (29 commits) ARM: bcm2835: Add names for the RPi Zero GPIO lines ARM: bcm2835: Fix names for the Raspberry Pi GPIO lines ARM: dts: enable GPIO-b for Broadcom NSP ARM: BCM5301X: Add DT for TP-LINK Archer C9 V1 ARM: dts: Add node for Broadcom OTP controller driver ARM: dts: Enable interrupt support for cygnus crmu gpio driver ARM: dts: Enable Broadcom iProc mailbox controller ARM: bcm2835: Add names for the Raspberry Pi GPIO lines ARM: bcm2835: dts: add thermal node to device-tree of bcm283x dt: bindings: add thermal device driver for bcm2835 ARM: dts: bcm283x: fix typo in mailbox address DT: binding: bcm2835-mbox: fix address typo in example ARM: dts: cygnus: fix naming of pinctrl node ARM: BCM53573: Specify PMU and its ILP clock in the DT ARM: BCM5301X: Add DT for Luxul XWR-3100 ARM: BCM5301X: Add DT for Luxul XAP-1510 ARM: BCM5301X: Specify USB 3.0 PHY in DT ARM: BCM5301X: Enable UART on Netgear R8000 ARM: BCM5301X: Add separated DTS include file for BCM47094 ARM: dts: NSP: Add QSPI nodes to NSPI and bcm958625k DTSes ...
2016-11-25pinctrl: sx150x: add support for sx1501, sx1504, sx1505 and sx1507Peter Rosin1-0/+98
Untested, register offsets carefully copied from datasheets. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-25pinctrl: sx150x: sort chips by part numberPeter Rosin1-71/+71
Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-25pinctrl: sx150x: use correct registers for reg_sense (sx1502 and sx1508)Peter Rosin1-2/+2
All other registers on these chips are 8-bit, but reg_sense is 16-bits and therefore needs to be moved down one notch. This was apparently overlooked in the conversion to regmap, which only updated the register locations for the 16-bit chips. Fixes: 6489677f86c3 ("pinctrl-sx150x: Replace sx150x_*_cfg by means of regmap API") Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-25pinctrl: imx: fix imx_pinctrl_desc initializationGary Bisson1-4/+4
Fixes: 6e408ed8be0e ("pinctrl: imx: fix initialization of imx_pinctrl_desc") Reviewed-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-24pinctrl: sx150x: support setting multiple pins at oncePeter Rosin1-0/+17
If the chip does not have an oscio pin, all pins are configured in the same regmap register making it trivial to update all pins at once, so do that. If an oscio pin is present, there needs to be more locking in place to handle all cases correctly, so this is skipped. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-23pinctrl: sx150x: various spelling fixes and some white-space cleanupPeter Rosin1-7/+6
Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-22pinctrl: mediatek: use builtin_platform_driverGeliang Tang1-5/+1
Use builtin_platform_driver() helper to simplify the code. Signed-off-by: Geliang Tang <geliangtang@gmail.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-22pinctrl: stm32: use builtin_platform_driverGeliang Tang1-5/+1
Use builtin_platform_driver() helper to simplify the code. Signed-off-by: Geliang Tang <geliangtang@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-22pinctrl: sunxi: Testing the wrong variableDan Carpenter1-2/+3
Smatch complains that we dereference "map" before testing it for NULL which is true. We should be testing "*map" instead. Also on the error path, we should free *map and set it to NULL. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-18pinctrl: nomadik: split up and comments MC0 pinsLinus Walleij1-6/+17
When debugging it helps to see exactly which pin goes where, so make it very detailed. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-16pinctrl: single: Fix a couple error codesDan Carpenter1-2/+6
We should return -ENOMEM instead of success if pcs_add_function() fails. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-16pinctrl: sunxi: fix theoretical uninitialized variable accessArnd Bergmann1-2/+5
gcc warns about a way that it could use an uninitialized variable: drivers/pinctrl/sunxi/pinctrl-sunxi.c: In function 'sunxi_pinctrl_init': drivers/pinctrl/sunxi/pinctrl-sunxi.c:1191:8: error: 'best_div' may be used uninitialized in this function [-Werror=maybe-uninitialized] This cannot really happen except if 'freq' is UINT_MAX and 'clock' is zero, and both of these are forbidden. To shut up the warning anyway, this changes the logic to initialize the return code to the first divider value before looking at the others. Fixes: 7c926492d38a ("pinctrl: sunxi: Add support for interrupt debouncing") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-16Merge tag 'sh-pfc-for-v4.10-tag2' of ↵Linus Walleij7-366/+816
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.10 (take two) - DU and EtherAVB pin groups for R-Car M3-W, - Bias handling cleanups and bug fixes, - Drive-strength for non-GPIO pins for R-Car H3, - EtherAVB MDIO & MII, and QSPI pin groups for R-Car H3.
generated by cgit v1.2.3 (git 2.39.0) at 2025-02-18 20:50:51 +0300