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path: root/drivers/pinctrl/Makefile
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2015-03-18pinctrl: add AMD GPIO driver support.Ken Xue1-0/+1
KERNCZ GPIO is a new IP from AMD. it can be implemented in both x86 and ARM. Current driver patch only support GPIO in x86. Signed-off-by: Ken Xue <Ken.Xue@amd.com> [Moved back to <linux/gpio.h> header] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: mediatek: Add Pinctrl/GPIO driver for mt8135.Hongzhou Yang1-0/+1
The mediatek SoCs have GPIO controller that handle both the muxing and GPIOs. The GPIO controller have pinmux, pull enable, pull select, direction and output high/low control. This driver include common driver and mt8135 part. The common driver include the pinctrl driver and GPIO driver. The mt8135 part contain its special device data. Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: bcm: consolidate Broadcom pinctrl driversRay Jui1-2/+1
Consolidate Broadcom pinctrl drivers into drivers/pinctrl/bcm/* Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09pinctrl: tegra: add a driver for Tegra210Stephen Warren1-0/+1
Tegra210's pinmux supports a different set of pins/options than earlier SoCs, so requires its own driver (well, table of pin-specific data). Cc: devicetree@vger.kernel.org Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-26pinctrl: add driver for Amlogic Meson SoCsBeniamino Galvani1-0/+1
This is a driver for the pinmux and GPIO controller available in Amlogic Meson SoCs. It currently supports only Meson8, however the common code should be generic enough to work also for other SoCs after having defined the proper set of functions and groups. GPIO interrupts are not supported at the moment due to lack of documentation. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-12pinctrl: Add driver for ZynqSoren Brinkmann1-0/+1
This adds a pin-control driver for Zynq. Changes since v2: - driver-specific DT properties are passed to the core in two arrays, one for the actual DT parsing one for the debugfs representation. Issue a compiler warning when the number of entries is not the same for both arrays. Changes since v1: - fix EMIO_SD1_CD pin name - add USB to pinmux options changes since RFCv2: - let Zynq select PINCTRL_ZYNQ. Boot hangs when pinctrl information is present in DT but no driver available. - add #defines to get rid of magical constants - add commas at end of initializers - separate changes in mach-zynq in separate patch - add driver specific io-standard DT property - refactored pinconf set function to not require arguments for argument-less properties - squash other patches in - support for IO-standard property - support for low-power mode property - migration to pinconf_generic_dt_node_to_map_all() - use newly created infrastructure to add pass driver-specific DT params to pinconf-generic changes since RFC: - use syscon/regmap to access registers in SLCR space - rebase to 3.18: rename enable -> set_mux - add kernel-doc - support pinconf - supported attributes - pin-bias: pull up, tristate, disable - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display argument Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Tested-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-11pinctrl: pass -DDEBUG in subdirsLinus Walleij1-1/+1
When drivers are compiled in subdirectories the -DDEBUG flag need to be passed in the individual Makefiles. Reported-by: Mika Westerberg <mika.westerberg@linux.intel.com> Suggested-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-29pinctrl: Move Intel Baytrail pinctrl driver under intel directoryMika Westerberg1-1/+1
We are going to have more pinctrl drivers for Intel hardware so separate all our pin controller drivers to own directory. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-09-04pinctrl: imx/mxs: move freescale drivers to subdirLinus Walleij1-18/+1
This moves all the Freescale-related drivers (i.MX and MXS) to its own subdirectory to clear the view. Cc: Alexander Shiyan <shc_work@mail.ru> Cc: Anson Huang <b20788@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Denis Carikli <denis@eukrea.com> Cc: Markus Pargmann <mpa@pengutronix.de> Cc: Greg Ungerer <gerg@uclinux.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-09-02pinctrl: sh-pfc: use a saner Kconfig symbolLinus Walleij1-2/+1
There is currently a kludge to get the Makefile to move down to sh-pfc:s drivers: the arch definitions are used twice to get it done. However we can very well use the Kconfig symbol for the SH PFC pin control feature itself: it doesn't matter that it comes from a lower leaf in the Kconfig hierarchy which is completely orthogonal. Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-08-29pinctrl: samsung: use CONFIG_PINCTRL_SAMSUNG symbol in makefileNaveen Krishna Chatradhi1-1/+1
Samsung Exynos7 is a ARM64bit processor. Which does not select the CONFIG_PLAT_SAMSUNG symbol. CONFIG_PINCTRL_SAMSUNG is being selected for both PLAT_SAMSUNG and ARCH_EXYNOS7 symbols. This patch modifes the pinctrl/Makefile to use CONFIG_PINCTRL_SAMSUNG symbol to compile the pinctrl/samsung/*.c Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Cc: Tomasz Figa <t.figa@samsung.com> Cc: linus.walleij@linaro.org Cc: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-08-28pinctrl: Add i.MX21 pincontrol driverAlexander Shiyan1-0/+1
This patch adds pincontrol driver for Freescale i.MX21 SOCs. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-08-08Merge tag 'dt-for-3.17' of ↵Linus Torvalds1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC device-tree changes from Olof Johansson: "Unlike the board branch, this keeps having large sets of changes for every release, but that's quite expected and is so far working well. Most of this is plumbing for various device bindings and new platforms, but there's also a bit of cleanup and code removal for things that are moved from platform code to DT contents (some OMAP clock code in particular). There's also a pinctrl driver for tegra here (appropriately acked), that's introduced this way to make it more bisectable. I'm happy to say that there were no conflicts at all with this branch this release, which means that changes are flowing through our tree as expected instead of merged through driver maintainers (or at least not done with conflicts). There are several new boards added, and a couple of SoCs. In no particular order: - Rockchip RK3288 SoC support, including DTS for a dev board that they have seeded with some community developers. - Better support for Hardkernel Exynos4-based ODROID boards. - CCF conversions (and dtsi contents) for several Renesas platforms. - Gumstix Pepper (TI AM335x) board support - TI eval board support for AM437x - Allwinner A23 SoC, very similar to existing ones which mostly has resulted in DT changes for support. Also includes support for an Ippo tablet with the chipset. - Allwinner A31 Hummingbird board support, not to be confused with the SolidRun i.MX-based Hummingboard. - Tegra30 Apalis board support" * tag 'dt-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (334 commits) ARM: dts: Enable USB host0 (EHCI) on rk3288-evb ARM: dts: add rk3288 ehci usb devices ARM: dts: Turn on USB host vbus on rk3288-evb ARM: tegra: apalis t30: fix device tree compatible node ARM: tegra: paz00: Fix some indentation inconsistencies ARM: zynq: DT: Clarify Xilinx Zynq platform ARM: dts: rockchip: add watchdog node ARM: dts: rockchip: remove pinctrl setting from radxarock uart2 ARM: dts: Add missing pinctrl for uart0/1 for exynos3250 ARM: dts: Remove duplicate 'interrput-parent' property for exynos3250 ARM: dts: Add TMU dt node to monitor the temperature for exynos3250 ARM: dts: Specify MAX77686 pmic interrupt for exynos5250-smdk5250 ARM: dts: cypress,cyapa trackpad is exynos5250-Snow only ARM: dts: max77686 is exynos5250-snow only ARM: zynq: DT: Remove DMA from board DTs ARM: zynq: DT: Add CAN node ARM: EXYNOS: Add exynos5260 PMU compatible string to DT match table ARM: dts: Add PMU DT node for exynos5260 SoC ARM: EXYNOS: Add support for Exynos5410 PMU ARM: dts: Add PMU to exynos5410 ...
2014-07-11pinctrl: nomadik: move all Nomadik drivers to subdirLinus Walleij1-9/+1
We have a bunch of Nomadik family pin control drivers, so let's move them into their own subdirectory. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11pinctrl: Add NVIDIA Tegra XUSB pad controller supportThierry Reding1-0/+1
The XUSB pad controller found on NVIDIA Tegra SoCs provides several pads that lanes can be assigned to in order to support a variety of interface options: USB 2.0, USB 3.0, PCIe and SATA. In addition to the pin controller used to assign lanes to pads two PHYs are exposed to allow the bricks for PCIe and SATA to be powered up and down by PCIe and SATA drivers. Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-11pinctrl: samsung: Group all drivers in a sub-dirSachin Kamat1-6/+2
Group all pin control drivers of Samsung platform together in a sub-directory for easy maintenance. Signed-off-by: Sachin Kamat <sachin.kamat@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11pinctrl: msm: move all qualcomm drivers to subdirLinus Walleij1-5/+1
We have four Qualcomm-related pin control drivers, and now there are drivers coming in for the PMICs on these systems, so let's create a qcom subdirectory to hold all the Qualcomm stuff. Acked-by: Ivan T. Ivanov <iivanov@mm-sol.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11pinctrl: msm: Add msm8960 definitionsBjorn Andersson1-0/+1
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11pinctrl: Add i.MX1 pincontrol driverAlexander Shiyan1-0/+1
This patch adds pincontrol driver for Freescale i.MX1 SOCs. Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-27pinctrl: add pinctrl driver for imx6sxAnson Huang1-0/+1
Add a pinctrl driver for i.MX6 SoloX based on pinctrl-imx core driver. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCsAntoine Tenart1-0/+1
The Marvell Berlin boards have a group based pinmuxing mechanism. This adds the core driver support. We actually do not need any information about the pins here and only have the definition of the groups. Let's take the example of the uart0 pinmuxing on the BG2Q. Balls BK4 and BH6 are muxed to respectively UART0 RX and TX if the group GSM12 is set to mode 0: Group Modes Offset Base Offset LSB Bit Width GSM12 3 sm_base 0x40 0x10 0x2 Ball Group Mode 0 Mode 1 Mode 2 BK4 GSM12 UART0_RX IrDA0_RX GPIO9 BH6 GSM12 UART0_TX IrDA0_TX GPIO10 So in order to configure BK4 -> UART0_TX and BH6 -> UART0_RX, we need to set (sm_base + 0x40 + 0x10) &= ff3fffff. As pin control registers are part of either chip control or system control registers, that deal with a bunch of other functions we rely on a regmap instead of exclusively remapping any resources. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-04pinctrl: sunxi: Move the Allwinner pinctrl driver to its own directoryMaxime Ripard1-1/+1
This will allow to create numerous files without crippling the main pinctrl directory. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-04-23pinctrl: qcom: Add definitions for IPQ8064Andy Gross1-0/+1
This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the Qualcomm IPQ8064 platform. Signed-off-by: Andy Gross <agross@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: msm: Add definitions for the APQ8064 platformBjorn Andersson1-0/+1
This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the Qualcomm APQ8064 platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-14pinctrl: Rename Broadcom Capri pinctrl driverSherman Yin1-1/+1
To be consistent with other Broadcom drivers, the Broadcom Capri pinctrl driver and its related CONFIG option are renamed to bcm281xx. Devicetree compatible string and binding documentation use "brcm,bcm11351-pinctrl" to match the machine binding here: Documentation/devicetree/bindings/arm/bcm/bcm11351.txt This driver supports pinctrl on BCM11130, BCM11140, BCM11351, BCM28145 and BCM28155 SoCs. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Matt Porter <mporter@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-16ARM: pinctrl: Add Broadcom Capri pinctrl driverSherman Yin1-0/+1
Adds pinctrl driver for Broadcom Capri (BCM281xx) SoCs. v4: - PINCTRL selected in Kconfig, PINCTRL_CAPRI selected in bcm_defconfig - make use of regmap - change CAPRI_PIN_UPDATE from macro to inline function. - Handle pull-up strength arg in Ohm instead of enum v3: Re-work driver to be based on generic pin config. Moved config selection from Kconfig to bcm_defconfig. v2: Use hyphens instead of underscore in DT property names. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Christian Daudt <bcm@fixthebug.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-13pinctrl: tegra: add pinmux controller driver for Tegra124Ashwini Ghuge1-0/+1
This adds a driver for the Tegra124 pinmux, and required parameterization data for Tegra124. The driver uses the common Tegra pincontrol driver utility functions to implement the majority of the driver. This driver is not compatible with the earlier NVIDIA's SoCs, hence add new compatibile as "nvidia,tegra124-pinmux". Originally written by Ashwini Gguhe. Thierry: - Cleanups in patches. ldewangan: - Fix some entries for groups. - Fix MUX enums and group sequence. Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> CC: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-06pinctrl: Add msm8x74 configurationBjorn Andersson1-0/+1
Add initial definition of parameters for pinctrl-msm for the msm8x74 platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-06pinctrl: Add Qualcomm TLMM driverBjorn Andersson1-0/+1
This adds a pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-25pinctrl: pinctrl-imx: add imx25 pinctrl driverDenis Carikli1-0/+1
This is mostly cut and paste from the imx35 pinctrl driver. The data was generated using sed and awk on arch/arm/plat-mxc/include/mach/iomux-mx25.h. Cc: Rob Herring <rob.herring@calxeda.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: devicetree@vger.kernel.org Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: linux-arm-kernel@lists.infradead.org Cc: Russell King <linux@arm.linux.org.uk> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Eric Bénard <eric@eukrea.com> Signed-off-by: Denis Carikli <denis@eukrea.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-06pinctrl: imx50: add pinctrl support code for the IMX50 SoCGreg Ungerer1-0/+1
Add code to support the specific pin arrangements of the Freescale IMX50 SoC. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-29pinctrl: imx27: imx27 pincontrol driverMarkus Pargmann1-0/+1
imx27 pincontrol driver using the imx1 core driver. The DT bindings are similar to other imx pincontrol drivers. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-29pinctrl: imx1 core driverMarkus Pargmann1-0/+1
Core driver for register formats of imx1/imx21/imx27 processors. The pins of those processors are grouped into ports. Each port has 32 pins. The pins mux configuration is controlled by registers with 1 or 2 bit per pin, depending on the specific control register. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-16pinctrl: add TB10x pin control driverChristian Ruppert1-0/+1
The pinmux driver of the Abilis Systems TB10x platform based on ARC700 CPUs. Used to control the pinmux and is a prerequisite for the GPIO driver. Signed-off-by: Christian Ruppert <christian.ruppert@abilis.com> Signed-off-by: Pierrick Hascoet <pierrick.hascoet@abilis.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-10pincntrl: add support for ams AS3722 pin control driverLaxman Dewangan1-0/+1
The AS3722 is a compact system PMU suitable for mobile phones, tablets etc. Add a driver to support accessing the GPIO, pinmux and pin configuration of 8 GPIO pins found on the ams AS3722 through pin control driver and gpiolib. The driver will register itself as the pincontrol driver and gpio driver. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-19pinctrl: ADI PIN control driver for the GPIO controller on bf54x and bf60x.Sonic Zhang1-0/+3
The new ADI GPIO2 controller was introduced since the BF548 and BF60x processors. It differs a lot from the old one on BF5xx processors. So, create a pinctrl driver under the pinctrl framework. - Define gpio ports and pin interrupt controllers as individual platform devices. - Register a pinctrl driver for the whole GPIO ports and pin interrupt devices. - Probe pint devices before port devices. Put device instances into the global gpio and pint lists. - Define peripheral, irq and gpio reservation bit masks for each gpio port as runtime resources. - Save and restore gpio port and pint status MMRs in syscore PM functions. - Create the plug-in subdrivers to hold the pinctrl soc data for bf54x and bf60x. Add soc data into struct adi_pinctrl. Initialize the soc data in pin controller probe function. Get the pin groups and functions via the soc data reference. - Call gpiochip_add_pin_range() in gpio device probe function to register range cross reference between gpio device and pin control device. - Get range by pinctrl_find_gpio_range_from_pin(), find gpio_port object by container_of() and find adi_pinctrl by pin control device name. - Handle peripheral and gpio requests in pinctrl operation functions. - Demux gpio IRQs via the irq_domain created by each GPIO port. v2-changes: - Remove unlinke() directive. v3-changes: - Rename struct adi_pmx to adi_pinctrl. - Fix the comments of struct gpio_pint. - Remove unused pin_base in struct gpio_port. - Change pint_assign into bool type. - Add comments about the relationship between pint device and port device to the driver header. - Use BIT macro to shift bit. - Remove all bitmap reservation help functions. Inline reservation functions into the actual code. - Remove gpio and offset mutual reference help functions. - Remove all help functions to find gpio_port and adi_pinctrl structs. Get range by pinctrl_find_gpio_range_from_pin(), find gpio_port object by container_of() and find adi_pinctrl by pin control device name. - Pass bool type usage variable to port_setup help function. - Separate long bit operations into several lines and add comments. - Use debugfs to output all GPIO request information. - Avoid to set drvdata to NULL - Add explanation to function adi_gpio_init_int() - Call gpiochip_add_pin_range() in gpio device probe function to register range cross reference between gpio device and pin control device. - Remove the reference to pin control device from the gpio_port struct. Remove the reference list to gpio device from the adi_pinctrl struct. Replace the global adi_pinctrl list with adi_gpio_port_list. Walk through the gpio list to do power suspend and resume operations. - Remove the global GPIO base from struct adi_pinctrl, define pin base in the platform data for each GPIO port device. - Initialize adi_pinctrl_setup in arch_initcall(). - print the status of triggers, whether it is in GPIO mode, if it is flagged to be used as IRQ, etc in adi_pin_dbg_show(). - Create the plug-in subdrivers to hold the pinctrl soc data for bf54x and bf60x. Add soc data into struct adi_pinctrl. Initialize the soc data in pin controller probe function. Get the pin groups and functions via the soc data reference. v4-changes: - remove useless system_state checking. - replace dev_err with dev_warn in both irq and gpio pin cases. - comment on relationship between irq type and invert operation. - It is not necessary to check the reservation mode of the requested pin in IRQ chip operation. Remove the reservation map. - Use existing gpio/pinctrl subsystem debugfs files. Remove pinctrl-adi2 driver specific debugfs output. - Add linkport group and function information for bf60x. - Separate uart and ctsrts pins into 2 groups. - Separate APAPI and alternative ATAPI pins into 2 groups. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-14pinctrl: palmas: add pincontrol driverLaxman Dewangan1-0/+1
TI Palmas series Power Management IC have multiple pins which can be configured for different functionality. This pins can be configured for different function. Also their properties like pull up/down, open drain enable/disable are configurable. Add support for pincontrol driver Palmas series device like TPS65913, TPS80036. The driver supports to be register from DT only. Changes from V1: - Add generic property for pins and functions in pinconf-generic. - Add APIs to map the DT and subnode. - Move common utils APIs to the pinctrl-utils from this file. - Update the binding document accordingly. Changes from V2: - Add ack by Lee. - Correct the binding docs. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-14pinctrl: add utility functions for add map/configsLaxman Dewangan1-1/+1
Some of pincontrol driver needs the utility function to create map list. The utility function needed for adding mux, configs etc. In place of duplicating this in each driver, add the common utility function in common file and use from device specific driver. This will reduce the duplicating of code across drivers. Changes from V1: - Add this files in this patch and add common utility APIs to here. Changes from V2: - Nothing in code. - Added Reviewed by Stephen. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-07-03Merge tag 'pinctrl-for-v3.11-1' of ↵Linus Torvalds1-1/+7
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control changes from Linus Walleij: - A large slew of improvements of the Genric pin configuration support, and deployment in four different platforms: Rockchip, Super-H PFC, ABx500 and TZ1090. Support BIAS_BUS_HOLD, get device tree parsing and debugfs support into shape. - We also have device tree support with generic naming conventions for the generic pin configuration. - Delete the unused and confusing direct pinconf API. Now state transitions is *the* way to control pins and multiplexing. - New drivers for Rockchip, TZ1090, and TZ1090 PDC. - Two pin control states related to power management are now handled in the device core: "sleep" and "idle", removing a lot of boilerplate code in drivers. We do not yet know if this is the final word for pin PM, but it already make things a lot easier to handle. - Handle sparse GPIO ranges passing a list of disparate pins, and utilize these in the new BayTrail (x86 Atom SoC) driver. - Make the sunxi (AllWinner) driver handle external interrupts. - Make it possible for pinctrl-single to handle the case where several pins are managed by a single register, and augment it to handle sleep modes. - Cleanups and improvements for the abx500 drivers. - Move Sirf pin control drivers to their own directory, support save/restore of context and add support for the SiRFatlas6 SoC. - PMU muxing for the Dove pinctrl driver. - Finalization and support for VF610 in the i.MX6 pinctrl driver. - Smoothen out various Exynos rough edges. - Generic cleanups of various kinds. * tag 'pinctrl-for-v3.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (82 commits) pinctrl: vt8500: wmt: remove redundant dev_err call in wmt_pinctrl_probe() pinctrl: remove bindings for pinconf options needing more thought pinctrl: remove slew-rate parameter from tz1090 pinctrl: set unit for debounce time pinconfig to usec pinctrl: more clarifications for generic pull configs pinctrl: rip out the direct pinconf API pinctrl-tz1090-pdc: add TZ1090 PDC pinctrl driver pinctrl-tz1090: add TZ1090 pinctrl driver pinctrl: samsung: Staticize drvdata_list pinctrl: rockchip: Add missing irq_gc_unlock() call before return error pinctrl: abx500: rework error path pinctrl: abx500: suppress hardcoded value pinctrl: abx500: factorize code pinctrl: abx500: fix abx500_gpio_get() pinctrl: abx500: fix abx500_pin_config_set() pinctrl: abx500: Add device tree support sh-pfc: Guard DT parsing with #ifdef CONFIG_OF pinctrl: add Intel BayTrail GPIO/pinctrl support pinctrl: fix pinconf_ops::pin_config_dbg_parse_modify kerneldoc pinctrl: Staticize local symbols ... Conflicts: drivers/net/ethernet/ti/davinci_mdio.c drivers/pinctrl/Makefile
2013-07-03Merge tag 'regmap-v3.11' of ↵Linus Torvalds1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap Pull regmap updates from Mark Brown: "A small but useful set of regmap updates this time around: - An abstraction for bitfields within a register map contributed by Srinivas Kandagatla, allowing drivers to cope more easily when hardware designers randomly move things about (mainly when talking to things like system controllers). - Changes from Lars-Peter Clausen to allow the MMIO regmap to be used from hard IRQ context. - Small improvements to the cache infrastructure and performance, including a default cache sync operation so now all regmaps can sync easily. There's also a pinctrl driver making use of the new bitfield API, merged here for dependency reasons. There will be a simple add/add conflict with the pinctrl tree as a result." * tag 'regmap-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap: pinctrl: st: Remove unnecessary use of of_match_ptr macro pinctrl: st: fix return value check pinctrl: st: Add pinctrl and pinconf support. regmap: debugfs: Suppress cache for partial register files regmap: Add regmap_field APIs regmap: core: Cache all registers by default when cache is enabled regmap: Implemented default cache sync operation regmap: Make regmap-mmio usable from atomic contexts regmap: regcache: Fixup locking for custom lock callbacks regmap: debugfs: Fix return from regmap_debugfs_get_dump_start regmap: debugfs: Don't mark lockdep as broken due to debugfs write regmap: rbtree: Use range information to allocate nodes regmap: rbtree: Factor out node allocation regmap: Make regmap_check_range_table() a public API regmap: Add support for discarding parts of the register cache
2013-06-25pinctrl: st: Add pinctrl and pinconf support.Srinivas KANDAGATLA1-0/+1
This patch add pinctrl support to ST SoCs. About hardware: ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle pin configurations. Each multi-function pin is controlled, driven and routed through the PIO multiplexing block. Each pin supports GPIO functionality (ALT0) and multiple alternate functions(ALT1 - ALTx) that directly connect the pin to different hardware blocks. When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and Pull Up (PU) are driven by the related PIO block. Otherwise the PIO multiplexing block configures these parameters and retiming the signal. About driver: This pinctrl driver manages both PIO and PIO-mux block using pinctrl, pinconf, pinmux, gpio subsystems. All the pinctrl related config information can only come from device trees. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@linaro.org>
2013-06-24pinctrl-tz1090-pdc: add TZ1090 PDC pinctrl driverJames Hogan1-0/+1
Add a pin control driver for the TZ1090's low power pins via the powerdown controller SOC_GPIO_CONTROL registers. These pins have individually controlled pull-up, and group controlled schmitt, slew-rate, drive-strength, and power-on-start (pos). The pdc_gpio0 and pdc_gpio1 pins can also be muxed onto the ir_mod_stable_out and ir_mod_power_out functions respectively. If no function is set they remain in GPIO mode. These muxes can be overridden by requesting them as GPIOs. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Rob Landley <rob@landley.net> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-doc@vger.kernel.org Cc: devicetree-discuss@lists.ozlabs.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-24pinctrl-tz1090: add TZ1090 pinctrl driverJames Hogan1-0/+1
Add a pin control driver for the main pins on the TZ1090 SoC. This doesn't include the low-power pins as they're controlled separately via the Powerdown Controller (PDC) registers. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Rob Landley <rob@landley.net> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-doc@vger.kernel.org Cc: devicetree-discuss@lists.ozlabs.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-18pinctrl: add Intel BayTrail GPIO/pinctrl supportMathias Nyman1-0/+1
Add support for gpio on Intel BayTrail platforms. BayTrail supports 3 banks of gpios called SCORE, NCORE ans SUS with 102, 28 and 44 gpio pins. Supports gpio interrupts and ACPI gpio events Pins may be muxed to alternate function instead of gpio by firmware. This driver does not touch the pin muxing and expect firmare to set pin muxing and pullup/down properties properly. Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-16pinctrl: add pinctrl driver for Rockchip SoCsHeiko Stübner1-0/+1
This driver adds support the Cortex-A9 based SoCs from Rockchip, so at least the RK2928, RK3066 (a and b) and RK3188. Earlier Rockchip SoCs seem to use similar mechanics for gpio handling so should be supportable with relative small changes. Pull handling on the rk3188 is currently a stub, due to it being a bit different to the earlier SoCs. Pinmuxing as well as gpio (and interrupt-) handling tested on a rk3066a based machine. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-16pinctrl: add VF610 pinctrl driverJingchang Lu1-0/+1
Adds Freescale Vybrid VF610 pin controller driver to IMX common pinctrl driver framework. Signed-off-by: Jingchang Lu <b35083@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-16pinctrl:sirf:re-arch and add support for new SiRFatlas6 SoCBarry Song1-1/+1
atlas6 is a SoC very similar with primaII, the register layput of pinctrl is same, but the pads, groups and functions of atlas6 have different layout with prima2, this patch 1. pull the definition of pads, groups and functions out of the pinctrl-sirf driver,and put them into soc-specific files 2. add pads, groups and functions tables for atlas6 3. let pads, groups and functions tables become the config data of the related dt compatible node, so the pinctrl-sirf can support all SiRF SoCs with the config data as private data. In this patch,we create a sirf dir, and let the old drivers/pinctrl/pinctrl-sirf.c = drivers/pinctrl/sirf/pinctrl-prima2.c + drivers/pinctrl/sirf/pinctrl-sirf.c drivers/pinctrl/sirf/pinctrl-atlas6.c is a newly created file for the pin layout of atlas6. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-16pinctrl: enable build of pinctrl-imx6sl driverShawn Guo1-0/+1
The pinctrl-imx6sl is in place. Enable the build of it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-05-20pinctrl: Add pinctrl-s3c24xx driverHeiko Stuebner1-0/+1
The s3c24xx pins follow a similar pattern as the other Samsung SoCs and can therefore reuse the already introduced infrastructure. The s3c24xx SoCs have one design oddity in that the first 4 external interrupts do not reside in the eint pending register but in the main interrupt controller instead. We solve this by forwarding the external interrupt from the main controller into the irq domain of the pin bank. The masking/acking of these interrupts is handled in the same way. Furthermore the S3C2412/2413 SoCs contain another oddity in that they keep the same 4 eints in the main interrupt controller and eintpend register and requiring ack operations to happen in both. This is solved by using different compatible properties for the wakeup eint node which set a property accordingly. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-05-04Merge tag 'drivers-for-linus' of ↵Linus Torvalds1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver changes from Olof Johansson: "This is a rather large set of patches for device drivers that for one reason or another the subsystem maintainer preferred to get merged through the arm-soc tree. There are both new drivers as well as existing drivers that are getting converted from platform-specific code into standalone drivers using the appropriate subsystem specific interfaces. In particular, we can now have pinctrl, clk, clksource and irqchip drivers in one file per driver, without the need to call into platform specific interface, or to get called from platform specific code, as long as all information about the hardware is provided through a device tree. Most of the drivers we touch this time are for clocksource. Since now most of them are part of drivers/clocksource, I expect that we won't have to touch these again from arm-soc and can let the clocksource maintainers take care of these in the future. Another larger part of this series is specific to the exynos platform, which is seeing some significant effort in upstreaming and modernization of its device drivers this time around, which unfortunately is also the cause for the churn and a lot of the merge conflicts. There is one new subsystem that gets merged as part of this series: the reset controller interface, which is a very simple interface for taking devices on the SoC out of reset or back into reset. Patches to use this interface on i.MX follow later in this merge window, and we are going to have other platforms (at least tegra and sirf) get converted in 3.11. This will let us get rid of platform specific callbacks in a number of platform independent device drivers." * tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (256 commits) irqchip: s3c24xx: add missing __init annotations ARM: dts: Disable the RTC by default on exynos5 clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3} ARM: exynos: restore mach/regs-clock.h for exynos5 clocksource: exynos_mct: fix build error on non-DT pinctrl: vt8500: wmt: Fix checking return value of pinctrl_register() irqchip: vt8500: Convert arch-vt8500 to new irqchip infrastructure reset: NULL deref on allocation failure reset: Add reset controller API dt: describe base reset signal binding ARM: EXYNOS: Add arm-pmu DT binding for exynos421x ARM: EXYNOS: Add arm-pmu DT binding for exynos5250 ARM: EXYNOS: Enable PMUs for exynos4 irqchip: exynos-combiner: Correct combined IRQs for exynos4 irqchip: exynos-combiner: Add set_irq_affinity function for combiner_irq ARM: EXYNOS: fix compilation error introduced due to common clock migration clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3} clk: exynos4: export clocks required for fimc-is clk: samsung: Fix compilation error clk: tegra: fix enum tegra114_clk to match binding ...
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-23 02:29:44 +0300