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2016-07-23PCI: altera: Poll for link up status after retraining the linkLey Foon Tan1-1/+11
Some PCIe devices take a long time to reach link up state after retrain. Poll for link up status after retraining the link. This is to make sure the link is up before we access configuration space. [bhelgaas: changelog] Signed-off-by: Ley Foon Tan <lftan@altera.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-07-22PCI: altera: Check link status before retrain linkLey Foon Tan1-0/+4
Check the link status before retraining. If the link is not up, don't bother trying to retrain it. [bhelgaas: split code move to separate patch, changelog] Signed-off-by: Ley Foon Tan <lftan@altera.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-07-22PCI: altera: Reorder read/write functionsBjorn Helgaas1-16/+16
Move cra_writel(), cra_readl(), and altera_pcie_link_is_up() so a future patch can use them in altera_pcie_retrain(). No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-05-21Merge tag 'char-misc-4.7-rc1' of ↵Linus Torvalds1-7/+7
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char / misc driver updates from Greg KH: "Here's the big char and misc driver update for 4.7-rc1. Lots of different tiny driver subsystems have updates here with new drivers and functionality. Details in the shortlog. All have been in linux-next with no reported issues for a while" * tag 'char-misc-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (125 commits) mcb: Delete num_cells variable which is not required mcb: Fixed bar number assignment for the gdd mcb: Replace ioremap and request_region with the devm version mcb: Implement bus->dev.release callback mcb: export bus information via sysfs mcb: Correctly initialize the bus's device mei: bus: call mei_cl_read_start under device lock coresight: etb10: adjust read pointer only when needed coresight: configuring ETF in FIFO mode when acting as link coresight: tmc: implementing TMC-ETF AUX space API coresight: moving struct cs_buffers to header file coresight: tmc: keep track of memory width coresight: tmc: make sysFS and Perf mode mutually exclusive coresight: tmc: dump system memory content only when needed coresight: tmc: adding mode of operation for link/sinks coresight: tmc: getting rid of multiple read access coresight: tmc: allocating memory when needed coresight: tmc: making prepare/unprepare functions generic coresight: tmc: splitting driver in ETB/ETF and ETR components coresight: tmc: cleaning up header file ...
2016-05-20Merge tag 'powerpc-4.7-1' of ↵Linus Torvalds3-8/+8
git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull powerpc updates from Michael Ellerman: "Highlights: - Support for Power ISA 3.0 (Power9) Radix Tree MMU from Aneesh Kumar K.V - Live patching support for ppc64le (also merged via livepatching.git) Various cleanups & minor fixes from: - Aaro Koskinen, Alexey Kardashevskiy, Andrew Donnellan, Aneesh Kumar K.V, Chris Smart, Daniel Axtens, Frederic Barrat, Gavin Shan, Ian Munsie, Lennart Sorensen, Madhavan Srinivasan, Mahesh Salgaonkar, Markus Elfring, Michael Ellerman, Oliver O'Halloran, Paul Gortmaker, Paul Mackerras, Rashmica Gupta, Russell Currey, Suraj Jitindar Singh, Thiago Jung Bauermann, Valentin Rothberg, Vipin K Parashar. General: - Update LMB associativity index during DLPAR add/remove from Nathan Fontenot - Fix branching to OOL handlers in relocatable kernel from Hari Bathini - Add support for userspace Power9 copy/paste from Chris Smart - Always use STRICT_MM_TYPECHECKS from Michael Ellerman - Add mask of possible MMU features from Michael Ellerman PCI: - Enable pass through of NVLink to guests from Alexey Kardashevskiy - Cleanups in preparation for powernv PCI hotplug from Gavin Shan - Don't report error in eeh_pe_reset_and_recover() from Gavin Shan - Restore initial state in eeh_pe_reset_and_recover() from Gavin Shan - Revert "powerpc/eeh: Fix crash in eeh_add_device_early() on Cell" from Guilherme G Piccoli - Remove the dependency on EEH struct in DDW mechanism from Guilherme G Piccoli selftests: - Test cp_abort during context switch from Chris Smart - Add several tests for transactional memory support from Rashmica Gupta perf: - Add support for sampling interrupt register state from Anju T - Add support for unwinding perf-stackdump from Chandan Kumar cxl: - Configure the PSL for two CAPI ports on POWER8NVL from Philippe Bergheaud - Allow initialization on timebase sync failures from Frederic Barrat - Increase timeout for detection of AFU mmio hang from Frederic Barrat - Handle num_of_processes larger than can fit in the SPA from Ian Munsie - Ensure PSL interrupt is configured for contexts with no AFU IRQs from Ian Munsie - Add kernel API to allow a context to operate with relocate disabled from Ian Munsie - Check periodically the coherent platform function's state from Christophe Lombard Freescale: - Updates from Scott: "Contains 86xx fixes, minor device tree fixes, an erratum workaround, and a kconfig dependency fix." * tag 'powerpc-4.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (192 commits) powerpc/86xx: Fix PCI interrupt map definition powerpc/86xx: Move pci1 definition to the include file powerpc/fsl: Fix build of the dtb embedded kernel images powerpc/fsl: Fix rcpm compatible string powerpc/fsl: Remove FSL_SOC dependency from FSL_LBC powerpc/fsl-pci: Add a workaround for PCI 5 errata powerpc/fsl: Fix SPI compatible on t208xrdb and t1040rdb powerpc/powernv/npu: Add PE to PHB's list powerpc/powernv: Fix insufficient memory allocation powerpc/iommu: Remove the dependency on EEH struct in DDW mechanism Revert "powerpc/eeh: Fix crash in eeh_add_device_early() on Cell" powerpc/eeh: Drop unnecessary label in eeh_pe_change_owner() powerpc/eeh: Ignore handlers in eeh_pe_reset_and_recover() powerpc/eeh: Restore initial state in eeh_pe_reset_and_recover() powerpc/eeh: Don't report error in eeh_pe_reset_and_recover() Revert "powerpc/powernv: Exclude root bus in pnv_pci_reset_secondary_bus()" powerpc/powernv/npu: Enable NVLink pass through powerpc/powernv/npu: Rework TCE Kill handling powerpc/powernv/npu: Add set/unset window helpers powerpc/powernv/ioda2: Export debug helper pe_level_printk() ...
2016-05-19Merge tag 'pci-v4.7-changes' of ↵Linus Torvalds33-424/+1496
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: "Enumeration: - Refine PCI support check in pcibios_init() (Adrian-Ken Rueegsegger) - Provide common functions for ECAM mapping (Jayachandran C) - Allow all PCIe services on non-ACPI host bridges (Jon Derrick) - Remove return values from pcie_port_platform_notify() and relatives (Jon Derrick) - Widen portdrv service type from 4 bits to 8 bits (Keith Busch) - Add Downstream Port Containment portdrv service type (Keith Busch) - Add Downstream Port Containment driver (Keith Busch) Resource management: - Identify Enhanced Allocation (EA) BAR Equivalent resources in sysfs (Alex Williamson) - Supply CPU physical address (not bus address) to iomem_is_exclusive() (Bjorn Helgaas) - alpha: Call iomem_is_exclusive() for IORESOURCE_MEM, but not IORESOURCE_IO (Bjorn Helgaas) - Mark Broadwell-EP Home Agent 1 as having non-compliant BARs (Prarit Bhargava) - Disable all BAR sizing for devices with non-compliant BARs (Prarit Bhargava) - Move PCI I/O space management from OF to PCI core code (Tomasz Nowicki) PCI device hotplug: - acpiphp_ibm: Avoid uninitialized variable reference (Dan Carpenter) - Use cached copy of PCI_EXP_SLTCAP_HPC bit (Lukas Wunner) Virtualization: - Mark Intel i40e NIC INTx masking as broken (Alex Williamson) - Reverse standard ACS vs device-specific ACS enabling (Alex Williamson) - Work around Intel Sunrise Point PCH incorrect ACS capability (Alex Williamson) IOMMU: - Add pci_add_dma_alias() to abstract implementation (Bjorn Helgaas) - Move informational printk to pci_add_dma_alias() (Bjorn Helgaas) - Add support for multiple DMA aliases (Jacek Lawrynowicz) - Add DMA alias quirk for mic_x200_dma (Jacek Lawrynowicz) Thunderbolt: - Fix double free of drom buffer (Andreas Noever) - Add Intel Thunderbolt device IDs (Lukas Wunner) - Fix typos and magic number (Lukas Wunner) - Support 1st gen Light Ridge controller (Lukas Wunner) Generic host bridge driver: - Use generic ECAM API (Jayachandran C) Cavium ThunderX host bridge driver: - Don't clobber read-only bits in bridge config registers (David Daney) - Use generic ECAM API (Jayachandran C) Freescale i.MX6 host bridge driver: - Use enum instead of bool for variant indicator (Andrey Smirnov) - Implement reset sequence for i.MX6+ (Andrey Smirnov) - Factor out ref clock enable (Bjorn Helgaas) - Add initial imx6sx support (Christoph Fritz) - Add reset-gpio-active-high boolean property to DT (Petr Štetiar) - Add DT property for link gen, default to Gen1 (Tim Harvey) - dts: Specify imx6qp version of PCIe core (Andrey Smirnov) - dts: Fix PCIe reset GPIO polarity on Toradex Apalis Ixora (Petr Štetiar) Marvell Armada host bridge driver: - add DT binding for Marvell Armada 7K/8K PCIe controller (Thomas Petazzoni) - Add driver for Marvell Armada 7K/8K PCIe controller (Thomas Petazzoni) Marvell MVEBU host bridge driver: - Constify mvebu_pcie_pm_ops structure (Jisheng Zhang) - Use SET_NOIRQ_SYSTEM_SLEEP_PM_OPS for mvebu_pcie_pm_ops (Jisheng Zhang) Microsoft Hyper-V host bridge driver: - Report resources release after stopping the bus (Vitaly Kuznetsov) - Add explicit barriers to config space access (Vitaly Kuznetsov) Renesas R-Car host bridge driver: - Select PCI_MSI_IRQ_DOMAIN (Arnd Bergmann) Synopsys DesignWare host bridge driver: - Remove incorrect RC memory base/limit configuration (Gabriele Paoloni) - Move Root Complex setup code to dw_pcie_setup_rc() (Jisheng Zhang) TI Keystone host bridge driver: - Add error IRQ handler (Murali Karicheri) - Remove unnecessary goto statement (Murali Karicheri) Miscellaneous: - Fix spelling errors (Colin Ian King)" * tag 'pci-v4.7-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (48 commits) PCI: Disable all BAR sizing for devices with non-compliant BARs x86/PCI: Mark Broadwell-EP Home Agent 1 as having non-compliant BARs PCI: Identify Enhanced Allocation (EA) BAR Equivalent resources in sysfs PCI, of: Move PCI I/O space management to PCI core code PCI: generic, thunder: Use generic ECAM API PCI: Provide common functions for ECAM mapping PCI: hv: Add explicit barriers to config space access PCI: Use cached copy of PCI_EXP_SLTCAP_HPC bit PCI: Add Downstream Port Containment driver PCI: Add Downstream Port Containment portdrv service type PCI: Widen portdrv service type from 4 bits to 8 bits PCI: designware: Remove incorrect RC memory base/limit configuration PCI: hv: Report resources release after stopping the bus ARM: dts: imx6qp: Specify imx6qp version of PCIe core PCI: imx6: Implement reset sequence for i.MX6+ PCI: imx6: Use enum instead of bool for variant indicator PCI: thunder: Don't clobber read-only bits in bridge config registers thunderbolt: Fix double free of drom buffer PCI: rcar: Select PCI_MSI_IRQ_DOMAIN PCI: armada: Add driver for Marvell Armada 7K/8K PCIe controller ...
2016-05-18Merge tag 'armsoc-drivers' of ↵Linus Torvalds1-17/+227
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Arnd Bergmann: "Driver updates for ARM SoCs, these contain various things that touch the drivers/ directory but got merged through arm-soc for practical reasons. For the most part, this is now related to power management controllers, which have not yet been abstracted into a separate subsystem, and typically require some code in drivers/soc or arch/arm to control the power domains. Another large chunk here is a rework of the NVIDIA Tegra USB3.0 support, which was surprisingly tricky and took a long time to get done. Finally, reset controller handling as always gets merged through here as well" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (97 commits) arm-ccn: Enable building as module soc/tegra: pmc: Add generic PM domain support usb: xhci: tegra: Add Tegra210 support usb: xhci: Add NVIDIA Tegra XUSB controller driver dt-bindings: usb: xhci-tegra: Add Tegra210 XUSB controller support dt-bindings: usb: Add NVIDIA Tegra XUSB controller binding PCI: tegra: Support per-lane PHYs dt-bindings: pci: tegra: Update for per-lane PHYs phy: tegra: Add Tegra210 support phy: Add Tegra XUSB pad controller support dt-bindings: phy: tegra-xusb-padctl: Add Tegra210 support dt-bindings: phy: Add NVIDIA Tegra XUSB pad controller binding phy: core: Allow children node to be overridden clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs drivers: firmware: psci: make two helper functions inline soc: renesas: rcar-sysc: Add support for R-Car H3 power areas soc: renesas: rcar-sysc: Add support for R-Car E2 power areas soc: renesas: rcar-sysc: Add support for R-Car M2-N power areas soc: renesas: rcar-sysc: Add support for R-Car M2-W power areas soc: renesas: rcar-sysc: Add support for R-Car H2 power areas ...
2016-05-18Merge tag 'armsoc-defconfig' of ↵Linus Torvalds2-3/+3
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC defconfig updates from Arnd Bergmann: "As usual, a bunch of commits, mostly adding drivers and other options to defconfigs. We are adding three new defconfig files for the newly added 32-bit machines (aspeed and mps2), the rest is mainly housekeeping. The changes outside of arch/arm/config/ are for a Kconfig symbol that got renamed" * tag 'armsoc-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (63 commits) ARM: aspeed: adapt defconfigs for new CONFIG_PRINTK_TIME ARM: u8500_defconfig: update sensor config ARM: u8500_defconfig: remove staging from defconfig ARM: multi_v7_defconfig: Remove unused Kconfig option MACH_UX500_DT ARM: at91/defconfig: sama5: add CONFIG_FHANDLE arm/configs: Add Aspeed defconfig arm/configs/multi_v5: Add Aspeed ast2400 ARM: at91: sama5: Update defconfig ARM: imx_v6_v7_defconfig: add CONFIG_MICREL_PHY ARM: imx_v6_v7_defconfig: add CONFIG_I2C_GPIO ARM: multi_v7: Enable Tegra XUSB controller in defconfig ARM: tegra: Enable XUSB controller in defconfig ARM: omap2plus_defconfig: Enable PWM and ir-rx51 as loadable modules ARM: multi_v7_defconfig: add the Atmel sama5d2-compatible ADC driver ARM: multi_v7_defconfig: add the Atmel Audio microphone interface PDMIC ARM: multi_v7_defconfig: add Atmel ISI (Image Sensor Interface) driver ARM: multi_v7_defconfig: add Atmel watchdog timers ARM: multi_v7_defconfig: add HLCDC drivers as modules ARM: at91/defconfig: add PDMIC driver to sama5_defconfig ARM: at91/defconfig: add HLCDC driver to sama5_defconfig ...
2016-05-17Merge branches 'pci/arm64' and 'pci/host-hv' into nextBjorn Helgaas12-237/+473
* pci/arm64: PCI, of: Move PCI I/O space management to PCI core code PCI: generic, thunder: Use generic ECAM API PCI: Provide common functions for ECAM mapping * pci/host-hv: PCI: hv: Add explicit barriers to config space access
2016-05-17Merge branches 'pci/hotplug' and 'pci/resource' into nextBjorn Helgaas3-18/+12
* pci/hotplug: PCI: Use cached copy of PCI_EXP_SLTCAP_HPC bit * pci/resource: PCI: Disable all BAR sizing for devices with non-compliant BARs x86/PCI: Mark Broadwell-EP Home Agent 1 as having non-compliant BARs PCI: Identify Enhanced Allocation (EA) BAR Equivalent resources in sysfs
2016-05-16PCI: Disable all BAR sizing for devices with non-compliant BARsPrarit Bhargava1-3/+3
b84106b4e229 ("PCI: Disable IO/MEM decoding for devices with non-compliant BARs") disabled BAR sizing for BARs 0-5 of devices that don't comply with the PCI spec. But it didn't do anything for expansion ROM BARs, so we still try to size them, resulting in warnings like this on Broadwell-EP: pci 0000:ff:12.0: BAR 6: failed to assign [mem size 0x00000001 pref] Move the non-compliant BAR check from __pci_read_base() up to pci_read_bases() so it applies to the expansion ROM BAR as well as to BARs 0-5. Note that direct callers of __pci_read_base(), like sriov_init(), will now bypass this check. We haven't had reports of devices with broken SR-IOV BARs yet. [bhelgaas: changelog] Fixes: b84106b4e229 ("PCI: Disable IO/MEM decoding for devices with non-compliant BARs") Signed-off-by: Prarit Bhargava <prarit@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org CC: Thomas Gleixner <tglx@linutronix.de> CC: Ingo Molnar <mingo@redhat.com> CC: "H. Peter Anvin" <hpa@zytor.com> CC: Andi Kleen <ak@linux.intel.com>
2016-05-16PCI: Identify Enhanced Allocation (EA) BAR Equivalent resources in sysfsAlex Williamson1-1/+1
Resource flags are exposed to userspace via the sysfs "resource" file. lspci reads the sysfs file to determine resource properties. Add a "BAR Equivalent Indicator" flag so lspci can distinguish between [virtual] and [enhanced] resources. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Sean O. Stalley <sean.stalley@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-05-12PCI, of: Move PCI I/O space management to PCI core codeTomasz Nowicki1-0/+115
No functional changes in this patch. PCI I/O space mapping code does not depend on OF; therefore it can be moved to PCI core code. This way we will be able to use it, e.g., in ACPI PCI code. Suggested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Tomasz Nowicki <tn@semihalf.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Arnd Bergmann <arnd@arndb.de> CC: Liviu Dudau <Liviu.Dudau@arm.com>
2016-05-12PCI: generic, thunder: Use generic ECAM APIJayachandran C7-237/+113
Use functions provided by drivers/pci/ecam.h for mapping the config space in drivers/pci/host/pci-host-common.c, and update its users to use 'struct pci_config_window' and 'struct pci_ecam_ops'. The changes are mostly to use 'struct pci_config_window' in place of 'struct gen_pci'. Some of the fields of gen_pci were only used temporarily and can be eliminated by using local variables or function arguments, these are not carried over to struct pci_config_window. pci-thunder-ecam.c and pci-thunder-pem.c are the only users of the pci_host_common_probe function and the gen_pci structure; these have been updated to use the new API as well. The patch does not introduce any functional changes other than a very minor one: with the new code, on 64-bit platforms, we do just a single ioremap for the whole config space. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-05-12PCI: Provide common functions for ECAM mappingJayachandran C4-0/+231
Add config option PCI_ECAM and file drivers/pci/ecam.c to provide generic functions for accessing memory-mapped PCI config space. The API is defined in drivers/pci/ecam.h and is written to replace the API in drivers/pci/host/pci-host-common.h. The file defines a new 'struct pci_config_window' to hold the information related to a PCI config area and its mapping. This structure is expected to be used as sysdata for controllers that have ECAM based mapping. Helper functions are provided to setup the mapping, free the mapping and to implement the map_bus method in 'struct pci_ops' Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-05-11powerpc/pci: Rename pcibios_find_pci_bus()Gavin Shan2-4/+4
This renames pcibios_find_pci_bus() to pci_find_bus_by_node() to avoid conflicts with those PCI subsystem weak function names, which have prefix "pcibios". No logical changes introduced. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-11powerpc/pci: Rename pcibios_{add, remove}_pci_devices()Gavin Shan3-4/+4
This renames pcibios_{add,remove}_pci_devices() to avoid conflicts with names of the weak functions in PCI subsystem, which have the prefix "pcibios". No logical changes introduced. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-By: Alistair Popple <alistair@popple.id.au> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-10Merge tag 'pci-v4.6-fixes-3' of ↵Linus Torvalds1-2/+4
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI fixes from Bjorn Helgaas: "Since v4.5, we've WARNed during resume if a PCI device, including a Thunderbolt device, was added while we were suspended. A change we merged for v4.6-rc1 turned that warning into a system hang. These enumeration patches from Lukas Wunner fix this issue: - Fix BUG on device attach failure - Do not treat EPROBE_DEFER as device attach failure" * tag 'pci-v4.6-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: PCI: Do not treat EPROBE_DEFER as device attach failure PCI: Fix BUG on device attach failure
2016-05-09Merge 4.6-rc7 into char-misc-testingGreg Kroah-Hartman3-6/+57
This resolves a merge issue with drivers/hv/ring_buffer.c Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-05-05PCI: hv: Add explicit barriers to config space accessVitaly Kuznetsov1-0/+14
I'm trying to pass-through Broadcom BCM5720 NIC (Dell device 1f5b) on a Dell R720 server. Everything works fine when the target VM has only one CPU, but SMP guests reboot when the NIC driver accesses PCI config space with hv_pcifront_read_config()/hv_pcifront_write_config(). The reboot appears to be induced by the hypervisor and no crash is observed. Windows event logs are not helpful at all ('Virtual machine ... has quit unexpectedly'). The particular access point is always different and putting debug between them (printk/mdelay/...) moves the issue further away. The server model affects the issue as well: on Dell R420 I'm able to pass-through BCM5720 NIC to SMP guests without issues. While I'm obviously failing to reveal the essence of the issue I was able to come up with a (possible) solution: if explicit barriers are added to hv_pcifront_read_config()/hv_pcifront_write_config() the issue goes away. The essential minimum is rmb() at the end on _hv_pcifront_read_config() and wmb() at the end of _hv_pcifront_write_config() but I'm not confident it will be sufficient for all hardware. I suggest the following barriers: 1) wmb()/mb() between choosing the function and writing to its space. 2) mb() before releasing the spinlock in both _hv_pcifront_read_config()/ _hv_pcifront_write_config() to ensure that consecutive reads/writes to the space won't get re-ordered as drivers may count on that. Config space access is not supposed to be performance-critical so these explicit barriers should not cause any slowdown. [bhelgaas: use Linux "barriers" terminology] Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jake Oshins <jakeo@microsoft.com>
2016-05-05PCI: Use cached copy of PCI_EXP_SLTCAP_HPC bitLukas Wunner1-14/+8
We cache the PCI_EXP_SLTCAP_HPC bit in pci_dev->is_hotplug_bridge on device probe, so there's no need to read it again on allocation of port service devices. No functional change intended. Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-05-03Merge branches 'pci/dpc', 'pci/resource' and 'pci/thunderbolt' into nextBjorn Helgaas7-9/+189
* pci/dpc: PCI: Add Downstream Port Containment driver PCI: Add Downstream Port Containment portdrv service type PCI: Widen portdrv service type from 4 bits to 8 bits * pci/resource: alpha/PCI: Call iomem_is_exclusive() for IORESOURCE_MEM, but not IORESOURCE_IO PCI: Supply CPU physical address (not bus address) to iomem_is_exclusive() * pci/thunderbolt: thunderbolt: Fix double free of drom buffer
2016-05-03Merge branches 'pci/host-armada', 'pci/host-designware', 'pci/host-hv', ↵Bjorn Helgaas15-127/+611
'pci/host-imx6', 'pci/host-keystone', 'pci/host-mvebu', 'pci/host-rcar', 'pci/host-thunder' and 'pci/host-vmd' into next * pci/host-armada: PCI: armada: Add driver for Marvell Armada 7K/8K PCIe controller dt-bindings: pci: add DT binding for Marvell Armada 7K/8K PCIe controller * pci/host-designware: PCI: designware: Remove incorrect RC memory base/limit configuration PCI: designware: Move Root Complex setup code to dw_pcie_setup_rc() * pci/host-hv: PCI: hv: Report resources release after stopping the bus * pci/host-imx6: ARM: dts: imx6qp: Specify imx6qp version of PCIe core PCI: imx6: Implement reset sequence for i.MX6+ PCI: imx6: Use enum instead of bool for variant indicator PCI: imx6: Add DT property for link gen, default to Gen1 PCI: imx6: Add reset-gpio-active-high boolean property to DT ARM: dts: imx6: Fix PCIe reset GPIO polarity on Toradex Apalis Ixora PCI: imx6: Add initial imx6sx support PCI: imx6: Factor out ref clock enable Revert "PCI: imx6: Add support for active-low reset GPIO" * pci/host-keystone: PCI: keystone: Remove unnecessary goto statement PCI: keystone: Add error IRQ handler * pci/host-mvebu: PCI: mvebu: Use SET_NOIRQ_SYSTEM_SLEEP_PM_OPS for mvebu_pcie_pm_ops PCI: mvebu: Constify mvebu_pcie_pm_ops structure * pci/host-rcar: PCI: rcar: Select PCI_MSI_IRQ_DOMAIN * pci/host-thunder: PCI: thunder: Don't clobber read-only bits in bridge config registers * pci/host-vmd: PCI: Remove return values from pcie_port_platform_notify() and relatives PCI/ACPI: Allow all PCIe services on non-ACPI host bridges
2016-05-03PCI: Add Downstream Port Containment driverKeith Busch3-0/+179
Add driver for the PCI Express Downstream Port Containment extended capability. DPC is an optional capability to contain uncorrectable errors below a port. For more information on DPC, please see PCI Express Base Specification Revision 4, section 7.31, or view the PCI-SIG DPC ECN here: https://pcisig.com/sites/default/files/specification_documents/ECN_DPC_2012-02-09_finalized.pdf When a DPC event is triggered, the hardware disables downstream links, so the DPC driver schedules removal for all devices below this port. This may happen concurrently with a PCIe hotplug driver if enabled. When all downstream devices are removed and the link state transitions to disabled, the DPC driver clears the DPC status and interrupt bits so the link may retrain for a newly connected device. [bhelgaas: clear (not set) DPC_CTL bits on remove, whitespace cleanup] Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Lukas Wunner <lukas@wunner.de>
2016-05-03PCI: Add Downstream Port Containment portdrv service typeKeith Busch3-3/+5
Add the Downstream Port Containment (PCIE_PORT_SERVICE_DPC) portdrv service type, available if the device has the DPC extended capability. [bhelgaas: split to separate patch, changelog] Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-05-03PCI: Widen portdrv service type from 4 bits to 8 bitsKeith Busch2-2/+2
The names of port service devices previously used one nibble to encode the port type and another nibble to encode the service type. We're about to add a fifth service type, so change device names to use one *byte* to encode the service type. For example, a hotplug port service on a downstream bridge was previously called "pcie24" and is now called "pcie204". The "2" encodes the device type (PCI_EXP_TYPE_DOWNSTREAM - 4), and the "4" (now "04") encodes the service (PCIE_PORT_SERVICE_HP). Based on Lukas Wunner's patch: https://github.com/l1k/linux/commit/b688d6e4873ab082e5916b1a993bc1d38c6f4178 [bhelgaas: split to separate patch, expand changelog] Based-on-patch-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-05-03PCI: designware: Remove incorrect RC memory base/limit configurationGabriele Paoloni1-8/+0
Currently dw_pcie_setup_rc() configures memory base and memory limit in the type1 configuration header for the root complex. In doing so it uses the CPU address (pp->mem_base) rather than the bus address (pp->mem_bus_addr). This is wrong and it is useless since the configuration is overwritten later on when pci_bus_assign_resources() is called. Remove this configuration from dw_pcie_setup_rc(). Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
2016-05-02PCI: hv: Report resources release after stopping the busVitaly Kuznetsov1-5/+5
Kernel hang is observed when pci-hyperv module is release with device drivers still attached. E.g., when I do 'rmmod pci_hyperv' with BCM5720 device pass-through-ed (tg3 module) I see the following: NMI watchdog: BUG: soft lockup - CPU#1 stuck for 22s! [rmmod:2104] ... Call Trace: [<ffffffffa0641487>] tg3_read_mem+0x87/0x100 [tg3] [<ffffffffa063f000>] ? 0xffffffffa063f000 [<ffffffffa0644375>] tg3_poll_fw+0x85/0x150 [tg3] [<ffffffffa0649877>] tg3_chip_reset+0x357/0x8c0 [tg3] [<ffffffffa064ca8b>] tg3_halt+0x3b/0x190 [tg3] [<ffffffffa0657611>] tg3_stop+0x171/0x230 [tg3] ... [<ffffffffa064c550>] tg3_remove_one+0x90/0x140 [tg3] [<ffffffff813bee59>] pci_device_remove+0x39/0xc0 [<ffffffff814a3201>] __device_release_driver+0xa1/0x160 [<ffffffff814a32e3>] device_release_driver+0x23/0x30 [<ffffffff813b794a>] pci_stop_bus_device+0x8a/0xa0 [<ffffffff813b7ab6>] pci_stop_root_bus+0x36/0x60 [<ffffffffa02c3f38>] hv_pci_remove+0x238/0x260 [pci_hyperv] The problem seems to be that we report local resources release before stopping the bus and removing devices from it and device drivers may try to perform some operations with these resources on shutdown. Move resources release report after we do pci_stop_root_bus(). Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jake Oshins <jakeo@microsoft.com>
2016-05-02PCI: imx6: Implement reset sequence for i.MX6+Andrey Smirnov1-2/+21
I.MX6+ has a dedicated bit for resetting PCIe core, which should be used instead of a regular reset sequence since using the latter will hang the SoC. This commit is based on c34068d48273e24d392d9a49a38be807954420ed from http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git Tested-by: Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-05-02PCI: imx6: Use enum instead of bool for variant indicatorAndrey Smirnov1-58/+69
Use enumerated type instead of a boolean flag to specify the variant of the PCIe IP block (6Q, 6SX, etc). This patch has zero functional impact, however it makes the code easier to extend for the case of more than 2 possible variants of an IP block (of which there are). [bhelgaas: rewrap comment, remove extra blank line] Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-05-02PCI: Do not treat EPROBE_DEFER as device attach failureLukas Wunner1-1/+1
Linux 4.5 introduced a behavioral change in device probing during the suspend process with commit 013c074f8642 ("PM / sleep: prohibit devices probing during suspend/hibernation"): It defers device probing during the entire suspend process, starting from the prepare phase and ending with the complete phase. A rule existed before that "we rely on subsystems not to do any probing once a device is suspended" but it is enforced only now (Alan Stern, https://lkml.org/lkml/2015/9/15/908). This resulted in a WARN splat if a PCI device (e.g., Thunderbolt) is plugged in while the system is asleep: Upon waking up, pciehp_resume() discovers new devices in the resume phase and immediately tries to bind them to a driver. Since probing is now deferred, device_attach() returns -EPROBE_DEFER, which provoked a WARN in pci_bus_add_device(). Linux 4.6-rc1 aggravates the situation with commit ab1a187bba5c ("PCI: Check device_attach() return value always"): If device_attach() returns a negative value, pci_bus_add_device() now removes the sysfs and procfs entries for the device and pci_bus_add_devices() subsequently locks up with a BUG. Even with the BUG fixed we're still in trouble because the device remains on the deferred probing list even though its sysfs and procfs entries are gone and its children won't be added. Fix by not interpreting -EPROBE_DEFER as failure. The device will be probed eventually (through device_unblock_probing() in dpm_complete()) and there is proper locking in place to avoid races (e.g., if devices are unplugged again und thus deleted from the system before deferred probing happens, I have tested this). Also, those functions which dereference dev->driver (e.g. pci_pm_*()) do contain proper NULL pointer checks. So it seems safe to ignore -EPROBE_DEFER. Fixes: ab1a187bba5c ("PCI: Check device_attach() return value always") Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Alan Stern <stern@rowland.harvard.edu>
2016-05-02PCI: Fix BUG on device attach failureLukas Wunner1-1/+3
Previously when pci_bus_add_device() called device_attach() and it returned a negative value, we emitted a WARN but carried on. Commit ab1a187bba5c ("PCI: Check device_attach() return value always"), introduced in Linux 4.6-rc1, changed this to unwind all steps preceding device_attach() and to not set dev->is_added = 1. The latter leads to a BUG if pci_bus_add_device() was called from pci_bus_add_devices(). Fix by not recursing to a child bus if device_attach() failed for the bridge leading to it. This can be triggered by plugging in a PCI device (e.g. Thunderbolt) while the system is asleep. The system locks up when woken because device_attach() returns -EPROBE_DEFER. Fixes: ab1a187bba5c ("PCI: Check device_attach() return value always") Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2016-05-02PCI: thunder: Don't clobber read-only bits in bridge config registersDavid Daney1-8/+34
The 32-bit addressing modes in the I/O and Prefetchable Memory registers are required to be read-only. Since the underlying access method allows them to be set, emulate their read-only nature and always set them. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-05-02PCI: rcar: Select PCI_MSI_IRQ_DOMAINArnd Bergmann1-0/+2
The R-Car PCIe driver requires the use of IRQ domains for its MSI code: drivers/pci/host/pcie-rcar.c:635:9: error: implicit declaration of function 'irq_find_mapping' [-Werror=implicit-function-declaration] drivers/pci/host/pcie-rcar.c:666:8: error: implicit declaration of function 'irq_create_mapping' [-Werror=implicit-function-declaration] ... Add a Kconfig select to ensure that the feature is always enabled. This is not consistent with what the other drivers do at the moment, but I have another patch that changes them to do it like this one, which is more logical. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Simon Horman <horms+renesas@verge.net.au>
2016-05-01drivers:hv: Use new vmbus_mmio_free() from client drivers.Jake Oshins1-7/+7
This patch modifies all the callers of vmbus_mmio_allocate() to call vmbus_mmio_free() instead of release_mem_region(). Signed-off-by: Jake Oshins <jakeo@microsoft.com> Signed-off-by: K. Y. Srinivasan <kys@microsoft.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-04-29PCI: tegra: Support per-lane PHYsThierry Reding1-17/+227
The current XUSB pad controller bindings are insufficient to describe PHY devices attached to USB controllers. New bindings have been created to overcome these restrictions. As a side-effect each root port now is assigned a set of PHY devices, one for each lane associated with the root port. This has the benefit of allowing fine-grained control of the power management for each lane. Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-26PCI: armada: Add driver for Marvell Armada 7K/8K PCIe controllerThomas Petazzoni3-0/+274
The Marvell Armada 7K/8K SoCs integrate a PCIe controller from Synopsys. Add a new driver that provides the small glue needed to use the existing Designware driver to make it work on Marvell Armada 7K/8K SoCs. The MSI support will be enabled at a later point. [bhelgaas: use dev_dbg(), dw_pcie_wait_for_link()] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-04-25PCI: Supply CPU physical address (not bus address) to iomem_is_exclusive()Bjorn Helgaas1-4/+3
iomem_is_exclusive() requires a CPU physical address, but on some arches we supplied a PCI bus address instead. On most arches, pci_resource_to_user(res) returns "res->start", which is a CPU physical address. But on microblaze, mips, powerpc, and sparc, it returns the PCI bus address corresponding to "res->start". The result is that pci_mmap_resource() may fail when it shouldn't (if the bus address happens to match an existing resource), or it may succeed when it should fail (if the resource is exclusive but the bus address doesn't match it). Call iomem_is_exclusive() with "res->start", which is always a CPU physical address, not the result of pci_resource_to_user(). Fixes: e8de1481fd71 ("resource: allow MMIO exclusivity for device drivers") Suggested-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Arjan van de Ven <arjan@linux.intel.com>
2016-04-25Merge branches 'pci/enumeration', 'pci/hotplug', 'pci/misc', 'pci/ntb', ↵Bjorn Helgaas6-36/+222
'pci/thunderbolt' and 'pci/virtualization' into next * pci/enumeration: x86/PCI: Refine PCI support check in pcibios_init() * pci/hotplug: PCI: acpiphp_ibm: Avoid uninitialized variable reference * pci/misc: PCI: Fix spelling errors * pci/ntb: PCI: Add DMA alias quirk for mic_x200_dma PCI: Add support for multiple DMA aliases PCI: Move informational printk to pci_add_dma_alias() PCI: Add pci_add_dma_alias() to abstract implementation * pci/thunderbolt: thunderbolt: Support 1st gen Light Ridge controller thunderbolt: Fix typos and magic number PCI: Add Intel Thunderbolt device IDs * pci/virtualization: PCI: Work around Intel Sunrise Point PCH incorrect ACS capability PCI: Reverse standard ACS vs device-specific ACS enabling PCI: Mark Intel i40e NIC INTx masking as broken
2016-04-25PCI: keystone: Remove unnecessary goto statementMurali Karicheri1-9/+14
Fix the misuse of goto statement in ks_pcie_get_irq_controller_info() as simple return is more appropriate for this function. While at it add an error log for absence of interrupt controller node. [bhelgaas: drop "ret" altogether since we always know the return value] Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Rob Herring <robh+dt@kernel.org> CC: Pawel Moll <pawel.moll@arm.com> CC: Mark Rutland <mark.rutland@arm.com> CC: Ian Campbell <ijc+devicetree@hellion.org.uk> CC: Kumar Gala <galak@codeaurora.org>
2016-04-22PCI: rcar-pcie: Remove Gen2 designation from KconfigSimon Horman2-3/+3
It appears that Gen2 is a misnomer for the R-Car PCIE driver which also supports Gen 1 and Gen 3 SoCs. Accordingly, drop Gen 2 from the help text and Kconfig symbol. Also, re-arange the Kconfig symbol name to use PCIE as the prefix. This appears to be in keeping with other PCIE Kconfig symbols. Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-04-20PCI: imx6: Add DT property for link gen, default to Gen1Tim Harvey1-7/+17
Freescale has stated [1] that the LVDS clock source of the IMX6 does not pass the PCI Gen2 clock jitter test, therefore unless an external Gen2 compliant external clock source is present and supplied back to the IMX6 PCIe core via LVDS CLK1/CLK2 you can not claim Gen2 compliance. Add a DT property to specify Gen1 vs Gen2 and check this before allowing a Gen2 link. We default to Gen1 if the property is not present because at this time there are no IMX6 boards in mainline that 'input' a clock on LVDS CLK1/CLK2. In order to be Gen2 compliant on IMX6 you need to: - Have a Gen2 compliant external clock generator and route that clock back to either LVDS CLK1 or LVDS CLK2 as an input (see IMX6SX-SabreSD reference design). - Specify this clock in the PCIe node in the DT (i.e., IMX6QDL_CLK_LVDS1_IN or IMX6QDL_CLK_LVDS2_IN instead of IMX6QDL_CLK_LVDS1_GATE which configures it as a CLK output). [1] https://community.freescale.com/message/453209 Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Zhu Richard <Richard.Zhu@freescale.com> CC: Akshay Bhat <akshay.bhat@timesys.com> CC: Rob Herring <robh+dt@kernel.org> CC: Shawn Guo <shawnguo@kernel.org>
2016-04-20PCI: imx6: Add reset-gpio-active-high boolean property to DTPetr Štetiar1-3/+11
Currently the reset-gpio DT property which controls the PCI bus device reset signal defaults to active-low reset sequence (L=reset state, H=operation state) plus the code in reset function isn't GPIO polarity aware - it doesn't matter if the defined reset-gpio is active-low or active-high, it will always result into active-low reset sequence. I've tried to fix it properly and change the reset-gpio reset sequence to be polarity-aware, but this patch has been accepted and then reverted as it has introduced few backward incompatible issues: 1. Some DTBs, for example, imx6qdl-sabresd, don't define reset-gpio polarity correctly: reset-gpio = <&gpio7 12 0>; which means that it's defined as active-high, but in reality it's active-low; thus it wouldn't work without a DTS fix. 2. The logic in the reset function is inverted: gpio_set_value_cansleep(imx6_pcie->reset_gpio, 0) msleep(100); gpio_set_value_cansleep(imx6_pcie->reset_gpio, 1); so even if some of the i.MX6 boards had reset-gpio polarity defined correctly in their DTSes, they would stop working. As we can't break old DTBs, we can't fix them, so we need to introduce this new DT reset-gpio-active-high boolean property so we can support boards with active-high reset sequence. This active-high reset sequence is for example needed on Apalis SoMs, where GPIO1_IO28, used to PCIe reset is not connected directly to PERST# PCIe signal, but it's ORed with RESETBMCU coming off the PMIC, and thus is inverted, active-high. Tested-by: Tim Harvey <tharvey@gateworks.com> # Gateworks Ventana boards (which have active-low PERST#) Signed-off-by: Petr Štetiar <ynezz@true.cz> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org>
2016-04-20PCI: imx6: Add initial imx6sx supportChristoph Fritz1-0/+53
Add initial PCIe support for the imx6 SoC derivate imx6sx. PCI MSI support is untested as the necessary suspend/resume quirk is not included in this patch. This patch is heavily based on patches by Richard Zhu. [bhelgaas: factor out refclk enable, fix adjacent typos in imx6q-pcie.txt] Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com> Acked-by: Richard Zhu <Richard.Zhu@freescale.com> Acked-by: Lucas Stach <l.stach@pengutronix.de>
2016-04-20PCI: imx6: Factor out ref clock enableBjorn Helgaas1-12/+24
Factor out ref clock enable to make it cleaner to add imx6sx support. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Christoph Fritz <chf.fritz@googlemail.com>
2016-04-20PCI: Work around Intel Sunrise Point PCH incorrect ACS capabilityAlex Williamson1-0/+78
Intel Sunrise Point root ports implement ACS but use dwords for the capability and control registers, putting the control register at the wrong offset. Use quirks to enable and test ACS for these devices, which match the standard functions modulo the broken control register offset. Note that lspci assumes devices implement ACS per spec, so it shows invalid ACS data for these devices. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-04-20PCI: Reverse standard ACS vs device-specific ACS enablingAlex Williamson2-8/+8
The original thought was that if a device implemented ACS, then surely we want to use that... well, it turns out that devices can make an ACS capability so broken that we still need to fall back to quirks. Reverse the order of ACS enabling to give quirks first shot at it. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-04-20PCI: Mark Intel i40e NIC INTx masking as brokenAlex Williamson1-0/+33
All of the i40e (XL710/X710) 10/20/40GbE NICs lack support for indicating INTx is asserted via the interrupt bit in the PCI status register. The DisINTx bit in the command register is functional, causing these devices to be incorrectly detected as supporting INTx masking. Quirk them to properly indicate no INTx masking support. Device IDs copied from i40e_devids.h. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: John Ronciak <john.ronciak@intel.com> CC: Jesse Brandeburg <jesse.brandeburg@intel.com>
2016-04-19Merge tag 'pci-v4.6-fixes-2' of ↵Linus Torvalds3-6/+57
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI fixes from Bjorn Helgaas: "These are fixes for two issues: - The VPD parsing code we added for v4.6 keeps some devices from crashing, but also keeps cxgb4 from reading non-standard extra VPD data that is relies on. Hariprasad added a way for the driver to specify how much VPD is valid. - The i.MX6 active-low reset GPIO support we added in v4.5 caused regressions on some boards, so we're reverting that. VPD: Add pci_set_vpd_size() (Hariprasad Shenai) cxgb4: Set VPD size so we can read both VPD structures (Hariprasad Shenai) Freescale i.MX6 host bridge driver: Revert "PCI: imx6: Add support for active-low reset GPIO" (Fabio Estevam)" * tag 'pci-v4.6-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: cxgb4: Set VPD size so we can read both VPD structures PCI: Add pci_set_vpd_size() to set VPD size Revert "PCI: imx6: Add support for active-low reset GPIO"
2016-04-15PCI: Add pci_set_vpd_size() to set VPD sizeHariprasad Shenai2-0/+43
After 104daa71b396 ("PCI: Determine actual VPD size on first access"), the PCI core computes the valid VPD size by parsing the VPD starting at offset 0x0. We don't attempt to read past that valid size because that causes some devices to crash. However, some devices do have data past that valid size. For example, Chelsio adapters contain two VPD structures, and the driver needs both of them. Add pci_set_vpd_size(). If a driver knows it is safe to read past the end of the VPD data structure at offset 0, it can use pci_set_vpd_size() to allow access to as much data as it needs. [bhelgaas: changelog, split patches, rename to pci_set_vpd_size() and return int (not ssize_t)] Fixes: 104daa71b396 ("PCI: Determine actual VPD size on first access") Tested-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-17 21:42:01 +0300