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2017-02-10PCI: xilinx-nwl: Remove mask for messages not supported by AXIBharat Kumar Gogada1-13/+1
Remove support for vendor-defined messages which are not supported by AXI. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-02-09PCI: xilinx: Configure PCIe MPS settingsBjorn Helgaas1-1/+3
Make sure PCIe MPS settings are valid when we enumerate a new hierarchy. Based-on-patch-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-15Merge tag 'pci-v4.10-changes' of ↵Linus Torvalds21-417/+1772
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: "PCI changes: - add support for PCI on ARM64 boxes with ACPI. We already had this for theoretical spec-compliant hardware; now we're adding quirks for the actual hardware (Cavium, HiSilicon, Qualcomm, X-Gene) - add runtime PM support for hotplug ports - enable runtime suspend for Intel UHCI that uses platform-specific wakeup signaling - add yet another host bridge registration interface. We hope this is extensible enough to subsume the others - expose device revision in sysfs for DRM - to avoid device conflicts, make sure any VF BAR updates are done before enabling the VF - avoid unnecessary link retrains for ASPM - allow INTx masking on Mellanox devices that support it - allow access to non-standard VPD for Chelsio devices - update Broadcom iProc support for PAXB v2, PAXC v2, inbound DMA, etc - update Rockchip support for max-link-speed - add NVIDIA Tegra210 support - add Layerscape LS1046a support - update R-Car compatibility strings - add Qualcomm MSM8996 support - remove some uninformative bootup messages" * tag 'pci-v4.10-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (115 commits) PCI: Enable access to non-standard VPD for Chelsio devices (cxgb3) PCI: Expand "VPD access disabled" quirk message PCI: pciehp: Remove loading message PCI: hotplug: Remove hotplug core message PCI: Remove service driver load/unload messages PCI/AER: Log AER IRQ when claiming Root Port PCI/AER: Log errors with PCI device, not PCIe service device PCI/AER: Remove unused version macros PCI/PME: Log PME IRQ when claiming Root Port PCI/PME: Drop unused support for PMEs from Root Complex Event Collectors PCI: Move config space size macros to pci_regs.h x86/platform/intel-mid: Constify mid_pci_platform_pm PCI/ASPM: Don't retrain link if ASPM not possible PCI: iproc: Skip check for legacy IRQ on PAXC buses PCI: pciehp: Leave power indicator on when enabling already-enabled slot PCI: pciehp: Prioritize data-link event over presence detect PCI: rcar: Add gen3 fallback compatibility string for pcie-rcar PCI: rcar: Use gen2 fallback compatibility last PCI: rcar-gen2: Use gen2 fallback compatibility last PCI: rockchip: Move the deassert of pm/aclk/pclk after phy_init() ..
2016-12-13Merge branch 'smp-hotplug-for-linus' of ↵Linus Torvalds1-50/+19
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull smp hotplug updates from Thomas Gleixner: "This is the final round of converting the notifier mess to the state machine. The removal of the notifiers and the related infrastructure will happen around rc1, as there are conversions outstanding in other trees. The whole exercise removed about 2000 lines of code in total and in course of the conversion several dozen bugs got fixed. The new mechanism allows to test almost every hotplug step standalone, so usage sites can exercise all transitions extensively. There is more room for improvement, like integrating all the pointlessly different architecture mechanisms of synchronizing, setting cpus online etc into the core code" * 'smp-hotplug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (60 commits) tracing/rb: Init the CPU mask on allocation soc/fsl/qbman: Convert to hotplug state machine soc/fsl/qbman: Convert to hotplug state machine zram: Convert to hotplug state machine KVM/PPC/Book3S HV: Convert to hotplug state machine arm64/cpuinfo: Convert to hotplug state machine arm64/cpuinfo: Make hotplug notifier symmetric mm/compaction: Convert to hotplug state machine iommu/vt-d: Convert to hotplug state machine mm/zswap: Convert pool to hotplug state machine mm/zswap: Convert dst-mem to hotplug state machine mm/zsmalloc: Convert to hotplug state machine mm/vmstat: Convert to hotplug state machine mm/vmstat: Avoid on each online CPU loops mm/vmstat: Drop get_online_cpus() from init_cpu_node_state/vmstat_cpu_dead() tracing/rb: Convert to hotplug state machine oprofile/nmi timer: Convert to hotplug state machine net/iucv: Use explicit clean up labels in iucv_init() x86/pci/amd-bus: Convert to hotplug state machine x86/oprofile/nmi: Convert to hotplug state machine ...
2016-12-12Merge branch 'pci/host-vmd' into nextBjorn Helgaas2-9/+23
* pci/host-vmd: PCI: vmd: Fix suspend handlers defined-but-not-used warning PCI: vmd: Use SRCU as a local RCU to prevent delaying global RCU PCI: vmd: Remove unnecessary pci_set_drvdata()
2016-12-12Merge branch 'pci/host-tegra' into nextBjorn Helgaas2-60/+102
* pci/host-tegra: arm64: tegra: Enable PCIe on Jetson TX1 arm64: tegra: Add PCIe host bridge on Tegra210 PCI: tegra: Enable the driver on 64-bit ARM PCI: tegra: Add Tegra210 support PCI: tegra: Implement PCA enable workaround dt-bindings: pci: tegra: Add Tegra210 support PCI: tegra: Use new pci_register_host_bridge() interface PCI: Export host bridge registration interface PCI: Allow driver-specific data in host bridge PCI: Add pci_register_host_bridge() interface
2016-12-12Merge branch 'pci/host-spear' into nextBjorn Helgaas1-5/+1
* pci/host-spear: PCI: spear: Use builtin_platform_driver() to simplify the code
2016-12-12Merge branch 'pci/host-rockchip' into nextBjorn Helgaas6-97/+221
* pci/host-rockchip: PCI: rockchip: Move the deassert of pm/aclk/pclk after phy_init() PCI: rockchip: Split out rockchip_cfg_atu() PCI: rockchip: Clean up bit definitions for PCIE_RC_CONFIG_LCS PCI: rockchip: Correct the use of FTS mask PCI: rockchip: Remove the pointer to L1 substate cap PCI: rockchip: Specify the link capability PCI: rockchip: Fix negotiated lanes calculation PCI: rockchip: Add Kconfig COMPILE_TEST PCI: rockchip: Mark RC as common clock architecture PCI: rockchip: Provide captured slot power limit and scale PCI: rockchip: Add three new resets as required properties PCI: Don't attempt to claim shadow copies of ROM PCI: designware: Check for iATU unroll support after initializing host PCI: qcom: Fix pp->dev usage before assignment PCI: designware-plat: Update author email address PCI: layerscape: Fix drvdata usage before assignment PCI: designware-plat: Change maintainer to Jose Abreu
2016-12-12Merge branch 'pci/host-rcar' into nextBjorn Helgaas2-3/+4
* pci/host-rcar: PCI: rcar: Add gen3 fallback compatibility string for pcie-rcar PCI: rcar: Use gen2 fallback compatibility last PCI: rcar-gen2: Use gen2 fallback compatibility last
2016-12-12Merge branch 'pci/host-qcom' into nextBjorn Helgaas1-5/+172
* pci/host-qcom: PCI: qcom: Add support for MSM8996 PCIe controller
2016-12-12Merge branch 'pci/host-layerscape' into nextBjorn Helgaas1-7/+13
* pci/host-layerscape: PCI: layerscape: Add LS1046a support PCI: layerscape: Remove redundant error message from ls_pcie_probe()
2016-12-12Merge branch 'pci/host-iproc' into nextBjorn Helgaas5-122/+902
* pci/host-iproc: PCI: iproc: Skip check for legacy IRQ on PAXC buses PCI: iproc: Fix incorrect MSI address alignment PCI: iproc: Add support for the next-gen PAXB controller PCI: iproc: Add PAXBv2 binding info PCI: iproc: Add inbound DMA mapping support PCI: iproc: Add optional dma-ranges PCI: iproc: Make outbound mapping code more generic PCI: iproc: Remove redundant outbound properties PCI: iproc: Add PAXC v2 support PCI: iproc: Add PAXCv2 related binding PCI: iproc: Fix exception with multi-function devices PCI: iproc: Add BCMA type PCI: iproc: Do not reset PAXC when initializing the driver PCI: iproc: Improve core register population
2016-12-12Merge branch 'pci/host-hv' into nextBjorn Helgaas1-39/+61
* pci/host-hv: PCI: hv: Allocate physically contiguous hypercall params buffer PCI: hv: Delete the device earlier from hbus->children for hot-remove PCI: hv: Fix hv_pci_remove() for hot-remove PCI: hv: Use the correct buffer size in new_pcichild_device() PCI: hv: Make unnecessarily global IRQ masking functions static
2016-12-12Merge branch 'pci/host-hisi' into nextBjorn Helgaas1-3/+1
* pci/host-hisi: PCI: hisi: Remove redundant error message from hisi_pcie_probe()
2016-12-12Merge branch 'pci/host-altera' into nextBjorn Helgaas1-8/+2
* pci/host-altera: PCI: altera: Remove redundant error message in altera_pcie_parse_dt() PCI: altera: Use builtin_platform_driver() to simplify the code
2016-12-12Merge branch 'pci/enumeration' into nextBjorn Helgaas2-5/+0
* pci/enumeration: PCI: Warn on possible RW1C corruption for sub-32 bit config writes PCI: Create revision file in sysfs
2016-12-08PCI: iproc: Skip check for legacy IRQ on PAXC busesAndy Gospodarek2-2/+12
PAXC and PAXCv2 buses do not support legacy IRQs so there is no reason to even try and map them. Without a change like this, one cannot create VFs on Nitro ports since legacy interrupts are checked as part of the PCI device creation process. Testing on PAXC hardware showed that VFs are properly created with only the change to not set pcie->map_irq, but just to be safe the change in iproc_pcie_setup() will ensure that pdev_fixup_irq() will not panic. Signed-off-by: Andy Gospodarek <gospo@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Ray Jui <ray.jui@broadcom.com>
2016-12-08PCI: rcar: Add gen3 fallback compatibility string for pcie-rcarSimon Horman1-0/+1
Add fallback compatibility string for the R-Car Gen 3 family. This is in keeping with the both the existing fallback compatibility string for the R-Car Gen 2 family and the fallback scheme being adopted wherever appropriate for drivers for Renesas SoCs. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-08PCI: rcar: Use gen2 fallback compatibility lastSimon Horman1-2/+2
Improve readability by listing fallback compatibility strings after the more-specific compatibility strings they provide a fallback for. This does not affect run-time behaviour as it is the order in the DTB that determines which compatibility string is used. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-08PCI: rcar-gen2: Use gen2 fallback compatibility lastSimon Horman1-1/+1
Improve readability by listing fallback compatibility strings after the more-specific compatibility strings they provide a fallback for. This does not affect run-time behaviour as it is the order in the DTB that determines which compatibility string is used. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-08PCI: rockchip: Move the deassert of pm/aclk/pclk after phy_init()Shawn Lin1-20/+20
Move deassert of pm/aclk/pclk after phy_init() as we want to optimize the logic of reset control and reuse rockchip_pcie_init_port() later which should fully follow the cold boot procedure of ROM code. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-12-08PCI: rockchip: Split out rockchip_cfg_atu()Shawn Lin1-49/+55
Split out a new function, rockchip_cfg_atu(), in order to re-configure the ATU when missing these information after wakeup from S3. [bhelgaas: add "dev" temporary, return 0 when known] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2016-12-08PCI: rockchip: Clean up bit definitions for PCIE_RC_CONFIG_LCSShawn Lin1-10/+4
PCIE_RC_CONFIG_LCS contains control and status bits specific to the PCIe link. The layout for this register looks the same as the existing PCI_EXP_LNKCTL and PCI_EXP_LNKSTA. So let's reuse them. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-08PCI: rockchip: Correct the use of FTS maskBrian Norris1-1/+1
We're trying to mask out bits[23:8] while retaining [32:24, 7:0], but we're doing the inverse. That doesn't have too much effect, since we're setting all the [23:8] bits to 1, and the other bits are only relevant for modes we're currently not using. But we should get this right. Fixes: ca1989084054 ("PCI: rockchip: Fix wrong transmitted FTS count") Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2016-12-08PCI: rockchip: Remove the pointer to L1 substate capShawn Lin1-9/+8
Per the errata of TRM, the RC can't support L1 substate, so remove the L1 substate cap as well as operation for PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2. Tested-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-08PCI: rockchip: Specify the link capabilityShawn Lin1-23/+37
rk3399 supports PCIe 2.x link speeds marginally at best, and on some boards, the link won't train at 5 GT/s at all. Rather than sacrifice 500ms waiting for training that will never happen, let's use the helper function, of_pci_get_max_link_speed(), to get the max link speed from DT and specify link capability. Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-08PCI: rockchip: Fix negotiated lanes calculationShawn Lin1-2/+2
The calculation of negotiated lanes is wrong: it should be shifted by PCIE_CORE_PL_CONF_LANE_SHIFT, but it is shifted by PCIE_CORE_PL_CONF_LANE_MASK instead. Let's fix it. Fixes: e77f847df54c ("PCI: rockchip: Add Rockchip PCIe controller support") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-08PCI: rockchip: Add Kconfig COMPILE_TESTShawn Lin1-1/+1
Allow selection of the Rockchip driver for compile testing, even if we aren't building for ARCH_ROCKCHIP. [bhelgaas: changelog] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-08PCI: rockchip: Mark RC as common clock architectureShawn Lin1-0/+6
The default value of common clock configuration is zero indicating Rockchip's RC is using asynchronous clock architecture but actually we are using common clock. This will confuse some EP drivers if they need some different settings referring to this value. Set the Common Clock Configuration bit in the Link Control Register. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-08PCI: rockchip: Provide captured slot power limit and scaleShawn Lin1-0/+40
If vpcie3v3 is available, we could provide these information via RC's configure register to make EP able to know the power limit. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-07PCI: Explain ARM64 ACPI/MCFG quirk Kconfig and build strategyBjorn Helgaas1-4/+15
Add Makefile comments to explain the Kconfig and build strategy for ARM64 drivers that work around not-quite-ECAM issues. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-07PCI: spear: Use builtin_platform_driver() to simplify the codeGeliang Tang1-5/+1
Use builtin_platform_driver() helper to simplify the code. Signed-off-by: Geliang Tang <geliangtang@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-07PCI: vmd: Fix suspend handlers defined-but-not-used warningBorislav Petkov1-1/+1
Fix the following warnings: drivers/pci/host/vmd.c:731:12: warning: ‘vmd_suspend’ defined but not used [-Wunused-function] static int vmd_suspend(struct device *dev) ^ drivers/pci/host/vmd.c:739:12: warning: ‘vmd_resume’ defined but not used [-Wunused-function] static int vmd_resume(struct device *dev) ^ Signed-off-by: Borislav Petkov <bp@suse.de> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org> Reviewed-by: Keith Busch <keith.busch@intel.com>
2016-12-07PCI: vmd: Use SRCU as a local RCU to prevent delaying global RCUJon Derrick2-7/+22
SRCU lets synchronize_srcu() depend on VMD-local RCU primitives, preventing long delays from locking up RCU in other systems. VMD performs a synchronize when removing a device, but will hit all IRQ lists if the device uses all VMD vectors. This patch will not help VMD's RCU synchronization, but will isolate the read side delays to the VMD subsystem. Additionally, the use of SRCU in VMD's ISR will keep it isolated from any other RCU waiters in the rest of the system. Tested using concurrent FIO and NVMe resets: [global] rw=read bs=4k direct=1 ioengine=libaio iodepth=32 norandommap timeout=300 runtime=1000000000 [nvme0] cpus_allowed=0-63 numjobs=8 filename=/dev/nvme0n1 [nvme1] cpus_allowed=0-63 numjobs=8 filename=/dev/nvme1n1 while (true) do for i in /sys/class/nvme/nvme*; do echo "Resetting ${i##*/}" echo 1 > $i/reset_controller; sleep 5 done; done Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Keith Busch <keith.busch@intel.com>
2016-12-07PCI: tegra: Enable the driver on 64-bit ARMThierry Reding1-1/+1
The Tegra PCI host controller driver no longer relies on any of the 32-bit ARM glue for PCI, so it can be enabled on 64-bit configurations. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
2016-12-07PCI: tegra: Add Tegra210 supportThierry Reding1-8/+34
The PCIe host controller found on Tegra X1 is very similar to its predecessor on Tegra K1. A bug was introduced in the new revision that is worked around by always enabling the performance counter, otherwise accesses to configuration space will block for a number of seconds. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
2016-12-07PCI: tegra: Implement PCA enable workaroundThierry Reding1-0/+13
Tegra210's PCIe controller has a bug that requires the PCA (performance counter) feature to be enabled. If this isn't done, accesses to device configuration space will hang the chip for tens of seconds. Implement the workaround. Based on commit 514e19138af2 ("pci: tegra: implement PCA enable workaround") from U-Boot by Stephen Warren <swarren@nvidia.com>. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
2016-12-07PCI: tegra: Use new pci_register_host_bridge() interfaceArnd Bergmann1-51/+54
Tegra is one of the remaining platforms that still use the traditional pci_common_init_dev() interface for probing PCI host bridges. This demonstrates how to convert it to the pci_register_host interface I just added in a previous patch. This leads to a more linear probe sequence that can handle errors better because we avoid callbacks into the driver, and it makes the driver architecture independent. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
2016-12-06PCI: Add MCFG quirks for X-Gene host controllerDuc Dang3-10/+122
PCIe controllers in X-Gene SoCs are not ECAM compliant: software needs to configure additional controller's register to address device at bus:dev:function. Add a quirk to discover controller MMIO register space and configure controller registers to select and address the target secondary device. The quirk will only be applied for X-Gene PCIe MCFG table with OEM revison 1, 2, 3 or 4 (PCIe controller v1 and v2 on X-Gene SoCs). Tested-by: Jon Masters <jcm@redhat.com> Signed-off-by: Duc Dang <dhdang@apm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-06PCI: Add MCFG quirks for Cavium ThunderX pass1.x host controllerTomasz Nowicki3-3/+11
ThunderX pass1.x requires to emulate the EA headers for on-chip devices hence it has to use custom pci_thunder_ecam_ops for accessing PCI config space (pci-thunder-ecam.c). Add new entries to MCFG quirk array where it can be applied while probing ACPI based PCI host controller. ThunderX pass1.x is using the same way for accessing off-chip devices (so-called PEM) as silicon pass-2.x so we need to add PEM quirk entries too. Quirk is considered for ThunderX silicon pass1.x only which is identified via MCFG revision 2. ThunderX pass 1.x requires the following accessors: NUMA node 0 PCI segments 0- 3: pci_thunder_ecam_ops (MCFG quirk) NUMA node 0 PCI segments 4- 9: thunder_pem_ecam_ops (MCFG quirk) NUMA node 1 PCI segments 10-13: pci_thunder_ecam_ops (MCFG quirk) NUMA node 1 PCI segments 14-19: thunder_pem_ecam_ops (MCFG quirk) [bhelgaas: change Makefile/ifdefs so quirk doesn't depend on CONFIG_PCI_HOST_THUNDER_ECAM] Signed-off-by: Tomasz Nowicki <tn@semihalf.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-06PCI: Add MCFG quirks for Cavium ThunderX pass2.x host controllerTomasz Nowicki3-2/+47
ThunderX PCIe controller to off-chip devices (so-called PEM) is not fully compliant with ECAM standard. It uses non-standard configuration space accessors (see thunder_pem_ecam_ops) and custom configuration space granulation (see bus_shift = 24). In order to access configuration space and probe PEM as ACPI-based PCI host controller we need to add MCFG quirk infrastructure. This involves: 1. A new thunder_pem_acpi_init() init function to locate PEM-specific register ranges using ACPI. 2. Export PEM thunder_pem_ecam_ops structure so it is visible to MCFG quirk code. 3. New quirk entries for each PEM segment. Each contains platform IDs, mentioned thunder_pem_ecam_ops and CFG resources. Quirk is considered for ThunderX silicon pass2.x only which is identified via MCFG revision 1. ThunderX pass 2.x requires the following accessors: NUMA Node 0 PCI segments 0- 3: pci_generic_ecam_ops (ECAM-compliant) NUMA Node 0 PCI segments 4- 9: thunder_pem_ecam_ops (MCFG quirk) NUMA Node 1 PCI segments 10-13: pci_generic_ecam_ops (ECAM-compliant) NUMA Node 1 PCI segments 14-19: thunder_pem_ecam_ops (MCFG quirk) [bhelgaas: adapt to use acpi_get_rc_resources(), update Makefile/ifdefs so quirk doesn't depend on CONFIG_PCI_HOST_THUNDER_PEM] Signed-off-by: Tomasz Nowicki <tn@semihalf.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-06PCI: thunder-pem: Factor out resource lookupBjorn Helgaas1-23/+27
Pull the register resource lookup out of thunder_pem_init() so we can easily add a corresponding lookup using ACPI. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-12-06PCI: Add MCFG quirks for HiSilicon Hip05/06/07 host controllersDongdong Liu2-1/+102
The PCIe controller in Hip05/Hip06/Hip07 SoCs is not completely ECAM-compliant. It is non-ECAM only for the RC bus config space; for any other bus underneath the root bus it does support ECAM access. Add specific quirks for PCI config space accessors. This involves: 1. New initialization call hisi_pcie_init() to obtain RC base addresses from PNP0C02 at the root of the ACPI namespace (under \_SB). 2. New entry in common quirk array. [bhelgaas: move to pcie-hisi.c and change Makefile/ifdefs so quirk doesn't depend on CONFIG_PCI_HISI] Signed-off-by: Dongdong Liu <liudongdong3@huawei.com> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-11-30PCI: hv: Allocate physically contiguous hypercall params bufferLong Li1-10/+19
hv_do_hypercall() assumes that we pass a segment from a physically contiguous buffer. A buffer allocated on the stack may not work if CONFIG_VMAP_STACK=y is set. Use kmalloc() to allocate this buffer. Reported-by: Haiyang Zhang <haiyangz@microsoft.com> Signed-off-by: Long Li <longli@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: K. Y. Srinivasan <kys@microsoft.com>
2016-11-24PCI: iproc: Fix incorrect MSI address alignmentRay Jui1-1/+1
In the code to handle PAXB v2 based MSI steering, the logic aligns the MSI register address to the size of supported inbound mapping range. This is incorrect since it rounds "up" the starting address to the next aligned address, but what we want is the starting address to be rounded "down" to the aligned address. This patch fixes the issue and allows MSI writes to be properly steered to the GIC. Fixes: 4b073155fbd3 ("PCI: iproc: Add support for the next-gen PAXB controller") Signed-off-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-11-24PCI: qcom: Add support for MSM8996 PCIe controllerSrinivas Kandagatla1-5/+172
Add support for the MSM8996/APQ8096 PCIe controller. MSM8996 supports Gen 1/2, one lane, 3 PCIe root complexes with support for MSI and legacy interrupts, and it conforms to PCI Express Base 2.1 specification. Add a post_init callback to qcom_pcie_ops, as the PCIe pipe clocks are only setup after the phy is powered on. It also adds an ltssm_enable callback as it is very much different from other supported SoCs in the driver. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
2016-11-24PCI: iproc: Add support for the next-gen PAXB controllerRay Jui3-0/+132
Add support for the next generation of the iProc PAXB host controller, used in Stingray. Signed-off-by: Oza Oza <oza.oza@broadcom.com> Signed-off-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com>
2016-11-23PCI/xgene-msi: Convert to hotplug state machineSebastian Andrzej Siewior1-50/+19
Install the callbacks via the state machine and let the core invoke the callbacks on the already online CPUs. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Cc: linux-pci@vger.kernel.org Cc: Duc Dang <dhdang@apm.com> Cc: rt@linuxtronix.de Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/20161117183541.8588-8-bigeasy@linutronix.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2016-11-22PCI: Warn on possible RW1C corruption for sub-32 bit config writesBjorn Helgaas2-5/+0
Hardware that supports only 32-bit config writes is not spec-compliant. For example, if software performs a 16-bit write, we must do a 32-bit read, merge in the 16 bits we intend to write, followed by a 32-bit write. If the 16 bits we *don't* intend to write happen to have any RW1C (write-one- to-clear) bits set, we just inadvertently cleared something we shouldn't have. Add a rate-limited warning when we do sub-32 bit config writes. Remove similar probe-time warnings from some of the affected host bridge drivers. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Enthusiastically-Acked-by: Russell King <rmk+kernel@armlinux.org.uk> Acked-by: Shawn Lin <shawn.lin@rock-chips.com> # rockchip Acked-by: Thierry Reding <treding@nvidia.com>
2016-11-17PCI: iproc: Add inbound DMA mapping supportRay Jui2-0/+252
Add support for inbound DMA mapping. The range of the inbound mapping is configured by the optional device tree property 'dma-ranges'. While inbound mapping is done automatically in the ASIC on most iProc-based SoCs, newer ASICs (e.g., Stingray) require inbound mapping to be configured explicitly in software. [bhelgaas: fold in fixes to avoid 32-bit division in iproc_pcie_ib_write() and uninitialized return value in iproc_pcie_setup_ib() from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Oza Oza <oza.oza@broadcom.com> Signed-off-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-23 22:36:26 +0300