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path: root/drivers/ntb/ntb_hw.c
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2014-10-17ntb: Adding split BAR support for Haswell platformsDave Jiang1-47/+178
On the Haswell platform, a split BAR option to allow creation of 2 32bit BARs (4 and 5) from the 64bit BAR 4. Adding support for this new option. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
2014-10-17ntb: use errata flag set via DID to implement workaroundDave Jiang1-9/+38
Instead of using a module parameter, we should detect the errata via PCI DID and then set an appropriate flag. This will be used for additional errata later on. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
2014-10-17ntb: conslidate reading of PPD to move platform detection earlierDave Jiang1-28/+98
To simplify some of the platform detection code. Move the platform detection to a function to be called earlier. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
2014-10-17ntb: move platform detection to separate functionDave Jiang1-27/+47
Move the platform detection function to separate functions to allow easier maintenence. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
2014-10-17NTB: debugfs device entryJon Mason1-0/+101
Create a debugfs entry for the NTB device to log the basic device info, as well as display the error count on a number of registers. Signed-off-by: Jon Mason <jon.mason@intel.com>
2014-04-07ntb: Use pci_enable_msix_range() instead of pci_enable_msix()Alexander Gordeev1-15/+5
As result of deprecation of MSI-X/MSI enablement functions pci_enable_msix() and pci_enable_msi_block() all drivers using these two interfaces need to be updated to use the new pci_enable_msi_range() or pci_enable_msi_exact() and pci_enable_msix_range() or pci_enable_msix_exact() interfaces. Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Signed-off-by: Jon Mason <jon.mason@intel.com>
2014-04-07ntb: Split ntb_setup_msix() into separate BWD/SNB routinesAlexander Gordeev1-65/+102
This is an cleanup effort to make ntb_setup_msix() more readable - use ntb_setup_bwd_msix() to init MSI-Xs on BWD hardware and ntb_setup_snb_msix() - on SNB hardware. Function ntb_setup_snb_msix() also initializes MSI-Xs the way it should has been done - looping pci_enable_msix() until success or failure. Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Signed-off-by: Jon Mason <jon.mason@intel.com>
2014-04-07ntb: Use pci_msix_vec_count() to obtain number of MSI-XsAlexander Gordeev1-11/+4
Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Signed-off-by: Jon Mason <jon.mason@intel.com>
2014-04-07NTB: Code Style Clean-upJon Mason1-9/+10
Some white space and 80 char overruns corrected. Signed-off-by: Jon Mason <jon.mason@intel.com>
2014-04-07ntb: Fix leakage of ntb_device::msix_entries[] arrayAlexander Gordeev1-0/+1
Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Signed-off-by: Jon Mason <jon.mason@intel.com>
2014-04-07NTB: Fix typo in setting one translation registerRoland Dreier1-1/+1
In the code for Xeon devices in back-to-back mode with xeon_errata_workaround disabled, the downstream device puts the wrong value in SNB_B2B_XLAT_OFFSETL (SNB_MBAR01_DSD_ADDR vs. SNB_MBAR01_USD_ADDR). This was spotted while reading code, since the typo has no practical effect, at least for now: the low 32 bits of both constants are actually identical anyway. However, it's clearer and safer to use the right name. Signed-off-by: Roland Dreier <roland@purestorage.com> Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-11-20NTB: Disable interrupts and poll under high loadJon Mason1-5/+37
Disable interrupts and poll under high load Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-11-20NTB: Enable Snoop on Primary SideJon Mason1-5/+12
Enable Snoop from Primary to Secondary side on BAR23 and BAR45 on all TLPs. Previously, Snoop was only enabled from Secondary to Primary side. This can have a performance improvement on some workloads. Also, make the code more obvious about how the link is being enabled. Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-11-20NTB: Document HW errataJon Mason1-0/+12
Add a comment describing the necessary ordering of modifications to the NTB Limit and Base registers. Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-11-20ntb: Fix missed call to pci_enable_msix()Alexander Gordeev1-0/+4
Current MSI-X enablement code assumes MSI-Xs were successfully allocated in case less than requested vectors were available. That assumption is wrong, since MSI-Xs should be enabled with a repeated call to pci_enable_msix(). This update fixes this. Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-11-20NTB: Fix NTB-RP Link UpJon Mason1-8/+28
The Xeon NTB-RP setup, the transparent side does not get a link up/down interrupt. Since the presence of a NTB device on the transparent side means that we have a NTB link up, we can work around the lack of an interrupt by simply calling the link up function to notify the upper layers. Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-11-20NTB: Xeon Doorbell errata workaroundJon Mason1-5/+15
Modifications to the 14th bit of the B2BDOORBELL register will not be mirrored to the remote system due to a hardware issue. To get around the issue, shrink the number of available doorbell bits by 1. The max number of doorbells was being used as a way to referencing the Link Doorbell bit. Since this would no longer work, the driver must now explicitly reference that bit. This does not affect the xeon_errata_workaround case, as it is not using the b2bdoorbell register. Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-09-05ntb: clean up unnecessary MSI/MSI-X capability findYijing Wang1-4/+3
PCI core will initialize device MSI/MSI-X capability in pci_msi_init_pci_dev(). So device driver should use pci_dev->msi_cap/msix_cap to determine whether the device support MSI/MSI-X instead of using pci_find_capability(pci_dev, PCI_CAP_ID_MSI/MSIX). Access to PCIe device config space again will consume more time. Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-09-05NTB: Update VersionJon Mason1-1/+1
Update NTB version to 1.0 Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-09-05NTB: Comment FixJon Mason1-2/+3
Add "data" ntb_register_db_callback parameter description comment and correct poor spelling. Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-09-05NTB: Remove References of non-B2B BWD HWJon Mason1-12/+4
NTB-RP is not a supported configuration on BWD hardware. Remove the code attempting to set it up. Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-09-05NTB: NTB-RP supportJon Mason1-102/+160
Add support for Non-Transparent Bridge connected to a PCI-E Root Port on the remote system (also known as NTB-RP mode). This allows for a NTB enabled system to be connected to a non-NTB enabled system/slot. Modifications to the registers and BARs/MWs on the Secondary side by the remote system are reflected into registers on the Primary side for the local system. Similarly, modifications of registers and BARs/MWs on Primary side by the local system are reflected into registers on the Secondary side for the Remote System. This allows communication between the 2 sides via these registers and BARs/MWs. Note: there is not a fix for the Xeon Errata (that was already worked around in NTB-B2B mode) for NTB-RP mode. Due to this limitation, NTB-RP will not work on the Secondary side with the Xeon Errata workaround enabled. To get around this, disable the workaround via the xeon_errata_workaround=0 modparm. However, this can cause the hang described in the errata. Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-09-05NTB: Rename Variables for NTB-RPJon Mason1-42/+41
Many variable names in the NTB driver refer to the primary or secondary side. However, these variables will be used to access the reverse case when in NTB-RP mode. Make these names more generic in anticipation of NTB-RP support. Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-09-05NTB: Use DMA Engine to Transmit and ReceiveJon Mason1-0/+17
Allocate and use a DMA engine channel to transmit and receive data over NTB. If none is allocated, fall back to using the CPU to transfer data. Signed-off-by: Jon Mason <jon.mason@intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
2013-09-04NTB: Enable 32bit SupportJon Mason1-2/+2
Correct the issues on NTB that prevented it from working on x86_32 and modify the Kconfig to allow it to be permitted to be used in that environment as well. Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-09-04NTB: Update Device IDsJon Mason1-9/+20
Add support for new Intel NTB devices on upcoming Xeon hardware. Since the Xeon hardware design is already in place in the driver, all that is needed are the new device ids. Remove the device IDs for NTB devs running in Transparent Bridge mode, as this driver is not being used for those devices. Rename the device IDs for NTB devs running in NTB-RP mode to better identify their usage model. "PS" to denote the Primary Side of NTB, and "SS" to denote the secondary side. The primary side is the interface exposed to the local system, and the secondary side is the interface exposed to the remote system. Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-09-04NTB: BWD Link RecoveryJon Mason1-3/+107
The BWD NTB device will drop the link if an error is encountered on the point-to-point PCI bridge. The link will stay down until all errors are cleared and the link is re-established. On link down, check to see if the error is detected, if so do the necessary housekeeping to try and recover from the error and reestablish the link. There is a potential race between the 2 NTB devices recovering at the same time. If the times are synchronized, the link will not recover and the driver will be stuck in this loop forever. Add a random interval to the recovery time to prevent this race. Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-09-04NTB: Xeon Errata WorkaroundJon Mason1-13/+96
There is a Xeon hardware errata related to writes to SDOORBELL or B2BDOORBELL in conjunction with inbound access to NTB MMIO Space, which may hang the system. To workaround this issue, use one of the memory windows to access the interrupt and scratch pad registers on the remote system. This bypasses the issue, but removes one of the memory windows from use by the transport. This reduction of MWs necessitates adding some logic to determine the number of available MWs. Since some NTB usage methodologies may have unidirectional traffic, the ability to disable the workaround via modparm has been added. See BF113 in http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-c5500-c3500-spec-update.pdf See BT119 in http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e5-family-spec-update.pdf Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-09-03NTB: Correct debugfs to work with more than 1 NTB DeviceJon Mason1-0/+27
Debugfs was setup in NTB to only have a single debugfs directory. This resulted in the leaking of debugfs directories and files when multiple NTB devices were present, due to each device stomping on the variables containing the previous device's values (thus preventing them from being freed on cleanup). Correct this by creating a secondary directory of the PCI BDF for each device present, and nesting the previously existing information in those directories. Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-09-03NTB: Correct USD/DSD IdentificationJon Mason1-2/+5
Due to ambiguous documentation, the USD/DSD identification is backward when compared to the setting in BIOS. Correct the bits to match the BIOS setting. Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-09-03NTB: Correct Number of Scratch Pad RegistersJon Mason1-1/+1
The NTB Xeon hardware has 16 scratch pad registers and 16 back-to-back scratch pad registers. Correct the #define to represent this and update the variable names to reflect their usage. Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-09-03NTB: Add Error Handling in ntb_device_setupJon Mason1-1/+4
If an error is encountered in ntb_device_setup, it is possible that the spci_cmd isn't populated. Writes to the offset can result in a NULL pointer dereference. This issue is easily encountered by running in NTB-RP mode, as it currently is not supported and will generate an error. To get around this issue, return if an error is encountered prior to attempting to write to the spci_cmd offset. Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-05-15NTB: Handle 64bit BAR sizesJon Mason1-2/+2
64bit BAR sizes are permissible with an NTB device. To support them various modifications and clean-ups were required, most significantly using 2 32bit scratch pad registers for each BAR. Also, modify the driver to allow more than 2 Memory Windows. Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-05-15ntb: off by one sanity checksDan Carpenter1-3/+3
These tests are off by one. If "mw" is equal to NTB_NUM_MW then we would go beyond the end of the ndev->mw[] array. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Jon Mason <jon.mason@intel.com>
2013-01-22NTB: Fix Sparse WarningsJon Mason1-2/+2
Address the sparse warnings and resulting fallout Signed-off-by: Jon Mason <jon.mason@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-01-21NTB: Update VersionJon Mason1-1/+1
Update NTB version to 0.25 Signed-off-by: Jon Mason <jon.mason@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-01-21NTB: namespacecheck cleanupsJon Mason1-14/+0
Declare ntb_bus_type static to remove it from name space, and remove unused ntb_get_max_spads function. Found via `make namespacecheck`. Signed-off-by: Jon Mason <jon.mason@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-01-18ntb: remove __dev* markingsGreg Kroah-Hartman1-9/+7
These are now gone from the kernel, so remove them from the newly-added drivers before they start to cause build errors for people. Cc: Jon Mason <jon.mason@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-01-18PCI-Express Non-Transparent Bridge SupportJon Mason1-0/+1157
A PCI-Express non-transparent bridge (NTB) is a point-to-point PCIe bus connecting 2 systems, providing electrical isolation between the two subsystems. A non-transparent bridge is functionally similar to a transparent bridge except that both sides of the bridge have their own independent address domains. The host on one side of the bridge will not have the visibility of the complete memory or I/O space on the other side of the bridge. To communicate across the non-transparent bridge, each NTB endpoint has one (or more) apertures exposed to the local system. Writes to these apertures are mirrored to memory on the remote system. Communications can also occur through the use of doorbell registers that initiate interrupts to the alternate domain, and scratch-pad registers accessible from both sides. The NTB device driver is needed to configure these memory windows, doorbell, and scratch-pad registers as well as use them in such a way as they can be turned into a viable communication channel to the remote system. ntb_hw.[ch] determines the usage model (NTB to NTB or NTB to Root Port) and abstracts away the underlying hardware to provide access and a common interface to the doorbell registers, scratch pads, and memory windows. These hardware interfaces are exported so that other, non-mainlined kernel drivers can access these. ntb_transport.[ch] also uses the exported interfaces in ntb_hw.[ch] to setup a communication channel(s) and provide a reliable way of transferring data from one side to the other, which it then exports so that "client" drivers can access them. These client drivers are used to provide a standard kernel interface (i.e., Ethernet device) to NTB, such that Linux can transfer data from one system to the other in a standard way. Signed-off-by: Jon Mason <jon.mason@intel.com> Reviewed-by: Nicholas Bellinger <nab@linux-iscsi.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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