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2020-11-14Revert "Add a WA to defer flash writes on PS_ALERT_N assertion"Jae Hyun Yoo1-61/+0
It's ineffective. A complete solution will be provided in CPLD logic. This reverts commit 40fe787c69a2949684091b4647188d8915c8e2fa. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Change-Id: I0e5972adfd424d64152f208b30add98b67e32d48
2020-11-05Merge v5.8.17, commit '6d07b544ce203a684d9ca52635dcf2f4fc89b7d4' into ↵Jason M. Bills14-47/+139
dev-5.8-intel
2020-10-30Merge tag 'v5.8.17' into dev-5.8Joel Stanley7-33/+41
This is the 5.8.17 stable release Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-10-29mtd: rawnand: ams-delta: Fix non-OF build warningJanusz Krzysztofik1-0/+2
[ Upstream commit 6d11178762f7c8338a028b428198383b8978b280 ] Commit 7c2f66a960fc ("mtd: rawnand: ams-delta: Add module device tables") introduced an OF module device table but wrapped a reference to it with of_match_ptr() which resolves to NULL in non-OF configs. That resulted in a clang compiler warning on unused variable in non-OF builds. Fix it. drivers/mtd/nand/raw/ams-delta.c:373:34: warning: unused variable 'gpio_nand_of_id_table' [-Wunused-const-variable] static const struct of_device_id gpio_nand_of_id_table[] = { ^ 1 warning generated. Fixes: 7c2f66a960fc ("mtd: rawnand: ams-delta: Add module device tables") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200919080403.17520-1-jmkrzyszt@gmail.com Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-29mtd: spinand: gigadevice: Add QE BitHauke Mehrtens1-5/+5
[ Upstream commit aea7687e77bebce5b67fab9d03347bd8df7933c7 ] The following GigaDevice chips have the QE BIT in the feature flags, I checked the datasheets, but did not try this. * GD5F1GQ4xExxG * GD5F1GQ4xFxxG * GD5F1GQ4UAYIG * GD5F4GQ4UAYIG The Quad operations like 0xEB mention that the QE bit has to be set. Fixes: c93c613214ac ("mtd: spinand: add support for GigaDevice GD5FxGQ4xA") Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Tested-by: Chuanhong Guo <gch981213@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200820165121.3192-3-hauke@hauke-m.de Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-29mtd: spinand: gigadevice: Only one dummy byte in QUADIOHauke Mehrtens1-2/+2
[ Upstream commit 6387ad9caf8f09747a8569e5876086b72ee9382c ] The datasheet only lists one dummy byte in the 0xEH operation for the following chips: * GD5F1GQ4xExxG * GD5F1GQ4xFxxG * GD5F1GQ4UAYIG * GD5F4GQ4UAYIG Fixes: c93c613214ac ("mtd: spinand: add support for GigaDevice GD5FxGQ4xA") Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Tested-by: Chuanhong Guo <gch981213@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200820165121.3192-2-hauke@hauke-m.de Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-29mtd: rawnand: vf610: disable clk on error handling path in probeEvgeny Novikov1-2/+4
[ Upstream commit cb7dc3178a9862614b1e7567d77f4679f027a074 ] vf610_nfc_probe() does not invoke clk_disable_unprepare() on one error handling path. The patch fixes that. Found by Linux Driver Verification project (linuxtesting.org). Fixes: 6f0ce4dfc5a3 ("mtd: rawnand: vf610: Avoid a potential NULL pointer dereference") Signed-off-by: Evgeny Novikov <novikov@ispras.ru> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200806072634.23528-1-novikov@ispras.ru Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-29mtd: rawnand: stm32_fmc2: fix a buffer overflowChristophe Kerello1-1/+1
[ Upstream commit ab16f54ef3cdb6bbc06a36f636a89e6db8a6cea3 ] This patch solves following static checker warning: drivers/mtd/nand/raw/stm32_fmc2_nand.c:350 stm32_fmc2_nfc_select_chip() error: buffer overflow 'nfc->data_phys_addr' 2 <= 2 The CS value can only be 0 or 1. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Fixes: 2cd457f328c1 ("mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driver") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/1595325127-32693-1-git-send-email-christophe.kerello@st.com Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-29mtd: hyperbus: hbmc-am654: Fix direct mapping setup flash accessVignesh Raghavendra1-2/+2
[ Upstream commit aca31ce96814c84d1a41aaa109c15abe61005af7 ] Setting up of direct mapping should be done with flash node's IO address space and not with controller's IO region. Fixes: b6fe8bc67d2d3 ("mtd: hyperbus: move direct mapping setup to AM654 HBMC driver") Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20200924081214.16934-3-vigneshr@ti.com Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-29mtd: mtdoops: Don't write panic data twiceMark Tomlinson1-5/+6
[ Upstream commit c1cf1d57d1492235309111ea6a900940213a9166 ] If calling mtdoops_write, don't also schedule work to be done later. Although this appears to not be causing an issue, possibly because the scheduled work will never get done, it is confusing. Fixes: 016c1291ce70 ("mtd: mtdoops: do not use mtd->panic_write directly") Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200903034217.23079-1-mark.tomlinson@alliedtelesis.co.nz Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-29mtd: lpddr: fix excessive stack usage with clangArnd Bergmann1-16/+19
[ Upstream commit 3e1b6469f8324bee5927b063e2aca30d3e56b907 ] Building lpddr2_nvm with clang can result in a giant stack usage in one function: drivers/mtd/lpddr/lpddr2_nvm.c:399:12: error: stack frame size of 1144 bytes in function 'lpddr2_nvm_probe' [-Werror,-Wframe-larger-than=] The problem is that clang decides to build a copy of the mtd_info structure on the stack and then do a memcpy() into the actual version. It shouldn't really do it that way, but it's not strictly a bug either. As a workaround, use a static const version of the structure to assign most of the members upfront and then only set the few members that require runtime knowledge at probe time. Fixes: 96ba9dd65788 ("mtd: lpddr: add driver for LPDDR2-NVM PCM memories") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Nathan Chancellor <natechancellor@gmail.com> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200505140136.263461-1-arnd@arndb.de Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-27Add a WA to defer flash writes on PS_ALERT_N assertionJae Hyun Yoo1-0/+61
To prevent SPI flash corruption, this commit adds a WA which monitors PS_ALERT_N signal for detecting AC loss and it defers flash writes when the signal is asserted. Actually, the PS_ALERT_N is asserted even when PSU is in an unhealthy state so it also adds 10 seconds of timeout for the deferring that covers AC loss case effectively. If PSU gets back to healthy state, flash writes will be continued immediately. Note: It's still not a complete solution since an AC loss could happen while a previous event is still asserted from >=10 seconds ago. We would miss it. Note: This would be a customization for some specific platforms and this is a WA to cover a defect of H/W design. Do not try upstream it. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Change-Id: I3d0c18d46e6b7dac2aa472acf742add8336244da
2020-10-10SPI Quad IO driver support AST2600arun-pm2-9/+48
This commit adds spi driver quad io support for AST2600 Note:- Removed n25q00 Quad I/O support for the time being due to clock issue with chip 'Micron 8UA15 - rw182 (128MB)' while enabling Quad I/O mode. Signed-off-by: arun-pm <arun.p.m@linux.intel.com>
2020-08-31Merge tag 'v5.8.5' into dev-5.8dev-5.8Joel Stanley7-14/+98
This is the 5.8.5 stable release Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-21ubi: fastmap: Free fastmap next anchor peb during detachZhihao Cheng1-0/+5
[ Upstream commit c3fc1a3919e35a9d8157ed3ae6fd0a478293ba2c ] ubi_wl_entry related with the fm_next_anchor PEB is not freed during detach, which causes a memory leak. Don't forget to release fm_next_anchor PEB while detaching ubi from mtd when CONFIG_MTD_UBI_FASTMAP is enabled. Signed-off-by: Zhihao Cheng <chengzhihao1@huawei.com> Fixes: 4b68bf9a69d22d ("ubi: Select fastmap anchor PEBs considering...") Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-08-21ubi: fastmap: Don't produce the initial next anchor PEB when fastmap is disabledZhihao Cheng1-1/+2
[ Upstream commit 3b185255bb2f34fa6927619b9ef27f192a3d9f5a ] Following process triggers a memleak caused by forgetting to release the initial next anchor PEB (CONFIG_MTD_UBI_FASTMAP is disabled): 1. attach -> __erase_worker -> produce the initial next anchor PEB 2. detach -> ubi_fastmap_close (Do nothing, it should have released the initial next anchor PEB) Don't produce the initial next anchor PEB in __erase_worker() when fastmap is disabled. Signed-off-by: Zhihao Cheng <chengzhihao1@huawei.com> Suggested-by: Sascha Hauer <s.hauer@pengutronix.de> Fixes: f9c34bb529975fe ("ubi: Fix producing anchor PEBs") Reported-by: syzbot+d9aab50b1154e3d163f5@syzkaller.appspotmail.com Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-08-21mtd: rawnand: brcmnand: ECC error handling on EDU transfersKamal Dasu1-0/+26
[ Upstream commit 4551e78ad98add1f16b70cf286d5aad3ce7bcd4c ] Implement ECC correctable and uncorrectable error handling for EDU reads. If ECC correctable bitflips are encountered on EDU transfer, read page again using PIO. This is needed due to a NAND controller limitation where corrected data is not transferred to the DMA buffer on ECC error. This applies to ECC correctable errors that are reported by the controller hardware based on set number of bitflips threshold in the controller threshold register, bitflips below the threshold are corrected silently and are not reported by the controller hardware. Fixes: a5d53ad26a8b ("mtd: rawnand: brcmnand: Add support for flash-edu for dma transfers") Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200612212902.21347-3-kdasu.kdev@gmail.com Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-08-21mtd: rawnand: fsl_upm: Remove unused mtd varBoris Brezillon1-1/+0
[ Upstream commit ccc49eff77bee2885447a032948959a134029fe3 ] The mtd var in fun_wait_rnb() is now unused, let's get rid of it and fix the warning resulting from this unused var. Fixes: 50a487e7719c ("mtd: rawnand: Pass a nand_chip object to chip->dev_ready()") Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200603134922.1352340-2-boris.brezillon@collabora.com Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-08-19mtd: spi-nor: intel-spi: Simulate WRDI commandAlexander Sverdlin1-0/+9
commit 44a80df4bfce02f5d51fe5040bdbdf10d0d78f4e upstream. After spi_nor_write_disable() return code checks were introduced in the spi-nor front end intel-spi backend stopped to work because WRDI was never supported and always failed. Just pretend it was sucessful and ignore the command itself. HW sequencer shall do the right thing automatically, while with SW sequencer we cannot do it anyway, because the only tool we had was preopcode and it makes no sense for WRDI. Fixes: bce679e5ae3a ("mtd: spi-nor: Check for errors after each Register Operation") Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/282e1305-fd08-e446-1a22-eb4dff78cfb4@nokia.com Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-08-19mtd: rawnand: qcom: avoid write to unavailable registerSivaprakash Murugesan1-1/+6
commit 443440cc4a901af462239d286cd10721aa1c7dfc upstream. SFLASHC_BURST_CFG is only available on older ipq NAND platforms, this register has been removed when the NAND controller got implemented in the qpic controller. Avoid writing this register on devices which are based on qpic NAND controller. Fixes: dce84760b09f ("mtd: nand: qcom: Support for IPQ8074 QPIC NAND controller") Cc: stable@vger.kernel.org Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/1591948696-16015-2-git-send-email-sivaprak@codeaurora.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-08-19mtd: rawnand: brcmnand: Don't default to edu transferKamal Dasu1-2/+3
[ Upstream commit bee3ab8bdd3b13faf08e5b6e0218f59b0a49fcc3 ] When flash-dma is absent do not default to using flash-edu. Make sure flash-edu is enabled before setting EDU transfer function. Fixes: a5d53ad26a8b ("mtd: rawnand: brcmnand: Add support for flash-edu for dma transfers") Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200612212902.21347-2-kdasu.kdev@gmail.com Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-08-13mtd: spi-nor: sfdp: Revert "default to addr_width of 3 for configurable widths"Joel Stanley1-1/+0
This reverts commit f9acd7fa80be6ee14aecdc54429f2a48e56224e8 which breaks mounting of UBI volumes with the aspeed-smc driver: ubi0: default fastmap pool size: 25 ubi0: default fastmap WL pool size: 12 ubi0: attaching mtd3 ubi0: scanning is finished ubi0 error: ubi_read_volume_table: the layout volume was not found ubi0 error: ubi_attach_mtd_dev: failed to attach mtd3, error -22 Found by bisecting between v5.7 and v5.8. OpenBMC-Staging-Count: 1 Fixes: f9acd7fa80be ("mtd: spi-nor: sfdp: default to addr_width of 3 for configurable widths") Tested-by: Alexander A. Filippov <a.filippov@yadro.com> Tested-by: Adriana Kobylak <anoo@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-11mtd: properly check all write ioctls for permissionsGreg Kroah-Hartman1-9/+47
commit f7e6b19bc76471ba03725fe58e0c218a3d6266c3 upstream. When doing a "write" ioctl call, properly check that we have permissions to do so before copying anything from userspace or anything else so we can "fail fast". This includes also covering the MEMWRITE ioctl which previously missed checking for this. Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Richard Weinberger <richard@nod.at> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: stable <stable@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> [rw: Fixed locking issue] Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-08-06spi-nor: aspeed-smc: Detect 4b opcodes differentlyCédric Le Goater1-1/+3
SNOR_F_4B_OPCODES and related defines were removed from spi-nor.h in 829ec6408dc5 ("mtd: spi-nor: Trim what is exposed in spi-nor.h"). Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: fix options for mx66l51235fAlexander Amelkin1-1/+1
Currently in driver spi-nor there is a line for mx66l51235l. According to Macronix site there is no such part number. The chip detected as such is actually mx66l51235f. According to the datasheet for mx66l51235f, "The device default is in 24-bit address mode" (section 9-10). Hence we removed SPI_NOR_4B_OPCODES option with this commit. OpenBMC-Staging-Count: 10 Fixes: d342b6a973af ("mtd: spi-nor: enable 4B opcodes for mx66l51235l") Signed-off-by: Alexander Soldatov <a.soldatov@yadro.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Lei YU <mine260309@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: Disable zero size segments on the AST2600Cédric Le Goater1-2/+6
A disabled segment for a CS should have a zero value in its segment register. The driver was generating an incorrect value which overlapped with segment CS0. Accesses to the flash were blocked and Linux hung. OpenBMC-Staging-Count: 4 Fixes: 3635b880313a ("mtd: spi-nor: aspeed: add initial support for ast2600") Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: fix training of multiple CS on the AST2600Cédric Le Goater1-4/+5
Each CE has its own read timing compensation register. OpenBMC-Staging-Count: 4 Fixes: c62871befcdb ("mtd: spi-nor: aspeed: add support for AST2600 training") Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: add support for AST2600 trainingCédric Le Goater1-0/+68
The training consists of finding the appropriate read timing delays for the HCLK dividers 2, 3, 4, and 5 and store the results in the Read Timing Compensation register. The previous SoC AST2500 and AST2400 were covering a broader HCLK range [ 1 - 5 ] because the AHB frequency was lower. The algorithm first reads a golden buffer at low speed and then performs reads with different clocks and delay cycles settings to find a breaking point. This selects the default clock frequency for the CEx control register. The current settings are bit optimistic as we pick the first delay giving good results. A safer approach would be to determine an interval and choose the middle value. We might change the approach depending on the results on other systems. Only CS0 is taken into account for the moment. OpenBMC-Staging-Count: 4 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: check upper freq limit when doing trainingCédric Le Goater1-1/+1
OpenBMC-Staging-Count: 4 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: Introduce a HCLK mask for trainingCédric Le Goater1-1/+6
The AST2600 handles more HCLK divisors than its predecessors. OpenBMC-Staging-Count: 4 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: Introduce training operations per platformCédric Le Goater1-4/+22
The read timing compensation register is different on the AST2600 and training will be slightly more complex. OpenBMC-Staging-Count: 4 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: Check for disabled segments on the AST2600Cédric Le Goater1-4/+11
The segments can be disabled on the AST2600 (zero register value). CS0 is open by default but not the other CS. This is closing the access to the flash device in user mode and forbids scanning. For multiple CS, we will need firmware or a DT property to reopen the flash AHB window. OpenBMC-Staging-Count: 4 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: add initial support for ast2600Cédric Le Goater1-0/+73
The Segment Registers of the AST2600 have a different encoding. A 1MB unit is used and the address range of a flash SPI slave is encoded with offsets in the overall controller window. The previous SoC AST2400 and AST2500 used absolute addresses. Only bits [27:20] are relevant and the end address is an upper bound limit. SPI training yet to come. OpenBMC-Staging-Count: 4 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: Introduce segment operationsCédric Le Goater1-20/+56
AST2600 will use a different encoding for the addresses defined in the Segment Register. OpenBMC-Staging-Count: 4 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: Introduce a field for the AHB physical addressCédric Le Goater1-12/+6
On the AST2600, we will use it to compute the address of the chip AHB window from the Segment Register value. It also removes the need of aspeed_smc_ahb_base_phy() helper. OpenBMC-Staging-Count: 4 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: Add support for w25q512jvCédric Le Goater2-0/+5157
OpenBMC-Staging-Count: 4 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: add support for the 4B opcodesCédric Le Goater1-2/+9
Switch the default controller value to use the read mode in order to customize the command and use SPINOR_OP_READ_4B (0x13) when the chip supports 4B opcodes. OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2020-08-06mtd: spi-nor: aspeed: use memcpy_fromio() to capture the optimization bufferCédric Le Goater1-4/+2
aspeed_smc_read_from_ahb() only reads the first word which is not what we want. We want to capture a CALIBRATE_BUF_SIZE size window of the flash contents to optimize the read. OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2020-08-06mtd: spi-nor: aspeed: clarify 4BYTE address mode maskCédric Le Goater1-1/+9
OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2020-08-06mtd: spi-nor: aspeed: introduce a aspeed_smc_default_read() helperCédric Le Goater1-7/+12
OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2020-08-06mtd: spi-nor: aspeed: limit the maximum SPI frequencyCédric Le Goater1-4/+13
The optimize read algo can choose a 100MHz SPI frequency which might be a bit too high for dual output IO on some chips, for the W25Q256 on palmetto for instance. The MX66L1G45G on witherspoon should be fine though. Also, the second chip of the FMC controller does not get any optimize settings for reads. Only the first is configured by U-Boot. To fix these two issues, we introduce a "spi-max-frequency" property in the device tree which will be used to cap the optimize read algorithm and we run the algo on the FMC controller chips as well. By default, the frequency setting is 50MHz. OpenBMC-Staging-Count: 10 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: optimize read modeCédric Le Goater1-0/+191
This is only for SPI controllers as U-Boot should have done it already for the FMC controller using DMAs. The algo is based on the one found in the OpenPOWER pflash tool. It first reads a golden buffer at low speed and then performs reads with different clocks and delay cycles settings to find the fastest configuration for the chip. It can be deactivated at boot time with the kernel parameter : aspeed_smc.optimize_read=0 OpenBMC-Staging-Count: 11 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Alexander Soldatov <a.soldatov@yadro.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: link controller with the ahb clockCédric Le Goater1-0/+10
We will need the AHB frequency to set the HCLK settings in the SMC controller to optimize the reads. OpenBMC-Staging-Count: 11 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: add support for SPI dual IO read modeCédric Le Goater1-11/+43
Implements support for the dual IO read mode on aspeed SMC/FMC controllers which uses both MISO and MOSI lines for data during a read to double the read bandwidth. Still to be done SNOR_PROTO_1_2_2 Based on work from Robert Lippert <roblip@gmail.com> OpenBMC-Staging-Count: 11 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: use command mode for readsCédric Le Goater1-1/+27
When reading flash contents, try to use the "command mode" if the AHB window configured for the flash module is big enough. Else, just fall back to the "user mode" to perform the read. OpenBMC-Staging-Count: 11 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-07mtd: rawnand: xway: Fix build issueMiquel Raynal1-1/+1
This MIPS driver does not support COMPILE_TEST yet and failed to build under my radar. Replace 'mtd' chich is not defined in the scope of xway_nand_remove() by nand_to_mtd(chip). The mistake has been added in the long series dropping nand_release(). Tested with a 7.3.0 MIPS GCC toolchain built with Buildroot. Fixes: 9fdd78f7bcda ("mtd: rawnand: xway: Stop using nand_release()") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200626065511.16424-1-miquel.raynal@bootlin.com
2020-06-15mtd: set master partition panic write flagKamal Dasu1-2/+2
Check and set master panic write flag so that low level drivers can use it to take required action to ensure oops data gets written to assigned mtdoops device partition. Fixes: 9f897bfdd89f ("mtd: Add flag to indicate panic_write") Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200615155134.32007-1-kdasu.kdev@gmail.com
2020-06-15nandsim: Fix return code testing of ns_find_operation()Richard Weinberger1-1/+1
ns_find_operation() returns 0 on success. Fixes: 052a7a5374bc ("mtd: rawnand: nandsim: Clean error handling") Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200615113404.25447-1-richard@nod.at
2020-06-10Merge tag 'for-linus-5.8-rc1' of ↵Linus Torvalds4-25/+57
git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs Pull UBI update from Richard Weinberger: "This contains a single change for UBI: - Select fastmap anchor PEBs considering wear level rules" * tag 'for-linus-5.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs: ubi: Select fastmap anchor PEBs considering wear level rules
2020-06-10Merge tag 'mtd/for-5.8' of ↵Linus Torvalds83-2484/+4131
git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD updates from Richard Weinberger: "MTD core changes: - partition parser: Support MTD names containing one or more colons. - mtdblock: clear cache_state to avoid writing to bad blocks repeatedly. Raw NAND core changes: - Stop using nand_release(), patched all drivers. - Give more information about the ECC weakness when not matching the chip's requirement. - MAINTAINERS updates. - Support emulated SLC mode on MLC NANDs. - Support "constrained" controllers, adapt the core and ONFI/JEDEC table parsing and Micron's code. - Take check_only into account. - Add an invalid ECC mode to discriminate with valid ones. - Return an enum from of_get_nand_ecc_algo(). - Drop OOB_FIRST placement scheme. - Introduce nand_extract_bits(). - Ensure a consistent bitflips numbering. - BCH lib: - Allow easy bit swapping. - Rework a little bit the exported function names. - Fix nand_gpio_waitrdy(). - Propage CS selection to sub operations. - Add a NAND_NO_BBM_QUIRK flag. - Give the possibility to verify a read operation is supported. - Add a helper to check supported operations. - Avoid indirect access to ->data_buf(). - Rename the use_bufpoi variables. - Fix comments about the use of bufpoi. - Rename a NAND chip option. - Reorder the nand_chip->options flags. - Translate obscure bitfields into readable macros. - Timings: - Fix default values. - Add mode information to the timings structure. Raw NAND controller driver changes: - Fixed many error paths. - Arasan - New driver - Au1550nd: - Various cleanups - Migration to ->exec_op() - brcmnand: - Misc cleanup. - Support v2.1-v2.2 controllers. - Remove unused including <linux/version.h>. - Correctly verify erased pages. - Fix Hamming OOB layout. - Cadence - Make cadence_nand_attach_chip static. - Cafe: - Set the NAND_NO_BBM_QUIRK flag - cmx270: - Remove this controller driver. - cs553x: - Misc cleanup - Migration to ->exec_op() - Davinci: - Misc cleanup. - Migration to ->exec_op() - Denali: - Add more delays before latching incoming data - Diskonchip: - Misc cleanup - Migration to ->exec_op() - Fsmc: - Change to non-atomic bit operations. - GPMI: - Use nand_extract_bits() - Fix runtime PM imbalance. - Ingenic: - Migration to exec_op() - Fix the RB gpio active-high property on qi, lb60 - Make qi_lb60_ooblayout_ops static. - Marvell: - Misc cleanup and small fixes - Nandsim: - Fix the error paths, driver wide. - Omap_elm: - Fix runtime PM imbalance. - STM32_FMC2: - Misc cleanups (error cases, comments, timeout valus, cosmetic changes). SPI NOR core changes: - Add, update support and fix few flashes. - Prepare BFPT parsing for JESD216 rev D. - Kernel doc fixes. CFI changes: - Support the absence of protection registers for Intel CFI flashes. - Replace zero-length array with flexible-arrays" * tag 'mtd/for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (208 commits) mtd: clear cache_state to avoid writing to bad blocks repeatedly mtd: parser: cmdline: Support MTD names containing one or more colons mtd: physmap_of_gemini: remove defined but not used symbol 'syscon_match' mtd: rawnand: Add an invalid ECC mode to discriminate with valid ones mtd: rawnand: Return an enum from of_get_nand_ecc_algo() mtd: rawnand: Drop OOB_FIRST placement scheme mtd: rawnand: Avoid a typedef mtd: Fix typo in mtd_ooblayout_set_databytes() description mtd: rawnand: Stop using nand_release() mtd: rawnand: nandsim: Reorganize ns_cleanup_module() mtd: rawnand: nandsim: Rename a label in ns_init_module() mtd: rawnand: nandsim: Manage lists on error in ns_init_module() mtd: rawnand: nandsim: Fix the label pointing on nand_cleanup() mtd: rawnand: nandsim: Free erase_block_wear on error mtd: rawnand: nandsim: Use an additional label when freeing the nandsim object mtd: rawnand: nandsim: Stop using nand_release() mtd: rawnand: nandsim: Free the partition names in ns_free() mtd: rawnand: nandsim: Free the allocated device on error in ns_init() mtd: rawnand: nandsim: Free partition names on error in ns_init() mtd: rawnand: nandsim: Fix the two ns_alloc_device() error paths ...
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