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2019-10-21Merge tag 'v5.3.7' into dev-5.3Joel Stanley1-3/+2
This is the 5.3.7 stable release Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-10-17mtd: rawnand: au1550nd: Fix au_read_buf16() prototypePaul Burton1-3/+2
commit df8fed831cbcdce7b283b2d9c1aadadcf8940d05 upstream. Commit 7e534323c416 ("mtd: rawnand: Pass a nand_chip object to chip->read_xxx() hooks") modified the prototype of the struct nand_chip read_buf function pointer. In the au1550nd driver we have 2 implementations of read_buf. The previously mentioned commit modified the au_read_buf() implementation to match the function pointer, but not au_read_buf16(). This results in a compiler warning for MIPS db1xxx_defconfig builds: drivers/mtd/nand/raw/au1550nd.c:443:57: warning: pointer type mismatch in conditional expression Fix this by updating the prototype of au_read_buf16() to take a struct nand_chip pointer as its first argument, as is expected after commit 7e534323c416 ("mtd: rawnand: Pass a nand_chip object to chip->read_xxx() hooks"). Note that this shouldn't have caused any functional issues at runtime, since the offset of the struct mtd_info within struct nand_chip is 0 making mtd_to_nand() effectively a type-cast. Signed-off-by: Paul Burton <paul.burton@mips.com> Fixes: 7e534323c416 ("mtd: rawnand: Pass a nand_chip object to chip->read_xxx() hooks") Cc: stable@vger.kernel.org # v4.20+ Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-10-08Merge tag 'v5.3.5' into dev-5.3Joel Stanley2-67/+41
This is the 5.3.5 stable release Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-10-05mtd: rawnand: stm32_fmc2: avoid warnings when building with W=1 optionChristophe Kerello1-61/+29
commit b410f4eb01a1950ed73ae40859d0978b1a924380 upstream. This patch solves warnings detected by setting W=1 when building. Warnings type detected: drivers/mtd/nand/raw/stm32_fmc2_nand.c: In function ‘stm32_fmc2_calc_timings’: drivers/mtd/nand/raw/stm32_fmc2_nand.c:1417:23: warning: comparison is always false due to limited range of data type [-Wtype-limits] else if (tims->twait > FMC2_PMEM_PATT_TIMING_MASK) Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Cc: stable@vger.kernel.org Fixes: 2cd457f328c1 ("mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driver") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-10-01mtd: cfi_cmdset_0002: Use chip_good() to retry in do_write_oneword()Tokunori Ikegami1-6/+12
commit 37c673ade35c707d50583b5b25091ff8ebdeafd7 upstream. As reported by the OpenWRT team, write requests sometimes fail on some platforms. Currently to check the state chip_ready() is used correctly as described by the flash memory S29GL256P11TFI01 datasheet. Also chip_good() is used to check if the write is succeeded and it was implemented by the commit fb4a90bfcd6d8 ("[MTD] CFI-0002 - Improve error checking"). But actually the write failure is caused on some platforms and also it can be fixed by using chip_good() to check the state and retry instead. Also it seems that it is caused after repeated about 1,000 times to retry the write one word with the reset command. By using chip_good() to check the state to be done it can be reduced the retry with reset. It is depended on the actual flash chip behavior so the root cause is unknown. Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Joakim Tjernlund <Joakim.Tjernlund@infinera.com> Cc: linux-mtd@lists.infradead.org Cc: stable@vger.kernel.org Reported-by: Fabio Bettoni <fbettoni@gmail.com> Signed-off-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Tokunori Ikegami <ikegami.t@gmail.com> [vigneshr@ti.com: Fix a checkpatch warning] Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-30mtd: spi-nor: aspeed: Disable zero size segments on the AST2600Cédric Le Goater1-2/+6
A disabled segment for a CS should have a zero value in its segment register. The driver was generating an incorrect value which overlapped with segment CS0. Accesses to the flash were blocked and Linux hung. OpenBMC-Staging-Count: 1 Fixes: 3635b880313a ("mtd: spi-nor: aspeed: add initial support for ast2600") Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-30mtd: spi-nor: aspeed: fix training of multiple CS on the AST2600Cédric Le Goater1-4/+5
Each CE has its own read timing compensation register. OpenBMC-Staging-Count: 1 Fixes: c62871befcdb ("mtd: spi-nor: aspeed: add support for AST2600 training") Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-26mtd: spi-nor: aspeed: add support for AST2600 trainingCédric Le Goater1-0/+68
The training consists of finding the appropriate read timing delays for the HCLK dividers 2, 3, 4, and 5 and store the results in the Read Timing Compensation register. The previous SoC AST2500 and AST2400 were covering a broader HCLK range [ 1 - 5 ] because the AHB frequency was lower. The algorithm first reads a golden buffer at low speed and then performs reads with different clocks and delay cycles settings to find a breaking point. This selects the default clock frequency for the CEx control register. The current settings are bit optimistic as we pick the first delay giving good results. A safer approach would be to determine an interval and choose the middle value. We might change the approach depending on the results on other systems. Only CS0 is taken into account for the moment. OpenBMC-Staging-Count: 1 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-26mtd: spi-nor: aspeed: check upper freq limit when doing trainingCédric Le Goater1-1/+1
OpenBMC-Staging-Count: 1 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-26mtd: spi-nor: aspeed: Introduce a HCLK mask for trainingCédric Le Goater1-1/+6
The AST2600 handles more HCLK divisors than its predecessors. OpenBMC-Staging-Count: 1 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-26mtd: spi-nor: aspeed: Introduce training operations per platformCédric Le Goater1-4/+22
The read timing compensation register is different on the AST2600 and training will be slightly more complex. OpenBMC-Staging-Count: 1 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-26mtd: spi-nor: aspeed: Check for disabled segments on the AST2600Cédric Le Goater1-4/+11
The segments can be disabled on the AST2600 (zero register value). CS0 is open by default but not the other CS. This is closing the access to the flash device in user mode and forbids scanning. For multiple CS, we will need firmware or a DT property to reopen the flash AHB window. OpenBMC-Staging-Count: 1 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-26mtd: spi-nor: aspeed: add initial support for ast2600Cédric Le Goater1-0/+73
The Segment Registers of the AST2600 have a different encoding. A 1MB unit is used and the address range of a flash SPI slave is encoded with offsets in the overall controller window. The previous SoC AST2400 and AST2500 used absolute addresses. Only bits [27:20] are relevant and the end address is an upper bound limit. SPI training yet to come. OpenBMC-Staging-Count: 1 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-26mtd: spi-nor: aspeed: Introduce segment operationsCédric Le Goater1-20/+56
AST2600 will use a different encoding for the addresses defined in the Segment Register. OpenBMC-Staging-Count: 1 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-26mtd: spi-nor: aspeed: Introduce a field for the AHB physical addressCédric Le Goater1-12/+6
On the AST2600, we will use it to compute the address of the chip AHB window from the Segment Register value. It also removes the need of aspeed_smc_ahb_base_phy() helper. OpenBMC-Staging-Count: 1 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-26mtd: spi-nor: Add support for w25q512jvCédric Le Goater1-0/+2
OpenBMC-Staging-Count: 1 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16mtd: spi-nor: aspeed: add support for the 4B opcodesCédric Le Goater1-2/+9
Switch the default controller value to use the read mode in order to customize the command and use SPINOR_OP_READ_4B (0x13) when the chip supports 4B opcodes. OpenBMC-Staging-Count: 4 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2019-09-16mtd: spi-nor: aspeed: use memcpy_fromio() to capture the optimization bufferCédric Le Goater1-4/+2
aspeed_smc_read_from_ahb() only reads the first word which is not what we want. We want to capture a CALIBRATE_BUF_SIZE size window of the flash contents to optimize the read. OpenBMC-Staging-Count: 4 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2019-09-16mtd: spi-nor: aspeed: clarify 4BYTE address mode maskCédric Le Goater1-1/+9
OpenBMC-Staging-Count: 4 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2019-09-16mtd: spi-nor: aspeed: introduce a aspeed_smc_default_read() helperCédric Le Goater1-7/+12
OpenBMC-Staging-Count: 4 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2019-09-16mtd: spi-nor: fix options for mx66l51235fAlexander Amelkin1-1/+1
Currently in driver spi-nor there is a line for mx66l51235l. According to Macronix site there is no such part number. The chip detected as such is actually mx66l51235f. According to the datasheet for mx66l51235f, "The device default is in 24-bit address mode" (section 9-10). Hence we removed SPI_NOR_4B_OPCODES option with this commit. OpenBMC-Staging-Count: 7 Fixes: d342b6a973af ("mtd: spi-nor: enable 4B opcodes for mx66l51235l") Signed-off-by: Alexander Soldatov <a.soldatov@yadro.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Lei YU <mine260309@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16mtd: spi-nor: aspeed: limit the maximum SPI frequencyCédric Le Goater1-4/+13
The optimize read algo can choose a 100MHz SPI frequency which might be a bit too high for dual output IO on some chips, for the W25Q256 on palmetto for instance. The MX66L1G45G on witherspoon should be fine though. Also, the second chip of the FMC controller does not get any optimize settings for reads. Only the first is configured by U-Boot. To fix these two issues, we introduce a "spi-max-frequency" property in the device tree which will be used to cap the optimize read algorithm and we run the algo on the FMC controller chips as well. By default, the frequency setting is 50MHz. OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16mtd: spi-nor: aspeed: optimize read modeCédric Le Goater1-0/+191
This is only for SPI controllers as U-Boot should have done it already for the FMC controller using DMAs. The algo is based on the one found in the OpenPOWER pflash tool. It first reads a golden buffer at low speed and then performs reads with different clocks and delay cycles settings to find the fastest configuration for the chip. It can be deactivated at boot time with the kernel parameter : aspeed_smc.optimize_read=0 OpenBMC-Staging-Count: 8 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Alexander Soldatov <a.soldatov@yadro.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16mtd: spi-nor: aspeed: link controller with the ahb clockCédric Le Goater1-0/+10
We will need the AHB frequency to set the HCLK settings in the SMC controller to optimize the reads. OpenBMC-Staging-Count: 8 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16mtd: spi-nor: aspeed: add support for SPI dual IO read modeCédric Le Goater1-11/+43
Implements support for the dual IO read mode on aspeed SMC/FMC controllers which uses both MISO and MOSI lines for data during a read to double the read bandwidth. Still to be done SNOR_PROTO_1_2_2 Based on work from Robert Lippert <roblip@gmail.com> OpenBMC-Staging-Count: 8 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-09-16mtd: spi-nor: aspeed: use command mode for readsCédric Le Goater1-1/+27
When reading flash contents, try to use the "command mode" if the AHB window configured for the flash module is big enough. Else, just fall back to the "user mode" to perform the read. OpenBMC-Staging-Count: 8 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-08-29mtd: hyperbus: fix dependency and build errorRandy Dunlap1-0/+1
lib/devres.c, which implements devm_ioremap_resource(), is only built when CONFIG_HAS_IOMEM is set/enabled, so MTD_HYPERBUS should depend on HAS_IOMEM. Fixes a build error and a Kconfig warning (as seen on UML builds): WARNING: unmet direct dependencies detected for MTD_COMPLEX_MAPPINGS Depends on [n]: MTD [=m] && HAS_IOMEM [=n] Selected by [m]: - MTD_HYPERBUS [=m] && MTD [=m] ERROR: "devm_ioremap_resource" [drivers/mtd/hyperbus/hyperbus-core.ko] undefined! Fixes: dcc7d3446a0f ("mtd: Add support for HyperBus memory devices") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: linux-mtd@lists.infradead.org Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-08-22Merge tag 'Wimplicit-fallthrough-5.3-rc6' of ↵Linus Torvalds1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/gustavoars/linux Pull more fallthrough fixes from Gustavo A. R. Silva: "Fix fall-through warnings on arm and mips for multiple configurations" * tag 'Wimplicit-fallthrough-5.3-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gustavoars/linux: video: fbdev: acornfb: Mark expected switch fall-through scsi: libsas: sas_discover: Mark expected switch fall-through MIPS: Octeon: Mark expected switch fall-through power: supply: ab8500_charger: Mark expected switch fall-through watchdog: wdt285: Mark expected switch fall-through mtd: sa1100: Mark expected switch fall-through drm/sun4i: tcon: Mark expected switch fall-through drm/sun4i: sun6i_mipi_dsi: Mark expected switch fall-through ARM: riscpc: Mark expected switch fall-through dmaengine: fsldma: Mark expected switch fall-through
2019-08-21mtd: sa1100: Mark expected switch fall-throughGustavo A. R. Silva1-0/+1
Mark switch cases where we are expecting to fall through. Fix the following warning (Building: assabet_defconfig arm): drivers/mtd/maps/sa1100-flash.c: In function ‘sa1100_probe_subdev’: drivers/mtd/maps/sa1100-flash.c:82:3: warning: this statement may fall through [-Wimplicit-fallthrough=] printk(KERN_WARNING "SA1100 flash: unknown base address " ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ "0x%08lx, assuming CS0\n", phys); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/mtd/maps/sa1100-flash.c:85:2: note: here case SA1100_CS0_PHYS: ^~~~ Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
2019-08-13mtd: spi-nor: Fix the disabling of write protection at initTudor Ambarus1-2/+3
spi_nor_spansion_clear_sr_bp() depends on spansion_quad_enable(). While spansion_quad_enable() is selected as default when initializing the flash parameters, the nor->quad_enable() method can be overwritten later on when parsing BFPT. Select the write protection disable mechanism at spi_nor_init() time, when the nor->quad_enable() method is already known. Fixes: 191f5c2ed4b6faba ("mtd: spi-nor: use 16-bit WRR command when QE is set on spansion flashes") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2019-08-05Merge tag 'mtd/fixes-for-5.3-rc3' of ↵Linus Torvalds2-4/+13
git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD fixes from Miquel Raynal: "NAND: - Fix Micron driver as some chips enable internal ECC correction during their discovery while they advertize they do not have any. Hyperbus: - Restrict the build to only ARM64 SoCs (and compile testing) which is what should have been done since the beginning. - Fix Kconfig issue by selection something instead of implying it" * tag 'mtd/fixes-for-5.3-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: mtd: hyperbus: Add hardware dependency to AM654 driver mtd: hyperbus: Kconfig: Fix HBMC_AM654 dependencies mtd: rawnand: micron: handle on-die "ECC-off" devices correctly
2019-08-03mtd: hyperbus: Add hardware dependency to AM654 driverJean Delvare1-0/+1
The hbmc-am654 driver is for the TI AM654, which is an ARM64 SoC, so don't propose this driver on other architectures unless build-testing. Fixes: b07079f1642c ("mtd: hyperbus: Add driver for TI's HyperBus memory controller") Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-08-03mtd: hyperbus: Kconfig: Fix HBMC_AM654 dependenciesVignesh Raghavendra1-1/+1
On x86_64, when CONFIG_OF is not disabled: WARNING: unmet direct dependencies detected for MUX_MMIO Depends on [n]: MULTIPLEXER [=y] && (OF [=n] || COMPILE_TEST [=n]) Selected by [y]: - HBMC_AM654 [=y] && MTD [=y] && MTD_HYPERBUS [=y] due to config HBMC_AM654 tristate "HyperBus controller driver for AM65x SoC" select MULTIPLEXER select MUX_MMIO Fix this by making HBMC_AM654 imply MUX_MMIO instead of select so that dependencies are taken care of. MUX_MMIO is optional for functioning of driver. Fixes: b07079f1642c ("mtd: hyperbus: Add driver for TI's HyperBus memory controller") Reported-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-08-03mtd: rawnand: micron: handle on-die "ECC-off" devices correctlyMarco Felsch1-3/+11
Some devices are not supposed to support on-die ECC but experience shows that internal ECC machinery can actually be enabled through the "SET FEATURE (EFh)" command, even if a read of the "READ ID Parameter Tables" returns that it is not. Currently, the driver checks the "READ ID Parameter" field directly after having enabled the feature. If the check fails it returns immediately but leaves the ECC on. When using buggy chips like MT29F2G08ABAGA and MT29F2G08ABBGA, all future read/program cycles will go through the on-die ECC, confusing the host controller which is supposed to be the one handling correction. To address this in a common way we need to turn off the on-die ECC directly after reading the "READ ID Parameter" and before checking the "ECC status". Cc: stable@vger.kernel.org Fixes: dbc44edbf833 ("mtd: rawnand: micron: Fix on-die ECC detection logic") Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-07-26mtd: onenand_base: Mark expected switch fall-throughGustavo A. R. Silva1-0/+1
In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. This patch fixes the following warning: drivers/mtd/nand/onenand/onenand_base.c: In function ‘onenand_check_features’: drivers/mtd/nand/onenand/onenand_base.c:3264:17: warning: this statement may fall through [-Wimplicit-fallthrough=] this->options |= ONENAND_HAS_NOP_1; drivers/mtd/nand/onenand/onenand_base.c:3265:2: note: here case ONENAND_DEVICE_DENSITY_4Gb: ^~~~ Warning level 3 was used: -Wimplicit-fallthrough=3 This patch is part of the ongoing efforts to enable -Wimplicit-fallthrough. Cc: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
2019-07-15docs: mtd: move it to the driver-api bookMauro Carvalho Chehab1-1/+1
While I was tempted to move it to admin-guide, as some docs there are more userspace-faced, there are some very technical discussions about memory error correction code from the Kernel implementer's PoV. So, let's place it inside the driver-api book. Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
2019-07-15docs: mtd: convert to ReSTMauro Carvalho Chehab1-1/+1
Rename the mtd documentation files to ReST, add an index for them and adjust in order to produce a nice html output via the Sphinx build system. It should be noticed that Sphinx doesn't handle very well URLs with dots in the middle. Thankfully, internally, the '.' char is translated to %2E, so we can jus use %2E instead of dots, and this will work fine on both text and processed files. At its new index.rst, let's add a :orphan: while this is not linked to the main index.rst file, in order to avoid build warnings. Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
2019-07-14Merge tag 'mtd/for-5.3' of ↵Linus Torvalds34-2427/+2334
git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD updates from Miquel Raynal: "This contains the following changes for MTD: MTD core changes: - New Hyperbus framework - New _is_locked (concat) implementation - Various cleanups NAND core changes: - use longest matching pattern in ->exec_op() default parser - export NAND operation tracer - add flag to indicate panic_write in MTD - use kzalloc() instead of kmalloc() and memset() Raw NAND controller drivers changes: - brcmnand: - fix BCH ECC layout for large page NAND parts - fallback to detected ecc-strength, ecc-step-size - when oops in progress use pio and interrupt polling - code refactor code to introduce helper functions - add support for v7.3 controller - FSMC: - use nand_op_trace for operation tracing - GPMI: - move all driver code into single file - various cleanups (including dmaengine changes) - use runtime PM to manage clocks - implement exec_op - MTK: - correct low level time calculation of r/w cycle - improve data sampling timing for read cycle - add validity check for CE# pin setting - fix wrongly assigned OOB buffer pointer issue - re-license MTK NAND driver as Dual MIT/GPL - STM32: - manage the get_irq error case - increase DMA completion timeouts Raw NAND chips drivers changes: - Macronix: add read-retry support Onenand driver changes: - add support for 8Gb datasize chips - avoid fall-through warnings SPI-NAND changes: - define macros for page-read ops with three-byte addresses - add support for two-byte device IDs and then for GigaDevice GD5F1GQ4UFxxG - add initial support for Paragon PN26G0xA - handle the case where the last page read has bitflips SPI-NOR core changes: - add support for the mt25ql02g and w25q16jv flashes - print error in case of jedec read id fails - is25lp256: add post BFPT fix to correct the addr_width SPI NOR controller drivers changes: - intel-spi: Add support for Intel Elkhart Lake SPI serial flash - smt32: remove the driver as the driver was replaced by spi-stm32-qspi.c - cadence-quadspi: add reset control" * tag 'mtd/for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (60 commits) mtd: concat: implement _is_locked mtd operation mtd: concat: refactor concat_lock/concat_unlock mtd: abi: do not use C++ style comments in uapi header mtd: afs: remove unneeded NULL check mtd: rawnand: stm32_fmc2: increase DMA completion timeouts mtd: rawnand: Use kzalloc() instead of kmalloc() and memset() mtd: hyperbus: Add driver for TI's HyperBus memory controller mtd: spinand: read returns badly if the last page has bitflips mtd: spinand: Add initial support for Paragon PN26G0xA mtd: rawnand: mtk: Re-license MTK NAND driver as Dual MIT/GPL mtd: rawnand: gpmi: remove double assignment to block_size dt-bindings: mtd: brcmnand: Add brcmnand, brcmnand-v7.3 support mtd: rawnand: brcmnand: Add support for v7.3 controller mtd: rawnand: brcmnand: Refactored code to introduce helper functions mtd: rawnand: brcmnand: When oops in progress use pio and interrupt polling mtd: Add flag to indicate panic_write mtd: rawnand: Add Macronix NAND read retry support mtd: onenand: Avoid fall-through warnings mtd: spinand: Add support for GigaDevice GD5F1GQ4UFxxG mtd: spinand: Add support for two-byte device IDs ...
2019-07-09Merge tag 'docs-5.3' of git://git.lwn.net/linuxLinus Torvalds1-1/+1
Pull Documentation updates from Jonathan Corbet: "It's been a relatively busy cycle for docs: - A fair pile of RST conversions, many from Mauro. These create more than the usual number of simple but annoying merge conflicts with other trees, unfortunately. He has a lot more of these waiting on the wings that, I think, will go to you directly later on. - A new document on how to use merges and rebases in kernel repos, and one on Spectre vulnerabilities. - Various improvements to the build system, including automatic markup of function() references because some people, for reasons I will never understand, were of the opinion that :c:func:``function()`` is unattractive and not fun to type. - We now recommend using sphinx 1.7, but still support back to 1.4. - Lots of smaller improvements, warning fixes, typo fixes, etc" * tag 'docs-5.3' of git://git.lwn.net/linux: (129 commits) docs: automarkup.py: ignore exceptions when seeking for xrefs docs: Move binderfs to admin-guide Disable Sphinx SmartyPants in HTML output doc: RCU callback locks need only _bh, not necessarily _irq docs: format kernel-parameters -- as code Doc : doc-guide : Fix a typo platform: x86: get rid of a non-existent document Add the RCU docs to the core-api manual Documentation: RCU: Add TOC tree hooks Documentation: RCU: Rename txt files to rst Documentation: RCU: Convert RCU UP systems to reST Documentation: RCU: Convert RCU linked list to reST Documentation: RCU: Convert RCU basic concepts to reST docs: filesystems: Remove uneeded .rst extension on toctables scripts/sphinx-pre-install: fix out-of-tree build docs: zh_CN: submitting-drivers.rst: Remove a duplicated Documentation/ Documentation: PGP: update for newer HW devices Documentation: Add section about CPU vulnerabilities for Spectre Documentation: platform: Delete x86-laptop-drivers.txt docs: Note that :c:func: should no longer be used ...
2019-07-07Merge tag 'spi-nor/for-5.3-v2' of ↵Miquel Raynal9-747/+60
gitolite.kernel.org:pub/scm/linux/kernel/git/mtd/linux into mtd/next SPI-NOR core changes: - add support for the mt25ql02g and w25q16jv flashes - print error in case of jedec read id fails - is25lp256: add post BFPT fix to correct the addr_width SPI NOR controller drivers changes: - intel-spi: Add support for Intel Elkhart Lake SPI serial flash - smt32: remove the driver as the driver was replaced by spi-stm32-qspi.c - cadence-quadspi: add reset control
2019-07-07mtd: concat: implement _is_locked mtd operationChris Packham1-0/+23
Add an implementation of the _is_locked operation for concatenated mtd devices. This doesn't handle getting the lock status of a range that spans chips, which is consistent with cfi_ppb_is_locked and cfi_intelext_is_locked which only look at the first block in the range. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Richard Weinberger <richard@nod.at>
2019-07-07mtd: concat: refactor concat_lock/concat_unlockChris Packham1-32/+12
concat_lock() and concat_unlock() only differed in terms of the mtd_xx operation they called. Refactor them to use a common helper function and pass a boolean flag to indicate whether lock or unlock is needed. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Richard Weinberger <richard@nod.at>
2019-07-07mtd: afs: remove unneeded NULL checkDing Xiang1-2/+1
NULL check before kfree is unneeded, so remove it. Signed-off-by: Ding Xiang <dingxiang@cmss.chinamobile.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2019-07-06Merge tag 'nand/for-5.3' of ↵Richard Weinberger136-2685/+1928
git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux into mtd/next NAND core changes: - use longest matching pattern in ->exec_op() default parser - export NAND operation tracer - add flag to indicate panic_write in MTD - use kzalloc() instead of kmalloc() and memset() Raw NAND controller drivers changes: - brcmnand: * fix BCH ECC layout for large page NAND parts * fallback to detected ecc-strength, ecc-step-size * when oops in progress use pio and interrupt polling * code refactor code to introduce helper functions * add support for v7.3 controller - FSMC: * use nand_op_trace for operation tracing - GPMI: * move all driver code into single file * various cleanups (including dmaengine changes) * use runtime PM to manage clocks * implement exec_op - MTK: * correct low level time calculation of r/w cycle * improve data sampling timing for read cycle * add validity check for CE# pin setting * fix wrongly assigned OOB buffer pointer issue * re-license MTK NAND driver as Dual MIT/GPL - STM32: * manage the get_irq error case * increase DMA completion timeouts Raw NAND chips drivers changes: - Macronix: add read-retry support Onenand driver changes: - add support for 8Gb datasize chips - avoid fall-through warnings SPI-NAND changes: - define macros for page-read ops with three-byte addresses - add support for two-byte device IDs and then for GigaDevice GD5F1GQ4UFxxG - add initial support for Paragon PN26G0xA - handle the case where the last page read has bitflips
2019-07-05mtd: rawnand: sunxi: Add A23/A33 DMA support with extra MBUS configurationMiquel Raynal1-0/+24
Allwinner NAND controllers can make use of DMA to enhance the I/O throughput thanks to ECC pipelining. DMA handling with A23/A33 NAND IP is a bit different than with the older SoCs, hence the introduction of a new compatible to handle: * the differences between register offsets, * the burst length change from 4 to minimum 8, * manage SRAM accesses through MBUS with extra configuration. Fixes: c49836f05aa1 ("mtd: rawnand: sunxi: Add A23/A33 DMA support") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-07-05Revert "mtd: rawnand: sunxi: Add A23/A33 DMA support"Miquel Raynal1-36/+2
This reverts commit c49836f05aa15282f7280e06ede3f6f8a6324833. The commit is wrong and its approach actually does not work. Let's revert it in order to add the feature with a clean patch. Fixes: c49836f05aa1 ("mtd: rawnand: sunxi: Add A23/A33 DMA support") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-07-01mtd: rawnand: ingenic: Fix ingenic_ecc dependencyPaul Cercueil4-11/+4
If MTD_NAND_JZ4780 is y and MTD_NAND_JZ4780_BCH is m, which select CONFIG_MTD_NAND_INGENIC_ECC to m, building fails: drivers/mtd/nand/raw/ingenic/ingenic_nand.o: In function `ingenic_nand_remove': ingenic_nand.c:(.text+0x177): undefined reference to `ingenic_ecc_release' drivers/mtd/nand/raw/ingenic/ingenic_nand.o: In function `ingenic_nand_ecc_correct': ingenic_nand.c:(.text+0x2ee): undefined reference to `ingenic_ecc_correct' To fix that, the ingenic_nand and ingenic_ecc modules have been fused into one single module. - The ingenic_ecc.c code is now compiled in only if $(CONFIG_MTD_NAND_INGENIC_ECC) is set. This is now a boolean instead of tristate. - To avoid changing the module name, the ingenic_nand.c file is moved to ingenic_nand_drv.c. Then the module name is still ingenic_nand. - Since ingenic_ecc.c is no more a module, the module-specific macros have been dropped, and the functions are no more exported for use by the ingenic_nand driver. Fixes: 15de8c6efd0e ("mtd: rawnand: ingenic: Separate top-level and SoC specific code") Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reported-by: Arnd Bergmann <arnd@arndb.de> Reported-by: Hulk Robot <hulkci@huawei.com> Cc: YueHaibing <yuehaibing@huawei.com> Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-07-01mtd: spinand: Fix max_bad_eraseblocks_per_lun info in memorgFrieder Schrempf2-3/+3
The 1Gb Macronix chip can have a maximum of 20 bad blocks, while the 2Gb version has twice as many blocks and therefore the maximum number of bad blocks is 40. The 4Gb GigaDevice GD5F4GQ4xA has twice as many blocks as its 2Gb counterpart and therefore a maximum of 80 bad blocks. Fixes: 377e517b5fa5 ("mtd: nand: Add max_bad_eraseblocks_per_lun info to memorg") Reported-by: Emil Lenngren <emil.lenngren@gmail.com> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-06-28mtd: rawnand: stm32_fmc2: increase DMA completion timeoutsAmelie Delaunay1-6/+9
When the system is overloaded, DMA data transfer completion occurs after 100ms. Increase the timeouts to let it the time to complete. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-06-28mtd: rawnand: Use kzalloc() instead of kmalloc() and memset()Fuqian Huang1-2/+1
Replace kmalloc() by a memset() followed with a kzalloc(). There is a recommendation to use zeroing allocator rather than allocator followed by memset(0) in ./scripts/coccinelle/api/alloc/zalloc-simple.cocci Signed-off-by: Fuqian Huang <huangfq.daxian@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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