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2014-11-19amdkfd: Instead of using get function, use container_ofAlexey Skidanov2-12/+11
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alexey Skidanov <Alexey.Skidanov@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
2014-11-17amdkfd: use schedule() in sync_with_hwOded Gabbay1-1/+2
amdkfd uses cpu_relax() in its sync_with_hw() function. Because cpu_relax() is defined as 'REP; NOP' on x86_64, it will block the CPU from servicing IOMMU PPR requests. This may cause a deadlock, because sync_with_hw() won't be completed until the PPR request has been served. Therefore, we need to use schedule() instead of cpu_relax() as it is the minimum requirement to allow other threads to execute. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
2014-11-20amdkfd: Fix memory leak on process deregistrationJay Cornwall1-0/+1
struct device_process_node was allocated during process registration but not released at process deregistration. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
2014-11-20amdkfd: add __iomem attribute to doorbell_ptrOded Gabbay2-6/+5
This patch was done due to sparse warning. It changes the definition of doorbell_ptr in queue_properties to be with __iomem attribute, so it would match the type which the doorbell module functions are returning. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
2014-11-20amdkfd: fence_wait_timeout() can be staticOded Gabbay1-2/+3
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
2014-11-20amdkfd: is_occupied() can be staticOded Gabbay1-3/+3
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
2014-11-20amdkfd: Fix sparse warnings in kfd_flat_memory.cOded Gabbay1-5/+6
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
2014-11-20amdkfd: pqm_get_kernel_queue() can be statickbuild test robot1-1/+2
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
2014-11-20amdkfd: test_kq() can be statickbuild test robot1-1/+1
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
2014-11-20amdkfd: Fix sparse warnings in kfd_topology.cOded Gabbay1-20/+20
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
2014-11-20amdkfd: Fix sparse warnings in kfd_chardev.cOded Gabbay1-4/+12
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
2014-11-09amdkfd: Display MEC fw version in topology nodeOded Gabbay1-2/+6
This patch displays the firmware version of the microcode that is currently running in the MEC. This is needed for the HSA RT, so it could differentiate its behavior based on fw version. e.g. workarounds for bugs in fw v2: Send the KGD_ENGINE_MEC1 as a parameter to the get_fw_version() Signed-off-by: Oded Gabbay <oded.gabbay@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-11-09drm/radeon: Add implementation of get_fw_versionOded Gabbay1-0/+53
This patch implements a new interface that was added to the kfd-->kgd interface. The new interface function retrieves the firmware version that is currently in use by a specific engine. The firmware was uploaded to the engine by the radeon driver. v2: Returns the fw version of the specific engine, as passed into the function by a new parameter Signed-off-by: Oded Gabbay <oded.gabbay@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-11-09drm/amd: Add get_fw_version to kfd-->kgd interfaceOded Gabbay1-0/+15
This patch adds a new interface to the kfd-->kgd interface. The new interface function retrieves the firmware version that is currently in use by the MEC engine. The firmware was uploaded to the MEC engine by the kgd (radeon). v2: Added parameter of engine type to interface function Signed-off-by: Oded Gabbay <oded.gabbay@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-11-07drm/i915: Update DRIVER_DATE to 20141107Daniel Vetter1-1/+1
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915: Add gen to the gpu hang ecodeMika Kuoppala1-1/+2
for the Brothers in Triage Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915: Cache HPLL frequency on VLV/CHVVille Syrjälä2-7/+8
We need the HPLL frequency when calculating cdclk. Currently we read that out from the hardware every single time, which isn't going to fly very well if the device is runtime suspended. So cache the HPLL frequency in dev_priv and use the cached value. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reference: https://bugs.freedesktop.org/show_bug.cgi?id=82939 Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07Revert "drm/i915/vlv: Remove check for Old Ack during forcewake"Mika Kuoppala1-7/+10
This reverts commit 5cb13c07dae73380d8b3ddc792740487b8742938. While the relevance for WaRsDontPollForAckOnClearingFWBits is under investigation, revert this as regression. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85684 Tested-by: Tested-by: lu hua <huax.lu@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: S, Deepak <deepak.s@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915: Make mmio flip wait for seqno in the work functionAnder Conselvan de Oliveira3-90/+12
This simplifies the code quite a bit compared to iterating over all rings during the ring interrupt. Also, it allows us to drop the mmio_flip spinlock, since the mmio_flip struct is only accessed in two places. The first is when the flip is queued and the other when the mmio writes are done. Since a flip cannot be queued while there is a pending flip, the two paths shouldn't ever run in parallel. We might need to revisit that if support for replacing flips is implemented though. v2: Don't hold dev->struct_mutext while waiting (Chris) v3: Make the wait uninterruptable (Chris) Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915: Make __wait_seqno non-static and rename to __i915_wait_seqnoAnder Conselvan de Oliveira2-9/+16
So that it can be used by the flip code to wait for rendering without holding any locks. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915: Move the .global_resources() hook call into ↵Ville Syrjälä1-21/+4
modeset_update_crtc_power_domains() We may need to access various hardware bits in the .global_resources() hook, so move the call to occur after enabling all the newly required power wells, but before disabling all the now unneeded wells. This should guarantee that we have all the sufficient hardware resources available during the .global_resources() call. And if not, any additional resources must be explicitly acquired by the .global_resorces() hook. For instance on VLV/CHV we need to access the gunit mailbox so that we can talk to punit/cck over sideband. In addition some PFI credit reprogramming may need to be addes as well, which may require the disp2d well. This should also make the power domain refcounts consistent on platforms which don't have a .global_resource() hook since now they too will call modeset_update_crtc_power_domains() which will drop the init power. Previously init power was just left enabled for such platforms. Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/audio: add DOC comment describing HDA over HDMI/DPJani Nikula1-0/+21
v2: include the section in the drm docbook. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915: make pipe/port based audio valid accessors easier to useJani Nikula3-27/+17
Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/audio: add audio codec enable debug log for g4xJani Nikula1-0/+2
Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/audio: add audio codec disable on g4xJani Nikula1-0/+20
This not based on any documentation... Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915: enable audio codec after portJani Nikula2-13/+15
As per spec, and similar to DDI. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/audio: add vlv/chv/gen5-7 audio codec disable sequenceJani Nikula3-0/+60
Add support for disabling the audio codec on vlv/chv/gen5-7, similar to hsw/bdw. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/audio: rewrite vlv/chv and gen 5-7 audio codec enable sequenceJani Nikula1-32/+31
Similar to the hsw/bdw enable sequence rewrite. v3: replace vblank wait with a comment v4: expand the comment on what should be done with the vblank wait Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/skl: Enable Gen9 RC6Zhe Wang1-1/+51
Configure and enable RC6 for Gen9. v2: Rebase on top of BDW rc6 support (Damien) Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Zhe Wang <zhe1.wang@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/skl: Gen9 ForcewakeZhe Wang3-2/+184
Implement common forcewake functions shared by Gen9 features. v2: Make the focewake_{get,put} functions static (Mika) Small coding style fix in the function definition (Damien) Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Zhe Wang <zhe1.wang@intel.com> (v1) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v2) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/skl: Log the order in which we flush the pipes in the WM codeDamien Lespiau1-4/+7
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/skl: Flush the WM configurationDamien Lespiau1-0/+135
When we write new values for the DDB allocation and WM parameters, we now need to trigger the double buffer update for the pipe to take the new configuration into account. As the DDB is a global resource shared between planes, enabling or disabling one plane will result in changes for all planes that are currently in use, thus the need write PLANE_SURF/CUR_BASE for more than the plane we're touching. v2: Don't wait for pipes that are off v3: Split the staging results structure to not exceed the 1Kb stack allocation in skl_update_wm() v4: Rework and document the algorithm after Ville found that it was all wrong. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/skl: Stage the pipe DDB allocationDamien Lespiau2-7/+8
To correctly flush the new DDB allocation we need to know about the pipe allocation layout inside the DDB in order to sequence the re-allocation to not cause a newly allocated pipe to fetch from a space that was previously allocated to another pipe. This patch preserves the per-pipe (start,end) allocation to be used in the flush. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/skl: Reduce the indentation level in skl_write_wm_values()Damien Lespiau1-21/+21
We can reduce the indentation level by continuing early. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/skl: Correctly align skl_compute_plane_wm() argumentsDamien Lespiau1-5/+5
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/skl: Rework when the transition WMs are computedDamien Lespiau1-15/+31
The transition WMs code was doing a shortcut and the values were copied from the WM0 ones at compute_wm_results() time. Going forward, we want to compute them like the other WMs and resolve their final register values in the same way as well. This patch does just that and isolate the transtion WM compute code in skl_compute_transition_wm() while skl_compute_wm_results() takes care of the register values. We also take the opportunity to disable the transition WMs for now. We've noticed underruns and they seem to be the culprit. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/skl: Move all the WM compute functions in one placeDamien Lespiau1-22/+22
The DDB allocation code managed to split in two the compute functions. Bring back skl_compute_transition_wm() and skl_compute_linetime_wm() with their little friends. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/skl: Reduce the number of holes in struct skl_wm_levelDamien Lespiau1-1/+1
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/skl: Make res_blocks/lines intermediate values 32 bitsDamien Lespiau1-16/+11
To align with the ilk WM code and because it makes sense to test against the upper bounds as soon as possible on variables that are bigger than the number of bits in the register, let's move the maximum checks from skl_compute_wm_results() to skl_compute_plane_wm(). v2: Leave the result values to 0 when overflowing the limits (Ville) Use 32 bits intermediate variables (Damien) Instead of using the 16 and 8 bits space we have in the result structure, use 32 bits local variables until we're sure they fit into the constraints. Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/skl: Use a more descriptive parameter name in skl_compute_plane_wm()Damien Lespiau1-2/+2
What we're talking about here is the DDB allocation (in blocks). That's more descriptive than 'max_page_buff_alloc'. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/skl: Make 'end' of the DDB allocation entry exclusiveDamien Lespiau2-15/+21
Ville suggested that we should use the same semantics as C arrays to reduce the number of those pesky +1/-1 in the allocation code. This patch leaves the debugfs file as is, showing the internal DDB allocation structure, not the values written in the registers. v2: Remove the test on ->end in skl_ddb_entry_size() (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/skl: Check the DDB state at modesetDamien Lespiau4-2/+64
v2: Don't check DDB on pre-SKL platforms Don't check DDB state on disabled pipes v3: Squash "Expose skl_ddb_get_hw_state()" Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/skl: Add a debugfs file to dump the DDB allocationDamien Lespiau1-0/+37
v2: minor conflict in i915_debugfs.c v3: Rebase on top of the for_each_pipe() change adding dev_priv as first argument. v4: minor conflict in the i915_debugfs_files array v5: minor conflict in the i915_debugfs_files array Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/skl: Augment the latency debugfs files for SKLDamien Lespiau1-14/+62
v2: Use the gen >= 9 in the debugfs file condition (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/skl: Read back the DDB allocation hw stateDamien Lespiau1-0/+29
This logically belongs to the WM state, so do it there. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/skl: Store the new WM state at the very end of the updateDamien Lespiau1-2/+3
We're going to add a new step, let's not hide the copy of the new WM state inside one inner function, but as a 1st level operation in the WM update. v2: Split the staging results structure to not exceed the 1Kb stack allocation in skl_update_wm() Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/gen9: Disable WM if corresponding latency is 0Vandana Kannan1-2/+12
According to updated BSpec, If level 1 or any higher level has a value of 0x00, that level and any higher levels are unused and the associated watermark registers must not be enabled. This patch checks for latency 0 for level >=1 and does not enable WM corresponding to level m | m>=n, if level n (n != 0) has a 0us latency. v2: Satheesh's review comments - zero-out latency values (for all higher levels if latency of given level is zero ) in read_wm_latency() function itself v3: removed redundant check as per Satheesh's observation. v4: rebase on top before merging (Damien) v5: Rebase on top of the default value removal (Ville) Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v3) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/gen9: Add 2us read latency to WM levelVandana Kannan1-0/+16
According to the updated Bspec, The mailbox response data is not currently accounting for memory read latency. Add 2 microseconds to the result for each level. This patch adds 2us to latency of level 0 for all cases and for all other levels (1-7) only if latency[level] > 0. v2: Slightly rework the patch and add a big comment (Damien) v3: Rebase on top of the renames of the memory latency defines Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v1) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v2) Reviewed-by: M, Satheeshakrishna <satheeshakrishna.m@intel.com> (v1) Cc: Lespiau, Damien <damien.lespiau@intel.com> Cc: M, Satheeshakrishna <satheeshakrishna.m@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/skl: Read the pipe WM HW statePradeep Bhat3-1/+108
This patch provides the implementation for reading the pipe wm HW state. v2: Incorporated Damien's review comments and also made modifications to incorporate the plane/cursor split. v3: No need to ident a line that was fitting 80 chars Return early instead of indenting the remaining of a function (Damien) v4: Rebase on top of nightly (minor conflict in intel_drv.h) v5: Rebase on top of nightly (minor conflict in intel_drv.h) v6: Rebase on top of nightly (minor conflict in intel_drv.h) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-07drm/i915/skl: Program the DDB allocationDamien Lespiau2-0/+25
v2: Adapt to the planes/cursor split Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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