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path: root/drivers/gpu
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2018-12-10drm/amdgpu: remove set but not used variable 'grbm_soft_reset'YueHaibing1-4/+2
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c: In function 'gfx_v8_0_pre_soft_reset': drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c:4950:27: warning: variable 'srbm_soft_reset' set but not used [-Wunused-but-set-variable] drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c: In function 'gfx_v8_0_post_soft_reset': drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c:5054:27: warning: variable 'srbm_soft_reset' set but not used [-Wunused-but-set-variable] It never used since introduction in commit d31a501ead7f ("drm/amdgpu: add pre_soft_reset ip func") and e4ae0fc33631 ("drm/amdgpu: implement gfx8 post_soft_reset") Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-10drm/amdgpu: Limit vm max ctx number to 4096Rex Zhu2-1/+2
driver need to reserve resource for each ctx for some hw features. so add this limitation. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-10drm/amdgpu: bypass RLC init under sriov for Tonga (v2)Tiecheng Zhou1-0/+5
RLC will go wrong in soft_reset under sriov Workaroound: only need to init RLC csb, and skip RLC stop, reset, start this is because host-driver has already done full initialization on RLC v2: squash in build fix Signed-off-by: Tiecehng Zhou <Tiecheng.Zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-08drm/amdgpu: move IV prescreening into the GMC codeChristian König9-154/+59
The GMC/VM subsystem is causing the faults, so move the handling here as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-08drm/amdgpu: remove VM fault_credit handlingChristian König7-115/+6
printk_ratelimit() is much better suited to limit the number of reported VM faults. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-08drm/amdgpu: send IVs to the KFD only after processing them v3Christian König1-21/+17
This allows us to filter out VM faults in the GMC code. v2: don't filter out all faults v3: fix copy&paste typo, send all IV to the KFD, don't change message level Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-08drm/amdkfd: Add support for doorbell BOsFelix Kuehling3-7/+62
This allows user mode to map doorbell pages into GPUVM address space. That way GPUs can submit to user mode queues (self-dispatch). Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-08drm/amdkfd: Add DMABuf import functionalityFelix Kuehling8-4/+262
This is used for interoperability between ROCm compute and graphics APIs. It allows importing graphics driver BOs into the ROCm SVM address space for zero-copy GPU access. The API is split into two steps (query and import) to allow user mode to manage the virtual address space allocation for the imported buffer. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-08drm/amdkfd: Add NULL-pointer checkFelix Kuehling1-1/+1
top_dev->gpu is NULL for CPUs. Avoid dereferencing it if NULL. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-08drm/amdgpu: Add KFD VRAM limit checkingFelix Kuehling5-54/+75
We don't want KFD processes evicting each other over VRAM usage. Therefore prevent overcommitting VRAM among KFD applications with a per-GPU limit. Also leave enough room for page tables on top of the application memory usage. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-08drm/amdgpu: Workaround build failure due to trace conflictKuehling, Felix4-1/+3
Avoid including mmu_context.h in amdgpu_amdkfd.h since that may be included in other header files that define traces. This leads to conflicts due to traces defined in other headers included via mmu_context.h. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-08drm/amd/powerplay: rv dal-pplib interface refactor powerplay parthersen wu6-9/+165
[WHY] clarify dal input parameters to pplib interface, remove un-used parameters. dal knows exactly which parameters needed and their effects at pplib and smu sides. current dal sequence for dcn1_update_clock to pplib: 1.smu10_display_clock_voltage_request for dcefclk 2.smu10_display_clock_voltage_request for fclk 3.phm_store_dal_configuration_data { set_min_deep_sleep_dcfclk set_active_display_count store_cc6_data --- this data never be referenced new sequence will be: 1. set_display_count --- need add new pplib interface 2. set_min_deep_sleep_dcfclk -- new pplib interface 3. set_hard_min_dcfclk_by_freq 4. set_hard_min_fclk_by_freq after this code refactor, smu10_display_clock_voltage_request, phm_store_dal_configuration_data will not be needed for rv. [HOW] step 1: add new functions at pplib interface step 2: add new functions at amdgpu dm and dc Signed-off-by: hersen wu <hersenxs.wu@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-08drm/amdgpu: Skip ring soft recovery when fence was NULLwentalou1-1/+1
amdgpu_ring_soft_recovery would have Call-Trace, when s_fence->parent was NULL inside amdgpu_job_timedout. Check fence first, as drm_sched_hw_job_reset did. Signed-off-by: Wentao Lou <Wentao.Lou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-08drm/amdgpu/psp: Destroy psp ring when doing gpu resetXiangliang Yu1-1/+3
PSP ring need to be destroy before starting reinit for vf. This patche move it from hypervisor driver into guest. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Frank Min <Frank.Min@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-08drm/amdgpu/psp: Add support VMR ring for VFXiangliang Yu4-31/+85
PSP only support VMR ring for SRIOV vf since v45 and all commands will be send to VMR ring for executing. VMR ring use C2PMSG 101 ~ 103 instead of C2PMSG 64 ~ 71. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-08drm/amdgpu/psp: Get psp fw version through reading registerXiangliang Yu1-1/+3
If PSP FW is running already, driver will not load PSP FW again and skip it. So psp fw version is not correct if reading it from FW binary file, need to get right version from register. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-08drm/amdgpu: always reserve one more shared slot for pipelined BO movesChristian König2-4/+6
This allows us to drop the extra reserve in TTM. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-08drm/amdgpu: always reserve two slots for the VMChristian König2-13/+6
And drop the now superflous extra reservations. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-08drm/amdgpu: fix using shared fence for exported BOs v2Christian König2-3/+11
It is perfectly possible that the BO list is created before the BO is exported. While at it clean up setting shared to one instead of true. v2: add comment and simplify logic Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-08drm/ttm: allow reserving more than one shared slot v3Christian König13-28/+33
Let's support simultaneous submissions to multiple engines. v2: rename the field to num_shared and fix up all users v3: rebased Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-08drm/amdgpu: both support PCO FP5/AM4 rlc fwAaron Liu1-1/+15
For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin For Picasso && FP5 SOCKET board, we use picasso_rlc.bin Judgment method: PCO AM4: revision >= 0xC8 && revision <= 0xCF or revision >= 0xD8 && revision <= 0xDF otherwise is PCO FP5 Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher at amd.com> Reviewed-by: Huang Rui <ray.huang at amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-08drm/amdgpu/powerplay: check MC firmware for FFC supportAlex Deucher1-0/+8
Check if the MC firmware supports FFC and tell the SMC so mclk switching is handled properly. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-08drm/amdgpu/powerplay: update smu7_ppsmc.hAlex Deucher1-0/+3
Add new messages for polaris. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-07drm/amdgpu: update smu firmware images for VI variants (v2)Alex Deucher2-5/+31
Some new variants require updated firmware. V2: add MODULE_FIRMWARE for new firmwares Reviewed-by: Huang Rui <ray.huang@amd.com> (v1) Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2018-12-07drm/i915/gvt: fix spelling mistake "Interupts" -> "Interrupts"Colin Ian King1-1/+1
There is a spelling mistake in an error message, fix it. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-12-07drm/i915/gvt: Fix shadow ctx ppgtt destroy functionXiong Zhang2-0/+37
Recently gvt shadow ctx create ppgtt table and this ppgtt's root pointer is modified at workload dispatch, then we lose the original ppgtt's root pointer, this causes the ppgtt destroy function abnormal as it will release the wrong root table. This patch save i915 context ppgtt root pointer at shadow ctx creation and restore it at shadow ctx destruction. v2: Split save and restore function (Zhenyu) Fixes:4f15665ccbba("drm/i915: Add ppgtt to GVT GEM context") Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-12-07drm/i915/gvt: fix a typo: "registeration" -> "registration".Peng Hao1-1/+1
Fix a typo in the error message reporting. Signed-off-by: Peng Hao <peng.hao2@zte.com.cn> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-12-07drm/i915/gvt: fix typo in two MI cmd annotationXinyun Liu1-3/+3
s/ME_SEMAPHORE_/MI_SEMAPHORE_ Signed-off-by: Xinyun Liu <xinyun.liu@intel.com> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-12-07drm/i915/gvt: update force-to-nonpriv register whitelistZhao Yan1-0/+1
Host print below warning message when creating guest: "gvt: vgpu(2) Invalid FORCE_NONPRIV write 83a8". Register 0x83a8 should be in force-to-nonpriv whitelist as required by guest v2: update commit message to describe purpose of this patch in detail (zhenyu wang) Signed-off-by: Zhao Yan <yan.y.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-12-07Merge tag 'drm-misc-next-2018-12-06' of ↵Dave Airlie37-508/+1008
git://anongit.freedesktop.org/drm/drm-misc into drm-next Final changes to drm-misc-next for v4.21: UAPI Changes: Core Changes: - Add dma_fence_get_stub to dma-buf, and use it in drm/syncobj. - Add and use DRM_MODESET_LOCK_BEGIN/END helpers. - Small fixes to drm_atomic_helper_resume(), drm_mode_setcrtc() and drm_atomic_helper_commit_duplicated_state() - Fix drm_atomic_state_helper.[c] extraction. Driver Changes: - Small fixes to tinydrm, vkms, meson, rcar-du, virtio, vkms, v3d, and pl111. - vc4: Allow scaling and YUV formats on cursor planes. - v3d: Enable use of the Texture Formatting Unit, and fix prime imports of buffers from other drivers. - Add support for the AUO G101EVN010 panel. - sun4i: Enable support for the H6 display engine. Signed-off-by: Dave Airlie <airlied@redhat.com> [airlied: added drm/v3d: fix broken build to the merge commit] From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/321be9d3-ab75-5f92-8193-e5113662edef@linux.intel.com
2018-12-06drm/tegra: sor: Reset the SOR if possibleThierry Reding1-4/+13
If the SOR is already up and running when the kernel driver is probed, setting a mode will typically fail. This can be seen for example on Jetson TX2. Under certain circumstances the generic power domain code will cause the SOR to be reset. However, if the power domain is never powered off (this can happen if the HDA controller is enabled, which is part of the same power domain as the SOR), then the SOR will end up not getting reset and fail to properly set a mode. To work around this, try to get the reset control and assert/deassert it, irrespective of whether or not a generic power domain is attached to the SOR. On platforms where the kernel implements generic power domains (up to Tegra210) this will fail, because the power domain will already have acquired an exclusive reference to the reset control. But on recent platforms there the BPMP provides an ABI to control power domains, it's possible to acquire the reset control from SOR and use it to put the SOR into a known good state at probe time. The proper solution for this is to make the SOR driver capable of dealing with hardware that's already up and running (by first grace- fully shutting it down, or perhaps by seamlessly transitioning to the kernel driver and taking over the running display configuration). That is fairly involved, though, so we'll go with this quickfix for now. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-06drm/tegra: sor: Remove temporary workaroundThierry Reding1-8/+0
Remove the temporary workaround of storing the Tegra186 HDMI/DP I/O pad ID in the SOR driver. The definition has long been available in the soc/tegra/pmc.h header file. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-06drm/ast: Fix connector leak during driver unloadSam Bobroff1-0/+1
When unloading the ast driver, a warning message is printed by drm_mode_config_cleanup() because a reference is still held to one of the drm_connector structs. Correct this by calling drm_crtc_force_disable_all() in ast_fbdev_destroy(). Signed-off-by: Sam Bobroff <sbobroff@linux.ibm.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/1e613f3c630c7bbc72e04a44b178259b9164d2f6.1543798395.git.sbobroff@linux.ibm.com
2018-12-06Merge tag 'drm-misc-fixes-2018-12-05' of ↵Dave Airlie9-39/+60
git://anongit.freedesktop.org/drm/drm-misc into drm-fixes UAPI: - Distinguish lease events from hotplug (Daniel) Other: - omap: Restore panel-dpi bus flags (Tomi) - omap: Fix a couple of dsi issues (Sebastian) Cc: Sebastian Reichel <sebastian.reichel@collabora.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com> From: Sean Paul <sean@poorly.run> Link: https://patchwork.freedesktop.org/patch/msgid/20181205201428.GA35447@art_vandelay
2018-12-06Merge branch 'drm-fixes-4.20' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie14-53/+104
into drm-fixes Fixes for 4.20: - Fix banding regression on 6 bpc panels - Vega20 fix for six 4k displays - Fix LRU handling in ttm_buffer_object_transfer - Use proper MC firmware for newer polaris variants - Vega20 powerplay fixes - VCN suspend/resume fix for PCO - Misc other fixes Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181205192934.2857-1-alexander.deucher@amd.com
2018-12-06Merge tag 'vmwgfx-next-2018-12-05' of ↵Dave Airlie19-563/+2340
git://people.freedesktop.org/~thomash/linux into drm-next Pull request of 2018-12-05 Page flip with damage by Deepak and others, Various vmwgfx minor fixes anc cleanups. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thomas Hellstrom <thellstrom@vmware.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181205103554.3675-1-thellstrom@vmware.com
2018-12-06Merge tag 'exynos-drm-next-for-v4.21' of ↵Dave Airlie21-348/+314
git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next - Refactoring of DMA and IOMMU code . This patch series simplifies DMA mapping creation by avoiding looping all components to get dma device object, reduces code size by merging IOMMU and DMA code. - Enhance plane alpha and blend mode support . This patch series adds configurable plane and pixel blend mode support for Exynos5433 DECON device. - Fix color format setting of Mixer driver . This patch series fixes color format and range setting by splitting range and format. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Inki Dae <inki.dae@samsung.com> Link: https://patchwork.freedesktop.org/patch/msgid/1544002853-11661-1-git-send-email-inki.dae@samsung.com
2018-12-06Merge branch 'drm-next-4.21' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie99-1461/+2859
into drm-next amdgpu and amdkfd: - Freesync support - ABM support in DC - KFD support for vega12 and polaris12 - Add sdma paging queue support for vega - Use ACPI to query backlight range on supported platforms - Clean up doorbell handling - KFD fix for pasid handling under non-HWS - Misc cleanups and fixes scheduler: - Revert "fix timeout handling v2" radeon: - Fix possible overflow on 32 bit ttm: - Fix for LRU handling for ghost objects Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181130192505.2946-1-alexander.deucher@amd.com
2018-12-06Merge tag 'drm-intel-next-2018-12-04' of ↵Dave Airlie56-1965/+4859
git://anongit.freedesktop.org/drm/drm-intel into drm-next Final drm/i915 changes for v4.21: - ICL DSI video mode enabling (Madhav, Vandita, Jani, Imre) - eDP sink count fix (José) - PSR fixes (José) - DRM DP helper and i915 DSC enabling (Manasi, Gaurav, Anusha) - DP FEC enabling (Anusha) - SKL+ watermark/ddb programming improvements (Ville) - Pixel format fixes (Ville) - Selftest updates (Chris, Tvrtko) - GT and engine workaround improvements (Tvrtko) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87va496uoe.fsf@intel.com
2018-12-06drm/scheduler: Add drm_sched_suspend/resume_timeout()Sharat Masetty2-16/+78
This patch adds two new functions to help client drivers suspend and resume the scheduler job timeout. This can be useful in cases where the hardware has preemption support enabled. Using this, it is possible to have the timeout active only for the ring which is active on the ringbuffer. This patch also makes the job_list_lock IRQ safe. Suggested-by: Christian Koenig <Christian.Koenig@amd.com> Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-06drm/scheduler: Set sched->thread to NULL on failureSharat Masetty1-2/+4
In cases where the scheduler instance is used as a base object of another driver object, it's not clear if the driver can call scheduler cleanup on the fail path. So, Set the sched->thread to NULL, so that the driver can safely call drm_sched_fini() during cleanup. Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-06drm/amdgpu/acpi: NULL check before some freeing functions is not neededWen Yang1-2/+1
kfree(NULL) is safe, so removes NULL check before freeing the mem. This patch also fix the ifnullfree.cocci warnings. Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Wen Yang <wen.yang99@zte.com.cn> CC: Alex Deucher <alexander.deucher@amd.com> CC: christian.koenig@amd.com CC: "David (ChunMing) Zhou" <David1.Zhou@amd.com> CC: David Airlie <airlied@linux.ie> (maintainer:DRM DRIVERS) CC: Lyude Paul <lyude@redhat.com> CC: Rex Zhu <Rex.Zhu@amd.com> CC: Jim Qu <Jim.Qu@amd.com> CC: amd-gfx@lists.freedesktop.org CC: dri-devel@lists.freedesktop.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-06drm/amd/include: Add mmhub 9.4 reg offsets and shift-maskLeo Li2-0/+67
In particular, we need the mmMC_VM_XGMI_LFB_CNTL register, for determining if xGMI is enabled on VG20. This will be used by DC to determine the correct spread spectrum adjustment for display and audio clocks. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-06drm/amdgpu/si: fix SI after doorbell reworkAlex Deucher1-1/+2
SI does not use doorbells, move asic doorbell init later asic check. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=108920 Reviewed-by: Oak Zeng <Oak.Zeng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-06drm/amdgpu/powerplay: fix clock stretcher limits on polaris (v2)Alex Deucher1-2/+15
Adjust limits for newer polaris variants. v2: fix polaris11 kicker (Jerry) Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-06drm/amdgpu/powerplay: fix mclk switch limit on polarisAlex Deucher1-1/+4
Update switch limit on newer polaris variants. This may fix flickering with high refresh rates with mclk switching enabled. Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-06drm/amd/display: Add tracing to dcDavid Francis6-4/+146
[Why] Tracing is a useful and cheap debug functionality [How] This creates a new trace system amdgpu_dm, currently with three trace events amdgpu_dc_rreg and amdgpu_dc_wreg report the address and value of any dc register reads and writes amdgpu_dc_performance requires at least one of those two to be enabled. It counts the register reads and writes since the last entry v2: Don't check for NULL before kfree Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-05drm/amdgpu/vcn: Update vcn.cur_state during suspendJames Zhu1-1/+2
Replace vcn_v1_0_stop with vcn_v1_0_set_powergating_state during suspend, to keep adev->vcn.cur_state update. It will fix VCN S3 hung issue. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-05Merge tag 'gvt-fixes-2018-12-04' of https://github.com/intel/gvt-linux into ↵Joonas Lahtinen1-1/+1
drm-intel-fixes gvt-fixes-2018-12-04 - Fix tiling mode format on BDW for VFIO gfx dmabuf (Tina) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> From: Zhenyu Wang <zhenyuw@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181204050633.GY12743@zhen-hp.sh.intel.com
2018-12-05drm/i915: Introduce per-engine workaroundsTvrtko Ursulin5-117/+151
We stopped re-applying the GT workarounds after engine reset since commit 59b449d5c82a ("drm/i915: Split out functions for different kinds of workarounds"). Issue with this is that some of the GT workarounds live in the MMIO space which gets lost during engine resets. So far the registers in 0x2xxx and 0xbxxx address range have been identified to be affected. This losing of applied workarounds has obvious negative effects and can even lead to hard system hangs (see the linked Bugzilla). Rather than just restoring this re-application, because we have also observed that it is not safe to just re-write all GT workarounds after engine resets (GPU might be live and weird hardware states can happen), we introduce a new class of per-engine workarounds and move only the affected GT workarounds over. Using the framework introduced in the previous patch, we therefore after engine reset, re-apply only the workarounds living in the affected MMIO address ranges. v2: * Move Wa_1406609255:icl to engine workarounds as well. * Rename API. (Chris Wilson) * Drop redundant IS_KABYLAKE. (Chris Wilson) * Re-order engine wa/ init so latest platforms are first. (Rodrigo Vivi) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=107945 Fixes: 59b449d5c82a ("drm/i915: Split out functions for different kinds of workarounds") Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: intel-gfx@lists.freedesktop.org Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20181203133341.10258-1-tvrtko.ursulin@linux.intel.com (cherry picked from commit 4a15c75c42460252a63d30f03b4766a52945fb47) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-29 19:14:32 +0300