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path: root/drivers/gpu
AgeCommit message (Expand)AuthorFilesLines
2014-05-13drm/i915/chv: Add DPLL state readout supportVille Syrjälä1-1/+33
2014-05-12drm/i915/chv: Pipe select change for DP and HDMIChon Ming Lee4-2/+20
2014-05-12drm/i915/chv: Add phy supports for CherryviewChon Ming Lee2-2/+270
2014-05-12drm/i915/chv: Add update and enable pll for CherryviewChon Ming Lee2-2/+202
2014-05-12drm/i915/chv: find the best divisor for the target clock v4Chon Ming Lee2-0/+107
2014-05-12drm/i915/chv: Trigger phy common lane resetChon Ming Lee2-15/+65
2014-05-12drm/i915/chv: Add vlv_pipe_to_channelChon Ming Lee1-0/+14
2014-05-12drm/i915/chv: Update Cherryview DPLL changes to support Port D. v2Chon Ming Lee3-2/+16
2014-05-12drm/i915/chv: Add DPIO offset for Cherryview. v3Chon Ming Lee3-2/+13
2014-05-12drm/i915/chv: Add DDL register defines for CherryviewVille Syrjälä1-0/+29
2014-05-12srm/i915/chv: Add Cherryview PCI IDsVille Syrjälä1-1/+11
2014-05-12drm/i915/chv: Initial clock gating support for CherryviewVille Syrjälä1-0/+13
2014-05-12drm/i915/chv: Add Cherryview interrupt registers into debugfsVille Syrjälä1-1/+41
2014-05-12drm/i915: Drop unecessary casts in i915_irq.cDaniel Vetter1-6/+6
2014-05-12drm/i915/chv: Preliminary interrupt support for CherryviewVille Syrjälä1-1/+224
2014-05-12drm/i915: Use hash tables for the command parserBrad Volkin4-38/+140
2014-05-12drm/i915: Convert gmch platforms over to ilk_crtc_{enable, disable}_planes()Ville Syrjälä1-78/+56
2014-05-09drm/i915/vlv: reset VLV media force wake request registerJani Nikula1-0/+2
2014-05-08drm/i915: Flush request queue when waiting for ring spaceChris Wilson3-27/+16
2014-05-08drm/i915: Improve fallback ring waitingChris Wilson1-6/+16
2014-05-07drm/i915/SDVO: For sysfs link put directory and target in correct orderEgbert Eich1-2/+2
2014-05-07drm/i915: use lane count and link rate from VBT as minimums for eDPJani Nikula1-7/+23
2014-05-07drm/i915: clean up VBT eDP link param decodingJani Nikula1-14/+38
2014-05-07drm/i915: consider the source max DP lane count tooPaulo Zanoni1-2/+18
2014-05-07drm/i915: Make aliasing a 2nd class VMBen Widawsky1-0/+4
2014-05-07drm/i915: Use topdown allocation for PPGTT PDEs on gen6/7Ben Widawsky1-2/+1
2014-05-07drm/i915: vlv: enable runtime PMImre Deak1-1/+1
2014-05-07drm/i915: vlv: add runtime PM supportImre Deak2-0/+389
2014-05-07drm/i915: propagate the error code from runtime PM callbacksImre Deak1-15/+42
2014-05-07drm/i915: add various missing GTI/Gunit register definitionsImre Deak1-1/+40
2014-05-07Merge branch 'mullins' of git://people.freedesktop.org/~deathsimple/linux int...Dave Airlie10-31/+187
2014-05-07Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/...Dave Airlie4-9/+10
2014-05-07Merge tag 'topc/core-stuff-2014-05-05' of git://anongit.freedesktop.org/drm-i...Dave Airlie4-20/+44
2014-05-06drm/i915/chv: Add DPINVGTT registers defines for CherryviewVille Syrjälä1-1/+11
2014-05-06drm/i915/chv: Add display interrupt registers bits for CherryviewVille Syrjälä1-1/+20
2014-05-06drm/i915/chv: Add DPFLIPSTAT register bits for CherryviewVille Syrjälä1-0/+7
2014-05-06drm/i915/chv: Add PIPESTAT register bits for CherryviewVille Syrjälä1-0/+8
2014-05-06drm/i915/chv: Enable aliasing PPGTT for CHVVille Syrjälä1-3/+4
2014-05-06drm/i915/chv: Flush caches when programming page tablesRafael Barbalho1-1/+10
2014-05-06drm/i915/chv: PPAT setup for CherryviewVille Syrjälä2-4/+40
2014-05-06drm/radeon: add Mullins VCE supportLeo Liu1-0/+1
2014-05-06drm/radeon: modesetting updates for Mullins.Samuel Li1-2/+3
2014-05-06drm/radeon: dpm updates for KV/KBAlex Deucher1-20/+97
2014-05-06drm/radeon: add Mullins dpm support.Samuel Li2-10/+11
2014-05-06drm/radeon: add Mullins UVD support.Samuel Li1-0/+1
2014-05-06drm/radeon: update cik init for Mullins.Samuel Li2-0/+72
2014-05-06drm/radeon: add Mullins chip familySamuel Li3-0/+3
2014-05-06drm/radeon: lower the ref * post PLL maximumChristian König1-1/+1
2014-05-06drm/radeon: check that we have a clock before PLL setupChristian König1-0/+3
2014-05-06drm/radeon: drm/radeon: add missing radeon_semaphore_free to error pathMaarten Lankhorst7-0/+7
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