summaryrefslogtreecommitdiff
path: root/drivers/gpu
AgeCommit message (Expand)AuthorFilesLines
2014-05-21Merge branch 'topic/drm-vblank-rework' into drm-intel-next-queuedDaniel Vetter30-845/+1487
2014-05-21drm/i915: Accurately initialize fifo underrun state on gmch platformsDaniel Vetter4-11/+10
2014-05-21drm/i915: rip our vblank reset hacks for runtime PMDaniel Vetter1-34/+0
2014-05-21drm/i915: Use new kms-native vblank functionsDaniel Vetter1-10/+12
2014-05-21drm/irq: Add kms-native crtc interface functionsDaniel Vetter1-0/+77
2014-05-21drm/irq: kerneldoc polishDaniel Vetter1-48/+117
2014-05-21drm/i915: Remove drm_vblank_pre/post_modeset callsDaniel Vetter1-5/+0
2014-05-21drm/i915: Move buffer pinning and ring selection to intel_crtc_page_flip()Ville Syrjälä2-81/+35
2014-05-21drm/i915: Drop the excessive vblank waits from modeset codepathsVille Syrjälä1-11/+7
2014-05-21drm/i915: Wait for vblank in hsw_enable_ips()Ville Syrjälä2-10/+7
2014-05-21drm/i915: Fix mmio vs. CS flip race on ILK+Ville Syrjälä3-7/+69
2014-05-21drm/i915: drop encoder hot_plug calls at resumeJesse Barnes1-19/+1
2014-05-21drm/i915: Drop now misleading DDI comment from dp_link_downDaniel Vetter1-16/+1
2014-05-20drm: Add drm_vblank_on()Ville Syrjälä2-19/+61
2014-05-20drm: Make blocking vblank wait return when the vblank interrupts get disabledVille Syrjälä1-0/+1
2014-05-20drm: Make the vblank disable timer per-crtcVille Syrjälä1-19/+21
2014-05-20drm: Use correct spinlock flavor in drm_vblank_get()Peter Hurley1-3/+3
2014-05-20drm/i915: shuffle panel codeJani Nikula1-75/+75
2014-05-20drm/i915: Clear GDSR after reset on ILKVille Syrjälä1-2/+8
2014-05-20drm/i915: Kill RMW from ILK reset codeVille Syrjälä1-7/+2
2014-05-20drm/i915: add missing unregister_oom_notifier to the error/unload pathImre Deak1-4/+5
2014-05-20drm/i915: Drop /** */ comments from i915_reg.hVille Syrjälä1-123/+123
2014-05-20drm/i915/chv: Add a bunch of pre production workaroundsVille Syrjälä2-1/+22
2014-05-20drm/i915/chv: Use RMW to toggle swing calc initVille Syrjälä3-7/+35
2014-05-20drm/i915/chv: Don't do group access reads from TX lanes eitherVille Syrjälä3-29/+59
2014-05-20drm/i915/chv: Don't use PCS group access readsVille Syrjälä3-16/+62
2014-05-20drm/i915/chv: Set soft reset override bit for data lane resetsVille Syrjälä3-0/+17
2014-05-20drm/i915/chv: Reset data lanes in encoder .post_disable() hookVille Syrjälä3-6/+48
2014-05-20drm/i915/chv: Turn off dclkp after the PLL has been disabledVille Syrjälä1-5/+10
2014-05-20drm/i915/chv: Move data lane deassert to encoder pre_enableVille Syrjälä3-7/+15
2014-05-20drm/i915/chv: Fix CHV PLL state trackingVille Syrjälä1-15/+26
2014-05-20drm/i915/chv: Register port D encoders and connectorsVille Syrjälä2-0/+10
2014-05-20drm/i915/chv: Fix PORT_TO_PIPE for CHVVille Syrjälä3-0/+6
2014-05-20drm/i915/chv: Bump num_pipes to 3Ville Syrjälä1-1/+1
2014-05-20drm/i915/chv: Add cursor pipe offsetsVille Syrjälä5-45/+71
2014-05-20drm/i915/chv: Fix gmbus for port DVille Syrjälä2-1/+5
2014-05-20drm/i915/chv: Configure crtc_mask correctly for CHVVille Syrjälä2-2/+16
2014-05-20drm/i915/chv: Make CHV irq handler loop until all interrupts are consumedVille Syrjälä1-15/+14
2014-05-20drrm/i915/chv: Use valleyview_pipestat_irq_handler() for CHVVille Syrjälä1-73/+17
2014-05-20drm/i915/chv: Clarify VLV/CHV PIPESTAT bits a bit moreVille Syrjälä1-2/+8
2014-05-20drm/i915/chv: Add CHV display supportRafael Barbalho2-3/+20
2014-05-20drm/i915/chv: Implement WaDisableSamplerPowerBypass for CHVRafael Barbalho1-0/+4
2014-05-20drm/i915/chv: Add some workaround notesVille Syrjälä2-2/+2
2014-05-20drm/i915/chv: Implement WaDisableSDEUnitClockGating:chvVille Syrjälä1-0/+4
2014-05-20drm/i915/chv: Implement WaDisableCSUnitClockGating:chvVille Syrjälä1-0/+4
2014-05-20drm/i915/chv: Implement WaDisableSemaphoreAndSyncFlipWait:chvVille Syrjälä1-0/+4
2014-05-20drm/i915/chv: Implement WaVSRefCountFullforceMissDisable:chv and WaDSRefCount...Ville Syrjälä1-0/+6
2014-05-20drm/i915/chv: Implement WaDisableThreadStallDopClockGating:chvVille Syrjälä1-0/+4
2014-05-20drm/i915/chv: Implement WaDisablePartialInstShootdown:chvVille Syrjälä1-0/+4
2014-05-20drm/i915: s/ironlake_/intel_ for the enable_share_dpll functionDaniel Vetter1-5/+3
generated by cgit v1.2.3 (git 2.39.0) at 2026-11-05 12:03:50 +0300