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2014-07-11drm/i915: Read guaranteed freq for valleyviewDeepak S1-0/+16
Reading RP1 for valleyview to help us enable "pm_rps" i-g-t testcase execution. Signed-off-by: Deepak S <deepak.s@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> [danvet: Add missing static.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: Call encoder->post_disable() in intel_sanitize_encoder()Ville Syrjälä1-0/+2
VLV and CHV disable the DP port only in the .post_disable() hook, so we need to make intel_sanitize_encoder() call that when it's trying to disable encoders without an active pipes. My bsw actaully hits this when an external display is connected. The BIOS still likes to turn on the eDP port, but leaves the pipe disabled. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: ddi: enable runtime pm during dpmsDaniel Vetter1-17/+8
Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> [danvet: Remove now bogus comment.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/armada: update Armada 510 (Dove) to use "ext_ref_clk1" as the clockRussell King1-1/+1
Remove the underscore between "clk" and "1" so that we match the name of the clock given in the documentation. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-07-11drm/armada: convert to componentized supportRussell King1-7/+148
Convert the Armada DRM driver to use the component helpers, which will permit us to clean up the driver and move towards an implementation which is compatible with a DT description of the hardware. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-07-11Merge branches 'drm-devel' and 'component-for-driver' into armada-drmRussell King2-0/+68
2014-07-11drm: add of_graph endpoint helper to find possible CRTCsRussell King2-0/+68
Add a helper to allow encoders to find their possible CRTCs from the OF graph without having to re-implement this functionality. We add a device_node to drm_crtc which corresponds with the port node in the DT description of the CRTC device. We can then scan the DRM device list for CRTCs to find their index, matching the appropriate CRTC using the port device_node, thus building up the possible CRTC mask. Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-07-11drm/i915: Use the cached min/min/rpe values in the vlv debugfs codeVille Syrjälä3-15/+14
No need to re-read the hardware rps fuses when we already have all the values tucked away in dev_priv->rps. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S <deepak.s@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: Don't disable PPGTT for CHV based in PCI revVille Syrjälä1-1/+2
In commit 62942ed7279d3e06dc15ae3d47665eff3b373327 Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Fri Jun 13 09:28:33 2014 -0700 drm/i915/vlv: disable PPGTT on early revs v3 we forgot about CHV. IS_VALLEYVIEW() is true for CHV, so we need to explicitly avoid disabling PPGTT on CHV. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S <deepak.s@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds26-73/+177
Pull drm fixes from Dave Airlie: "Nothing too scary, we have one outstanding i915 regression but Daniel has promised the fix as soon as he's finished testing it a bit. Fixes for the main x86 drivers: - radeon: dpm fixes, displayport regression fix - i915: quirks for backlight regression, edp reboot fix, valleyview black screen fixes - nouveau: display port regression fixes, fix for memory reclocking" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/radeon/dpm: Reenabling SS on Cayman drm/radeon: fix typo in ci_stop_dpm() drm/radeon: fix typo in golden register setup on evergreen drm/radeon: only print meaningful VM faults drm/radeon/dp: return -EIO for flags not zero case drm/i915/vlv: T12 eDP panel timing enforcement during reboot drm/i915: Only unbind vgacon, not other console drivers drm/i915: Don't clobber the GTT when it's within stolen memory drm/i915/vlv: Update the DSI ULPS entry/exit sequence drm/i915/vlv: DPI FIFO empty check is not needed drm/i915: Toshiba CB35 has a controllable backlight drm/i915: Acer C720 and C720P have controllable backlights drm/i915: quirk asserts controllable backlight presence, overriding VBT drm/nouveau/ram: fix test for gpio presence drm/nouveau/dp: workaround broken display drm/nouveau/dp: fix required link bandwidth calculations drm/nouveau/kms: restore fbcon after display has been resumed drm/nv50-/kms: pass a non-zero value for head to sor dpms methods drm/nouveau/fb: Prevent inlining of ramfuc_reg drm/gk104/ram: bash mpll bit 31 on
2014-07-11drm/radeon/dpm: Reenabling SS on CaymanAlexandre Demers1-6/+0
It reverts commit c745fe611ca42295c9d91d8e305d27983e9132ef now that Cayman is stable since VDDCI fix. Spread spectrum was not the culprit. This depends on b0880e87c1fd038b84498944f52e52c3e86ebe59 (drm/radeon/dpm: fix vddci setup typo on cayman). Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2014-07-11drm/radeon: fix typo in ci_stop_dpm()Alex Deucher1-1/+1
Need to use the RREG32_SMC() accessor since the register is an smc indirect index. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2014-07-11drm/radeon: fix typo in golden register setup on evergreenAlex Deucher1-4/+4
Fixes hangs on driver load on some cards. bug: https://bugs.freedesktop.org/show_bug.cgi?id=76998 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2014-07-11drm/radeon: only print meaningful VM faultsChristian König3-6/+12
Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-07-11drm/radeon/dp: return -EIO for flags not zero caseAlex Deucher1-1/+1
If there are error flags in the aux transaction return -EIO rather than -EBUSY. -EIO restarts the whole transaction while -EBUSY jus retries. Fixes problematic aux transfers. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=80684 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2014-07-11drm/i915: Make the RPS interrupt generation mask handle the vlv waChris Wilson1-5/+5
We can eliminate a lot of special case code by making the computation of the interrupt mask be correct for all callers. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: Move RPS evaluation interval counters to i915->rpsChris Wilson2-27/+23
Place the RPS counters inside the RPS struct. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: Don't cast a pointer to void* unnecessarilyDamien Lespiau1-1/+1
C is super happy to asign anything pointer to void *. Don't pretend otherwise. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: don't read LVDS regs at compute_config timePaulo Zanoni1-4/+9
We may reach this point while the machine is still runtime suspended, so we'll hit a WARN. The other encoders also don't touch registers at this point, so instead of waking the machine up, write some code to keep the register always at the same state, including after we runtime suspend/resume. Testcase: igt/pm_rpm Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80463 Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: check the power domains in intel_lvds_get_hw_state()Paulo Zanoni1-0/+5
Just like we do for the other encoders. This should fix some WARNs when running pm_rpm on SNB. Testcase: igt/pm_rpm Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80463 Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: check the power domains in ironlake_get_pipe_config()Paulo Zanoni1-0/+4
Just like we already do in haswell_get_pipe_config(). This should prevent some WARNs when we run pm_rpm on SNB. Testcase: igt/pm_rpm Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80463 Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: don't skip shared DPLL assertion on LPTPaulo Zanoni1-5/+0
Since we now have support for shared DPLLS. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: Only touch WRPLL hw state in enable/disable hooksDaniel Vetter3-21/+8
To be able to do this we need to separately keep track of how many crtcs need a given WRPLL and how many actually actively use it. The common shared dpll framework already has all this, including massive state readout and cross checking. Which allows us to do this switch in a fairly small patch. Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: Switch to common shared dpll framework for WRPLLsDaniel Vetter5-144/+27
Mostly this patch is one big excersize in deleting code and asserts which are no longer needed. Note that we still abuse the shared dpll framework a bit since we call the enable/disable functions from the crtc mode_set and off hooks. But changing the actual hardware sequence will be done in the next step. Note that besides the massive amount of changes in this patch the places and order in which the low-level WRPLL code is called is absolutely unchanged. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> [imre: rebased on patchset version w/o pch/crt/fdi refactoring] Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: ->enable hook for WRPLLsDaniel Vetter1-32/+19
This time around another cute hack to pre-fill the pll->hw_state with the right values. And also remove a bunch of checks which will be replaced by lots more checks in the common framework. Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: ->disable hook for WRPLLsDaniel Vetter2-14/+20
Currently still with a redudant WARN_ON in there, the common shared dpll code will take care of this in the future. Also we need to flip the switch for the transitional hack now to make sure that we disable the right pll. Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: State readout support for WRPLLsDaniel Vetter5-0/+31
Still tacked onto the side, but slowly getting there. v2: Don't forget the debugfs file. v3 (from Paulo): Don't forget to check the power domains. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: add POWER_DOMAIN_PLLSPaulo Zanoni4-0/+14
And get/put it when needed. The special thing about this commit is that it will now return false in ibx_pch_dpll_get_hw_state() in case the power domain is not enabled. This will fix some WARNs we have when we run pm_rpm on SNB. Testcase: igt/pm_rpm Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=80463 Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: Document that the pll->mode_set hook is optionalDaniel Vetter1-0/+2
The WRPLLs won't use them. Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: Basic shared dpll support for WRPLLsDaniel Vetter3-10/+34
Just filing in names and ids, but not yet officially registering them so that the hw state cross checker doesn't completely freak out about them. Still since we do already read out and cross check config->shared_dpll the basics are now there to flesh out the wrpll shared dpll implementation. The idea is now to roll out all the callbacks step-by-step and then at the end switch to the shared dpll framework. This way hw and sw changes are clearly separated. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> [imre: added const to hsw_ddi_pll_names (Damien)] Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: Precompute static ddi_pll_sel values in encodersDaniel Vetter3-35/+26
This way only the dynamic WRPLL selection for hdmi ddi mode is done in intel_ddi_pll_select. v2: Don't clobber the precomputed values when selecting clocks fro hdmi encoders. v3 (from Paulo): Rebase on top of the s/IS_HASWELL/HAS_DDI/ patch. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Paulo Zanoni <przanoni@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: BDW also has special-purpose DP DDI clocksPaulo Zanoni1-1/+1
Don't let it fall in the HAS_PCH_SPLIT() case. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: State readout and cross-checking for ddi_pll_selDaniel Vetter3-55/+34
To make things a bit more manageable extract a new function for reading out common ddi port state. This means a bit of duplication between encoders and the core since both look at the same registers, but doesn't seem worth to make a fuzz about. We can also remove the state readout code in intel_ddi_setup_hw_pll_state. That code is only called from the hardware take over and not the cross check code, and only after the crtc state is reconstructed. So we can rely on an accurate value of crtc->config.ddi_pll_sel already. Compared to the old code also trust the hw state more and don't special-case port A - we want to cross-check the actual-state, not bake in our own assumptions about how this is supposed to all be linked up. v2: Make use of the read-out ddi_pll_sel in intel_ddi_clock_get. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> [imre: rebased on patchset version w/o pch/crt/fdi refactoring] Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: Move ddi_pll_sel into the pipe configDaniel Vetter2-19/+20
Just boring sed job for preparation. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> [imre: rebased on patchset version w/o pch/crt/fdi refactoring] Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: Add a debugfs file for the shared dpll stateDaniel Vetter1-0/+26
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: Move SPLL disabling into hsw_crt_post_disableDaniel Vetter2-7/+15
Similar to how the ->crtc_mode_set hook should touch the hardware to enable anything the ->crtc_off hook should disable anything in the hardware. Otherwise runtime pm for dpms will not work. Currently the only things left int the haswell_crtc_off hook is disabling the ddi plls. We can't move the WRPLL enabling out yet because the current ddi pll sharing code used by the haswell code doesn't separately track active users and overall users. This must be fixed by porting it to the generic shared display pll framework, which is powerful enough. But the SPLL source is only used by the crt encoder and so can be moved already. We only need to make sure that the ddi port E is already off, which hsw_fdi_disable does by calling intel_ddi_post_disable. With this the code reorg to shuffle hsw fdi/lpt specific code into a new hsw-specific crt encoder type is now finally complete. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> [imre: rebased on patchset version w/o pch/crt/fdi refactoring] Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: Move the SPLL enabling into hsw_crt_pre_enableDaniel Vetter2-18/+14
The call to intel_ddi_pll_enable in haswell_crtc_mode_set is the only function that still touches the hardware state from the crtc mode_set callback on hsw. Since the SPLL isn't ever shared we can easily take it out into the hsw crt encoder functions. Temporarily we'll loose a bit of WARN_ON coverage with this, but once the WRPLLs are switched over that will be restored. For the SPLL selection add a WARN in the hsw fdi link training code. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> [imre: rebased on patchset version w/o pch/crt/fdi refactoring] Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: ddi: move pch cleanup before encoder->post_disableImre Deak1-4/+4
This is needed by an upcoming patch that moves the PCH/CRT PLL disabling into the post_disable hook, after which we want to keep the modeset sequence at its current state. At this point this won't have an effect since the PCH/CRT post_disable hook is atm a NOP. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: ddi: move pch setup after encoder->pre_enableImre Deak1-6/+5
This is needed by an upcoming patch that moves the PCH/CRT PLL enabling into the pre_enable hook, after which we want to keep the modeset sequence at its current state. At this point this won't have an effect since the PCH/CRT pre_enable hook is atm a NOP. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: Clean up WRPLL/SPLL #definesDaniel Vetter2-9/+10
Luckily the bit definitions match, but it's still confusing to use one when handling the other. So sprinkle some OCD over the #defines to make them match and use the right version in each place. Maybe we should unify these definitions completely, but that can always be done sometime in the future. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: Remove spll_refcount for hswDaniel Vetter2-29/+13
SPLL would be a reference clock we could potentially share, especially if we want to use the SSC mode. But currently we don't, so let's rip out this complexity for a simpler conversion to the new display pll framework. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-11drm/i915: Check hw state in assert_can_disable_lcpllDaniel Vetter1-4/+3
All the other checks also check hw state, so checking our software refcounts for the plls looks a bit odd. Also this will simplify the conversion over to the shared dpll framework, which itself has massive amounts of checks to make sure that we never leave a display pll enabled when we shouldn't. So after that conversion we should stil have a good enough coverage of asserts for entering pc8/runtime pm on hsw/bdw. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-10drm/i915: Add a couple WARN()'s to catch missing locksMatt Roper1-0/+4
Add !mutex_is_locked() checks to intel_pin_and_fence_fb_obj() and intel_unpin_fb_obj() to help catch failures to grab struct_mutex when operating on fb objects. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-10drm/i915: Add missing locking to primary plane handlersMatt Roper1-2/+15
intel_primary_plane_{setplane,disable} were lacking struct_mutex locking around their GEM operations. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reported-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-10drm/i915: get/put runtime PM at i915_semaphore_statusPaulo Zanoni1-0/+2
Otherwise we will print some WARNs when we read registers and the machine is suspended. Testcase: igt/pm_rpm/debugfs-read Cc: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-10drm/i915: fix D_COMP usage on BDWPaulo Zanoni2-6/+20
On HSW, the D_COMP register can be accessed through the mailbox (read and write) or through MMIO on a MCHBAR offset (read only). On BDW, the access should be done through MMIO on another address. So to account for all these cases, create hsw_read_dcomp() with the correct implementation for reading, and also fix hsw_write_dcomp() to do the correct thing on BDW. With this patch, we can now get back from the PC8+ state on BDW. We were previously getting a black screen and lots of dmesg errors. Please notice that the bug only happens when you actually reach the PC8+ states, not when you only allow it. Testcase: igt/pm_rpm/rte Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-10drm/i915: fix hsw_write_dcomp() error messagePaulo Zanoni1-1/+1
That function can be used to write anything on D_COMP, not just disable it, so print a more appropriate message. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-10drm/tilcdc: Fix build breakageSachin Kamat3-3/+3
Commit 34ea3d386347 ("drm: add register and unregister functions for connectors") probably missed out converting the drm_sysfs_connector_remove instances in the following files. Without this patch we get the following compilation error: ERROR: "drm_sysfs_connector_remove" [drivers/gpu/drm/tilcdc/tilcdc.ko] undefined! Signed-off-by: Sachin Kamat <sachin.kamat@samsung.com> CC: Thomas Wood <thomas.wood@intel.com> CC: David Herrmann <dh.herrmann@gmail.com> CC: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-07-10Merge tag 'drm-intel-fixes-2014-07-09' of ↵Dave Airlie10-24/+130
git://anongit.freedesktop.org/drm-intel into drm-fixes Fixes for regressions and black screens, cc: stable where applicapable (the last minute rebase was to sprinkle missing stable tags). A bit more than what I'd wish for, but excluding vlv and that the first 3 patches are just quirks for 1 regression it looks much better. There's still a "oops, lost dithering" issue on older platforms open. I'm working on a fix for that now but didn't want to delay this pile. * tag 'drm-intel-fixes-2014-07-09' of git://anongit.freedesktop.org/drm-intel: drm/i915/vlv: T12 eDP panel timing enforcement during reboot drm/i915: Only unbind vgacon, not other console drivers drm/i915: Don't clobber the GTT when it's within stolen memory drm/i915/vlv: Update the DSI ULPS entry/exit sequence drm/i915/vlv: DPI FIFO empty check is not needed drm/i915: Toshiba CB35 has a controllable backlight drm/i915: Acer C720 and C720P have controllable backlights drm/i915: quirk asserts controllable backlight presence, overriding VBT
2014-07-10Merge branch 'drm-nouveau-next' of ↵Dave Airlie10-31/+29
git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-fixes A couple of DP regression fixes, kepler memory reclocking fixes, and a fix for an annoying display issue that can pop up on resume. * 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: drm/nouveau/ram: fix test for gpio presence drm/nouveau/dp: workaround broken display drm/nouveau/dp: fix required link bandwidth calculations drm/nouveau/kms: restore fbcon after display has been resumed drm/nv50-/kms: pass a non-zero value for head to sor dpms methods drm/nouveau/fb: Prevent inlining of ramfuc_reg drm/gk104/ram: bash mpll bit 31 on
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