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path: root/drivers/gpu
AgeCommit message (Expand)AuthorFilesLines
2010-12-08drm/i915: Disable renderctx powersaving support for IronlakeChris Wilson1-1/+1
2010-12-08Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson4-61/+91
2010-12-08drm/i915/dp: Only apply the workaround if the select is still activeChris Wilson1-2/+6
2010-12-07drm/i915: Emit a request to clear a flushed and idle ring for unbusy boChris Wilson1-1/+11
2010-12-06drm/i915: Wait for the bo if a display flip is pipelined on the other ringChris Wilson1-1/+1
2010-12-06drm/i915: Only emit a flush if there is an outstanding gpu writeChris Wilson1-2/+3
2010-12-06drm/i915: Completely disable fence pipelining.Chris Wilson1-2/+4
2010-12-06drm/i915: Uncouple render/power ctx before suspendingChris Wilson3-26/+36
2010-12-06drm/i915: Ignore fenced commands for gpu access on gen4Chris Wilson1-11/+16
2010-12-06drm/i915: caps.has_rc6 is no longer used, remove it.Chris Wilson3-6/+3
2010-12-06drm/i915: Power Context register is only available for gen4 mobilesChris Wilson1-1/+1
2010-12-06drm/i915: Avoid using PIPE_CONTROL on IronlakeChris Wilson2-159/+4
2010-12-06drm/i915/lvds: Always restore panel-fitter when enabling the LVDSChris Wilson1-44/+54
2010-12-06drm/i915/ringbuffer: Only print an error on the second attempt to reset headChris Wilson1-14/+16
2010-12-05drm/i915/dp: Trivial code tidyChris Wilson1-3/+3
2010-12-05Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson1-0/+3
2010-12-05drm/i915: announce to userspace that the bsd ring is coherentDaniel Vetter1-0/+3
2010-12-05Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson1-13/+59
2010-12-05drm/i915: Enable self-refresh for IronlakeChris Wilson1-1/+1
2010-12-05drm/i915: Implement GPU semaphores for inter-ring synchronisation on SNBChris Wilson14-439/+648
2010-12-05drm/i915: Be paranoid and bail on resetting if we can't take the lock.Chris Wilson1-1/+2
2010-12-05drm/i915: Allow LVDS to be on pipe A for Ironlake+Chris Wilson1-0/+2
2010-12-05drm/i915: Re-enable RC6 for power-savings.Chris Wilson1-1/+0
2010-12-05drm/i915: Enable CB tuning of the Display PLLChris Wilson2-1/+17
2010-12-05drm/i915: Explain why we need to write DPLL twiceChris Wilson1-5/+5
2010-12-05drm/i915/lvds: Connect the PWM to the LVDS pipeChris Wilson1-3/+11
2010-12-04drm/i915: Factor in pixel-repeat in FDI M/N calculationChris Wilson1-0/+3
2010-12-04drm/i915: Death to the unnecessary 64bit divideChris Wilson1-13/+5
2010-12-03drm/i915: Clean conflicting modesetting registers upon initChris Wilson1-0/+51
2010-12-03drm/nouveau: fabricate DCB encoder table for iMac G4Francisco Jerez1-64/+38
2010-12-03drm/nouveau: tidy up and extend dma object creation interfacesBen Skeggs8-160/+184
2010-12-03drm/nouveau: remove some useless GETPARAMsBen Skeggs1-16/+1
2010-12-03drm/nv84: fix minor issues in PCRYPT implementationBen Skeggs2-1/+2
2010-12-03drm/nouveau: remove dummy page use from PCI(E)GART, use PTE present insteadBen Skeggs2-37/+3
2010-12-03drm/nv50: fix 0x100c90 init for NVAFBen Skeggs1-3/+6
2010-12-03drm/nv50: allocate page for unknown PFB object in nv50_fb.cBen Skeggs2-1/+56
2010-12-03drm/nouveau: rework gpu-specific instmem interfacesBen Skeggs6-243/+270
2010-12-03drm/nouveau: simplify gpuobj suspend/resumeBen Skeggs4-73/+21
2010-12-03drm/nv50: rework PGPIO IRQ handling and hotplug detectionBen Skeggs7-104/+234
2010-12-03drm/nv04-nv40: unregister irq handler on destroyBen Skeggs1-0/+3
2010-12-03drm/nouveau: tidy+move PGRAPH ISRs to their respective *_graph.c filesBen Skeggs8-894/+809
2010-12-03drm/nouveau: move PFIFO ISR into nv04_fifo.cBen Skeggs7-208/+219
2010-12-03drm/nv04-nv40: register vblank isrBen Skeggs2-19/+18
2010-12-03drm/nouveau: move bitfield/enum helpers to nouveau_util.cBen Skeggs3-68/+63
2010-12-03drm/nv50: use register/unregister functionality for PDISPLAY ISRBen Skeggs4-18/+13
2010-12-03drm/nv50: move GPIO ISR to nv50_gpio.cBen Skeggs5-24/+40
2010-12-03drm/nv84: move PCRYPT ISR out of nouveau_irq.cBen Skeggs5-25/+98
2010-12-03drm/nouveau: allow irq handlers to be installed by engine-specific codeBen Skeggs2-1/+37
2010-12-03drm/nv50: 0x50c0 apparently works on NVA3+ too, so lets allow itBen Skeggs1-5/+4
2010-12-03drm/nv50: fix compute object classBen Skeggs1-2/+8
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