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path: root/drivers/gpu/drm
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2011-07-25Merge branch 'drm-nouveau-next' of ↵Dave Airlie18-147/+98
git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-core-next * 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: drm/nouveau/gr: disable fifo access and idle before suspend ctx unload drm/nouveau: pass flag to engine fini() method on suspend drm/nouveau: replace nv04_graph_fifo_access() use with direct reg bashing drm/nv40/gr: rewrite/split context takedown functions drm/nouveau: detect disabled device in irq handler and return IRQ_NONE drm/nouveau: ignore connector type when deciding digital/analog on DVI-I drm/nouveau: Add a quirk for Gigabyte NX86T drm/nouveau: do not leak in nv20_graph_create drm/nv50/dp: fix hack to work for macbooks booted via EFI
2011-07-25drm/nouveau/gr: disable fifo access and idle before suspend ctx unloadBen Skeggs4-0/+20
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-07-25drm/nouveau: pass flag to engine fini() method on suspendBen Skeggs14-20/+21
It may not be necessary to fail in certain cases (such as failing to idle) on module unload, whereas on suspend it's important to ensure a consistent state can be restored on resume. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-07-25drm/nouveau: replace nv04_graph_fifo_access() use with direct reg bashingBen Skeggs4-20/+8
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-07-25drm/nv40/gr: rewrite/split context takedown functionsBen Skeggs1-91/+19
It's completely pointless to save the PGRAPH context when destroying a channel, so don't bother. This commit should also fix kernel.org bug 39422, where the DRM channel state was incorrectly being saved because we left PGRAPH FIFO access enabled while running the ctxprog. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-07-25drm/nouveau: detect disabled device in irq handler and return IRQ_NONEBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-07-25drm/nouveau: ignore connector type when deciding digital/analog on DVI-IBen Skeggs1-15/+19
If the connector table is lying, which it often does on the boards of a particular manufacturer, we may end up doing the wrong thing. Listen to the encoder table instead, it's more reliable. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-07-25drm/nouveau: Add a quirk for Gigabyte NX86TEmil Velikov1-0/+6
The connector table lies, the card has DVI-I not HDMI Fixes bug https://bugs.freedesktop.org/show_bug.cgi?id=35675 v2: Mention the bugreport Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-07-25drm/nouveau: do not leak in nv20_graph_createJesper Juhl1-0/+2
If we return due to an unknown chipset in drivers/gpu/drm/nouveau/nv20_graph.c:nv20_graph_create() we'll leak the memory allocated to 'pgraph'. This patch should fix the leak. Signed-off-by: Jesper Juhl <jj@chaosbits.net> Reviewed-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-07-25drm/nv50/dp: fix hack to work for macbooks booted via EFIBen Skeggs1-0/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-07-18drm/radeon/kms: add info query for backend mapAlex Deucher7-1/+22
The 3D driver need to get the pipe to backend map to certain things. Add a query to get the info. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-07-15drm: platform multi-device supportRob Clark1-2/+3
Include the device id in the bus-id to give userspace a way to open the correct "cardN" when there are multiple device instances. Signed-off-by: Rob Clark <rob@ti.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-07-14drm/radeon: Don't clobber error return value in page flipping cleanup paths.Michel Dänzer1-7/+2
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-07-14drm/radeon: Don't generate new fence for page flip.Michel Dänzer1-27/+6
Use the fence of the new frontbuffer, if any. Generating a new fence could cause us to wait for completely unrelated rendering to finish before performing the flip. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-07-14Merge branch 'drm-intel-next' of ↵Dave Airlie20-404/+1101
ssh://master.kernel.org/pub/scm/linux/kernel/git/keithp/linux-2.6 into drm-core-next * 'drm-intel-next' of ssh://master.kernel.org/pub/scm/linux/kernel/git/keithp/linux-2.6: (52 commits) drm/i915: provide module parameter description drm/i915: add module parameter compiler hints drm/i915/bios: Avoid temporary allocation whilst searching for downclock drm/i915: Cache GT fifo count for SandyBridge i915: Fix opregion notifications drm/i915: TVDAC_STATE_CHG does not indicate successful load-detect drm/i915: Select correct pipe during TV detect drm/i915/ringbuffer: Idling requires waiting for the ring to be empty Revert "drm/i915: enable rc6 by default" drm/i915: Clean up i915_driver_load failure path drm/i915: Enable i915 frame buffer compression by default drm/i915: Share the common work of disabling active FBC before updating drm/i915: Perform intel_enable_fbc() from a delayed task drm/i915: Disable FBC across page-flipping drm/i915: Set persistent-mode for ILK/SNB framebuffer compression drm/i915: Use of a CPU fence is mandatory to update FBC regions upon CPU writes drm/i915: Remove vestigial pitch from post-gen2 FBC control routines drm/i915: Replace direct calls to vfunc.disable_fbc with intel_disable_fbc() drm/i915: Only export the generic intel_disable_fbc() interface drm/i915: Enable GPU reset on Ivybridge. ...
2011-07-14drm/i915: provide module parameter descriptionBen Widawsky1-0/+29
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-14drm/i915: add module parameter compiler hintsBen Widawsky2-22/+22
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-14drm/i915/bios: Avoid temporary allocation whilst searching for downclockChris Wilson1-59/+83
Alan Cox reported a missing check on the kmalloc return value for the allocation of a temporary mode used for searching for the LVDS downlock frequency. This allocation is roughly 200 bytes, a little too large to friviously place on the stack. However, we can simply use the few bytes we need stored within the original DVO timing data, skip the translation and do the compare directly between the timing data rather than on a mode, thus avoiding the need for any temporary allocations. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Cc: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-13drm/i915: Cache GT fifo count for SandyBridgeChris Wilson3-5/+12
The read back of the available FIFO entries is vital for system stability, but extremely costly. However, we only need a guide so as to avoid eating into the reserved entries and since we are the only consumer we can cache the read of the count from the last write. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-13i915: Fix opregion notificationsMatthew Garrett1-4/+11
opregion-based platforms will send ACPI video event 0x80 for a range of notification types for legacy compatibility. This is interpreted as a display switch event, which may not be appropriate in the circumstances. When we receive such an event we should make sure that the platform is genuinely requesting a display switch before passing that event through to userspace. Signed-off-by: Matthew Garrett <mjg@redhat.com> Tested-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-13drm/i915: TVDAC_STATE_CHG does not indicate successful load-detectKeith Packard1-20/+20
Do not use this bit to indicate that load detection has completed, instead just wait for vblank, at which point the load registers will have been updated. Signed-off-by: Keith Packard <keithp@keithp.com> Tested-by: Yi Sun <yi.sun@intel.com>
2011-07-13drm/i915: Select correct pipe during TV detectKeith Packard1-0/+6
Signed-off-by: Keith Packard <keithp@keithp.com> Tested-by: Yi Sun <yi.sun@intel.com>
2011-07-13Merge 3.0-rc7 into drm-core-nextDave Airlie25-297/+509
This pulls in all the drm fixes up to this point which are needed for some -next patches to work.
2011-07-13DRM: remove drm_pci_device_is_pcieJon Mason6-7/+7
drm_pci_device_is_pcie duplicates the funcationality of pci_is_pcie. Convert callers of the former to the latter. This has the side benefit of removing an unnecessary search in the PCI configuration space due to using a saved PCIe capability offset. [airlied: update for new callsite] Signed-off-by: Jon Mason <jdmason@kudzu.us> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-07-12Merge branch 'drm-intel-fixes' into drm-intel-nextKeith Packard3-5/+13
2011-07-12drm/i915/ringbuffer: Idling requires waiting for the ring to be emptyChris Wilson1-1/+1
...which is measured by the size and not the amount of space remaining. Waiting upon size-8, did one of two things. In the common case with more than 8 bytes available to write into the ring, it would return immediately. Otherwise, it would timeout given the impossible condition of waiting for more space than is available in the ring, leading to warnings such as: [drm:intel_cleanup_ring_buffer] *ERROR* failed to quiesce render ring whilst cleaning up: -16 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-12Revert "drm/i915: enable rc6 by default"Keith Packard1-1/+1
This reverts commit a51f7a66fb5e4af5ec4286baef940d06594b59d2. We still have a few Ironlake and Sandybridge machines which fail when RC6 is enabled. Better luck next release? Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-12drm/i915: Clean up i915_driver_load failure pathKeith Packard1-3/+11
i915_driver_load adds a write-combining MTRR region for the GTT aperture to improve memory speeds through the aperture. If i915_driver_load fails after this, it would not have cleaned up the MTRR. This shouldn't cause any problems, except for consuming an MTRR register. Still, it's best to clean up completely in the failure path, which is easily done by calling mtrr_del if the mtrr was successfully allocated. i915_driver_load calls i915_gem_load which register i915_gem_inactive_shrink. If i915_driver_load fails after calling i915_gem_load, the shrinker will be left registered. When called, it will access freed memory and crash. The fix is to unregister the shrinker in the failure path using code duplicated from i915_driver_unload. i915_driver_load also has some incorrect gotos in the error cleanup paths: * After failing to initialize the GTT (which cannot happen, btw, intel_gtt_get returns a fixed (non-NULL) value), it tries to free the uninitialized WC IO mapping. Fixed this by changing the target from out_iomapfree to out_rmmap Signed-off-by: Keith Packard <keithp@keithp.com> Tested-by: Lin Ming <ming.m.lin@intel.com>
2011-07-08drm/i915: Enable i915 frame buffer compression by defaultKeith Packard1-1/+1
We'll try again with the new fixes. Prepare to see this reverted when we get regression reports... Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-08drm/radeon/kms: clean up multiple crtc handling for evergreen+ (v2)Alex Deucher1-61/+98
evergreen+ asics have 2-6 crtcs. Don't access crtc registers for crtc regs that don't exist as they have very high latency and may cause problems on some asics. The previous code missed a few cases and was not fine grained enough (missed the 4 crtc case for example). Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=38800 v2: fix typo noticed by Chris Bandy <cbandy@jbandy.com> Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Reviewed-by: Michel Dänzer <michel@daenzer.net> Tested-by: Simon Farnsworth <simon.farnsworth@onelan.co.uk> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-07-08drm/i915: Share the common work of disabling active FBC before updatingChris Wilson2-60/+64
Upon review, all path share the same dependencies for updating the registers and so we can benefit from sharing the code and checking early. This removes the unsightly intel_wait_for_vblank() from the lowlevel functions and upon further analysis the only path that will require a wait is if we are performing an instantaneous transition between two valid FBC configurations. The page-flip path itself will have disabled FBC registers and will have waited for at least one vblank before finishing the flip and attempting to re-enable FBC. This wait can be accomplished simply by delaying the enable until after we are sure that a vblank will have passed, which we are already doing to make sure that the display is settled before enabling FBC. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-08drm/i915: Perform intel_enable_fbc() from a delayed taskChris Wilson3-2/+90
In order to accommodate the requirements of re-enabling FBC after page-flipping, but to avoid doing so and incurring the cost of a wait for vblank in the middle of a page-flip sequence, we defer the actual enablement by 50ms. If any request to disable FBC arrive within that interval, the enablement is cancelled and we are saved from blocking on the wait. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-08drm/i915: Disable FBC across page-flippingChris Wilson1-0/+2
Page-flipping updates the scanout address, nukes the FBC compressed image and so forces an FBC update so that the displayed image remains consistent. However, page-flipping does not update the FBC registers themselves, which remain pointing to both the old address and the old CPU fence. Future updates to the new front-buffer (scanout) are then undetected! This first approach to demonstrate the issue and highlight the fix, simply disables FBC upon page-flip (a recompression will be forced on every flip so FBC becomes immaterial) and then re-enables FBC in the page-flip finish work function, so that the FBC registers are now pointing to the new framebuffer and front-buffer rendering works once more. Ideally, we want to only re-enable FBC after page-flipping is complete, as otherwise we are just wasting cycles and power (with needless recompression) whilst the page-flipping application is still running. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33487 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-08drm/i915: Set persistent-mode for ILK/SNB framebuffer compressionChris Wilson2-0/+3
Persistent mode is intended for use with front-buffer rendering, such as X, where it is necessary to detect writes to the scanout either by the GPU or through the CPU's fence, and recompress the dirty regions on the fly. (By comparison to the back-buffer rendering, the scanout is always recompressed after a page-flip.) References: https://bugs.freedesktop.org/show_bug.cgi?id=33487 References: https://bugs.freedesktop.org/show_bug.cgi?id=31742 Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-08drm/i915: Use of a CPU fence is mandatory to update FBC regions upon CPU writesChris Wilson1-19/+14
...and this requirement is enforced by intel_update_fbc() so we can remove the later check from g4x_enable_fbc() and ironlake_enable_fbc(). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-08drm/i915: Remove vestigial pitch from post-gen2 FBC control routinesChris Wilson1-6/+2
The cfb_pitch was only used for 8xx_enable_fbc(), every later routine was just overwriting the value with itself thanks to a copy'n'paste error. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-08drm/i915: Replace direct calls to vfunc.disable_fbc with intel_disable_fbc()Chris Wilson1-8/+5
...to ensure that any pending FBC enable tasklet is cancelled. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-08drm/i915: Only export the generic intel_disable_fbc() interfaceChris Wilson4-34/+30
As the enable/disable routines will be gain additional complexity in future patches, it is necessary that all callers do not bypass the generic interface by calling into the chipset routines directly. to do this we make the chipset routines static, so there is no choice. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-08Merge branch 'drm-intel-fixes' into drm-intel-nextKeith Packard1-0/+1
2011-07-08drm/i915: Enable GPU reset on Ivybridge.Kenneth Graunke1-0/+1
According to the hardware documentation, GDRST is exactly the same as on Sandybridge. So simply enable the existing code. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-08Merge branch 'drm-intel-fixes' into drm-intel-nextKeith Packard6-32/+103
2011-07-08drm/i915/dp: manage sink power state if possibleJesse Barnes1-0/+35
On sinks with a DPCD rev of 1.1 or greater, we can send sink power management commands to address 0x600 per section 5.1.5 of the DisplayPort 1.1a spec. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-08drm/i915/dp: consolidate AUX retry codeJesse Barnes1-21/+30
When checking link status during a hot plug event or detecting sink presence, we need to retry 3 times per the spec (section 9.1 of the 1.1a DisplayPort spec). Consolidate the retry code into a native_aux_read_retry function for use by get_link_status and _detect. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-08drm/i915/dp: remove DPMS mode tracking from DPJesse Barnes1-5/+1
We currently use this when a hot plug event is received, only checking the link status and re-training if we had previously configured a link. However if we want to preserve the DP configuration across both hot plug and DPMS events (which we do for userspace apps that don't respond to hot plug uevents), we need to unconditionally check the link and try to bring it up on hot plug. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-08drm/i915/dp: try to read receiver capabilities 3 times when detectingJesse Barnes1-5/+10
If ->detect is called too soon after a hot plug event, the sink may not be ready yet. So try up to 3 times with 1ms sleeps in between tries to get the data (spec dictates that receivers must be ready to respond within 1ms and that sources should try 3 times). See section 9.1 of the 1.1a DisplayPort spec. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-08drm/i915/dp: read more receiver capability bits on hotplugJesse Barnes1-0/+11
When a hotplug event is received, we need to check the receiver cap bits in case they've changed (as they might with a hub or chain config). Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-08drm/i915/dp: use DP DPCD defines when looking at DPCD valuesJesse Barnes1-8/+10
Makes it easier to search for DP related constants. Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-08drm/i915/dp: retry link status read 3 times on failureJesse Barnes1-7/+13
Especially after a hotplug or power status change, the sink may not reply immediately to a link status query. So retry 3 times per the spec to really make sure nothing is there. See section 9.1 of the 1.1a DisplayPort spec. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-08drm/i915: use pipe bpp in DP link bandwidth calculationJesse Barnes1-5/+7
Now that we track bpp on a per-pipe basis, we can use the actual value rather than assuming 24bpp. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-08drm/i915: check for supported depth at fb init timeJesse Barnes1-0/+5
This will catch bad fb configs earlier. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Keith Packard <keithp@keithp.com>
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