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path: root/drivers/gpu/drm/nouveau/nvkm/engine
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2016-04-22Merge branch 'linux-4.6' of git://github.com/skeggsb/linux into drm-fixesDave Airlie1-0/+2
transform feedback fix. * 'linux-4.6' of git://github.com/skeggsb/linux: drm/nouveau/gr/gf100: select a stream master to fixup tfb offset queries
2016-04-22drm/nouveau/gr/gf100: select a stream master to fixup tfb offset queriesBen Skeggs1-0/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Cc: stable@vger.kernel.org
2016-04-06Merge branch 'linux-4.6' of git://github.com/skeggsb/linux into drm-fixesDave Airlie1-0/+17
Just a single fix to prevent GM20B systems hanging at boot. * 'linux-4.6' of git://github.com/skeggsb/linux: drm/nouveau/tegra: acquire and enable reference clock if needed
2016-04-06drm/nouveau/tegra: acquire and enable reference clock if neededAlexandre Courbot1-0/+17
GM20B requires an extra clock compared to GK20A. Add that information into the platform data and acquire and enable this clock if necessary. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-16nouveau: fix nv40_perfctr_next() cleanup regressionArnd Bergmann1-2/+4
gcc-6 warns about code in the nouveau driver that is obviously silly: drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c: In function 'nv40_perfctr_next': drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c:62:19: warning: self-comparison always evaluats to false [-Wtautological-compare] if (pm->sequence != pm->sequence) { The behavior was accidentally introduced in a patch described as "This is purely preparation for upcoming commits, there should be no code changes here.". As far as I can tell, that was true for the rest of that patch except for this one function, which has been changed to a NOP. This patch restores the original behavior. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: 8c1aeaa13954 ("drm/nouveau/pm: cosmetic changes") Reviewed-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-03-14drm/nouveau/clk/gm20b: add basic driverAlexandre Courbot1-0/+1
Add a basic clock driver that reuses the GK20A logic. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/volt: add GM20B driverAlexandre Courbot1-0/+1
Add basic GM20B volt driver that reuses the GK20A logic. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/ce/gm107: expose MaxwellDmaCopyABen Skeggs3-2/+58
The HW accepts KeplerDmaCopyA and MaxwellDmaCopyA classes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gm107: KeplerChannelGpfifoB, and 2048 channelsBen Skeggs3-1/+48
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk110: expose KeplerChannelGpfifoBBen Skeggs5-2/+85
This class supports a WFI method (0x0078) that's not present on the KeplerChannelGpfifoA class. The binary driver exposes both classes on these GPUs for some reason, though there doesn't appear to be any difference in the setup that's done for each (ie. even if you allocate GpfifoA, the WFI method will still work). We shall just expose GpfifoB, as I don't see a good reason to report the presence of both. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: submit NOP after all PBDMA_INTR_0, not just DEVICEBen Skeggs1-1/+2
Prevents the same interrupt from re-triggering forever. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: add vic plumbingBen Skeggs1-0/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: add sec plumbingBen Skeggs1-0/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: add nvdec plumbingBen Skeggs2-0/+3
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: add nvenc plumbingBen Skeggs2-7/+23
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: add msenc plumbingBen Skeggs1-0/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/core: add vic plumbingBen Skeggs3-0/+3
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/core: add nvdec plumbingBen Skeggs4-0/+5
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/core: add nvenc plumbingBen Skeggs4-21/+28
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/core: add msenc plumbingBen Skeggs2-0/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: make use of topology info during gpfifo constructionBen Skeggs1-47/+97
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: make use of topology info during fault recoveryBen Skeggs2-34/+26
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: make use of topology info when handling ctxsw timeoutBen Skeggs1-20/+9
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: read device topology information from hwBen Skeggs3-5/+103
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: cosmetic engine->runlist changesBen Skeggs4-48/+50
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: don't attempt recovery of unknown mmu enginesBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: identify fault-recovery members more clearlyBen Skeggs2-10/+12
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: rename spoon to pbdma, and move detection to oneinitBen Skeggs2-10/+14
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gf100: fix certain engines not being recovered after a faultBen Skeggs1-2/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gf100: don't attempt recovery of unknown mmu enginesBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gf100: identify fault-recovery members more clearlyBen Skeggs2-10/+12
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gf100: rename spooon to pbdma, and move detection to oneinitBen Skeggs2-12/+17
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/fuc: Store $r0 in interrupt handlerRoy Spliet14-932/+936
It's supposed to always be 0, but at least nv_iowr() temporarily violates this. Since the ih touches $r0, it should be stored. Signed-off-by: Roy Spliet <rs855@cam.ac.uk> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: kick channel upon removalAlexandre Courbot1-0/+1
A channel may still be processed by the PBDMA even after removal, unless it is properly kicked. Some chips are more sensible to this than others, with GM20B triggering the issue very easily (the PBDMA will try to fetch methods from the previously-removed channel after a new one is added). Make sure this cannot happen by kicking the channel right after it is disabled, and before the new runlist is submitted. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/device/pci: set as non-CPU-coherent on ARM64Alexandre Courbot1-1/+1
Without this buffer inconsistencies may appear between the CPU and GPU when using a PCI GPU on an ARM64 board. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: take runlist target into accountAlexandre Courbot1-1/+5
Bits 28:29 of RUNLIST_BASE specify the memory target of the runlist. Set it to 0x3 (SYS_MEM_NONCOHERENT) if the runlist object resides in system memory. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gf100: take runlist target into accountAlexandre Courbot1-1/+5
Bits 28:29 of RUNLIST_BASE specify the memory target of the runlist. Set it to 0x3 (SYS_MEM_NONCOHERENT) if the runlist object resides in system memory. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: fix chid bit maskXia Yang1-2/+2
Fix the channel id bit mask in FIFO schedule timeout error handling. FIFO_ENGINE_STATUS_NEXT_ID is bit 27:16 thus 0x0fff0000. FIFO_ENGINE_STATUS_ID is bit 11:0 thus 0x00000fff. Signed-off-by: Xia Yang <xiay@nvidia.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/instmem/gk20a: set DMA mask earlyAlexandre Courbot1-0/+9
DMA mask is typically set in nouveau_ttm_init(), but this function is called late during initialization and GK20A's instmem will have called DMA functions before this happens. Having a wrongly set DMA mask can result in the use of unneeded bounce buffers. Set it early to avoid this. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/gm206: remove implementation, it's now identical to gm200Ben Skeggs5-92/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/gm200: switch over to using sw_nonctx from firmwareBen Skeggs3-204/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/gm200: switch over to using sw_method_init from firmwareBen Skeggs3-358/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/gm200: switch over to using sw_bundle_init from firmwareBen Skeggs3-278/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/gm200: switch over to using sw_ctx from firmwareBen Skeggs3-317/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/iccsense: implement for ina209, ina219 and ina3221Karol Herbst1-0/+20
based on Martins initial work v3: fix ina2x9 calculations v4: don't kmalloc(0), fix the lsb/pga stuff v5: add a field to tell if the power reading may be invalid add nkvm_iccsense_read_all function check for the device on the i2c bus Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr>
2016-03-14drm/nouveau/subdev/iccsense: add new subdev for power sensorsMartin Peres2-63/+66
Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr>
2016-03-14drm/nouveau/secboot/gm20b: add secure boot supportAlexandre Courbot2-3/+7
Add secure boot support for the GM20B chip found in Tegra X1. Secure boot on Tegra works slightly differently from desktop, notably in the way the WPR region is set up. In addition, the firmware bootloaders use a slightly different header format. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/secboot/gm200: add secure-boot supportAlexandre Courbot2-7/+4
Add secure-boot for the dGPU set of GM20X chips, using the PMU as the high-secure falcon. This work is based on Deepak Goyal's initial port of Secure Boot to Nouveau. v2. use proper memory target function Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/gm200: do not load firmware for secure falconsAlexandre Courbot1-6/+15
Secure falcons' firmware is managed by secboot. Do not load it in GR for them. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/gf100: add support for securely-managed falconsAlexandre Courbot1-4/+24
Start securely-managed falcons using secboot functions since the process for them is different from just writing CPUCTL. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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