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path: root/drivers/gpu/drm/i915
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2010-12-17drm/i915: Add support for precise vblank timestamping (v2)Mario Kleiner5-6/+119
v2: Change IS_IRONLAKE to IS_GEN5 to adapt to 2.6.37 This patch adds new functions for use by the drm core: .get_vblank_timestamp() provides a precise timestamp for the end of the most recent (or current) vblank interval of a given crtc, as needed for the DRI2 implementation of the OML_sync_control extension. It is a thin wrapper around the drm function drm_calc_vbltimestamp_from_scanoutpos() which does almost all the work. .get_scanout_position() provides the current horizontal and vertical video scanout position and "in vblank" status of a given crtc, as needed by the drm for use by drm_calc_vbltimestamp_from_scanoutpos(). The patch modifies the pageflip completion routine to use these precise vblank timestamps as the timestamps for pageflip completion events. This code has been only tested on a HP-Mini Netbook with Atom processor and Intel 945GME gpu. The codepath for (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) gpu's has not been tested so far due to lack of hardware. Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-15drm/i915: Add frame buffer compression on SandybridgeYuanhan Liu4-3/+20
Add frame buffer compression on Sandybridge. The method is similar to Ironlake, except that two new registers of type GTTMMADR must be written with the right fence info. Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-15drm/i915: Add self-refresh support on SandybridgeYuanhan Liu3-18/+334
Add the support of memory self-refresh on Sandybridge, which is now support 3 levels of watermarks and the source of the latency values for watermarks has changed. On Sandybridge, the LP0 WM value is not hardcoded any more. All the latency value is now should be extracted from MCHBAR SSKPD register. And the MCHBAR base address is changed, too. For the WM values, if any calculated watermark values is larger than the maximum value that can be programmed into the associated watermark register, that watermark must be disabled. Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> [ickle: remove duplicate compute routines and fixup for checkpatch] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-15drm/i915: Wait for vblank before unpinning old fbChris Wilson1-1/+3
Be paranoid and ensure that the vblank has passed and the scanout has switched to the new fb, before unpinning the old one and possibly tearing down its PTEs. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-15Revert "drm/i915: Avoid using PIPE_CONTROL on Ironlake"Chris Wilson2-3/+162
Restore PIPE_CONTROL once again just for Ironlake, as it appears that MI_USER_INTERRUPT does not have the same coherency guarantees, that is on Ironlake the interrupt following a GPU write is not guaranteed to arrive after the write is coherent from the CPU, as it does on the other generations. Reported-by: Zhenyu Wang <zhenyuw@linux.intel.com> Reported-by: Shuang He <shuang.he@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32402 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-15drm/i915/bios: Reverse order of 100/120 Mhz SSC clocksChris Wilson1-1/+1
Fixes the lack of output on the LVDS panel of the Lenovo U160. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31596 Reported-and-tested-by: Dirk Gouders <gouders@et.bocholt.fh-gelsenkirchen.de> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-14drm/i915: Pass clock limits down to PLL matcherChris Wilson1-18/+16
As we already know the limits for the hardware clock, pass it down rather than recomputing them for each match. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-14drm/i915: Poll for seqno completion if IRQ is disabledChris Wilson1-2/+4
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32288 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-14drm/i915/ringbuffer: Make IRQ refcnting atomicChris Wilson4-46/+56
In order to enforce the correct memory barriers for irq get/put, we need to perform the actual counting using atomic operations. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-09Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson5-57/+47
2010-12-09drm/i915/sdvo: Only use the SDVO pin if it is in the valid rangeChris Wilson1-3/+6
BIOSes. Can't live without them (apparently), definitely can't live with them. Reported-by: Ben Gamari <bgamari@gmail.com> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=24312 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-09drm/i915: Enable RC6 autodownclocking on SandybridgeChris Wilson2-0/+148
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-09drm/i915: Terminate the FORCE WAKE after we have finished readingChris Wilson3-9/+35
Once we have read the value out of the GT power well, we need to remove the FORCE WAKE bit to allow the system to auto-power down. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-09drm/i915/gtt: Clear the cachelines upon resumeChris Wilson1-1/+2
Required for my pineview system to not barf after resuming. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-09drm/i915: Restore GTT mapping first upon resumeChris Wilson1-1/+6
As suggested by Daniel Vetter, this is a safeguard should any of the registers cause reference to PTE entries. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-09drm/i915: driver.suspend and .resume are always setChris Wilson1-5/+0
So we can remove the repeated initialisation. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-09drm/i915: Mark the user reloc error paths as unlikelyChris Wilson1-9/+8
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-09drm/i915: Eliminate drm_gem_object_lookup during relocationChris Wilson2-27/+129
As we provide a list of all objects that will be accessed from the batchbuffer, we can build a lut of the handles associated with those objects for this invocation and use that to avoid the overhead of looking up those objects again for every relocation. The cost of building and searching a small hash table is much less than that of acquiring a spinlock, searching a radix tree and manipulating an atomic refcnt per relocation. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-09drm/i915: Re-arm the idle timers if the device is still busyChris Wilson1-2/+16
Don't post a downclocking task if the device is still active when the idle timer fires. A pathological process could queue up several seconds worth of processing and then go to sleep, during which time the idle timer would kick in and downclock the GPU. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-09drm/i915/ringbuffer: Handle wrapping of the autoreported HEADChris Wilson2-13/+11
If the tail advances beyond the autoreport HEAD value, then we need to fallback to an uncached read of the HEAD register in order to ascertain the correct amount of remaining space in the ringbuffer. Reported-by: Fang, Xun <xunx.fang@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32259 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-08drm/i915/dp: Fix I2C/EDID handling with active DisplayPort to DVI converterDavid Flynn1-7/+30
The DisplayPort standard (1.1a) states that: The I2C-over-AUX Reply field is valid only when Native AUX CH Reply field is AUX_ACK (00). When Native AUX CH Reply field is not 00, then, I2C-over-AUX Reply field must be 00 and be ignored. This fixes broken EDID reading when using an active DisplayPort to duallink DVI converter. If the AUX CH replier chooses to defer the transaction, a short read occurs and erroneous data is returned as the i2c reply due to a lack of length checking and failure to check for AUX ACK. As a result, broken EDIDs can look like: 0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef 00: bc bc bc ff bc bc bc ff bc bc bc ac bc bc bc 45 ???.???.???????E 10: bc bc bc 10 bc bc bc 34 bc bc bc ee bc bc bc 4c ???????4???????L 20: bc bc bc 50 bc bc bc 00 bc bc bc 40 bc bc bc 00 ???P???.???@???. 30: bc bc bc 01 bc bc bc 01 bc bc bc a0 bc bc bc 40 ???????????????@ 40: bc bc bc 00 bc bc bc 00 bc bc bc 00 bc bc bc 55 ???.???.???.???U 50: bc bc bc 35 bc bc bc 31 bc bc bc 20 bc bc bc fc ???5???1??? ???? 60: bc bc bc 4c bc bc bc 34 bc bc bc 46 bc bc bc 00 ???L???4???F???. 70: bc bc bc 38 bc bc bc 11 bc bc bc 20 bc bc bc 20 ???8??????? ??? 80: bc bc bc ff bc bc bc ff bc bc bc ff bc bc bc ff ???.???.???.???. ... which can lead to: [drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder [drm:drm_edid_block_valid] *ERROR* Raw EDID: <3>30 30 30 30 30 30 30 32 38 32 30 32 63 63 31 61 000000028202cc1a <3>28 00 02 8c 00 00 00 00 18 00 00 00 00 00 00 00 (............... <3>20 4c 61 73 74 20 62 65 61 63 6f 6e 3a 20 33 32 Last beacon: 32 <3>32 30 6d 73 20 61 67 6f 46 00 05 8c 00 00 00 00 20ms agoF....... <3>36 00 00 00 00 00 00 00 00 0c 57 69 2d 46 69 20 6.........Wi-Fi <3>52 6f 75 74 65 72 01 08 82 84 8b 96 24 30 48 6c Router......$0Hl <3>03 01 01 06 02 00 00 2a 01 00 2f 01 00 32 04 0c .......*../..2.. <3>12 18 60 dd 09 00 10 18 02 00 00 01 00 00 18 00 ..`............. Signed-off-by: David Flynn <davidf@rd.bbc.co.uk> [ickle: fix up some surrounding checkpatch warnings] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
2010-12-08drm/i915: i915 cannot provide switcher services.Dave Airlie1-34/+0
it has a DSM but the switcher is done via WMI. Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-12-08drm/i915: Disable renderctx powersaving support for IronlakeChris Wilson1-1/+1
... still causes a failure during suspend. Reported-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-08Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson4-61/+91
Conflicts: drivers/gpu/drm/i915/i915_gem.c drivers/gpu/drm/i915/intel_dp.c
2010-12-08drm/i915/dp: Only apply the workaround if the select is still activeChris Wilson1-2/+6
As we may try to power down the link at various times, it is not necessarily still coupled with an encoder and so we must be careful not to depend upon an operation that is only valid when the link is still attached to a pipe. Fixes regression in 5bddd17. Reported-and-tested-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org [after applying 5bddd17]
2010-12-07drm/i915: Emit a request to clear a flushed and idle ring for unbusy boChris Wilson1-1/+11
In order for bos to retire eventually, a request must be sent down the ring. This is expected, for example, by occlusion queries for which mesa will wait upon (whilst running glean) before issuing more batches and so the normal activity upon the ring is suspended and we need to emit a request to clear the idle ring. Reported-by: Jinjin, Wang <jinjin.wang@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30380 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-06drm/i915: Wait for the bo if a display flip is pipelined on the other ringChris Wilson1-1/+1
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-06drm/i915: Only emit a flush if there is an outstanding gpu writeChris Wilson1-2/+3
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-06drm/i915: Completely disable fence pipelining.Chris Wilson1-2/+4
I'm still seeing tiling corruption of PutImage and CopyArea (I think) under mutter on pnv, so obviously the pipelining logic is deeply flawed. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-06drm/i915: Uncouple render/power ctx before suspendingChris Wilson3-26/+36
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-06drm/i915: Ignore fenced commands for gpu access on gen4Chris Wilson1-11/+16
Userspace should not have been declaring that it needed fenced GPU access with gen4+ as those GPUs have no fenced commands, but to be on the safe side it is easier to ignore userspace in case they did. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-06drm/i915: caps.has_rc6 is no longer used, remove it.Chris Wilson3-6/+3
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-06drm/i915: Power Context register is only available for gen4 mobilesChris Wilson1-1/+1
The ability to save the hardware context upon powering down the render clock through PWRCTXA is only available on a couple of gen4 chipsets. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-06drm/i915: Avoid using PIPE_CONTROL on IronlakeChris Wilson2-159/+4
The workaround is hideous and we are using the STORE_DWORD on all other generations on all other rings, so use for the gen5 render ring as well. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-06drm/i915/lvds: Always restore panel-fitter when enabling the LVDSChris Wilson1-44/+54
Linus Torvalds pointed out that our code was unbalanced when powering on the panel with respect to the power off sequence in that we were failing to restore the panel-fitter. The consequence of this would be that across a simple DPMS off/on for a non-native mode, without an intervening modeset, the panel fitter would remain disabled and the output would shift on the panel. Reported-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-06drm/i915/ringbuffer: Only print an error on the second attempt to reset headChris Wilson1-14/+16
There's not much we can do here but hope for the best. However the first failure happens quite frequently and if often remedied by the second attempt to reset HEAD. So only print the error if that attempt also fails. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=19802 Reported-by: Thomas Meyer <thomas@m3y3r.de> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
2010-12-05drm/i915/dp: Trivial code tidyChris Wilson1-3/+3
Locally scope the crtc to where it is used. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson1-0/+3
Immediate merge for the conflicting introduction of HAS_COHERENT_RINGS. Conflicts: drivers/gpu/drm/i915/i915_dma.c include/drm/i915_drm.h
2010-12-05drm/i915: announce to userspace that the bsd ring is coherentDaniel Vetter1-0/+3
Otherwise we can't really fix the abi-braindeadness of forcing libva to manually wait for rendering when switching rings. Which in turn makes implementing hw semaphores a pointless exercise (at least for ironlake). [Also added the relaxed fencing param to explain the jump in numbering - relaxed fencing is in -next.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson1-13/+59
2010-12-05drm/i915: Enable self-refresh for IronlakeChris Wilson1-1/+1
We disabled this a while ago as it was inexplicably broken. However, it now appears to work... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Implement GPU semaphores for inter-ring synchronisation on SNBChris Wilson14-439/+648
The bulk of the change is to convert the growing list of rings into an array so that the relationship between the rings and the semaphore sync registers can be easily computed. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Be paranoid and bail on resetting if we can't take the lock.Chris Wilson1-1/+2
This will declare the machine wedged, but is better than truly wedging the machine. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Allow LVDS to be on pipe A for Ironlake+Chris Wilson1-0/+2
Previously we enabled this for gen4, only to have to revert it due to it causing a large number of spurious wakeups. Try again hoping that the hardware has become more sane in the mean time... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Re-enable RC6 for power-savings.Chris Wilson1-1/+0
Let's see if we've successfully cleared up all the bugs from last time... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Enable CB tuning of the Display PLLChris Wilson2-1/+17
Magic numbers from the specs. This is supposed to allow the PLL some variance to improve jitter performance and VCO headroom across manufacturing and environmental variations. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Explain why we need to write DPLL twiceChris Wilson1-5/+5
... it's because setting the Pixel Multiply bits only takes effect once the PLL is enabled and stable. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915/lvds: Connect the PWM to the LVDS pipeChris Wilson1-3/+11
... and do not just assume to always use pipe B. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-04drm/i915: Factor in pixel-repeat in FDI M/N calculationChris Wilson1-0/+3
Fixes the modesetting on the secondary panel of the Libretto W100 and presumably many more Ironlake laptops with SDVO LVDS displays. Reported-and-tested-by: Matthew Willoughby <mattfredwill@gmail.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
2010-12-04drm/i915: Death to the unnecessary 64bit divideChris Wilson1-13/+5
Use the hardware DDA to calculate the ratio with as much accuracy as is possible. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
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