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path: root/drivers/gpu/drm/i915
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2009-11-25ACPICA: Add post-order callback to acpi_walk_namespaceLin Ming1-1/+1
The existing interface only has a pre-order callback. This change adds an additional parameter for a post-order callback which will be more useful for bus scans. ACPICA BZ 779. Also update the external calls to acpi_walk_namespace. http://www.acpica.org/bugzilla/show_bug.cgi?id=779 Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
2009-11-18drm: Add async event synchronization for drmWaitVblankKristian Høgsberg1-0/+1
This patch adds a new flag to the drmWaitVblank ioctl, which asks the drm to return immediately and notify userspace when the specified vblank sequence happens by sending an event back on the drm fd. The event mechanism works with the other flags supported by the ioctls, specifically, the vblank sequence can be specified relatively or absolutely, and works for primary and seconday crtc. The signal field of the vblank request is used to provide user data, which will be sent back to user space in the vblank event. Signed-off-by: Kristian Høgsberg <krh@redhat.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-11-12drm/i915: Add more registers save/restore for Ironlake suspendZhenyu Wang2-1/+47
Add more display registers save/restore to fix unstable issues during S4 testing on Ironlake. And DPLL_B_MD should not be restored on Ironlake. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-12drm/i915: Fix IRQ stall issue on IronlakeZou, Nanhai1-1/+9
The master irq control in DE must be disabled before irq handling, and enable after the process. This fixes the irq stall issue on Ironlake. Cc: Stable Team <stable@kernel.org> Signed-off-by: Zou, Nanhai <nanhai.zou@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06Merge remote branch 'airlied/drm-next' into drm-intel-nextEric Anholt1-0/+1
2009-11-06drm/i915: fix get_core_clock_speed for G33 class desktop chipsDaniel Vetter1-1/+1
Somehow the case for G33 got dropped while porting from ums code. This made a 400MHz chip into a 133MHz one which resulted in the unnecessary enabling of double wide pipe mode which in turn screwed up the overlay code. Nothing else (than the overlay code) seems to be affected. This fixes fdo.org bug #24835 Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06drm/i915: Add display hotplug event on IronlakeZhenyu Wang3-4/+34
Enable display hotplug irqs from Ibex Peak (PCH). Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06drm/i915: Add ACPI OpRegion support for IronlakeZhao Yakui4-8/+96
Add the support of ACPI opregion on Ironlake so that the backlight brightness can be adjusted by using ACPI interface >/sys/class/backlight/acpi_video0/brightness Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Tested-by: Zhao Yakui <yakui.zhao@intel.com> [zhenyuw: cleanups, fix typo for checking GSE irq and convert to current irq handling logic.] Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06drm/i915: enable self-refresh on 965Jesse Barnes1-4/+28
Need to calculate the SR watermark and enable it. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06drm/i915: Support 30 bit depth modesKristian Høgsberg2-1/+5
Signed-off-by: Kristian Høgsberg <krh@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06drm/i915: debugfs interface to manually reset the GPUChris Wilson1-1/+115
Create a /debug/dri/%d/i915_wedged file to display the current wedged status, and to enable setting that value. On an i965, this will also trigger a GPU reset. Useful in order to attempt to recover from some error conditions that are not currently caught by the automatic hang detection code. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06drm/i915: Use a single thread workqueueChris Wilson1-1/+1
Our work is serialised so allocating per-cpu workqueues is overkill and a waste of resources. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06drm/i915: Replace DRM_DEBUG with DRM_DEBUG_KMS in DVO output code.Zhao Yakui5-55/+61
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06drm/i915: Enable the SDVO debug code, which is now under DEBUG_KMS.Eric Anholt1-10/+0
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06drm/i915: Replace DRM_DEBUG with DRM_DEBUG_KMSZhao Yakui8-89/+99
Replace the DRM_DEBUG with DRM_DEBUG_KMS in output device code. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06drm/i915: Replace DRM_DEBUG with DRM_DEBUG_DRIVERZhao Yakui6-36/+38
Replace the DRM_DEBUG with DRM_DEBUG_DRIVER in generic i915 driver. Then the debug info can be obtained by adding the boot option of "drm.debug=0x02". At the same time the debug info in increase/decrease clock is also printed by using DRM_DEBUG_DRIVER instead of DRM_DEBUG_KMS. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06drm/i915: overlay: kill one more unnecessary uninterruptible sleepDaniel Vetter1-10/+7
I've simply overlooked one case in the conversion to interruptible sleeps. Rectify this. Also delete a leftover debug printk. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06drm/i915: kill i915_lp_ring_syncDaniel Vetter2-19/+0
It's not needed anymore. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06drm/i915: implement interruptible sleeps in the overlay codeDaniel Vetter3-34/+159
At least for the common case of userspace ioctls. When doing a modeset operation, the wait is still uninterruptible. But considering that failing to turn off the overlay when switching off the crtc it's running on hangs the chip, it doesn't complicate matters _very_ much. There's just an unkillable X in addition to a black screen. BUG() about it and explain in the code. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06drm/i915: implement fastpath for overlay flip waitingDaniel Vetter4-11/+41
As long as the gpu can keep up, neither the cpu (waiting for gpu) nore the gpu (waiting for vblank to do an overlay flip) stalls. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06drm/i915: fully switch off overlay when not in useDaniel Vetter1-2/+1
Now that the cache flushing of the memory based overlay regs works, we can safely switch off the overlay. Beforehand it was only disabled (like in userspace). Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06drm/i915: implement drmmode overlay support v4Daniel Vetter7-3/+1361
This implements intel overlay support for kms via a device-specific ioctl. Thomas Hellstrom brought up the idea of a general ioctl (on dri-devel). We've reached the conclusion that such an infrastructure only makes sense when multiple kms overlay implementations exists, which atm don't (and it doesn't look like this is gonna change). Open issues: - Runs in sync with the gpu, i.e. unnecessary waiting. I've decided to wait on this because the hw tends to hang when changing something in this area. I left some dummy functions as infrastructure. - polyphase filtering uses a static table. - uses uninterruptible sleeps. Unfortunately the alternatives may unnecessarily wedged the hw if/when we timeout too early (and userspace only overloaded the batch buffers with stuff worth a few secs of gpu time). Changes since v1: - fix off-by-one misconception on my side. This fixes fullscreen playback. Changes since v2: - add underrun detection as spec'ed for i965. - flush caches properly, fixing visual corruptions. Changes since v4: - fix up cache flushing of overlay memory regs. - killed require_pipe_a logic - it hangs the chip. Tested-By: diego.abelenda@gmail.com (on a 865G) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> [anholt: Resolved against the MADVISE ioctl going in before this one] Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06drm/i915: kill superflous IS_I855 macroDaniel Vetter2-3/+2
It is identical to I85X. Use that one instead. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> [anholt: fix conflicts against the display function pointer stuff] Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06drm/i915: add i915_lp_ring_sync helperDaniel Vetter2-10/+40
This just waits until the hw passed the current ring position with cmd execution. This slightly changes the existing i915_wait_request function to make uninterruptible waiting possible - no point in returning to userspace while mucking around with the overlay, that piece of hw is just too fragile. Also replace a magic 0 with the symbolic constant (and kill the then superflous comment) while I was looking at the code. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06drm/i915: add render standby supportJesse Barnes4-3/+54
Render standy allows the GPU to power down the render unit when idle. In order for this to work, it needs a page of graphics memory to save state. This patch allocates that page and enables the feature on supported chipsets. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06drm/i915: HDMI hardware workaround for IronlakeZhenyu Wang1-4/+22
This brings some hardware workaround for HDMI port on PCH (Ibex Peak), which fixes unstable issues like during rotation. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06drm/i915: Fix and cleanup DPLL calculation for IronlakeZhenyu Wang1-9/+6
When the ideal error range can't be reached, this will safely use a most closed one. Clean up some dumb codes in DPLL function too. This fixes DPLL clock issue against one monitor at 1680x1050@60hz. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06drm/i915: Avoid potential sleep whilst holding spinlockChris Wilson1-2/+2
Miles Lane reported the following error: 2 locks held by cat/4179: #0: (&p->lock){+.+.+.}, at: [<c10a3884>] seq_read+0x25/0x315 #1: (&dev_priv->mm.active_list_lock){+.+...}, at: [<c119a854>] i915_batchbuffer_info+0x2b/0x124 Pid: 4179, comm: cat Not tainted 2.6.32-rc5-git1 #2 Call Trace: [<c104874f>] ? __debug_show_held_locks+0x1e/0x20 [<c1023fb0>] __might_sleep+0xf0/0xf7 [<c101c393>] kmap+0x17/0x58 [<c119a8d6>] i915_batchbuffer_info+0xad/0x124 [<c10a39bf>] seq_read+0x160/0x315 [<c108fb8c>] ? rw_verify_area+0x98/0xbb [<c10a385f>] ? seq_read+0x0/0x315 [<c1090331>] vfs_read+0x75/0xa9 [<c10903f9>] sys_read+0x3b/0x5d [<c1002a8f>] sysenter_do_call+0x12/0x36 The fix is relatively simple, use the atomic variants of kmap() that avoid the potential sleep. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Miles Lane <miles.lane@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-04Merge branch 'for-linus' of ↵Linus Torvalds8-95/+486
git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: drm/i915: Ironlake suspend/resume support drm/i915: kill warning in intel_find_pll_g4x_dp drm/i915: update watermarks before enabling PLLs drm/i915: add FIFO watermark support for G4x drm/i915: quiet DP i2c init drm/i915: fix panel fitting filter coefficient select for Ironlake drm/i915: fix to setup display reference clock control on Ironlake drm/i915: Install a fence register for fbc on g4x drm/i915: save/restore BLC histogram control reg across suspend/resume drm/i915: Fix FDI M/N setting according with correct color depth drm/i915: disable powersave feature for Ironlake currently drm/i915: Fix render reclock availability detection. drm/i915: Save and restore the GM45 FBC regs on suspend and resume. drm/i915: Set the LVDS_BORDER when using LVDS scaling mode drm/i915: disable FBC for Pineview, fixing a boot hang.
2009-11-02i915: fix intel graphics suspend breakage due to resume/lid event confusionLinus Torvalds3-8/+24
In commit c1c7af60892070e4b82ad63bbfb95ae745056de0 ("drm/i915: force mode set at lid open time") the intel graphics driver was taught to restore the LVDS mode on lid open. That caused problems with interaction with the suspend/resume code, which commonly runs at the same time (suspend is often caused by the lid close event, while lid open is commonly a resume event), which was worked around with in commit 06891e27a9b5dba5268bb80e41a283f51335afe7 ("drm/i915: fix suspend/resume breakage in lid notifier"). However, in the meantime the lid event code had also grown a user event notifier (commit 06324194eee97a51b5f172270df49ec39192d6cc: "drm/i915: generate a KMS uevent at lid open/close time"), and now _that_ causes problems with suspend/resume and some versions of Xorg reacting to those uevents by setting the mode. So this effectively reverts that commit 06324194ee, and makes the lid open protection logic against suspend/resume more explicit. This fixes at least one laptop. See http://bugzilla.kernel.org/show_bug.cgi?id=14484 for more details. Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Riccardo Magliocchetti <riccardo.magliocchetti@gmail.com> Cc: Eric Anholt <eric@anholt.net> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-10-26drm: Add async event synchronization for drmWaitVblankKristian Høgsberg1-0/+1
This patch adds a new flag to the drmWaitVblank ioctl, which asks the drm to return immediately and notify userspace when the specified vblank sequence happens by sending an event back on the drm fd. The event mechanism works with the other flags supported by the ioctls, specifically, the vblank sequence can be specified relatively or absolutely, and works for primary and seconday crtc. The signal field of the vblank request is used to provide user data, which will be sent back to user space in the vblank event. Signed-off-by: Kristian Høgsberg <krh@redhat.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-10-23drm/i915: Ironlake suspend/resume supportZhenyu Wang2-55/+256
This adds registers save/restore for Ironlake to make suspend work. Signed-off-by: Guo, Chaohong <chaohong.guo@intel.com> [zhenyuw: some code re-orgnization, and add more save/restore for FDI link and transcoder registers, also fix palette register for Ironlake] Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-23drm/i915: kill warning in intel_find_pll_g4x_dpJesse Barnes1-0/+1
Initialize clock.vco to silence gcc. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-23drm/i915: update watermarks before enabling PLLsJesse Barnes1-1/+2
When coming back from DPMS or turning on a display, make sure we have the watermarks set up before turning on the display plane, otherwise we may get underruns. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Dirk Hohndel <hohndel@infradead.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-23drm/i915: add FIFO watermark support for G4xJesse Barnes2-8/+84
Turns out G4x needs to have sensible watermarks set, especially for self-refresh enabled modes. Add support for it. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Dirk Hohndel <hohndel@infradead.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-19drm/i915: quiet DP i2c initZhenyu Wang1-1/+1
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-19drm/i915: fix panel fitting filter coefficient select for IronlakeZhenyu Wang2-1/+6
Must set filter selection as hardcoded coefficients for medium 3x3 filtering, which matches vbios setting for Ironlake. This fixes display corrupt issue on HP arrandale with new vbios. Cc: Stable Team <stable@kernel.org> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-19drm/i915: fix to setup display reference clock control on IronlakeZhenyu Wang2-2/+42
For new stepping of PCH, the display reference clock is fully under driver's control. This one trys to setup all needed reference clock for different outputs. Older stepping of PCH chipset should be ignoring this. This fixes output failure issue on newer PCH which requires driver to take control of reference clock enabling. Cc: Stable Team <stable@kernel.org> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-15drm/i915: Install a fence register for fbc on g4xChris Wilson1-3/+5
To enable framebuffer compression on a g4x, we not only need the buffer to tiled (X only), we also need to hold a fence register for the buffer. Currently we only install a fence register for pre-i965s when setting up the scanout buffer. Rather than adding some convoluted logic to g4x_enable_fbc() to acquire a fence register, and perhaps to g4x_disable_fbc() to release it again, we can extend the acquisition during setup to all chipsets. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-15drm/i915: save/restore BLC histogram control reg across suspend/resumeJesse Barnes3-0/+5
Turns out some machines, like the ThinkPad X40 don't come back if you don't save/restore this register. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-13drm/i915: Fix FDI M/N setting according with correct color depthZhenyu Wang2-4/+32
FDI M/N calculation hasn't taken the current pipe color depth into account, but always set as 24bpp. This one checks current pipe color depth setting, and change FDI M/N calculation a little to use bits_per_pixel first, then convert to bytes_per_pixel later. This fixes display corrupt issue on Arrandle LVDS with 1600x900 panel in 18bpp dual-channel mode. Cc: Stable Team <stable@kernel.org> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-13drm/i915: disable powersave feature for Ironlake currentlyZhenyu Wang2-3/+13
Until we figure out the right setting for powersave features on Ironlake, disable it for now. Also disable watermark update, which has new registers for it on Ironlake too. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> [anholt: Resolved against the Pineview FBC changes] Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-13drm/i915: Fix render reclock availability detection.Andy Lutomirski1-8/+6
If the device didn't support EDP, we would bail out too soon. Signed-off-by: Andy Lutomirski <luto@mit.edu> [anholt: Pulled this patch out of the patch for adding quirks to enable reclocking.] Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-13drm/i915: Save and restore the GM45 FBC regs on suspend and resume.Jesse Barnes2-8/+19
This hasn't fixed the regressions we were testing against, but clearly should be required. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-13drm/i915: Set the LVDS_BORDER when using LVDS scaling modeZhao Yakui4-1/+15
According to the spec the LVDS_BORDER_ENABLE bit decides whether the border data should be included in the active display and data sent to the panel. Border should be used when in VGA centered (un-scaled) mode or when scaling a 4:3 source image to a wide screen panel (typical 16:9). So when the LVDS scaling is used, decide whether the LVDS_BORDER should be enabled or not according to the current scaling mode. At the same time fix the typo error in LVDS center scaling mode. https://bugs.freedesktop.org/show_bug.cgi?id=23789 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> tested-by: Zhao Jian <jian.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-13drm/i915: disable FBC for Pineview, fixing a boot hang.Shaohua Li2-3/+2
Pineview doesn't have this FBC mechanism, so this code doesn't apply. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-09Merge branch 'drm-intel-next' of ↵Linus Torvalds8-32/+49
git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel * 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: drm/i915: Initialize HDMI outputs as HDMI connectors, not DVI. drm/i915: Multiply the refresh by 1000 in TV mode validatiion drm/i915: Enable irq to trace batch buffer completion. drm/i915: batch submit seqno off-by-one. drm/i915: Record device minor rather than pointer in TRACE_EVENT drm/i915: Don't call intel_update_fbc from intel_crtc_cursor_set
2009-10-08Merge branch 'drm-next' of ../drm-next into drm-linusDave Airlie3-2/+21
conflict in radeon since new init path merged with vga arb code. Conflicts: drivers/gpu/drm/radeon/radeon.h drivers/gpu/drm/radeon/radeon_asic.h drivers/gpu/drm/radeon/radeon_device.c
2009-10-06drm/fb: add more correct 8/16/24/32 bpp fb support.Dave Airlie3-1/+18
The previous patches had some unwanted side effects, I've fixed the lack of 32bpp working, and fixed up 16bpp so it should also work. this also adds the interface to allow the driver to set a preferred console depth so for example low memory rn50 can set it to 8bpp. It also catches 24bpp on cards that can't do it and forces 32bpp. Tested on r100/r600/i945. Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-10-05drm/fb: add setcmap and fix 8-bit support.Dave Airlie2-1/+3
This adds support for the setcmap api and fixes the 8bpp support at least on radeon hardware. It adds a new load_lut hook which can be called once the color map is setup. Signed-off-by: Dave Airlie <airlied@redhat.com>
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