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path: root/drivers/gpu/drm/i915/intel_pm.c
AgeCommit message (Expand)AuthorFilesLines
2014-11-07drm/i915/skl: Read the Memory Latency Values for WM computationPradeep Bhat1-6/+70
2014-10-24drm/i915/chv: Use 16 and 32 for low and high drain latency precision.Rodrigo Vivi1-15/+25
2014-10-24drm/i915/bdw: Remove BDW preproduction W/As until C stepping.Rodrigo Vivi1-10/+0
2014-10-24drm/i915: Do not export RC6p and RC6pp if they don't existRodrigo Vivi1-5/+10
2014-10-21Merge branch 'drm-intel-next-fixes' into drm-intel-nextDaniel Vetter1-197/+46
2014-10-03drm/i915: s/pm._irqs_disabled/pm.irqs_enabled/Daniel Vetter1-1/+0
2014-10-01drm/i915: Extract intel_runtime_pm.cDaniel Vetter1-1160/+0
2014-10-01Merge branch 'topic/skl-stage1' into drm-intel-next-queuedDaniel Vetter1-2/+28
2014-09-29drm/i915: Don't spam dmesg with rps messages on vlv/chvVille Syrjälä1-6/+7
2014-09-29Revert "drm/i915/bdw: BDW Software Turbo"Daniel Vetter1-191/+39
2014-09-29drm/i915: Minimize the huge amount of unecessary fbc sw cache clean.Rodrigo Vivi1-1/+1
2014-09-24drm/i915/skl: Move gen9 pm initialization into its own branchDamien Lespiau1-3/+3
2014-09-24drm/i915/skl: Implement WaDisableDgMirrorFixInHalfSliceChicken5:sklDamien Lespiau1-0/+8
2014-09-24drm/i915/skl: Implement Wa4x4STCOptimizationDisable:sklDamien Lespiau1-0/+4
2014-09-24drm/i915/skl: Implement WaDisableSDEUnitClockGating:sklDamien Lespiau1-0/+8
2014-09-24drm/i915/skl: Restore pipe B/C interruptsSatheeshakrishna M1-1/+1
2014-09-24drm/i915/skl: Provide a placeholder for init_clock_gating()Damien Lespiau1-0/+6
2014-09-23drm/i915: add SW tracking to FBC enablingPaulo Zanoni1-11/+20
2014-09-23drm/i915: extract intel_init_fbc()Paulo Zanoni1-22/+28
2014-09-19drm/i915: Avoid reading fbc registers in vain when fbc was never enabled.Rodrigo Vivi1-0/+6
2014-09-19drm/i915: Only flush fbc on sw when fbc is enabled.Rodrigo Vivi1-0/+3
2014-09-19drm/i915: Limit the watermark to at least 8 entries on gen2/3Ville Syrjälä1-0/+11
2014-09-04drm/i915: Reset power sequencer pipe tracking when disp2d is offVille Syrjälä1-0/+2
2014-09-03drm/i915: Rename global latency_ns variableChris Wilson1-18/+18
2014-09-03drm/i915: Disable trickle feed for gen2/3Ville Syrjälä1-0/+10
2014-09-03drm/i915: Fix gen2 planes B and C max watermark valueVille Syrjälä1-4/+20
2014-09-03drm/i915: Init some CHV workarounds via LRIs in ring->init_context()Ville Syrjälä1-14/+0
2014-09-03drm/i915: Warn about odd rps values on CHVVille Syrjälä1-0/+11
2014-09-03drm/i915/bdw: BDW Software TurboDaisy Sun1-39/+191
2014-09-03drm/i915: Populate mem_freq in init_gt_powerwave()Ville Syrjälä1-47/+43
2014-09-03drm/i915/bdw: Apply workarounds in render ring init functionArun Siluvery1-48/+0
2014-09-03drm/i915: FBC flush nuke for BDWRodrigo Vivi1-0/+10
2014-09-03drm/i915: rename gen8_init_clock_gating to broadwell_init_clock_gatingPaulo Zanoni1-2/+2
2014-09-03drm/i915: call lpt_init_clock_gating on BDW tooPaulo Zanoni1-0/+2
2014-09-03drm/i915: Bring UP Power Wells before disabling RC6.Deepak S1-0/+6
2014-09-03drm/i915: Use dev_priv as first argument of for_each_pipe()Damien Lespiau1-9/+8
2014-09-03drm/i915: Add 180 degree primary plane rotation supportSonika Jindal1-0/+6
2014-09-03Merge tag 'drm-intel-next-2014-09-01' of git://anongit.freedesktop.org/drm-in...Dave Airlie1-2/+0
2014-08-26Merge tag 'drm-intel-next-2014-08-08' of git://anongit.freedesktop.org/drm-in...Dave Airlie1-54/+474
2014-08-11drm/i915: Remove set but unused 'gt_perf_status'Damien Lespiau1-2/+0
2014-08-08Merge tag 'drm-intel-fixes-2014-08-08' of git://anongit.freedesktop.org/drm-i...Linus Torvalds1-22/+19
2014-08-08drm/i915: Add sprite watermark programming for VLV and CHVGajanan Bhat1-0/+33
2014-08-08drm/i915: Round-up clock and limit drain latencyGajanan Bhat1-1/+4
2014-08-08drm/i915: Generalize drain latency computationGajanan Bhat1-37/+50
2014-08-08drm/i915: Polish the chv cmnlane resrt macrosVille Syrjälä1-4/+4
2014-08-08drm/i915: Hack to tie both common lanes together on chvVille Syrjälä1-2/+12
2014-08-08drm/i915: Add cherryview_update_wm()Ville Syrjälä1-1/+80
2014-08-08drm/i915: Update DDL only for current CRTCGajanan Bhat1-16/+9
2014-08-08drm/i915: Parametrize VLV_DDL registersVille Syrjälä1-29/+23
2014-08-08drm/i915: Fill out the FWx watermark register definesVille Syrjälä1-4/+7
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